config.yaml

stages:
  - make_assets
  - embed_reveal
  - docusaurus

build_dir: /build
output_type: last
output_dir: /output

make_assets:
  plugin: command
  options:
    command: make
    locations: 
      - chapters/intro/soc/slides
    args:
      - all

embed_reveal:
  plugin: reveal_embed
  options:
    target: docusaurus
    extension: mdx
    build:
      intro: slides/intro

docusaurus:
  plugin: docusaurus
  options:
    course_name: Computer Architecture
    sidebar: js
    math: true
    structure:
      - Introduction: chapters/landing-page/README.md
      - Regulament: chapters/rules/rules.md
      - Notare: chapters/grading/grading.md
      - Echipa: chapters/team/team.md
      - Tutoriale:
          path: chapters/guides
          extra:
            - media/
          subsections:
            - Instalare Vivado/: install/
            - Creare proiect Vivado/: project/
            - Simulare Vivado/: simulation/
            - Programare FPGA Vivado/: programming/
            - Rulare exemple practice/: runtasks/
            - Docker:
                path: docker/
                extra:
                  - media/
                subsections:
                  - Windows/: windows/
                  - Linux/: linux/
                  - MacOS/: macos/
            - VPL/: vpl/ 
      - Laboratoare:
          - 0 Recapitulare:
              - Circuite combinaționale:
                  path: chapters/combinational-circuits/intro
                  extra:
                    - media/
                  subsections:
                    - Teorie/: reading/
              - Porti logice:
                  path: chapters/combinational-circuits/logic-gates
                  extra:
                    - media/
                  subsections:
                    - Teorie/: reading/
              - Sumatoare:
                  path: chapters/combinational-circuits/adders
                  extra:
                    - media/
                  subsections:
                    - Teorie/: reading/
              - Circuite secvențiale:
                  path: chapters/sequential-circuits/intro
                  extra:
                    - media/
                  subsections:
                    - Teorie/: reading/
              - Bistabil D:
                  path: chapters/sequential-circuits/d-flip-flop
                  extra:
                    - media/
                  subsections:
                    - Teorie/: reading/
              - Automate finite:
                  path: chapters/sequential-circuits/fsms
                  extra:
                    - media/
                  subsections:
                    - Teorie/: reading/
          - 1 Verilog Combinațional:
              - Limbaj Verilog:
                  path: chapters/verilog/intro
                  extra:
                    - media/
                  subsections:
                    - Teorie/: reading/
              - Descriere structurala:
                  path: chapters/verilog/basic
                  extra:
                    - media/
                  subsections:
                    - Teorie/: reading/
                    - Practică/: drills/
          - 2 Verilog Combinațional:
              - Operatori:
                  path: chapters/verilog/operators
                  extra:
                    - media/
                  subsections:
                    - Teorie/: reading/
                    - Practică/: drills/
              - Parametri:
                  path: chapters/verilog/parameters
                  subsections:
                    - Teorie/: reading/
                    - Practică/: drills/
              - Testare:
                  path: chapters/verilog/testing
                  extra:
                    - media/
                  subsections:
                    - Teorie/: reading/
                    - Practică/: drills/
          - 3 Verilog Combinațional:
              - Descriere Comportamentala:
                  path: chapters/verilog/behavioral
                  extra:
                    - media/
                  subsections:
                    - Teorie/: reading/
                    - Practică/: drills/
          - 4 Verilog Secvențial:
              - Always-Edge:
                  path: chapters/verilog/always-edge
                  subsections:
                    - Teorie/: reading/
              - Debouncer:
                  path: chapters/verilog/debouncer
                  subsections:
                    - Teorie/: reading/
                    - Practică/: drills/
          - 5 Verilog Secvențial:
              - Automate finite:
                  path: chapters/verilog/fsms
                  extra:
                    - media/
                  subsections:
                    - Teorie/: reading/
              - Memorie:
                  path: chapters/verilog/memory
                  extra:
                    - media/
                  subsections:
                    - Teorie/: reading/
                    - Practică/: drills/
          - 6 Verilog Secvențial:
              - Unitate aritmetica logica:
                  path: chapters/microprogramable_cpu/arithmetic-logic-unit
                  extra:
                    - media/
                  subsections:
                    - Teorie/: reading/
                    - Practică/: drills/
          - 7 Calculator Didactic:
              - Arhitectura:
                  path: chapters/microprogramable_cpu/architecture
                  extra:
                    - media/
                  subsections:
                    - Teorie/: reading/
          - 8 Calculator Didactic:
              - Unitate de comanda:
                  path: chapters/microprogramable_cpu/control-unit
                  extra:
                    - media/
                  subsections:
                    - Teorie/: reading/
          - 9 Calculator Didactic:
              - Moduri de adresare:
                  path: chapters/microprogramable_cpu/addressing-modes
                  extra:
                    - media/
                  subsections:
                    - Teorie/: reading/
      - Curs:
          path: /build/embed_reveal
          subsections:
            - 0 Introducere: intro/intro.mdx
      - Evaluare:
          path: assignments
          subsections:
            - Test Circuite Combinaționale:
                path: combinational
                extra:
                  - led7/media/
                subsections:
                  - True Table/: comb/
                  - 7 LED Segment/: led7/
                  - ALU/: alu/
            - Test Circuite Secvențiale:
                path: sequential
                subsections:
                  - FSM/: fsm/
                  - Operation Register/: opregister/
                  - Flag RAM/: flagram/
            # - Test Calculator Didactic:
            #     path: cpu
            #     subsections:
            #       - 1/: 1/
            #       - 2/: 2/
            #       - 3/: 3/
            - Teme:
                path: projects
                subsections:
                  - FPU/: fpu/
            # - Examen AB:
            #     path: exam
            #     subsections:
            #       - 1/: 1/
      
    static_assets:
      - slides/intro: /build/make_assets/chapters/intro/soc/slides/_site
    config_meta:
      title: Computer Architecture
      url: http://localhost/
      baseUrl: /computer-architecture/
      onBrokenLinks: warn
      onBrokenMarkdownLinks: warn
    config_socials:
      Main site: https://curs.upb.ro
      OCW: https://ocw.cs.pub.ro/courses/ac-is
    copyright_string: Comnputer Architecture Team