From 2e4e29f1b41b948c553535bf0b5daf77e0fa846b Mon Sep 17 00:00:00 2001
From: Brandon Chuang <brandon_chuang@edge-core.com>
Date: Thu, 25 Nov 2021 16:02:53 +0800
Subject: [PATCH] [as4224/as5114/as4564] Update DTS

In order to upgrade the LK release from 5.10.4 to 5.10.7x the addition modification shown below is mandatory.
dma-ranges = <0x42000000 0x0 0x00000000 0x0 0x00000000 0x0 0x40000000>;

The SSD parameter has been adjusted to have better performance in uboot
So the linux kernel does not need to initialize the default value
By this skip phy config then it can leverage the adjusted parameter of uboot.

Signed-off-by: Brandon Chuang <brandon_chuang@edge-core.com>
---
 .../kernels/5.10-lts/patches/0012-accton-as4224.patch | 11 ++++++++---
 .../kernels/5.10-lts/patches/0020-accton-as5114.patch | 11 ++++++++---
 .../5.10-lts/patches/0023-accton-as4564-26p.patch     | 11 ++++++++---
 3 files changed, 24 insertions(+), 9 deletions(-)

diff --git a/packages/base/any/kernels/5.10-lts/patches/0012-accton-as4224.patch b/packages/base/any/kernels/5.10-lts/patches/0012-accton-as4224.patch
index 50d293e43..c518b8acb 100644
--- a/packages/base/any/kernels/5.10-lts/patches/0012-accton-as4224.patch
+++ b/packages/base/any/kernels/5.10-lts/patches/0012-accton-as4224.patch
@@ -1,9 +1,9 @@
 diff --git a/arch/arm64/boot/dts/marvell/accton-as4224.dts b/arch/arm64/boot/dts/marvell/accton-as4224.dts
 new file mode 100644
-index 0000000..ee43c1e
+index 0000000..e9234e1
 --- /dev/null
 +++ b/arch/arm64/boot/dts/marvell/accton-as4224.dts
-@@ -0,0 +1,459 @@
+@@ -0,0 +1,464 @@
 +// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
 +/*
 + * Copyright (C) 2016 Marvell Technology Group Ltd.
@@ -285,6 +285,7 @@ index 0000000..ee43c1e
 +};
 +
 +&cp0_pcie0 {
++	dma-ranges = <0x42000000 0x0 0x00000000 0x0 0x00000000 0x0 0x40000000>;
 +	ranges = <0x81000000 0x0 0xfb000000 0x0 0xfb000000 0x0 0xf0000
 +		0x82000000 0x0 0xf6000000 0x0 0xf6000000 0x0 0x2000000
 +		0x82000000 0x0 0xf9000000 0x0 0xf9000000 0x0 0x100000>;
@@ -393,13 +394,17 @@ index 0000000..ee43c1e
 +	};
 +};
 +
++&cp0_comphy1 {
++   phy-skip-config;
++};
++
 +&cp0_sata0 {
 +	status = "okay";
 +
 +	sata-port@1 {
 +		status = "okay";
 +		/* Generic PHY, providing serdes lanes */
-+		phys = <&cp0_comphy1 0>;
++		//phys = <&cp0_comphy1 0>;
 +	};
 +};
 +
diff --git a/packages/base/any/kernels/5.10-lts/patches/0020-accton-as5114.patch b/packages/base/any/kernels/5.10-lts/patches/0020-accton-as5114.patch
index bc6293e28..acc528ab3 100644
--- a/packages/base/any/kernels/5.10-lts/patches/0020-accton-as5114.patch
+++ b/packages/base/any/kernels/5.10-lts/patches/0020-accton-as5114.patch
@@ -1,9 +1,9 @@
 diff --git a/arch/arm64/boot/dts/marvell/accton-as5114.dts b/arch/arm64/boot/dts/marvell/accton-as5114.dts
 new file mode 100644
-index 0000000..68dc6b3
+index 0000000..8351ec0
 --- /dev/null
 +++ b/arch/arm64/boot/dts/marvell/accton-as5114.dts
-@@ -0,0 +1,1912 @@
+@@ -0,0 +1,1917 @@
 +// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
 +/*
 + * Copyright (C) 2016 Marvell Technology Group Ltd.
@@ -1738,6 +1738,7 @@ index 0000000..68dc6b3
 +};
 +
 +&cp0_pcie0 {
++	dma-ranges = <0x42000000 0x0 0x00000000 0x0 0x00000000 0x0 0x40000000>;
 +	ranges = <0x81000000 0x0 0xfb000000 0x0 0xfb000000 0x0 0xf0000
 +		0x82000000 0x0 0xf6000000 0x0 0xf6000000 0x0 0x2000000
 +		0x82000000 0x0 0xf9000000 0x0 0xf9000000 0x0 0x100000>;
@@ -1846,13 +1847,17 @@ index 0000000..68dc6b3
 +	};
 +};
 +
++&cp0_comphy1 {
++   phy-skip-config;
++};
++
 +&cp0_sata0 {
 +	status = "okay";
 +
 +	sata-port@1 {
 +		status = "okay";
 +		/* Generic PHY, providing serdes lanes */
-+		phys = <&cp0_comphy1 0>;
++		//phys = <&cp0_comphy1 0>;
 +	};
 +};
 +
diff --git a/packages/base/any/kernels/5.10-lts/patches/0023-accton-as4564-26p.patch b/packages/base/any/kernels/5.10-lts/patches/0023-accton-as4564-26p.patch
index f9dfdf26f..dbc17927c 100644
--- a/packages/base/any/kernels/5.10-lts/patches/0023-accton-as4564-26p.patch
+++ b/packages/base/any/kernels/5.10-lts/patches/0023-accton-as4564-26p.patch
@@ -1,9 +1,9 @@
 diff --git a/arch/arm64/boot/dts/marvell/accton-as4564-26p.dts b/arch/arm64/boot/dts/marvell/accton-as4564-26p.dts
 new file mode 100644
-index 000000000..9852aa3b6
+index 0000000..cee3779
 --- /dev/null
 +++ b/arch/arm64/boot/dts/marvell/accton-as4564-26p.dts
-@@ -0,0 +1,394 @@
+@@ -0,0 +1,399 @@
 +// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
 +/*
 + * Copyright (C) 2016 Marvell Technology Group Ltd.
@@ -221,6 +221,7 @@ index 000000000..9852aa3b6
 +};
 +
 +&cp0_pcie0 {
++	dma-ranges = <0x42000000 0x0 0x00000000 0x0 0x00000000 0x0 0x40000000>;
 +	ranges = <0x81000000 0x0 0xfb000000 0x0 0xfb000000 0x0 0xf0000
 +		0x82000000 0x0 0xf6000000 0x0 0xf6000000 0x0 0x2000000
 +		0x82000000 0x0 0xf9000000 0x0 0xf9000000 0x0 0x100000>;
@@ -328,13 +329,17 @@ index 000000000..9852aa3b6
 +	};
 +};
 +
++&cp0_comphy1 {
++   phy-skip-config;
++};
++
 +&cp0_sata0 {
 +	status = "okay";
 +
 +	sata-port@1 {
 +		status = "okay";
 +		/* Generic PHY, providing serdes lanes */
-+		phys = <&cp0_comphy1 0>;
++		//phys = <&cp0_comphy1 0>;
 +	};
 +};
 +