TestBenchMultiplier.vhdtst

-- Testbench for multilier

Library IEEE;
Use IEEE.std_logic_1164.all;
Use IEEE.std_logic_textio.all;
Use STD.textio.all;
USE ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
USE ieee.numeric_std.ALL;

entity TestBenchMultiplier is

end TestBenchMultiplier;

architecture stimulus of TestBenchMultiplier is

component generic_multiplier
          GENERIC(
               WIDTH : integer := 16
          );
          port(
               multiplicant : IN     std_logic_vector (WIDTH-1 DOWNTO 0);
               multiplier   : IN     std_logic_vector (WIDTH-1 DOWNTO 0);
               product      : OUT    std_logic_vector (WIDTH+WIDTH-1 DOWNTO 0);
               twocomp      : IN     std_logic
          );
end component;

signal multiplicant : std_logic_vector(15 downto 0);
signal multiplier : std_logic_vector(15 downto 0);
signal product : std_logic_vector(31 downto 0);
signal twocomp : std_logic;

begin
     -- DUT is Device Under Test
     DUT:generic_multiplier  generic map(WIDTH => 16) port map(
         multiplicant => multiplicant,
         multiplier => multiplier,
         product => product,
         twocomp => twocomp
     );

     STIMULUS0:process
     begin
          -- insert stimulus here
          multiplicant <= (others => '0');
          multiplier <= (others => '0');
          twocomp <= '0';
          wait for 2 ns;

          multiplicant <= conv_std_logic_vector(2, 16);
          multiplier <= conv_std_logic_vector(8, 16);
          twocomp <= '0';
          wait for 2 ns;

          -- Negative test (signed)
          multiplicant <= conv_std_logic_vector(-2, 16);
          multiplier <= conv_std_logic_vector(8, 16);
          twocomp <= '1';
          wait for 2 ns;

          -- Negative test (signed)
          multiplicant <= conv_std_logic_vector(-2, 16);
          multiplier <= conv_std_logic_vector(-8, 16);
          twocomp <= '1';
          wait for 2 ns;
     end process;

end architecture;