TestBenchRams.vhdtst

-- Tester of RAM Module

Library IEEE;
Use IEEE.std_logic_1164.all;
Use IEEE.std_logic_textio.all;
Use STD.textio.all;
USE ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
USE ieee.numeric_std.ALL;

entity TestBenchRams is

end TestBenchRams;

architecture stimulus of TestBenchRams is

component rams
          GENERIC(
               WIDTH : integer := 16;
               SIZE          : integer := 16;
               BITS_ADDRESS  : integer := 4
          );
          Port (
              WR      : in std_logic;
              CLK     : in std_logic;
              Datain  : in std_logic_vector(WIDTH-1 downto 0);
              Dataout : out std_logic_vector(WIDTH-1 downto 0);
              Addr    : in std_logic_vector(3 downto 0)
              );
end component;

constant period_clk : time := 10 ns;

signal Datain : std_logic_vector(15 downto 0);
signal Dataout : std_logic_vector(15 downto 0);
signal Addr : std_logic_vector(3 downto 0);
signal WR : std_logic;
signal CLK : std_logic;


begin
     -- DUT is Device Under Test
     DUT:rams  generic map(WIDTH => 16, SIZE => 16, BITS_ADDRESS => 4) port map(
         WR => WR,
         CLK => CLK,
         Datain  => Datain,
         Dataout => Dataout,
         Addr => Addr
     );

     CLK_process :process
      begin
           CLK <= '0';
           wait for period_clk / 2;
           CLK <= '1';
           wait for period_clk / 2;
      end process;

     STIMULUS0:process
     begin
          -- insert stimulus here
          WR <= '1';
          Addr <= conv_std_logic_vector(0, 4);
          Datain <= conv_std_logic_vector(1, 16);
          wait for period_clk;

          WR <= '1';
          Addr <= conv_std_logic_vector(1, 4);
          Datain <= conv_std_logic_vector(2, 16);
          wait for period_clk;

          WR <= '1';
          Addr <= conv_std_logic_vector(2, 4);
          Datain <= conv_std_logic_vector(3, 16);
          wait for period_clk;

          WR <= '0';
          Addr <= conv_std_logic_vector(0, 4);
          wait for period_clk;

          WR <= '0';
          Addr <= conv_std_logic_vector(1, 4);
          wait for period_clk;

          WR <= '0';
          Addr <= conv_std_logic_vector(2, 4);
          wait for period_clk;

     end process;

end architecture;