diff --git a/EF_GPIO8.yaml b/EF_GPIO8.yaml index b5fc056..4510dd4 100644 --- a/EF_GPIO8.yaml +++ b/EF_GPIO8.yaml @@ -32,6 +32,8 @@ info: - WB: 588 digital_supply_voltage: n/a analog_supply_voltage: n/a + irq_reg_offset: 0xFF00 + fifo_reg_offset: 0xFE00 ports: - name: bus_in diff --git a/README.md b/README.md index ea55ad2..d6c1a83 100644 --- a/README.md +++ b/README.md @@ -46,10 +46,10 @@ The following table is the result for implementing the EF_GPIO8 IP with differen |DATAI|0000|0x00000000|r|Data In Register; Reading from this register returns the pins status (8 pins); one bit per pin| |DATAO|0004|0x00000000|w|Data Out Register; Writing to this register change the status of the port pins (8 pins); one bit per pin| |DIR|0008|0x00000000|w|Direction Register; One bit per pin 1: output, 0: input| -|IM|0f00|0x00000000|w|Interrupt Mask Register; write 1/0 to enable/disable interrupts; check the interrupt flags table for more details| -|RIS|0f08|0x00000000|w|Raw Interrupt Status; reflects the current interrupts status;check the interrupt flags table for more details| -|MIS|0f04|0x00000000|w|Masked Interrupt Status; On a read, this register gives the current masked status value of the corresponding interrupt. A write has no effect; check the interrupt flags table for more details| -|IC|0f0c|0x00000000|w|Interrupt Clear Register; On a write of 1, the corresponding interrupt (both raw interrupt and masked interrupt, if enabled) is cleared; check the interrupt flags table for more details| +|IM|ff00|0x00000000|w|Interrupt Mask Register; write 1/0 to enable/disable interrupts; check the interrupt flags table for more details| +|RIS|ff08|0x00000000|w|Raw Interrupt Status; reflects the current interrupts status;check the interrupt flags table for more details| +|MIS|ff04|0x00000000|w|Masked Interrupt Status; On a read, this register gives the current masked status value of the corresponding interrupt. A write has no effect; check the interrupt flags table for more details| +|IC|ff0c|0x00000000|w|Interrupt Clear Register; On a write of 1, the corresponding interrupt (both raw interrupt and masked interrupt, if enabled) is cleared; check the interrupt flags table for more details| ### DATAI Register [Offset: 0x0, mode: r] diff --git a/hdl/rtl/bus_wrappers/EF_GPIO8_AHBL.pp.v b/hdl/rtl/bus_wrappers/EF_GPIO8_AHBL.pp.v index 250fa14..cc13237 100644 --- a/hdl/rtl/bus_wrappers/EF_GPIO8_AHBL.pp.v +++ b/hdl/rtl/bus_wrappers/EF_GPIO8_AHBL.pp.v @@ -1,7 +1,7 @@ /* - Copyright 2023 Efabless Corp. + Copyright 2024 Efabless Corp. - Author: Mohamed Shalan (mshalan@aucegypt.edu) + Author: Mohamed Shalan (mshalan@efabless.com) Licensed under the Apache License, Version 2.0 (the "License"); you may not use this file except in compliance with the License. @@ -22,7 +22,6 @@ `timescale 1ns/1ps `default_nettype none - module EF_GPIO8_AHBL ( input wire HCLK, input wire HRESETn, @@ -36,26 +35,30 @@ module EF_GPIO8_AHBL ( output wire [31:0] HRDATA, output wire IRQ , - input [7:0] io_in, - output [7:0] io_out, - output [7:0] io_oe + input [8-1:0] io_in, + output [8-1:0] io_out, + output [8-1:0] io_oe ); - localparam DATAI_REG_OFFSET = 16'd0; - localparam DATAO_REG_OFFSET = 16'd4; - localparam DIR_REG_OFFSET = 16'd8; - localparam IM_REG_OFFSET = 16'd3840; - localparam MIS_REG_OFFSET = 16'd3844; - localparam RIS_REG_OFFSET = 16'd3848; - localparam IC_REG_OFFSET = 16'd3852; - + localparam DATAI_REG_OFFSET = 16'h0000; + localparam DATAO_REG_OFFSET = 16'h0004; + localparam DIR_REG_OFFSET = 16'h0008; + localparam IM_REG_OFFSET = 16'hFF00; + localparam MIS_REG_OFFSET = 16'hFF04; + localparam RIS_REG_OFFSET = 16'hFF08; + localparam IC_REG_OFFSET = 16'hFF0C; wire clk = HCLK; wire rst_n = HRESETn; reg last_HSEL, last_HWRITE; reg [31:0] last_HADDR; reg [1:0] last_HTRANS; - always@ (posedge HCLK) begin - if(HREADY) begin + always@ (posedge HCLK or negedge HRESETn) begin + if(~HRESETn) begin + last_HSEL <= 1'b0; + last_HADDR <= 1'b0; + last_HWRITE <= 1'b0; + last_HTRANS <= 1'b0; + end else if(HREADY) begin last_HSEL <= HSEL; last_HADDR <= HADDR; last_HWRITE <= HWRITE; @@ -102,17 +105,17 @@ module EF_GPIO8_AHBL ( wire [1-1:0] pin6_ne; wire [1-1:0] pin7_ne; - + // Register Definitions wire [8-1:0] DATAI_WIRE; assign DATAI_WIRE = bus_in; - reg [8-1:0] DATAO_REG; + reg [7:0] DATAO_REG; assign bus_out = DATAO_REG; always @(posedge HCLK or negedge HRESETn) if(~HRESETn) DATAO_REG <= 0; else if(ahbl_we & (last_HADDR[16-1:0]==DATAO_REG_OFFSET)) DATAO_REG <= HWDATA[8-1:0]; - reg [8-1:0] DIR_REG; + reg [7:0] DIR_REG; assign bus_oe = DIR_REG; always @(posedge HCLK or negedge HRESETn) if(~HRESETn) DIR_REG <= 0; else if(ahbl_we & (last_HADDR[16-1:0]==DIR_REG_OFFSET)) diff --git a/hdl/rtl/bus_wrappers/EF_GPIO8_AHBL.v b/hdl/rtl/bus_wrappers/EF_GPIO8_AHBL.v index a434ff9..72d8657 100644 --- a/hdl/rtl/bus_wrappers/EF_GPIO8_AHBL.v +++ b/hdl/rtl/bus_wrappers/EF_GPIO8_AHBL.v @@ -1,7 +1,7 @@ /* - Copyright 2023 Efabless Corp. + Copyright 2024 Efabless Corp. - Author: Mohamed Shalan (mshalan@aucegypt.edu) + Author: Mohamed Shalan (mshalan@efabless.com) Licensed under the Apache License, Version 2.0 (the "License"); you may not use this file except in compliance with the License. @@ -22,25 +22,24 @@ `timescale 1ns/1ps `default_nettype none -`define AHBL_AW 16 +`define AHBL_AW 16 `include "ahbl_wrapper.vh" module EF_GPIO8_AHBL ( `AHBL_SLAVE_PORTS, - input [7:0] io_in, - output [7:0] io_out, - output [7:0] io_oe + input [8-1:0] io_in, + output [8-1:0] io_out, + output [8-1:0] io_oe ); - localparam DATAI_REG_OFFSET = `AHBL_AW'd0; - localparam DATAO_REG_OFFSET = `AHBL_AW'd4; - localparam DIR_REG_OFFSET = `AHBL_AW'd8; - localparam IM_REG_OFFSET = `AHBL_AW'd3840; - localparam MIS_REG_OFFSET = `AHBL_AW'd3844; - localparam RIS_REG_OFFSET = `AHBL_AW'd3848; - localparam IC_REG_OFFSET = `AHBL_AW'd3852; - + localparam DATAI_REG_OFFSET = `AHBL_AW'h0000; + localparam DATAO_REG_OFFSET = `AHBL_AW'h0004; + localparam DIR_REG_OFFSET = `AHBL_AW'h0008; + localparam IM_REG_OFFSET = `AHBL_AW'hFF00; + localparam MIS_REG_OFFSET = `AHBL_AW'hFF04; + localparam RIS_REG_OFFSET = `AHBL_AW'hFF08; + localparam IC_REG_OFFSET = `AHBL_AW'hFF0C; wire clk = HCLK; wire rst_n = HRESETn; @@ -83,15 +82,15 @@ module EF_GPIO8_AHBL ( wire [1-1:0] pin6_ne; wire [1-1:0] pin7_ne; - + // Register Definitions wire [8-1:0] DATAI_WIRE; assign DATAI_WIRE = bus_in; - reg [8-1:0] DATAO_REG; + reg [7:0] DATAO_REG; assign bus_out = DATAO_REG; `AHBL_REG(DATAO_REG, 0, 8) - reg [8-1:0] DIR_REG; + reg [7:0] DIR_REG; assign bus_oe = DIR_REG; `AHBL_REG(DIR_REG, 0, 8) diff --git a/hdl/rtl/bus_wrappers/EF_GPIO8_APB.pp.v b/hdl/rtl/bus_wrappers/EF_GPIO8_APB.pp.v index 3dca753..06b555d 100644 --- a/hdl/rtl/bus_wrappers/EF_GPIO8_APB.pp.v +++ b/hdl/rtl/bus_wrappers/EF_GPIO8_APB.pp.v @@ -1,7 +1,7 @@ /* - Copyright 2023 Efabless Corp. + Copyright 2024 Efabless Corp. - Author: Mohamed Shalan (mshalan@aucegypt.edu) + Author: Mohamed Shalan (mshalan@efabless.com) Licensed under the Apache License, Version 2.0 (the "License"); you may not use this file except in compliance with the License. @@ -21,54 +21,6 @@ `timescale 1ns/1ps `default_nettype none - - - -/* - Copyright 2020 AUCOHL - - Author: Mohamed Shalan (mshalan@aucegypt.edu) - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at: - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - - - - - - - - - - - - - - - - - - - - - - - - - - - - module EF_GPIO8_APB ( @@ -83,19 +35,18 @@ module EF_GPIO8_APB ( output wire [31:0] PRDATA, output wire IRQ , - input [7:0] io_in, - output [7:0] io_out, - output [7:0] io_oe + input [8-1:0] io_in, + output [8-1:0] io_out, + output [8-1:0] io_oe ); - localparam DATAI_REG_OFFSET = 16'd0; - localparam DATAO_REG_OFFSET = 16'd4; - localparam DIR_REG_OFFSET = 16'd8; - localparam IM_REG_OFFSET = 16'd3840; - localparam MIS_REG_OFFSET = 16'd3844; - localparam RIS_REG_OFFSET = 16'd3848; - localparam IC_REG_OFFSET = 16'd3852; - + localparam DATAI_REG_OFFSET = 16'h0000; + localparam DATAO_REG_OFFSET = 16'h0004; + localparam DIR_REG_OFFSET = 16'h0008; + localparam IM_REG_OFFSET = 16'hFF00; + localparam MIS_REG_OFFSET = 16'hFF04; + localparam RIS_REG_OFFSET = 16'hFF08; + localparam IC_REG_OFFSET = 16'hFF0C; wire clk = PCLK; wire rst_n = PRESETn; @@ -140,17 +91,17 @@ module EF_GPIO8_APB ( wire [1-1:0] pin6_ne; wire [1-1:0] pin7_ne; - + // Register Definitions wire [8-1:0] DATAI_WIRE; assign DATAI_WIRE = bus_in; - reg [8-1:0] DATAO_REG; + reg [7:0] DATAO_REG; assign bus_out = DATAO_REG; always @(posedge PCLK or negedge PRESETn) if(~PRESETn) DATAO_REG <= 0; else if(apb_we & (PADDR[16-1:0]==DATAO_REG_OFFSET)) DATAO_REG <= PWDATA[8-1:0]; - reg [8-1:0] DIR_REG; + reg [7:0] DIR_REG; assign bus_oe = DIR_REG; always @(posedge PCLK or negedge PRESETn) if(~PRESETn) DIR_REG <= 0; else if(apb_we & (PADDR[16-1:0]==DIR_REG_OFFSET)) @@ -359,6 +310,6 @@ module EF_GPIO8_APB ( (PADDR[16-1:0] == IC_REG_OFFSET) ? IC_REG : 32'hDEADBEEF; - assign PREADY = 1'b1; + assign PREADY = 1'b1; endmodule diff --git a/hdl/rtl/bus_wrappers/EF_GPIO8_APB.v b/hdl/rtl/bus_wrappers/EF_GPIO8_APB.v index 82ca7bd..b5a07fb 100644 --- a/hdl/rtl/bus_wrappers/EF_GPIO8_APB.v +++ b/hdl/rtl/bus_wrappers/EF_GPIO8_APB.v @@ -1,7 +1,7 @@ /* - Copyright 2023 Efabless Corp. + Copyright 2024 Efabless Corp. - Author: Mohamed Shalan (mshalan@aucegypt.edu) + Author: Mohamed Shalan (mshalan@efabless.com) Licensed under the Apache License, Version 2.0 (the "License"); you may not use this file except in compliance with the License. @@ -22,25 +22,24 @@ `timescale 1ns/1ps `default_nettype none -`define APB_AW 16 +`define APB_AW 16 `include "apb_wrapper.vh" module EF_GPIO8_APB ( `APB_SLAVE_PORTS, - input [7:0] io_in, - output [7:0] io_out, - output [7:0] io_oe + input [8-1:0] io_in, + output [8-1:0] io_out, + output [8-1:0] io_oe ); - localparam DATAI_REG_OFFSET = `APB_AW'd0; - localparam DATAO_REG_OFFSET = `APB_AW'd4; - localparam DIR_REG_OFFSET = `APB_AW'd8; - localparam IM_REG_OFFSET = `APB_AW'd3840; - localparam MIS_REG_OFFSET = `APB_AW'd3844; - localparam RIS_REG_OFFSET = `APB_AW'd3848; - localparam IC_REG_OFFSET = `APB_AW'd3852; - + localparam DATAI_REG_OFFSET = `APB_AW'h0000; + localparam DATAO_REG_OFFSET = `APB_AW'h0004; + localparam DIR_REG_OFFSET = `APB_AW'h0008; + localparam IM_REG_OFFSET = `APB_AW'hFF00; + localparam MIS_REG_OFFSET = `APB_AW'hFF04; + localparam RIS_REG_OFFSET = `APB_AW'hFF08; + localparam IC_REG_OFFSET = `APB_AW'hFF0C; wire clk = PCLK; wire rst_n = PRESETn; @@ -83,15 +82,15 @@ module EF_GPIO8_APB ( wire [1-1:0] pin6_ne; wire [1-1:0] pin7_ne; - + // Register Definitions wire [8-1:0] DATAI_WIRE; assign DATAI_WIRE = bus_in; - reg [8-1:0] DATAO_REG; + reg [7:0] DATAO_REG; assign bus_out = DATAO_REG; `APB_REG(DATAO_REG, 0, 8) - reg [8-1:0] DIR_REG; + reg [7:0] DIR_REG; assign bus_oe = DIR_REG; `APB_REG(DIR_REG, 0, 8) @@ -292,6 +291,6 @@ module EF_GPIO8_APB ( (PADDR[`APB_AW-1:0] == IC_REG_OFFSET) ? IC_REG : 32'hDEADBEEF; - assign PREADY = 1'b1; + assign PREADY = 1'b1; endmodule diff --git a/hdl/rtl/bus_wrappers/EF_GPIO8_WB.pp.v b/hdl/rtl/bus_wrappers/EF_GPIO8_WB.pp.v index 1990906..29fd755 100644 --- a/hdl/rtl/bus_wrappers/EF_GPIO8_WB.pp.v +++ b/hdl/rtl/bus_wrappers/EF_GPIO8_WB.pp.v @@ -1,5 +1,5 @@ /* - Copyright 2023 Efabless Corp. + Copyright 2024 Efabless Corp. Author: Mohamed Shalan (mshalan@efabless.com) @@ -22,7 +22,6 @@ `timescale 1ns/1ps `default_nettype none - module EF_GPIO8_WB ( input wire ext_clk, input wire clk_i, @@ -36,19 +35,18 @@ module EF_GPIO8_WB ( output reg ack_o, input wire we_i, output wire IRQ, - input [7:0] io_in, - output [7:0] io_out, - output [7:0] io_oe + input [8-1:0] io_in, + output [8-1:0] io_out, + output [8-1:0] io_oe ); - localparam DATAI_REG_OFFSET = 16'd0; - localparam DATAO_REG_OFFSET = 16'd4; - localparam DIR_REG_OFFSET = 16'd8; - localparam IM_REG_OFFSET = 16'd3840; - localparam MIS_REG_OFFSET = 16'd3844; - localparam RIS_REG_OFFSET = 16'd3848; - localparam IC_REG_OFFSET = 16'd3852; - + localparam DATAI_REG_OFFSET = 16'h0000; + localparam DATAO_REG_OFFSET = 16'h0004; + localparam DIR_REG_OFFSET = 16'h0008; + localparam IM_REG_OFFSET = 16'hFF00; + localparam MIS_REG_OFFSET = 16'hFF04; + localparam RIS_REG_OFFSET = 16'hFF08; + localparam IC_REG_OFFSET = 16'hFF0C; wire clk = clk_i; wire rst_n = (~rst_i); @@ -94,14 +92,15 @@ module EF_GPIO8_WB ( wire [1-1:0] pin6_ne; wire [1-1:0] pin7_ne; + // Register Definitions wire [8-1:0] DATAI_WIRE; assign DATAI_WIRE = bus_in; - reg [8-1:0] DATAO_REG; + reg [7:0] DATAO_REG; assign bus_out = DATAO_REG; always @(posedge clk_i or posedge rst_i) if(rst_i) DATAO_REG <= 0; else if(wb_we & (adr_i[16-1:0]==DATAO_REG_OFFSET)) DATAO_REG <= dat_i[8-1:0]; - reg [8-1:0] DIR_REG; + reg [7:0] DIR_REG; assign bus_oe = DIR_REG; always @(posedge clk_i or posedge rst_i) if(rst_i) DIR_REG <= 0; else if(wb_we & (adr_i[16-1:0]==DIR_REG_OFFSET)) DIR_REG <= dat_i[8-1:0]; diff --git a/hdl/rtl/bus_wrappers/EF_GPIO8_WB.v b/hdl/rtl/bus_wrappers/EF_GPIO8_WB.v index 9913a3b..d6c14c9 100644 --- a/hdl/rtl/bus_wrappers/EF_GPIO8_WB.v +++ b/hdl/rtl/bus_wrappers/EF_GPIO8_WB.v @@ -1,5 +1,5 @@ /* - Copyright 2023 Efabless Corp. + Copyright 2024 Efabless Corp. Author: Mohamed Shalan (mshalan@efabless.com) @@ -28,19 +28,18 @@ module EF_GPIO8_WB ( `WB_SLAVE_PORTS, - input [7:0] io_in, - output [7:0] io_out, - output [7:0] io_oe + input [8-1:0] io_in, + output [8-1:0] io_out, + output [8-1:0] io_oe ); - localparam DATAI_REG_OFFSET = `WB_AW'd0; - localparam DATAO_REG_OFFSET = `WB_AW'd4; - localparam DIR_REG_OFFSET = `WB_AW'd8; - localparam IM_REG_OFFSET = `WB_AW'd3840; - localparam MIS_REG_OFFSET = `WB_AW'd3844; - localparam RIS_REG_OFFSET = `WB_AW'd3848; - localparam IC_REG_OFFSET = `WB_AW'd3852; - + localparam DATAI_REG_OFFSET = `WB_AW'h0000; + localparam DATAO_REG_OFFSET = `WB_AW'h0004; + localparam DIR_REG_OFFSET = `WB_AW'h0008; + localparam IM_REG_OFFSET = `WB_AW'hFF00; + localparam MIS_REG_OFFSET = `WB_AW'hFF04; + localparam RIS_REG_OFFSET = `WB_AW'hFF08; + localparam IC_REG_OFFSET = `WB_AW'hFF0C; wire clk = clk_i; wire rst_n = (~rst_i); @@ -83,14 +82,15 @@ module EF_GPIO8_WB ( wire [1-1:0] pin6_ne; wire [1-1:0] pin7_ne; + // Register Definitions wire [8-1:0] DATAI_WIRE; assign DATAI_WIRE = bus_in; - reg [8-1:0] DATAO_REG; + reg [7:0] DATAO_REG; assign bus_out = DATAO_REG; `WB_REG(DATAO_REG, 0, 8) - reg [8-1:0] DIR_REG; + reg [7:0] DIR_REG; assign bus_oe = DIR_REG; `WB_REG(DIR_REG, 0, 8)