change name of clocking instantiation to avoid SV keyword

[mattvenn]

caravel-lite/verilog/rtl/mgmt_core.v

Line 179 in 793bf63

caravel_clocking clocking(

some designs we are testing use subsets of system verilog. These are supported in iverilog with the -g2012 option for example.
This then breaks in the caravel context because clocking is an SV keyword.