diff --git a/verilog/rtl/simple_por.v b/verilog/rtl/simple_por.v
index 0129f4c7..d5a8a9d3 100644
--- a/verilog/rtl/simple_por.v
+++ b/verilog/rtl/simple_por.v
@@ -28,7 +28,7 @@ module simple_por(
     output por_l
 );
 
-    wire mid, porb_h;
+    wire mid;
     reg inode;
 
     // This is a behavioral model!  Actual circuit is a resitor dumping