diff --git a/signoff/RAM128/standalone_pvr/eco-RAM128.lvs.json b/signoff/RAM128/standalone_pvr/eco-RAM128.lvs.json
new file mode 100644
index 0000000..a755648
--- /dev/null
+++ b/signoff/RAM128/standalone_pvr/eco-RAM128.lvs.json
@@ -0,0 +1,1252 @@
+[
+ {
+ "pins": [
+ [
+ "1",
+ "2",
+ "3",
+ "4"
+ ], [
+ "1",
+ "2",
+ "3",
+ "4"
+ ]
+ ]
+ },
+ {
+ "pins": [
+ [
+ "1",
+ "2",
+ "3",
+ "4"
+ ], [
+ "1",
+ "2",
+ "3",
+ "4"
+ ]
+ ]
+ },
+ {
+ "name": [
+ "sky130_fd_sc_hd__dlclkp_1",
+ "sky130_fd_sc_hd__dlclkp_1"
+ ],
+ "devices": [
+ [
+ ["sky130_fd_pr__pfet_01v8_hvt", 10],
+ ["sky130_fd_pr__nfet_01v8", 10 ]
+ ], [
+ ["sky130_fd_pr__pfet_01v8_hvt", 10 ],
+ ["sky130_fd_pr__nfet_01v8", 10 ]
+ ]
+ ],
+ "nets": [
+ 17,
+ 17
+ ],
+ "badnets": [
+ ],
+ "badelements": [
+ ],
+ "pins": [
+ [
+ "VGND",
+ "CLK",
+ "VPB",
+ "VNB",
+ "VPWR",
+ "GCLK",
+ "GATE"
+ ], [
+ "VGND",
+ "CLK",
+ "VPB",
+ "VNB",
+ "VPWR",
+ "GCLK",
+ "GATE"
+ ]
+ ]
+ },
+ {
+ "name": [
+ "sky130_fd_sc_hd__ebufn_2",
+ "sky130_fd_sc_hd__ebufn_2"
+ ],
+ "devices": [
+ [
+ ["sky130_fd_pr__pfet_01v8_hvt", 4],
+ ["sky130_fd_pr__nfet_01v8", 4 ]
+ ], [
+ ["sky130_fd_pr__pfet_01v8_hvt", 4 ],
+ ["sky130_fd_pr__nfet_01v8", 4 ]
+ ]
+ ],
+ "nets": [
+ 11,
+ 11
+ ],
+ "badnets": [
+ ],
+ "badelements": [
+ ],
+ "pins": [
+ [
+ "VGND",
+ "TE_B",
+ "VPWR",
+ "VNB",
+ "VPB",
+ "Z",
+ "A"
+ ], [
+ "VGND",
+ "TE_B",
+ "VPWR",
+ "VNB",
+ "VPB",
+ "Z",
+ "A"
+ ]
+ ]
+ },
+ {
+ "name": [
+ "sky130_fd_sc_hd__clkbuf_4",
+ "sky130_fd_sc_hd__clkbuf_4"
+ ],
+ "devices": [
+ [
+ ["sky130_fd_pr__pfet_01v8_hvt", 2],
+ ["sky130_fd_pr__nfet_01v8", 2 ]
+ ], [
+ ["sky130_fd_pr__pfet_01v8_hvt", 2 ],
+ ["sky130_fd_pr__nfet_01v8", 2 ]
+ ]
+ ],
+ "nets": [
+ 7,
+ 7
+ ],
+ "badnets": [
+ ],
+ "badelements": [
+ ],
+ "pins": [
+ [
+ "VPWR",
+ "X",
+ "VPB",
+ "A",
+ "VGND",
+ "VNB"
+ ], [
+ "VPWR",
+ "X",
+ "VPB",
+ "A",
+ "VGND",
+ "VNB"
+ ]
+ ]
+ },
+ {
+ "name": [
+ "sky130_fd_sc_hd__dlxtp_1",
+ "sky130_fd_sc_hd__dlxtp_1"
+ ],
+ "devices": [
+ [
+ ["sky130_fd_pr__nfet_01v8", 9],
+ ["sky130_fd_pr__pfet_01v8_hvt", 9 ]
+ ], [
+ ["sky130_fd_pr__nfet_01v8", 9 ],
+ ["sky130_fd_pr__pfet_01v8_hvt", 9 ]
+ ]
+ ],
+ "nets": [
+ 16,
+ 16
+ ],
+ "badnets": [
+ ],
+ "badelements": [
+ ],
+ "pins": [
+ [
+ "VPWR",
+ "VGND",
+ "VPB",
+ "VNB",
+ "D",
+ "Q",
+ "GATE"
+ ], [
+ "VPWR",
+ "VGND",
+ "VPB",
+ "VNB",
+ "D",
+ "Q",
+ "GATE"
+ ]
+ ]
+ },
+ {
+ "name": [
+ "sky130_fd_sc_hd__and4bb_2",
+ "sky130_fd_sc_hd__and4bb_2"
+ ],
+ "devices": [
+ [
+ ["sky130_fd_pr__pfet_01v8_hvt", 7],
+ ["sky130_fd_pr__nfet_01v8", 7 ]
+ ], [
+ ["sky130_fd_pr__pfet_01v8_hvt", 7 ],
+ ["sky130_fd_pr__nfet_01v8", 7 ]
+ ]
+ ],
+ "nets": [
+ 15,
+ 15
+ ],
+ "badnets": [
+ ],
+ "badelements": [
+ ],
+ "pins": [
+ [
+ "VGND",
+ "X",
+ "D",
+ "C",
+ "B_N",
+ "A_N",
+ "VNB",
+ "VPWR",
+ "VPB"
+ ], [
+ "VGND",
+ "X",
+ "D",
+ "C",
+ "B_N",
+ "A_N",
+ "VNB",
+ "VPWR",
+ "VPB"
+ ]
+ ]
+ },
+ {
+ "name": [
+ "sky130_fd_sc_hd__dfxtp_1",
+ "sky130_fd_sc_hd__dfxtp_1"
+ ],
+ "devices": [
+ [
+ ["sky130_fd_pr__nfet_01v8", 12],
+ ["sky130_fd_pr__pfet_01v8_hvt", 12 ]
+ ], [
+ ["sky130_fd_pr__nfet_01v8", 12 ],
+ ["sky130_fd_pr__pfet_01v8_hvt", 12 ]
+ ]
+ ],
+ "nets": [
+ 18,
+ 18
+ ],
+ "badnets": [
+ ],
+ "badelements": [
+ ],
+ "pins": [
+ [
+ "VPB",
+ "VNB",
+ "VGND",
+ "VPWR",
+ "D",
+ "Q",
+ "CLK"
+ ], [
+ "VPB",
+ "VNB",
+ "VGND",
+ "VPWR",
+ "D",
+ "Q",
+ "CLK"
+ ]
+ ]
+ },
+ {
+ "name": [
+ "sky130_fd_sc_hd__inv_1",
+ "sky130_fd_sc_hd__inv_1"
+ ],
+ "devices": [
+ [
+ ["sky130_fd_pr__nfet_01v8", 1],
+ ["sky130_fd_pr__pfet_01v8_hvt", 1 ]
+ ], [
+ ["sky130_fd_pr__nfet_01v8", 1 ],
+ ["sky130_fd_pr__pfet_01v8_hvt", 1 ]
+ ]
+ ],
+ "nets": [
+ 6,
+ 6
+ ],
+ "badnets": [
+ ],
+ "badelements": [
+ ],
+ "pins": [
+ [
+ "VGND",
+ "VNB",
+ "VPWR",
+ "VPB",
+ "A",
+ "Y"
+ ], [
+ "VGND",
+ "VNB",
+ "VPWR",
+ "VPB",
+ "A",
+ "Y"
+ ]
+ ]
+ },
+ {
+ "name": [
+ "sky130_fd_sc_hd__and2_1",
+ "sky130_fd_sc_hd__and2_1"
+ ],
+ "devices": [
+ [
+ ["sky130_fd_pr__pfet_01v8_hvt", 3],
+ ["sky130_fd_pr__nfet_01v8", 3 ]
+ ], [
+ ["sky130_fd_pr__pfet_01v8_hvt", 3 ],
+ ["sky130_fd_pr__nfet_01v8", 3 ]
+ ]
+ ],
+ "nets": [
+ 9,
+ 9
+ ],
+ "badnets": [
+ ],
+ "badelements": [
+ ],
+ "pins": [
+ [
+ "VGND",
+ "X",
+ "A",
+ "B",
+ "VNB",
+ "VPWR",
+ "VPB"
+ ], [
+ "VGND",
+ "X",
+ "A",
+ "B",
+ "VNB",
+ "VPWR",
+ "VPB"
+ ]
+ ]
+ },
+ {
+ "name": [
+ "sky130_fd_sc_hd__diode_2",
+ "sky130_fd_sc_hd__diode_2"
+ ],
+ "devices": [
+ [
+ ["sky130_fd_pr__diode_pw2nd_05v5", 1 ]
+ ], [
+ ["sky130_fd_pr__diode_pw2nd_05v5", 1 ]
+ ]
+ ],
+ "nets": [
+ 2,
+ 2
+ ],
+ "badnets": [
+ ],
+ "badelements": [
+ ],
+ "pins": [
+ [
+ "VNB",
+ "DIODE",
+ "VPB",
+ "VGND",
+ "VPWR"
+ ], [
+ "VNB",
+ "DIODE",
+ "VPB",
+ "VGND",
+ "VPWR"
+ ]
+ ]
+ },
+ {
+ "name": [
+ "sky130_fd_sc_hd__decap_8",
+ "sky130_fd_sc_hd__decap_8"
+ ],
+ "devices": [
+ [
+ ["sky130_fd_pr__pfet_01v8_hvt", 1],
+ ["sky130_fd_pr__nfet_01v8", 1 ]
+ ], [
+ ["sky130_fd_pr__pfet_01v8_hvt", 1 ],
+ ["sky130_fd_pr__nfet_01v8", 1 ]
+ ]
+ ],
+ "nets": [
+ 4,
+ 4
+ ],
+ "badnets": [
+ ],
+ "badelements": [
+ ],
+ "pins": [
+ [
+ "VPB",
+ "VNB",
+ "VPWR",
+ "VGND"
+ ], [
+ "VPB",
+ "VNB",
+ "VPWR",
+ "VGND"
+ ]
+ ]
+ },
+ {
+ "name": [
+ "sky130_fd_sc_hd__decap_12",
+ "sky130_fd_sc_hd__decap_12"
+ ],
+ "devices": [
+ [
+ ["sky130_fd_pr__pfet_01v8_hvt", 1],
+ ["sky130_fd_pr__nfet_01v8", 1 ]
+ ], [
+ ["sky130_fd_pr__pfet_01v8_hvt", 1 ],
+ ["sky130_fd_pr__nfet_01v8", 1 ]
+ ]
+ ],
+ "nets": [
+ 4,
+ 4
+ ],
+ "badnets": [
+ ],
+ "badelements": [
+ ],
+ "pins": [
+ [
+ "VPB",
+ "VNB",
+ "VPWR",
+ "VGND"
+ ], [
+ "VPB",
+ "VNB",
+ "VPWR",
+ "VGND"
+ ]
+ ]
+ },
+ {
+ "name": [
+ "sky130_fd_sc_hd__clkbuf_2",
+ "sky130_fd_sc_hd__clkbuf_2"
+ ],
+ "devices": [
+ [
+ ["sky130_fd_pr__pfet_01v8_hvt", 2],
+ ["sky130_fd_pr__nfet_01v8", 2 ]
+ ], [
+ ["sky130_fd_pr__pfet_01v8_hvt", 2 ],
+ ["sky130_fd_pr__nfet_01v8", 2 ]
+ ]
+ ],
+ "nets": [
+ 7,
+ 7
+ ],
+ "badnets": [
+ ],
+ "badelements": [
+ ],
+ "pins": [
+ [
+ "A",
+ "VPWR",
+ "VPB",
+ "VGND",
+ "VNB",
+ "X"
+ ], [
+ "A",
+ "VPWR",
+ "VPB",
+ "VGND",
+ "VNB",
+ "X"
+ ]
+ ]
+ },
+ {
+ "name": [
+ "sky130_fd_sc_hd__clkbuf_16",
+ "sky130_fd_sc_hd__clkbuf_16"
+ ],
+ "devices": [
+ [
+ ["sky130_fd_pr__pfet_01v8_hvt", 2],
+ ["sky130_fd_pr__nfet_01v8", 2 ]
+ ], [
+ ["sky130_fd_pr__pfet_01v8_hvt", 2 ],
+ ["sky130_fd_pr__nfet_01v8", 2 ]
+ ]
+ ],
+ "nets": [
+ 7,
+ 7
+ ],
+ "badnets": [
+ ],
+ "badelements": [
+ ],
+ "pins": [
+ [
+ "VPWR",
+ "X",
+ "VPB",
+ "VGND",
+ "VNB",
+ "A"
+ ], [
+ "VPWR",
+ "X",
+ "VPB",
+ "VGND",
+ "VNB",
+ "A"
+ ]
+ ]
+ },
+ {
+ "name": [
+ "sky130_fd_sc_hd__decap_4",
+ "sky130_fd_sc_hd__decap_4"
+ ],
+ "devices": [
+ [
+ ["sky130_fd_pr__pfet_01v8_hvt", 1],
+ ["sky130_fd_pr__nfet_01v8", 1 ]
+ ], [
+ ["sky130_fd_pr__pfet_01v8_hvt", 1 ],
+ ["sky130_fd_pr__nfet_01v8", 1 ]
+ ]
+ ],
+ "nets": [
+ 4,
+ 4
+ ],
+ "badnets": [
+ ],
+ "badelements": [
+ ],
+ "pins": [
+ [
+ "VPB",
+ "VNB",
+ "VPWR",
+ "VGND"
+ ], [
+ "VPB",
+ "VNB",
+ "VPWR",
+ "VGND"
+ ]
+ ]
+ },
+ {
+ "name": [
+ "sky130_fd_sc_hd__decap_6",
+ "sky130_fd_sc_hd__decap_6"
+ ],
+ "devices": [
+ [
+ ["sky130_fd_pr__pfet_01v8_hvt", 1],
+ ["sky130_fd_pr__nfet_01v8", 1 ]
+ ], [
+ ["sky130_fd_pr__pfet_01v8_hvt", 1 ],
+ ["sky130_fd_pr__nfet_01v8", 1 ]
+ ]
+ ],
+ "nets": [
+ 4,
+ 4
+ ],
+ "badnets": [
+ ],
+ "badelements": [
+ ],
+ "pins": [
+ [
+ "VPB",
+ "VNB",
+ "VPWR",
+ "VGND"
+ ], [
+ "VPB",
+ "VNB",
+ "VPWR",
+ "VGND"
+ ]
+ ]
+ },
+ {
+ "name": [
+ "sky130_fd_sc_hd__decap_3",
+ "sky130_fd_sc_hd__decap_3"
+ ],
+ "devices": [
+ [
+ ["sky130_fd_pr__pfet_01v8_hvt", 1],
+ ["sky130_fd_pr__nfet_01v8", 1 ]
+ ], [
+ ["sky130_fd_pr__pfet_01v8_hvt", 1 ],
+ ["sky130_fd_pr__nfet_01v8", 1 ]
+ ]
+ ],
+ "nets": [
+ 4,
+ 4
+ ],
+ "badnets": [
+ ],
+ "badelements": [
+ ],
+ "pins": [
+ [
+ "VPB",
+ "VNB",
+ "VPWR",
+ "VGND"
+ ], [
+ "VPB",
+ "VNB",
+ "VPWR",
+ "VGND"
+ ]
+ ]
+ },
+ {
+ "name": [
+ "sky130_fd_sc_hd__and4b_2",
+ "sky130_fd_sc_hd__and4b_2"
+ ],
+ "devices": [
+ [
+ ["sky130_fd_pr__pfet_01v8_hvt", 6],
+ ["sky130_fd_pr__nfet_01v8", 6 ]
+ ], [
+ ["sky130_fd_pr__pfet_01v8_hvt", 6 ],
+ ["sky130_fd_pr__nfet_01v8", 6 ]
+ ]
+ ],
+ "nets": [
+ 14,
+ 14
+ ],
+ "badnets": [
+ ],
+ "badelements": [
+ ],
+ "pins": [
+ [
+ "VGND",
+ "X",
+ "D",
+ "A_N",
+ "C",
+ "B",
+ "VPWR",
+ "VPB",
+ "VNB"
+ ], [
+ "VGND",
+ "X",
+ "D",
+ "A_N",
+ "C",
+ "B",
+ "VPWR",
+ "VPB",
+ "VNB"
+ ]
+ ]
+ },
+ {
+ "name": [
+ "sky130_fd_sc_hd__mux4_1",
+ "sky130_fd_sc_hd__mux4_1"
+ ],
+ "devices": [
+ [
+ ["sky130_fd_pr__pfet_01v8_hvt", 13],
+ ["sky130_fd_pr__nfet_01v8", 13 ]
+ ], [
+ ["sky130_fd_pr__pfet_01v8_hvt", 13 ],
+ ["sky130_fd_pr__nfet_01v8", 13 ]
+ ]
+ ],
+ "nets": [
+ 24,
+ 24
+ ],
+ "badnets": [
+ ],
+ "badelements": [
+ ],
+ "pins": [
+ [
+ "S1",
+ "VPWR",
+ "VGND",
+ "VPB",
+ "VNB",
+ "X",
+ "A1",
+ "A3",
+ "A0",
+ "A2",
+ "S0"
+ ], [
+ "S1",
+ "VPWR",
+ "VGND",
+ "VPB",
+ "VNB",
+ "X",
+ "A1",
+ "A3",
+ "A0",
+ "A2",
+ "S0"
+ ]
+ ]
+ },
+ {
+ "name": [
+ "sky130_fd_sc_hd__conb_1",
+ "sky130_fd_sc_hd__conb_1"
+ ],
+ "devices": [
+ [
+ ["sky130_fd_pr__res_generic_po", 2 ]
+ ], [
+ ["sky130_fd_pr__res_generic_po", 2 ]
+ ]
+ ],
+ "nets": [
+ 4,
+ 4
+ ],
+ "badnets": [
+ ],
+ "badelements": [
+ ],
+ "pins": [
+ [
+ "VGND",
+ "LO",
+ "HI",
+ "VPWR",
+ "VNB",
+ "VPB"
+ ], [
+ "VGND",
+ "LO",
+ "HI",
+ "VPWR",
+ "VNB",
+ "VPB"
+ ]
+ ]
+ },
+ {
+ "name": [
+ "sky130_fd_sc_hd__and4_2",
+ "sky130_fd_sc_hd__and4_2"
+ ],
+ "devices": [
+ [
+ ["sky130_fd_pr__nfet_01v8", 5],
+ ["sky130_fd_pr__pfet_01v8_hvt", 5 ]
+ ], [
+ ["sky130_fd_pr__nfet_01v8", 5 ],
+ ["sky130_fd_pr__pfet_01v8_hvt", 5 ]
+ ]
+ ],
+ "nets": [
+ 13,
+ 13
+ ],
+ "badnets": [
+ ],
+ "badelements": [
+ ],
+ "pins": [
+ [
+ "VPWR",
+ "VPB",
+ "VNB",
+ "VGND",
+ "X",
+ "A",
+ "C",
+ "B",
+ "D"
+ ], [
+ "VPWR",
+ "VPB",
+ "VNB",
+ "VGND",
+ "X",
+ "A",
+ "C",
+ "B",
+ "D"
+ ]
+ ]
+ },
+ {
+ "name": [
+ "sky130_fd_sc_hd__nor4b_2",
+ "sky130_fd_sc_hd__nor4b_2"
+ ],
+ "devices": [
+ [
+ ["sky130_fd_pr__pfet_01v8_hvt", 5],
+ ["sky130_fd_pr__nfet_01v8", 5 ]
+ ], [
+ ["sky130_fd_pr__pfet_01v8_hvt", 5 ],
+ ["sky130_fd_pr__nfet_01v8", 5 ]
+ ]
+ ],
+ "nets": [
+ 13,
+ 13
+ ],
+ "badnets": [
+ ],
+ "badelements": [
+ ],
+ "pins": [
+ [
+ "VPB",
+ "Y",
+ "VGND",
+ "VNB",
+ "D_N",
+ "VPWR",
+ "A",
+ "C",
+ "B"
+ ], [
+ "VPB",
+ "Y",
+ "VGND",
+ "VNB",
+ "D_N",
+ "VPWR",
+ "A",
+ "C",
+ "B"
+ ]
+ ]
+ },
+ {
+ "name": [
+ "sky130_fd_sc_hd__nor3b_2",
+ "sky130_fd_sc_hd__nor3b_2"
+ ],
+ "devices": [
+ [
+ ["sky130_fd_pr__pfet_01v8_hvt", 4],
+ ["sky130_fd_pr__nfet_01v8", 4 ]
+ ], [
+ ["sky130_fd_pr__pfet_01v8_hvt", 4 ],
+ ["sky130_fd_pr__nfet_01v8", 4 ]
+ ]
+ ],
+ "nets": [
+ 11,
+ 11
+ ],
+ "badnets": [
+ ],
+ "badelements": [
+ ],
+ "pins": [
+ [
+ "Y",
+ "VGND",
+ "VNB",
+ "VPB",
+ "VPWR",
+ "A",
+ "B",
+ "C_N"
+ ], [
+ "Y",
+ "VGND",
+ "VNB",
+ "VPB",
+ "VPWR",
+ "A",
+ "B",
+ "C_N"
+ ]
+ ]
+ },
+ {
+ "name": [
+ "sky130_fd_sc_hd__and3b_2",
+ "sky130_fd_sc_hd__and3b_2"
+ ],
+ "devices": [
+ [
+ ["sky130_fd_pr__pfet_01v8_hvt", 5],
+ ["sky130_fd_pr__nfet_01v8", 5 ]
+ ], [
+ ["sky130_fd_pr__pfet_01v8_hvt", 5 ],
+ ["sky130_fd_pr__nfet_01v8", 5 ]
+ ]
+ ],
+ "nets": [
+ 12,
+ 12
+ ],
+ "badnets": [
+ ],
+ "badelements": [
+ ],
+ "pins": [
+ [
+ "VGND",
+ "VNB",
+ "VPWR",
+ "VPB",
+ "C",
+ "X",
+ "B",
+ "A_N"
+ ], [
+ "VGND",
+ "VNB",
+ "VPWR",
+ "VPB",
+ "C",
+ "X",
+ "B",
+ "A_N"
+ ]
+ ]
+ },
+ {
+ "name": [
+ "sky130_fd_sc_hd__and3_2",
+ "sky130_fd_sc_hd__and3_2"
+ ],
+ "devices": [
+ [
+ ["sky130_fd_pr__pfet_01v8_hvt", 4],
+ ["sky130_fd_pr__nfet_01v8", 4 ]
+ ], [
+ ["sky130_fd_pr__pfet_01v8_hvt", 4 ],
+ ["sky130_fd_pr__nfet_01v8", 4 ]
+ ]
+ ],
+ "nets": [
+ 11,
+ 11
+ ],
+ "badnets": [
+ ],
+ "badelements": [
+ ],
+ "pins": [
+ [
+ "X",
+ "VGND",
+ "A",
+ "C",
+ "B",
+ "VNB",
+ "VPWR",
+ "VPB"
+ ], [
+ "X",
+ "VGND",
+ "A",
+ "C",
+ "B",
+ "VNB",
+ "VPWR",
+ "VPB"
+ ]
+ ]
+ },
+ {
+ "name": [
+ "RAM128",
+ "RAM128"
+ ],
+ "devices": [
+ [
+ ["sky130_fd_sc_hd__dlclkp_1", 512],
+ ["sky130_fd_sc_hd__ebufn_2", 4224],
+ ["sky130_fd_sc_hd__clkbuf_4", 153],
+ ["sky130_fd_sc_hd__dlxtp_1", 4096],
+ ["sky130_fd_sc_hd__and4bb_2", 48],
+ ["sky130_fd_sc_hd__dfxtp_1", 128],
+ ["sky130_fd_sc_hd__inv_1", 1024],
+ ["sky130_fd_sc_hd__and2_1", 512],
+ ["sky130_fd_sc_hd__diode_2", 386],
+ ["sky130_fd_sc_hd__decap_8", 1],
+ ["sky130_fd_sc_hd__decap_12", 1],
+ ["sky130_fd_sc_hd__clkbuf_2", 348],
+ ["sky130_fd_sc_hd__clkbuf_16", 160],
+ ["sky130_fd_sc_hd__decap_4", 1],
+ ["sky130_fd_sc_hd__decap_6", 1],
+ ["sky130_fd_sc_hd__decap_3", 1],
+ ["sky130_fd_sc_hd__and4b_2", 48],
+ ["sky130_fd_sc_hd__mux4_1", 32],
+ ["sky130_fd_sc_hd__conb_1", 16],
+ ["sky130_fd_sc_hd__and4_2", 16],
+ ["sky130_fd_sc_hd__nor4b_2", 16],
+ ["sky130_fd_sc_hd__nor3b_2", 5],
+ ["sky130_fd_sc_hd__and3b_2", 10],
+ ["sky130_fd_sc_hd__and3_2", 5 ]
+ ], [
+ ["sky130_fd_sc_hd__dlclkp_1", 512 ],
+ ["sky130_fd_sc_hd__ebufn_2", 4224 ],
+ ["sky130_fd_sc_hd__clkbuf_4", 153 ],
+ ["sky130_fd_sc_hd__dlxtp_1", 4096 ],
+ ["sky130_fd_sc_hd__and4bb_2", 48 ],
+ ["sky130_fd_sc_hd__dfxtp_1", 128 ],
+ ["sky130_fd_sc_hd__inv_1", 1024 ],
+ ["sky130_fd_sc_hd__and2_1", 512 ],
+ ["sky130_fd_sc_hd__diode_2", 386 ],
+ ["sky130_fd_sc_hd__decap_8", 1 ],
+ ["sky130_fd_sc_hd__decap_12", 1 ],
+ ["sky130_fd_sc_hd__clkbuf_2", 348 ],
+ ["sky130_fd_sc_hd__clkbuf_16", 160 ],
+ ["sky130_fd_sc_hd__decap_4", 1 ],
+ ["sky130_fd_sc_hd__decap_6", 1 ],
+ ["sky130_fd_sc_hd__decap_3", 1 ],
+ ["sky130_fd_sc_hd__and4b_2", 48 ],
+ ["sky130_fd_sc_hd__mux4_1", 32 ],
+ ["sky130_fd_sc_hd__conb_1", 16 ],
+ ["sky130_fd_sc_hd__and4_2", 16 ],
+ ["sky130_fd_sc_hd__nor4b_2", 16 ],
+ ["sky130_fd_sc_hd__nor3b_2", 5 ],
+ ["sky130_fd_sc_hd__and3b_2", 10 ],
+ ["sky130_fd_sc_hd__and3_2", 5 ]
+ ]
+ ],
+ "nets": [
+ 7320,
+ 7320
+ ],
+ "badnets": [
+ ],
+ "badelements": [
+ ],
+ "pins": [
+ [
+ "A0[5]",
+ "A0[6]",
+ "CLK",
+ "Di0[0]",
+ "Di0[10]",
+ "Di0[11]",
+ "Di0[12]",
+ "Di0[13]",
+ "Di0[14]",
+ "Di0[15]",
+ "Di0[16]",
+ "Di0[17]",
+ "Di0[18]",
+ "Di0[19]",
+ "Di0[1]",
+ "Di0[20]",
+ "Di0[21]",
+ "Di0[22]",
+ "Di0[23]",
+ "Di0[24]",
+ "Di0[25]",
+ "Di0[26]",
+ "Di0[27]",
+ "Di0[28]",
+ "Di0[29]",
+ "Di0[2]",
+ "Di0[30]",
+ "Di0[31]",
+ "Di0[3]",
+ "Di0[4]",
+ "Di0[5]",
+ "Di0[6]",
+ "Di0[7]",
+ "Di0[8]",
+ "Di0[9]",
+ "Do0[0]",
+ "Do0[1]",
+ "Do0[2]",
+ "Do0[3]",
+ "Do0[4]",
+ "Do0[5]",
+ "Do0[6]",
+ "Do0[7]",
+ "Do0[8]",
+ "Do0[9]",
+ "Do0[10]",
+ "Do0[11]",
+ "Do0[12]",
+ "Do0[13]",
+ "Do0[14]",
+ "Do0[15]",
+ "Do0[16]",
+ "Do0[17]",
+ "Do0[18]",
+ "Do0[19]",
+ "Do0[20]",
+ "Do0[21]",
+ "Do0[22]",
+ "Do0[23]",
+ "Do0[24]",
+ "Do0[25]",
+ "Do0[26]",
+ "Do0[27]",
+ "Do0[28]",
+ "Do0[29]",
+ "Do0[30]",
+ "Do0[31]",
+ "EN0",
+ "A0[3]",
+ "A0[4]",
+ "A0[0]",
+ "A0[1]",
+ "A0[2]",
+ "WE0[0]",
+ "WE0[1]",
+ "WE0[2]",
+ "WE0[3]",
+ "VGND",
+ "VPWR"
+ ], [
+ "A0[5]",
+ "A0[6]",
+ "CLK",
+ "Di0[0]",
+ "Di0[10]",
+ "Di0[11]",
+ "Di0[12]",
+ "Di0[13]",
+ "Di0[14]",
+ "Di0[15]",
+ "Di0[16]",
+ "Di0[17]",
+ "Di0[18]",
+ "Di0[19]",
+ "Di0[1]",
+ "Di0[20]",
+ "Di0[21]",
+ "Di0[22]",
+ "Di0[23]",
+ "Di0[24]",
+ "Di0[25]",
+ "Di0[26]",
+ "Di0[27]",
+ "Di0[28]",
+ "Di0[29]",
+ "Di0[2]",
+ "Di0[30]",
+ "Di0[31]",
+ "Di0[3]",
+ "Di0[4]",
+ "Di0[5]",
+ "Di0[6]",
+ "Di0[7]",
+ "Di0[8]",
+ "Di0[9]",
+ "Do0[0]",
+ "Do0[1]",
+ "Do0[2]",
+ "Do0[3]",
+ "Do0[4]",
+ "Do0[5]",
+ "Do0[6]",
+ "Do0[7]",
+ "Do0[8]",
+ "Do0[9]",
+ "Do0[10]",
+ "Do0[11]",
+ "Do0[12]",
+ "Do0[13]",
+ "Do0[14]",
+ "Do0[15]",
+ "Do0[16]",
+ "Do0[17]",
+ "Do0[18]",
+ "Do0[19]",
+ "Do0[20]",
+ "Do0[21]",
+ "Do0[22]",
+ "Do0[23]",
+ "Do0[24]",
+ "Do0[25]",
+ "Do0[26]",
+ "Do0[27]",
+ "Do0[28]",
+ "Do0[29]",
+ "Do0[30]",
+ "Do0[31]",
+ "EN0",
+ "A0[3]",
+ "A0[4]",
+ "A0[0]",
+ "A0[1]",
+ "A0[2]",
+ "WE0[0]",
+ "WE0[1]",
+ "WE0[2]",
+ "WE0[3]",
+ "VGND",
+ "VPWR"
+ ]
+ ]
+ }
+]
diff --git a/signoff/RAM128/standalone_pvr/eco-RAM128.lvs.report b/signoff/RAM128/standalone_pvr/eco-RAM128.lvs.report
new file mode 100644
index 0000000..f7cadb4
--- /dev/null
+++ b/signoff/RAM128/standalone_pvr/eco-RAM128.lvs.report
@@ -0,0 +1,752 @@
+
+Circuit 1 cell sky130_fd_pr__pfet_01v8_hvt and Circuit 2 cell sky130_fd_pr__pfet_01v8_hvt are black boxes.
+
+Subcircuit pins:
+Circuit 1: sky130_fd_pr__pfet_01v8_hvt |Circuit 2: sky130_fd_pr__pfet_01v8_hvt
+-------------------------------------------|-------------------------------------------
+1 |1
+2 |2
+3 |3
+4 |4
+---------------------------------------------------------------------------------------
+Cell pin lists are equivalent.
+Device classes sky130_fd_pr__pfet_01v8_hvt and sky130_fd_pr__pfet_01v8_hvt are equivalent.
+
+Circuit 1 cell sky130_fd_pr__nfet_01v8 and Circuit 2 cell sky130_fd_pr__nfet_01v8 are black boxes.
+
+Subcircuit pins:
+Circuit 1: sky130_fd_pr__nfet_01v8 |Circuit 2: sky130_fd_pr__nfet_01v8
+-------------------------------------------|-------------------------------------------
+1 |1
+2 |2
+3 |3
+4 |4
+---------------------------------------------------------------------------------------
+Cell pin lists are equivalent.
+Device classes sky130_fd_pr__nfet_01v8 and sky130_fd_pr__nfet_01v8 are equivalent.
+
+Subcircuit summary:
+Circuit 1: sky130_fd_sc_hd__dlclkp_1 |Circuit 2: sky130_fd_sc_hd__dlclkp_1
+-------------------------------------------|-------------------------------------------
+sky130_fd_pr__pfet_01v8_hvt (10) |sky130_fd_pr__pfet_01v8_hvt (10)
+sky130_fd_pr__nfet_01v8 (10) |sky130_fd_pr__nfet_01v8 (10)
+Number of devices: 20 |Number of devices: 20
+Number of nets: 17 |Number of nets: 17
+---------------------------------------------------------------------------------------
+Netlists match uniquely.
+
+Subcircuit pins:
+Circuit 1: sky130_fd_sc_hd__dlclkp_1 |Circuit 2: sky130_fd_sc_hd__dlclkp_1
+-------------------------------------------|-------------------------------------------
+VGND |VGND
+CLK |CLK
+VPB |VPB
+VNB |VNB
+VPWR |VPWR
+GCLK |GCLK
+GATE |GATE
+---------------------------------------------------------------------------------------
+Cell pin lists are equivalent.
+Device classes sky130_fd_sc_hd__dlclkp_1 and sky130_fd_sc_hd__dlclkp_1 are equivalent.
+
+Class sky130_fd_sc_hd__ebufn_2 (0): Merged 4 parallel devices.
+Class sky130_fd_sc_hd__ebufn_2 (1): Merged 4 parallel devices.
+Subcircuit summary:
+Circuit 1: sky130_fd_sc_hd__ebufn_2 |Circuit 2: sky130_fd_sc_hd__ebufn_2
+-------------------------------------------|-------------------------------------------
+sky130_fd_pr__pfet_01v8_hvt (6->4) |sky130_fd_pr__pfet_01v8_hvt (6->4)
+sky130_fd_pr__nfet_01v8 (6->4) |sky130_fd_pr__nfet_01v8 (6->4)
+Number of devices: 8 |Number of devices: 8
+Number of nets: 11 |Number of nets: 11
+---------------------------------------------------------------------------------------
+Netlists match uniquely.
+
+Subcircuit pins:
+Circuit 1: sky130_fd_sc_hd__ebufn_2 |Circuit 2: sky130_fd_sc_hd__ebufn_2
+-------------------------------------------|-------------------------------------------
+VGND |VGND
+TE_B |TE_B
+VPWR |VPWR
+VNB |VNB
+VPB |VPB
+Z |Z
+A |A
+---------------------------------------------------------------------------------------
+Cell pin lists are equivalent.
+Device classes sky130_fd_sc_hd__ebufn_2 and sky130_fd_sc_hd__ebufn_2 are equivalent.
+
+Class sky130_fd_sc_hd__clkbuf_4 (0): Merged 6 parallel devices.
+Class sky130_fd_sc_hd__clkbuf_4 (1): Merged 6 parallel devices.
+Subcircuit summary:
+Circuit 1: sky130_fd_sc_hd__clkbuf_4 |Circuit 2: sky130_fd_sc_hd__clkbuf_4
+-------------------------------------------|-------------------------------------------
+sky130_fd_pr__pfet_01v8_hvt (5->2) |sky130_fd_pr__pfet_01v8_hvt (5->2)
+sky130_fd_pr__nfet_01v8 (5->2) |sky130_fd_pr__nfet_01v8 (5->2)
+Number of devices: 4 |Number of devices: 4
+Number of nets: 7 |Number of nets: 7
+---------------------------------------------------------------------------------------
+Netlists match uniquely.
+
+Subcircuit pins:
+Circuit 1: sky130_fd_sc_hd__clkbuf_4 |Circuit 2: sky130_fd_sc_hd__clkbuf_4
+-------------------------------------------|-------------------------------------------
+VPWR |VPWR
+X |X
+VPB |VPB
+A |A
+VGND |VGND
+VNB |VNB
+---------------------------------------------------------------------------------------
+Cell pin lists are equivalent.
+Device classes sky130_fd_sc_hd__clkbuf_4 and sky130_fd_sc_hd__clkbuf_4 are equivalent.
+
+Subcircuit summary:
+Circuit 1: sky130_fd_sc_hd__dlxtp_1 |Circuit 2: sky130_fd_sc_hd__dlxtp_1
+-------------------------------------------|-------------------------------------------
+sky130_fd_pr__nfet_01v8 (9) |sky130_fd_pr__nfet_01v8 (9)
+sky130_fd_pr__pfet_01v8_hvt (9) |sky130_fd_pr__pfet_01v8_hvt (9)
+Number of devices: 18 |Number of devices: 18
+Number of nets: 16 |Number of nets: 16
+---------------------------------------------------------------------------------------
+Netlists match uniquely.
+
+Subcircuit pins:
+Circuit 1: sky130_fd_sc_hd__dlxtp_1 |Circuit 2: sky130_fd_sc_hd__dlxtp_1
+-------------------------------------------|-------------------------------------------
+VPWR |VPWR
+VGND |VGND
+VPB |VPB
+VNB |VNB
+D |D
+Q |Q
+GATE |GATE
+---------------------------------------------------------------------------------------
+Cell pin lists are equivalent.
+Device classes sky130_fd_sc_hd__dlxtp_1 and sky130_fd_sc_hd__dlxtp_1 are equivalent.
+
+Class sky130_fd_sc_hd__and4bb_2 (0): Merged 2 parallel devices.
+Class sky130_fd_sc_hd__and4bb_2 (1): Merged 2 parallel devices.
+Subcircuit summary:
+Circuit 1: sky130_fd_sc_hd__and4bb_2 |Circuit 2: sky130_fd_sc_hd__and4bb_2
+-------------------------------------------|-------------------------------------------
+sky130_fd_pr__pfet_01v8_hvt (8->7) |sky130_fd_pr__pfet_01v8_hvt (8->7)
+sky130_fd_pr__nfet_01v8 (8->7) |sky130_fd_pr__nfet_01v8 (8->7)
+Number of devices: 14 |Number of devices: 14
+Number of nets: 15 |Number of nets: 15
+---------------------------------------------------------------------------------------
+Netlists match uniquely.
+
+Subcircuit pins:
+Circuit 1: sky130_fd_sc_hd__and4bb_2 |Circuit 2: sky130_fd_sc_hd__and4bb_2
+-------------------------------------------|-------------------------------------------
+VGND |VGND
+X |X
+D |D
+C |C
+B_N |B_N
+A_N |A_N
+VNB |VNB
+VPWR |VPWR
+VPB |VPB
+---------------------------------------------------------------------------------------
+Cell pin lists are equivalent.
+Device classes sky130_fd_sc_hd__and4bb_2 and sky130_fd_sc_hd__and4bb_2 are equivalent.
+
+Subcircuit summary:
+Circuit 1: sky130_fd_sc_hd__dfxtp_1 |Circuit 2: sky130_fd_sc_hd__dfxtp_1
+-------------------------------------------|-------------------------------------------
+sky130_fd_pr__nfet_01v8 (12) |sky130_fd_pr__nfet_01v8 (12)
+sky130_fd_pr__pfet_01v8_hvt (12) |sky130_fd_pr__pfet_01v8_hvt (12)
+Number of devices: 24 |Number of devices: 24
+Number of nets: 18 |Number of nets: 18
+---------------------------------------------------------------------------------------
+Netlists match uniquely.
+
+Subcircuit pins:
+Circuit 1: sky130_fd_sc_hd__dfxtp_1 |Circuit 2: sky130_fd_sc_hd__dfxtp_1
+-------------------------------------------|-------------------------------------------
+VPB |VPB
+VNB |VNB
+VGND |VGND
+VPWR |VPWR
+D |D
+Q |Q
+CLK |CLK
+---------------------------------------------------------------------------------------
+Cell pin lists are equivalent.
+Device classes sky130_fd_sc_hd__dfxtp_1 and sky130_fd_sc_hd__dfxtp_1 are equivalent.
+
+Subcircuit summary:
+Circuit 1: sky130_fd_sc_hd__inv_1 |Circuit 2: sky130_fd_sc_hd__inv_1
+-------------------------------------------|-------------------------------------------
+sky130_fd_pr__nfet_01v8 (1) |sky130_fd_pr__nfet_01v8 (1)
+sky130_fd_pr__pfet_01v8_hvt (1) |sky130_fd_pr__pfet_01v8_hvt (1)
+Number of devices: 2 |Number of devices: 2
+Number of nets: 6 |Number of nets: 6
+---------------------------------------------------------------------------------------
+Netlists match uniquely.
+
+Subcircuit pins:
+Circuit 1: sky130_fd_sc_hd__inv_1 |Circuit 2: sky130_fd_sc_hd__inv_1
+-------------------------------------------|-------------------------------------------
+VGND |VGND
+VNB |VNB
+VPWR |VPWR
+VPB |VPB
+A |A
+Y |Y
+---------------------------------------------------------------------------------------
+Cell pin lists are equivalent.
+Device classes sky130_fd_sc_hd__inv_1 and sky130_fd_sc_hd__inv_1 are equivalent.
+
+Subcircuit summary:
+Circuit 1: sky130_fd_sc_hd__and2_1 |Circuit 2: sky130_fd_sc_hd__and2_1
+-------------------------------------------|-------------------------------------------
+sky130_fd_pr__pfet_01v8_hvt (3) |sky130_fd_pr__pfet_01v8_hvt (3)
+sky130_fd_pr__nfet_01v8 (3) |sky130_fd_pr__nfet_01v8 (3)
+Number of devices: 6 |Number of devices: 6
+Number of nets: 9 |Number of nets: 9
+---------------------------------------------------------------------------------------
+Netlists match uniquely.
+
+Subcircuit pins:
+Circuit 1: sky130_fd_sc_hd__and2_1 |Circuit 2: sky130_fd_sc_hd__and2_1
+-------------------------------------------|-------------------------------------------
+VGND |VGND
+X |X
+A |A
+B |B
+VNB |VNB
+VPWR |VPWR
+VPB |VPB
+---------------------------------------------------------------------------------------
+Cell pin lists are equivalent.
+Device classes sky130_fd_sc_hd__and2_1 and sky130_fd_sc_hd__and2_1 are equivalent.
+
+Cell sky130_fd_sc_hd__diode_2 (0) disconnected node: VPB
+Cell sky130_fd_sc_hd__diode_2 (0) disconnected node: VGND
+Cell sky130_fd_sc_hd__diode_2 (0) disconnected node: VPWR
+Cell sky130_fd_sc_hd__diode_2 (1) disconnected node: VGND
+Cell sky130_fd_sc_hd__diode_2 (1) disconnected node: VPB
+Cell sky130_fd_sc_hd__diode_2 (1) disconnected node: VPWR
+Subcircuit summary:
+Circuit 1: sky130_fd_sc_hd__diode_2 |Circuit 2: sky130_fd_sc_hd__diode_2
+-------------------------------------------|-------------------------------------------
+sky130_fd_pr__diode_pw2nd_05v5 (1) |sky130_fd_pr__diode_pw2nd_05v5 (1)
+Number of devices: 1 |Number of devices: 1
+Number of nets: 2 |Number of nets: 2
+---------------------------------------------------------------------------------------
+Netlists match uniquely.
+
+Subcircuit pins:
+Circuit 1: sky130_fd_sc_hd__diode_2 |Circuit 2: sky130_fd_sc_hd__diode_2
+-------------------------------------------|-------------------------------------------
+VNB |VNB
+DIODE |DIODE
+VPB |VPB
+VGND |VGND
+VPWR |VPWR
+---------------------------------------------------------------------------------------
+Cell pin lists are equivalent.
+Device classes sky130_fd_sc_hd__diode_2 and sky130_fd_sc_hd__diode_2 are equivalent.
+
+Subcircuit summary:
+Circuit 1: sky130_fd_sc_hd__decap_8 |Circuit 2: sky130_fd_sc_hd__decap_8
+-------------------------------------------|-------------------------------------------
+sky130_fd_pr__pfet_01v8_hvt (1) |sky130_fd_pr__pfet_01v8_hvt (1)
+sky130_fd_pr__nfet_01v8 (1) |sky130_fd_pr__nfet_01v8 (1)
+Number of devices: 2 |Number of devices: 2
+Number of nets: 4 |Number of nets: 4
+---------------------------------------------------------------------------------------
+Netlists match uniquely.
+
+Subcircuit pins:
+Circuit 1: sky130_fd_sc_hd__decap_8 |Circuit 2: sky130_fd_sc_hd__decap_8
+-------------------------------------------|-------------------------------------------
+VPB |VPB
+VNB |VNB
+VPWR |VPWR
+VGND |VGND
+---------------------------------------------------------------------------------------
+Cell pin lists are equivalent.
+Device classes sky130_fd_sc_hd__decap_8 and sky130_fd_sc_hd__decap_8 are equivalent.
+
+Subcircuit summary:
+Circuit 1: sky130_fd_sc_hd__decap_12 |Circuit 2: sky130_fd_sc_hd__decap_12
+-------------------------------------------|-------------------------------------------
+sky130_fd_pr__pfet_01v8_hvt (1) |sky130_fd_pr__pfet_01v8_hvt (1)
+sky130_fd_pr__nfet_01v8 (1) |sky130_fd_pr__nfet_01v8 (1)
+Number of devices: 2 |Number of devices: 2
+Number of nets: 4 |Number of nets: 4
+---------------------------------------------------------------------------------------
+Netlists match uniquely.
+
+Subcircuit pins:
+Circuit 1: sky130_fd_sc_hd__decap_12 |Circuit 2: sky130_fd_sc_hd__decap_12
+-------------------------------------------|-------------------------------------------
+VPB |VPB
+VNB |VNB
+VPWR |VPWR
+VGND |VGND
+---------------------------------------------------------------------------------------
+Cell pin lists are equivalent.
+Device classes sky130_fd_sc_hd__decap_12 and sky130_fd_sc_hd__decap_12 are equivalent.
+
+Class sky130_fd_sc_hd__clkbuf_2 (0): Merged 2 parallel devices.
+Class sky130_fd_sc_hd__clkbuf_2 (1): Merged 2 parallel devices.
+Subcircuit summary:
+Circuit 1: sky130_fd_sc_hd__clkbuf_2 |Circuit 2: sky130_fd_sc_hd__clkbuf_2
+-------------------------------------------|-------------------------------------------
+sky130_fd_pr__pfet_01v8_hvt (3->2) |sky130_fd_pr__pfet_01v8_hvt (3->2)
+sky130_fd_pr__nfet_01v8 (3->2) |sky130_fd_pr__nfet_01v8 (3->2)
+Number of devices: 4 |Number of devices: 4
+Number of nets: 7 |Number of nets: 7
+---------------------------------------------------------------------------------------
+Netlists match uniquely.
+
+Subcircuit pins:
+Circuit 1: sky130_fd_sc_hd__clkbuf_2 |Circuit 2: sky130_fd_sc_hd__clkbuf_2
+-------------------------------------------|-------------------------------------------
+A |A
+VPWR |VPWR
+VPB |VPB
+VGND |VGND
+VNB |VNB
+X |X
+---------------------------------------------------------------------------------------
+Cell pin lists are equivalent.
+Device classes sky130_fd_sc_hd__clkbuf_2 and sky130_fd_sc_hd__clkbuf_2 are equivalent.
+
+Class sky130_fd_sc_hd__clkbuf_16 (0): Merged 36 parallel devices.
+Class sky130_fd_sc_hd__clkbuf_16 (1): Merged 36 parallel devices.
+Subcircuit summary:
+Circuit 1: sky130_fd_sc_hd__clkbuf_16 |Circuit 2: sky130_fd_sc_hd__clkbuf_16
+-------------------------------------------|-------------------------------------------
+sky130_fd_pr__pfet_01v8_hvt (20->2) |sky130_fd_pr__pfet_01v8_hvt (20->2)
+sky130_fd_pr__nfet_01v8 (20->2) |sky130_fd_pr__nfet_01v8 (20->2)
+Number of devices: 4 |Number of devices: 4
+Number of nets: 7 |Number of nets: 7
+---------------------------------------------------------------------------------------
+Netlists match uniquely.
+
+Subcircuit pins:
+Circuit 1: sky130_fd_sc_hd__clkbuf_16 |Circuit 2: sky130_fd_sc_hd__clkbuf_16
+-------------------------------------------|-------------------------------------------
+VPWR |VPWR
+X |X
+VPB |VPB
+VGND |VGND
+VNB |VNB
+A |A
+---------------------------------------------------------------------------------------
+Cell pin lists are equivalent.
+Device classes sky130_fd_sc_hd__clkbuf_16 and sky130_fd_sc_hd__clkbuf_16 are equivalent.
+
+Subcircuit summary:
+Circuit 1: sky130_fd_sc_hd__decap_4 |Circuit 2: sky130_fd_sc_hd__decap_4
+-------------------------------------------|-------------------------------------------
+sky130_fd_pr__pfet_01v8_hvt (1) |sky130_fd_pr__pfet_01v8_hvt (1)
+sky130_fd_pr__nfet_01v8 (1) |sky130_fd_pr__nfet_01v8 (1)
+Number of devices: 2 |Number of devices: 2
+Number of nets: 4 |Number of nets: 4
+---------------------------------------------------------------------------------------
+Netlists match uniquely.
+
+Subcircuit pins:
+Circuit 1: sky130_fd_sc_hd__decap_4 |Circuit 2: sky130_fd_sc_hd__decap_4
+-------------------------------------------|-------------------------------------------
+VPB |VPB
+VNB |VNB
+VPWR |VPWR
+VGND |VGND
+---------------------------------------------------------------------------------------
+Cell pin lists are equivalent.
+Device classes sky130_fd_sc_hd__decap_4 and sky130_fd_sc_hd__decap_4 are equivalent.
+
+Subcircuit summary:
+Circuit 1: sky130_fd_sc_hd__decap_6 |Circuit 2: sky130_fd_sc_hd__decap_6
+-------------------------------------------|-------------------------------------------
+sky130_fd_pr__pfet_01v8_hvt (1) |sky130_fd_pr__pfet_01v8_hvt (1)
+sky130_fd_pr__nfet_01v8 (1) |sky130_fd_pr__nfet_01v8 (1)
+Number of devices: 2 |Number of devices: 2
+Number of nets: 4 |Number of nets: 4
+---------------------------------------------------------------------------------------
+Netlists match uniquely.
+
+Subcircuit pins:
+Circuit 1: sky130_fd_sc_hd__decap_6 |Circuit 2: sky130_fd_sc_hd__decap_6
+-------------------------------------------|-------------------------------------------
+VPB |VPB
+VNB |VNB
+VPWR |VPWR
+VGND |VGND
+---------------------------------------------------------------------------------------
+Cell pin lists are equivalent.
+Device classes sky130_fd_sc_hd__decap_6 and sky130_fd_sc_hd__decap_6 are equivalent.
+
+Subcircuit summary:
+Circuit 1: sky130_fd_sc_hd__decap_3 |Circuit 2: sky130_fd_sc_hd__decap_3
+-------------------------------------------|-------------------------------------------
+sky130_fd_pr__pfet_01v8_hvt (1) |sky130_fd_pr__pfet_01v8_hvt (1)
+sky130_fd_pr__nfet_01v8 (1) |sky130_fd_pr__nfet_01v8 (1)
+Number of devices: 2 |Number of devices: 2
+Number of nets: 4 |Number of nets: 4
+---------------------------------------------------------------------------------------
+Netlists match uniquely.
+
+Subcircuit pins:
+Circuit 1: sky130_fd_sc_hd__decap_3 |Circuit 2: sky130_fd_sc_hd__decap_3
+-------------------------------------------|-------------------------------------------
+VPB |VPB
+VNB |VNB
+VPWR |VPWR
+VGND |VGND
+---------------------------------------------------------------------------------------
+Cell pin lists are equivalent.
+Device classes sky130_fd_sc_hd__decap_3 and sky130_fd_sc_hd__decap_3 are equivalent.
+
+Class sky130_fd_sc_hd__and4b_2 (0): Merged 2 parallel devices.
+Class sky130_fd_sc_hd__and4b_2 (1): Merged 2 parallel devices.
+Subcircuit summary:
+Circuit 1: sky130_fd_sc_hd__and4b_2 |Circuit 2: sky130_fd_sc_hd__and4b_2
+-------------------------------------------|-------------------------------------------
+sky130_fd_pr__pfet_01v8_hvt (7->6) |sky130_fd_pr__pfet_01v8_hvt (7->6)
+sky130_fd_pr__nfet_01v8 (7->6) |sky130_fd_pr__nfet_01v8 (7->6)
+Number of devices: 12 |Number of devices: 12
+Number of nets: 14 |Number of nets: 14
+---------------------------------------------------------------------------------------
+Netlists match uniquely.
+
+Subcircuit pins:
+Circuit 1: sky130_fd_sc_hd__and4b_2 |Circuit 2: sky130_fd_sc_hd__and4b_2
+-------------------------------------------|-------------------------------------------
+VGND |VGND
+X |X
+D |D
+A_N |A_N
+C |C
+B |B
+VPWR |VPWR
+VPB |VPB
+VNB |VNB
+---------------------------------------------------------------------------------------
+Cell pin lists are equivalent.
+Device classes sky130_fd_sc_hd__and4b_2 and sky130_fd_sc_hd__and4b_2 are equivalent.
+
+Subcircuit summary:
+Circuit 1: sky130_fd_sc_hd__mux4_1 |Circuit 2: sky130_fd_sc_hd__mux4_1
+-------------------------------------------|-------------------------------------------
+sky130_fd_pr__pfet_01v8_hvt (13) |sky130_fd_pr__pfet_01v8_hvt (13)
+sky130_fd_pr__nfet_01v8 (13) |sky130_fd_pr__nfet_01v8 (13)
+Number of devices: 26 |Number of devices: 26
+Number of nets: 24 |Number of nets: 24
+---------------------------------------------------------------------------------------
+Netlists match uniquely.
+
+Subcircuit pins:
+Circuit 1: sky130_fd_sc_hd__mux4_1 |Circuit 2: sky130_fd_sc_hd__mux4_1
+-------------------------------------------|-------------------------------------------
+S1 |S1
+VPWR |VPWR
+VGND |VGND
+VPB |VPB
+VNB |VNB
+X |X
+A1 |A1
+A3 |A3
+A0 |A0
+A2 |A2
+S0 |S0
+---------------------------------------------------------------------------------------
+Cell pin lists are equivalent.
+Device classes sky130_fd_sc_hd__mux4_1 and sky130_fd_sc_hd__mux4_1 are equivalent.
+
+Cell sky130_fd_sc_hd__conb_1 (0) disconnected node: VNB
+Cell sky130_fd_sc_hd__conb_1 (0) disconnected node: VPB
+Cell sky130_fd_sc_hd__conb_1 (1) disconnected node: VNB
+Cell sky130_fd_sc_hd__conb_1 (1) disconnected node: VPB
+Subcircuit summary:
+Circuit 1: sky130_fd_sc_hd__conb_1 |Circuit 2: sky130_fd_sc_hd__conb_1
+-------------------------------------------|-------------------------------------------
+sky130_fd_pr__res_generic_po (2) |sky130_fd_pr__res_generic_po (2)
+Number of devices: 2 |Number of devices: 2
+Number of nets: 4 |Number of nets: 4
+---------------------------------------------------------------------------------------
+Resolving automorphisms by property value.
+Resolving automorphisms by pin name.
+Netlists match uniquely.
+
+Subcircuit pins:
+Circuit 1: sky130_fd_sc_hd__conb_1 |Circuit 2: sky130_fd_sc_hd__conb_1
+-------------------------------------------|-------------------------------------------
+VGND |VGND
+LO |LO
+HI |HI
+VPWR |VPWR
+VNB |VNB
+VPB |VPB
+---------------------------------------------------------------------------------------
+Cell pin lists are equivalent.
+Device classes sky130_fd_sc_hd__conb_1 and sky130_fd_sc_hd__conb_1 are equivalent.
+
+Class sky130_fd_sc_hd__and4_2 (0): Merged 2 parallel devices.
+Class sky130_fd_sc_hd__and4_2 (1): Merged 2 parallel devices.
+Subcircuit summary:
+Circuit 1: sky130_fd_sc_hd__and4_2 |Circuit 2: sky130_fd_sc_hd__and4_2
+-------------------------------------------|-------------------------------------------
+sky130_fd_pr__nfet_01v8 (6->5) |sky130_fd_pr__nfet_01v8 (6->5)
+sky130_fd_pr__pfet_01v8_hvt (6->5) |sky130_fd_pr__pfet_01v8_hvt (6->5)
+Number of devices: 10 |Number of devices: 10
+Number of nets: 13 |Number of nets: 13
+---------------------------------------------------------------------------------------
+Netlists match uniquely.
+
+Subcircuit pins:
+Circuit 1: sky130_fd_sc_hd__and4_2 |Circuit 2: sky130_fd_sc_hd__and4_2
+-------------------------------------------|-------------------------------------------
+VPWR |VPWR
+VPB |VPB
+VNB |VNB
+VGND |VGND
+X |X
+A |A
+C |C
+B |B
+D |D
+---------------------------------------------------------------------------------------
+Cell pin lists are equivalent.
+Device classes sky130_fd_sc_hd__and4_2 and sky130_fd_sc_hd__and4_2 are equivalent.
+
+Class sky130_fd_sc_hd__nor4b_2 (0): Merged 8 parallel devices.
+Class sky130_fd_sc_hd__nor4b_2 (1): Merged 8 parallel devices.
+Subcircuit summary:
+Circuit 1: sky130_fd_sc_hd__nor4b_2 |Circuit 2: sky130_fd_sc_hd__nor4b_2
+-------------------------------------------|-------------------------------------------
+sky130_fd_pr__pfet_01v8_hvt (9->5) |sky130_fd_pr__pfet_01v8_hvt (9->5)
+sky130_fd_pr__nfet_01v8 (9->5) |sky130_fd_pr__nfet_01v8 (9->5)
+Number of devices: 10 |Number of devices: 10
+Number of nets: 13 |Number of nets: 13
+---------------------------------------------------------------------------------------
+Netlists match uniquely.
+
+Subcircuit pins:
+Circuit 1: sky130_fd_sc_hd__nor4b_2 |Circuit 2: sky130_fd_sc_hd__nor4b_2
+-------------------------------------------|-------------------------------------------
+VPB |VPB
+Y |Y
+VGND |VGND
+VNB |VNB
+D_N |D_N
+VPWR |VPWR
+A |A
+C |C
+B |B
+---------------------------------------------------------------------------------------
+Cell pin lists are equivalent.
+Device classes sky130_fd_sc_hd__nor4b_2 and sky130_fd_sc_hd__nor4b_2 are equivalent.
+
+Class sky130_fd_sc_hd__nor3b_2 (0): Merged 6 parallel devices.
+Class sky130_fd_sc_hd__nor3b_2 (1): Merged 6 parallel devices.
+Subcircuit summary:
+Circuit 1: sky130_fd_sc_hd__nor3b_2 |Circuit 2: sky130_fd_sc_hd__nor3b_2
+-------------------------------------------|-------------------------------------------
+sky130_fd_pr__pfet_01v8_hvt (7->4) |sky130_fd_pr__pfet_01v8_hvt (7->4)
+sky130_fd_pr__nfet_01v8 (7->4) |sky130_fd_pr__nfet_01v8 (7->4)
+Number of devices: 8 |Number of devices: 8
+Number of nets: 11 |Number of nets: 11
+---------------------------------------------------------------------------------------
+Netlists match uniquely.
+
+Subcircuit pins:
+Circuit 1: sky130_fd_sc_hd__nor3b_2 |Circuit 2: sky130_fd_sc_hd__nor3b_2
+-------------------------------------------|-------------------------------------------
+Y |Y
+VGND |VGND
+VNB |VNB
+VPB |VPB
+VPWR |VPWR
+A |A
+B |B
+C_N |C_N
+---------------------------------------------------------------------------------------
+Cell pin lists are equivalent.
+Device classes sky130_fd_sc_hd__nor3b_2 and sky130_fd_sc_hd__nor3b_2 are equivalent.
+
+Class sky130_fd_sc_hd__and3b_2 (0): Merged 2 parallel devices.
+Class sky130_fd_sc_hd__and3b_2 (1): Merged 2 parallel devices.
+Subcircuit summary:
+Circuit 1: sky130_fd_sc_hd__and3b_2 |Circuit 2: sky130_fd_sc_hd__and3b_2
+-------------------------------------------|-------------------------------------------
+sky130_fd_pr__pfet_01v8_hvt (6->5) |sky130_fd_pr__pfet_01v8_hvt (6->5)
+sky130_fd_pr__nfet_01v8 (6->5) |sky130_fd_pr__nfet_01v8 (6->5)
+Number of devices: 10 |Number of devices: 10
+Number of nets: 12 |Number of nets: 12
+---------------------------------------------------------------------------------------
+Netlists match uniquely.
+
+Subcircuit pins:
+Circuit 1: sky130_fd_sc_hd__and3b_2 |Circuit 2: sky130_fd_sc_hd__and3b_2
+-------------------------------------------|-------------------------------------------
+VGND |VGND
+VNB |VNB
+VPWR |VPWR
+VPB |VPB
+C |C
+X |X
+B |B
+A_N |A_N
+---------------------------------------------------------------------------------------
+Cell pin lists are equivalent.
+Device classes sky130_fd_sc_hd__and3b_2 and sky130_fd_sc_hd__and3b_2 are equivalent.
+
+Class sky130_fd_sc_hd__and3_2 (0): Merged 2 parallel devices.
+Class sky130_fd_sc_hd__and3_2 (1): Merged 2 parallel devices.
+Subcircuit summary:
+Circuit 1: sky130_fd_sc_hd__and3_2 |Circuit 2: sky130_fd_sc_hd__and3_2
+-------------------------------------------|-------------------------------------------
+sky130_fd_pr__pfet_01v8_hvt (5->4) |sky130_fd_pr__pfet_01v8_hvt (5->4)
+sky130_fd_pr__nfet_01v8 (5->4) |sky130_fd_pr__nfet_01v8 (5->4)
+Number of devices: 8 |Number of devices: 8
+Number of nets: 11 |Number of nets: 11
+---------------------------------------------------------------------------------------
+Netlists match uniquely.
+
+Subcircuit pins:
+Circuit 1: sky130_fd_sc_hd__and3_2 |Circuit 2: sky130_fd_sc_hd__and3_2
+-------------------------------------------|-------------------------------------------
+X |X
+VGND |VGND
+A |A
+C |C
+B |B
+VNB |VNB
+VPWR |VPWR
+VPB |VPB
+---------------------------------------------------------------------------------------
+Cell pin lists are equivalent.
+Device classes sky130_fd_sc_hd__and3_2 and sky130_fd_sc_hd__and3_2 are equivalent.
+
+Class RAM128 (0): Merged 1013 parallel devices.
+Class RAM128 (1): Merged 1013 parallel devices.
+Subcircuit summary:
+Circuit 1: RAM128 |Circuit 2: RAM128
+-------------------------------------------|-------------------------------------------
+sky130_fd_sc_hd__dlclkp_1 (512) |sky130_fd_sc_hd__dlclkp_1 (512)
+sky130_fd_sc_hd__ebufn_2 (4224) |sky130_fd_sc_hd__ebufn_2 (4224)
+sky130_fd_sc_hd__clkbuf_4 (153) |sky130_fd_sc_hd__clkbuf_4 (153)
+sky130_fd_sc_hd__dlxtp_1 (4096) |sky130_fd_sc_hd__dlxtp_1 (4096)
+sky130_fd_sc_hd__and4bb_2 (48) |sky130_fd_sc_hd__and4bb_2 (48)
+sky130_fd_sc_hd__dfxtp_1 (128) |sky130_fd_sc_hd__dfxtp_1 (128)
+sky130_fd_sc_hd__inv_1 (1024) |sky130_fd_sc_hd__inv_1 (1024)
+sky130_fd_sc_hd__and2_1 (512) |sky130_fd_sc_hd__and2_1 (512)
+sky130_fd_sc_hd__diode_2 (770->386) |sky130_fd_sc_hd__diode_2 (770->386)
+sky130_fd_sc_hd__decap_8 (55->1) |sky130_fd_sc_hd__decap_8 (55->1)
+sky130_fd_sc_hd__decap_12 (475->1) |sky130_fd_sc_hd__decap_12 (475->1)
+sky130_fd_sc_hd__clkbuf_2 (348) |sky130_fd_sc_hd__clkbuf_2 (348)
+sky130_fd_sc_hd__clkbuf_16 (160) |sky130_fd_sc_hd__clkbuf_16 (160)
+sky130_fd_sc_hd__decap_4 (30->1) |sky130_fd_sc_hd__decap_4 (30->1)
+sky130_fd_sc_hd__decap_6 (12->1) |sky130_fd_sc_hd__decap_6 (12->1)
+sky130_fd_sc_hd__decap_3 (62->1) |sky130_fd_sc_hd__decap_3 (62->1)
+sky130_fd_sc_hd__and4b_2 (48) |sky130_fd_sc_hd__and4b_2 (48)
+sky130_fd_sc_hd__mux4_1 (32) |sky130_fd_sc_hd__mux4_1 (32)
+sky130_fd_sc_hd__conb_1 (16) |sky130_fd_sc_hd__conb_1 (16)
+sky130_fd_sc_hd__and4_2 (16) |sky130_fd_sc_hd__and4_2 (16)
+sky130_fd_sc_hd__nor4b_2 (16) |sky130_fd_sc_hd__nor4b_2 (16)
+sky130_fd_sc_hd__nor3b_2 (5) |sky130_fd_sc_hd__nor3b_2 (5)
+sky130_fd_sc_hd__and3b_2 (10) |sky130_fd_sc_hd__and3b_2 (10)
+sky130_fd_sc_hd__and3_2 (5) |sky130_fd_sc_hd__and3_2 (5)
+Number of devices: 11744 |Number of devices: 11744
+Number of nets: 7320 |Number of nets: 7320
+---------------------------------------------------------------------------------------
+Resolving automorphisms by property value.
+Resolving automorphisms by pin name.
+Netlists match uniquely.
+
+Subcircuit pins:
+Circuit 1: RAM128 |Circuit 2: RAM128
+-------------------------------------------|-------------------------------------------
+A0[5] |A0[5]
+A0[6] |A0[6]
+CLK |CLK
+Di0[0] |Di0[0]
+Di0[10] |Di0[10]
+Di0[11] |Di0[11]
+Di0[12] |Di0[12]
+Di0[13] |Di0[13]
+Di0[14] |Di0[14]
+Di0[15] |Di0[15]
+Di0[16] |Di0[16]
+Di0[17] |Di0[17]
+Di0[18] |Di0[18]
+Di0[19] |Di0[19]
+Di0[1] |Di0[1]
+Di0[20] |Di0[20]
+Di0[21] |Di0[21]
+Di0[22] |Di0[22]
+Di0[23] |Di0[23]
+Di0[24] |Di0[24]
+Di0[25] |Di0[25]
+Di0[26] |Di0[26]
+Di0[27] |Di0[27]
+Di0[28] |Di0[28]
+Di0[29] |Di0[29]
+Di0[2] |Di0[2]
+Di0[30] |Di0[30]
+Di0[31] |Di0[31]
+Di0[3] |Di0[3]
+Di0[4] |Di0[4]
+Di0[5] |Di0[5]
+Di0[6] |Di0[6]
+Di0[7] |Di0[7]
+Di0[8] |Di0[8]
+Di0[9] |Di0[9]
+Do0[0] |Do0[0]
+Do0[1] |Do0[1]
+Do0[2] |Do0[2]
+Do0[3] |Do0[3]
+Do0[4] |Do0[4]
+Do0[5] |Do0[5]
+Do0[6] |Do0[6]
+Do0[7] |Do0[7]
+Do0[8] |Do0[8]
+Do0[9] |Do0[9]
+Do0[10] |Do0[10]
+Do0[11] |Do0[11]
+Do0[12] |Do0[12]
+Do0[13] |Do0[13]
+Do0[14] |Do0[14]
+Do0[15] |Do0[15]
+Do0[16] |Do0[16]
+Do0[17] |Do0[17]
+Do0[18] |Do0[18]
+Do0[19] |Do0[19]
+Do0[20] |Do0[20]
+Do0[21] |Do0[21]
+Do0[22] |Do0[22]
+Do0[23] |Do0[23]
+Do0[24] |Do0[24]
+Do0[25] |Do0[25]
+Do0[26] |Do0[26]
+Do0[27] |Do0[27]
+Do0[28] |Do0[28]
+Do0[29] |Do0[29]
+Do0[30] |Do0[30]
+Do0[31] |Do0[31]
+EN0 |EN0
+A0[3] |A0[3]
+A0[4] |A0[4]
+A0[0] |A0[0]
+A0[1] |A0[1]
+A0[2] |A0[2]
+WE0[0] |WE0[0]
+WE0[1] |WE0[1]
+WE0[2] |WE0[2]
+WE0[3] |WE0[3]
+VGND |VGND
+VPWR |VPWR
+---------------------------------------------------------------------------------------
+Cell pin lists are equivalent.
+Device classes RAM128 and RAM128 are equivalent.
+
+Final result: Circuits match uniquely.
+.
diff --git a/signoff/RAM128/standalone_pvr/eco-RAM128.unflattened b/signoff/RAM128/standalone_pvr/eco-RAM128.unflattened
new file mode 100644
index 0000000..e69de29
diff --git a/signoff/RAM128/standalone_pvr/eco-RAM128_klayout_drc.xml b/signoff/RAM128/standalone_pvr/eco-RAM128_klayout_drc.xml
new file mode 100644
index 0000000..cc82c7b
--- /dev/null
+++ b/signoff/RAM128/standalone_pvr/eco-RAM128_klayout_drc.xml
@@ -0,0 +1,873 @@
+
+
+ SKY130 DRC runset
+
+ drc: script='tech-files/sky130A_mr.drc'
+ RAM128
+
+
+
+
+ dnwell.2
+ dnwell.2 : min. dnwell width : 3.0um
+
+
+
+
+ nwell.1
+ nwell.1 : min. nwell width : 0.84um
+
+
+
+
+ nwell.2a
+ nwell.2a : min. nwell spacing (merged if less) : 1.27um
+
+
+
+
+ nwell.6
+ nwell.6 : min enclosure of nwellHole by dnwell : 1.03um
+
+
+
+
+ hvtp.1
+ hvtp.1 : min. hvtp width : 0.38um
+
+
+
+
+ hvtp.2
+ hvtp.2 : min. hvtp spacing : 0.38um
+
+
+
+
+ hvtr.1
+ hvtr.1 : min. hvtr width : 0.38um
+
+
+
+
+ hvtr.2
+ hvtr.2 : min. hvtr spacing : 0.38um
+
+
+
+
+ hvtr.2_a
+ hvtr.2_a : hvtr must not overlap hvtp
+
+
+
+
+ lvtn.1a
+ lvtn.1a : min. lvtn width : 0.38um
+
+
+
+
+ lvtn.2
+ lvtn.2 : min. lvtn spacing : 0.38um
+
+
+
+
+ ncm.1
+ ncm.1 : min. ncm width : 0.38um
+
+
+
+
+ ncm.2a
+ ncm.2a : min. ncm spacing : 0.38um
+
+
+
+
+ difftap.1
+ difftap.1 : min. diff width across areaid:ce : 0.15um
+
+
+
+
+ difftap.1_a
+ difftap.1_a : min. diff width in periphery : 0.15um
+
+
+
+
+ difftap.1_b
+ difftap.1_b : min. tap width across areaid:ce : 0.15um
+
+
+
+
+ difftap.1_c
+ difftap.1_c : min. tap width in periphery : 0.15um
+
+
+
+
+ difftap.3
+ difftap.3 : min. difftap spacing : 0.27um
+
+
+
+
+ tunm.1
+ tunm.1 : min. tunm width : 0.41um
+
+
+
+
+ tunm.2
+ tunm.2 : min. tunm spacing : 0.5um
+
+
+
+
+ poly.1a
+ poly.1a : min. poly width : 0.15um
+
+
+
+
+ poly.2
+ poly.2 : min. poly spacing : 0.21um
+
+
+
+
+ rpm.1a
+ rpm.1a : min. rpm width : 1.27um
+
+
+
+
+ rpm.2
+ rpm.2 : min. rpm spacing : 0.84um
+
+
+
+
+ urpm.1a
+ urpm.1a : min. rpm width : 1.27um
+
+
+
+
+ urpm.2
+ urpm.2 : min. rpm spacing : 0.84um
+
+
+
+
+ npc.1
+ npc.1 : min. npc width : 0.27um
+
+
+
+
+ npc.2
+ npc.2 : min. npc spacing, should be manually merged if less than : 0.27um
+
+
+
+
+ nsd.1
+ nsd.1 : min. nsdm width : 0.38um
+
+
+
+
+ nsd.2
+ nsd.2 : min. nsdm spacing, should be manually merged if less than : 0.38um
+
+
+
+
+ psd.1
+ psd.1 : min. psdm width : 0.38um
+
+
+
+
+ psd.2
+ psd.2 : min. psdm spacing, should be manually merged if less than : 0.38um
+
+
+
+
+ licon.1
+ licon.1 : licon should be rectangle
+
+
+
+
+ licon.1_a/b
+ licon.1_a/b : minimum/maximum width of licon : 0.17um
+
+
+
+
+ licon.13
+ licon.13 : min. difftap licon spacing to npc : 0.09um
+
+
+
+
+ licon.13_a
+ licon.13_a : licon of diffTap in periphery must not overlap npc
+
+
+
+
+ licon.17
+ licon.17 : Licons may not overlap both poly and (diff or tap)
+
+
+
+
+ capm.1
+ capm.1 : min. capm width : 1.0um
+
+
+
+
+ capm.2a
+ capm.2a : min. capm spacing : 0.84um
+
+
+
+
+ capm.2b
+ capm.2b : min. capm spacing : 1.2um
+
+
+
+
+ capm.2b_a
+ capm.2b_a : min. spacing of m3_bot_plate : 1.2um
+
+
+
+
+ capm.3
+ capm.3 : min. capm and m3 enclosure of m3 : 0.14um
+
+
+
+
+ capm.3_a
+ capm.3_a : min. m3 enclosure of capm : 0.14um
+
+
+
+
+ capm.4
+ capm.4 : min. capm enclosure of via3 : 0.14um
+
+
+
+
+ capm.5
+ capm.5 : min. capm spacing to via3 : 0.14um
+
+
+
+
+ capm.11
+ capm.11 : Min spacing of capm and met3 not overlapping capm : 0.5um
+
+
+
+
+ cap2m.1
+ cap2m.1 : min. cap2m width : 1.0um
+
+
+
+
+ cap2m.2a
+ cap2m.2a : min. cap2m spacing : 0.84um
+
+
+
+
+ cap2m.2b
+ cap2m.2b : min. cap2m spacing : 1.2um
+
+
+
+
+ cap2m.2b_a
+ cap2m.2b_a : min. spacing of m4_bot_plate : 1.2um
+
+
+
+
+ cap2m.3
+ cap2m.3 : min. m4 enclosure of cap2m : 0.14um
+
+
+
+
+ cap2m.3_a
+ cap2m.3_a : min. m4 enclosure of cap2m : 0.14um
+
+
+
+
+ cap2m.4
+ cap2m.4 : min. cap2m enclosure of via4 : 0.14um
+
+
+
+
+ cap2m.5
+ cap2m.5 : min. cap2m spacing to via4 : 0.14um
+
+
+
+
+ cap2m.11
+ cap2m.11 : Min spacing of cap2m and met4 not overlapping cap2m : 0.5um
+
+
+
+
+ li.1
+ li.1 : min. li width : 0.17um
+
+
+
+
+ li.3
+ li.3 : min. li spacing : 0.17um
+
+
+
+
+ li.5
+ li.5 : min. li enclosure of licon of 2 adjacent edges : 0.08um
+
+
+
+
+ li.6
+ li.6 : min. li area : 0.0561um²
+
+
+
+
+ ct.1
+ ct.1: non-ring mcon should be rectangular
+
+
+
+
+ ct.1_a
+ ct.1_a : minimum width of mcon : 0.17um
+
+
+
+
+ ct.1_b
+ ct.1_b : maximum length of mcon : 0.17um
+
+
+
+
+ ct.2
+ ct.2 : min. mcon spacing : 0.19um
+
+
+
+
+ ct.3
+ ct.3 : min. width of ring-shaped mcon : 0.17um
+
+
+
+
+ ct.3_a
+ ct.3_a : max. width of ring-shaped mcon : 0.175um
+
+
+
+
+ ct.3_b
+ ct.3_b: ring-shaped mcon must be enclosed by areaid_sl
+
+
+
+
+ ct.4
+ ct.4 : mcon should covered by li
+
+
+
+
+ m1.1
+ m1.1 : min. m1 width : 0.14um
+
+
+
+
+ m1.2
+ m1.2 : min. m1 spacing : 0.14um
+
+
+
+
+ m1.3ab
+ m1.3ab : min. 3um.m1 spacing m1 : 0.28um
+
+
+
+
+ 791_m1.4
+ 791_m1.4 : min. m1 enclosure of mcon : 0.03um
+
+
+
+
+ m1.4
+ m1.4 : mcon periphery must be enclosed by m1
+
+
+
+
+ m1.4a
+ m1.4a : min. m1 enclosure of mcon for specific cells : 0.005um
+
+
+
+
+ m1.4a_a
+ m1.4a_a : mcon periph must be enclosed by met1 for specific cells
+
+
+
+
+ m1.6
+ m1.6 : min. m1 area : 0.083um²
+
+
+
+
+ m1.7
+ m1.7 : min. m1 with holes area : 0.14um²
+
+
+
+
+ m1.5
+ m1.5 : min. m1 enclosure of mcon of 2 adjacent edges : 0.06um
+
+
+
+
+ via.1a
+ via.1a : via outside of moduleCut should be rectangular
+
+
+
+
+ via.1a_a
+ via.1a_a : min. width of via outside of moduleCut : 0.15um
+
+
+
+
+ via.1a_b
+ via.1a_b : maximum length of via : 0.15um
+
+
+
+
+ via.2
+ via.2 : min. via spacing : 0.17um
+
+
+
+
+ via.3
+ via.3 : min. width of ring-shaped via : 0.2um
+
+
+
+
+ via.3_a
+ via.3_a : max. width of ring-shaped via : 0.205um
+
+
+
+
+ via.3_b
+ via.3_b: ring-shaped via must be enclosed by areaid_sl
+
+
+
+
+ via.4a
+ via.4a : min. m1 enclosure of 0.15um via : 0.055um
+
+
+
+
+ via.4a_a
+ via.4a_a : 0.15um via must be enclosed by met1
+
+
+
+
+ via.5a
+ via.5a : min. m1 enclosure of 0.15um via of 2 adjacent edges : 0.085um
+
+
+
+
+ m2.1
+ m2.1 : min. m2 width : 0.14um
+
+
+
+
+ m2.2
+ m2.2 : min. m2 spacing : 0.14um
+
+
+
+
+ m2.3ab
+ m2.3ab : min. 3um.m2 spacing m2 : 0.28um
+
+
+
+
+ m2.6
+ m2.6 : min. m2 area : 0.0676um²
+
+
+
+
+ m2.7
+ m2.7 : min. m2 holes area : 0.14um²
+
+
+
+
+ m2.4
+ m2.4 : min. m2 enclosure of via : 0.055um
+
+
+
+
+ m2.4_a
+ m2.4_a : via in periphery must be enclosed by met2
+
+
+
+
+ m2.5
+ m2.5 : min. m2 enclosure of via of 2 adjacent edges : 0.085um
+
+
+
+
+ via2.1a
+ via2.1a : via2 outside of moduleCut should be rectangular
+
+
+
+
+ via2.1a_a
+ via2.1a_a : min. width of via2 outside of moduleCut : 0.2um
+
+
+
+
+ via2.1a_b
+ via2.1a_b : maximum length of via2 : 0.2um
+
+
+
+
+ via2.2
+ via2.2 : min. via2 spacing : 0.2um
+
+
+
+
+ via2.3
+ via2.3 : min. width of ring-shaped via2 : 0.2um
+
+
+
+
+ via2.3_a
+ via2.3_a : max. width of ring-shaped via2 : 0.205um
+
+
+
+
+ via2.3_b
+ via2.3_b: ring-shaped via2 must be enclosed by areaid_sl
+
+
+
+
+ via2.4
+ via2.4 : min. m2 enclosure of via2 : 0.04um
+
+
+
+
+ via2.4_a
+ via2.4_a : via must be enclosed by met2
+
+
+
+
+ via2.5
+ via2.5 : min. m3 enclosure of via2 of 2 adjacent edges : 0.085um
+
+
+
+
+ m3.1
+ m3.1 : min. m3 width : 0.3um
+
+
+
+
+ m3.2
+ m3.2 : min. m3 spacing : 0.3um
+
+
+
+
+ m3.3cd
+ m3.3cd : min. 3um.m3 spacing m3 : 0.4um
+
+
+
+
+ m3.4
+ m3.4 : min. m3 enclosure of via2 : 0.065um
+
+
+
+
+ m3.4_a
+ m3.4_a : via2 must be enclosed by met3
+
+
+
+
+ via3.1
+ via3.1 : via3 outside of moduleCut should be rectangular
+
+
+
+
+ via3.1_a
+ via3.1_a : min. width of via3 outside of moduleCut : 0.2um
+
+
+
+
+ via3.1_b
+ via3.1_b : maximum length of via3 : 0.2um
+
+
+
+
+ via3.2
+ via3.2 : min. via3 spacing : 0.2um
+
+
+
+
+ via3.4
+ via3.4 : min. m3 enclosure of via3 : 0.06um
+
+
+
+
+ via3.4_a
+ via3.4_a : non-ring via3 must be enclosed by met3
+
+
+
+
+ via3.5
+ via3.5 : min. m3 enclosure of via3 of 2 adjacent edges : 0.09um
+
+
+
+
+ m4.1
+ m4.1 : min. m4 width : 0.3um
+
+
+
+
+ m4.2
+ m4.2 : min. m4 spacing : 0.3um
+
+
+
+
+ m4.4a
+ m4.4a : min. m4 area : 0.240um²
+
+
+
+
+ m4.5ab
+ m4.5ab : min. 3um.m4 spacing m4 : 0.4um
+
+
+
+
+ m4.3
+ m4.3 : min. m4 enclosure of via3 : 0.065um
+
+
+
+
+ m4.3_a
+ m4.3_a : via3 must be enclosed by met4
+
+
+
+
+ via4.1
+ via4.1 : via4 outside of moduleCut should be rectangular
+
+
+
+
+ via4.1_a
+ via4.1_a : min. width of via4 outside of moduleCut : 0.8um
+
+
+
+
+ via4.1_b
+ via4.1_b : maximum length of via4 : 0.8um
+
+
+
+
+ via4.2
+ via4.2 : min. via4 spacing : 0.8um
+
+
+
+
+ via4.3
+ via4.3 : min. width of ring-shaped via4 : 0.8um
+
+
+
+
+ via4.3_a
+ via4.3_a : max. width of ring-shaped via4 : 0.805um
+
+
+
+
+ via4.3_b
+ via4.3_b: ring-shaped via4 must be enclosed by areaid_sl
+
+
+
+
+ via4.4
+ via4.4 : min. m4 enclosure of via4 : 0.19um
+
+
+
+
+ via4.4_a
+ via4.4_a : m4 must enclose all via4
+
+
+
+
+ m5.1
+ m5.1 : min. m5 width : 1.6um
+
+
+
+
+ m5.2
+ m5.2 : min. m5 spacing : 1.6um
+
+
+
+
+ m5.3
+ m5.3 : min. m5 enclosure of via4 : 0.31um
+
+
+
+
+ m5.3_a
+ m5.3_a : via must be enclosed by m5
+
+
+
+
+ m5.4
+ m5.4 : min. m5 area : 4.0um²
+
+
+
+
+ pad.2
+ pad.2 : min. pad spacing : 1.27um
+
+
+
+
+ hvi.1
+ hvi.1 : min. hvi width : 0.6um
+
+
+
+
+ hvi.2a
+ hvi.2a : min. hvi spacing : 0.7um
+
+
+
+
+ hvntm.1
+ hvntm.1 : min. hvntm width : 0.7um
+
+
+
+
+ hvntm.2
+ hvntm.2 : min. hvntm spacing : 0.7um
+
+
+
+
+
+
+ RAM128
+
+
+
+ |
+
+
+
+
diff --git a/signoff/RAM128/standalone_pvr/eco-lvs_summary.rpt b/signoff/RAM128/standalone_pvr/eco-lvs_summary.rpt
new file mode 100644
index 0000000..64103fd
--- /dev/null
+++ b/signoff/RAM128/standalone_pvr/eco-lvs_summary.rpt
@@ -0,0 +1 @@
+Layout Vs Schematic Passed
\ No newline at end of file
diff --git a/signoff/RAM256/standalone_pvr/eco-RAM256.lvs.json b/signoff/RAM256/standalone_pvr/eco-RAM256.lvs.json
new file mode 100644
index 0000000..b29495f
--- /dev/null
+++ b/signoff/RAM256/standalone_pvr/eco-RAM256.lvs.json
@@ -0,0 +1,1388 @@
+[
+ {
+ "pins": [
+ [
+ "1",
+ "2",
+ "3",
+ "4"
+ ], [
+ "1",
+ "2",
+ "3",
+ "4"
+ ]
+ ]
+ },
+ {
+ "pins": [
+ [
+ "1",
+ "2",
+ "3",
+ "4"
+ ], [
+ "1",
+ "2",
+ "3",
+ "4"
+ ]
+ ]
+ },
+ {
+ "name": [
+ "sky130_fd_sc_hd__and2_1",
+ "sky130_fd_sc_hd__and2_1"
+ ],
+ "devices": [
+ [
+ ["sky130_fd_pr__pfet_01v8_hvt", 3],
+ ["sky130_fd_pr__nfet_01v8", 3 ]
+ ], [
+ ["sky130_fd_pr__pfet_01v8_hvt", 3 ],
+ ["sky130_fd_pr__nfet_01v8", 3 ]
+ ]
+ ],
+ "nets": [
+ 9,
+ 9
+ ],
+ "badnets": [
+ ],
+ "badelements": [
+ ],
+ "pins": [
+ [
+ "VGND",
+ "X",
+ "A",
+ "B",
+ "VNB",
+ "VPWR",
+ "VPB"
+ ], [
+ "VGND",
+ "X",
+ "A",
+ "B",
+ "VNB",
+ "VPWR",
+ "VPB"
+ ]
+ ]
+ },
+ {
+ "name": [
+ "sky130_fd_sc_hd__dlxtp_1",
+ "sky130_fd_sc_hd__dlxtp_1"
+ ],
+ "devices": [
+ [
+ ["sky130_fd_pr__nfet_01v8", 9],
+ ["sky130_fd_pr__pfet_01v8_hvt", 9 ]
+ ], [
+ ["sky130_fd_pr__nfet_01v8", 9 ],
+ ["sky130_fd_pr__pfet_01v8_hvt", 9 ]
+ ]
+ ],
+ "nets": [
+ 16,
+ 16
+ ],
+ "badnets": [
+ ],
+ "badelements": [
+ ],
+ "pins": [
+ [
+ "VPWR",
+ "VGND",
+ "VPB",
+ "VNB",
+ "D",
+ "Q",
+ "GATE"
+ ], [
+ "VPWR",
+ "VGND",
+ "VPB",
+ "VNB",
+ "D",
+ "Q",
+ "GATE"
+ ]
+ ]
+ },
+ {
+ "name": [
+ "sky130_fd_sc_hd__ebufn_2",
+ "sky130_fd_sc_hd__ebufn_2"
+ ],
+ "devices": [
+ [
+ ["sky130_fd_pr__pfet_01v8_hvt", 4],
+ ["sky130_fd_pr__nfet_01v8", 4 ]
+ ], [
+ ["sky130_fd_pr__pfet_01v8_hvt", 4 ],
+ ["sky130_fd_pr__nfet_01v8", 4 ]
+ ]
+ ],
+ "nets": [
+ 11,
+ 11
+ ],
+ "badnets": [
+ ],
+ "badelements": [
+ ],
+ "pins": [
+ [
+ "VGND",
+ "TE_B",
+ "VPWR",
+ "VNB",
+ "VPB",
+ "Z",
+ "A"
+ ], [
+ "VGND",
+ "TE_B",
+ "VPWR",
+ "VNB",
+ "VPB",
+ "Z",
+ "A"
+ ]
+ ]
+ },
+ {
+ "name": [
+ "sky130_fd_sc_hd__dlclkp_1",
+ "sky130_fd_sc_hd__dlclkp_1"
+ ],
+ "devices": [
+ [
+ ["sky130_fd_pr__pfet_01v8_hvt", 10],
+ ["sky130_fd_pr__nfet_01v8", 10 ]
+ ], [
+ ["sky130_fd_pr__pfet_01v8_hvt", 10 ],
+ ["sky130_fd_pr__nfet_01v8", 10 ]
+ ]
+ ],
+ "nets": [
+ 17,
+ 17
+ ],
+ "badnets": [
+ ],
+ "badelements": [
+ ],
+ "pins": [
+ [
+ "VGND",
+ "CLK",
+ "VPB",
+ "VNB",
+ "VPWR",
+ "GCLK",
+ "GATE"
+ ], [
+ "VGND",
+ "CLK",
+ "VPB",
+ "VNB",
+ "VPWR",
+ "GCLK",
+ "GATE"
+ ]
+ ]
+ },
+ {
+ "name": [
+ "sky130_fd_sc_hd__diode_2",
+ "sky130_fd_sc_hd__diode_2"
+ ],
+ "devices": [
+ [
+ ["sky130_fd_pr__diode_pw2nd_05v5", 1 ]
+ ], [
+ ["sky130_fd_pr__diode_pw2nd_05v5", 1 ]
+ ]
+ ],
+ "nets": [
+ 2,
+ 2
+ ],
+ "badnets": [
+ ],
+ "badelements": [
+ ],
+ "pins": [
+ [
+ "VNB",
+ "DIODE",
+ "VPB",
+ "VGND",
+ "VPWR"
+ ], [
+ "VNB",
+ "DIODE",
+ "VPB",
+ "VGND",
+ "VPWR"
+ ]
+ ]
+ },
+ {
+ "name": [
+ "sky130_fd_sc_hd__and4_2",
+ "sky130_fd_sc_hd__and4_2"
+ ],
+ "devices": [
+ [
+ ["sky130_fd_pr__nfet_01v8", 5],
+ ["sky130_fd_pr__pfet_01v8_hvt", 5 ]
+ ], [
+ ["sky130_fd_pr__nfet_01v8", 5 ],
+ ["sky130_fd_pr__pfet_01v8_hvt", 5 ]
+ ]
+ ],
+ "nets": [
+ 13,
+ 13
+ ],
+ "badnets": [
+ ],
+ "badelements": [
+ ],
+ "pins": [
+ [
+ "VPWR",
+ "VPB",
+ "VNB",
+ "VGND",
+ "X",
+ "A",
+ "C",
+ "B",
+ "D"
+ ], [
+ "VPWR",
+ "VPB",
+ "VNB",
+ "VGND",
+ "X",
+ "A",
+ "C",
+ "B",
+ "D"
+ ]
+ ]
+ },
+ {
+ "name": [
+ "sky130_fd_sc_hd__decap_12",
+ "sky130_fd_sc_hd__decap_12"
+ ],
+ "devices": [
+ [
+ ["sky130_fd_pr__pfet_01v8_hvt", 1],
+ ["sky130_fd_pr__nfet_01v8", 1 ]
+ ], [
+ ["sky130_fd_pr__pfet_01v8_hvt", 1 ],
+ ["sky130_fd_pr__nfet_01v8", 1 ]
+ ]
+ ],
+ "nets": [
+ 4,
+ 4
+ ],
+ "badnets": [
+ ],
+ "badelements": [
+ ],
+ "pins": [
+ [
+ "VPB",
+ "VNB",
+ "VPWR",
+ "VGND"
+ ], [
+ "VPB",
+ "VNB",
+ "VPWR",
+ "VGND"
+ ]
+ ]
+ },
+ {
+ "name": [
+ "sky130_fd_sc_hd__inv_1",
+ "sky130_fd_sc_hd__inv_1"
+ ],
+ "devices": [
+ [
+ ["sky130_fd_pr__nfet_01v8", 1],
+ ["sky130_fd_pr__pfet_01v8_hvt", 1 ]
+ ], [
+ ["sky130_fd_pr__nfet_01v8", 1 ],
+ ["sky130_fd_pr__pfet_01v8_hvt", 1 ]
+ ]
+ ],
+ "nets": [
+ 6,
+ 6
+ ],
+ "badnets": [
+ ],
+ "badelements": [
+ ],
+ "pins": [
+ [
+ "VGND",
+ "VNB",
+ "VPWR",
+ "VPB",
+ "A",
+ "Y"
+ ], [
+ "VGND",
+ "VNB",
+ "VPWR",
+ "VPB",
+ "A",
+ "Y"
+ ]
+ ]
+ },
+ {
+ "name": [
+ "sky130_fd_sc_hd__dfxtp_1",
+ "sky130_fd_sc_hd__dfxtp_1"
+ ],
+ "devices": [
+ [
+ ["sky130_fd_pr__nfet_01v8", 12],
+ ["sky130_fd_pr__pfet_01v8_hvt", 12 ]
+ ], [
+ ["sky130_fd_pr__nfet_01v8", 12 ],
+ ["sky130_fd_pr__pfet_01v8_hvt", 12 ]
+ ]
+ ],
+ "nets": [
+ 18,
+ 18
+ ],
+ "badnets": [
+ ],
+ "badelements": [
+ ],
+ "pins": [
+ [
+ "VPB",
+ "VNB",
+ "VGND",
+ "VPWR",
+ "D",
+ "Q",
+ "CLK"
+ ], [
+ "VPB",
+ "VNB",
+ "VGND",
+ "VPWR",
+ "D",
+ "Q",
+ "CLK"
+ ]
+ ]
+ },
+ {
+ "name": [
+ "sky130_fd_sc_hd__mux4_1",
+ "sky130_fd_sc_hd__mux4_1"
+ ],
+ "devices": [
+ [
+ ["sky130_fd_pr__pfet_01v8_hvt", 13],
+ ["sky130_fd_pr__nfet_01v8", 13 ]
+ ], [
+ ["sky130_fd_pr__pfet_01v8_hvt", 13 ],
+ ["sky130_fd_pr__nfet_01v8", 13 ]
+ ]
+ ],
+ "nets": [
+ 24,
+ 24
+ ],
+ "badnets": [
+ ],
+ "badelements": [
+ ],
+ "pins": [
+ [
+ "S1",
+ "VPWR",
+ "VGND",
+ "VPB",
+ "VNB",
+ "X",
+ "A1",
+ "A3",
+ "A0",
+ "A2",
+ "S0"
+ ], [
+ "S1",
+ "VPWR",
+ "VGND",
+ "VPB",
+ "VNB",
+ "X",
+ "A1",
+ "A3",
+ "A0",
+ "A2",
+ "S0"
+ ]
+ ]
+ },
+ {
+ "name": [
+ "sky130_fd_sc_hd__clkbuf_4",
+ "sky130_fd_sc_hd__clkbuf_4"
+ ],
+ "devices": [
+ [
+ ["sky130_fd_pr__pfet_01v8_hvt", 2],
+ ["sky130_fd_pr__nfet_01v8", 2 ]
+ ], [
+ ["sky130_fd_pr__pfet_01v8_hvt", 2 ],
+ ["sky130_fd_pr__nfet_01v8", 2 ]
+ ]
+ ],
+ "nets": [
+ 7,
+ 7
+ ],
+ "badnets": [
+ ],
+ "badelements": [
+ ],
+ "pins": [
+ [
+ "VPWR",
+ "X",
+ "VPB",
+ "A",
+ "VGND",
+ "VNB"
+ ], [
+ "VPWR",
+ "X",
+ "VPB",
+ "A",
+ "VGND",
+ "VNB"
+ ]
+ ]
+ },
+ {
+ "name": [
+ "sky130_fd_sc_hd__and3b_2",
+ "sky130_fd_sc_hd__and3b_2"
+ ],
+ "devices": [
+ [
+ ["sky130_fd_pr__pfet_01v8_hvt", 5],
+ ["sky130_fd_pr__nfet_01v8", 5 ]
+ ], [
+ ["sky130_fd_pr__pfet_01v8_hvt", 5 ],
+ ["sky130_fd_pr__nfet_01v8", 5 ]
+ ]
+ ],
+ "nets": [
+ 12,
+ 12
+ ],
+ "badnets": [
+ ],
+ "badelements": [
+ ],
+ "pins": [
+ [
+ "VGND",
+ "VNB",
+ "VPWR",
+ "VPB",
+ "C",
+ "X",
+ "B",
+ "A_N"
+ ], [
+ "VGND",
+ "VNB",
+ "VPWR",
+ "VPB",
+ "C",
+ "X",
+ "B",
+ "A_N"
+ ]
+ ]
+ },
+ {
+ "name": [
+ "sky130_fd_sc_hd__clkbuf_16",
+ "sky130_fd_sc_hd__clkbuf_16"
+ ],
+ "devices": [
+ [
+ ["sky130_fd_pr__pfet_01v8_hvt", 2],
+ ["sky130_fd_pr__nfet_01v8", 2 ]
+ ], [
+ ["sky130_fd_pr__pfet_01v8_hvt", 2 ],
+ ["sky130_fd_pr__nfet_01v8", 2 ]
+ ]
+ ],
+ "nets": [
+ 7,
+ 7
+ ],
+ "badnets": [
+ ],
+ "badelements": [
+ ],
+ "pins": [
+ [
+ "VPWR",
+ "X",
+ "VPB",
+ "VGND",
+ "VNB",
+ "A"
+ ], [
+ "VPWR",
+ "X",
+ "VPB",
+ "VGND",
+ "VNB",
+ "A"
+ ]
+ ]
+ },
+ {
+ "name": [
+ "sky130_fd_sc_hd__decap_3",
+ "sky130_fd_sc_hd__decap_3"
+ ],
+ "devices": [
+ [
+ ["sky130_fd_pr__pfet_01v8_hvt", 1],
+ ["sky130_fd_pr__nfet_01v8", 1 ]
+ ], [
+ ["sky130_fd_pr__pfet_01v8_hvt", 1 ],
+ ["sky130_fd_pr__nfet_01v8", 1 ]
+ ]
+ ],
+ "nets": [
+ 4,
+ 4
+ ],
+ "badnets": [
+ ],
+ "badelements": [
+ ],
+ "pins": [
+ [
+ "VPB",
+ "VNB",
+ "VPWR",
+ "VGND"
+ ], [
+ "VPB",
+ "VNB",
+ "VPWR",
+ "VGND"
+ ]
+ ]
+ },
+ {
+ "name": [
+ "sky130_fd_sc_hd__clkbuf_2",
+ "sky130_fd_sc_hd__clkbuf_2"
+ ],
+ "devices": [
+ [
+ ["sky130_fd_pr__pfet_01v8_hvt", 2],
+ ["sky130_fd_pr__nfet_01v8", 2 ]
+ ], [
+ ["sky130_fd_pr__pfet_01v8_hvt", 2 ],
+ ["sky130_fd_pr__nfet_01v8", 2 ]
+ ]
+ ],
+ "nets": [
+ 7,
+ 7
+ ],
+ "badnets": [
+ ],
+ "badelements": [
+ ],
+ "pins": [
+ [
+ "A",
+ "VPWR",
+ "VPB",
+ "VGND",
+ "VNB",
+ "X"
+ ], [
+ "A",
+ "VPWR",
+ "VPB",
+ "VGND",
+ "VNB",
+ "X"
+ ]
+ ]
+ },
+ {
+ "name": [
+ "sky130_fd_sc_hd__and4bb_2",
+ "sky130_fd_sc_hd__and4bb_2"
+ ],
+ "devices": [
+ [
+ ["sky130_fd_pr__pfet_01v8_hvt", 7],
+ ["sky130_fd_pr__nfet_01v8", 7 ]
+ ], [
+ ["sky130_fd_pr__pfet_01v8_hvt", 7 ],
+ ["sky130_fd_pr__nfet_01v8", 7 ]
+ ]
+ ],
+ "nets": [
+ 15,
+ 15
+ ],
+ "badnets": [
+ ],
+ "badelements": [
+ ],
+ "pins": [
+ [
+ "VGND",
+ "X",
+ "D",
+ "C",
+ "B_N",
+ "A_N",
+ "VNB",
+ "VPWR",
+ "VPB"
+ ], [
+ "VGND",
+ "X",
+ "D",
+ "C",
+ "B_N",
+ "A_N",
+ "VNB",
+ "VPWR",
+ "VPB"
+ ]
+ ]
+ },
+ {
+ "name": [
+ "sky130_fd_sc_hd__decap_8",
+ "sky130_fd_sc_hd__decap_8"
+ ],
+ "devices": [
+ [
+ ["sky130_fd_pr__pfet_01v8_hvt", 1],
+ ["sky130_fd_pr__nfet_01v8", 1 ]
+ ], [
+ ["sky130_fd_pr__pfet_01v8_hvt", 1 ],
+ ["sky130_fd_pr__nfet_01v8", 1 ]
+ ]
+ ],
+ "nets": [
+ 4,
+ 4
+ ],
+ "badnets": [
+ ],
+ "badelements": [
+ ],
+ "pins": [
+ [
+ "VPB",
+ "VNB",
+ "VPWR",
+ "VGND"
+ ], [
+ "VPB",
+ "VNB",
+ "VPWR",
+ "VGND"
+ ]
+ ]
+ },
+ {
+ "name": [
+ "sky130_fd_sc_hd__nor4b_2",
+ "sky130_fd_sc_hd__nor4b_2"
+ ],
+ "devices": [
+ [
+ ["sky130_fd_pr__pfet_01v8_hvt", 5],
+ ["sky130_fd_pr__nfet_01v8", 5 ]
+ ], [
+ ["sky130_fd_pr__pfet_01v8_hvt", 5 ],
+ ["sky130_fd_pr__nfet_01v8", 5 ]
+ ]
+ ],
+ "nets": [
+ 13,
+ 13
+ ],
+ "badnets": [
+ ],
+ "badelements": [
+ ],
+ "pins": [
+ [
+ "VPB",
+ "Y",
+ "VGND",
+ "VNB",
+ "D_N",
+ "VPWR",
+ "A",
+ "C",
+ "B"
+ ], [
+ "VPB",
+ "Y",
+ "VGND",
+ "VNB",
+ "D_N",
+ "VPWR",
+ "A",
+ "C",
+ "B"
+ ]
+ ]
+ },
+ {
+ "name": [
+ "sky130_fd_sc_hd__and4b_2",
+ "sky130_fd_sc_hd__and4b_2"
+ ],
+ "devices": [
+ [
+ ["sky130_fd_pr__pfet_01v8_hvt", 6],
+ ["sky130_fd_pr__nfet_01v8", 6 ]
+ ], [
+ ["sky130_fd_pr__pfet_01v8_hvt", 6 ],
+ ["sky130_fd_pr__nfet_01v8", 6 ]
+ ]
+ ],
+ "nets": [
+ 14,
+ 14
+ ],
+ "badnets": [
+ ],
+ "badelements": [
+ ],
+ "pins": [
+ [
+ "VGND",
+ "X",
+ "D",
+ "A_N",
+ "C",
+ "B",
+ "VPWR",
+ "VPB",
+ "VNB"
+ ], [
+ "VGND",
+ "X",
+ "D",
+ "A_N",
+ "C",
+ "B",
+ "VPWR",
+ "VPB",
+ "VNB"
+ ]
+ ]
+ },
+ {
+ "name": [
+ "sky130_fd_sc_hd__decap_4",
+ "sky130_fd_sc_hd__decap_4"
+ ],
+ "devices": [
+ [
+ ["sky130_fd_pr__pfet_01v8_hvt", 1],
+ ["sky130_fd_pr__nfet_01v8", 1 ]
+ ], [
+ ["sky130_fd_pr__pfet_01v8_hvt", 1 ],
+ ["sky130_fd_pr__nfet_01v8", 1 ]
+ ]
+ ],
+ "nets": [
+ 4,
+ 4
+ ],
+ "badnets": [
+ ],
+ "badelements": [
+ ],
+ "pins": [
+ [
+ "VPB",
+ "VNB",
+ "VPWR",
+ "VGND"
+ ], [
+ "VPB",
+ "VNB",
+ "VPWR",
+ "VGND"
+ ]
+ ]
+ },
+ {
+ "name": [
+ "sky130_fd_sc_hd__and3_2",
+ "sky130_fd_sc_hd__and3_2"
+ ],
+ "devices": [
+ [
+ ["sky130_fd_pr__pfet_01v8_hvt", 4],
+ ["sky130_fd_pr__nfet_01v8", 4 ]
+ ], [
+ ["sky130_fd_pr__pfet_01v8_hvt", 4 ],
+ ["sky130_fd_pr__nfet_01v8", 4 ]
+ ]
+ ],
+ "nets": [
+ 11,
+ 11
+ ],
+ "badnets": [
+ ],
+ "badelements": [
+ ],
+ "pins": [
+ [
+ "X",
+ "VGND",
+ "A",
+ "C",
+ "B",
+ "VNB",
+ "VPWR",
+ "VPB"
+ ], [
+ "X",
+ "VGND",
+ "A",
+ "C",
+ "B",
+ "VNB",
+ "VPWR",
+ "VPB"
+ ]
+ ]
+ },
+ {
+ "name": [
+ "sky130_fd_sc_hd__decap_6",
+ "sky130_fd_sc_hd__decap_6"
+ ],
+ "devices": [
+ [
+ ["sky130_fd_pr__pfet_01v8_hvt", 1],
+ ["sky130_fd_pr__nfet_01v8", 1 ]
+ ], [
+ ["sky130_fd_pr__pfet_01v8_hvt", 1 ],
+ ["sky130_fd_pr__nfet_01v8", 1 ]
+ ]
+ ],
+ "nets": [
+ 4,
+ 4
+ ],
+ "badnets": [
+ ],
+ "badelements": [
+ ],
+ "pins": [
+ [
+ "VPB",
+ "VNB",
+ "VPWR",
+ "VGND"
+ ], [
+ "VPB",
+ "VNB",
+ "VPWR",
+ "VGND"
+ ]
+ ]
+ },
+ {
+ "name": [
+ "sky130_fd_sc_hd__mux2_1",
+ "sky130_fd_sc_hd__mux2_1"
+ ],
+ "devices": [
+ [
+ ["sky130_fd_pr__pfet_01v8_hvt", 6],
+ ["sky130_fd_pr__nfet_01v8", 6 ]
+ ], [
+ ["sky130_fd_pr__pfet_01v8_hvt", 6 ],
+ ["sky130_fd_pr__nfet_01v8", 6 ]
+ ]
+ ],
+ "nets": [
+ 14,
+ 14
+ ],
+ "badnets": [
+ ],
+ "badelements": [
+ ],
+ "pins": [
+ [
+ "VPB",
+ "VNB",
+ "A0",
+ "A1",
+ "X",
+ "VPWR",
+ "S",
+ "VGND"
+ ], [
+ "VPB",
+ "VNB",
+ "A0",
+ "A1",
+ "X",
+ "VPWR",
+ "S",
+ "VGND"
+ ]
+ ]
+ },
+ {
+ "name": [
+ "sky130_fd_sc_hd__conb_1",
+ "sky130_fd_sc_hd__conb_1"
+ ],
+ "devices": [
+ [
+ ["sky130_fd_pr__res_generic_po", 2 ]
+ ], [
+ ["sky130_fd_pr__res_generic_po", 2 ]
+ ]
+ ],
+ "nets": [
+ 4,
+ 4
+ ],
+ "badnets": [
+ ],
+ "badelements": [
+ ],
+ "pins": [
+ [
+ "VGND",
+ "LO",
+ "HI",
+ "VPWR",
+ "VNB",
+ "VPB"
+ ], [
+ "VGND",
+ "LO",
+ "HI",
+ "VPWR",
+ "VNB",
+ "VPB"
+ ]
+ ]
+ },
+ {
+ "name": [
+ "sky130_fd_sc_hd__nor3b_2",
+ "sky130_fd_sc_hd__nor3b_2"
+ ],
+ "devices": [
+ [
+ ["sky130_fd_pr__pfet_01v8_hvt", 4],
+ ["sky130_fd_pr__nfet_01v8", 4 ]
+ ], [
+ ["sky130_fd_pr__pfet_01v8_hvt", 4 ],
+ ["sky130_fd_pr__nfet_01v8", 4 ]
+ ]
+ ],
+ "nets": [
+ 11,
+ 11
+ ],
+ "badnets": [
+ ],
+ "badelements": [
+ ],
+ "pins": [
+ [
+ "Y",
+ "VGND",
+ "VNB",
+ "VPB",
+ "VPWR",
+ "A",
+ "B",
+ "C_N"
+ ], [
+ "Y",
+ "VGND",
+ "VNB",
+ "VPB",
+ "VPWR",
+ "A",
+ "B",
+ "C_N"
+ ]
+ ]
+ },
+ {
+ "name": [
+ "sky130_fd_sc_hd__and2b_2",
+ "sky130_fd_sc_hd__and2b_2"
+ ],
+ "devices": [
+ [
+ ["sky130_fd_pr__pfet_01v8_hvt", 4],
+ ["sky130_fd_pr__nfet_01v8", 4 ]
+ ], [
+ ["sky130_fd_pr__pfet_01v8_hvt", 4 ],
+ ["sky130_fd_pr__nfet_01v8", 4 ]
+ ]
+ ],
+ "nets": [
+ 10,
+ 10
+ ],
+ "badnets": [
+ ],
+ "badelements": [
+ ],
+ "pins": [
+ [
+ "VGND",
+ "X",
+ "B",
+ "A_N",
+ "VPWR",
+ "VPB",
+ "VNB"
+ ], [
+ "VGND",
+ "X",
+ "B",
+ "A_N",
+ "VPWR",
+ "VPB",
+ "VNB"
+ ]
+ ]
+ },
+ {
+ "name": [
+ "sky130_fd_sc_hd__and2_2",
+ "sky130_fd_sc_hd__and2_2"
+ ],
+ "devices": [
+ [
+ ["sky130_fd_pr__pfet_01v8_hvt", 3],
+ ["sky130_fd_pr__nfet_01v8", 3 ]
+ ], [
+ ["sky130_fd_pr__pfet_01v8_hvt", 3 ],
+ ["sky130_fd_pr__nfet_01v8", 3 ]
+ ]
+ ],
+ "nets": [
+ 9,
+ 9
+ ],
+ "badnets": [
+ ],
+ "badelements": [
+ ],
+ "pins": [
+ [
+ "VPWR",
+ "VPB",
+ "VNB",
+ "X",
+ "A",
+ "B",
+ "VGND"
+ ], [
+ "VPWR",
+ "VPB",
+ "VNB",
+ "X",
+ "A",
+ "B",
+ "VGND"
+ ]
+ ]
+ },
+ {
+ "name": [
+ "RAM256",
+ "RAM256"
+ ],
+ "devices": [
+ [
+ ["sky130_fd_sc_hd__and2_1", 1024],
+ ["sky130_fd_sc_hd__dlxtp_1", 8192],
+ ["sky130_fd_sc_hd__ebufn_2", 8448],
+ ["sky130_fd_sc_hd__dlclkp_1", 1024],
+ ["sky130_fd_sc_hd__diode_2", 836],
+ ["sky130_fd_sc_hd__and4_2", 32],
+ ["sky130_fd_sc_hd__decap_12", 1],
+ ["sky130_fd_sc_hd__inv_1", 2048],
+ ["sky130_fd_sc_hd__dfxtp_1", 256],
+ ["sky130_fd_sc_hd__mux4_1", 64],
+ ["sky130_fd_sc_hd__clkbuf_4", 306],
+ ["sky130_fd_sc_hd__and3b_2", 20],
+ ["sky130_fd_sc_hd__clkbuf_16", 320],
+ ["sky130_fd_sc_hd__decap_3", 1],
+ ["sky130_fd_sc_hd__clkbuf_2", 700],
+ ["sky130_fd_sc_hd__and4bb_2", 96],
+ ["sky130_fd_sc_hd__decap_8", 1],
+ ["sky130_fd_sc_hd__nor4b_2", 32],
+ ["sky130_fd_sc_hd__and4b_2", 96],
+ ["sky130_fd_sc_hd__decap_4", 1],
+ ["sky130_fd_sc_hd__and3_2", 10],
+ ["sky130_fd_sc_hd__decap_6", 1],
+ ["sky130_fd_sc_hd__mux2_1", 32],
+ ["sky130_fd_sc_hd__conb_1", 32],
+ ["sky130_fd_sc_hd__nor3b_2", 10],
+ ["sky130_fd_sc_hd__and2b_2", 1],
+ ["sky130_fd_sc_hd__and2_2", 1 ]
+ ], [
+ ["sky130_fd_sc_hd__and2_1", 1024 ],
+ ["sky130_fd_sc_hd__dlxtp_1", 8192 ],
+ ["sky130_fd_sc_hd__ebufn_2", 8448 ],
+ ["sky130_fd_sc_hd__dlclkp_1", 1024 ],
+ ["sky130_fd_sc_hd__diode_2", 836 ],
+ ["sky130_fd_sc_hd__and4_2", 32 ],
+ ["sky130_fd_sc_hd__decap_12", 1 ],
+ ["sky130_fd_sc_hd__inv_1", 2048 ],
+ ["sky130_fd_sc_hd__dfxtp_1", 256 ],
+ ["sky130_fd_sc_hd__mux4_1", 64 ],
+ ["sky130_fd_sc_hd__clkbuf_4", 306 ],
+ ["sky130_fd_sc_hd__and3b_2", 20 ],
+ ["sky130_fd_sc_hd__clkbuf_16", 320 ],
+ ["sky130_fd_sc_hd__decap_3", 1 ],
+ ["sky130_fd_sc_hd__clkbuf_2", 700 ],
+ ["sky130_fd_sc_hd__and4bb_2", 96 ],
+ ["sky130_fd_sc_hd__decap_8", 1 ],
+ ["sky130_fd_sc_hd__nor4b_2", 32 ],
+ ["sky130_fd_sc_hd__and4b_2", 96 ],
+ ["sky130_fd_sc_hd__decap_4", 1 ],
+ ["sky130_fd_sc_hd__and3_2", 10 ],
+ ["sky130_fd_sc_hd__decap_6", 1 ],
+ ["sky130_fd_sc_hd__mux2_1", 32 ],
+ ["sky130_fd_sc_hd__conb_1", 32 ],
+ ["sky130_fd_sc_hd__nor3b_2", 10 ],
+ ["sky130_fd_sc_hd__and2b_2", 1 ],
+ ["sky130_fd_sc_hd__and2_2", 1 ]
+ ]
+ ],
+ "nets": [
+ 14632,
+ 14632
+ ],
+ "badnets": [
+ ],
+ "badelements": [
+ ],
+ "pins": [
+ [
+ "Do0[0]",
+ "Do0[1]",
+ "Do0[2]",
+ "Do0[3]",
+ "Do0[4]",
+ "Do0[5]",
+ "Do0[6]",
+ "Do0[7]",
+ "Do0[8]",
+ "Do0[9]",
+ "Do0[10]",
+ "Do0[11]",
+ "Do0[12]",
+ "Do0[13]",
+ "Do0[14]",
+ "Do0[15]",
+ "Do0[16]",
+ "Do0[17]",
+ "Do0[18]",
+ "Do0[19]",
+ "Do0[20]",
+ "Do0[21]",
+ "Do0[22]",
+ "Do0[23]",
+ "Do0[24]",
+ "Do0[25]",
+ "Do0[26]",
+ "Do0[27]",
+ "Do0[28]",
+ "Do0[29]",
+ "Do0[30]",
+ "Do0[31]",
+ "A0[7]",
+ "VGND",
+ "VPWR",
+ "A0[6]",
+ "A0[5]",
+ "CLK",
+ "Di0[0]",
+ "Di0[10]",
+ "Di0[11]",
+ "Di0[12]",
+ "Di0[13]",
+ "Di0[14]",
+ "Di0[15]",
+ "Di0[16]",
+ "Di0[17]",
+ "Di0[18]",
+ "Di0[19]",
+ "Di0[1]",
+ "Di0[20]",
+ "Di0[21]",
+ "Di0[22]",
+ "Di0[23]",
+ "Di0[24]",
+ "Di0[25]",
+ "Di0[26]",
+ "Di0[27]",
+ "Di0[28]",
+ "Di0[29]",
+ "Di0[2]",
+ "Di0[30]",
+ "Di0[31]",
+ "Di0[3]",
+ "Di0[4]",
+ "Di0[5]",
+ "Di0[6]",
+ "Di0[7]",
+ "Di0[8]",
+ "Di0[9]",
+ "A0[3]",
+ "A0[4]",
+ "A0[0]",
+ "A0[1]",
+ "A0[2]",
+ "WE0[0]",
+ "WE0[1]",
+ "WE0[2]",
+ "WE0[3]",
+ "EN0"
+ ], [
+ "Do0[0]",
+ "Do0[1]",
+ "Do0[2]",
+ "Do0[3]",
+ "Do0[4]",
+ "Do0[5]",
+ "Do0[6]",
+ "Do0[7]",
+ "Do0[8]",
+ "Do0[9]",
+ "Do0[10]",
+ "Do0[11]",
+ "Do0[12]",
+ "Do0[13]",
+ "Do0[14]",
+ "Do0[15]",
+ "Do0[16]",
+ "Do0[17]",
+ "Do0[18]",
+ "Do0[19]",
+ "Do0[20]",
+ "Do0[21]",
+ "Do0[22]",
+ "Do0[23]",
+ "Do0[24]",
+ "Do0[25]",
+ "Do0[26]",
+ "Do0[27]",
+ "Do0[28]",
+ "Do0[29]",
+ "Do0[30]",
+ "Do0[31]",
+ "A0[7]",
+ "VGND",
+ "VPWR",
+ "A0[6]",
+ "A0[5]",
+ "CLK",
+ "Di0[0]",
+ "Di0[10]",
+ "Di0[11]",
+ "Di0[12]",
+ "Di0[13]",
+ "Di0[14]",
+ "Di0[15]",
+ "Di0[16]",
+ "Di0[17]",
+ "Di0[18]",
+ "Di0[19]",
+ "Di0[1]",
+ "Di0[20]",
+ "Di0[21]",
+ "Di0[22]",
+ "Di0[23]",
+ "Di0[24]",
+ "Di0[25]",
+ "Di0[26]",
+ "Di0[27]",
+ "Di0[28]",
+ "Di0[29]",
+ "Di0[2]",
+ "Di0[30]",
+ "Di0[31]",
+ "Di0[3]",
+ "Di0[4]",
+ "Di0[5]",
+ "Di0[6]",
+ "Di0[7]",
+ "Di0[8]",
+ "Di0[9]",
+ "A0[3]",
+ "A0[4]",
+ "A0[0]",
+ "A0[1]",
+ "A0[2]",
+ "WE0[0]",
+ "WE0[1]",
+ "WE0[2]",
+ "WE0[3]",
+ "EN0"
+ ]
+ ]
+ }
+]
diff --git a/signoff/RAM256/standalone_pvr/eco-RAM256.lvs.report b/signoff/RAM256/standalone_pvr/eco-RAM256.lvs.report
new file mode 100644
index 0000000..eb85daa
--- /dev/null
+++ b/signoff/RAM256/standalone_pvr/eco-RAM256.lvs.report
@@ -0,0 +1,833 @@
+
+Circuit 1 cell sky130_fd_pr__pfet_01v8_hvt and Circuit 2 cell sky130_fd_pr__pfet_01v8_hvt are black boxes.
+
+Subcircuit pins:
+Circuit 1: sky130_fd_pr__pfet_01v8_hvt |Circuit 2: sky130_fd_pr__pfet_01v8_hvt
+-------------------------------------------|-------------------------------------------
+1 |1
+2 |2
+3 |3
+4 |4
+---------------------------------------------------------------------------------------
+Cell pin lists are equivalent.
+Device classes sky130_fd_pr__pfet_01v8_hvt and sky130_fd_pr__pfet_01v8_hvt are equivalent.
+
+Circuit 1 cell sky130_fd_pr__nfet_01v8 and Circuit 2 cell sky130_fd_pr__nfet_01v8 are black boxes.
+
+Subcircuit pins:
+Circuit 1: sky130_fd_pr__nfet_01v8 |Circuit 2: sky130_fd_pr__nfet_01v8
+-------------------------------------------|-------------------------------------------
+1 |1
+2 |2
+3 |3
+4 |4
+---------------------------------------------------------------------------------------
+Cell pin lists are equivalent.
+Device classes sky130_fd_pr__nfet_01v8 and sky130_fd_pr__nfet_01v8 are equivalent.
+
+Subcircuit summary:
+Circuit 1: sky130_fd_sc_hd__and2_1 |Circuit 2: sky130_fd_sc_hd__and2_1
+-------------------------------------------|-------------------------------------------
+sky130_fd_pr__pfet_01v8_hvt (3) |sky130_fd_pr__pfet_01v8_hvt (3)
+sky130_fd_pr__nfet_01v8 (3) |sky130_fd_pr__nfet_01v8 (3)
+Number of devices: 6 |Number of devices: 6
+Number of nets: 9 |Number of nets: 9
+---------------------------------------------------------------------------------------
+Netlists match uniquely.
+
+Subcircuit pins:
+Circuit 1: sky130_fd_sc_hd__and2_1 |Circuit 2: sky130_fd_sc_hd__and2_1
+-------------------------------------------|-------------------------------------------
+VGND |VGND
+X |X
+A |A
+B |B
+VNB |VNB
+VPWR |VPWR
+VPB |VPB
+---------------------------------------------------------------------------------------
+Cell pin lists are equivalent.
+Device classes sky130_fd_sc_hd__and2_1 and sky130_fd_sc_hd__and2_1 are equivalent.
+
+Subcircuit summary:
+Circuit 1: sky130_fd_sc_hd__dlxtp_1 |Circuit 2: sky130_fd_sc_hd__dlxtp_1
+-------------------------------------------|-------------------------------------------
+sky130_fd_pr__nfet_01v8 (9) |sky130_fd_pr__nfet_01v8 (9)
+sky130_fd_pr__pfet_01v8_hvt (9) |sky130_fd_pr__pfet_01v8_hvt (9)
+Number of devices: 18 |Number of devices: 18
+Number of nets: 16 |Number of nets: 16
+---------------------------------------------------------------------------------------
+Netlists match uniquely.
+
+Subcircuit pins:
+Circuit 1: sky130_fd_sc_hd__dlxtp_1 |Circuit 2: sky130_fd_sc_hd__dlxtp_1
+-------------------------------------------|-------------------------------------------
+VPWR |VPWR
+VGND |VGND
+VPB |VPB
+VNB |VNB
+D |D
+Q |Q
+GATE |GATE
+---------------------------------------------------------------------------------------
+Cell pin lists are equivalent.
+Device classes sky130_fd_sc_hd__dlxtp_1 and sky130_fd_sc_hd__dlxtp_1 are equivalent.
+
+Class sky130_fd_sc_hd__ebufn_2 (0): Merged 4 parallel devices.
+Class sky130_fd_sc_hd__ebufn_2 (1): Merged 4 parallel devices.
+Subcircuit summary:
+Circuit 1: sky130_fd_sc_hd__ebufn_2 |Circuit 2: sky130_fd_sc_hd__ebufn_2
+-------------------------------------------|-------------------------------------------
+sky130_fd_pr__pfet_01v8_hvt (6->4) |sky130_fd_pr__pfet_01v8_hvt (6->4)
+sky130_fd_pr__nfet_01v8 (6->4) |sky130_fd_pr__nfet_01v8 (6->4)
+Number of devices: 8 |Number of devices: 8
+Number of nets: 11 |Number of nets: 11
+---------------------------------------------------------------------------------------
+Netlists match uniquely.
+
+Subcircuit pins:
+Circuit 1: sky130_fd_sc_hd__ebufn_2 |Circuit 2: sky130_fd_sc_hd__ebufn_2
+-------------------------------------------|-------------------------------------------
+VGND |VGND
+TE_B |TE_B
+VPWR |VPWR
+VNB |VNB
+VPB |VPB
+Z |Z
+A |A
+---------------------------------------------------------------------------------------
+Cell pin lists are equivalent.
+Device classes sky130_fd_sc_hd__ebufn_2 and sky130_fd_sc_hd__ebufn_2 are equivalent.
+
+Subcircuit summary:
+Circuit 1: sky130_fd_sc_hd__dlclkp_1 |Circuit 2: sky130_fd_sc_hd__dlclkp_1
+-------------------------------------------|-------------------------------------------
+sky130_fd_pr__pfet_01v8_hvt (10) |sky130_fd_pr__pfet_01v8_hvt (10)
+sky130_fd_pr__nfet_01v8 (10) |sky130_fd_pr__nfet_01v8 (10)
+Number of devices: 20 |Number of devices: 20
+Number of nets: 17 |Number of nets: 17
+---------------------------------------------------------------------------------------
+Netlists match uniquely.
+
+Subcircuit pins:
+Circuit 1: sky130_fd_sc_hd__dlclkp_1 |Circuit 2: sky130_fd_sc_hd__dlclkp_1
+-------------------------------------------|-------------------------------------------
+VGND |VGND
+CLK |CLK
+VPB |VPB
+VNB |VNB
+VPWR |VPWR
+GCLK |GCLK
+GATE |GATE
+---------------------------------------------------------------------------------------
+Cell pin lists are equivalent.
+Device classes sky130_fd_sc_hd__dlclkp_1 and sky130_fd_sc_hd__dlclkp_1 are equivalent.
+
+Cell sky130_fd_sc_hd__diode_2 (0) disconnected node: VPB
+Cell sky130_fd_sc_hd__diode_2 (0) disconnected node: VGND
+Cell sky130_fd_sc_hd__diode_2 (0) disconnected node: VPWR
+Cell sky130_fd_sc_hd__diode_2 (1) disconnected node: VGND
+Cell sky130_fd_sc_hd__diode_2 (1) disconnected node: VPB
+Cell sky130_fd_sc_hd__diode_2 (1) disconnected node: VPWR
+Subcircuit summary:
+Circuit 1: sky130_fd_sc_hd__diode_2 |Circuit 2: sky130_fd_sc_hd__diode_2
+-------------------------------------------|-------------------------------------------
+sky130_fd_pr__diode_pw2nd_05v5 (1) |sky130_fd_pr__diode_pw2nd_05v5 (1)
+Number of devices: 1 |Number of devices: 1
+Number of nets: 2 |Number of nets: 2
+---------------------------------------------------------------------------------------
+Netlists match uniquely.
+
+Subcircuit pins:
+Circuit 1: sky130_fd_sc_hd__diode_2 |Circuit 2: sky130_fd_sc_hd__diode_2
+-------------------------------------------|-------------------------------------------
+VNB |VNB
+DIODE |DIODE
+VPB |VPB
+VGND |VGND
+VPWR |VPWR
+---------------------------------------------------------------------------------------
+Cell pin lists are equivalent.
+Device classes sky130_fd_sc_hd__diode_2 and sky130_fd_sc_hd__diode_2 are equivalent.
+
+Class sky130_fd_sc_hd__and4_2 (0): Merged 2 parallel devices.
+Class sky130_fd_sc_hd__and4_2 (1): Merged 2 parallel devices.
+Subcircuit summary:
+Circuit 1: sky130_fd_sc_hd__and4_2 |Circuit 2: sky130_fd_sc_hd__and4_2
+-------------------------------------------|-------------------------------------------
+sky130_fd_pr__nfet_01v8 (6->5) |sky130_fd_pr__nfet_01v8 (6->5)
+sky130_fd_pr__pfet_01v8_hvt (6->5) |sky130_fd_pr__pfet_01v8_hvt (6->5)
+Number of devices: 10 |Number of devices: 10
+Number of nets: 13 |Number of nets: 13
+---------------------------------------------------------------------------------------
+Netlists match uniquely.
+
+Subcircuit pins:
+Circuit 1: sky130_fd_sc_hd__and4_2 |Circuit 2: sky130_fd_sc_hd__and4_2
+-------------------------------------------|-------------------------------------------
+VPWR |VPWR
+VPB |VPB
+VNB |VNB
+VGND |VGND
+X |X
+A |A
+C |C
+B |B
+D |D
+---------------------------------------------------------------------------------------
+Cell pin lists are equivalent.
+Device classes sky130_fd_sc_hd__and4_2 and sky130_fd_sc_hd__and4_2 are equivalent.
+
+Subcircuit summary:
+Circuit 1: sky130_fd_sc_hd__decap_12 |Circuit 2: sky130_fd_sc_hd__decap_12
+-------------------------------------------|-------------------------------------------
+sky130_fd_pr__pfet_01v8_hvt (1) |sky130_fd_pr__pfet_01v8_hvt (1)
+sky130_fd_pr__nfet_01v8 (1) |sky130_fd_pr__nfet_01v8 (1)
+Number of devices: 2 |Number of devices: 2
+Number of nets: 4 |Number of nets: 4
+---------------------------------------------------------------------------------------
+Netlists match uniquely.
+
+Subcircuit pins:
+Circuit 1: sky130_fd_sc_hd__decap_12 |Circuit 2: sky130_fd_sc_hd__decap_12
+-------------------------------------------|-------------------------------------------
+VPB |VPB
+VNB |VNB
+VPWR |VPWR
+VGND |VGND
+---------------------------------------------------------------------------------------
+Cell pin lists are equivalent.
+Device classes sky130_fd_sc_hd__decap_12 and sky130_fd_sc_hd__decap_12 are equivalent.
+
+Subcircuit summary:
+Circuit 1: sky130_fd_sc_hd__inv_1 |Circuit 2: sky130_fd_sc_hd__inv_1
+-------------------------------------------|-------------------------------------------
+sky130_fd_pr__nfet_01v8 (1) |sky130_fd_pr__nfet_01v8 (1)
+sky130_fd_pr__pfet_01v8_hvt (1) |sky130_fd_pr__pfet_01v8_hvt (1)
+Number of devices: 2 |Number of devices: 2
+Number of nets: 6 |Number of nets: 6
+---------------------------------------------------------------------------------------
+Netlists match uniquely.
+
+Subcircuit pins:
+Circuit 1: sky130_fd_sc_hd__inv_1 |Circuit 2: sky130_fd_sc_hd__inv_1
+-------------------------------------------|-------------------------------------------
+VGND |VGND
+VNB |VNB
+VPWR |VPWR
+VPB |VPB
+A |A
+Y |Y
+---------------------------------------------------------------------------------------
+Cell pin lists are equivalent.
+Device classes sky130_fd_sc_hd__inv_1 and sky130_fd_sc_hd__inv_1 are equivalent.
+
+Subcircuit summary:
+Circuit 1: sky130_fd_sc_hd__dfxtp_1 |Circuit 2: sky130_fd_sc_hd__dfxtp_1
+-------------------------------------------|-------------------------------------------
+sky130_fd_pr__nfet_01v8 (12) |sky130_fd_pr__nfet_01v8 (12)
+sky130_fd_pr__pfet_01v8_hvt (12) |sky130_fd_pr__pfet_01v8_hvt (12)
+Number of devices: 24 |Number of devices: 24
+Number of nets: 18 |Number of nets: 18
+---------------------------------------------------------------------------------------
+Netlists match uniquely.
+
+Subcircuit pins:
+Circuit 1: sky130_fd_sc_hd__dfxtp_1 |Circuit 2: sky130_fd_sc_hd__dfxtp_1
+-------------------------------------------|-------------------------------------------
+VPB |VPB
+VNB |VNB
+VGND |VGND
+VPWR |VPWR
+D |D
+Q |Q
+CLK |CLK
+---------------------------------------------------------------------------------------
+Cell pin lists are equivalent.
+Device classes sky130_fd_sc_hd__dfxtp_1 and sky130_fd_sc_hd__dfxtp_1 are equivalent.
+
+Subcircuit summary:
+Circuit 1: sky130_fd_sc_hd__mux4_1 |Circuit 2: sky130_fd_sc_hd__mux4_1
+-------------------------------------------|-------------------------------------------
+sky130_fd_pr__pfet_01v8_hvt (13) |sky130_fd_pr__pfet_01v8_hvt (13)
+sky130_fd_pr__nfet_01v8 (13) |sky130_fd_pr__nfet_01v8 (13)
+Number of devices: 26 |Number of devices: 26
+Number of nets: 24 |Number of nets: 24
+---------------------------------------------------------------------------------------
+Netlists match uniquely.
+
+Subcircuit pins:
+Circuit 1: sky130_fd_sc_hd__mux4_1 |Circuit 2: sky130_fd_sc_hd__mux4_1
+-------------------------------------------|-------------------------------------------
+S1 |S1
+VPWR |VPWR
+VGND |VGND
+VPB |VPB
+VNB |VNB
+X |X
+A1 |A1
+A3 |A3
+A0 |A0
+A2 |A2
+S0 |S0
+---------------------------------------------------------------------------------------
+Cell pin lists are equivalent.
+Device classes sky130_fd_sc_hd__mux4_1 and sky130_fd_sc_hd__mux4_1 are equivalent.
+
+Class sky130_fd_sc_hd__clkbuf_4 (0): Merged 6 parallel devices.
+Class sky130_fd_sc_hd__clkbuf_4 (1): Merged 6 parallel devices.
+Subcircuit summary:
+Circuit 1: sky130_fd_sc_hd__clkbuf_4 |Circuit 2: sky130_fd_sc_hd__clkbuf_4
+-------------------------------------------|-------------------------------------------
+sky130_fd_pr__pfet_01v8_hvt (5->2) |sky130_fd_pr__pfet_01v8_hvt (5->2)
+sky130_fd_pr__nfet_01v8 (5->2) |sky130_fd_pr__nfet_01v8 (5->2)
+Number of devices: 4 |Number of devices: 4
+Number of nets: 7 |Number of nets: 7
+---------------------------------------------------------------------------------------
+Netlists match uniquely.
+
+Subcircuit pins:
+Circuit 1: sky130_fd_sc_hd__clkbuf_4 |Circuit 2: sky130_fd_sc_hd__clkbuf_4
+-------------------------------------------|-------------------------------------------
+VPWR |VPWR
+X |X
+VPB |VPB
+A |A
+VGND |VGND
+VNB |VNB
+---------------------------------------------------------------------------------------
+Cell pin lists are equivalent.
+Device classes sky130_fd_sc_hd__clkbuf_4 and sky130_fd_sc_hd__clkbuf_4 are equivalent.
+
+Class sky130_fd_sc_hd__and3b_2 (0): Merged 2 parallel devices.
+Class sky130_fd_sc_hd__and3b_2 (1): Merged 2 parallel devices.
+Subcircuit summary:
+Circuit 1: sky130_fd_sc_hd__and3b_2 |Circuit 2: sky130_fd_sc_hd__and3b_2
+-------------------------------------------|-------------------------------------------
+sky130_fd_pr__pfet_01v8_hvt (6->5) |sky130_fd_pr__pfet_01v8_hvt (6->5)
+sky130_fd_pr__nfet_01v8 (6->5) |sky130_fd_pr__nfet_01v8 (6->5)
+Number of devices: 10 |Number of devices: 10
+Number of nets: 12 |Number of nets: 12
+---------------------------------------------------------------------------------------
+Netlists match uniquely.
+
+Subcircuit pins:
+Circuit 1: sky130_fd_sc_hd__and3b_2 |Circuit 2: sky130_fd_sc_hd__and3b_2
+-------------------------------------------|-------------------------------------------
+VGND |VGND
+VNB |VNB
+VPWR |VPWR
+VPB |VPB
+C |C
+X |X
+B |B
+A_N |A_N
+---------------------------------------------------------------------------------------
+Cell pin lists are equivalent.
+Device classes sky130_fd_sc_hd__and3b_2 and sky130_fd_sc_hd__and3b_2 are equivalent.
+
+Class sky130_fd_sc_hd__clkbuf_16 (0): Merged 36 parallel devices.
+Class sky130_fd_sc_hd__clkbuf_16 (1): Merged 36 parallel devices.
+Subcircuit summary:
+Circuit 1: sky130_fd_sc_hd__clkbuf_16 |Circuit 2: sky130_fd_sc_hd__clkbuf_16
+-------------------------------------------|-------------------------------------------
+sky130_fd_pr__pfet_01v8_hvt (20->2) |sky130_fd_pr__pfet_01v8_hvt (20->2)
+sky130_fd_pr__nfet_01v8 (20->2) |sky130_fd_pr__nfet_01v8 (20->2)
+Number of devices: 4 |Number of devices: 4
+Number of nets: 7 |Number of nets: 7
+---------------------------------------------------------------------------------------
+Netlists match uniquely.
+
+Subcircuit pins:
+Circuit 1: sky130_fd_sc_hd__clkbuf_16 |Circuit 2: sky130_fd_sc_hd__clkbuf_16
+-------------------------------------------|-------------------------------------------
+VPWR |VPWR
+X |X
+VPB |VPB
+VGND |VGND
+VNB |VNB
+A |A
+---------------------------------------------------------------------------------------
+Cell pin lists are equivalent.
+Device classes sky130_fd_sc_hd__clkbuf_16 and sky130_fd_sc_hd__clkbuf_16 are equivalent.
+
+Subcircuit summary:
+Circuit 1: sky130_fd_sc_hd__decap_3 |Circuit 2: sky130_fd_sc_hd__decap_3
+-------------------------------------------|-------------------------------------------
+sky130_fd_pr__pfet_01v8_hvt (1) |sky130_fd_pr__pfet_01v8_hvt (1)
+sky130_fd_pr__nfet_01v8 (1) |sky130_fd_pr__nfet_01v8 (1)
+Number of devices: 2 |Number of devices: 2
+Number of nets: 4 |Number of nets: 4
+---------------------------------------------------------------------------------------
+Netlists match uniquely.
+
+Subcircuit pins:
+Circuit 1: sky130_fd_sc_hd__decap_3 |Circuit 2: sky130_fd_sc_hd__decap_3
+-------------------------------------------|-------------------------------------------
+VPB |VPB
+VNB |VNB
+VPWR |VPWR
+VGND |VGND
+---------------------------------------------------------------------------------------
+Cell pin lists are equivalent.
+Device classes sky130_fd_sc_hd__decap_3 and sky130_fd_sc_hd__decap_3 are equivalent.
+
+Class sky130_fd_sc_hd__clkbuf_2 (0): Merged 2 parallel devices.
+Class sky130_fd_sc_hd__clkbuf_2 (1): Merged 2 parallel devices.
+Subcircuit summary:
+Circuit 1: sky130_fd_sc_hd__clkbuf_2 |Circuit 2: sky130_fd_sc_hd__clkbuf_2
+-------------------------------------------|-------------------------------------------
+sky130_fd_pr__pfet_01v8_hvt (3->2) |sky130_fd_pr__pfet_01v8_hvt (3->2)
+sky130_fd_pr__nfet_01v8 (3->2) |sky130_fd_pr__nfet_01v8 (3->2)
+Number of devices: 4 |Number of devices: 4
+Number of nets: 7 |Number of nets: 7
+---------------------------------------------------------------------------------------
+Netlists match uniquely.
+
+Subcircuit pins:
+Circuit 1: sky130_fd_sc_hd__clkbuf_2 |Circuit 2: sky130_fd_sc_hd__clkbuf_2
+-------------------------------------------|-------------------------------------------
+A |A
+VPWR |VPWR
+VPB |VPB
+VGND |VGND
+VNB |VNB
+X |X
+---------------------------------------------------------------------------------------
+Cell pin lists are equivalent.
+Device classes sky130_fd_sc_hd__clkbuf_2 and sky130_fd_sc_hd__clkbuf_2 are equivalent.
+
+Class sky130_fd_sc_hd__and4bb_2 (0): Merged 2 parallel devices.
+Class sky130_fd_sc_hd__and4bb_2 (1): Merged 2 parallel devices.
+Subcircuit summary:
+Circuit 1: sky130_fd_sc_hd__and4bb_2 |Circuit 2: sky130_fd_sc_hd__and4bb_2
+-------------------------------------------|-------------------------------------------
+sky130_fd_pr__pfet_01v8_hvt (8->7) |sky130_fd_pr__pfet_01v8_hvt (8->7)
+sky130_fd_pr__nfet_01v8 (8->7) |sky130_fd_pr__nfet_01v8 (8->7)
+Number of devices: 14 |Number of devices: 14
+Number of nets: 15 |Number of nets: 15
+---------------------------------------------------------------------------------------
+Netlists match uniquely.
+
+Subcircuit pins:
+Circuit 1: sky130_fd_sc_hd__and4bb_2 |Circuit 2: sky130_fd_sc_hd__and4bb_2
+-------------------------------------------|-------------------------------------------
+VGND |VGND
+X |X
+D |D
+C |C
+B_N |B_N
+A_N |A_N
+VNB |VNB
+VPWR |VPWR
+VPB |VPB
+---------------------------------------------------------------------------------------
+Cell pin lists are equivalent.
+Device classes sky130_fd_sc_hd__and4bb_2 and sky130_fd_sc_hd__and4bb_2 are equivalent.
+
+Subcircuit summary:
+Circuit 1: sky130_fd_sc_hd__decap_8 |Circuit 2: sky130_fd_sc_hd__decap_8
+-------------------------------------------|-------------------------------------------
+sky130_fd_pr__pfet_01v8_hvt (1) |sky130_fd_pr__pfet_01v8_hvt (1)
+sky130_fd_pr__nfet_01v8 (1) |sky130_fd_pr__nfet_01v8 (1)
+Number of devices: 2 |Number of devices: 2
+Number of nets: 4 |Number of nets: 4
+---------------------------------------------------------------------------------------
+Netlists match uniquely.
+
+Subcircuit pins:
+Circuit 1: sky130_fd_sc_hd__decap_8 |Circuit 2: sky130_fd_sc_hd__decap_8
+-------------------------------------------|-------------------------------------------
+VPB |VPB
+VNB |VNB
+VPWR |VPWR
+VGND |VGND
+---------------------------------------------------------------------------------------
+Cell pin lists are equivalent.
+Device classes sky130_fd_sc_hd__decap_8 and sky130_fd_sc_hd__decap_8 are equivalent.
+
+Class sky130_fd_sc_hd__nor4b_2 (0): Merged 8 parallel devices.
+Class sky130_fd_sc_hd__nor4b_2 (1): Merged 8 parallel devices.
+Subcircuit summary:
+Circuit 1: sky130_fd_sc_hd__nor4b_2 |Circuit 2: sky130_fd_sc_hd__nor4b_2
+-------------------------------------------|-------------------------------------------
+sky130_fd_pr__pfet_01v8_hvt (9->5) |sky130_fd_pr__pfet_01v8_hvt (9->5)
+sky130_fd_pr__nfet_01v8 (9->5) |sky130_fd_pr__nfet_01v8 (9->5)
+Number of devices: 10 |Number of devices: 10
+Number of nets: 13 |Number of nets: 13
+---------------------------------------------------------------------------------------
+Netlists match uniquely.
+
+Subcircuit pins:
+Circuit 1: sky130_fd_sc_hd__nor4b_2 |Circuit 2: sky130_fd_sc_hd__nor4b_2
+-------------------------------------------|-------------------------------------------
+VPB |VPB
+Y |Y
+VGND |VGND
+VNB |VNB
+D_N |D_N
+VPWR |VPWR
+A |A
+C |C
+B |B
+---------------------------------------------------------------------------------------
+Cell pin lists are equivalent.
+Device classes sky130_fd_sc_hd__nor4b_2 and sky130_fd_sc_hd__nor4b_2 are equivalent.
+
+Class sky130_fd_sc_hd__and4b_2 (0): Merged 2 parallel devices.
+Class sky130_fd_sc_hd__and4b_2 (1): Merged 2 parallel devices.
+Subcircuit summary:
+Circuit 1: sky130_fd_sc_hd__and4b_2 |Circuit 2: sky130_fd_sc_hd__and4b_2
+-------------------------------------------|-------------------------------------------
+sky130_fd_pr__pfet_01v8_hvt (7->6) |sky130_fd_pr__pfet_01v8_hvt (7->6)
+sky130_fd_pr__nfet_01v8 (7->6) |sky130_fd_pr__nfet_01v8 (7->6)
+Number of devices: 12 |Number of devices: 12
+Number of nets: 14 |Number of nets: 14
+---------------------------------------------------------------------------------------
+Netlists match uniquely.
+
+Subcircuit pins:
+Circuit 1: sky130_fd_sc_hd__and4b_2 |Circuit 2: sky130_fd_sc_hd__and4b_2
+-------------------------------------------|-------------------------------------------
+VGND |VGND
+X |X
+D |D
+A_N |A_N
+C |C
+B |B
+VPWR |VPWR
+VPB |VPB
+VNB |VNB
+---------------------------------------------------------------------------------------
+Cell pin lists are equivalent.
+Device classes sky130_fd_sc_hd__and4b_2 and sky130_fd_sc_hd__and4b_2 are equivalent.
+
+Subcircuit summary:
+Circuit 1: sky130_fd_sc_hd__decap_4 |Circuit 2: sky130_fd_sc_hd__decap_4
+-------------------------------------------|-------------------------------------------
+sky130_fd_pr__pfet_01v8_hvt (1) |sky130_fd_pr__pfet_01v8_hvt (1)
+sky130_fd_pr__nfet_01v8 (1) |sky130_fd_pr__nfet_01v8 (1)
+Number of devices: 2 |Number of devices: 2
+Number of nets: 4 |Number of nets: 4
+---------------------------------------------------------------------------------------
+Netlists match uniquely.
+
+Subcircuit pins:
+Circuit 1: sky130_fd_sc_hd__decap_4 |Circuit 2: sky130_fd_sc_hd__decap_4
+-------------------------------------------|-------------------------------------------
+VPB |VPB
+VNB |VNB
+VPWR |VPWR
+VGND |VGND
+---------------------------------------------------------------------------------------
+Cell pin lists are equivalent.
+Device classes sky130_fd_sc_hd__decap_4 and sky130_fd_sc_hd__decap_4 are equivalent.
+
+Class sky130_fd_sc_hd__and3_2 (0): Merged 2 parallel devices.
+Class sky130_fd_sc_hd__and3_2 (1): Merged 2 parallel devices.
+Subcircuit summary:
+Circuit 1: sky130_fd_sc_hd__and3_2 |Circuit 2: sky130_fd_sc_hd__and3_2
+-------------------------------------------|-------------------------------------------
+sky130_fd_pr__pfet_01v8_hvt (5->4) |sky130_fd_pr__pfet_01v8_hvt (5->4)
+sky130_fd_pr__nfet_01v8 (5->4) |sky130_fd_pr__nfet_01v8 (5->4)
+Number of devices: 8 |Number of devices: 8
+Number of nets: 11 |Number of nets: 11
+---------------------------------------------------------------------------------------
+Netlists match uniquely.
+
+Subcircuit pins:
+Circuit 1: sky130_fd_sc_hd__and3_2 |Circuit 2: sky130_fd_sc_hd__and3_2
+-------------------------------------------|-------------------------------------------
+X |X
+VGND |VGND
+A |A
+C |C
+B |B
+VNB |VNB
+VPWR |VPWR
+VPB |VPB
+---------------------------------------------------------------------------------------
+Cell pin lists are equivalent.
+Device classes sky130_fd_sc_hd__and3_2 and sky130_fd_sc_hd__and3_2 are equivalent.
+
+Subcircuit summary:
+Circuit 1: sky130_fd_sc_hd__decap_6 |Circuit 2: sky130_fd_sc_hd__decap_6
+-------------------------------------------|-------------------------------------------
+sky130_fd_pr__pfet_01v8_hvt (1) |sky130_fd_pr__pfet_01v8_hvt (1)
+sky130_fd_pr__nfet_01v8 (1) |sky130_fd_pr__nfet_01v8 (1)
+Number of devices: 2 |Number of devices: 2
+Number of nets: 4 |Number of nets: 4
+---------------------------------------------------------------------------------------
+Netlists match uniquely.
+
+Subcircuit pins:
+Circuit 1: sky130_fd_sc_hd__decap_6 |Circuit 2: sky130_fd_sc_hd__decap_6
+-------------------------------------------|-------------------------------------------
+VPB |VPB
+VNB |VNB
+VPWR |VPWR
+VGND |VGND
+---------------------------------------------------------------------------------------
+Cell pin lists are equivalent.
+Device classes sky130_fd_sc_hd__decap_6 and sky130_fd_sc_hd__decap_6 are equivalent.
+
+Subcircuit summary:
+Circuit 1: sky130_fd_sc_hd__mux2_1 |Circuit 2: sky130_fd_sc_hd__mux2_1
+-------------------------------------------|-------------------------------------------
+sky130_fd_pr__pfet_01v8_hvt (6) |sky130_fd_pr__pfet_01v8_hvt (6)
+sky130_fd_pr__nfet_01v8 (6) |sky130_fd_pr__nfet_01v8 (6)
+Number of devices: 12 |Number of devices: 12
+Number of nets: 14 |Number of nets: 14
+---------------------------------------------------------------------------------------
+Netlists match uniquely.
+
+Subcircuit pins:
+Circuit 1: sky130_fd_sc_hd__mux2_1 |Circuit 2: sky130_fd_sc_hd__mux2_1
+-------------------------------------------|-------------------------------------------
+VPB |VPB
+VNB |VNB
+A0 |A0
+A1 |A1
+X |X
+VPWR |VPWR
+S |S
+VGND |VGND
+---------------------------------------------------------------------------------------
+Cell pin lists are equivalent.
+Device classes sky130_fd_sc_hd__mux2_1 and sky130_fd_sc_hd__mux2_1 are equivalent.
+
+Cell sky130_fd_sc_hd__conb_1 (0) disconnected node: VNB
+Cell sky130_fd_sc_hd__conb_1 (0) disconnected node: VPB
+Cell sky130_fd_sc_hd__conb_1 (1) disconnected node: VNB
+Cell sky130_fd_sc_hd__conb_1 (1) disconnected node: VPB
+Subcircuit summary:
+Circuit 1: sky130_fd_sc_hd__conb_1 |Circuit 2: sky130_fd_sc_hd__conb_1
+-------------------------------------------|-------------------------------------------
+sky130_fd_pr__res_generic_po (2) |sky130_fd_pr__res_generic_po (2)
+Number of devices: 2 |Number of devices: 2
+Number of nets: 4 |Number of nets: 4
+---------------------------------------------------------------------------------------
+Resolving automorphisms by property value.
+Resolving automorphisms by pin name.
+Netlists match uniquely.
+
+Subcircuit pins:
+Circuit 1: sky130_fd_sc_hd__conb_1 |Circuit 2: sky130_fd_sc_hd__conb_1
+-------------------------------------------|-------------------------------------------
+VGND |VGND
+LO |LO
+HI |HI
+VPWR |VPWR
+VNB |VNB
+VPB |VPB
+---------------------------------------------------------------------------------------
+Cell pin lists are equivalent.
+Device classes sky130_fd_sc_hd__conb_1 and sky130_fd_sc_hd__conb_1 are equivalent.
+
+Class sky130_fd_sc_hd__nor3b_2 (0): Merged 6 parallel devices.
+Class sky130_fd_sc_hd__nor3b_2 (1): Merged 6 parallel devices.
+Subcircuit summary:
+Circuit 1: sky130_fd_sc_hd__nor3b_2 |Circuit 2: sky130_fd_sc_hd__nor3b_2
+-------------------------------------------|-------------------------------------------
+sky130_fd_pr__pfet_01v8_hvt (7->4) |sky130_fd_pr__pfet_01v8_hvt (7->4)
+sky130_fd_pr__nfet_01v8 (7->4) |sky130_fd_pr__nfet_01v8 (7->4)
+Number of devices: 8 |Number of devices: 8
+Number of nets: 11 |Number of nets: 11
+---------------------------------------------------------------------------------------
+Netlists match uniquely.
+
+Subcircuit pins:
+Circuit 1: sky130_fd_sc_hd__nor3b_2 |Circuit 2: sky130_fd_sc_hd__nor3b_2
+-------------------------------------------|-------------------------------------------
+Y |Y
+VGND |VGND
+VNB |VNB
+VPB |VPB
+VPWR |VPWR
+A |A
+B |B
+C_N |C_N
+---------------------------------------------------------------------------------------
+Cell pin lists are equivalent.
+Device classes sky130_fd_sc_hd__nor3b_2 and sky130_fd_sc_hd__nor3b_2 are equivalent.
+
+Class sky130_fd_sc_hd__and2b_2 (0): Merged 2 parallel devices.
+Class sky130_fd_sc_hd__and2b_2 (1): Merged 2 parallel devices.
+Subcircuit summary:
+Circuit 1: sky130_fd_sc_hd__and2b_2 |Circuit 2: sky130_fd_sc_hd__and2b_2
+-------------------------------------------|-------------------------------------------
+sky130_fd_pr__pfet_01v8_hvt (5->4) |sky130_fd_pr__pfet_01v8_hvt (5->4)
+sky130_fd_pr__nfet_01v8 (5->4) |sky130_fd_pr__nfet_01v8 (5->4)
+Number of devices: 8 |Number of devices: 8
+Number of nets: 10 |Number of nets: 10
+---------------------------------------------------------------------------------------
+Netlists match uniquely.
+
+Subcircuit pins:
+Circuit 1: sky130_fd_sc_hd__and2b_2 |Circuit 2: sky130_fd_sc_hd__and2b_2
+-------------------------------------------|-------------------------------------------
+VGND |VGND
+X |X
+B |B
+A_N |A_N
+VPWR |VPWR
+VPB |VPB
+VNB |VNB
+---------------------------------------------------------------------------------------
+Cell pin lists are equivalent.
+Device classes sky130_fd_sc_hd__and2b_2 and sky130_fd_sc_hd__and2b_2 are equivalent.
+
+Class sky130_fd_sc_hd__and2_2 (0): Merged 2 parallel devices.
+Class sky130_fd_sc_hd__and2_2 (1): Merged 2 parallel devices.
+Subcircuit summary:
+Circuit 1: sky130_fd_sc_hd__and2_2 |Circuit 2: sky130_fd_sc_hd__and2_2
+-------------------------------------------|-------------------------------------------
+sky130_fd_pr__pfet_01v8_hvt (4->3) |sky130_fd_pr__pfet_01v8_hvt (4->3)
+sky130_fd_pr__nfet_01v8 (4->3) |sky130_fd_pr__nfet_01v8 (4->3)
+Number of devices: 6 |Number of devices: 6
+Number of nets: 9 |Number of nets: 9
+---------------------------------------------------------------------------------------
+Netlists match uniquely.
+
+Subcircuit pins:
+Circuit 1: sky130_fd_sc_hd__and2_2 |Circuit 2: sky130_fd_sc_hd__and2_2
+-------------------------------------------|-------------------------------------------
+VPWR |VPWR
+VPB |VPB
+VNB |VNB
+X |X
+A |A
+B |B
+VGND |VGND
+---------------------------------------------------------------------------------------
+Cell pin lists are equivalent.
+Device classes sky130_fd_sc_hd__and2_2 and sky130_fd_sc_hd__and2_2 are equivalent.
+
+Class RAM256 (0): Merged 2411 parallel devices.
+Class RAM256 (1): Merged 2411 parallel devices.
+Subcircuit summary:
+Circuit 1: RAM256 |Circuit 2: RAM256
+-------------------------------------------|-------------------------------------------
+sky130_fd_sc_hd__and2_1 (1024) |sky130_fd_sc_hd__and2_1 (1024)
+sky130_fd_sc_hd__dlxtp_1 (8192) |sky130_fd_sc_hd__dlxtp_1 (8192)
+sky130_fd_sc_hd__ebufn_2 (8448) |sky130_fd_sc_hd__ebufn_2 (8448)
+sky130_fd_sc_hd__dlclkp_1 (1024) |sky130_fd_sc_hd__dlclkp_1 (1024)
+sky130_fd_sc_hd__diode_2 (1604->836) |sky130_fd_sc_hd__diode_2 (1604->836)
+sky130_fd_sc_hd__and4_2 (32) |sky130_fd_sc_hd__and4_2 (32)
+sky130_fd_sc_hd__decap_12 (1319->1) |sky130_fd_sc_hd__decap_12 (1319->1)
+sky130_fd_sc_hd__inv_1 (2048) |sky130_fd_sc_hd__inv_1 (2048)
+sky130_fd_sc_hd__dfxtp_1 (256) |sky130_fd_sc_hd__dfxtp_1 (256)
+sky130_fd_sc_hd__mux4_1 (64) |sky130_fd_sc_hd__mux4_1 (64)
+sky130_fd_sc_hd__clkbuf_4 (306) |sky130_fd_sc_hd__clkbuf_4 (306)
+sky130_fd_sc_hd__and3b_2 (20) |sky130_fd_sc_hd__and3b_2 (20)
+sky130_fd_sc_hd__clkbuf_16 (320) |sky130_fd_sc_hd__clkbuf_16 (320)
+sky130_fd_sc_hd__decap_3 (148->1) |sky130_fd_sc_hd__decap_3 (148->1)
+sky130_fd_sc_hd__clkbuf_2 (700) |sky130_fd_sc_hd__clkbuf_2 (700)
+sky130_fd_sc_hd__and4bb_2 (96) |sky130_fd_sc_hd__and4bb_2 (96)
+sky130_fd_sc_hd__decap_8 (102->1) |sky130_fd_sc_hd__decap_8 (102->1)
+sky130_fd_sc_hd__nor4b_2 (32) |sky130_fd_sc_hd__nor4b_2 (32)
+sky130_fd_sc_hd__and4b_2 (96) |sky130_fd_sc_hd__and4b_2 (96)
+sky130_fd_sc_hd__decap_4 (25->1) |sky130_fd_sc_hd__decap_4 (25->1)
+sky130_fd_sc_hd__and3_2 (10) |sky130_fd_sc_hd__and3_2 (10)
+sky130_fd_sc_hd__decap_6 (54->1) |sky130_fd_sc_hd__decap_6 (54->1)
+sky130_fd_sc_hd__mux2_1 (32) |sky130_fd_sc_hd__mux2_1 (32)
+sky130_fd_sc_hd__conb_1 (32) |sky130_fd_sc_hd__conb_1 (32)
+sky130_fd_sc_hd__nor3b_2 (10) |sky130_fd_sc_hd__nor3b_2 (10)
+sky130_fd_sc_hd__and2b_2 (1) |sky130_fd_sc_hd__and2b_2 (1)
+sky130_fd_sc_hd__and2_2 (1) |sky130_fd_sc_hd__and2_2 (1)
+Number of devices: 23585 |Number of devices: 23585
+Number of nets: 14632 |Number of nets: 14632
+---------------------------------------------------------------------------------------
+Resolving automorphisms by property value.
+Resolving automorphisms by pin name.
+Netlists match uniquely.
+
+Subcircuit pins:
+Circuit 1: RAM256 |Circuit 2: RAM256
+-------------------------------------------|-------------------------------------------
+Do0[0] |Do0[0]
+Do0[1] |Do0[1]
+Do0[2] |Do0[2]
+Do0[3] |Do0[3]
+Do0[4] |Do0[4]
+Do0[5] |Do0[5]
+Do0[6] |Do0[6]
+Do0[7] |Do0[7]
+Do0[8] |Do0[8]
+Do0[9] |Do0[9]
+Do0[10] |Do0[10]
+Do0[11] |Do0[11]
+Do0[12] |Do0[12]
+Do0[13] |Do0[13]
+Do0[14] |Do0[14]
+Do0[15] |Do0[15]
+Do0[16] |Do0[16]
+Do0[17] |Do0[17]
+Do0[18] |Do0[18]
+Do0[19] |Do0[19]
+Do0[20] |Do0[20]
+Do0[21] |Do0[21]
+Do0[22] |Do0[22]
+Do0[23] |Do0[23]
+Do0[24] |Do0[24]
+Do0[25] |Do0[25]
+Do0[26] |Do0[26]
+Do0[27] |Do0[27]
+Do0[28] |Do0[28]
+Do0[29] |Do0[29]
+Do0[30] |Do0[30]
+Do0[31] |Do0[31]
+A0[7] |A0[7]
+VGND |VGND
+VPWR |VPWR
+A0[6] |A0[6]
+A0[5] |A0[5]
+CLK |CLK
+Di0[0] |Di0[0]
+Di0[10] |Di0[10]
+Di0[11] |Di0[11]
+Di0[12] |Di0[12]
+Di0[13] |Di0[13]
+Di0[14] |Di0[14]
+Di0[15] |Di0[15]
+Di0[16] |Di0[16]
+Di0[17] |Di0[17]
+Di0[18] |Di0[18]
+Di0[19] |Di0[19]
+Di0[1] |Di0[1]
+Di0[20] |Di0[20]
+Di0[21] |Di0[21]
+Di0[22] |Di0[22]
+Di0[23] |Di0[23]
+Di0[24] |Di0[24]
+Di0[25] |Di0[25]
+Di0[26] |Di0[26]
+Di0[27] |Di0[27]
+Di0[28] |Di0[28]
+Di0[29] |Di0[29]
+Di0[2] |Di0[2]
+Di0[30] |Di0[30]
+Di0[31] |Di0[31]
+Di0[3] |Di0[3]
+Di0[4] |Di0[4]
+Di0[5] |Di0[5]
+Di0[6] |Di0[6]
+Di0[7] |Di0[7]
+Di0[8] |Di0[8]
+Di0[9] |Di0[9]
+A0[3] |A0[3]
+A0[4] |A0[4]
+A0[0] |A0[0]
+A0[1] |A0[1]
+A0[2] |A0[2]
+WE0[0] |WE0[0]
+WE0[1] |WE0[1]
+WE0[2] |WE0[2]
+WE0[3] |WE0[3]
+EN0 |EN0
+---------------------------------------------------------------------------------------
+Cell pin lists are equivalent.
+Device classes RAM256 and RAM256 are equivalent.
+
+Final result: Circuits match uniquely.
+.
diff --git a/signoff/RAM256/standalone_pvr/eco-RAM256.unflattened b/signoff/RAM256/standalone_pvr/eco-RAM256.unflattened
new file mode 100644
index 0000000..e69de29
diff --git a/signoff/RAM256/standalone_pvr/eco-RAM256_klayout_drc.xml b/signoff/RAM256/standalone_pvr/eco-RAM256_klayout_drc.xml
new file mode 100644
index 0000000..d506485
--- /dev/null
+++ b/signoff/RAM256/standalone_pvr/eco-RAM256_klayout_drc.xml
@@ -0,0 +1,873 @@
+
+
+ SKY130 DRC runset
+
+ drc: script='tech-files/sky130A_mr.drc'
+ RAM256
+
+
+
+
+ dnwell.2
+ dnwell.2 : min. dnwell width : 3.0um
+
+
+
+
+ nwell.1
+ nwell.1 : min. nwell width : 0.84um
+
+
+
+
+ nwell.2a
+ nwell.2a : min. nwell spacing (merged if less) : 1.27um
+
+
+
+
+ nwell.6
+ nwell.6 : min enclosure of nwellHole by dnwell : 1.03um
+
+
+
+
+ hvtp.1
+ hvtp.1 : min. hvtp width : 0.38um
+
+
+
+
+ hvtp.2
+ hvtp.2 : min. hvtp spacing : 0.38um
+
+
+
+
+ hvtr.1
+ hvtr.1 : min. hvtr width : 0.38um
+
+
+
+
+ hvtr.2
+ hvtr.2 : min. hvtr spacing : 0.38um
+
+
+
+
+ hvtr.2_a
+ hvtr.2_a : hvtr must not overlap hvtp
+
+
+
+
+ lvtn.1a
+ lvtn.1a : min. lvtn width : 0.38um
+
+
+
+
+ lvtn.2
+ lvtn.2 : min. lvtn spacing : 0.38um
+
+
+
+
+ ncm.1
+ ncm.1 : min. ncm width : 0.38um
+
+
+
+
+ ncm.2a
+ ncm.2a : min. ncm spacing : 0.38um
+
+
+
+
+ difftap.1
+ difftap.1 : min. diff width across areaid:ce : 0.15um
+
+
+
+
+ difftap.1_a
+ difftap.1_a : min. diff width in periphery : 0.15um
+
+
+
+
+ difftap.1_b
+ difftap.1_b : min. tap width across areaid:ce : 0.15um
+
+
+
+
+ difftap.1_c
+ difftap.1_c : min. tap width in periphery : 0.15um
+
+
+
+
+ difftap.3
+ difftap.3 : min. difftap spacing : 0.27um
+
+
+
+
+ tunm.1
+ tunm.1 : min. tunm width : 0.41um
+
+
+
+
+ tunm.2
+ tunm.2 : min. tunm spacing : 0.5um
+
+
+
+
+ poly.1a
+ poly.1a : min. poly width : 0.15um
+
+
+
+
+ poly.2
+ poly.2 : min. poly spacing : 0.21um
+
+
+
+
+ rpm.1a
+ rpm.1a : min. rpm width : 1.27um
+
+
+
+
+ rpm.2
+ rpm.2 : min. rpm spacing : 0.84um
+
+
+
+
+ urpm.1a
+ urpm.1a : min. rpm width : 1.27um
+
+
+
+
+ urpm.2
+ urpm.2 : min. rpm spacing : 0.84um
+
+
+
+
+ npc.1
+ npc.1 : min. npc width : 0.27um
+
+
+
+
+ npc.2
+ npc.2 : min. npc spacing, should be manually merged if less than : 0.27um
+
+
+
+
+ nsd.1
+ nsd.1 : min. nsdm width : 0.38um
+
+
+
+
+ nsd.2
+ nsd.2 : min. nsdm spacing, should be manually merged if less than : 0.38um
+
+
+
+
+ psd.1
+ psd.1 : min. psdm width : 0.38um
+
+
+
+
+ psd.2
+ psd.2 : min. psdm spacing, should be manually merged if less than : 0.38um
+
+
+
+
+ licon.1
+ licon.1 : licon should be rectangle
+
+
+
+
+ licon.1_a/b
+ licon.1_a/b : minimum/maximum width of licon : 0.17um
+
+
+
+
+ licon.13
+ licon.13 : min. difftap licon spacing to npc : 0.09um
+
+
+
+
+ licon.13_a
+ licon.13_a : licon of diffTap in periphery must not overlap npc
+
+
+
+
+ licon.17
+ licon.17 : Licons may not overlap both poly and (diff or tap)
+
+
+
+
+ capm.1
+ capm.1 : min. capm width : 1.0um
+
+
+
+
+ capm.2a
+ capm.2a : min. capm spacing : 0.84um
+
+
+
+
+ capm.2b
+ capm.2b : min. capm spacing : 1.2um
+
+
+
+
+ capm.2b_a
+ capm.2b_a : min. spacing of m3_bot_plate : 1.2um
+
+
+
+
+ capm.3
+ capm.3 : min. capm and m3 enclosure of m3 : 0.14um
+
+
+
+
+ capm.3_a
+ capm.3_a : min. m3 enclosure of capm : 0.14um
+
+
+
+
+ capm.4
+ capm.4 : min. capm enclosure of via3 : 0.14um
+
+
+
+
+ capm.5
+ capm.5 : min. capm spacing to via3 : 0.14um
+
+
+
+
+ capm.11
+ capm.11 : Min spacing of capm and met3 not overlapping capm : 0.5um
+
+
+
+
+ cap2m.1
+ cap2m.1 : min. cap2m width : 1.0um
+
+
+
+
+ cap2m.2a
+ cap2m.2a : min. cap2m spacing : 0.84um
+
+
+
+
+ cap2m.2b
+ cap2m.2b : min. cap2m spacing : 1.2um
+
+
+
+
+ cap2m.2b_a
+ cap2m.2b_a : min. spacing of m4_bot_plate : 1.2um
+
+
+
+
+ cap2m.3
+ cap2m.3 : min. m4 enclosure of cap2m : 0.14um
+
+
+
+
+ cap2m.3_a
+ cap2m.3_a : min. m4 enclosure of cap2m : 0.14um
+
+
+
+
+ cap2m.4
+ cap2m.4 : min. cap2m enclosure of via4 : 0.14um
+
+
+
+
+ cap2m.5
+ cap2m.5 : min. cap2m spacing to via4 : 0.14um
+
+
+
+
+ cap2m.11
+ cap2m.11 : Min spacing of cap2m and met4 not overlapping cap2m : 0.5um
+
+
+
+
+ li.1
+ li.1 : min. li width : 0.17um
+
+
+
+
+ li.3
+ li.3 : min. li spacing : 0.17um
+
+
+
+
+ li.5
+ li.5 : min. li enclosure of licon of 2 adjacent edges : 0.08um
+
+
+
+
+ li.6
+ li.6 : min. li area : 0.0561um²
+
+
+
+
+ ct.1
+ ct.1: non-ring mcon should be rectangular
+
+
+
+
+ ct.1_a
+ ct.1_a : minimum width of mcon : 0.17um
+
+
+
+
+ ct.1_b
+ ct.1_b : maximum length of mcon : 0.17um
+
+
+
+
+ ct.2
+ ct.2 : min. mcon spacing : 0.19um
+
+
+
+
+ ct.3
+ ct.3 : min. width of ring-shaped mcon : 0.17um
+
+
+
+
+ ct.3_a
+ ct.3_a : max. width of ring-shaped mcon : 0.175um
+
+
+
+
+ ct.3_b
+ ct.3_b: ring-shaped mcon must be enclosed by areaid_sl
+
+
+
+
+ ct.4
+ ct.4 : mcon should covered by li
+
+
+
+
+ m1.1
+ m1.1 : min. m1 width : 0.14um
+
+
+
+
+ m1.2
+ m1.2 : min. m1 spacing : 0.14um
+
+
+
+
+ m1.3ab
+ m1.3ab : min. 3um.m1 spacing m1 : 0.28um
+
+
+
+
+ 791_m1.4
+ 791_m1.4 : min. m1 enclosure of mcon : 0.03um
+
+
+
+
+ m1.4
+ m1.4 : mcon periphery must be enclosed by m1
+
+
+
+
+ m1.4a
+ m1.4a : min. m1 enclosure of mcon for specific cells : 0.005um
+
+
+
+
+ m1.4a_a
+ m1.4a_a : mcon periph must be enclosed by met1 for specific cells
+
+
+
+
+ m1.6
+ m1.6 : min. m1 area : 0.083um²
+
+
+
+
+ m1.7
+ m1.7 : min. m1 with holes area : 0.14um²
+
+
+
+
+ m1.5
+ m1.5 : min. m1 enclosure of mcon of 2 adjacent edges : 0.06um
+
+
+
+
+ via.1a
+ via.1a : via outside of moduleCut should be rectangular
+
+
+
+
+ via.1a_a
+ via.1a_a : min. width of via outside of moduleCut : 0.15um
+
+
+
+
+ via.1a_b
+ via.1a_b : maximum length of via : 0.15um
+
+
+
+
+ via.2
+ via.2 : min. via spacing : 0.17um
+
+
+
+
+ via.3
+ via.3 : min. width of ring-shaped via : 0.2um
+
+
+
+
+ via.3_a
+ via.3_a : max. width of ring-shaped via : 0.205um
+
+
+
+
+ via.3_b
+ via.3_b: ring-shaped via must be enclosed by areaid_sl
+
+
+
+
+ via.4a
+ via.4a : min. m1 enclosure of 0.15um via : 0.055um
+
+
+
+
+ via.4a_a
+ via.4a_a : 0.15um via must be enclosed by met1
+
+
+
+
+ via.5a
+ via.5a : min. m1 enclosure of 0.15um via of 2 adjacent edges : 0.085um
+
+
+
+
+ m2.1
+ m2.1 : min. m2 width : 0.14um
+
+
+
+
+ m2.2
+ m2.2 : min. m2 spacing : 0.14um
+
+
+
+
+ m2.3ab
+ m2.3ab : min. 3um.m2 spacing m2 : 0.28um
+
+
+
+
+ m2.6
+ m2.6 : min. m2 area : 0.0676um²
+
+
+
+
+ m2.7
+ m2.7 : min. m2 holes area : 0.14um²
+
+
+
+
+ m2.4
+ m2.4 : min. m2 enclosure of via : 0.055um
+
+
+
+
+ m2.4_a
+ m2.4_a : via in periphery must be enclosed by met2
+
+
+
+
+ m2.5
+ m2.5 : min. m2 enclosure of via of 2 adjacent edges : 0.085um
+
+
+
+
+ via2.1a
+ via2.1a : via2 outside of moduleCut should be rectangular
+
+
+
+
+ via2.1a_a
+ via2.1a_a : min. width of via2 outside of moduleCut : 0.2um
+
+
+
+
+ via2.1a_b
+ via2.1a_b : maximum length of via2 : 0.2um
+
+
+
+
+ via2.2
+ via2.2 : min. via2 spacing : 0.2um
+
+
+
+
+ via2.3
+ via2.3 : min. width of ring-shaped via2 : 0.2um
+
+
+
+
+ via2.3_a
+ via2.3_a : max. width of ring-shaped via2 : 0.205um
+
+
+
+
+ via2.3_b
+ via2.3_b: ring-shaped via2 must be enclosed by areaid_sl
+
+
+
+
+ via2.4
+ via2.4 : min. m2 enclosure of via2 : 0.04um
+
+
+
+
+ via2.4_a
+ via2.4_a : via must be enclosed by met2
+
+
+
+
+ via2.5
+ via2.5 : min. m3 enclosure of via2 of 2 adjacent edges : 0.085um
+
+
+
+
+ m3.1
+ m3.1 : min. m3 width : 0.3um
+
+
+
+
+ m3.2
+ m3.2 : min. m3 spacing : 0.3um
+
+
+
+
+ m3.3cd
+ m3.3cd : min. 3um.m3 spacing m3 : 0.4um
+
+
+
+
+ m3.4
+ m3.4 : min. m3 enclosure of via2 : 0.065um
+
+
+
+
+ m3.4_a
+ m3.4_a : via2 must be enclosed by met3
+
+
+
+
+ via3.1
+ via3.1 : via3 outside of moduleCut should be rectangular
+
+
+
+
+ via3.1_a
+ via3.1_a : min. width of via3 outside of moduleCut : 0.2um
+
+
+
+
+ via3.1_b
+ via3.1_b : maximum length of via3 : 0.2um
+
+
+
+
+ via3.2
+ via3.2 : min. via3 spacing : 0.2um
+
+
+
+
+ via3.4
+ via3.4 : min. m3 enclosure of via3 : 0.06um
+
+
+
+
+ via3.4_a
+ via3.4_a : non-ring via3 must be enclosed by met3
+
+
+
+
+ via3.5
+ via3.5 : min. m3 enclosure of via3 of 2 adjacent edges : 0.09um
+
+
+
+
+ m4.1
+ m4.1 : min. m4 width : 0.3um
+
+
+
+
+ m4.2
+ m4.2 : min. m4 spacing : 0.3um
+
+
+
+
+ m4.4a
+ m4.4a : min. m4 area : 0.240um²
+
+
+
+
+ m4.5ab
+ m4.5ab : min. 3um.m4 spacing m4 : 0.4um
+
+
+
+
+ m4.3
+ m4.3 : min. m4 enclosure of via3 : 0.065um
+
+
+
+
+ m4.3_a
+ m4.3_a : via3 must be enclosed by met4
+
+
+
+
+ via4.1
+ via4.1 : via4 outside of moduleCut should be rectangular
+
+
+
+
+ via4.1_a
+ via4.1_a : min. width of via4 outside of moduleCut : 0.8um
+
+
+
+
+ via4.1_b
+ via4.1_b : maximum length of via4 : 0.8um
+
+
+
+
+ via4.2
+ via4.2 : min. via4 spacing : 0.8um
+
+
+
+
+ via4.3
+ via4.3 : min. width of ring-shaped via4 : 0.8um
+
+
+
+
+ via4.3_a
+ via4.3_a : max. width of ring-shaped via4 : 0.805um
+
+
+
+
+ via4.3_b
+ via4.3_b: ring-shaped via4 must be enclosed by areaid_sl
+
+
+
+
+ via4.4
+ via4.4 : min. m4 enclosure of via4 : 0.19um
+
+
+
+
+ via4.4_a
+ via4.4_a : m4 must enclose all via4
+
+
+
+
+ m5.1
+ m5.1 : min. m5 width : 1.6um
+
+
+
+
+ m5.2
+ m5.2 : min. m5 spacing : 1.6um
+
+
+
+
+ m5.3
+ m5.3 : min. m5 enclosure of via4 : 0.31um
+
+
+
+
+ m5.3_a
+ m5.3_a : via must be enclosed by m5
+
+
+
+
+ m5.4
+ m5.4 : min. m5 area : 4.0um²
+
+
+
+
+ pad.2
+ pad.2 : min. pad spacing : 1.27um
+
+
+
+
+ hvi.1
+ hvi.1 : min. hvi width : 0.6um
+
+
+
+
+ hvi.2a
+ hvi.2a : min. hvi spacing : 0.7um
+
+
+
+
+ hvntm.1
+ hvntm.1 : min. hvntm width : 0.7um
+
+
+
+
+ hvntm.2
+ hvntm.2 : min. hvntm spacing : 0.7um
+
+
+
+
+
+
+ RAM256
+
+
+
+ |
+
+
+
+
diff --git a/signoff/RAM256/standalone_pvr/eco-lvs_summary.rpt b/signoff/RAM256/standalone_pvr/eco-lvs_summary.rpt
new file mode 100644
index 0000000..64103fd
--- /dev/null
+++ b/signoff/RAM256/standalone_pvr/eco-lvs_summary.rpt
@@ -0,0 +1 @@
+Layout Vs Schematic Passed
\ No newline at end of file
diff --git a/signoff/mgmt_core_wrapper/standalone_pvr/eco-lvs_summary.rpt b/signoff/mgmt_core_wrapper/standalone_pvr/eco-lvs_summary.rpt
new file mode 100644
index 0000000..64103fd
--- /dev/null
+++ b/signoff/mgmt_core_wrapper/standalone_pvr/eco-lvs_summary.rpt
@@ -0,0 +1 @@
+Layout Vs Schematic Passed
\ No newline at end of file
diff --git a/signoff/mgmt_core_wrapper/standalone_pvr/eco-mgmt_core_wrapper.lvs.json b/signoff/mgmt_core_wrapper/standalone_pvr/eco-mgmt_core_wrapper.lvs.json
new file mode 100644
index 0000000..5635084
--- /dev/null
+++ b/signoff/mgmt_core_wrapper/standalone_pvr/eco-mgmt_core_wrapper.lvs.json
@@ -0,0 +1,13018 @@
+[
+ {
+ "pins": [
+ [
+ "1",
+ "2",
+ "3",
+ "4"
+ ], [
+ "1",
+ "2",
+ "3",
+ "4"
+ ]
+ ]
+ },
+ {
+ "pins": [
+ [
+ "1",
+ "2",
+ "3",
+ "4"
+ ], [
+ "1",
+ "2",
+ "3",
+ "4"
+ ]
+ ]
+ },
+ {
+ "name": [
+ "sky130_fd_sc_hd__ebufn_2",
+ "sky130_fd_sc_hd__ebufn_2"
+ ],
+ "devices": [
+ [
+ ["sky130_fd_pr__pfet_01v8_hvt", 4],
+ ["sky130_fd_pr__nfet_01v8", 4 ]
+ ], [
+ ["sky130_fd_pr__pfet_01v8_hvt", 4 ],
+ ["sky130_fd_pr__nfet_01v8", 4 ]
+ ]
+ ],
+ "nets": [
+ 11,
+ 11
+ ],
+ "badnets": [
+ ],
+ "badelements": [
+ ],
+ "pins": [
+ [
+ "VGND",
+ "TE_B",
+ "VPWR",
+ "VNB",
+ "VPB",
+ "Z",
+ "A"
+ ], [
+ "VGND",
+ "TE_B",
+ "VPWR",
+ "VNB",
+ "VPB",
+ "Z",
+ "A"
+ ]
+ ]
+ },
+ {
+ "name": [
+ "sky130_fd_sc_hd__dlclkp_1",
+ "sky130_fd_sc_hd__dlclkp_1"
+ ],
+ "devices": [
+ [
+ ["sky130_fd_pr__pfet_01v8_hvt", 10],
+ ["sky130_fd_pr__nfet_01v8", 10 ]
+ ], [
+ ["sky130_fd_pr__pfet_01v8_hvt", 10 ],
+ ["sky130_fd_pr__nfet_01v8", 10 ]
+ ]
+ ],
+ "nets": [
+ 17,
+ 17
+ ],
+ "badnets": [
+ ],
+ "badelements": [
+ ],
+ "pins": [
+ [
+ "VGND",
+ "CLK",
+ "VPB",
+ "VNB",
+ "VPWR",
+ "GCLK",
+ "GATE"
+ ], [
+ "VGND",
+ "CLK",
+ "VPB",
+ "VNB",
+ "VPWR",
+ "GCLK",
+ "GATE"
+ ]
+ ]
+ },
+ {
+ "name": [
+ "sky130_fd_sc_hd__clkbuf_4",
+ "sky130_fd_sc_hd__clkbuf_4"
+ ],
+ "devices": [
+ [
+ ["sky130_fd_pr__pfet_01v8_hvt", 2],
+ ["sky130_fd_pr__nfet_01v8", 2 ]
+ ], [
+ ["sky130_fd_pr__pfet_01v8_hvt", 2 ],
+ ["sky130_fd_pr__nfet_01v8", 2 ]
+ ]
+ ],
+ "nets": [
+ 7,
+ 7
+ ],
+ "badnets": [
+ ],
+ "badelements": [
+ ],
+ "pins": [
+ [
+ "VPWR",
+ "X",
+ "VPB",
+ "A",
+ "VGND",
+ "VNB"
+ ], [
+ "VPWR",
+ "X",
+ "VPB",
+ "A",
+ "VGND",
+ "VNB"
+ ]
+ ]
+ },
+ {
+ "name": [
+ "sky130_fd_sc_hd__dlxtp_1",
+ "sky130_fd_sc_hd__dlxtp_1"
+ ],
+ "devices": [
+ [
+ ["sky130_fd_pr__nfet_01v8", 9],
+ ["sky130_fd_pr__pfet_01v8_hvt", 9 ]
+ ], [
+ ["sky130_fd_pr__nfet_01v8", 9 ],
+ ["sky130_fd_pr__pfet_01v8_hvt", 9 ]
+ ]
+ ],
+ "nets": [
+ 16,
+ 16
+ ],
+ "badnets": [
+ ],
+ "badelements": [
+ ],
+ "pins": [
+ [
+ "VPWR",
+ "VGND",
+ "VPB",
+ "VNB",
+ "D",
+ "Q",
+ "GATE"
+ ], [
+ "VPWR",
+ "VGND",
+ "VPB",
+ "VNB",
+ "D",
+ "Q",
+ "GATE"
+ ]
+ ]
+ },
+ {
+ "name": [
+ "sky130_fd_sc_hd__and4bb_2",
+ "sky130_fd_sc_hd__and4bb_2"
+ ],
+ "devices": [
+ [
+ ["sky130_fd_pr__pfet_01v8_hvt", 7],
+ ["sky130_fd_pr__nfet_01v8", 7 ]
+ ], [
+ ["sky130_fd_pr__pfet_01v8_hvt", 7 ],
+ ["sky130_fd_pr__nfet_01v8", 7 ]
+ ]
+ ],
+ "nets": [
+ 15,
+ 15
+ ],
+ "badnets": [
+ ],
+ "badelements": [
+ ],
+ "pins": [
+ [
+ "VGND",
+ "X",
+ "D",
+ "C",
+ "B_N",
+ "A_N",
+ "VNB",
+ "VPWR",
+ "VPB"
+ ], [
+ "VGND",
+ "X",
+ "D",
+ "C",
+ "B_N",
+ "A_N",
+ "VNB",
+ "VPWR",
+ "VPB"
+ ]
+ ]
+ },
+ {
+ "name": [
+ "sky130_fd_sc_hd__inv_1",
+ "sky130_fd_sc_hd__inv_1"
+ ],
+ "devices": [
+ [
+ ["sky130_fd_pr__nfet_01v8", 1],
+ ["sky130_fd_pr__pfet_01v8_hvt", 1 ]
+ ], [
+ ["sky130_fd_pr__nfet_01v8", 1 ],
+ ["sky130_fd_pr__pfet_01v8_hvt", 1 ]
+ ]
+ ],
+ "nets": [
+ 6,
+ 6
+ ],
+ "badnets": [
+ ],
+ "badelements": [
+ ],
+ "pins": [
+ [
+ "VGND",
+ "VNB",
+ "VPWR",
+ "VPB",
+ "A",
+ "Y"
+ ], [
+ "VGND",
+ "VNB",
+ "VPWR",
+ "VPB",
+ "A",
+ "Y"
+ ]
+ ]
+ },
+ {
+ "name": [
+ "sky130_fd_sc_hd__dfxtp_1",
+ "sky130_fd_sc_hd__dfxtp_1"
+ ],
+ "devices": [
+ [
+ ["sky130_fd_pr__nfet_01v8", 12],
+ ["sky130_fd_pr__pfet_01v8_hvt", 12 ]
+ ], [
+ ["sky130_fd_pr__nfet_01v8", 12 ],
+ ["sky130_fd_pr__pfet_01v8_hvt", 12 ]
+ ]
+ ],
+ "nets": [
+ 18,
+ 18
+ ],
+ "badnets": [
+ ],
+ "badelements": [
+ ],
+ "pins": [
+ [
+ "VPB",
+ "VNB",
+ "VGND",
+ "VPWR",
+ "D",
+ "Q",
+ "CLK"
+ ], [
+ "VPB",
+ "VNB",
+ "VGND",
+ "VPWR",
+ "D",
+ "Q",
+ "CLK"
+ ]
+ ]
+ },
+ {
+ "name": [
+ "sky130_fd_sc_hd__and2_1",
+ "sky130_fd_sc_hd__and2_1"
+ ],
+ "devices": [
+ [
+ ["sky130_fd_pr__pfet_01v8_hvt", 3],
+ ["sky130_fd_pr__nfet_01v8", 3 ]
+ ], [
+ ["sky130_fd_pr__pfet_01v8_hvt", 3 ],
+ ["sky130_fd_pr__nfet_01v8", 3 ]
+ ]
+ ],
+ "nets": [
+ 9,
+ 9
+ ],
+ "badnets": [
+ ],
+ "badelements": [
+ ],
+ "pins": [
+ [
+ "VGND",
+ "X",
+ "A",
+ "B",
+ "VNB",
+ "VPWR",
+ "VPB"
+ ], [
+ "VGND",
+ "X",
+ "A",
+ "B",
+ "VNB",
+ "VPWR",
+ "VPB"
+ ]
+ ]
+ },
+ {
+ "name": [
+ "sky130_fd_sc_hd__diode_2",
+ "sky130_fd_sc_hd__diode_2"
+ ],
+ "devices": [
+ [
+ ["sky130_fd_pr__diode_pw2nd_05v5", 1 ]
+ ], [
+ ["sky130_fd_pr__diode_pw2nd_05v5", 1 ]
+ ]
+ ],
+ "nets": [
+ 2,
+ 2
+ ],
+ "badnets": [
+ ],
+ "badelements": [
+ ],
+ "pins": [
+ [
+ "VNB",
+ "DIODE",
+ "VGND",
+ "VPWR",
+ "VPB"
+ ], [
+ "VNB",
+ "DIODE",
+ "VGND",
+ "VPWR",
+ "VPB"
+ ]
+ ]
+ },
+ {
+ "name": [
+ "sky130_fd_sc_hd__decap_12",
+ "sky130_fd_sc_hd__decap_12"
+ ],
+ "devices": [
+ [
+ ["sky130_fd_pr__pfet_01v8_hvt", 1],
+ ["sky130_fd_pr__nfet_01v8", 1 ]
+ ], [
+ ["sky130_fd_pr__pfet_01v8_hvt", 1 ],
+ ["sky130_fd_pr__nfet_01v8", 1 ]
+ ]
+ ],
+ "nets": [
+ 4,
+ 4
+ ],
+ "badnets": [
+ ],
+ "badelements": [
+ ],
+ "pins": [
+ [
+ "VPB",
+ "VNB",
+ "VPWR",
+ "VGND"
+ ], [
+ "VPB",
+ "VNB",
+ "VPWR",
+ "VGND"
+ ]
+ ]
+ },
+ {
+ "name": [
+ "sky130_fd_sc_hd__decap_8",
+ "sky130_fd_sc_hd__decap_8"
+ ],
+ "devices": [
+ [
+ ["sky130_fd_pr__pfet_01v8_hvt", 1],
+ ["sky130_fd_pr__nfet_01v8", 1 ]
+ ], [
+ ["sky130_fd_pr__pfet_01v8_hvt", 1 ],
+ ["sky130_fd_pr__nfet_01v8", 1 ]
+ ]
+ ],
+ "nets": [
+ 4,
+ 4
+ ],
+ "badnets": [
+ ],
+ "badelements": [
+ ],
+ "pins": [
+ [
+ "VPB",
+ "VNB",
+ "VPWR",
+ "VGND"
+ ], [
+ "VPB",
+ "VNB",
+ "VPWR",
+ "VGND"
+ ]
+ ]
+ },
+ {
+ "name": [
+ "sky130_fd_sc_hd__clkbuf_2",
+ "sky130_fd_sc_hd__clkbuf_2"
+ ],
+ "devices": [
+ [
+ ["sky130_fd_pr__pfet_01v8_hvt", 2],
+ ["sky130_fd_pr__nfet_01v8", 2 ]
+ ], [
+ ["sky130_fd_pr__pfet_01v8_hvt", 2 ],
+ ["sky130_fd_pr__nfet_01v8", 2 ]
+ ]
+ ],
+ "nets": [
+ 7,
+ 7
+ ],
+ "badnets": [
+ ],
+ "badelements": [
+ ],
+ "pins": [
+ [
+ "A",
+ "VPWR",
+ "VPB",
+ "VGND",
+ "VNB",
+ "X"
+ ], [
+ "A",
+ "VPWR",
+ "VPB",
+ "VGND",
+ "VNB",
+ "X"
+ ]
+ ]
+ },
+ {
+ "name": [
+ "sky130_fd_sc_hd__clkbuf_16",
+ "sky130_fd_sc_hd__clkbuf_16"
+ ],
+ "devices": [
+ [
+ ["sky130_fd_pr__pfet_01v8_hvt", 2],
+ ["sky130_fd_pr__nfet_01v8", 2 ]
+ ], [
+ ["sky130_fd_pr__pfet_01v8_hvt", 2 ],
+ ["sky130_fd_pr__nfet_01v8", 2 ]
+ ]
+ ],
+ "nets": [
+ 7,
+ 7
+ ],
+ "badnets": [
+ ],
+ "badelements": [
+ ],
+ "pins": [
+ [
+ "VPWR",
+ "X",
+ "VPB",
+ "VGND",
+ "VNB",
+ "A"
+ ], [
+ "VPWR",
+ "X",
+ "VPB",
+ "VGND",
+ "VNB",
+ "A"
+ ]
+ ]
+ },
+ {
+ "name": [
+ "sky130_fd_sc_hd__decap_4",
+ "sky130_fd_sc_hd__decap_4"
+ ],
+ "devices": [
+ [
+ ["sky130_fd_pr__pfet_01v8_hvt", 1],
+ ["sky130_fd_pr__nfet_01v8", 1 ]
+ ], [
+ ["sky130_fd_pr__pfet_01v8_hvt", 1 ],
+ ["sky130_fd_pr__nfet_01v8", 1 ]
+ ]
+ ],
+ "nets": [
+ 4,
+ 4
+ ],
+ "badnets": [
+ ],
+ "badelements": [
+ ],
+ "pins": [
+ [
+ "VPB",
+ "VNB",
+ "VPWR",
+ "VGND"
+ ], [
+ "VPB",
+ "VNB",
+ "VPWR",
+ "VGND"
+ ]
+ ]
+ },
+ {
+ "name": [
+ "sky130_fd_sc_hd__decap_6",
+ "sky130_fd_sc_hd__decap_6"
+ ],
+ "devices": [
+ [
+ ["sky130_fd_pr__pfet_01v8_hvt", 1],
+ ["sky130_fd_pr__nfet_01v8", 1 ]
+ ], [
+ ["sky130_fd_pr__pfet_01v8_hvt", 1 ],
+ ["sky130_fd_pr__nfet_01v8", 1 ]
+ ]
+ ],
+ "nets": [
+ 4,
+ 4
+ ],
+ "badnets": [
+ ],
+ "badelements": [
+ ],
+ "pins": [
+ [
+ "VPB",
+ "VNB",
+ "VPWR",
+ "VGND"
+ ], [
+ "VPB",
+ "VNB",
+ "VPWR",
+ "VGND"
+ ]
+ ]
+ },
+ {
+ "name": [
+ "sky130_fd_sc_hd__decap_3",
+ "sky130_fd_sc_hd__decap_3"
+ ],
+ "devices": [
+ [
+ ["sky130_fd_pr__pfet_01v8_hvt", 1],
+ ["sky130_fd_pr__nfet_01v8", 1 ]
+ ], [
+ ["sky130_fd_pr__pfet_01v8_hvt", 1 ],
+ ["sky130_fd_pr__nfet_01v8", 1 ]
+ ]
+ ],
+ "nets": [
+ 4,
+ 4
+ ],
+ "badnets": [
+ ],
+ "badelements": [
+ ],
+ "pins": [
+ [
+ "VPB",
+ "VNB",
+ "VPWR",
+ "VGND"
+ ], [
+ "VPB",
+ "VNB",
+ "VPWR",
+ "VGND"
+ ]
+ ]
+ },
+ {
+ "name": [
+ "sky130_fd_sc_hd__and4b_2",
+ "sky130_fd_sc_hd__and4b_2"
+ ],
+ "devices": [
+ [
+ ["sky130_fd_pr__pfet_01v8_hvt", 6],
+ ["sky130_fd_pr__nfet_01v8", 6 ]
+ ], [
+ ["sky130_fd_pr__pfet_01v8_hvt", 6 ],
+ ["sky130_fd_pr__nfet_01v8", 6 ]
+ ]
+ ],
+ "nets": [
+ 14,
+ 14
+ ],
+ "badnets": [
+ ],
+ "badelements": [
+ ],
+ "pins": [
+ [
+ "VGND",
+ "X",
+ "D",
+ "A_N",
+ "C",
+ "B",
+ "VPWR",
+ "VPB",
+ "VNB"
+ ], [
+ "VGND",
+ "X",
+ "D",
+ "A_N",
+ "C",
+ "B",
+ "VPWR",
+ "VPB",
+ "VNB"
+ ]
+ ]
+ },
+ {
+ "name": [
+ "sky130_fd_sc_hd__mux4_1",
+ "sky130_fd_sc_hd__mux4_1"
+ ],
+ "devices": [
+ [
+ ["sky130_fd_pr__pfet_01v8_hvt", 13],
+ ["sky130_fd_pr__nfet_01v8", 13 ]
+ ], [
+ ["sky130_fd_pr__pfet_01v8_hvt", 13 ],
+ ["sky130_fd_pr__nfet_01v8", 13 ]
+ ]
+ ],
+ "nets": [
+ 24,
+ 24
+ ],
+ "badnets": [
+ ],
+ "badelements": [
+ ],
+ "pins": [
+ [
+ "S1",
+ "VPWR",
+ "VGND",
+ "VPB",
+ "VNB",
+ "X",
+ "A1",
+ "A3",
+ "A0",
+ "A2",
+ "S0"
+ ], [
+ "S1",
+ "VPWR",
+ "VGND",
+ "VPB",
+ "VNB",
+ "X",
+ "A1",
+ "A3",
+ "A0",
+ "A2",
+ "S0"
+ ]
+ ]
+ },
+ {
+ "name": [
+ "sky130_fd_sc_hd__conb_1",
+ "sky130_fd_sc_hd__conb_1"
+ ],
+ "devices": [
+ [
+ ["sky130_fd_pr__res_generic_po", 2 ]
+ ], [
+ ["sky130_fd_pr__res_generic_po", 2 ]
+ ]
+ ],
+ "nets": [
+ 4,
+ 4
+ ],
+ "badnets": [
+ ],
+ "badelements": [
+ ],
+ "pins": [
+ [
+ "VGND",
+ "LO",
+ "HI",
+ "VPWR",
+ "VPB",
+ "VNB"
+ ], [
+ "VGND",
+ "LO",
+ "HI",
+ "VPWR",
+ "VPB",
+ "VNB"
+ ]
+ ]
+ },
+ {
+ "name": [
+ "sky130_fd_sc_hd__and4_2",
+ "sky130_fd_sc_hd__and4_2"
+ ],
+ "devices": [
+ [
+ ["sky130_fd_pr__nfet_01v8", 5],
+ ["sky130_fd_pr__pfet_01v8_hvt", 5 ]
+ ], [
+ ["sky130_fd_pr__nfet_01v8", 5 ],
+ ["sky130_fd_pr__pfet_01v8_hvt", 5 ]
+ ]
+ ],
+ "nets": [
+ 13,
+ 13
+ ],
+ "badnets": [
+ ],
+ "badelements": [
+ ],
+ "pins": [
+ [
+ "VPWR",
+ "VPB",
+ "VNB",
+ "VGND",
+ "X",
+ "A",
+ "C",
+ "B",
+ "D"
+ ], [
+ "VPWR",
+ "VPB",
+ "VNB",
+ "VGND",
+ "X",
+ "A",
+ "C",
+ "B",
+ "D"
+ ]
+ ]
+ },
+ {
+ "name": [
+ "sky130_fd_sc_hd__nor4b_2",
+ "sky130_fd_sc_hd__nor4b_2"
+ ],
+ "devices": [
+ [
+ ["sky130_fd_pr__pfet_01v8_hvt", 5],
+ ["sky130_fd_pr__nfet_01v8", 5 ]
+ ], [
+ ["sky130_fd_pr__pfet_01v8_hvt", 5 ],
+ ["sky130_fd_pr__nfet_01v8", 5 ]
+ ]
+ ],
+ "nets": [
+ 13,
+ 13
+ ],
+ "badnets": [
+ ],
+ "badelements": [
+ ],
+ "pins": [
+ [
+ "VPB",
+ "Y",
+ "VGND",
+ "VNB",
+ "D_N",
+ "VPWR",
+ "A",
+ "C",
+ "B"
+ ], [
+ "VPB",
+ "Y",
+ "VGND",
+ "VNB",
+ "D_N",
+ "VPWR",
+ "A",
+ "C",
+ "B"
+ ]
+ ]
+ },
+ {
+ "name": [
+ "sky130_fd_sc_hd__nor3b_2",
+ "sky130_fd_sc_hd__nor3b_2"
+ ],
+ "devices": [
+ [
+ ["sky130_fd_pr__pfet_01v8_hvt", 4],
+ ["sky130_fd_pr__nfet_01v8", 4 ]
+ ], [
+ ["sky130_fd_pr__pfet_01v8_hvt", 4 ],
+ ["sky130_fd_pr__nfet_01v8", 4 ]
+ ]
+ ],
+ "nets": [
+ 11,
+ 11
+ ],
+ "badnets": [
+ ],
+ "badelements": [
+ ],
+ "pins": [
+ [
+ "Y",
+ "VGND",
+ "VNB",
+ "VPB",
+ "VPWR",
+ "A",
+ "B",
+ "C_N"
+ ], [
+ "Y",
+ "VGND",
+ "VNB",
+ "VPB",
+ "VPWR",
+ "A",
+ "B",
+ "C_N"
+ ]
+ ]
+ },
+ {
+ "name": [
+ "sky130_fd_sc_hd__and3b_2",
+ "sky130_fd_sc_hd__and3b_2"
+ ],
+ "devices": [
+ [
+ ["sky130_fd_pr__pfet_01v8_hvt", 5],
+ ["sky130_fd_pr__nfet_01v8", 5 ]
+ ], [
+ ["sky130_fd_pr__pfet_01v8_hvt", 5 ],
+ ["sky130_fd_pr__nfet_01v8", 5 ]
+ ]
+ ],
+ "nets": [
+ 12,
+ 12
+ ],
+ "badnets": [
+ ],
+ "badelements": [
+ ],
+ "pins": [
+ [
+ "VGND",
+ "VNB",
+ "VPWR",
+ "VPB",
+ "C",
+ "X",
+ "B",
+ "A_N"
+ ], [
+ "VGND",
+ "VNB",
+ "VPWR",
+ "VPB",
+ "C",
+ "X",
+ "B",
+ "A_N"
+ ]
+ ]
+ },
+ {
+ "name": [
+ "sky130_fd_sc_hd__and3_2",
+ "sky130_fd_sc_hd__and3_2"
+ ],
+ "devices": [
+ [
+ ["sky130_fd_pr__pfet_01v8_hvt", 4],
+ ["sky130_fd_pr__nfet_01v8", 4 ]
+ ], [
+ ["sky130_fd_pr__pfet_01v8_hvt", 4 ],
+ ["sky130_fd_pr__nfet_01v8", 4 ]
+ ]
+ ],
+ "nets": [
+ 11,
+ 11
+ ],
+ "badnets": [
+ ],
+ "badelements": [
+ ],
+ "pins": [
+ [
+ "X",
+ "VGND",
+ "A",
+ "C",
+ "B",
+ "VNB",
+ "VPWR",
+ "VPB"
+ ], [
+ "X",
+ "VGND",
+ "A",
+ "C",
+ "B",
+ "VNB",
+ "VPWR",
+ "VPB"
+ ]
+ ]
+ },
+ {
+ "name": [
+ "sky130_fd_sc_hd__mux2_1",
+ "sky130_fd_sc_hd__mux2_1"
+ ],
+ "devices": [
+ [
+ ["sky130_fd_pr__pfet_01v8_hvt", 6],
+ ["sky130_fd_pr__nfet_01v8", 6 ]
+ ], [
+ ["sky130_fd_pr__pfet_01v8_hvt", 6 ],
+ ["sky130_fd_pr__nfet_01v8", 6 ]
+ ]
+ ],
+ "nets": [
+ 14,
+ 14
+ ],
+ "badnets": [
+ ],
+ "badelements": [
+ ],
+ "pins": [
+ [
+ "VPB",
+ "VNB",
+ "A0",
+ "A1",
+ "X",
+ "VPWR",
+ "S",
+ "VGND"
+ ], [
+ "VPB",
+ "VNB",
+ "A0",
+ "A1",
+ "X",
+ "VPWR",
+ "S",
+ "VGND"
+ ]
+ ]
+ },
+ {
+ "name": [
+ "sky130_fd_sc_hd__and2b_2",
+ "sky130_fd_sc_hd__and2b_2"
+ ],
+ "devices": [
+ [
+ ["sky130_fd_pr__pfet_01v8_hvt", 4],
+ ["sky130_fd_pr__nfet_01v8", 4 ]
+ ], [
+ ["sky130_fd_pr__pfet_01v8_hvt", 4 ],
+ ["sky130_fd_pr__nfet_01v8", 4 ]
+ ]
+ ],
+ "nets": [
+ 10,
+ 10
+ ],
+ "badnets": [
+ ],
+ "badelements": [
+ ],
+ "pins": [
+ [
+ "VGND",
+ "X",
+ "B",
+ "A_N",
+ "VPWR",
+ "VPB",
+ "VNB"
+ ], [
+ "VGND",
+ "X",
+ "B",
+ "A_N",
+ "VPWR",
+ "VPB",
+ "VNB"
+ ]
+ ]
+ },
+ {
+ "name": [
+ "sky130_fd_sc_hd__and2_2",
+ "sky130_fd_sc_hd__and2_2"
+ ],
+ "devices": [
+ [
+ ["sky130_fd_pr__pfet_01v8_hvt", 3],
+ ["sky130_fd_pr__nfet_01v8", 3 ]
+ ], [
+ ["sky130_fd_pr__pfet_01v8_hvt", 3 ],
+ ["sky130_fd_pr__nfet_01v8", 3 ]
+ ]
+ ],
+ "nets": [
+ 9,
+ 9
+ ],
+ "badnets": [
+ ],
+ "badelements": [
+ ],
+ "pins": [
+ [
+ "VPWR",
+ "VPB",
+ "VNB",
+ "X",
+ "A",
+ "B",
+ "VGND"
+ ], [
+ "VPWR",
+ "VPB",
+ "VNB",
+ "X",
+ "A",
+ "B",
+ "VGND"
+ ]
+ ]
+ },
+ {
+ "name": [
+ "sky130_ef_sc_hd__decap_12",
+ "sky130_ef_sc_hd__decap_12"
+ ],
+ "devices": [
+ [
+ ["sky130_fd_pr__pfet_01v8_hvt", 1],
+ ["sky130_fd_pr__nfet_01v8", 1 ]
+ ], [
+ ["sky130_fd_pr__pfet_01v8_hvt", 1 ],
+ ["sky130_fd_pr__nfet_01v8", 1 ]
+ ]
+ ],
+ "nets": [
+ 4,
+ 4
+ ],
+ "badnets": [
+ ],
+ "badelements": [
+ ],
+ "pins": [
+ [
+ "VPB",
+ "VNB",
+ "VPWR",
+ "VGND"
+ ], [
+ "VPB",
+ "VNB",
+ "VPWR",
+ "VGND"
+ ]
+ ]
+ },
+ {
+ "name": [
+ "sky130_fd_sc_hd__a211o_1",
+ "sky130_fd_sc_hd__a211o_1"
+ ],
+ "devices": [
+ [
+ ["sky130_fd_pr__pfet_01v8_hvt", 5],
+ ["sky130_fd_pr__nfet_01v8", 5 ]
+ ], [
+ ["sky130_fd_pr__pfet_01v8_hvt", 5 ],
+ ["sky130_fd_pr__nfet_01v8", 5 ]
+ ]
+ ],
+ "nets": [
+ 13,
+ 13
+ ],
+ "badnets": [
+ ],
+ "badelements": [
+ ],
+ "pins": [
+ [
+ "VGND",
+ "VNB",
+ "VPB",
+ "A2",
+ "X",
+ "A1",
+ "B1",
+ "C1",
+ "VPWR"
+ ], [
+ "VGND",
+ "VNB",
+ "VPB",
+ "A2",
+ "X",
+ "A1",
+ "B1",
+ "C1",
+ "VPWR"
+ ]
+ ]
+ },
+ {
+ "name": [
+ "sky130_fd_sc_hd__a211oi_2",
+ "sky130_fd_sc_hd__a211oi_2"
+ ],
+ "devices": [
+ [
+ ["sky130_fd_pr__nfet_01v8", 4],
+ ["sky130_fd_pr__pfet_01v8_hvt", 4 ]
+ ], [
+ ["sky130_fd_pr__nfet_01v8", 4 ],
+ ["sky130_fd_pr__pfet_01v8_hvt", 4 ]
+ ]
+ ],
+ "nets": [
+ 12,
+ 12
+ ],
+ "badnets": [
+ ],
+ "badelements": [
+ ],
+ "pins": [
+ [
+ "VPB",
+ "Y",
+ "VNB",
+ "B1",
+ "C1",
+ "VPWR",
+ "A2",
+ "A1",
+ "VGND"
+ ], [
+ "VPB",
+ "Y",
+ "VNB",
+ "B1",
+ "C1",
+ "VPWR",
+ "A2",
+ "A1",
+ "VGND"
+ ]
+ ]
+ },
+ {
+ "name": [
+ "sky130_fd_sc_hd__o211a_1",
+ "sky130_fd_sc_hd__o211a_1"
+ ],
+ "devices": [
+ [
+ ["sky130_fd_pr__nfet_01v8", 5],
+ ["sky130_fd_pr__pfet_01v8_hvt", 5 ]
+ ], [
+ ["sky130_fd_pr__nfet_01v8", 5 ],
+ ["sky130_fd_pr__pfet_01v8_hvt", 5 ]
+ ]
+ ],
+ "nets": [
+ 13,
+ 13
+ ],
+ "badnets": [
+ ],
+ "badelements": [
+ ],
+ "pins": [
+ [
+ "VPWR",
+ "VPB",
+ "VNB",
+ "C1",
+ "A1",
+ "B1",
+ "A2",
+ "X",
+ "VGND"
+ ], [
+ "VPWR",
+ "VPB",
+ "VNB",
+ "C1",
+ "A1",
+ "B1",
+ "A2",
+ "X",
+ "VGND"
+ ]
+ ]
+ },
+ {
+ "name": [
+ "sky130_fd_sc_hd__and4b_1",
+ "sky130_fd_sc_hd__and4b_1"
+ ],
+ "devices": [
+ [
+ ["sky130_fd_pr__nfet_01v8", 6],
+ ["sky130_fd_pr__pfet_01v8_hvt", 6 ]
+ ], [
+ ["sky130_fd_pr__nfet_01v8", 6 ],
+ ["sky130_fd_pr__pfet_01v8_hvt", 6 ]
+ ]
+ ],
+ "nets": [
+ 14,
+ 14
+ ],
+ "badnets": [
+ ],
+ "badelements": [
+ ],
+ "pins": [
+ [
+ "VGND",
+ "VPWR",
+ "VPB",
+ "VNB",
+ "X",
+ "D",
+ "A_N",
+ "C",
+ "B"
+ ], [
+ "VGND",
+ "VPWR",
+ "VPB",
+ "VNB",
+ "X",
+ "D",
+ "A_N",
+ "C",
+ "B"
+ ]
+ ]
+ },
+ {
+ "name": [
+ "sky130_fd_sc_hd__o41a_1",
+ "sky130_fd_sc_hd__o41a_1"
+ ],
+ "devices": [
+ [
+ ["sky130_fd_pr__nfet_01v8", 6],
+ ["sky130_fd_pr__pfet_01v8_hvt", 6 ]
+ ], [
+ ["sky130_fd_pr__nfet_01v8", 6 ],
+ ["sky130_fd_pr__pfet_01v8_hvt", 6 ]
+ ]
+ ],
+ "nets": [
+ 15,
+ 15
+ ],
+ "badnets": [
+ ],
+ "badelements": [
+ ],
+ "pins": [
+ [
+ "VPWR",
+ "VPB",
+ "VNB",
+ "A2",
+ "A3",
+ "A4",
+ "B1",
+ "A1",
+ "X",
+ "VGND"
+ ], [
+ "VPWR",
+ "VPB",
+ "VNB",
+ "A2",
+ "A3",
+ "A4",
+ "B1",
+ "A1",
+ "X",
+ "VGND"
+ ]
+ ]
+ },
+ {
+ "name": [
+ "sky130_fd_sc_hd__a221o_1",
+ "sky130_fd_sc_hd__a221o_1"
+ ],
+ "devices": [
+ [
+ ["sky130_fd_pr__nfet_01v8", 6],
+ ["sky130_fd_pr__pfet_01v8_hvt", 6 ]
+ ], [
+ ["sky130_fd_pr__nfet_01v8", 6 ],
+ ["sky130_fd_pr__pfet_01v8_hvt", 6 ]
+ ]
+ ],
+ "nets": [
+ 15,
+ 15
+ ],
+ "badnets": [
+ ],
+ "badelements": [
+ ],
+ "pins": [
+ [
+ "VGND",
+ "VPWR",
+ "VPB",
+ "VNB",
+ "X",
+ "B1",
+ "A1",
+ "C1",
+ "A2",
+ "B2"
+ ], [
+ "VGND",
+ "VPWR",
+ "VPB",
+ "VNB",
+ "X",
+ "B1",
+ "A1",
+ "C1",
+ "A2",
+ "B2"
+ ]
+ ]
+ },
+ {
+ "name": [
+ "sky130_fd_sc_hd__a32o_1",
+ "sky130_fd_sc_hd__a32o_1"
+ ],
+ "devices": [
+ [
+ ["sky130_fd_pr__nfet_01v8", 6],
+ ["sky130_fd_pr__pfet_01v8_hvt", 6 ]
+ ], [
+ ["sky130_fd_pr__nfet_01v8", 6 ],
+ ["sky130_fd_pr__pfet_01v8_hvt", 6 ]
+ ]
+ ],
+ "nets": [
+ 15,
+ 15
+ ],
+ "badnets": [
+ ],
+ "badelements": [
+ ],
+ "pins": [
+ [
+ "VGND",
+ "VPWR",
+ "B2",
+ "X",
+ "B1",
+ "A2",
+ "A3",
+ "A1",
+ "VPB",
+ "VNB"
+ ], [
+ "VGND",
+ "VPWR",
+ "B2",
+ "X",
+ "B1",
+ "A2",
+ "A3",
+ "A1",
+ "VPB",
+ "VNB"
+ ]
+ ]
+ },
+ {
+ "name": [
+ "sky130_fd_sc_hd__nor2_1",
+ "sky130_fd_sc_hd__nor2_1"
+ ],
+ "devices": [
+ [
+ ["sky130_fd_pr__pfet_01v8_hvt", 2],
+ ["sky130_fd_pr__nfet_01v8", 2 ]
+ ], [
+ ["sky130_fd_pr__pfet_01v8_hvt", 2 ],
+ ["sky130_fd_pr__nfet_01v8", 2 ]
+ ]
+ ],
+ "nets": [
+ 8,
+ 8
+ ],
+ "badnets": [
+ ],
+ "badelements": [
+ ],
+ "pins": [
+ [
+ "Y",
+ "A",
+ "VPB",
+ "VGND",
+ "VNB",
+ "B",
+ "VPWR"
+ ], [
+ "Y",
+ "A",
+ "VPB",
+ "VGND",
+ "VNB",
+ "B",
+ "VPWR"
+ ]
+ ]
+ },
+ {
+ "name": [
+ "sky130_fd_sc_hd__o31a_1",
+ "sky130_fd_sc_hd__o31a_1"
+ ],
+ "devices": [
+ [
+ ["sky130_fd_pr__nfet_01v8", 5],
+ ["sky130_fd_pr__pfet_01v8_hvt", 5 ]
+ ], [
+ ["sky130_fd_pr__nfet_01v8", 5 ],
+ ["sky130_fd_pr__pfet_01v8_hvt", 5 ]
+ ]
+ ],
+ "nets": [
+ 13,
+ 13
+ ],
+ "badnets": [
+ ],
+ "badelements": [
+ ],
+ "pins": [
+ [
+ "VPWR",
+ "VGND",
+ "A2",
+ "A1",
+ "X",
+ "B1",
+ "A3",
+ "VNB",
+ "VPB"
+ ], [
+ "VPWR",
+ "VGND",
+ "A2",
+ "A1",
+ "X",
+ "B1",
+ "A3",
+ "VNB",
+ "VPB"
+ ]
+ ]
+ },
+ {
+ "name": [
+ "sky130_fd_sc_hd__dlygate4sd3_1",
+ "sky130_fd_sc_hd__dlygate4sd3_1"
+ ],
+ "devices": [
+ [
+ ["sky130_fd_pr__pfet_01v8_hvt", 4],
+ ["sky130_fd_pr__nfet_01v8", 4 ]
+ ], [
+ ["sky130_fd_pr__pfet_01v8_hvt", 4 ],
+ ["sky130_fd_pr__nfet_01v8", 4 ]
+ ]
+ ],
+ "nets": [
+ 9,
+ 9
+ ],
+ "badnets": [
+ ],
+ "badelements": [
+ ],
+ "pins": [
+ [
+ "A",
+ "X",
+ "VGND",
+ "VNB",
+ "VPWR",
+ "VPB"
+ ], [
+ "A",
+ "X",
+ "VGND",
+ "VNB",
+ "VPWR",
+ "VPB"
+ ]
+ ]
+ },
+ {
+ "name": [
+ "sky130_fd_sc_hd__dfxtp_4",
+ "sky130_fd_sc_hd__dfxtp_4"
+ ],
+ "devices": [
+ [
+ ["sky130_fd_pr__pfet_01v8_hvt", 12],
+ ["sky130_fd_pr__nfet_01v8", 12 ]
+ ], [
+ ["sky130_fd_pr__pfet_01v8_hvt", 12 ],
+ ["sky130_fd_pr__nfet_01v8", 12 ]
+ ]
+ ],
+ "nets": [
+ 18,
+ 18
+ ],
+ "badnets": [
+ ],
+ "badelements": [
+ ],
+ "pins": [
+ [
+ "VPB",
+ "VNB",
+ "VGND",
+ "VPWR",
+ "Q",
+ "D",
+ "CLK"
+ ], [
+ "VPB",
+ "VNB",
+ "VGND",
+ "VPWR",
+ "Q",
+ "D",
+ "CLK"
+ ]
+ ]
+ },
+ {
+ "name": [
+ "sky130_fd_sc_hd__buf_6",
+ "sky130_fd_sc_hd__buf_6"
+ ],
+ "devices": [
+ [
+ ["sky130_fd_pr__pfet_01v8_hvt", 2],
+ ["sky130_fd_pr__nfet_01v8", 2 ]
+ ], [
+ ["sky130_fd_pr__pfet_01v8_hvt", 2 ],
+ ["sky130_fd_pr__nfet_01v8", 2 ]
+ ]
+ ],
+ "nets": [
+ 7,
+ 7
+ ],
+ "badnets": [
+ ],
+ "badelements": [
+ ],
+ "pins": [
+ [
+ "VGND",
+ "X",
+ "VNB",
+ "A",
+ "VPWR",
+ "VPB"
+ ], [
+ "VGND",
+ "X",
+ "VNB",
+ "A",
+ "VPWR",
+ "VPB"
+ ]
+ ]
+ },
+ {
+ "name": [
+ "sky130_fd_sc_hd__buf_12",
+ "sky130_fd_sc_hd__buf_12"
+ ],
+ "devices": [
+ [
+ ["sky130_fd_pr__nfet_01v8", 2],
+ ["sky130_fd_pr__pfet_01v8_hvt", 2 ]
+ ], [
+ ["sky130_fd_pr__nfet_01v8", 2 ],
+ ["sky130_fd_pr__pfet_01v8_hvt", 2 ]
+ ]
+ ],
+ "nets": [
+ 7,
+ 7
+ ],
+ "badnets": [
+ ],
+ "badelements": [
+ ],
+ "pins": [
+ [
+ "X",
+ "VPWR",
+ "VPB",
+ "VGND",
+ "VNB",
+ "A"
+ ], [
+ "X",
+ "VPWR",
+ "VPB",
+ "VGND",
+ "VNB",
+ "A"
+ ]
+ ]
+ },
+ {
+ "name": [
+ "sky130_fd_sc_hd__or4b_4",
+ "sky130_fd_sc_hd__or4b_4"
+ ],
+ "devices": [
+ [
+ ["sky130_fd_pr__pfet_01v8_hvt", 6],
+ ["sky130_fd_pr__nfet_01v8", 6 ]
+ ], [
+ ["sky130_fd_pr__pfet_01v8_hvt", 6 ],
+ ["sky130_fd_pr__nfet_01v8", 6 ]
+ ]
+ ],
+ "nets": [
+ 14,
+ 14
+ ],
+ "badnets": [
+ ],
+ "badelements": [
+ ],
+ "pins": [
+ [
+ "VPB",
+ "VGND",
+ "VNB",
+ "VPWR",
+ "X",
+ "B",
+ "C",
+ "A",
+ "D_N"
+ ], [
+ "VPB",
+ "VGND",
+ "VNB",
+ "VPWR",
+ "X",
+ "B",
+ "C",
+ "A",
+ "D_N"
+ ]
+ ]
+ },
+ {
+ "name": [
+ "sky130_fd_sc_hd__buf_8",
+ "sky130_fd_sc_hd__buf_8"
+ ],
+ "devices": [
+ [
+ ["sky130_fd_pr__nfet_01v8", 2],
+ ["sky130_fd_pr__pfet_01v8_hvt", 2 ]
+ ], [
+ ["sky130_fd_pr__nfet_01v8", 2 ],
+ ["sky130_fd_pr__pfet_01v8_hvt", 2 ]
+ ]
+ ],
+ "nets": [
+ 7,
+ 7
+ ],
+ "badnets": [
+ ],
+ "badelements": [
+ ],
+ "pins": [
+ [
+ "X",
+ "VGND",
+ "VNB",
+ "VPWR",
+ "VPB",
+ "A"
+ ], [
+ "X",
+ "VGND",
+ "VNB",
+ "VPWR",
+ "VPB",
+ "A"
+ ]
+ ]
+ },
+ {
+ "name": [
+ "sky130_fd_sc_hd__nand2_1",
+ "sky130_fd_sc_hd__nand2_1"
+ ],
+ "devices": [
+ [
+ ["sky130_fd_pr__pfet_01v8_hvt", 2],
+ ["sky130_fd_pr__nfet_01v8", 2 ]
+ ], [
+ ["sky130_fd_pr__pfet_01v8_hvt", 2 ],
+ ["sky130_fd_pr__nfet_01v8", 2 ]
+ ]
+ ],
+ "nets": [
+ 8,
+ 8
+ ],
+ "badnets": [
+ ],
+ "badelements": [
+ ],
+ "pins": [
+ [
+ "VGND",
+ "Y",
+ "A",
+ "VPWR",
+ "VPB",
+ "B",
+ "VNB"
+ ], [
+ "VGND",
+ "Y",
+ "A",
+ "VPWR",
+ "VPB",
+ "B",
+ "VNB"
+ ]
+ ]
+ },
+ {
+ "name": [
+ "sky130_fd_sc_hd__buf_4",
+ "sky130_fd_sc_hd__buf_4"
+ ],
+ "devices": [
+ [
+ ["sky130_fd_pr__pfet_01v8_hvt", 2],
+ ["sky130_fd_pr__nfet_01v8", 2 ]
+ ], [
+ ["sky130_fd_pr__pfet_01v8_hvt", 2 ],
+ ["sky130_fd_pr__nfet_01v8", 2 ]
+ ]
+ ],
+ "nets": [
+ 7,
+ 7
+ ],
+ "badnets": [
+ ],
+ "badelements": [
+ ],
+ "pins": [
+ [
+ "X",
+ "VGND",
+ "VNB",
+ "VPWR",
+ "VPB",
+ "A"
+ ], [
+ "X",
+ "VGND",
+ "VNB",
+ "VPWR",
+ "VPB",
+ "A"
+ ]
+ ]
+ },
+ {
+ "name": [
+ "sky130_fd_sc_hd__a31o_1",
+ "sky130_fd_sc_hd__a31o_1"
+ ],
+ "devices": [
+ [
+ ["sky130_fd_pr__pfet_01v8_hvt", 5],
+ ["sky130_fd_pr__nfet_01v8", 5 ]
+ ], [
+ ["sky130_fd_pr__pfet_01v8_hvt", 5 ],
+ ["sky130_fd_pr__nfet_01v8", 5 ]
+ ]
+ ],
+ "nets": [
+ 13,
+ 13
+ ],
+ "badnets": [
+ ],
+ "badelements": [
+ ],
+ "pins": [
+ [
+ "VGND",
+ "B1",
+ "X",
+ "A2",
+ "A1",
+ "A3",
+ "VNB",
+ "VPB",
+ "VPWR"
+ ], [
+ "VGND",
+ "B1",
+ "X",
+ "A2",
+ "A1",
+ "A3",
+ "VNB",
+ "VPB",
+ "VPWR"
+ ]
+ ]
+ },
+ {
+ "name": [
+ "sky130_fd_sc_hd__a21bo_1",
+ "sky130_fd_sc_hd__a21bo_1"
+ ],
+ "devices": [
+ [
+ ["sky130_fd_pr__pfet_01v8_hvt", 5],
+ ["sky130_fd_pr__nfet_01v8", 5 ]
+ ], [
+ ["sky130_fd_pr__pfet_01v8_hvt", 5 ],
+ ["sky130_fd_pr__nfet_01v8", 5 ]
+ ]
+ ],
+ "nets": [
+ 12,
+ 12
+ ],
+ "badnets": [
+ ],
+ "badelements": [
+ ],
+ "pins": [
+ [
+ "X",
+ "A2",
+ "A1",
+ "B1_N",
+ "VPB",
+ "VNB",
+ "VPWR",
+ "VGND"
+ ], [
+ "X",
+ "A2",
+ "A1",
+ "B1_N",
+ "VPB",
+ "VNB",
+ "VPWR",
+ "VGND"
+ ]
+ ]
+ },
+ {
+ "name": [
+ "sky130_fd_sc_hd__o21a_1",
+ "sky130_fd_sc_hd__o21a_1"
+ ],
+ "devices": [
+ [
+ ["sky130_fd_pr__pfet_01v8_hvt", 4],
+ ["sky130_fd_pr__nfet_01v8", 4 ]
+ ], [
+ ["sky130_fd_pr__pfet_01v8_hvt", 4 ],
+ ["sky130_fd_pr__nfet_01v8", 4 ]
+ ]
+ ],
+ "nets": [
+ 11,
+ 11
+ ],
+ "badnets": [
+ ],
+ "badelements": [
+ ],
+ "pins": [
+ [
+ "VPB",
+ "VNB",
+ "A1",
+ "B1",
+ "X",
+ "A2",
+ "VPWR",
+ "VGND"
+ ], [
+ "VPB",
+ "VNB",
+ "A1",
+ "B1",
+ "X",
+ "A2",
+ "VPWR",
+ "VGND"
+ ]
+ ]
+ },
+ {
+ "name": [
+ "sky130_fd_sc_hd__a31o_4",
+ "sky130_fd_sc_hd__a31o_4"
+ ],
+ "devices": [
+ [
+ ["sky130_fd_pr__pfet_01v8_hvt", 5],
+ ["sky130_fd_pr__nfet_01v8", 8 ]
+ ], [
+ ["sky130_fd_pr__pfet_01v8_hvt", 5 ],
+ ["sky130_fd_pr__nfet_01v8", 8 ]
+ ]
+ ],
+ "nets": [
+ 15,
+ 15
+ ],
+ "badnets": [
+ ],
+ "badelements": [
+ ],
+ "pins": [
+ [
+ "VNB",
+ "A2",
+ "A1",
+ "A3",
+ "VPB",
+ "B1",
+ "X",
+ "VGND",
+ "VPWR"
+ ], [
+ "VNB",
+ "A2",
+ "A1",
+ "A3",
+ "VPB",
+ "B1",
+ "X",
+ "VGND",
+ "VPWR"
+ ]
+ ]
+ },
+ {
+ "name": [
+ "sky130_fd_sc_hd__and3_4",
+ "sky130_fd_sc_hd__and3_4"
+ ],
+ "devices": [
+ [
+ ["sky130_fd_pr__pfet_01v8_hvt", 4],
+ ["sky130_fd_pr__nfet_01v8", 4 ]
+ ], [
+ ["sky130_fd_pr__pfet_01v8_hvt", 4 ],
+ ["sky130_fd_pr__nfet_01v8", 4 ]
+ ]
+ ],
+ "nets": [
+ 11,
+ 11
+ ],
+ "badnets": [
+ ],
+ "badelements": [
+ ],
+ "pins": [
+ [
+ "X",
+ "VGND",
+ "A",
+ "C",
+ "B",
+ "VNB",
+ "VPWR",
+ "VPB"
+ ], [
+ "X",
+ "VGND",
+ "A",
+ "C",
+ "B",
+ "VNB",
+ "VPWR",
+ "VPB"
+ ]
+ ]
+ },
+ {
+ "name": [
+ "sky130_fd_sc_hd__a211oi_4",
+ "sky130_fd_sc_hd__a211oi_4"
+ ],
+ "devices": [
+ [
+ ["sky130_fd_pr__nfet_01v8", 4],
+ ["sky130_fd_pr__pfet_01v8_hvt", 8 ]
+ ], [
+ ["sky130_fd_pr__nfet_01v8", 4 ],
+ ["sky130_fd_pr__pfet_01v8_hvt", 8 ]
+ ]
+ ],
+ "nets": [
+ 14,
+ 14
+ ],
+ "badnets": [
+ ],
+ "badelements": [
+ ],
+ "pins": [
+ [
+ "VPB",
+ "VGND",
+ "C1",
+ "VNB",
+ "B1",
+ "A1",
+ "VPWR",
+ "A2",
+ "Y"
+ ], [
+ "VPB",
+ "VGND",
+ "C1",
+ "VNB",
+ "B1",
+ "A1",
+ "VPWR",
+ "A2",
+ "Y"
+ ]
+ ]
+ },
+ {
+ "name": [
+ "sky130_fd_sc_hd__o221a_1",
+ "sky130_fd_sc_hd__o221a_1"
+ ],
+ "devices": [
+ [
+ ["sky130_fd_pr__nfet_01v8", 6],
+ ["sky130_fd_pr__pfet_01v8_hvt", 6 ]
+ ], [
+ ["sky130_fd_pr__nfet_01v8", 6 ],
+ ["sky130_fd_pr__pfet_01v8_hvt", 6 ]
+ ]
+ ],
+ "nets": [
+ 15,
+ 15
+ ],
+ "badnets": [
+ ],
+ "badelements": [
+ ],
+ "pins": [
+ [
+ "VPB",
+ "VNB",
+ "VGND",
+ "X",
+ "B1",
+ "A1",
+ "C1",
+ "B2",
+ "A2",
+ "VPWR"
+ ], [
+ "VPB",
+ "VNB",
+ "VGND",
+ "X",
+ "B1",
+ "A1",
+ "C1",
+ "B2",
+ "A2",
+ "VPWR"
+ ]
+ ]
+ },
+ {
+ "name": [
+ "sky130_fd_sc_hd__o311a_1",
+ "sky130_fd_sc_hd__o311a_1"
+ ],
+ "devices": [
+ [
+ ["sky130_fd_pr__nfet_01v8", 6],
+ ["sky130_fd_pr__pfet_01v8_hvt", 6 ]
+ ], [
+ ["sky130_fd_pr__nfet_01v8", 6 ],
+ ["sky130_fd_pr__pfet_01v8_hvt", 6 ]
+ ]
+ ],
+ "nets": [
+ 15,
+ 15
+ ],
+ "badnets": [
+ ],
+ "badelements": [
+ ],
+ "pins": [
+ [
+ "VNB",
+ "VPB",
+ "VGND",
+ "VPWR",
+ "B1",
+ "A1",
+ "C1",
+ "A2",
+ "X",
+ "A3"
+ ], [
+ "VNB",
+ "VPB",
+ "VGND",
+ "VPWR",
+ "B1",
+ "A1",
+ "C1",
+ "A2",
+ "X",
+ "A3"
+ ]
+ ]
+ },
+ {
+ "name": [
+ "sky130_fd_sc_hd__a21o_1",
+ "sky130_fd_sc_hd__a21o_1"
+ ],
+ "devices": [
+ [
+ ["sky130_fd_pr__nfet_01v8", 4],
+ ["sky130_fd_pr__pfet_01v8_hvt", 4 ]
+ ], [
+ ["sky130_fd_pr__nfet_01v8", 4 ],
+ ["sky130_fd_pr__pfet_01v8_hvt", 4 ]
+ ]
+ ],
+ "nets": [
+ 11,
+ 11
+ ],
+ "badnets": [
+ ],
+ "badelements": [
+ ],
+ "pins": [
+ [
+ "VNB",
+ "VPB",
+ "VGND",
+ "VPWR",
+ "A2",
+ "X",
+ "B1",
+ "A1"
+ ], [
+ "VNB",
+ "VPB",
+ "VGND",
+ "VPWR",
+ "A2",
+ "X",
+ "B1",
+ "A1"
+ ]
+ ]
+ },
+ {
+ "name": [
+ "sky130_fd_sc_hd__a41o_1",
+ "sky130_fd_sc_hd__a41o_1"
+ ],
+ "devices": [
+ [
+ ["sky130_fd_pr__nfet_01v8", 6],
+ ["sky130_fd_pr__pfet_01v8_hvt", 6 ]
+ ], [
+ ["sky130_fd_pr__nfet_01v8", 6 ],
+ ["sky130_fd_pr__pfet_01v8_hvt", 6 ]
+ ]
+ ],
+ "nets": [
+ 15,
+ 15
+ ],
+ "badnets": [
+ ],
+ "badelements": [
+ ],
+ "pins": [
+ [
+ "VPWR",
+ "VGND",
+ "VNB",
+ "VPB",
+ "B1",
+ "A4",
+ "A3",
+ "A2",
+ "A1",
+ "X"
+ ], [
+ "VPWR",
+ "VGND",
+ "VNB",
+ "VPB",
+ "B1",
+ "A4",
+ "A3",
+ "A2",
+ "A1",
+ "X"
+ ]
+ ]
+ },
+ {
+ "name": [
+ "sky130_fd_sc_hd__a31oi_1",
+ "sky130_fd_sc_hd__a31oi_1"
+ ],
+ "devices": [
+ [
+ ["sky130_fd_pr__nfet_01v8", 4],
+ ["sky130_fd_pr__pfet_01v8_hvt", 4 ]
+ ], [
+ ["sky130_fd_pr__nfet_01v8", 4 ],
+ ["sky130_fd_pr__pfet_01v8_hvt", 4 ]
+ ]
+ ],
+ "nets": [
+ 12,
+ 12
+ ],
+ "badnets": [
+ ],
+ "badelements": [
+ ],
+ "pins": [
+ [
+ "VPB",
+ "VNB",
+ "B1",
+ "A1",
+ "VGND",
+ "A3",
+ "A2",
+ "Y",
+ "VPWR"
+ ], [
+ "VPB",
+ "VNB",
+ "B1",
+ "A1",
+ "VGND",
+ "A3",
+ "A2",
+ "Y",
+ "VPWR"
+ ]
+ ]
+ },
+ {
+ "name": [
+ "sky130_fd_sc_hd__a22o_1",
+ "sky130_fd_sc_hd__a22o_1"
+ ],
+ "devices": [
+ [
+ ["sky130_fd_pr__pfet_01v8_hvt", 5],
+ ["sky130_fd_pr__nfet_01v8", 5 ]
+ ], [
+ ["sky130_fd_pr__pfet_01v8_hvt", 5 ],
+ ["sky130_fd_pr__nfet_01v8", 5 ]
+ ]
+ ],
+ "nets": [
+ 13,
+ 13
+ ],
+ "badnets": [
+ ],
+ "badelements": [
+ ],
+ "pins": [
+ [
+ "VPB",
+ "VNB",
+ "A2",
+ "A1",
+ "B1",
+ "X",
+ "B2",
+ "VPWR",
+ "VGND"
+ ], [
+ "VPB",
+ "VNB",
+ "A2",
+ "A1",
+ "B1",
+ "X",
+ "B2",
+ "VPWR",
+ "VGND"
+ ]
+ ]
+ },
+ {
+ "name": [
+ "sky130_fd_sc_hd__or3b_1",
+ "sky130_fd_sc_hd__or3b_1"
+ ],
+ "devices": [
+ [
+ ["sky130_fd_pr__nfet_01v8", 5],
+ ["sky130_fd_pr__pfet_01v8_hvt", 5 ]
+ ], [
+ ["sky130_fd_pr__nfet_01v8", 5 ],
+ ["sky130_fd_pr__pfet_01v8_hvt", 5 ]
+ ]
+ ],
+ "nets": [
+ 12,
+ 12
+ ],
+ "badnets": [
+ ],
+ "badelements": [
+ ],
+ "pins": [
+ [
+ "VPWR",
+ "VGND",
+ "VNB",
+ "VPB",
+ "X",
+ "B",
+ "A",
+ "C_N"
+ ], [
+ "VPWR",
+ "VGND",
+ "VNB",
+ "VPB",
+ "X",
+ "B",
+ "A",
+ "C_N"
+ ]
+ ]
+ },
+ {
+ "name": [
+ "sky130_fd_sc_hd__and3_1",
+ "sky130_fd_sc_hd__and3_1"
+ ],
+ "devices": [
+ [
+ ["sky130_fd_pr__pfet_01v8_hvt", 4],
+ ["sky130_fd_pr__nfet_01v8", 4 ]
+ ], [
+ ["sky130_fd_pr__pfet_01v8_hvt", 4 ],
+ ["sky130_fd_pr__nfet_01v8", 4 ]
+ ]
+ ],
+ "nets": [
+ 11,
+ 11
+ ],
+ "badnets": [
+ ],
+ "badelements": [
+ ],
+ "pins": [
+ [
+ "VGND",
+ "A",
+ "B",
+ "C",
+ "X",
+ "VNB",
+ "VPWR",
+ "VPB"
+ ], [
+ "VGND",
+ "A",
+ "B",
+ "C",
+ "X",
+ "VNB",
+ "VPWR",
+ "VPB"
+ ]
+ ]
+ },
+ {
+ "name": [
+ "sky130_fd_sc_hd__o22a_1",
+ "sky130_fd_sc_hd__o22a_1"
+ ],
+ "devices": [
+ [
+ ["sky130_fd_pr__nfet_01v8", 5],
+ ["sky130_fd_pr__pfet_01v8_hvt", 5 ]
+ ], [
+ ["sky130_fd_pr__nfet_01v8", 5 ],
+ ["sky130_fd_pr__pfet_01v8_hvt", 5 ]
+ ]
+ ],
+ "nets": [
+ 13,
+ 13
+ ],
+ "badnets": [
+ ],
+ "badelements": [
+ ],
+ "pins": [
+ [
+ "VPWR",
+ "VGND",
+ "VPB",
+ "VNB",
+ "B1",
+ "X",
+ "B2",
+ "A1",
+ "A2"
+ ], [
+ "VPWR",
+ "VGND",
+ "VPB",
+ "VNB",
+ "B1",
+ "X",
+ "B2",
+ "A1",
+ "A2"
+ ]
+ ]
+ },
+ {
+ "name": [
+ "sky130_fd_sc_hd__a22o_2",
+ "sky130_fd_sc_hd__a22o_2"
+ ],
+ "devices": [
+ [
+ ["sky130_fd_pr__pfet_01v8_hvt", 5],
+ ["sky130_fd_pr__nfet_01v8", 5 ]
+ ], [
+ ["sky130_fd_pr__pfet_01v8_hvt", 5 ],
+ ["sky130_fd_pr__nfet_01v8", 5 ]
+ ]
+ ],
+ "nets": [
+ 13,
+ 13
+ ],
+ "badnets": [
+ ],
+ "badelements": [
+ ],
+ "pins": [
+ [
+ "VPB",
+ "VNB",
+ "X",
+ "A2",
+ "B1",
+ "A1",
+ "B2",
+ "VPWR",
+ "VGND"
+ ], [
+ "VPB",
+ "VNB",
+ "X",
+ "A2",
+ "B1",
+ "A1",
+ "B2",
+ "VPWR",
+ "VGND"
+ ]
+ ]
+ },
+ {
+ "name": [
+ "sky130_fd_sc_hd__a22o_4",
+ "sky130_fd_sc_hd__a22o_4"
+ ],
+ "devices": [
+ [
+ ["sky130_fd_pr__pfet_01v8_hvt", 5],
+ ["sky130_fd_pr__nfet_01v8", 5 ]
+ ], [
+ ["sky130_fd_pr__pfet_01v8_hvt", 5 ],
+ ["sky130_fd_pr__nfet_01v8", 5 ]
+ ]
+ ],
+ "nets": [
+ 13,
+ 13
+ ],
+ "badnets": [
+ ],
+ "badelements": [
+ ],
+ "pins": [
+ [
+ "VPWR",
+ "VGND",
+ "VPB",
+ "VNB",
+ "A1",
+ "X",
+ "B2",
+ "A2",
+ "B1"
+ ], [
+ "VPWR",
+ "VGND",
+ "VPB",
+ "VNB",
+ "A1",
+ "X",
+ "B2",
+ "A2",
+ "B1"
+ ]
+ ]
+ },
+ {
+ "name": [
+ "sky130_fd_sc_hd__and2b_1",
+ "sky130_fd_sc_hd__and2b_1"
+ ],
+ "devices": [
+ [
+ ["sky130_fd_pr__pfet_01v8_hvt", 4],
+ ["sky130_fd_pr__nfet_01v8", 4 ]
+ ], [
+ ["sky130_fd_pr__pfet_01v8_hvt", 4 ],
+ ["sky130_fd_pr__nfet_01v8", 4 ]
+ ]
+ ],
+ "nets": [
+ 10,
+ 10
+ ],
+ "badnets": [
+ ],
+ "badelements": [
+ ],
+ "pins": [
+ [
+ "VGND",
+ "B",
+ "X",
+ "A_N",
+ "VPWR",
+ "VPB",
+ "VNB"
+ ], [
+ "VGND",
+ "B",
+ "X",
+ "A_N",
+ "VPWR",
+ "VPB",
+ "VNB"
+ ]
+ ]
+ },
+ {
+ "name": [
+ "sky130_fd_sc_hd__dfxtp_2",
+ "sky130_fd_sc_hd__dfxtp_2"
+ ],
+ "devices": [
+ [
+ ["sky130_fd_pr__nfet_01v8", 12],
+ ["sky130_fd_pr__pfet_01v8_hvt", 12 ]
+ ], [
+ ["sky130_fd_pr__nfet_01v8", 12 ],
+ ["sky130_fd_pr__pfet_01v8_hvt", 12 ]
+ ]
+ ],
+ "nets": [
+ 18,
+ 18
+ ],
+ "badnets": [
+ ],
+ "badelements": [
+ ],
+ "pins": [
+ [
+ "VPB",
+ "VNB",
+ "VGND",
+ "VPWR",
+ "D",
+ "Q",
+ "CLK"
+ ], [
+ "VPB",
+ "VNB",
+ "VGND",
+ "VPWR",
+ "D",
+ "Q",
+ "CLK"
+ ]
+ ]
+ },
+ {
+ "name": [
+ "sky130_fd_sc_hd__o21ai_1",
+ "sky130_fd_sc_hd__o21ai_1"
+ ],
+ "devices": [
+ [
+ ["sky130_fd_pr__pfet_01v8_hvt", 3],
+ ["sky130_fd_pr__nfet_01v8", 3 ]
+ ], [
+ ["sky130_fd_pr__pfet_01v8_hvt", 3 ],
+ ["sky130_fd_pr__nfet_01v8", 3 ]
+ ]
+ ],
+ "nets": [
+ 10,
+ 10
+ ],
+ "badnets": [
+ ],
+ "badelements": [
+ ],
+ "pins": [
+ [
+ "A2",
+ "B1",
+ "VPWR",
+ "A1",
+ "VGND",
+ "Y",
+ "VPB",
+ "VNB"
+ ], [
+ "A2",
+ "B1",
+ "VPWR",
+ "A1",
+ "VGND",
+ "Y",
+ "VPB",
+ "VNB"
+ ]
+ ]
+ },
+ {
+ "name": [
+ "sky130_fd_sc_hd__and4_1",
+ "sky130_fd_sc_hd__and4_1"
+ ],
+ "devices": [
+ [
+ ["sky130_fd_pr__pfet_01v8_hvt", 5],
+ ["sky130_fd_pr__nfet_01v8", 5 ]
+ ], [
+ ["sky130_fd_pr__pfet_01v8_hvt", 5 ],
+ ["sky130_fd_pr__nfet_01v8", 5 ]
+ ]
+ ],
+ "nets": [
+ 13,
+ 13
+ ],
+ "badnets": [
+ ],
+ "badelements": [
+ ],
+ "pins": [
+ [
+ "VNB",
+ "VPWR",
+ "VPB",
+ "VGND",
+ "X",
+ "D",
+ "B",
+ "C",
+ "A"
+ ], [
+ "VNB",
+ "VPWR",
+ "VPB",
+ "VGND",
+ "X",
+ "D",
+ "B",
+ "C",
+ "A"
+ ]
+ ]
+ },
+ {
+ "name": [
+ "sky130_fd_sc_hd__a311oi_4",
+ "sky130_fd_sc_hd__a311oi_4"
+ ],
+ "devices": [
+ [
+ ["sky130_fd_pr__nfet_01v8", 5],
+ ["sky130_fd_pr__pfet_01v8_hvt", 5 ]
+ ], [
+ ["sky130_fd_pr__nfet_01v8", 5 ],
+ ["sky130_fd_pr__pfet_01v8_hvt", 5 ]
+ ]
+ ],
+ "nets": [
+ 14,
+ 14
+ ],
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+ ],
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+ ],
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+ [
+ "Y",
+ "VPWR",
+ "VGND",
+ "VPB",
+ "VNB",
+ "A1",
+ "A2",
+ "B1",
+ "C1",
+ "A3"
+ ], [
+ "Y",
+ "VPWR",
+ "VGND",
+ "VPB",
+ "VNB",
+ "A1",
+ "A2",
+ "B1",
+ "C1",
+ "A3"
+ ]
+ ]
+ },
+ {
+ "name": [
+ "sky130_fd_sc_hd__a221o_4",
+ "sky130_fd_sc_hd__a221o_4"
+ ],
+ "devices": [
+ [
+ ["sky130_fd_pr__nfet_01v8", 6],
+ ["sky130_fd_pr__pfet_01v8_hvt", 6 ]
+ ], [
+ ["sky130_fd_pr__nfet_01v8", 6 ],
+ ["sky130_fd_pr__pfet_01v8_hvt", 6 ]
+ ]
+ ],
+ "nets": [
+ 15,
+ 15
+ ],
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+ ],
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+ ],
+ "pins": [
+ [
+ "VPWR",
+ "VNB",
+ "VPB",
+ "C1",
+ "B2",
+ "A2",
+ "A1",
+ "B1",
+ "X",
+ "VGND"
+ ], [
+ "VPWR",
+ "VNB",
+ "VPB",
+ "C1",
+ "B2",
+ "A2",
+ "A1",
+ "B1",
+ "X",
+ "VGND"
+ ]
+ ]
+ },
+ {
+ "name": [
+ "sky130_fd_sc_hd__inv_2",
+ "sky130_fd_sc_hd__inv_2"
+ ],
+ "devices": [
+ [
+ ["sky130_fd_pr__pfet_01v8_hvt", 1],
+ ["sky130_fd_pr__nfet_01v8", 1 ]
+ ], [
+ ["sky130_fd_pr__pfet_01v8_hvt", 1 ],
+ ["sky130_fd_pr__nfet_01v8", 1 ]
+ ]
+ ],
+ "nets": [
+ 6,
+ 6
+ ],
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+ ],
+ "badelements": [
+ ],
+ "pins": [
+ [
+ "VGND",
+ "VNB",
+ "VPWR",
+ "VPB",
+ "Y",
+ "A"
+ ], [
+ "VGND",
+ "VNB",
+ "VPWR",
+ "VPB",
+ "Y",
+ "A"
+ ]
+ ]
+ },
+ {
+ "name": [
+ "sky130_fd_sc_hd__a311o_1",
+ "sky130_fd_sc_hd__a311o_1"
+ ],
+ "devices": [
+ [
+ ["sky130_fd_pr__nfet_01v8", 6],
+ ["sky130_fd_pr__pfet_01v8_hvt", 6 ]
+ ], [
+ ["sky130_fd_pr__nfet_01v8", 6 ],
+ ["sky130_fd_pr__pfet_01v8_hvt", 6 ]
+ ]
+ ],
+ "nets": [
+ 15,
+ 15
+ ],
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+ ],
+ "badelements": [
+ ],
+ "pins": [
+ [
+ "VPWR",
+ "VGND",
+ "A1",
+ "A3",
+ "B1",
+ "C1",
+ "A2",
+ "X",
+ "VPB",
+ "VNB"
+ ], [
+ "VPWR",
+ "VGND",
+ "A1",
+ "A3",
+ "B1",
+ "C1",
+ "A2",
+ "X",
+ "VPB",
+ "VNB"
+ ]
+ ]
+ },
+ {
+ "name": [
+ "sky130_fd_sc_hd__mux4_2",
+ "sky130_fd_sc_hd__mux4_2"
+ ],
+ "devices": [
+ [
+ ["sky130_fd_pr__pfet_01v8_hvt", 13],
+ ["sky130_fd_pr__nfet_01v8", 13 ]
+ ], [
+ ["sky130_fd_pr__pfet_01v8_hvt", 13 ],
+ ["sky130_fd_pr__nfet_01v8", 13 ]
+ ]
+ ],
+ "nets": [
+ 24,
+ 24
+ ],
+ "badnets": [
+ ],
+ "badelements": [
+ ],
+ "pins": [
+ [
+ "X",
+ "A1",
+ "A3",
+ "A0",
+ "A2",
+ "S0",
+ "VPB",
+ "VNB",
+ "VPWR",
+ "VGND",
+ "S1"
+ ], [
+ "X",
+ "A1",
+ "A3",
+ "A0",
+ "A2",
+ "S0",
+ "VPB",
+ "VNB",
+ "VPWR",
+ "VGND",
+ "S1"
+ ]
+ ]
+ },
+ {
+ "name": [
+ "sky130_fd_sc_hd__and3b_4",
+ "sky130_fd_sc_hd__and3b_4"
+ ],
+ "devices": [
+ [
+ ["sky130_fd_pr__nfet_01v8", 5],
+ ["sky130_fd_pr__pfet_01v8_hvt", 5 ]
+ ], [
+ ["sky130_fd_pr__nfet_01v8", 5 ],
+ ["sky130_fd_pr__pfet_01v8_hvt", 5 ]
+ ]
+ ],
+ "nets": [
+ 12,
+ 12
+ ],
+ "badnets": [
+ ],
+ "badelements": [
+ ],
+ "pins": [
+ [
+ "VNB",
+ "VPWR",
+ "VPB",
+ "VGND",
+ "X",
+ "C",
+ "B",
+ "A_N"
+ ], [
+ "VNB",
+ "VPWR",
+ "VPB",
+ "VGND",
+ "X",
+ "C",
+ "B",
+ "A_N"
+ ]
+ ]
+ },
+ {
+ "name": [
+ "sky130_fd_sc_hd__a2111o_1",
+ "sky130_fd_sc_hd__a2111o_1"
+ ],
+ "devices": [
+ [
+ ["sky130_fd_pr__nfet_01v8", 6],
+ ["sky130_fd_pr__pfet_01v8_hvt", 6 ]
+ ], [
+ ["sky130_fd_pr__nfet_01v8", 6 ],
+ ["sky130_fd_pr__pfet_01v8_hvt", 6 ]
+ ]
+ ],
+ "nets": [
+ 15,
+ 15
+ ],
+ "badnets": [
+ ],
+ "badelements": [
+ ],
+ "pins": [
+ [
+ "VPWR",
+ "VNB",
+ "VPB",
+ "D1",
+ "X",
+ "A1",
+ "B1",
+ "A2",
+ "C1",
+ "VGND"
+ ], [
+ "VPWR",
+ "VNB",
+ "VPB",
+ "D1",
+ "X",
+ "A1",
+ "B1",
+ "A2",
+ "C1",
+ "VGND"
+ ]
+ ]
+ },
+ {
+ "name": [
+ "sky130_fd_sc_hd__nor4_1",
+ "sky130_fd_sc_hd__nor4_1"
+ ],
+ "devices": [
+ [
+ ["sky130_fd_pr__nfet_01v8", 4],
+ ["sky130_fd_pr__pfet_01v8_hvt", 4 ]
+ ], [
+ ["sky130_fd_pr__nfet_01v8", 4 ],
+ ["sky130_fd_pr__pfet_01v8_hvt", 4 ]
+ ]
+ ],
+ "nets": [
+ 12,
+ 12
+ ],
+ "badnets": [
+ ],
+ "badelements": [
+ ],
+ "pins": [
+ [
+ "VPWR",
+ "VGND",
+ "VNB",
+ "VPB",
+ "A",
+ "C",
+ "B",
+ "D",
+ "Y"
+ ], [
+ "VPWR",
+ "VGND",
+ "VNB",
+ "VPB",
+ "A",
+ "C",
+ "B",
+ "D",
+ "Y"
+ ]
+ ]
+ },
+ {
+ "name": [
+ "sky130_fd_sc_hd__o21ai_4",
+ "sky130_fd_sc_hd__o21ai_4"
+ ],
+ "devices": [
+ [
+ ["sky130_fd_pr__pfet_01v8_hvt", 3],
+ ["sky130_fd_pr__nfet_01v8", 3 ]
+ ], [
+ ["sky130_fd_pr__pfet_01v8_hvt", 3 ],
+ ["sky130_fd_pr__nfet_01v8", 3 ]
+ ]
+ ],
+ "nets": [
+ 10,
+ 10
+ ],
+ "badnets": [
+ ],
+ "badelements": [
+ ],
+ "pins": [
+ [
+ "Y",
+ "VPB",
+ "VNB",
+ "A2",
+ "VGND",
+ "A1",
+ "B1",
+ "VPWR"
+ ], [
+ "Y",
+ "VPB",
+ "VNB",
+ "A2",
+ "VGND",
+ "A1",
+ "B1",
+ "VPWR"
+ ]
+ ]
+ },
+ {
+ "name": [
+ "sky130_fd_sc_hd__o21ba_1",
+ "sky130_fd_sc_hd__o21ba_1"
+ ],
+ "devices": [
+ [
+ ["sky130_fd_pr__nfet_01v8", 5],
+ ["sky130_fd_pr__pfet_01v8_hvt", 5 ]
+ ], [
+ ["sky130_fd_pr__nfet_01v8", 5 ],
+ ["sky130_fd_pr__pfet_01v8_hvt", 5 ]
+ ]
+ ],
+ "nets": [
+ 12,
+ 12
+ ],
+ "badnets": [
+ ],
+ "badelements": [
+ ],
+ "pins": [
+ [
+ "VNB",
+ "VPB",
+ "A2",
+ "B1_N",
+ "A1",
+ "X",
+ "VGND",
+ "VPWR"
+ ], [
+ "VNB",
+ "VPB",
+ "A2",
+ "B1_N",
+ "A1",
+ "X",
+ "VGND",
+ "VPWR"
+ ]
+ ]
+ },
+ {
+ "name": [
+ "sky130_fd_sc_hd__clkbuf_8",
+ "sky130_fd_sc_hd__clkbuf_8"
+ ],
+ "devices": [
+ [
+ ["sky130_fd_pr__pfet_01v8_hvt", 2],
+ ["sky130_fd_pr__nfet_01v8", 2 ]
+ ], [
+ ["sky130_fd_pr__pfet_01v8_hvt", 2 ],
+ ["sky130_fd_pr__nfet_01v8", 2 ]
+ ]
+ ],
+ "nets": [
+ 7,
+ 7
+ ],
+ "badnets": [
+ ],
+ "badelements": [
+ ],
+ "pins": [
+ [
+ "X",
+ "VGND",
+ "VNB",
+ "A",
+ "VPWR",
+ "VPB"
+ ], [
+ "X",
+ "VGND",
+ "VNB",
+ "A",
+ "VPWR",
+ "VPB"
+ ]
+ ]
+ },
+ {
+ "name": [
+ "sky130_fd_sc_hd__a31oi_4",
+ "sky130_fd_sc_hd__a31oi_4"
+ ],
+ "devices": [
+ [
+ ["sky130_fd_pr__nfet_01v8", 4],
+ ["sky130_fd_pr__pfet_01v8_hvt", 4 ]
+ ], [
+ ["sky130_fd_pr__nfet_01v8", 4 ],
+ ["sky130_fd_pr__pfet_01v8_hvt", 4 ]
+ ]
+ ],
+ "nets": [
+ 12,
+ 12
+ ],
+ "badnets": [
+ ],
+ "badelements": [
+ ],
+ "pins": [
+ [
+ "Y",
+ "VPWR",
+ "VPB",
+ "VNB",
+ "B1",
+ "A1",
+ "VGND",
+ "A3",
+ "A2"
+ ], [
+ "Y",
+ "VPWR",
+ "VPB",
+ "VNB",
+ "B1",
+ "A1",
+ "VGND",
+ "A3",
+ "A2"
+ ]
+ ]
+ },
+ {
+ "name": [
+ "sky130_fd_sc_hd__nand4_1",
+ "sky130_fd_sc_hd__nand4_1"
+ ],
+ "devices": [
+ [
+ ["sky130_fd_pr__pfet_01v8_hvt", 4],
+ ["sky130_fd_pr__nfet_01v8", 4 ]
+ ], [
+ ["sky130_fd_pr__pfet_01v8_hvt", 4 ],
+ ["sky130_fd_pr__nfet_01v8", 4 ]
+ ]
+ ],
+ "nets": [
+ 12,
+ 12
+ ],
+ "badnets": [
+ ],
+ "badelements": [
+ ],
+ "pins": [
+ [
+ "VGND",
+ "VNB",
+ "VPWR",
+ "VPB",
+ "A",
+ "C",
+ "B",
+ "D",
+ "Y"
+ ], [
+ "VGND",
+ "VNB",
+ "VPWR",
+ "VPB",
+ "A",
+ "C",
+ "B",
+ "D",
+ "Y"
+ ]
+ ]
+ },
+ {
+ "name": [
+ "sky130_fd_sc_hd__or4b_1",
+ "sky130_fd_sc_hd__or4b_1"
+ ],
+ "devices": [
+ [
+ ["sky130_fd_pr__pfet_01v8_hvt", 6],
+ ["sky130_fd_pr__nfet_01v8", 6 ]
+ ], [
+ ["sky130_fd_pr__pfet_01v8_hvt", 6 ],
+ ["sky130_fd_pr__nfet_01v8", 6 ]
+ ]
+ ],
+ "nets": [
+ 14,
+ 14
+ ],
+ "badnets": [
+ ],
+ "badelements": [
+ ],
+ "pins": [
+ [
+ "VGND",
+ "VNB",
+ "VPB",
+ "VPWR",
+ "A",
+ "B",
+ "C",
+ "X",
+ "D_N"
+ ], [
+ "VGND",
+ "VNB",
+ "VPB",
+ "VPWR",
+ "A",
+ "B",
+ "C",
+ "X",
+ "D_N"
+ ]
+ ]
+ },
+ {
+ "name": [
+ "sky130_fd_sc_hd__nor3_1",
+ "sky130_fd_sc_hd__nor3_1"
+ ],
+ "devices": [
+ [
+ ["sky130_fd_pr__pfet_01v8_hvt", 3],
+ ["sky130_fd_pr__nfet_01v8", 3 ]
+ ], [
+ ["sky130_fd_pr__pfet_01v8_hvt", 3 ],
+ ["sky130_fd_pr__nfet_01v8", 3 ]
+ ]
+ ],
+ "nets": [
+ 10,
+ 10
+ ],
+ "badnets": [
+ ],
+ "badelements": [
+ ],
+ "pins": [
+ [
+ "Y",
+ "VGND",
+ "VNB",
+ "VPB",
+ "A",
+ "B",
+ "C",
+ "VPWR"
+ ], [
+ "Y",
+ "VGND",
+ "VNB",
+ "VPB",
+ "A",
+ "B",
+ "C",
+ "VPWR"
+ ]
+ ]
+ },
+ {
+ "name": [
+ "sky130_fd_sc_hd__nor2_2",
+ "sky130_fd_sc_hd__nor2_2"
+ ],
+ "devices": [
+ [
+ ["sky130_fd_pr__pfet_01v8_hvt", 2],
+ ["sky130_fd_pr__nfet_01v8", 2 ]
+ ], [
+ ["sky130_fd_pr__pfet_01v8_hvt", 2 ],
+ ["sky130_fd_pr__nfet_01v8", 2 ]
+ ]
+ ],
+ "nets": [
+ 8,
+ 8
+ ],
+ "badnets": [
+ ],
+ "badelements": [
+ ],
+ "pins": [
+ [
+ "VPWR",
+ "B",
+ "VGND",
+ "VNB",
+ "A",
+ "VPB",
+ "Y"
+ ], [
+ "VPWR",
+ "B",
+ "VGND",
+ "VNB",
+ "A",
+ "VPB",
+ "Y"
+ ]
+ ]
+ },
+ {
+ "name": [
+ "sky130_fd_sc_hd__or2_1",
+ "sky130_fd_sc_hd__or2_1"
+ ],
+ "devices": [
+ [
+ ["sky130_fd_pr__nfet_01v8", 3],
+ ["sky130_fd_pr__pfet_01v8_hvt", 3 ]
+ ], [
+ ["sky130_fd_pr__nfet_01v8", 3 ],
+ ["sky130_fd_pr__pfet_01v8_hvt", 3 ]
+ ]
+ ],
+ "nets": [
+ 9,
+ 9
+ ],
+ "badnets": [
+ ],
+ "badelements": [
+ ],
+ "pins": [
+ [
+ "A",
+ "VPWR",
+ "X",
+ "B",
+ "VPB",
+ "VGND",
+ "VNB"
+ ], [
+ "A",
+ "VPWR",
+ "X",
+ "B",
+ "VPB",
+ "VGND",
+ "VNB"
+ ]
+ ]
+ },
+ {
+ "name": [
+ "sky130_fd_sc_hd__nand2_8",
+ "sky130_fd_sc_hd__nand2_8"
+ ],
+ "devices": [
+ [
+ ["sky130_fd_pr__nfet_01v8", 2],
+ ["sky130_fd_pr__pfet_01v8_hvt", 2 ]
+ ], [
+ ["sky130_fd_pr__nfet_01v8", 2 ],
+ ["sky130_fd_pr__pfet_01v8_hvt", 2 ]
+ ]
+ ],
+ "nets": [
+ 8,
+ 8
+ ],
+ "badnets": [
+ ],
+ "badelements": [
+ ],
+ "pins": [
+ [
+ "Y",
+ "VGND",
+ "A",
+ "VPWR",
+ "VPB",
+ "B",
+ "VNB"
+ ], [
+ "Y",
+ "VGND",
+ "A",
+ "VPWR",
+ "VPB",
+ "B",
+ "VNB"
+ ]
+ ]
+ },
+ {
+ "name": [
+ "sky130_fd_sc_hd__a311oi_1",
+ "sky130_fd_sc_hd__a311oi_1"
+ ],
+ "devices": [
+ [
+ ["sky130_fd_pr__nfet_01v8", 5],
+ ["sky130_fd_pr__pfet_01v8_hvt", 5 ]
+ ], [
+ ["sky130_fd_pr__nfet_01v8", 5 ],
+ ["sky130_fd_pr__pfet_01v8_hvt", 5 ]
+ ]
+ ],
+ "nets": [
+ 14,
+ 14
+ ],
+ "badnets": [
+ ],
+ "badelements": [
+ ],
+ "pins": [
+ [
+ "VPWR",
+ "VGND",
+ "VPB",
+ "VNB",
+ "A1",
+ "A2",
+ "A3",
+ "B1",
+ "C1",
+ "Y"
+ ], [
+ "VPWR",
+ "VGND",
+ "VPB",
+ "VNB",
+ "A1",
+ "A2",
+ "A3",
+ "B1",
+ "C1",
+ "Y"
+ ]
+ ]
+ },
+ {
+ "name": [
+ "sky130_fd_sc_hd__clkinv_16",
+ "sky130_fd_sc_hd__clkinv_16"
+ ],
+ "devices": [
+ [
+ ["sky130_fd_pr__nfet_01v8", 1],
+ ["sky130_fd_pr__pfet_01v8_hvt", 1 ]
+ ], [
+ ["sky130_fd_pr__nfet_01v8", 1 ],
+ ["sky130_fd_pr__pfet_01v8_hvt", 1 ]
+ ]
+ ],
+ "nets": [
+ 6,
+ 6
+ ],
+ "badnets": [
+ ],
+ "badelements": [
+ ],
+ "pins": [
+ [
+ "Y",
+ "A",
+ "VPWR",
+ "VPB",
+ "VGND",
+ "VNB"
+ ], [
+ "Y",
+ "A",
+ "VPWR",
+ "VPB",
+ "VGND",
+ "VNB"
+ ]
+ ]
+ },
+ {
+ "name": [
+ "sky130_fd_sc_hd__nand3_1",
+ "sky130_fd_sc_hd__nand3_1"
+ ],
+ "devices": [
+ [
+ ["sky130_fd_pr__pfet_01v8_hvt", 3],
+ ["sky130_fd_pr__nfet_01v8", 3 ]
+ ], [
+ ["sky130_fd_pr__pfet_01v8_hvt", 3 ],
+ ["sky130_fd_pr__nfet_01v8", 3 ]
+ ]
+ ],
+ "nets": [
+ 10,
+ 10
+ ],
+ "badnets": [
+ ],
+ "badelements": [
+ ],
+ "pins": [
+ [
+ "VGND",
+ "Y",
+ "A",
+ "B",
+ "C",
+ "VPWR",
+ "VPB",
+ "VNB"
+ ], [
+ "VGND",
+ "Y",
+ "A",
+ "B",
+ "C",
+ "VPWR",
+ "VPB",
+ "VNB"
+ ]
+ ]
+ },
+ {
+ "name": [
+ "sky130_fd_sc_hd__a221o_2",
+ "sky130_fd_sc_hd__a221o_2"
+ ],
+ "devices": [
+ [
+ ["sky130_fd_pr__pfet_01v8_hvt", 6],
+ ["sky130_fd_pr__nfet_01v8", 6 ]
+ ], [
+ ["sky130_fd_pr__pfet_01v8_hvt", 6 ],
+ ["sky130_fd_pr__nfet_01v8", 6 ]
+ ]
+ ],
+ "nets": [
+ 15,
+ 15
+ ],
+ "badnets": [
+ ],
+ "badelements": [
+ ],
+ "pins": [
+ [
+ "VGND",
+ "X",
+ "B1",
+ "A1",
+ "C1",
+ "A2",
+ "B2",
+ "VPB",
+ "VNB",
+ "VPWR"
+ ], [
+ "VGND",
+ "X",
+ "B1",
+ "A1",
+ "C1",
+ "A2",
+ "B2",
+ "VPB",
+ "VNB",
+ "VPWR"
+ ]
+ ]
+ },
+ {
+ "name": [
+ "sky130_fd_sc_hd__a21o_4",
+ "sky130_fd_sc_hd__a21o_4"
+ ],
+ "devices": [
+ [
+ ["sky130_fd_pr__nfet_01v8", 6],
+ ["sky130_fd_pr__pfet_01v8_hvt", 4 ]
+ ], [
+ ["sky130_fd_pr__nfet_01v8", 6 ],
+ ["sky130_fd_pr__pfet_01v8_hvt", 4 ]
+ ]
+ ],
+ "nets": [
+ 12,
+ 12
+ ],
+ "badnets": [
+ ],
+ "badelements": [
+ ],
+ "pins": [
+ [
+ "VPWR",
+ "A2",
+ "A1",
+ "VNB",
+ "X",
+ "B1",
+ "VPB",
+ "VGND"
+ ], [
+ "VPWR",
+ "A2",
+ "A1",
+ "VNB",
+ "X",
+ "B1",
+ "VPB",
+ "VGND"
+ ]
+ ]
+ },
+ {
+ "name": [
+ "sky130_fd_sc_hd__a2bb2o_1",
+ "sky130_fd_sc_hd__a2bb2o_1"
+ ],
+ "devices": [
+ [
+ ["sky130_fd_pr__pfet_01v8_hvt", 6],
+ ["sky130_fd_pr__nfet_01v8", 6 ]
+ ], [
+ ["sky130_fd_pr__pfet_01v8_hvt", 6 ],
+ ["sky130_fd_pr__nfet_01v8", 6 ]
+ ]
+ ],
+ "nets": [
+ 14,
+ 14
+ ],
+ "badnets": [
+ ],
+ "badelements": [
+ ],
+ "pins": [
+ [
+ "VPWR",
+ "VPB",
+ "VNB",
+ "A1_N",
+ "A2_N",
+ "X",
+ "B2",
+ "B1",
+ "VGND"
+ ], [
+ "VPWR",
+ "VPB",
+ "VNB",
+ "A1_N",
+ "A2_N",
+ "X",
+ "B2",
+ "B1",
+ "VGND"
+ ]
+ ]
+ },
+ {
+ "name": [
+ "sky130_fd_sc_hd__a21boi_1",
+ "sky130_fd_sc_hd__a21boi_1"
+ ],
+ "devices": [
+ [
+ ["sky130_fd_pr__pfet_01v8_hvt", 4],
+ ["sky130_fd_pr__nfet_01v8", 4 ]
+ ], [
+ ["sky130_fd_pr__pfet_01v8_hvt", 4 ],
+ ["sky130_fd_pr__nfet_01v8", 4 ]
+ ]
+ ],
+ "nets": [
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+ 11
+ ],
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+ ],
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+ ],
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+ [
+ "A1",
+ "A2",
+ "B1_N",
+ "VNB",
+ "VPB",
+ "VGND",
+ "Y",
+ "VPWR"
+ ], [
+ "A1",
+ "A2",
+ "B1_N",
+ "VNB",
+ "VPB",
+ "VGND",
+ "Y",
+ "VPWR"
+ ]
+ ]
+ },
+ {
+ "name": [
+ "sky130_fd_sc_hd__nand2_2",
+ "sky130_fd_sc_hd__nand2_2"
+ ],
+ "devices": [
+ [
+ ["sky130_fd_pr__pfet_01v8_hvt", 2],
+ ["sky130_fd_pr__nfet_01v8", 2 ]
+ ], [
+ ["sky130_fd_pr__pfet_01v8_hvt", 2 ],
+ ["sky130_fd_pr__nfet_01v8", 2 ]
+ ]
+ ],
+ "nets": [
+ 8,
+ 8
+ ],
+ "badnets": [
+ ],
+ "badelements": [
+ ],
+ "pins": [
+ [
+ "VGND",
+ "Y",
+ "A",
+ "VNB",
+ "B",
+ "VPWR",
+ "VPB"
+ ], [
+ "VGND",
+ "Y",
+ "A",
+ "VNB",
+ "B",
+ "VPWR",
+ "VPB"
+ ]
+ ]
+ },
+ {
+ "name": [
+ "sky130_fd_sc_hd__a21oi_2",
+ "sky130_fd_sc_hd__a21oi_2"
+ ],
+ "devices": [
+ [
+ ["sky130_fd_pr__nfet_01v8", 5],
+ ["sky130_fd_pr__pfet_01v8_hvt", 3 ]
+ ], [
+ ["sky130_fd_pr__nfet_01v8", 5 ],
+ ["sky130_fd_pr__pfet_01v8_hvt", 3 ]
+ ]
+ ],
+ "nets": [
+ 11,
+ 11
+ ],
+ "badnets": [
+ ],
+ "badelements": [
+ ],
+ "pins": [
+ [
+ "Y",
+ "VNB",
+ "VPWR",
+ "B1",
+ "VGND",
+ "A2",
+ "A1",
+ "VPB"
+ ], [
+ "Y",
+ "VNB",
+ "VPWR",
+ "B1",
+ "VGND",
+ "A2",
+ "A1",
+ "VPB"
+ ]
+ ]
+ },
+ {
+ "name": [
+ "sky130_fd_sc_hd__o21bai_1",
+ "sky130_fd_sc_hd__o21bai_1"
+ ],
+ "devices": [
+ [
+ ["sky130_fd_pr__pfet_01v8_hvt", 4],
+ ["sky130_fd_pr__nfet_01v8", 4 ]
+ ], [
+ ["sky130_fd_pr__pfet_01v8_hvt", 4 ],
+ ["sky130_fd_pr__nfet_01v8", 4 ]
+ ]
+ ],
+ "nets": [
+ 11,
+ 11
+ ],
+ "badnets": [
+ ],
+ "badelements": [
+ ],
+ "pins": [
+ [
+ "VNB",
+ "VPB",
+ "VGND",
+ "Y",
+ "VPWR",
+ "A1",
+ "A2",
+ "B1_N"
+ ], [
+ "VNB",
+ "VPB",
+ "VGND",
+ "Y",
+ "VPWR",
+ "A1",
+ "A2",
+ "B1_N"
+ ]
+ ]
+ },
+ {
+ "name": [
+ "sky130_fd_sc_hd__a21oi_1",
+ "sky130_fd_sc_hd__a21oi_1"
+ ],
+ "devices": [
+ [
+ ["sky130_fd_pr__nfet_01v8", 3],
+ ["sky130_fd_pr__pfet_01v8_hvt", 3 ]
+ ], [
+ ["sky130_fd_pr__nfet_01v8", 3 ],
+ ["sky130_fd_pr__pfet_01v8_hvt", 3 ]
+ ]
+ ],
+ "nets": [
+ 10,
+ 10
+ ],
+ "badnets": [
+ ],
+ "badelements": [
+ ],
+ "pins": [
+ [
+ "VNB",
+ "VPB",
+ "Y",
+ "A2",
+ "VGND",
+ "A1",
+ "VPWR",
+ "B1"
+ ], [
+ "VNB",
+ "VPB",
+ "Y",
+ "A2",
+ "VGND",
+ "A1",
+ "VPWR",
+ "B1"
+ ]
+ ]
+ },
+ {
+ "name": [
+ "sky130_fd_sc_hd__or4bb_1",
+ "sky130_fd_sc_hd__or4bb_1"
+ ],
+ "devices": [
+ [
+ ["sky130_fd_pr__nfet_01v8", 7],
+ ["sky130_fd_pr__pfet_01v8_hvt", 7 ]
+ ], [
+ ["sky130_fd_pr__nfet_01v8", 7 ],
+ ["sky130_fd_pr__pfet_01v8_hvt", 7 ]
+ ]
+ ],
+ "nets": [
+ 15,
+ 15
+ ],
+ "badnets": [
+ ],
+ "badelements": [
+ ],
+ "pins": [
+ [
+ "VPWR",
+ "B",
+ "A",
+ "X",
+ "D_N",
+ "C_N",
+ "VGND",
+ "VNB",
+ "VPB"
+ ], [
+ "VPWR",
+ "B",
+ "A",
+ "X",
+ "D_N",
+ "C_N",
+ "VGND",
+ "VNB",
+ "VPB"
+ ]
+ ]
+ },
+ {
+ "name": [
+ "sky130_fd_sc_hd__a221oi_4",
+ "sky130_fd_sc_hd__a221oi_4"
+ ],
+ "devices": [
+ [
+ ["sky130_fd_pr__nfet_01v8", 5],
+ ["sky130_fd_pr__pfet_01v8_hvt", 5 ]
+ ], [
+ ["sky130_fd_pr__nfet_01v8", 5 ],
+ ["sky130_fd_pr__pfet_01v8_hvt", 5 ]
+ ]
+ ],
+ "nets": [
+ 14,
+ 14
+ ],
+ "badnets": [
+ ],
+ "badelements": [
+ ],
+ "pins": [
+ [
+ "VGND",
+ "VPB",
+ "VNB",
+ "B1",
+ "C1",
+ "A1",
+ "A2",
+ "VPWR",
+ "B2",
+ "Y"
+ ], [
+ "VGND",
+ "VPB",
+ "VNB",
+ "B1",
+ "C1",
+ "A1",
+ "A2",
+ "VPWR",
+ "B2",
+ "Y"
+ ]
+ ]
+ },
+ {
+ "name": [
+ "sky130_fd_sc_hd__mux2_4",
+ "sky130_fd_sc_hd__mux2_4"
+ ],
+ "devices": [
+ [
+ ["sky130_fd_pr__pfet_01v8_hvt", 6],
+ ["sky130_fd_pr__nfet_01v8", 6 ]
+ ], [
+ ["sky130_fd_pr__pfet_01v8_hvt", 6 ],
+ ["sky130_fd_pr__nfet_01v8", 6 ]
+ ]
+ ],
+ "nets": [
+ 14,
+ 14
+ ],
+ "badnets": [
+ ],
+ "badelements": [
+ ],
+ "pins": [
+ [
+ "VGND",
+ "VPWR",
+ "S",
+ "VNB",
+ "VPB",
+ "X",
+ "A0",
+ "A1"
+ ], [
+ "VGND",
+ "VPWR",
+ "S",
+ "VNB",
+ "VPB",
+ "X",
+ "A0",
+ "A1"
+ ]
+ ]
+ },
+ {
+ "name": [
+ "sky130_fd_sc_hd__clkinv_4",
+ "sky130_fd_sc_hd__clkinv_4"
+ ],
+ "devices": [
+ [
+ ["sky130_fd_pr__pfet_01v8_hvt", 1],
+ ["sky130_fd_pr__nfet_01v8", 1 ]
+ ], [
+ ["sky130_fd_pr__pfet_01v8_hvt", 1 ],
+ ["sky130_fd_pr__nfet_01v8", 1 ]
+ ]
+ ],
+ "nets": [
+ 6,
+ 6
+ ],
+ "badnets": [
+ ],
+ "badelements": [
+ ],
+ "pins": [
+ [
+ "VPWR",
+ "VPB",
+ "VGND",
+ "VNB",
+ "A",
+ "Y"
+ ], [
+ "VPWR",
+ "VPB",
+ "VGND",
+ "VNB",
+ "A",
+ "Y"
+ ]
+ ]
+ },
+ {
+ "name": [
+ "sky130_fd_sc_hd__o211ai_1",
+ "sky130_fd_sc_hd__o211ai_1"
+ ],
+ "devices": [
+ [
+ ["sky130_fd_pr__pfet_01v8_hvt", 4],
+ ["sky130_fd_pr__nfet_01v8", 4 ]
+ ], [
+ ["sky130_fd_pr__pfet_01v8_hvt", 4 ],
+ ["sky130_fd_pr__nfet_01v8", 4 ]
+ ]
+ ],
+ "nets": [
+ 12,
+ 12
+ ],
+ "badnets": [
+ ],
+ "badelements": [
+ ],
+ "pins": [
+ [
+ "Y",
+ "VPB",
+ "VNB",
+ "VPWR",
+ "A2",
+ "A1",
+ "VGND",
+ "C1",
+ "B1"
+ ], [
+ "Y",
+ "VPB",
+ "VNB",
+ "VPWR",
+ "A2",
+ "A1",
+ "VGND",
+ "C1",
+ "B1"
+ ]
+ ]
+ },
+ {
+ "name": [
+ "sky130_fd_sc_hd__nor2_4",
+ "sky130_fd_sc_hd__nor2_4"
+ ],
+ "devices": [
+ [
+ ["sky130_fd_pr__pfet_01v8_hvt", 2],
+ ["sky130_fd_pr__nfet_01v8", 2 ]
+ ], [
+ ["sky130_fd_pr__pfet_01v8_hvt", 2 ],
+ ["sky130_fd_pr__nfet_01v8", 2 ]
+ ]
+ ],
+ "nets": [
+ 8,
+ 8
+ ],
+ "badnets": [
+ ],
+ "badelements": [
+ ],
+ "pins": [
+ [
+ "Y",
+ "B",
+ "VPB",
+ "A",
+ "VGND",
+ "VNB",
+ "VPWR"
+ ], [
+ "Y",
+ "B",
+ "VPB",
+ "A",
+ "VGND",
+ "VNB",
+ "VPWR"
+ ]
+ ]
+ },
+ {
+ "name": [
+ "sky130_fd_sc_hd__a21oi_4",
+ "sky130_fd_sc_hd__a21oi_4"
+ ],
+ "devices": [
+ [
+ ["sky130_fd_pr__pfet_01v8_hvt", 3],
+ ["sky130_fd_pr__nfet_01v8", 3 ]
+ ], [
+ ["sky130_fd_pr__pfet_01v8_hvt", 3 ],
+ ["sky130_fd_pr__nfet_01v8", 3 ]
+ ]
+ ],
+ "nets": [
+ 10,
+ 10
+ ],
+ "badnets": [
+ ],
+ "badelements": [
+ ],
+ "pins": [
+ [
+ "A2",
+ "VGND",
+ "B1",
+ "VPWR",
+ "A1",
+ "VNB",
+ "Y",
+ "VPB"
+ ], [
+ "A2",
+ "VGND",
+ "B1",
+ "VPWR",
+ "A1",
+ "VNB",
+ "Y",
+ "VPB"
+ ]
+ ]
+ },
+ {
+ "name": [
+ "sky130_fd_sc_hd__o2111ai_1",
+ "sky130_fd_sc_hd__o2111ai_1"
+ ],
+ "devices": [
+ [
+ ["sky130_fd_pr__pfet_01v8_hvt", 5],
+ ["sky130_fd_pr__nfet_01v8", 5 ]
+ ], [
+ ["sky130_fd_pr__pfet_01v8_hvt", 5 ],
+ ["sky130_fd_pr__nfet_01v8", 5 ]
+ ]
+ ],
+ "nets": [
+ 14,
+ 14
+ ],
+ "badnets": [
+ ],
+ "badelements": [
+ ],
+ "pins": [
+ [
+ "VNB",
+ "Y",
+ "VPB",
+ "B1",
+ "A2",
+ "VGND",
+ "A1",
+ "D1",
+ "C1",
+ "VPWR"
+ ], [
+ "VNB",
+ "Y",
+ "VPB",
+ "B1",
+ "A2",
+ "VGND",
+ "A1",
+ "D1",
+ "C1",
+ "VPWR"
+ ]
+ ]
+ },
+ {
+ "name": [
+ "sky130_fd_sc_hd__nand2b_1",
+ "sky130_fd_sc_hd__nand2b_1"
+ ],
+ "devices": [
+ [
+ ["sky130_fd_pr__nfet_01v8", 3],
+ ["sky130_fd_pr__pfet_01v8_hvt", 3 ]
+ ], [
+ ["sky130_fd_pr__nfet_01v8", 3 ],
+ ["sky130_fd_pr__pfet_01v8_hvt", 3 ]
+ ]
+ ],
+ "nets": [
+ 9,
+ 9
+ ],
+ "badnets": [
+ ],
+ "badelements": [
+ ],
+ "pins": [
+ [
+ "Y",
+ "VNB",
+ "VPWR",
+ "VPB",
+ "A_N",
+ "VGND",
+ "B"
+ ], [
+ "Y",
+ "VNB",
+ "VPWR",
+ "VPB",
+ "A_N",
+ "VGND",
+ "B"
+ ]
+ ]
+ },
+ {
+ "name": [
+ "sky130_fd_sc_hd__or4bb_4",
+ "sky130_fd_sc_hd__or4bb_4"
+ ],
+ "devices": [
+ [
+ ["sky130_fd_pr__pfet_01v8_hvt", 7],
+ ["sky130_fd_pr__nfet_01v8", 7 ]
+ ], [
+ ["sky130_fd_pr__pfet_01v8_hvt", 7 ],
+ ["sky130_fd_pr__nfet_01v8", 7 ]
+ ]
+ ],
+ "nets": [
+ 15,
+ 15
+ ],
+ "badnets": [
+ ],
+ "badelements": [
+ ],
+ "pins": [
+ [
+ "X",
+ "B",
+ "A",
+ "D_N",
+ "C_N",
+ "VGND",
+ "VNB",
+ "VPB",
+ "VPWR"
+ ], [
+ "X",
+ "B",
+ "A",
+ "D_N",
+ "C_N",
+ "VGND",
+ "VNB",
+ "VPB",
+ "VPWR"
+ ]
+ ]
+ },
+ {
+ "name": [
+ "sky130_fd_sc_hd__and4b_4",
+ "sky130_fd_sc_hd__and4b_4"
+ ],
+ "devices": [
+ [
+ ["sky130_fd_pr__pfet_01v8_hvt", 6],
+ ["sky130_fd_pr__nfet_01v8", 6 ]
+ ], [
+ ["sky130_fd_pr__pfet_01v8_hvt", 6 ],
+ ["sky130_fd_pr__nfet_01v8", 6 ]
+ ]
+ ],
+ "nets": [
+ 14,
+ 14
+ ],
+ "badnets": [
+ ],
+ "badelements": [
+ ],
+ "pins": [
+ [
+ "VGND",
+ "X",
+ "D",
+ "A_N",
+ "C",
+ "B",
+ "VPWR",
+ "VPB",
+ "VNB"
+ ], [
+ "VGND",
+ "X",
+ "D",
+ "A_N",
+ "C",
+ "B",
+ "VPWR",
+ "VPB",
+ "VNB"
+ ]
+ ]
+ },
+ {
+ "name": [
+ "sky130_fd_sc_hd__o2111a_1",
+ "sky130_fd_sc_hd__o2111a_1"
+ ],
+ "devices": [
+ [
+ ["sky130_fd_pr__pfet_01v8_hvt", 6],
+ ["sky130_fd_pr__nfet_01v8", 6 ]
+ ], [
+ ["sky130_fd_pr__pfet_01v8_hvt", 6 ],
+ ["sky130_fd_pr__nfet_01v8", 6 ]
+ ]
+ ],
+ "nets": [
+ 15,
+ 15
+ ],
+ "badnets": [
+ ],
+ "badelements": [
+ ],
+ "pins": [
+ [
+ "VPWR",
+ "VGND",
+ "VPB",
+ "VNB",
+ "D1",
+ "C1",
+ "A1",
+ "A2",
+ "B1",
+ "X"
+ ], [
+ "VPWR",
+ "VGND",
+ "VPB",
+ "VNB",
+ "D1",
+ "C1",
+ "A1",
+ "A2",
+ "B1",
+ "X"
+ ]
+ ]
+ },
+ {
+ "name": [
+ "sky130_fd_sc_hd__a2bb2o_4",
+ "sky130_fd_sc_hd__a2bb2o_4"
+ ],
+ "devices": [
+ [
+ ["sky130_fd_pr__nfet_01v8", 6],
+ ["sky130_fd_pr__pfet_01v8_hvt", 6 ]
+ ], [
+ ["sky130_fd_pr__nfet_01v8", 6 ],
+ ["sky130_fd_pr__pfet_01v8_hvt", 6 ]
+ ]
+ ],
+ "nets": [
+ 14,
+ 14
+ ],
+ "badnets": [
+ ],
+ "badelements": [
+ ],
+ "pins": [
+ [
+ "VPWR",
+ "A2_N",
+ "X",
+ "A1_N",
+ "B2",
+ "B1",
+ "VNB",
+ "VPB",
+ "VGND"
+ ], [
+ "VPWR",
+ "A2_N",
+ "X",
+ "A1_N",
+ "B2",
+ "B1",
+ "VNB",
+ "VPB",
+ "VGND"
+ ]
+ ]
+ },
+ {
+ "name": [
+ "sky130_fd_sc_hd__and4bb_1",
+ "sky130_fd_sc_hd__and4bb_1"
+ ],
+ "devices": [
+ [
+ ["sky130_fd_pr__pfet_01v8_hvt", 7],
+ ["sky130_fd_pr__nfet_01v8", 7 ]
+ ], [
+ ["sky130_fd_pr__pfet_01v8_hvt", 7 ],
+ ["sky130_fd_pr__nfet_01v8", 7 ]
+ ]
+ ],
+ "nets": [
+ 15,
+ 15
+ ],
+ "badnets": [
+ ],
+ "badelements": [
+ ],
+ "pins": [
+ [
+ "VGND",
+ "C",
+ "A_N",
+ "B_N",
+ "X",
+ "D",
+ "VPWR",
+ "VPB",
+ "VNB"
+ ], [
+ "VGND",
+ "C",
+ "A_N",
+ "B_N",
+ "X",
+ "D",
+ "VPWR",
+ "VPB",
+ "VNB"
+ ]
+ ]
+ },
+ {
+ "name": [
+ "sky130_fd_sc_hd__xnor2_1",
+ "sky130_fd_sc_hd__xnor2_1"
+ ],
+ "devices": [
+ [
+ ["sky130_fd_pr__pfet_01v8_hvt", 5],
+ ["sky130_fd_pr__nfet_01v8", 5 ]
+ ], [
+ ["sky130_fd_pr__pfet_01v8_hvt", 5 ],
+ ["sky130_fd_pr__nfet_01v8", 5 ]
+ ]
+ ],
+ "nets": [
+ 11,
+ 11
+ ],
+ "badnets": [
+ ],
+ "badelements": [
+ ],
+ "pins": [
+ [
+ "Y",
+ "VGND",
+ "VPB",
+ "VNB",
+ "VPWR",
+ "A",
+ "B"
+ ], [
+ "Y",
+ "VGND",
+ "VPB",
+ "VNB",
+ "VPWR",
+ "A",
+ "B"
+ ]
+ ]
+ },
+ {
+ "name": [
+ "sky130_fd_sc_hd__nand4_2",
+ "sky130_fd_sc_hd__nand4_2"
+ ],
+ "devices": [
+ [
+ ["sky130_fd_pr__pfet_01v8_hvt", 4],
+ ["sky130_fd_pr__nfet_01v8", 4 ]
+ ], [
+ ["sky130_fd_pr__pfet_01v8_hvt", 4 ],
+ ["sky130_fd_pr__nfet_01v8", 4 ]
+ ]
+ ],
+ "nets": [
+ 12,
+ 12
+ ],
+ "badnets": [
+ ],
+ "badelements": [
+ ],
+ "pins": [
+ [
+ "VGND",
+ "Y",
+ "B",
+ "C",
+ "A",
+ "D",
+ "VPWR",
+ "VPB",
+ "VNB"
+ ], [
+ "VGND",
+ "Y",
+ "B",
+ "C",
+ "A",
+ "D",
+ "VPWR",
+ "VPB",
+ "VNB"
+ ]
+ ]
+ },
+ {
+ "name": [
+ "sky130_fd_sc_hd__clkbuf_1",
+ "sky130_fd_sc_hd__clkbuf_1"
+ ],
+ "devices": [
+ [
+ ["sky130_fd_pr__pfet_01v8_hvt", 2],
+ ["sky130_fd_pr__nfet_01v8", 2 ]
+ ], [
+ ["sky130_fd_pr__pfet_01v8_hvt", 2 ],
+ ["sky130_fd_pr__nfet_01v8", 2 ]
+ ]
+ ],
+ "nets": [
+ 7,
+ 7
+ ],
+ "badnets": [
+ ],
+ "badelements": [
+ ],
+ "pins": [
+ [
+ "VGND",
+ "A",
+ "VNB",
+ "X",
+ "VPWR",
+ "VPB"
+ ], [
+ "VGND",
+ "A",
+ "VNB",
+ "X",
+ "VPWR",
+ "VPB"
+ ]
+ ]
+ },
+ {
+ "name": [
+ "sky130_fd_sc_hd__o22a_4",
+ "sky130_fd_sc_hd__o22a_4"
+ ],
+ "devices": [
+ [
+ ["sky130_fd_pr__pfet_01v8_hvt", 5],
+ ["sky130_fd_pr__nfet_01v8", 5 ]
+ ], [
+ ["sky130_fd_pr__pfet_01v8_hvt", 5 ],
+ ["sky130_fd_pr__nfet_01v8", 5 ]
+ ]
+ ],
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+ 13
+ ],
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+ ],
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+ [
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+ "VNB",
+ "A2",
+ "X",
+ "B1",
+ "A1",
+ "B2",
+ "VPWR",
+ "VGND"
+ ], [
+ "VPB",
+ "VNB",
+ "A2",
+ "X",
+ "B1",
+ "A1",
+ "B2",
+ "VPWR",
+ "VGND"
+ ]
+ ]
+ },
+ {
+ "name": [
+ "sky130_fd_sc_hd__dlymetal6s2s_1",
+ "sky130_fd_sc_hd__dlymetal6s2s_1"
+ ],
+ "devices": [
+ [
+ ["sky130_fd_pr__pfet_01v8_hvt", 6],
+ ["sky130_fd_pr__nfet_01v8", 6 ]
+ ], [
+ ["sky130_fd_pr__pfet_01v8_hvt", 6 ],
+ ["sky130_fd_pr__nfet_01v8", 6 ]
+ ]
+ ],
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+ [
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+ "VPWR",
+ "VPB",
+ "VGND",
+ "VNB",
+ "X"
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+ "VPWR",
+ "VPB",
+ "VGND",
+ "VNB",
+ "X"
+ ]
+ ]
+ },
+ {
+ "name": [
+ "sky130_fd_sc_hd__buf_2",
+ "sky130_fd_sc_hd__buf_2"
+ ],
+ "devices": [
+ [
+ ["sky130_fd_pr__pfet_01v8_hvt", 2],
+ ["sky130_fd_pr__nfet_01v8", 2 ]
+ ], [
+ ["sky130_fd_pr__pfet_01v8_hvt", 2 ],
+ ["sky130_fd_pr__nfet_01v8", 2 ]
+ ]
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+ ],
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+ [
+ "X",
+ "VGND",
+ "VNB",
+ "A",
+ "VPWR",
+ "VPB"
+ ], [
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+ "VGND",
+ "VNB",
+ "A",
+ "VPWR",
+ "VPB"
+ ]
+ ]
+ },
+ {
+ "name": [
+ "sky130_fd_sc_hd__xor2_1",
+ "sky130_fd_sc_hd__xor2_1"
+ ],
+ "devices": [
+ [
+ ["sky130_fd_pr__pfet_01v8_hvt", 5],
+ ["sky130_fd_pr__nfet_01v8", 5 ]
+ ], [
+ ["sky130_fd_pr__pfet_01v8_hvt", 5 ],
+ ["sky130_fd_pr__nfet_01v8", 5 ]
+ ]
+ ],
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+ [
+ "A",
+ "VGND",
+ "B",
+ "VNB",
+ "VPB",
+ "X",
+ "VPWR"
+ ], [
+ "A",
+ "VGND",
+ "B",
+ "VNB",
+ "VPB",
+ "X",
+ "VPWR"
+ ]
+ ]
+ },
+ {
+ "name": [
+ "sky130_fd_sc_hd__and4_4",
+ "sky130_fd_sc_hd__and4_4"
+ ],
+ "devices": [
+ [
+ ["sky130_fd_pr__pfet_01v8_hvt", 5],
+ ["sky130_fd_pr__nfet_01v8", 5 ]
+ ], [
+ ["sky130_fd_pr__pfet_01v8_hvt", 5 ],
+ ["sky130_fd_pr__nfet_01v8", 5 ]
+ ]
+ ],
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+ ],
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+ ],
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+ "VGND",
+ "X",
+ "C",
+ "D",
+ "B",
+ "A",
+ "VPWR",
+ "VPB",
+ "VNB"
+ ], [
+ "VGND",
+ "X",
+ "C",
+ "D",
+ "B",
+ "A",
+ "VPWR",
+ "VPB",
+ "VNB"
+ ]
+ ]
+ },
+ {
+ "name": [
+ "sky130_fd_sc_hd__o32a_1",
+ "sky130_fd_sc_hd__o32a_1"
+ ],
+ "devices": [
+ [
+ ["sky130_fd_pr__nfet_01v8", 6],
+ ["sky130_fd_pr__pfet_01v8_hvt", 6 ]
+ ], [
+ ["sky130_fd_pr__nfet_01v8", 6 ],
+ ["sky130_fd_pr__pfet_01v8_hvt", 6 ]
+ ]
+ ],
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+ ],
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+ ],
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+ [
+ "VGND",
+ "VPWR",
+ "X",
+ "A1",
+ "B1",
+ "A2",
+ "B2",
+ "A3",
+ "VPB",
+ "VNB"
+ ], [
+ "VGND",
+ "VPWR",
+ "X",
+ "A1",
+ "B1",
+ "A2",
+ "B2",
+ "A3",
+ "VPB",
+ "VNB"
+ ]
+ ]
+ },
+ {
+ "name": [
+ "sky130_fd_sc_hd__or4b_2",
+ "sky130_fd_sc_hd__or4b_2"
+ ],
+ "devices": [
+ [
+ ["sky130_fd_pr__nfet_01v8", 6],
+ ["sky130_fd_pr__pfet_01v8_hvt", 6 ]
+ ], [
+ ["sky130_fd_pr__nfet_01v8", 6 ],
+ ["sky130_fd_pr__pfet_01v8_hvt", 6 ]
+ ]
+ ],
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+ ],
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+ [
+ "VPWR",
+ "VGND",
+ "VNB",
+ "VPB",
+ "X",
+ "D_N",
+ "B",
+ "C",
+ "A"
+ ], [
+ "VPWR",
+ "VGND",
+ "VNB",
+ "VPB",
+ "X",
+ "D_N",
+ "B",
+ "C",
+ "A"
+ ]
+ ]
+ },
+ {
+ "name": [
+ "sky130_fd_sc_hd__a22oi_2",
+ "sky130_fd_sc_hd__a22oi_2"
+ ],
+ "devices": [
+ [
+ ["sky130_fd_pr__pfet_01v8_hvt", 4],
+ ["sky130_fd_pr__nfet_01v8", 4 ]
+ ], [
+ ["sky130_fd_pr__pfet_01v8_hvt", 4 ],
+ ["sky130_fd_pr__nfet_01v8", 4 ]
+ ]
+ ],
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+ 12
+ ],
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+ [
+ "VGND",
+ "A2",
+ "A1",
+ "VPWR",
+ "B1",
+ "B2",
+ "VNB",
+ "Y",
+ "VPB"
+ ], [
+ "VGND",
+ "A2",
+ "A1",
+ "VPWR",
+ "B1",
+ "B2",
+ "VNB",
+ "Y",
+ "VPB"
+ ]
+ ]
+ },
+ {
+ "name": [
+ "sky130_fd_sc_hd__and2_4",
+ "sky130_fd_sc_hd__and2_4"
+ ],
+ "devices": [
+ [
+ ["sky130_fd_pr__pfet_01v8_hvt", 3],
+ ["sky130_fd_pr__nfet_01v8", 3 ]
+ ], [
+ ["sky130_fd_pr__pfet_01v8_hvt", 3 ],
+ ["sky130_fd_pr__nfet_01v8", 3 ]
+ ]
+ ],
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+ 9
+ ],
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+ ],
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+ [
+ "B",
+ "A",
+ "VGND",
+ "X",
+ "VPWR",
+ "VPB",
+ "VNB"
+ ], [
+ "B",
+ "A",
+ "VGND",
+ "X",
+ "VPWR",
+ "VPB",
+ "VNB"
+ ]
+ ]
+ },
+ {
+ "name": [
+ "sky130_fd_sc_hd__nand4_4",
+ "sky130_fd_sc_hd__nand4_4"
+ ],
+ "devices": [
+ [
+ ["sky130_fd_pr__nfet_01v8", 4],
+ ["sky130_fd_pr__pfet_01v8_hvt", 4 ]
+ ], [
+ ["sky130_fd_pr__nfet_01v8", 4 ],
+ ["sky130_fd_pr__pfet_01v8_hvt", 4 ]
+ ]
+ ],
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+ 12
+ ],
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+ ],
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+ [
+ "VGND",
+ "Y",
+ "VPWR",
+ "VPB",
+ "VNB",
+ "A",
+ "B",
+ "C",
+ "D"
+ ], [
+ "VGND",
+ "Y",
+ "VPWR",
+ "VPB",
+ "VNB",
+ "A",
+ "B",
+ "C",
+ "D"
+ ]
+ ]
+ },
+ {
+ "name": [
+ "sky130_fd_sc_hd__a2111o_2",
+ "sky130_fd_sc_hd__a2111o_2"
+ ],
+ "devices": [
+ [
+ ["sky130_fd_pr__pfet_01v8_hvt", 6],
+ ["sky130_fd_pr__nfet_01v8", 6 ]
+ ], [
+ ["sky130_fd_pr__pfet_01v8_hvt", 6 ],
+ ["sky130_fd_pr__nfet_01v8", 6 ]
+ ]
+ ],
+ "nets": [
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+ 15
+ ],
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+ ],
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+ ],
+ "pins": [
+ [
+ "VGND",
+ "VNB",
+ "VPB",
+ "A1",
+ "X",
+ "A2",
+ "D1",
+ "C1",
+ "B1",
+ "VPWR"
+ ], [
+ "VGND",
+ "VNB",
+ "VPB",
+ "A1",
+ "X",
+ "A2",
+ "D1",
+ "C1",
+ "B1",
+ "VPWR"
+ ]
+ ]
+ },
+ {
+ "name": [
+ "sky130_fd_sc_hd__o2bb2a_1",
+ "sky130_fd_sc_hd__o2bb2a_1"
+ ],
+ "devices": [
+ [
+ ["sky130_fd_pr__pfet_01v8_hvt", 6],
+ ["sky130_fd_pr__nfet_01v8", 6 ]
+ ], [
+ ["sky130_fd_pr__pfet_01v8_hvt", 6 ],
+ ["sky130_fd_pr__nfet_01v8", 6 ]
+ ]
+ ],
+ "nets": [
+ 14,
+ 14
+ ],
+ "badnets": [
+ ],
+ "badelements": [
+ ],
+ "pins": [
+ [
+ "VGND",
+ "VNB",
+ "VPB",
+ "A1_N",
+ "A2_N",
+ "X",
+ "B1",
+ "B2",
+ "VPWR"
+ ], [
+ "VGND",
+ "VNB",
+ "VPB",
+ "A1_N",
+ "A2_N",
+ "X",
+ "B1",
+ "B2",
+ "VPWR"
+ ]
+ ]
+ },
+ {
+ "name": [
+ "sky130_fd_sc_hd__and3b_1",
+ "sky130_fd_sc_hd__and3b_1"
+ ],
+ "devices": [
+ [
+ ["sky130_fd_pr__nfet_01v8", 5],
+ ["sky130_fd_pr__pfet_01v8_hvt", 5 ]
+ ], [
+ ["sky130_fd_pr__nfet_01v8", 5 ],
+ ["sky130_fd_pr__pfet_01v8_hvt", 5 ]
+ ]
+ ],
+ "nets": [
+ 12,
+ 12
+ ],
+ "badnets": [
+ ],
+ "badelements": [
+ ],
+ "pins": [
+ [
+ "VNB",
+ "VPWR",
+ "VPB",
+ "VGND",
+ "X",
+ "A_N",
+ "C",
+ "B"
+ ], [
+ "VNB",
+ "VPWR",
+ "VPB",
+ "VGND",
+ "X",
+ "A_N",
+ "C",
+ "B"
+ ]
+ ]
+ },
+ {
+ "name": [
+ "sky130_fd_sc_hd__a2111oi_1",
+ "sky130_fd_sc_hd__a2111oi_1"
+ ],
+ "devices": [
+ [
+ ["sky130_fd_pr__pfet_01v8_hvt", 5],
+ ["sky130_fd_pr__nfet_01v8", 5 ]
+ ], [
+ ["sky130_fd_pr__pfet_01v8_hvt", 5 ],
+ ["sky130_fd_pr__nfet_01v8", 5 ]
+ ]
+ ],
+ "nets": [
+ 14,
+ 14
+ ],
+ "badnets": [
+ ],
+ "badelements": [
+ ],
+ "pins": [
+ [
+ "VGND",
+ "Y",
+ "VNB",
+ "VPB",
+ "C1",
+ "B1",
+ "A1",
+ "D1",
+ "VPWR",
+ "A2"
+ ], [
+ "VGND",
+ "Y",
+ "VNB",
+ "VPB",
+ "C1",
+ "B1",
+ "A1",
+ "D1",
+ "VPWR",
+ "A2"
+ ]
+ ]
+ },
+ {
+ "name": [
+ "sky130_fd_sc_hd__o2111ai_4",
+ "sky130_fd_sc_hd__o2111ai_4"
+ ],
+ "devices": [
+ [
+ ["sky130_fd_pr__nfet_01v8", 5],
+ ["sky130_fd_pr__pfet_01v8_hvt", 5 ]
+ ], [
+ ["sky130_fd_pr__nfet_01v8", 5 ],
+ ["sky130_fd_pr__pfet_01v8_hvt", 5 ]
+ ]
+ ],
+ "nets": [
+ 14,
+ 14
+ ],
+ "badnets": [
+ ],
+ "badelements": [
+ ],
+ "pins": [
+ [
+ "VPWR",
+ "VNB",
+ "Y",
+ "VPB",
+ "B1",
+ "C1",
+ "A1",
+ "VGND",
+ "A2",
+ "D1"
+ ], [
+ "VPWR",
+ "VNB",
+ "Y",
+ "VPB",
+ "B1",
+ "C1",
+ "A1",
+ "VGND",
+ "A2",
+ "D1"
+ ]
+ ]
+ },
+ {
+ "name": [
+ "sky130_fd_sc_hd__o22ai_4",
+ "sky130_fd_sc_hd__o22ai_4"
+ ],
+ "devices": [
+ [
+ ["sky130_fd_pr__nfet_01v8", 4],
+ ["sky130_fd_pr__pfet_01v8_hvt", 4 ]
+ ], [
+ ["sky130_fd_pr__nfet_01v8", 4 ],
+ ["sky130_fd_pr__pfet_01v8_hvt", 4 ]
+ ]
+ ],
+ "nets": [
+ 12,
+ 12
+ ],
+ "badnets": [
+ ],
+ "badelements": [
+ ],
+ "pins": [
+ [
+ "B2",
+ "A2",
+ "VGND",
+ "B1",
+ "A1",
+ "VPWR",
+ "Y",
+ "VPB",
+ "VNB"
+ ], [
+ "B2",
+ "A2",
+ "VGND",
+ "B1",
+ "A1",
+ "VPWR",
+ "Y",
+ "VPB",
+ "VNB"
+ ]
+ ]
+ },
+ {
+ "name": [
+ "sky130_fd_sc_hd__a211o_2",
+ "sky130_fd_sc_hd__a211o_2"
+ ],
+ "devices": [
+ [
+ ["sky130_fd_pr__nfet_01v8", 5],
+ ["sky130_fd_pr__pfet_01v8_hvt", 5 ]
+ ], [
+ ["sky130_fd_pr__nfet_01v8", 5 ],
+ ["sky130_fd_pr__pfet_01v8_hvt", 5 ]
+ ]
+ ],
+ "nets": [
+ 13,
+ 13
+ ],
+ "badnets": [
+ ],
+ "badelements": [
+ ],
+ "pins": [
+ [
+ "VPWR",
+ "VGND",
+ "VPB",
+ "VNB",
+ "A1",
+ "B1",
+ "C1",
+ "X",
+ "A2"
+ ], [
+ "VPWR",
+ "VGND",
+ "VPB",
+ "VNB",
+ "A1",
+ "B1",
+ "C1",
+ "X",
+ "A2"
+ ]
+ ]
+ },
+ {
+ "name": [
+ "sky130_fd_sc_hd__a32oi_4",
+ "sky130_fd_sc_hd__a32oi_4"
+ ],
+ "devices": [
+ [
+ ["sky130_fd_pr__nfet_01v8", 5],
+ ["sky130_fd_pr__pfet_01v8_hvt", 5 ]
+ ], [
+ ["sky130_fd_pr__nfet_01v8", 5 ],
+ ["sky130_fd_pr__pfet_01v8_hvt", 5 ]
+ ]
+ ],
+ "nets": [
+ 14,
+ 14
+ ],
+ "badnets": [
+ ],
+ "badelements": [
+ ],
+ "pins": [
+ [
+ "VPWR",
+ "VNB",
+ "VPB",
+ "Y",
+ "A1",
+ "B1",
+ "B2",
+ "A3",
+ "A2",
+ "VGND"
+ ], [
+ "VPWR",
+ "VNB",
+ "VPB",
+ "Y",
+ "A1",
+ "B1",
+ "B2",
+ "A3",
+ "A2",
+ "VGND"
+ ]
+ ]
+ },
+ {
+ "name": [
+ "sky130_fd_sc_hd__and2b_4",
+ "sky130_fd_sc_hd__and2b_4"
+ ],
+ "devices": [
+ [
+ ["sky130_fd_pr__nfet_01v8", 4],
+ ["sky130_fd_pr__pfet_01v8_hvt", 4 ]
+ ], [
+ ["sky130_fd_pr__nfet_01v8", 4 ],
+ ["sky130_fd_pr__pfet_01v8_hvt", 4 ]
+ ]
+ ],
+ "nets": [
+ 10,
+ 10
+ ],
+ "badnets": [
+ ],
+ "badelements": [
+ ],
+ "pins": [
+ [
+ "VPWR",
+ "VPB",
+ "VNB",
+ "VGND",
+ "A_N",
+ "X",
+ "B"
+ ], [
+ "VPWR",
+ "VPB",
+ "VNB",
+ "VGND",
+ "A_N",
+ "X",
+ "B"
+ ]
+ ]
+ },
+ {
+ "name": [
+ "sky130_fd_sc_hd__clkinv_2",
+ "sky130_fd_sc_hd__clkinv_2"
+ ],
+ "devices": [
+ [
+ ["sky130_fd_pr__nfet_01v8", 1],
+ ["sky130_fd_pr__pfet_01v8_hvt", 1 ]
+ ], [
+ ["sky130_fd_pr__nfet_01v8", 1 ],
+ ["sky130_fd_pr__pfet_01v8_hvt", 1 ]
+ ]
+ ],
+ "nets": [
+ 6,
+ 6
+ ],
+ "badnets": [
+ ],
+ "badelements": [
+ ],
+ "pins": [
+ [
+ "VPWR",
+ "VPB",
+ "VGND",
+ "VNB",
+ "Y",
+ "A"
+ ], [
+ "VPWR",
+ "VPB",
+ "VGND",
+ "VNB",
+ "Y",
+ "A"
+ ]
+ ]
+ },
+ {
+ "name": [
+ "sky130_fd_sc_hd__o2bb2ai_2",
+ "sky130_fd_sc_hd__o2bb2ai_2"
+ ],
+ "devices": [
+ [
+ ["sky130_fd_pr__pfet_01v8_hvt", 5],
+ ["sky130_fd_pr__nfet_01v8", 5 ]
+ ], [
+ ["sky130_fd_pr__pfet_01v8_hvt", 5 ],
+ ["sky130_fd_pr__nfet_01v8", 5 ]
+ ]
+ ],
+ "nets": [
+ 13,
+ 13
+ ],
+ "badnets": [
+ ],
+ "badelements": [
+ ],
+ "pins": [
+ [
+ "VGND",
+ "Y",
+ "VPWR",
+ "A1_N",
+ "B2",
+ "A2_N",
+ "B1",
+ "VNB",
+ "VPB"
+ ], [
+ "VGND",
+ "Y",
+ "VPWR",
+ "A1_N",
+ "B2",
+ "A2_N",
+ "B1",
+ "VNB",
+ "VPB"
+ ]
+ ]
+ },
+ {
+ "name": [
+ "sky130_fd_sc_hd__or3b_2",
+ "sky130_fd_sc_hd__or3b_2"
+ ],
+ "devices": [
+ [
+ ["sky130_fd_pr__pfet_01v8_hvt", 5],
+ ["sky130_fd_pr__nfet_01v8", 5 ]
+ ], [
+ ["sky130_fd_pr__pfet_01v8_hvt", 5 ],
+ ["sky130_fd_pr__nfet_01v8", 5 ]
+ ]
+ ],
+ "nets": [
+ 12,
+ 12
+ ],
+ "badnets": [
+ ],
+ "badelements": [
+ ],
+ "pins": [
+ [
+ "VGND",
+ "VNB",
+ "VPB",
+ "VPWR",
+ "B",
+ "X",
+ "C_N",
+ "A"
+ ], [
+ "VGND",
+ "VNB",
+ "VPB",
+ "VPWR",
+ "B",
+ "X",
+ "C_N",
+ "A"
+ ]
+ ]
+ },
+ {
+ "name": [
+ "sky130_fd_sc_hd__or3b_4",
+ "sky130_fd_sc_hd__or3b_4"
+ ],
+ "devices": [
+ [
+ ["sky130_fd_pr__pfet_01v8_hvt", 5],
+ ["sky130_fd_pr__nfet_01v8", 5 ]
+ ], [
+ ["sky130_fd_pr__pfet_01v8_hvt", 5 ],
+ ["sky130_fd_pr__nfet_01v8", 5 ]
+ ]
+ ],
+ "nets": [
+ 12,
+ 12
+ ],
+ "badnets": [
+ ],
+ "badelements": [
+ ],
+ "pins": [
+ [
+ "VPWR",
+ "VGND",
+ "VNB",
+ "VPB",
+ "X",
+ "B",
+ "C_N",
+ "A"
+ ], [
+ "VPWR",
+ "VGND",
+ "VNB",
+ "VPB",
+ "X",
+ "B",
+ "C_N",
+ "A"
+ ]
+ ]
+ },
+ {
+ "name": [
+ "sky130_fd_sc_hd__a22oi_1",
+ "sky130_fd_sc_hd__a22oi_1"
+ ],
+ "devices": [
+ [
+ ["sky130_fd_pr__nfet_01v8", 4],
+ ["sky130_fd_pr__pfet_01v8_hvt", 4 ]
+ ], [
+ ["sky130_fd_pr__nfet_01v8", 4 ],
+ ["sky130_fd_pr__pfet_01v8_hvt", 4 ]
+ ]
+ ],
+ "nets": [
+ 12,
+ 12
+ ],
+ "badnets": [
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+ "Y",
+ "VNB",
+ "VPB"
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+ "A2",
+ "VPWR",
+ "A1",
+ "VGND",
+ "B2",
+ "Y",
+ "VNB",
+ "VPB"
+ ]
+ ]
+ },
+ {
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+ "sky130_fd_sc_hd__o31a_2",
+ "sky130_fd_sc_hd__o31a_2"
+ ],
+ "devices": [
+ [
+ ["sky130_fd_pr__nfet_01v8", 5],
+ ["sky130_fd_pr__pfet_01v8_hvt", 5 ]
+ ], [
+ ["sky130_fd_pr__nfet_01v8", 5 ],
+ ["sky130_fd_pr__pfet_01v8_hvt", 5 ]
+ ]
+ ],
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+ "X",
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+ "A2",
+ "VPB",
+ "VNB"
+ ], [
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+ "VGND",
+ "A3",
+ "X",
+ "B1",
+ "A1",
+ "A2",
+ "VPB",
+ "VNB"
+ ]
+ ]
+ },
+ {
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+ "sky130_fd_sc_hd__or2_4",
+ "sky130_fd_sc_hd__or2_4"
+ ],
+ "devices": [
+ [
+ ["sky130_fd_pr__pfet_01v8_hvt", 3],
+ ["sky130_fd_pr__nfet_01v8", 3 ]
+ ], [
+ ["sky130_fd_pr__pfet_01v8_hvt", 3 ],
+ ["sky130_fd_pr__nfet_01v8", 3 ]
+ ]
+ ],
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+ 9
+ ],
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+ "B",
+ "X",
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+ "A"
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+ "VGND",
+ "VNB",
+ "B",
+ "X",
+ "VPWR",
+ "A"
+ ]
+ ]
+ },
+ {
+ "name": [
+ "sky130_fd_sc_hd__a21o_2",
+ "sky130_fd_sc_hd__a21o_2"
+ ],
+ "devices": [
+ [
+ ["sky130_fd_pr__pfet_01v8_hvt", 4],
+ ["sky130_fd_pr__nfet_01v8", 4 ]
+ ], [
+ ["sky130_fd_pr__pfet_01v8_hvt", 4 ],
+ ["sky130_fd_pr__nfet_01v8", 4 ]
+ ]
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+ "X",
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+ "VPWR",
+ "VGND"
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+ "VPB",
+ "A1",
+ "X",
+ "B1",
+ "A2",
+ "VPWR",
+ "VGND"
+ ]
+ ]
+ },
+ {
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+ "sky130_fd_sc_hd__a31o_2",
+ "sky130_fd_sc_hd__a31o_2"
+ ],
+ "devices": [
+ [
+ ["sky130_fd_pr__pfet_01v8_hvt", 5],
+ ["sky130_fd_pr__nfet_01v8", 5 ]
+ ], [
+ ["sky130_fd_pr__pfet_01v8_hvt", 5 ],
+ ["sky130_fd_pr__nfet_01v8", 5 ]
+ ]
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+ "VGND",
+ "VNB",
+ "VPB",
+ "A2",
+ "A1",
+ "B1",
+ "A3",
+ "X",
+ "VPWR"
+ ], [
+ "VGND",
+ "VNB",
+ "VPB",
+ "A2",
+ "A1",
+ "B1",
+ "A3",
+ "X",
+ "VPWR"
+ ]
+ ]
+ },
+ {
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+ "sky130_fd_sc_hd__and4bb_4",
+ "sky130_fd_sc_hd__and4bb_4"
+ ],
+ "devices": [
+ [
+ ["sky130_fd_pr__pfet_01v8_hvt", 7],
+ ["sky130_fd_pr__nfet_01v8", 7 ]
+ ], [
+ ["sky130_fd_pr__pfet_01v8_hvt", 7 ],
+ ["sky130_fd_pr__nfet_01v8", 7 ]
+ ]
+ ],
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+ [
+ "VGND",
+ "X",
+ "C",
+ "D",
+ "B_N",
+ "A_N",
+ "VPWR",
+ "VPB",
+ "VNB"
+ ], [
+ "VGND",
+ "X",
+ "C",
+ "D",
+ "B_N",
+ "A_N",
+ "VPWR",
+ "VPB",
+ "VNB"
+ ]
+ ]
+ },
+ {
+ "name": [
+ "sky130_fd_sc_hd__o41ai_1",
+ "sky130_fd_sc_hd__o41ai_1"
+ ],
+ "devices": [
+ [
+ ["sky130_fd_pr__pfet_01v8_hvt", 5],
+ ["sky130_fd_pr__nfet_01v8", 5 ]
+ ], [
+ ["sky130_fd_pr__pfet_01v8_hvt", 5 ],
+ ["sky130_fd_pr__nfet_01v8", 5 ]
+ ]
+ ],
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+ ],
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+ ],
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+ [
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+ "VGND",
+ "VPB",
+ "VNB",
+ "A2",
+ "A1",
+ "A3",
+ "A4",
+ "VPWR",
+ "B1"
+ ], [
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+ "VGND",
+ "VPB",
+ "VNB",
+ "A2",
+ "A1",
+ "A3",
+ "A4",
+ "VPWR",
+ "B1"
+ ]
+ ]
+ },
+ {
+ "name": [
+ "sky130_fd_sc_hd__o21ba_2",
+ "sky130_fd_sc_hd__o21ba_2"
+ ],
+ "devices": [
+ [
+ ["sky130_fd_pr__nfet_01v8", 5],
+ ["sky130_fd_pr__pfet_01v8_hvt", 5 ]
+ ], [
+ ["sky130_fd_pr__nfet_01v8", 5 ],
+ ["sky130_fd_pr__pfet_01v8_hvt", 5 ]
+ ]
+ ],
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+ ],
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+ [
+ "VNB",
+ "VPB",
+ "X",
+ "A2",
+ "A1",
+ "B1_N",
+ "VGND",
+ "VPWR"
+ ], [
+ "VNB",
+ "VPB",
+ "X",
+ "A2",
+ "A1",
+ "B1_N",
+ "VGND",
+ "VPWR"
+ ]
+ ]
+ },
+ {
+ "name": [
+ "sky130_fd_sc_hd__nor3_2",
+ "sky130_fd_sc_hd__nor3_2"
+ ],
+ "devices": [
+ [
+ ["sky130_fd_pr__pfet_01v8_hvt", 3],
+ ["sky130_fd_pr__nfet_01v8", 3 ]
+ ], [
+ ["sky130_fd_pr__pfet_01v8_hvt", 3 ],
+ ["sky130_fd_pr__nfet_01v8", 3 ]
+ ]
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+ "VGND",
+ "VNB",
+ "VPB",
+ "B",
+ "C",
+ "A",
+ "Y"
+ ], [
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+ "VGND",
+ "VNB",
+ "VPB",
+ "B",
+ "C",
+ "A",
+ "Y"
+ ]
+ ]
+ },
+ {
+ "name": [
+ "sky130_fd_sc_hd__a32o_2",
+ "sky130_fd_sc_hd__a32o_2"
+ ],
+ "devices": [
+ [
+ ["sky130_fd_pr__pfet_01v8_hvt", 6],
+ ["sky130_fd_pr__nfet_01v8", 6 ]
+ ], [
+ ["sky130_fd_pr__pfet_01v8_hvt", 6 ],
+ ["sky130_fd_pr__nfet_01v8", 6 ]
+ ]
+ ],
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+ [
+ "VGND",
+ "VNB",
+ "VPB",
+ "A2",
+ "B2",
+ "A1",
+ "B1",
+ "A3",
+ "X",
+ "VPWR"
+ ], [
+ "VGND",
+ "VNB",
+ "VPB",
+ "A2",
+ "B2",
+ "A1",
+ "B1",
+ "A3",
+ "X",
+ "VPWR"
+ ]
+ ]
+ },
+ {
+ "name": [
+ "sky130_fd_sc_hd__a32o_4",
+ "sky130_fd_sc_hd__a32o_4"
+ ],
+ "devices": [
+ [
+ ["sky130_fd_pr__nfet_01v8", 6],
+ ["sky130_fd_pr__pfet_01v8_hvt", 6 ]
+ ], [
+ ["sky130_fd_pr__nfet_01v8", 6 ],
+ ["sky130_fd_pr__pfet_01v8_hvt", 6 ]
+ ]
+ ],
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+ ],
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+ ],
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+ [
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+ "VPB",
+ "VNB",
+ "B2",
+ "A1",
+ "B1",
+ "A3",
+ "A2",
+ "X",
+ "VGND"
+ ], [
+ "VPWR",
+ "VPB",
+ "VNB",
+ "B2",
+ "A1",
+ "B1",
+ "A3",
+ "A2",
+ "X",
+ "VGND"
+ ]
+ ]
+ },
+ {
+ "name": [
+ "sky130_fd_sc_hd__o21ai_2",
+ "sky130_fd_sc_hd__o21ai_2"
+ ],
+ "devices": [
+ [
+ ["sky130_fd_pr__nfet_01v8", 3],
+ ["sky130_fd_pr__pfet_01v8_hvt", 3 ]
+ ], [
+ ["sky130_fd_pr__nfet_01v8", 3 ],
+ ["sky130_fd_pr__pfet_01v8_hvt", 3 ]
+ ]
+ ],
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+ 10
+ ],
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+ [
+ "Y",
+ "VPB",
+ "VNB",
+ "A2",
+ "VGND",
+ "VPWR",
+ "B1",
+ "A1"
+ ], [
+ "Y",
+ "VPB",
+ "VNB",
+ "A2",
+ "VGND",
+ "VPWR",
+ "B1",
+ "A1"
+ ]
+ ]
+ },
+ {
+ "name": [
+ "sky130_fd_sc_hd__or2_2",
+ "sky130_fd_sc_hd__or2_2"
+ ],
+ "devices": [
+ [
+ ["sky130_fd_pr__pfet_01v8_hvt", 3],
+ ["sky130_fd_pr__nfet_01v8", 3 ]
+ ], [
+ ["sky130_fd_pr__pfet_01v8_hvt", 3 ],
+ ["sky130_fd_pr__nfet_01v8", 3 ]
+ ]
+ ],
+ "nets": [
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+ 9
+ ],
+ "badnets": [
+ ],
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+ ],
+ "pins": [
+ [
+ "VPB",
+ "VGND",
+ "VNB",
+ "B",
+ "X",
+ "VPWR",
+ "A"
+ ], [
+ "VPB",
+ "VGND",
+ "VNB",
+ "B",
+ "X",
+ "VPWR",
+ "A"
+ ]
+ ]
+ },
+ {
+ "name": [
+ "sky130_fd_sc_hd__nand3_2",
+ "sky130_fd_sc_hd__nand3_2"
+ ],
+ "devices": [
+ [
+ ["sky130_fd_pr__nfet_01v8", 3],
+ ["sky130_fd_pr__pfet_01v8_hvt", 3 ]
+ ], [
+ ["sky130_fd_pr__nfet_01v8", 3 ],
+ ["sky130_fd_pr__pfet_01v8_hvt", 3 ]
+ ]
+ ],
+ "nets": [
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+ 10
+ ],
+ "badnets": [
+ ],
+ "badelements": [
+ ],
+ "pins": [
+ [
+ "Y",
+ "VNB",
+ "VPWR",
+ "VPB",
+ "C",
+ "B",
+ "A",
+ "VGND"
+ ], [
+ "Y",
+ "VNB",
+ "VPWR",
+ "VPB",
+ "C",
+ "B",
+ "A",
+ "VGND"
+ ]
+ ]
+ },
+ {
+ "name": [
+ "sky130_fd_sc_hd__o211ai_4",
+ "sky130_fd_sc_hd__o211ai_4"
+ ],
+ "devices": [
+ [
+ ["sky130_fd_pr__pfet_01v8_hvt", 4],
+ ["sky130_fd_pr__nfet_01v8", 8 ]
+ ], [
+ ["sky130_fd_pr__pfet_01v8_hvt", 4 ],
+ ["sky130_fd_pr__nfet_01v8", 8 ]
+ ]
+ ],
+ "nets": [
+ 14,
+ 14
+ ],
+ "badnets": [
+ ],
+ "badelements": [
+ ],
+ "pins": [
+ [
+ "VNB",
+ "Y",
+ "B1",
+ "C1",
+ "VPB",
+ "A1",
+ "VGND",
+ "A2",
+ "VPWR"
+ ], [
+ "VNB",
+ "Y",
+ "B1",
+ "C1",
+ "VPB",
+ "A1",
+ "VGND",
+ "A2",
+ "VPWR"
+ ]
+ ]
+ },
+ {
+ "name": [
+ "sky130_fd_sc_hd__o311ai_1",
+ "sky130_fd_sc_hd__o311ai_1"
+ ],
+ "devices": [
+ [
+ ["sky130_fd_pr__nfet_01v8", 5],
+ ["sky130_fd_pr__pfet_01v8_hvt", 5 ]
+ ], [
+ ["sky130_fd_pr__nfet_01v8", 5 ],
+ ["sky130_fd_pr__pfet_01v8_hvt", 5 ]
+ ]
+ ],
+ "nets": [
+ 14,
+ 14
+ ],
+ "badnets": [
+ ],
+ "badelements": [
+ ],
+ "pins": [
+ [
+ "VPB",
+ "VNB",
+ "Y",
+ "B1",
+ "C1",
+ "A3",
+ "A2",
+ "A1",
+ "VPWR",
+ "VGND"
+ ], [
+ "VPB",
+ "VNB",
+ "Y",
+ "B1",
+ "C1",
+ "A3",
+ "A2",
+ "A1",
+ "VPWR",
+ "VGND"
+ ]
+ ]
+ },
+ {
+ "name": [
+ "sky130_fd_sc_hd__nor4b_1",
+ "sky130_fd_sc_hd__nor4b_1"
+ ],
+ "devices": [
+ [
+ ["sky130_fd_pr__nfet_01v8", 5],
+ ["sky130_fd_pr__pfet_01v8_hvt", 5 ]
+ ], [
+ ["sky130_fd_pr__nfet_01v8", 5 ],
+ ["sky130_fd_pr__pfet_01v8_hvt", 5 ]
+ ]
+ ],
+ "nets": [
+ 13,
+ 13
+ ],
+ "badnets": [
+ ],
+ "badelements": [
+ ],
+ "pins": [
+ [
+ "VPWR",
+ "D_N",
+ "A",
+ "C",
+ "B",
+ "VPB",
+ "VGND",
+ "VNB",
+ "Y"
+ ], [
+ "VPWR",
+ "D_N",
+ "A",
+ "C",
+ "B",
+ "VPB",
+ "VGND",
+ "VNB",
+ "Y"
+ ]
+ ]
+ },
+ {
+ "name": [
+ "sky130_fd_sc_hd__o31ai_1",
+ "sky130_fd_sc_hd__o31ai_1"
+ ],
+ "devices": [
+ [
+ ["sky130_fd_pr__nfet_01v8", 4],
+ ["sky130_fd_pr__pfet_01v8_hvt", 4 ]
+ ], [
+ ["sky130_fd_pr__nfet_01v8", 4 ],
+ ["sky130_fd_pr__pfet_01v8_hvt", 4 ]
+ ]
+ ],
+ "nets": [
+ 12,
+ 12
+ ],
+ "badnets": [
+ ],
+ "badelements": [
+ ],
+ "pins": [
+ [
+ "VPB",
+ "VNB",
+ "A3",
+ "B1",
+ "VPWR",
+ "A1",
+ "A2",
+ "Y",
+ "VGND"
+ ], [
+ "VPB",
+ "VNB",
+ "A3",
+ "B1",
+ "VPWR",
+ "A1",
+ "A2",
+ "Y",
+ "VGND"
+ ]
+ ]
+ },
+ {
+ "name": [
+ "sky130_fd_sc_hd__nor4_2",
+ "sky130_fd_sc_hd__nor4_2"
+ ],
+ "devices": [
+ [
+ ["sky130_fd_pr__pfet_01v8_hvt", 4],
+ ["sky130_fd_pr__nfet_01v8", 4 ]
+ ], [
+ ["sky130_fd_pr__pfet_01v8_hvt", 4 ],
+ ["sky130_fd_pr__nfet_01v8", 4 ]
+ ]
+ ],
+ "nets": [
+ 12,
+ 12
+ ],
+ "badnets": [
+ ],
+ "badelements": [
+ ],
+ "pins": [
+ [
+ "VPWR",
+ "Y",
+ "VGND",
+ "VNB",
+ "VPB",
+ "A",
+ "C",
+ "B",
+ "D"
+ ], [
+ "VPWR",
+ "Y",
+ "VGND",
+ "VNB",
+ "VPB",
+ "A",
+ "C",
+ "B",
+ "D"
+ ]
+ ]
+ },
+ {
+ "name": [
+ "sky130_fd_sc_hd__o22ai_1",
+ "sky130_fd_sc_hd__o22ai_1"
+ ],
+ "devices": [
+ [
+ ["sky130_fd_pr__nfet_01v8", 4],
+ ["sky130_fd_pr__pfet_01v8_hvt", 4 ]
+ ], [
+ ["sky130_fd_pr__nfet_01v8", 4 ],
+ ["sky130_fd_pr__pfet_01v8_hvt", 4 ]
+ ]
+ ],
+ "nets": [
+ 12,
+ 12
+ ],
+ "badnets": [
+ ],
+ "badelements": [
+ ],
+ "pins": [
+ [
+ "Y",
+ "VPB",
+ "VNB",
+ "A2",
+ "A1",
+ "VPWR",
+ "B2",
+ "VGND",
+ "B1"
+ ], [
+ "Y",
+ "VPB",
+ "VNB",
+ "A2",
+ "A1",
+ "VPWR",
+ "B2",
+ "VGND",
+ "B1"
+ ]
+ ]
+ },
+ {
+ "name": [
+ "sky130_fd_sc_hd__nand2_4",
+ "sky130_fd_sc_hd__nand2_4"
+ ],
+ "devices": [
+ [
+ ["sky130_fd_pr__nfet_01v8", 2],
+ ["sky130_fd_pr__pfet_01v8_hvt", 2 ]
+ ], [
+ ["sky130_fd_pr__nfet_01v8", 2 ],
+ ["sky130_fd_pr__pfet_01v8_hvt", 2 ]
+ ]
+ ],
+ "nets": [
+ 8,
+ 8
+ ],
+ "badnets": [
+ ],
+ "badelements": [
+ ],
+ "pins": [
+ [
+ "VGND",
+ "Y",
+ "A",
+ "VNB",
+ "VPWR",
+ "VPB",
+ "B"
+ ], [
+ "VGND",
+ "Y",
+ "A",
+ "VNB",
+ "VPWR",
+ "VPB",
+ "B"
+ ]
+ ]
+ },
+ {
+ "name": [
+ "sky130_fd_sc_hd__o21bai_4",
+ "sky130_fd_sc_hd__o21bai_4"
+ ],
+ "devices": [
+ [
+ ["sky130_fd_pr__pfet_01v8_hvt", 4],
+ ["sky130_fd_pr__nfet_01v8", 4 ]
+ ], [
+ ["sky130_fd_pr__pfet_01v8_hvt", 4 ],
+ ["sky130_fd_pr__nfet_01v8", 4 ]
+ ]
+ ],
+ "nets": [
+ 11,
+ 11
+ ],
+ "badnets": [
+ ],
+ "badelements": [
+ ],
+ "pins": [
+ [
+ "A1",
+ "A2",
+ "B1_N",
+ "VNB",
+ "VPB",
+ "Y",
+ "VGND",
+ "VPWR"
+ ], [
+ "A1",
+ "A2",
+ "B1_N",
+ "VNB",
+ "VPB",
+ "Y",
+ "VGND",
+ "VPWR"
+ ]
+ ]
+ },
+ {
+ "name": [
+ "sky130_fd_sc_hd__a211oi_1",
+ "sky130_fd_sc_hd__a211oi_1"
+ ],
+ "devices": [
+ [
+ ["sky130_fd_pr__pfet_01v8_hvt", 4],
+ ["sky130_fd_pr__nfet_01v8", 4 ]
+ ], [
+ ["sky130_fd_pr__pfet_01v8_hvt", 4 ],
+ ["sky130_fd_pr__nfet_01v8", 4 ]
+ ]
+ ],
+ "nets": [
+ 12,
+ 12
+ ],
+ "badnets": [
+ ],
+ "badelements": [
+ ],
+ "pins": [
+ [
+ "VNB",
+ "Y",
+ "VPB",
+ "A2",
+ "C1",
+ "VPWR",
+ "A1",
+ "B1",
+ "VGND"
+ ], [
+ "VNB",
+ "Y",
+ "VPB",
+ "A2",
+ "C1",
+ "VPWR",
+ "A1",
+ "B1",
+ "VGND"
+ ]
+ ]
+ },
+ {
+ "name": [
+ "sky130_fd_sc_hd__inv_4",
+ "sky130_fd_sc_hd__inv_4"
+ ],
+ "devices": [
+ [
+ ["sky130_fd_pr__pfet_01v8_hvt", 1],
+ ["sky130_fd_pr__nfet_01v8", 1 ]
+ ], [
+ ["sky130_fd_pr__pfet_01v8_hvt", 1 ],
+ ["sky130_fd_pr__nfet_01v8", 1 ]
+ ]
+ ],
+ "nets": [
+ 6,
+ 6
+ ],
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+ "VNB",
+ "VPWR",
+ "VPB"
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+ ]
+ },
+ {
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+ "sky130_fd_sc_hd__mux2_8"
+ ],
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+ [
+ ["sky130_fd_pr__nfet_01v8", 6],
+ ["sky130_fd_pr__pfet_01v8_hvt", 6 ]
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+ ["sky130_fd_pr__pfet_01v8_hvt", 6 ]
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+ "VPB",
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+ "S",
+ "VPWR"
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+ },
+ {
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+ "sky130_fd_sc_hd__inv_6",
+ "sky130_fd_sc_hd__inv_6"
+ ],
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+ [
+ ["sky130_fd_pr__pfet_01v8_hvt", 1],
+ ["sky130_fd_pr__nfet_01v8", 1 ]
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+ ["sky130_fd_pr__nfet_01v8", 1 ]
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+ "VPWR",
+ "VPB",
+ "VGND",
+ "VNB"
+ ]
+ ]
+ },
+ {
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+ "sky130_fd_sc_hd__a22oi_4",
+ "sky130_fd_sc_hd__a22oi_4"
+ ],
+ "devices": [
+ [
+ ["sky130_fd_pr__nfet_01v8", 4],
+ ["sky130_fd_pr__pfet_01v8_hvt", 4 ]
+ ], [
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+ ["sky130_fd_pr__pfet_01v8_hvt", 4 ]
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+ "VGND",
+ "B2"
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+ "Y",
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+ "A2",
+ "A1",
+ "B1",
+ "VGND",
+ "B2"
+ ]
+ ]
+ },
+ {
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+ "sky130_fd_sc_hd__nor2_8"
+ ],
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+ [
+ ["sky130_fd_pr__pfet_01v8_hvt", 2],
+ ["sky130_fd_pr__nfet_01v8", 2 ]
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+ ["sky130_fd_pr__nfet_01v8", 2 ]
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+ "A",
+ "VPB",
+ "VGND",
+ "VNB",
+ "B",
+ "VPWR"
+ ]
+ ]
+ },
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+ "sky130_fd_sc_hd__nor4_4",
+ "sky130_fd_sc_hd__nor4_4"
+ ],
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+ [
+ ["sky130_fd_pr__pfet_01v8_hvt", 4],
+ ["sky130_fd_pr__nfet_01v8", 4 ]
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+ ["sky130_fd_pr__pfet_01v8_hvt", 4 ],
+ ["sky130_fd_pr__nfet_01v8", 4 ]
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+ "A",
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+ "VGND",
+ "VNB",
+ "B",
+ "C",
+ "A",
+ "D",
+ "VPWR"
+ ]
+ ]
+ },
+ {
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+ "sky130_fd_sc_hd__a41o_2",
+ "sky130_fd_sc_hd__a41o_2"
+ ],
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+ [
+ ["sky130_fd_pr__pfet_01v8_hvt", 6],
+ ["sky130_fd_pr__nfet_01v8", 6 ]
+ ], [
+ ["sky130_fd_pr__pfet_01v8_hvt", 6 ],
+ ["sky130_fd_pr__nfet_01v8", 6 ]
+ ]
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+ "VPB",
+ "A3",
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+ "A4",
+ "B1",
+ "A1",
+ "X",
+ "VPWR"
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+ "VGND",
+ "VNB",
+ "VPB",
+ "A3",
+ "A2",
+ "A4",
+ "B1",
+ "A1",
+ "X",
+ "VPWR"
+ ]
+ ]
+ },
+ {
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+ "sky130_fd_sc_hd__mux2_2",
+ "sky130_fd_sc_hd__mux2_2"
+ ],
+ "devices": [
+ [
+ ["sky130_fd_pr__pfet_01v8_hvt", 6],
+ ["sky130_fd_pr__nfet_01v8", 6 ]
+ ], [
+ ["sky130_fd_pr__pfet_01v8_hvt", 6 ],
+ ["sky130_fd_pr__nfet_01v8", 6 ]
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+ "VPWR",
+ "S"
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+ "VPB",
+ "A1",
+ "A0",
+ "X",
+ "VGND",
+ "VPWR",
+ "S"
+ ]
+ ]
+ },
+ {
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+ "sky130_fd_sc_hd__nand2b_2",
+ "sky130_fd_sc_hd__nand2b_2"
+ ],
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+ [
+ ["sky130_fd_pr__pfet_01v8_hvt", 3],
+ ["sky130_fd_pr__nfet_01v8", 3 ]
+ ], [
+ ["sky130_fd_pr__pfet_01v8_hvt", 3 ],
+ ["sky130_fd_pr__nfet_01v8", 3 ]
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+ "VPB"
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+ "VGND",
+ "A_N",
+ "VNB",
+ "VPWR",
+ "Y",
+ "VPB"
+ ]
+ ]
+ },
+ {
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+ "sky130_fd_sc_hd__o221ai_4",
+ "sky130_fd_sc_hd__o221ai_4"
+ ],
+ "devices": [
+ [
+ ["sky130_fd_pr__nfet_01v8", 5],
+ ["sky130_fd_pr__pfet_01v8_hvt", 5 ]
+ ], [
+ ["sky130_fd_pr__nfet_01v8", 5 ],
+ ["sky130_fd_pr__pfet_01v8_hvt", 5 ]
+ ]
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+ "VNB",
+ "B2",
+ "C1",
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+ "VGND",
+ "A2",
+ "A1",
+ "Y"
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+ "VPB",
+ "VNB",
+ "B2",
+ "C1",
+ "B1",
+ "VGND",
+ "A2",
+ "A1",
+ "Y"
+ ]
+ ]
+ },
+ {
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+ "sky130_fd_sc_hd__a211o_4",
+ "sky130_fd_sc_hd__a211o_4"
+ ],
+ "devices": [
+ [
+ ["sky130_fd_pr__pfet_01v8_hvt", 7],
+ ["sky130_fd_pr__nfet_01v8", 7 ]
+ ], [
+ ["sky130_fd_pr__pfet_01v8_hvt", 7 ],
+ ["sky130_fd_pr__nfet_01v8", 7 ]
+ ]
+ ],
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+ [
+ "VGND",
+ "VPB",
+ "VNB",
+ "C1",
+ "A2",
+ "VPWR",
+ "A1",
+ "B1",
+ "X"
+ ], [
+ "VGND",
+ "VPB",
+ "VNB",
+ "C1",
+ "A2",
+ "VPWR",
+ "A1",
+ "B1",
+ "X"
+ ]
+ ]
+ },
+ {
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+ "sky130_fd_sc_hd__o2bb2a_2",
+ "sky130_fd_sc_hd__o2bb2a_2"
+ ],
+ "devices": [
+ [
+ ["sky130_fd_pr__nfet_01v8", 6],
+ ["sky130_fd_pr__pfet_01v8_hvt", 6 ]
+ ], [
+ ["sky130_fd_pr__nfet_01v8", 6 ],
+ ["sky130_fd_pr__pfet_01v8_hvt", 6 ]
+ ]
+ ],
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+ ],
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+ "VPWR",
+ "VPB",
+ "VNB",
+ "VGND",
+ "A1_N",
+ "A2_N",
+ "X",
+ "B2",
+ "B1"
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+ "VPB",
+ "VNB",
+ "VGND",
+ "A1_N",
+ "A2_N",
+ "X",
+ "B2",
+ "B1"
+ ]
+ ]
+ },
+ {
+ "name": [
+ "sky130_fd_sc_hd__nand2b_4",
+ "sky130_fd_sc_hd__nand2b_4"
+ ],
+ "devices": [
+ [
+ ["sky130_fd_pr__nfet_01v8", 3],
+ ["sky130_fd_pr__pfet_01v8_hvt", 3 ]
+ ], [
+ ["sky130_fd_pr__nfet_01v8", 3 ],
+ ["sky130_fd_pr__pfet_01v8_hvt", 3 ]
+ ]
+ ],
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+ ],
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+ "VPWR",
+ "Y",
+ "VPB",
+ "VNB",
+ "B",
+ "VGND",
+ "A_N"
+ ], [
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+ "Y",
+ "VPB",
+ "VNB",
+ "B",
+ "VGND",
+ "A_N"
+ ]
+ ]
+ },
+ {
+ "name": [
+ "sky130_fd_sc_hd__o21a_2",
+ "sky130_fd_sc_hd__o21a_2"
+ ],
+ "devices": [
+ [
+ ["sky130_fd_pr__pfet_01v8_hvt", 4],
+ ["sky130_fd_pr__nfet_01v8", 4 ]
+ ], [
+ ["sky130_fd_pr__pfet_01v8_hvt", 4 ],
+ ["sky130_fd_pr__nfet_01v8", 4 ]
+ ]
+ ],
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+ ],
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+ [
+ "VNB",
+ "VPB",
+ "A2",
+ "X",
+ "A1",
+ "B1",
+ "VGND",
+ "VPWR"
+ ], [
+ "VNB",
+ "VPB",
+ "A2",
+ "X",
+ "A1",
+ "B1",
+ "VGND",
+ "VPWR"
+ ]
+ ]
+ },
+ {
+ "name": [
+ "sky130_fd_sc_hd__o2111ai_2",
+ "sky130_fd_sc_hd__o2111ai_2"
+ ],
+ "devices": [
+ [
+ ["sky130_fd_pr__pfet_01v8_hvt", 5],
+ ["sky130_fd_pr__nfet_01v8", 5 ]
+ ], [
+ ["sky130_fd_pr__pfet_01v8_hvt", 5 ],
+ ["sky130_fd_pr__nfet_01v8", 5 ]
+ ]
+ ],
+ "nets": [
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+ 14
+ ],
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+ ],
+ "badelements": [
+ ],
+ "pins": [
+ [
+ "VPWR",
+ "A2",
+ "A1",
+ "B1",
+ "D1",
+ "VGND",
+ "C1",
+ "Y",
+ "VPB",
+ "VNB"
+ ], [
+ "VPWR",
+ "A2",
+ "A1",
+ "B1",
+ "D1",
+ "VGND",
+ "C1",
+ "Y",
+ "VPB",
+ "VNB"
+ ]
+ ]
+ },
+ {
+ "name": [
+ "sky130_fd_sc_hd__a311o_2",
+ "sky130_fd_sc_hd__a311o_2"
+ ],
+ "devices": [
+ [
+ ["sky130_fd_pr__pfet_01v8_hvt", 6],
+ ["sky130_fd_pr__nfet_01v8", 6 ]
+ ], [
+ ["sky130_fd_pr__pfet_01v8_hvt", 6 ],
+ ["sky130_fd_pr__nfet_01v8", 6 ]
+ ]
+ ],
+ "nets": [
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+ 15
+ ],
+ "badnets": [
+ ],
+ "badelements": [
+ ],
+ "pins": [
+ [
+ "VPWR",
+ "VGND",
+ "A2",
+ "B1",
+ "A3",
+ "C1",
+ "X",
+ "A1",
+ "VPB",
+ "VNB"
+ ], [
+ "VPWR",
+ "VGND",
+ "A2",
+ "B1",
+ "A3",
+ "C1",
+ "X",
+ "A1",
+ "VPB",
+ "VNB"
+ ]
+ ]
+ },
+ {
+ "name": [
+ "sky130_fd_sc_hd__a221oi_1",
+ "sky130_fd_sc_hd__a221oi_1"
+ ],
+ "devices": [
+ [
+ ["sky130_fd_pr__nfet_01v8", 5],
+ ["sky130_fd_pr__pfet_01v8_hvt", 5 ]
+ ], [
+ ["sky130_fd_pr__nfet_01v8", 5 ],
+ ["sky130_fd_pr__pfet_01v8_hvt", 5 ]
+ ]
+ ],
+ "nets": [
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+ 14
+ ],
+ "badnets": [
+ ],
+ "badelements": [
+ ],
+ "pins": [
+ [
+ "VGND",
+ "VNB",
+ "VPB",
+ "Y",
+ "B2",
+ "A2",
+ "VPWR",
+ "A1",
+ "B1",
+ "C1"
+ ], [
+ "VGND",
+ "VNB",
+ "VPB",
+ "Y",
+ "B2",
+ "A2",
+ "VPWR",
+ "A1",
+ "B1",
+ "C1"
+ ]
+ ]
+ },
+ {
+ "name": [
+ "sky130_fd_sc_hd__o41a_4",
+ "sky130_fd_sc_hd__o41a_4"
+ ],
+ "devices": [
+ [
+ ["sky130_fd_pr__nfet_01v8", 6],
+ ["sky130_fd_pr__pfet_01v8_hvt", 6 ]
+ ], [
+ ["sky130_fd_pr__nfet_01v8", 6 ],
+ ["sky130_fd_pr__pfet_01v8_hvt", 6 ]
+ ]
+ ],
+ "nets": [
+ 15,
+ 15
+ ],
+ "badnets": [
+ ],
+ "badelements": [
+ ],
+ "pins": [
+ [
+ "VPWR",
+ "VPB",
+ "VNB",
+ "A2",
+ "A3",
+ "A4",
+ "B1",
+ "X",
+ "A1",
+ "VGND"
+ ], [
+ "VPWR",
+ "VPB",
+ "VNB",
+ "A2",
+ "A3",
+ "A4",
+ "B1",
+ "X",
+ "A1",
+ "VGND"
+ ]
+ ]
+ },
+ {
+ "name": [
+ "sky130_fd_sc_hd__nand4b_2",
+ "sky130_fd_sc_hd__nand4b_2"
+ ],
+ "devices": [
+ [
+ ["sky130_fd_pr__nfet_01v8", 5],
+ ["sky130_fd_pr__pfet_01v8_hvt", 5 ]
+ ], [
+ ["sky130_fd_pr__nfet_01v8", 5 ],
+ ["sky130_fd_pr__pfet_01v8_hvt", 5 ]
+ ]
+ ],
+ "nets": [
+ 13,
+ 13
+ ],
+ "badnets": [
+ ],
+ "badelements": [
+ ],
+ "pins": [
+ [
+ "C",
+ "D",
+ "B",
+ "A_N",
+ "VGND",
+ "VPWR",
+ "Y",
+ "VPB",
+ "VNB"
+ ], [
+ "C",
+ "D",
+ "B",
+ "A_N",
+ "VGND",
+ "VPWR",
+ "Y",
+ "VPB",
+ "VNB"
+ ]
+ ]
+ },
+ {
+ "name": [
+ "sky130_fd_sc_hd__o2bb2ai_1",
+ "sky130_fd_sc_hd__o2bb2ai_1"
+ ],
+ "devices": [
+ [
+ ["sky130_fd_pr__pfet_01v8_hvt", 5],
+ ["sky130_fd_pr__nfet_01v8", 5 ]
+ ], [
+ ["sky130_fd_pr__pfet_01v8_hvt", 5 ],
+ ["sky130_fd_pr__nfet_01v8", 5 ]
+ ]
+ ],
+ "nets": [
+ 13,
+ 13
+ ],
+ "badnets": [
+ ],
+ "badelements": [
+ ],
+ "pins": [
+ [
+ "Y",
+ "VGND",
+ "VPB",
+ "VNB",
+ "A2_N",
+ "B2",
+ "B1",
+ "A1_N",
+ "VPWR"
+ ], [
+ "Y",
+ "VGND",
+ "VPB",
+ "VNB",
+ "A2_N",
+ "B2",
+ "B1",
+ "A1_N",
+ "VPWR"
+ ]
+ ]
+ },
+ {
+ "name": [
+ "sky130_fd_sc_hd__o31a_4",
+ "sky130_fd_sc_hd__o31a_4"
+ ],
+ "devices": [
+ [
+ ["sky130_fd_pr__pfet_01v8_hvt", 5],
+ ["sky130_fd_pr__nfet_01v8", 5 ]
+ ], [
+ ["sky130_fd_pr__pfet_01v8_hvt", 5 ],
+ ["sky130_fd_pr__nfet_01v8", 5 ]
+ ]
+ ],
+ "nets": [
+ 13,
+ 13
+ ],
+ "badnets": [
+ ],
+ "badelements": [
+ ],
+ "pins": [
+ [
+ "VGND",
+ "VPB",
+ "VNB",
+ "X",
+ "A3",
+ "A1",
+ "B1",
+ "A2",
+ "VPWR"
+ ], [
+ "VGND",
+ "VPB",
+ "VNB",
+ "X",
+ "A3",
+ "A1",
+ "B1",
+ "A2",
+ "VPWR"
+ ]
+ ]
+ },
+ {
+ "name": [
+ "sky130_fd_sc_hd__xor2_4",
+ "sky130_fd_sc_hd__xor2_4"
+ ],
+ "devices": [
+ [
+ ["sky130_fd_pr__pfet_01v8_hvt", 5],
+ ["sky130_fd_pr__nfet_01v8", 5 ]
+ ], [
+ ["sky130_fd_pr__pfet_01v8_hvt", 5 ],
+ ["sky130_fd_pr__nfet_01v8", 5 ]
+ ]
+ ],
+ "nets": [
+ 11,
+ 11
+ ],
+ "badnets": [
+ ],
+ "badelements": [
+ ],
+ "pins": [
+ [
+ "VPB",
+ "VNB",
+ "X",
+ "VPWR",
+ "A",
+ "VGND",
+ "B"
+ ], [
+ "VPB",
+ "VNB",
+ "X",
+ "VPWR",
+ "A",
+ "VGND",
+ "B"
+ ]
+ ]
+ },
+ {
+ "name": [
+ "sky130_fd_sc_hd__a2bb2o_2",
+ "sky130_fd_sc_hd__a2bb2o_2"
+ ],
+ "devices": [
+ [
+ ["sky130_fd_pr__pfet_01v8_hvt", 6],
+ ["sky130_fd_pr__nfet_01v8", 6 ]
+ ], [
+ ["sky130_fd_pr__pfet_01v8_hvt", 6 ],
+ ["sky130_fd_pr__nfet_01v8", 6 ]
+ ]
+ ],
+ "nets": [
+ 14,
+ 14
+ ],
+ "badnets": [
+ ],
+ "badelements": [
+ ],
+ "pins": [
+ [
+ "VNB",
+ "VPB",
+ "A1_N",
+ "X",
+ "B1",
+ "B2",
+ "A2_N",
+ "VGND",
+ "VPWR"
+ ], [
+ "VNB",
+ "VPB",
+ "A1_N",
+ "X",
+ "B1",
+ "B2",
+ "A2_N",
+ "VGND",
+ "VPWR"
+ ]
+ ]
+ },
+ {
+ "name": [
+ "sky130_fd_sc_hd__nor3_4",
+ "sky130_fd_sc_hd__nor3_4"
+ ],
+ "devices": [
+ [
+ ["sky130_fd_pr__pfet_01v8_hvt", 3],
+ ["sky130_fd_pr__nfet_01v8", 3 ]
+ ], [
+ ["sky130_fd_pr__pfet_01v8_hvt", 3 ],
+ ["sky130_fd_pr__nfet_01v8", 3 ]
+ ]
+ ],
+ "nets": [
+ 10,
+ 10
+ ],
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+ ],
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+ "VNB",
+ "B",
+ "A",
+ "C",
+ "VPWR"
+ ]
+ ]
+ },
+ {
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+ "sky130_fd_sc_hd__o211ai_2"
+ ],
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+ [
+ ["sky130_fd_pr__nfet_01v8", 4],
+ ["sky130_fd_pr__pfet_01v8_hvt", 4 ]
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+ ["sky130_fd_pr__pfet_01v8_hvt", 4 ]
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+ "C1",
+ "A1",
+ "B1",
+ "VGND",
+ "VPWR"
+ ]
+ ]
+ },
+ {
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+ "sky130_fd_sc_hd__o311ai_4",
+ "sky130_fd_sc_hd__o311ai_4"
+ ],
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+ [
+ ["sky130_fd_pr__pfet_01v8_hvt", 5],
+ ["sky130_fd_pr__nfet_01v8", 5 ]
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+ ["sky130_fd_pr__nfet_01v8", 5 ]
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+ "B1",
+ "C1"
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+ "VNB",
+ "VPWR",
+ "VGND",
+ "A1",
+ "A3",
+ "A2",
+ "B1",
+ "C1"
+ ]
+ ]
+ },
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+ "sky130_fd_sc_hd__o211a_2",
+ "sky130_fd_sc_hd__o211a_2"
+ ],
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+ [
+ ["sky130_fd_pr__pfet_01v8_hvt", 5],
+ ["sky130_fd_pr__nfet_01v8", 5 ]
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+ ["sky130_fd_pr__nfet_01v8", 5 ]
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+ "VPWR",
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+ "X",
+ "A2",
+ "A1"
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+ "VPB",
+ "VNB",
+ "VPWR",
+ "B1",
+ "C1",
+ "X",
+ "A2",
+ "A1"
+ ]
+ ]
+ },
+ {
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+ "sky130_fd_sc_hd__nand3b_1",
+ "sky130_fd_sc_hd__nand3b_1"
+ ],
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+ [
+ ["sky130_fd_pr__pfet_01v8_hvt", 4],
+ ["sky130_fd_pr__nfet_01v8", 4 ]
+ ], [
+ ["sky130_fd_pr__pfet_01v8_hvt", 4 ],
+ ["sky130_fd_pr__nfet_01v8", 4 ]
+ ]
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+ "C",
+ "VNB",
+ "VPWR",
+ "VPB",
+ "Y"
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+ "VGND",
+ "B",
+ "C",
+ "VNB",
+ "VPWR",
+ "VPB",
+ "Y"
+ ]
+ ]
+ },
+ {
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+ "sky130_fd_sc_hd__o22a_2",
+ "sky130_fd_sc_hd__o22a_2"
+ ],
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+ [
+ ["sky130_fd_pr__nfet_01v8", 5],
+ ["sky130_fd_pr__pfet_01v8_hvt", 5 ]
+ ], [
+ ["sky130_fd_pr__nfet_01v8", 5 ],
+ ["sky130_fd_pr__pfet_01v8_hvt", 5 ]
+ ]
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+ "VNB",
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+ "B1",
+ "A2",
+ "A1"
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+ "VGND",
+ "VPB",
+ "VNB",
+ "X",
+ "B2",
+ "B1",
+ "A2",
+ "A1"
+ ]
+ ]
+ },
+ {
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+ "sky130_fd_sc_hd__a2bb2oi_4",
+ "sky130_fd_sc_hd__a2bb2oi_4"
+ ],
+ "devices": [
+ [
+ ["sky130_fd_pr__nfet_01v8", 5],
+ ["sky130_fd_pr__pfet_01v8_hvt", 5 ]
+ ], [
+ ["sky130_fd_pr__nfet_01v8", 5 ],
+ ["sky130_fd_pr__pfet_01v8_hvt", 5 ]
+ ]
+ ],
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+ "VNB",
+ "A1_N",
+ "A2_N",
+ "B2",
+ "B1",
+ "Y",
+ "VPWR"
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+ "VPB",
+ "VNB",
+ "A1_N",
+ "A2_N",
+ "B2",
+ "B1",
+ "Y",
+ "VPWR"
+ ]
+ ]
+ },
+ {
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+ "sky130_fd_sc_hd__o21a_4",
+ "sky130_fd_sc_hd__o21a_4"
+ ],
+ "devices": [
+ [
+ ["sky130_fd_pr__nfet_01v8", 4],
+ ["sky130_fd_pr__pfet_01v8_hvt", 6 ]
+ ], [
+ ["sky130_fd_pr__nfet_01v8", 4 ],
+ ["sky130_fd_pr__pfet_01v8_hvt", 6 ]
+ ]
+ ],
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+ "A2",
+ "VGND",
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+ "X",
+ "B1"
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+ "VPWR",
+ "A2",
+ "VGND",
+ "A1",
+ "VPB",
+ "X",
+ "B1"
+ ]
+ ]
+ },
+ {
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+ "sky130_fd_sc_hd__a2bb2oi_2",
+ "sky130_fd_sc_hd__a2bb2oi_2"
+ ],
+ "devices": [
+ [
+ ["sky130_fd_pr__pfet_01v8_hvt", 5],
+ ["sky130_fd_pr__nfet_01v8", 5 ]
+ ], [
+ ["sky130_fd_pr__pfet_01v8_hvt", 5 ],
+ ["sky130_fd_pr__nfet_01v8", 5 ]
+ ]
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+ "VNB",
+ "VPB",
+ "B2",
+ "A2_N",
+ "A1_N",
+ "B1",
+ "Y",
+ "VPWR"
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+ "VNB",
+ "VPB",
+ "B2",
+ "A2_N",
+ "A1_N",
+ "B1",
+ "Y",
+ "VPWR"
+ ]
+ ]
+ },
+ {
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+ "sky130_fd_sc_hd__o311a_2",
+ "sky130_fd_sc_hd__o311a_2"
+ ],
+ "devices": [
+ [
+ ["sky130_fd_pr__pfet_01v8_hvt", 6],
+ ["sky130_fd_pr__nfet_01v8", 6 ]
+ ], [
+ ["sky130_fd_pr__pfet_01v8_hvt", 6 ],
+ ["sky130_fd_pr__nfet_01v8", 6 ]
+ ]
+ ],
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+ "VPB",
+ "VNB",
+ "X",
+ "A2",
+ "B1",
+ "A3",
+ "A1",
+ "C1"
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+ "VGND",
+ "VPB",
+ "VNB",
+ "X",
+ "A2",
+ "B1",
+ "A3",
+ "A1",
+ "C1"
+ ]
+ ]
+ },
+ {
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+ "sky130_fd_sc_hd__o221ai_1",
+ "sky130_fd_sc_hd__o221ai_1"
+ ],
+ "devices": [
+ [
+ ["sky130_fd_pr__nfet_01v8", 5],
+ ["sky130_fd_pr__pfet_01v8_hvt", 5 ]
+ ], [
+ ["sky130_fd_pr__nfet_01v8", 5 ],
+ ["sky130_fd_pr__pfet_01v8_hvt", 5 ]
+ ]
+ ],
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+ ],
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+ "VPB",
+ "VNB",
+ "Y",
+ "B1",
+ "C1",
+ "VGND",
+ "A1",
+ "A2",
+ "B2",
+ "VPWR"
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+ "VNB",
+ "Y",
+ "B1",
+ "C1",
+ "VGND",
+ "A1",
+ "A2",
+ "B2",
+ "VPWR"
+ ]
+ ]
+ },
+ {
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+ "sky130_fd_sc_hd__inv_12",
+ "sky130_fd_sc_hd__inv_12"
+ ],
+ "devices": [
+ [
+ ["sky130_fd_pr__pfet_01v8_hvt", 1],
+ ["sky130_fd_pr__nfet_01v8", 1 ]
+ ], [
+ ["sky130_fd_pr__pfet_01v8_hvt", 1 ],
+ ["sky130_fd_pr__nfet_01v8", 1 ]
+ ]
+ ],
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+ 6
+ ],
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+ "Y",
+ "A",
+ "VGND",
+ "VNB",
+ "VPWR",
+ "VPB"
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+ "A",
+ "VGND",
+ "VNB",
+ "VPWR",
+ "VPB"
+ ]
+ ]
+ },
+ {
+ "name": [
+ "sky130_fd_sc_hd__o211a_4",
+ "sky130_fd_sc_hd__o211a_4"
+ ],
+ "devices": [
+ [
+ ["sky130_fd_pr__nfet_01v8", 7],
+ ["sky130_fd_pr__pfet_01v8_hvt", 7 ]
+ ], [
+ ["sky130_fd_pr__nfet_01v8", 7 ],
+ ["sky130_fd_pr__pfet_01v8_hvt", 7 ]
+ ]
+ ],
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+ 15
+ ],
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+ ],
+ "badelements": [
+ ],
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+ [
+ "X",
+ "VPWR",
+ "VPB",
+ "VNB",
+ "B1",
+ "C1",
+ "A2",
+ "VGND",
+ "A1"
+ ], [
+ "X",
+ "VPWR",
+ "VPB",
+ "VNB",
+ "B1",
+ "C1",
+ "A2",
+ "VGND",
+ "A1"
+ ]
+ ]
+ },
+ {
+ "name": [
+ "sky130_fd_sc_hd__o311a_4",
+ "sky130_fd_sc_hd__o311a_4"
+ ],
+ "devices": [
+ [
+ ["sky130_fd_pr__pfet_01v8_hvt", 6],
+ ["sky130_fd_pr__nfet_01v8", 6 ]
+ ], [
+ ["sky130_fd_pr__pfet_01v8_hvt", 6 ],
+ ["sky130_fd_pr__nfet_01v8", 6 ]
+ ]
+ ],
+ "nets": [
+ 15,
+ 15
+ ],
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+ ],
+ "badelements": [
+ ],
+ "pins": [
+ [
+ "VPWR",
+ "VGND",
+ "C1",
+ "B1",
+ "A1",
+ "X",
+ "A2",
+ "A3",
+ "VPB",
+ "VNB"
+ ], [
+ "VPWR",
+ "VGND",
+ "C1",
+ "B1",
+ "A1",
+ "X",
+ "A2",
+ "A3",
+ "VPB",
+ "VNB"
+ ]
+ ]
+ },
+ {
+ "name": [
+ "sky130_fd_sc_hd__a41oi_2",
+ "sky130_fd_sc_hd__a41oi_2"
+ ],
+ "devices": [
+ [
+ ["sky130_fd_pr__pfet_01v8_hvt", 5],
+ ["sky130_fd_pr__nfet_01v8", 5 ]
+ ], [
+ ["sky130_fd_pr__pfet_01v8_hvt", 5 ],
+ ["sky130_fd_pr__nfet_01v8", 5 ]
+ ]
+ ],
+ "nets": [
+ 14,
+ 14
+ ],
+ "badnets": [
+ ],
+ "badelements": [
+ ],
+ "pins": [
+ [
+ "VPWR",
+ "Y",
+ "A1",
+ "B1",
+ "VGND",
+ "A3",
+ "A2",
+ "A4",
+ "VNB",
+ "VPB"
+ ], [
+ "VPWR",
+ "Y",
+ "A1",
+ "B1",
+ "VGND",
+ "A3",
+ "A2",
+ "A4",
+ "VNB",
+ "VPB"
+ ]
+ ]
+ },
+ {
+ "name": [
+ "sky130_fd_sc_hd__nand4b_4",
+ "sky130_fd_sc_hd__nand4b_4"
+ ],
+ "devices": [
+ [
+ ["sky130_fd_pr__nfet_01v8", 5],
+ ["sky130_fd_pr__pfet_01v8_hvt", 5 ]
+ ], [
+ ["sky130_fd_pr__nfet_01v8", 5 ],
+ ["sky130_fd_pr__pfet_01v8_hvt", 5 ]
+ ]
+ ],
+ "nets": [
+ 13,
+ 13
+ ],
+ "badnets": [
+ ],
+ "badelements": [
+ ],
+ "pins": [
+ [
+ "VNB",
+ "VPWR",
+ "Y",
+ "VPB",
+ "VGND",
+ "D",
+ "B",
+ "C",
+ "A_N"
+ ], [
+ "VNB",
+ "VPWR",
+ "Y",
+ "VPB",
+ "VGND",
+ "D",
+ "B",
+ "C",
+ "A_N"
+ ]
+ ]
+ },
+ {
+ "name": [
+ "sky130_fd_sc_hd__xor2_2",
+ "sky130_fd_sc_hd__xor2_2"
+ ],
+ "devices": [
+ [
+ ["sky130_fd_pr__pfet_01v8_hvt", 5],
+ ["sky130_fd_pr__nfet_01v8", 5 ]
+ ], [
+ ["sky130_fd_pr__pfet_01v8_hvt", 5 ],
+ ["sky130_fd_pr__nfet_01v8", 5 ]
+ ]
+ ],
+ "nets": [
+ 11,
+ 11
+ ],
+ "badnets": [
+ ],
+ "badelements": [
+ ],
+ "pins": [
+ [
+ "VPB",
+ "VNB",
+ "VPWR",
+ "X",
+ "A",
+ "B",
+ "VGND"
+ ], [
+ "VPB",
+ "VNB",
+ "VPWR",
+ "X",
+ "A",
+ "B",
+ "VGND"
+ ]
+ ]
+ },
+ {
+ "name": [
+ "sky130_fd_sc_hd__a2111o_4",
+ "sky130_fd_sc_hd__a2111o_4"
+ ],
+ "devices": [
+ [
+ ["sky130_fd_pr__pfet_01v8_hvt", 6],
+ ["sky130_fd_pr__nfet_01v8", 6 ]
+ ], [
+ ["sky130_fd_pr__pfet_01v8_hvt", 6 ],
+ ["sky130_fd_pr__nfet_01v8", 6 ]
+ ]
+ ],
+ "nets": [
+ 15,
+ 15
+ ],
+ "badnets": [
+ ],
+ "badelements": [
+ ],
+ "pins": [
+ [
+ "VPWR",
+ "VGND",
+ "VPB",
+ "VNB",
+ "B1",
+ "A1",
+ "X",
+ "D1",
+ "C1",
+ "A2"
+ ], [
+ "VPWR",
+ "VGND",
+ "VPB",
+ "VNB",
+ "B1",
+ "A1",
+ "X",
+ "D1",
+ "C1",
+ "A2"
+ ]
+ ]
+ },
+ {
+ "name": [
+ "sky130_fd_sc_hd__o41a_2",
+ "sky130_fd_sc_hd__o41a_2"
+ ],
+ "devices": [
+ [
+ ["sky130_fd_pr__nfet_01v8", 6],
+ ["sky130_fd_pr__pfet_01v8_hvt", 6 ]
+ ], [
+ ["sky130_fd_pr__nfet_01v8", 6 ],
+ ["sky130_fd_pr__pfet_01v8_hvt", 6 ]
+ ]
+ ],
+ "nets": [
+ 15,
+ 15
+ ],
+ "badnets": [
+ ],
+ "badelements": [
+ ],
+ "pins": [
+ [
+ "VPWR",
+ "VPB",
+ "VNB",
+ "B1",
+ "A3",
+ "A2",
+ "A1",
+ "A4",
+ "X",
+ "VGND"
+ ], [
+ "VPWR",
+ "VPB",
+ "VNB",
+ "B1",
+ "A3",
+ "A2",
+ "A1",
+ "A4",
+ "X",
+ "VGND"
+ ]
+ ]
+ },
+ {
+ "name": [
+ "sky130_fd_sc_hd__o221a_2",
+ "sky130_fd_sc_hd__o221a_2"
+ ],
+ "devices": [
+ [
+ ["sky130_fd_pr__pfet_01v8_hvt", 6],
+ ["sky130_fd_pr__nfet_01v8", 6 ]
+ ], [
+ ["sky130_fd_pr__pfet_01v8_hvt", 6 ],
+ ["sky130_fd_pr__nfet_01v8", 6 ]
+ ]
+ ],
+ "nets": [
+ 15,
+ 15
+ ],
+ "badnets": [
+ ],
+ "badelements": [
+ ],
+ "pins": [
+ [
+ "VGND",
+ "X",
+ "C1",
+ "A2",
+ "B2",
+ "B1",
+ "A1",
+ "VNB",
+ "VPB",
+ "VPWR"
+ ], [
+ "VGND",
+ "X",
+ "C1",
+ "A2",
+ "B2",
+ "B1",
+ "A1",
+ "VNB",
+ "VPB",
+ "VPWR"
+ ]
+ ]
+ },
+ {
+ "name": [
+ "sky130_fd_sc_hd__a2bb2oi_1",
+ "sky130_fd_sc_hd__a2bb2oi_1"
+ ],
+ "devices": [
+ [
+ ["sky130_fd_pr__pfet_01v8_hvt", 5],
+ ["sky130_fd_pr__nfet_01v8", 5 ]
+ ], [
+ ["sky130_fd_pr__pfet_01v8_hvt", 5 ],
+ ["sky130_fd_pr__nfet_01v8", 5 ]
+ ]
+ ],
+ "nets": [
+ 13,
+ 13
+ ],
+ "badnets": [
+ ],
+ "badelements": [
+ ],
+ "pins": [
+ [
+ "VGND",
+ "Y",
+ "VPWR",
+ "A2_N",
+ "B1",
+ "B2",
+ "A1_N",
+ "VPB",
+ "VNB"
+ ], [
+ "VGND",
+ "Y",
+ "VPWR",
+ "A2_N",
+ "B1",
+ "B2",
+ "A1_N",
+ "VPB",
+ "VNB"
+ ]
+ ]
+ },
+ {
+ "name": [
+ "sky130_fd_sc_hd__nor4b_4",
+ "sky130_fd_sc_hd__nor4b_4"
+ ],
+ "devices": [
+ [
+ ["sky130_fd_pr__nfet_01v8", 5],
+ ["sky130_fd_pr__pfet_01v8_hvt", 5 ]
+ ], [
+ ["sky130_fd_pr__nfet_01v8", 5 ],
+ ["sky130_fd_pr__pfet_01v8_hvt", 5 ]
+ ]
+ ],
+ "nets": [
+ 13,
+ 13
+ ],
+ "badnets": [
+ ],
+ "badelements": [
+ ],
+ "pins": [
+ [
+ "C",
+ "A",
+ "B",
+ "D_N",
+ "VPWR",
+ "Y",
+ "VPB",
+ "VGND",
+ "VNB"
+ ], [
+ "C",
+ "A",
+ "B",
+ "D_N",
+ "VPWR",
+ "Y",
+ "VPB",
+ "VGND",
+ "VNB"
+ ]
+ ]
+ },
+ {
+ "name": [
+ "sky130_fd_sc_hd__o32ai_1",
+ "sky130_fd_sc_hd__o32ai_1"
+ ],
+ "devices": [
+ [
+ ["sky130_fd_pr__nfet_01v8", 5],
+ ["sky130_fd_pr__pfet_01v8_hvt", 5 ]
+ ], [
+ ["sky130_fd_pr__nfet_01v8", 5 ],
+ ["sky130_fd_pr__pfet_01v8_hvt", 5 ]
+ ]
+ ],
+ "nets": [
+ 14,
+ 14
+ ],
+ "badnets": [
+ ],
+ "badelements": [
+ ],
+ "pins": [
+ [
+ "Y",
+ "VPB",
+ "VNB",
+ "B2",
+ "VPWR",
+ "A1",
+ "A2",
+ "A3",
+ "B1",
+ "VGND"
+ ], [
+ "Y",
+ "VPB",
+ "VNB",
+ "B2",
+ "VPWR",
+ "A1",
+ "A2",
+ "A3",
+ "B1",
+ "VGND"
+ ]
+ ]
+ },
+ {
+ "name": [
+ "sky130_fd_sc_hd__inv_8",
+ "sky130_fd_sc_hd__inv_8"
+ ],
+ "devices": [
+ [
+ ["sky130_fd_pr__pfet_01v8_hvt", 1],
+ ["sky130_fd_pr__nfet_01v8", 1 ]
+ ], [
+ ["sky130_fd_pr__pfet_01v8_hvt", 1 ],
+ ["sky130_fd_pr__nfet_01v8", 1 ]
+ ]
+ ],
+ "nets": [
+ 6,
+ 6
+ ],
+ "badnets": [
+ ],
+ "badelements": [
+ ],
+ "pins": [
+ [
+ "A",
+ "Y",
+ "VGND",
+ "VNB",
+ "VPWR",
+ "VPB"
+ ], [
+ "A",
+ "Y",
+ "VGND",
+ "VNB",
+ "VPWR",
+ "VPB"
+ ]
+ ]
+ },
+ {
+ "name": [
+ "sky130_fd_sc_hd__nand3b_4",
+ "sky130_fd_sc_hd__nand3b_4"
+ ],
+ "devices": [
+ [
+ ["sky130_fd_pr__nfet_01v8", 4],
+ ["sky130_fd_pr__pfet_01v8_hvt", 4 ]
+ ], [
+ ["sky130_fd_pr__nfet_01v8", 4 ],
+ ["sky130_fd_pr__pfet_01v8_hvt", 4 ]
+ ]
+ ],
+ "nets": [
+ 11,
+ 11
+ ],
+ "badnets": [
+ ],
+ "badelements": [
+ ],
+ "pins": [
+ [
+ "VNB",
+ "VPWR",
+ "Y",
+ "VPB",
+ "B",
+ "C",
+ "VGND",
+ "A_N"
+ ], [
+ "VNB",
+ "VPWR",
+ "Y",
+ "VPB",
+ "B",
+ "C",
+ "VGND",
+ "A_N"
+ ]
+ ]
+ },
+ {
+ "name": [
+ "sky130_fd_sc_hd__nor3b_4",
+ "sky130_fd_sc_hd__nor3b_4"
+ ],
+ "devices": [
+ [
+ ["sky130_fd_pr__nfet_01v8", 4],
+ ["sky130_fd_pr__pfet_01v8_hvt", 4 ]
+ ], [
+ ["sky130_fd_pr__nfet_01v8", 4 ],
+ ["sky130_fd_pr__pfet_01v8_hvt", 4 ]
+ ]
+ ],
+ "nets": [
+ 11,
+ 11
+ ],
+ "badnets": [
+ ],
+ "badelements": [
+ ],
+ "pins": [
+ [
+ "VPWR",
+ "A",
+ "B",
+ "C_N",
+ "VPB",
+ "VGND",
+ "Y",
+ "VNB"
+ ], [
+ "VPWR",
+ "A",
+ "B",
+ "C_N",
+ "VPB",
+ "VGND",
+ "Y",
+ "VNB"
+ ]
+ ]
+ },
+ {
+ "name": [
+ "RAM128",
+ "RAM128"
+ ],
+ "devices": [
+ [
+ ["sky130_fd_sc_hd__ebufn_2", 4224],
+ ["sky130_fd_sc_hd__dlclkp_1", 512],
+ ["sky130_fd_sc_hd__clkbuf_4", 153],
+ ["sky130_fd_sc_hd__dlxtp_1", 4096],
+ ["sky130_fd_sc_hd__and4bb_2", 48],
+ ["sky130_fd_sc_hd__inv_1", 1024],
+ ["sky130_fd_sc_hd__dfxtp_1", 128],
+ ["sky130_fd_sc_hd__and2_1", 512],
+ ["sky130_fd_sc_hd__diode_2", 386],
+ ["sky130_fd_sc_hd__decap_12", 1],
+ ["sky130_fd_sc_hd__decap_8", 1],
+ ["sky130_fd_sc_hd__clkbuf_2", 348],
+ ["sky130_fd_sc_hd__clkbuf_16", 160],
+ ["sky130_fd_sc_hd__decap_4", 1],
+ ["sky130_fd_sc_hd__decap_6", 1],
+ ["sky130_fd_sc_hd__decap_3", 1],
+ ["sky130_fd_sc_hd__and4b_2", 48],
+ ["sky130_fd_sc_hd__mux4_1", 32],
+ ["sky130_fd_sc_hd__conb_1", 16],
+ ["sky130_fd_sc_hd__and4_2", 16],
+ ["sky130_fd_sc_hd__nor4b_2", 16],
+ ["sky130_fd_sc_hd__nor3b_2", 5],
+ ["sky130_fd_sc_hd__and3b_2", 10],
+ ["sky130_fd_sc_hd__and3_2", 5 ]
+ ], [
+ ["sky130_fd_sc_hd__ebufn_2", 4224 ],
+ ["sky130_fd_sc_hd__dlclkp_1", 512 ],
+ ["sky130_fd_sc_hd__clkbuf_4", 153 ],
+ ["sky130_fd_sc_hd__dlxtp_1", 4096 ],
+ ["sky130_fd_sc_hd__and4bb_2", 48 ],
+ ["sky130_fd_sc_hd__inv_1", 1024 ],
+ ["sky130_fd_sc_hd__dfxtp_1", 128 ],
+ ["sky130_fd_sc_hd__and2_1", 512 ],
+ ["sky130_fd_sc_hd__diode_2", 386 ],
+ ["sky130_fd_sc_hd__decap_12", 1 ],
+ ["sky130_fd_sc_hd__decap_8", 1 ],
+ ["sky130_fd_sc_hd__clkbuf_2", 348 ],
+ ["sky130_fd_sc_hd__clkbuf_16", 160 ],
+ ["sky130_fd_sc_hd__decap_4", 1 ],
+ ["sky130_fd_sc_hd__decap_6", 1 ],
+ ["sky130_fd_sc_hd__decap_3", 1 ],
+ ["sky130_fd_sc_hd__and4b_2", 48 ],
+ ["sky130_fd_sc_hd__mux4_1", 32 ],
+ ["sky130_fd_sc_hd__conb_1", 16 ],
+ ["sky130_fd_sc_hd__and4_2", 16 ],
+ ["sky130_fd_sc_hd__nor4b_2", 16 ],
+ ["sky130_fd_sc_hd__nor3b_2", 5 ],
+ ["sky130_fd_sc_hd__and3b_2", 10 ],
+ ["sky130_fd_sc_hd__and3_2", 5 ]
+ ]
+ ],
+ "nets": [
+ 7320,
+ 7320
+ ],
+ "badnets": [
+ ],
+ "badelements": [
+ ],
+ "pins": [
+ [
+ "A0[5]",
+ "A0[6]",
+ "CLK",
+ "Di0[0]",
+ "Di0[10]",
+ "Di0[11]",
+ "Di0[12]",
+ "Di0[13]",
+ "Di0[14]",
+ "Di0[15]",
+ "Di0[16]",
+ "Di0[17]",
+ "Di0[18]",
+ "Di0[19]",
+ "Di0[1]",
+ "Di0[20]",
+ "Di0[21]",
+ "Di0[22]",
+ "Di0[23]",
+ "Di0[24]",
+ "Di0[25]",
+ "Di0[26]",
+ "Di0[27]",
+ "Di0[28]",
+ "Di0[29]",
+ "Di0[2]",
+ "Di0[30]",
+ "Di0[31]",
+ "Di0[3]",
+ "Di0[4]",
+ "Di0[5]",
+ "Di0[6]",
+ "Di0[7]",
+ "Di0[8]",
+ "Di0[9]",
+ "Do0[0]",
+ "Do0[1]",
+ "Do0[2]",
+ "Do0[3]",
+ "Do0[4]",
+ "Do0[5]",
+ "Do0[6]",
+ "Do0[7]",
+ "Do0[8]",
+ "Do0[9]",
+ "Do0[10]",
+ "Do0[11]",
+ "Do0[12]",
+ "Do0[13]",
+ "Do0[14]",
+ "Do0[15]",
+ "Do0[16]",
+ "Do0[17]",
+ "Do0[18]",
+ "Do0[19]",
+ "Do0[20]",
+ "Do0[21]",
+ "Do0[22]",
+ "Do0[23]",
+ "Do0[24]",
+ "Do0[25]",
+ "Do0[26]",
+ "Do0[27]",
+ "Do0[28]",
+ "Do0[29]",
+ "Do0[30]",
+ "Do0[31]",
+ "EN0",
+ "A0[3]",
+ "A0[4]",
+ "A0[0]",
+ "A0[1]",
+ "A0[2]",
+ "WE0[0]",
+ "WE0[1]",
+ "WE0[2]",
+ "WE0[3]",
+ "VGND",
+ "VPWR"
+ ], [
+ "A0[5]",
+ "A0[6]",
+ "CLK",
+ "Di0[0]",
+ "Di0[10]",
+ "Di0[11]",
+ "Di0[12]",
+ "Di0[13]",
+ "Di0[14]",
+ "Di0[15]",
+ "Di0[16]",
+ "Di0[17]",
+ "Di0[18]",
+ "Di0[19]",
+ "Di0[1]",
+ "Di0[20]",
+ "Di0[21]",
+ "Di0[22]",
+ "Di0[23]",
+ "Di0[24]",
+ "Di0[25]",
+ "Di0[26]",
+ "Di0[27]",
+ "Di0[28]",
+ "Di0[29]",
+ "Di0[2]",
+ "Di0[30]",
+ "Di0[31]",
+ "Di0[3]",
+ "Di0[4]",
+ "Di0[5]",
+ "Di0[6]",
+ "Di0[7]",
+ "Di0[8]",
+ "Di0[9]",
+ "Do0[0]",
+ "Do0[1]",
+ "Do0[2]",
+ "Do0[3]",
+ "Do0[4]",
+ "Do0[5]",
+ "Do0[6]",
+ "Do0[7]",
+ "Do0[8]",
+ "Do0[9]",
+ "Do0[10]",
+ "Do0[11]",
+ "Do0[12]",
+ "Do0[13]",
+ "Do0[14]",
+ "Do0[15]",
+ "Do0[16]",
+ "Do0[17]",
+ "Do0[18]",
+ "Do0[19]",
+ "Do0[20]",
+ "Do0[21]",
+ "Do0[22]",
+ "Do0[23]",
+ "Do0[24]",
+ "Do0[25]",
+ "Do0[26]",
+ "Do0[27]",
+ "Do0[28]",
+ "Do0[29]",
+ "Do0[30]",
+ "Do0[31]",
+ "EN0",
+ "A0[3]",
+ "A0[4]",
+ "A0[0]",
+ "A0[1]",
+ "A0[2]",
+ "WE0[0]",
+ "WE0[1]",
+ "WE0[2]",
+ "WE0[3]",
+ "VGND",
+ "VPWR"
+ ]
+ ]
+ },
+ {
+ "name": [
+ "sky130_fd_sc_hd__nand3_4",
+ "sky130_fd_sc_hd__nand3_4"
+ ],
+ "devices": [
+ [
+ ["sky130_fd_pr__nfet_01v8", 3],
+ ["sky130_fd_pr__pfet_01v8_hvt", 3 ]
+ ], [
+ ["sky130_fd_pr__nfet_01v8", 3 ],
+ ["sky130_fd_pr__pfet_01v8_hvt", 3 ]
+ ]
+ ],
+ "nets": [
+ 10,
+ 10
+ ],
+ "badnets": [
+ ],
+ "badelements": [
+ ],
+ "pins": [
+ [
+ "VGND",
+ "Y",
+ "VNB",
+ "VPWR",
+ "VPB",
+ "A",
+ "B",
+ "C"
+ ], [
+ "VGND",
+ "Y",
+ "VNB",
+ "VPWR",
+ "VPB",
+ "A",
+ "B",
+ "C"
+ ]
+ ]
+ },
+ {
+ "name": [
+ "sky130_fd_sc_hd__xnor2_4",
+ "sky130_fd_sc_hd__xnor2_4"
+ ],
+ "devices": [
+ [
+ ["sky130_fd_pr__nfet_01v8", 5],
+ ["sky130_fd_pr__pfet_01v8_hvt", 5 ]
+ ], [
+ ["sky130_fd_pr__nfet_01v8", 5 ],
+ ["sky130_fd_pr__pfet_01v8_hvt", 5 ]
+ ]
+ ],
+ "nets": [
+ 11,
+ 11
+ ],
+ "badnets": [
+ ],
+ "badelements": [
+ ],
+ "pins": [
+ [
+ "VNB",
+ "VPB",
+ "A",
+ "B",
+ "VPWR",
+ "VGND",
+ "Y"
+ ], [
+ "VNB",
+ "VPB",
+ "A",
+ "B",
+ "VPWR",
+ "VGND",
+ "Y"
+ ]
+ ]
+ },
+ {
+ "name": [
+ "sky130_fd_sc_hd__a2111oi_4",
+ "sky130_fd_sc_hd__a2111oi_4"
+ ],
+ "devices": [
+ [
+ ["sky130_fd_pr__nfet_01v8", 5],
+ ["sky130_fd_pr__pfet_01v8_hvt", 5 ]
+ ], [
+ ["sky130_fd_pr__nfet_01v8", 5 ],
+ ["sky130_fd_pr__pfet_01v8_hvt", 5 ]
+ ]
+ ],
+ "nets": [
+ 14,
+ 14
+ ],
+ "badnets": [
+ ],
+ "badelements": [
+ ],
+ "pins": [
+ [
+ "VGND",
+ "VPWR",
+ "A1",
+ "A2",
+ "C1",
+ "D1",
+ "B1",
+ "VPB",
+ "Y",
+ "VNB"
+ ], [
+ "VGND",
+ "VPWR",
+ "A1",
+ "A2",
+ "C1",
+ "D1",
+ "B1",
+ "VPB",
+ "Y",
+ "VNB"
+ ]
+ ]
+ },
+ {
+ "name": [
+ "sky130_fd_sc_hd__a311o_4",
+ "sky130_fd_sc_hd__a311o_4"
+ ],
+ "devices": [
+ [
+ ["sky130_fd_pr__pfet_01v8_hvt", 6],
+ ["sky130_fd_pr__nfet_01v8", 6 ]
+ ], [
+ ["sky130_fd_pr__pfet_01v8_hvt", 6 ],
+ ["sky130_fd_pr__nfet_01v8", 6 ]
+ ]
+ ],
+ "nets": [
+ 15,
+ 15
+ ],
+ "badnets": [
+ ],
+ "badelements": [
+ ],
+ "pins": [
+ [
+ "X",
+ "A1",
+ "B1",
+ "A2",
+ "A3",
+ "C1",
+ "VNB",
+ "VPB",
+ "VGND",
+ "VPWR"
+ ], [
+ "X",
+ "A1",
+ "B1",
+ "A2",
+ "A3",
+ "C1",
+ "VNB",
+ "VPB",
+ "VGND",
+ "VPWR"
+ ]
+ ]
+ },
+ {
+ "name": [
+ "sky130_fd_sc_hd__a221oi_2",
+ "sky130_fd_sc_hd__a221oi_2"
+ ],
+ "devices": [
+ [
+ ["sky130_fd_pr__nfet_01v8", 5],
+ ["sky130_fd_pr__pfet_01v8_hvt", 5 ]
+ ], [
+ ["sky130_fd_pr__nfet_01v8", 5 ],
+ ["sky130_fd_pr__pfet_01v8_hvt", 5 ]
+ ]
+ ],
+ "nets": [
+ 14,
+ 14
+ ],
+ "badnets": [
+ ],
+ "badelements": [
+ ],
+ "pins": [
+ [
+ "VGND",
+ "VPB",
+ "VNB",
+ "VPWR",
+ "A1",
+ "B1",
+ "A2",
+ "C1",
+ "B2",
+ "Y"
+ ], [
+ "VGND",
+ "VPB",
+ "VNB",
+ "VPWR",
+ "A1",
+ "B1",
+ "A2",
+ "C1",
+ "B2",
+ "Y"
+ ]
+ ]
+ },
+ {
+ "name": [
+ "sky130_fd_sc_hd__o22ai_2",
+ "sky130_fd_sc_hd__o22ai_2"
+ ],
+ "devices": [
+ [
+ ["sky130_fd_pr__pfet_01v8_hvt", 4],
+ ["sky130_fd_pr__nfet_01v8", 4 ]
+ ], [
+ ["sky130_fd_pr__pfet_01v8_hvt", 4 ],
+ ["sky130_fd_pr__nfet_01v8", 4 ]
+ ]
+ ],
+ "nets": [
+ 12,
+ 12
+ ],
+ "badnets": [
+ ],
+ "badelements": [
+ ],
+ "pins": [
+ [
+ "B2",
+ "VPWR",
+ "B1",
+ "A2",
+ "VGND",
+ "A1",
+ "Y",
+ "VNB",
+ "VPB"
+ ], [
+ "B2",
+ "VPWR",
+ "B1",
+ "A2",
+ "VGND",
+ "A1",
+ "Y",
+ "VNB",
+ "VPB"
+ ]
+ ]
+ },
+ {
+ "name": [
+ "sky130_fd_sc_hd__a31oi_2",
+ "sky130_fd_sc_hd__a31oi_2"
+ ],
+ "devices": [
+ [
+ ["sky130_fd_pr__nfet_01v8", 4],
+ ["sky130_fd_pr__pfet_01v8_hvt", 4 ]
+ ], [
+ ["sky130_fd_pr__nfet_01v8", 4 ],
+ ["sky130_fd_pr__pfet_01v8_hvt", 4 ]
+ ]
+ ],
+ "nets": [
+ 12,
+ 12
+ ],
+ "badnets": [
+ ],
+ "badelements": [
+ ],
+ "pins": [
+ [
+ "VNB",
+ "VPB",
+ "Y",
+ "VPWR",
+ "VGND",
+ "A1",
+ "B1",
+ "A3",
+ "A2"
+ ], [
+ "VNB",
+ "VPB",
+ "Y",
+ "VPWR",
+ "VGND",
+ "A1",
+ "B1",
+ "A3",
+ "A2"
+ ]
+ ]
+ },
+ {
+ "name": [
+ "sky130_fd_sc_hd__o2111a_2",
+ "sky130_fd_sc_hd__o2111a_2"
+ ],
+ "devices": [
+ [
+ ["sky130_fd_pr__pfet_01v8_hvt", 6],
+ ["sky130_fd_pr__nfet_01v8", 6 ]
+ ], [
+ ["sky130_fd_pr__pfet_01v8_hvt", 6 ],
+ ["sky130_fd_pr__nfet_01v8", 6 ]
+ ]
+ ],
+ "nets": [
+ 15,
+ 15
+ ],
+ "badnets": [
+ ],
+ "badelements": [
+ ],
+ "pins": [
+ [
+ "VGND",
+ "VNB",
+ "VPB",
+ "C1",
+ "X",
+ "B1",
+ "A2",
+ "A1",
+ "D1",
+ "VPWR"
+ ], [
+ "VGND",
+ "VNB",
+ "VPB",
+ "C1",
+ "X",
+ "B1",
+ "A2",
+ "A1",
+ "D1",
+ "VPWR"
+ ]
+ ]
+ },
+ {
+ "name": [
+ "sky130_fd_sc_hd__clkinv_8",
+ "sky130_fd_sc_hd__clkinv_8"
+ ],
+ "devices": [
+ [
+ ["sky130_fd_pr__nfet_01v8", 1],
+ ["sky130_fd_pr__pfet_01v8_hvt", 1 ]
+ ], [
+ ["sky130_fd_pr__nfet_01v8", 1 ],
+ ["sky130_fd_pr__pfet_01v8_hvt", 1 ]
+ ]
+ ],
+ "nets": [
+ 6,
+ 6
+ ],
+ "badnets": [
+ ],
+ "badelements": [
+ ],
+ "pins": [
+ [
+ "VPWR",
+ "VPB",
+ "VGND",
+ "VNB",
+ "Y",
+ "A"
+ ], [
+ "VPWR",
+ "VPB",
+ "VGND",
+ "VNB",
+ "Y",
+ "A"
+ ]
+ ]
+ },
+ {
+ "name": [
+ "sky130_fd_sc_hd__xnor2_2",
+ "sky130_fd_sc_hd__xnor2_2"
+ ],
+ "devices": [
+ [
+ ["sky130_fd_pr__pfet_01v8_hvt", 5],
+ ["sky130_fd_pr__nfet_01v8", 5 ]
+ ], [
+ ["sky130_fd_pr__pfet_01v8_hvt", 5 ],
+ ["sky130_fd_pr__nfet_01v8", 5 ]
+ ]
+ ],
+ "nets": [
+ 11,
+ 11
+ ],
+ "badnets": [
+ ],
+ "badelements": [
+ ],
+ "pins": [
+ [
+ "VGND",
+ "Y",
+ "VPWR",
+ "B",
+ "A",
+ "VPB",
+ "VNB"
+ ], [
+ "VGND",
+ "Y",
+ "VPWR",
+ "B",
+ "A",
+ "VPB",
+ "VNB"
+ ]
+ ]
+ },
+ {
+ "name": [
+ "sky130_fd_sc_hd__o41ai_2",
+ "sky130_fd_sc_hd__o41ai_2"
+ ],
+ "devices": [
+ [
+ ["sky130_fd_pr__nfet_01v8", 5],
+ ["sky130_fd_pr__pfet_01v8_hvt", 5 ]
+ ], [
+ ["sky130_fd_pr__nfet_01v8", 5 ],
+ ["sky130_fd_pr__pfet_01v8_hvt", 5 ]
+ ]
+ ],
+ "nets": [
+ 14,
+ 14
+ ],
+ "badnets": [
+ ],
+ "badelements": [
+ ],
+ "pins": [
+ [
+ "Y",
+ "VGND",
+ "A1",
+ "A3",
+ "A2",
+ "A4",
+ "B1",
+ "VPWR",
+ "VPB",
+ "VNB"
+ ], [
+ "Y",
+ "VGND",
+ "A1",
+ "A3",
+ "A2",
+ "A4",
+ "B1",
+ "VPWR",
+ "VPB",
+ "VNB"
+ ]
+ ]
+ },
+ {
+ "name": [
+ "sky130_fd_sc_hd__o31ai_4",
+ "sky130_fd_sc_hd__o31ai_4"
+ ],
+ "devices": [
+ [
+ ["sky130_fd_pr__pfet_01v8_hvt", 4],
+ ["sky130_fd_pr__nfet_01v8", 4 ]
+ ], [
+ ["sky130_fd_pr__pfet_01v8_hvt", 4 ],
+ ["sky130_fd_pr__nfet_01v8", 4 ]
+ ]
+ ],
+ "nets": [
+ 12,
+ 12
+ ],
+ "badnets": [
+ ],
+ "badelements": [
+ ],
+ "pins": [
+ [
+ "VPB",
+ "VNB",
+ "A2",
+ "A1",
+ "VPWR",
+ "B1",
+ "A3",
+ "VGND",
+ "Y"
+ ], [
+ "VPB",
+ "VNB",
+ "A2",
+ "A1",
+ "VPWR",
+ "B1",
+ "A3",
+ "VGND",
+ "Y"
+ ]
+ ]
+ },
+ {
+ "name": [
+ "sky130_fd_sc_hd__o31ai_2",
+ "sky130_fd_sc_hd__o31ai_2"
+ ],
+ "devices": [
+ [
+ ["sky130_fd_pr__pfet_01v8_hvt", 4],
+ ["sky130_fd_pr__nfet_01v8", 4 ]
+ ], [
+ ["sky130_fd_pr__pfet_01v8_hvt", 4 ],
+ ["sky130_fd_pr__nfet_01v8", 4 ]
+ ]
+ ],
+ "nets": [
+ 12,
+ 12
+ ],
+ "badnets": [
+ ],
+ "badelements": [
+ ],
+ "pins": [
+ [
+ "VPB",
+ "VNB",
+ "Y",
+ "VGND",
+ "VPWR",
+ "A1",
+ "A2",
+ "B1",
+ "A3"
+ ], [
+ "VPB",
+ "VNB",
+ "Y",
+ "VGND",
+ "VPWR",
+ "A1",
+ "A2",
+ "B1",
+ "A3"
+ ]
+ ]
+ },
+ {
+ "name": [
+ "sky130_fd_sc_hd__o2111a_4",
+ "sky130_fd_sc_hd__o2111a_4"
+ ],
+ "devices": [
+ [
+ ["sky130_fd_pr__nfet_01v8", 8],
+ ["sky130_fd_pr__pfet_01v8_hvt", 8 ]
+ ], [
+ ["sky130_fd_pr__nfet_01v8", 8 ],
+ ["sky130_fd_pr__pfet_01v8_hvt", 8 ]
+ ]
+ ],
+ "nets": [
+ 17,
+ 17
+ ],
+ "badnets": [
+ ],
+ "badelements": [
+ ],
+ "pins": [
+ [
+ "VPWR",
+ "X",
+ "D1",
+ "VNB",
+ "VPB",
+ "VGND",
+ "A2",
+ "A1",
+ "B1",
+ "C1"
+ ], [
+ "VPWR",
+ "X",
+ "D1",
+ "VNB",
+ "VPB",
+ "VGND",
+ "A2",
+ "A1",
+ "B1",
+ "C1"
+ ]
+ ]
+ },
+ {
+ "name": [
+ "sky130_fd_sc_hd__o2bb2a_4",
+ "sky130_fd_sc_hd__o2bb2a_4"
+ ],
+ "devices": [
+ [
+ ["sky130_fd_pr__nfet_01v8", 6],
+ ["sky130_fd_pr__pfet_01v8_hvt", 6 ]
+ ], [
+ ["sky130_fd_pr__nfet_01v8", 6 ],
+ ["sky130_fd_pr__pfet_01v8_hvt", 6 ]
+ ]
+ ],
+ "nets": [
+ 14,
+ 14
+ ],
+ "badnets": [
+ ],
+ "badelements": [
+ ],
+ "pins": [
+ [
+ "VGND",
+ "A2_N",
+ "X",
+ "A1_N",
+ "B2",
+ "B1",
+ "VNB",
+ "VPB",
+ "VPWR"
+ ], [
+ "VGND",
+ "A2_N",
+ "X",
+ "A1_N",
+ "B2",
+ "B1",
+ "VNB",
+ "VPB",
+ "VPWR"
+ ]
+ ]
+ },
+ {
+ "name": [
+ "sky130_fd_sc_hd__a41o_4",
+ "sky130_fd_sc_hd__a41o_4"
+ ],
+ "devices": [
+ [
+ ["sky130_fd_pr__nfet_01v8", 6],
+ ["sky130_fd_pr__pfet_01v8_hvt", 6 ]
+ ], [
+ ["sky130_fd_pr__nfet_01v8", 6 ],
+ ["sky130_fd_pr__pfet_01v8_hvt", 6 ]
+ ]
+ ],
+ "nets": [
+ 15,
+ 15
+ ],
+ "badnets": [
+ ],
+ "badelements": [
+ ],
+ "pins": [
+ [
+ "VGND",
+ "VPB",
+ "VNB",
+ "VPWR",
+ "A3",
+ "A2",
+ "A1",
+ "B1",
+ "X",
+ "A4"
+ ], [
+ "VGND",
+ "VPB",
+ "VNB",
+ "VPWR",
+ "A3",
+ "A2",
+ "A1",
+ "B1",
+ "X",
+ "A4"
+ ]
+ ]
+ },
+ {
+ "name": [
+ "sky130_fd_sc_hd__a32oi_2",
+ "sky130_fd_sc_hd__a32oi_2"
+ ],
+ "devices": [
+ [
+ ["sky130_fd_pr__nfet_01v8", 5],
+ ["sky130_fd_pr__pfet_01v8_hvt", 5 ]
+ ], [
+ ["sky130_fd_pr__nfet_01v8", 5 ],
+ ["sky130_fd_pr__pfet_01v8_hvt", 5 ]
+ ]
+ ],
+ "nets": [
+ 14,
+ 14
+ ],
+ "badnets": [
+ ],
+ "badelements": [
+ ],
+ "pins": [
+ [
+ "VPWR",
+ "VNB",
+ "VPB",
+ "B1",
+ "A1",
+ "A3",
+ "A2",
+ "VGND",
+ "B2",
+ "Y"
+ ], [
+ "VPWR",
+ "VNB",
+ "VPB",
+ "B1",
+ "A1",
+ "A3",
+ "A2",
+ "VGND",
+ "B2",
+ "Y"
+ ]
+ ]
+ },
+ {
+ "name": [
+ "sky130_fd_sc_hd__a32oi_1",
+ "sky130_fd_sc_hd__a32oi_1"
+ ],
+ "devices": [
+ [
+ ["sky130_fd_pr__pfet_01v8_hvt", 5],
+ ["sky130_fd_pr__nfet_01v8", 5 ]
+ ], [
+ ["sky130_fd_pr__pfet_01v8_hvt", 5 ],
+ ["sky130_fd_pr__nfet_01v8", 5 ]
+ ]
+ ],
+ "nets": [
+ 14,
+ 14
+ ],
+ "badnets": [
+ ],
+ "badelements": [
+ ],
+ "pins": [
+ [
+ "Y",
+ "VPB",
+ "VNB",
+ "A1",
+ "A2",
+ "A3",
+ "B1",
+ "VGND",
+ "B2",
+ "VPWR"
+ ], [
+ "Y",
+ "VPB",
+ "VNB",
+ "A1",
+ "A2",
+ "A3",
+ "B1",
+ "VGND",
+ "B2",
+ "VPWR"
+ ]
+ ]
+ },
+ {
+ "name": [
+ "sky130_fd_sc_hd__a21boi_2",
+ "sky130_fd_sc_hd__a21boi_2"
+ ],
+ "devices": [
+ [
+ ["sky130_fd_pr__nfet_01v8", 6],
+ ["sky130_fd_pr__pfet_01v8_hvt", 4 ]
+ ], [
+ ["sky130_fd_pr__nfet_01v8", 6 ],
+ ["sky130_fd_pr__pfet_01v8_hvt", 4 ]
+ ]
+ ],
+ "nets": [
+ 12,
+ 12
+ ],
+ "badnets": [
+ ],
+ "badelements": [
+ ],
+ "pins": [
+ [
+ "B1_N",
+ "VPWR",
+ "A1",
+ "A2",
+ "VNB",
+ "Y",
+ "VGND",
+ "VPB"
+ ], [
+ "B1_N",
+ "VPWR",
+ "A1",
+ "A2",
+ "VNB",
+ "Y",
+ "VGND",
+ "VPB"
+ ]
+ ]
+ },
+ {
+ "name": [
+ "sky130_fd_sc_hd__nand3b_2",
+ "sky130_fd_sc_hd__nand3b_2"
+ ],
+ "devices": [
+ [
+ ["sky130_fd_pr__nfet_01v8", 4],
+ ["sky130_fd_pr__pfet_01v8_hvt", 4 ]
+ ], [
+ ["sky130_fd_pr__nfet_01v8", 4 ],
+ ["sky130_fd_pr__pfet_01v8_hvt", 4 ]
+ ]
+ ],
+ "nets": [
+ 11,
+ 11
+ ],
+ "badnets": [
+ ],
+ "badelements": [
+ ],
+ "pins": [
+ [
+ "VPWR",
+ "Y",
+ "VPB",
+ "VNB",
+ "C",
+ "B",
+ "VGND",
+ "A_N"
+ ], [
+ "VPWR",
+ "Y",
+ "VPB",
+ "VNB",
+ "C",
+ "B",
+ "VGND",
+ "A_N"
+ ]
+ ]
+ },
+ {
+ "name": [
+ "RAM256",
+ "RAM256"
+ ],
+ "devices": [
+ [
+ ["sky130_fd_sc_hd__and2_1", 1024],
+ ["sky130_fd_sc_hd__dlxtp_1", 8192],
+ ["sky130_fd_sc_hd__ebufn_2", 8448],
+ ["sky130_fd_sc_hd__dlclkp_1", 1024],
+ ["sky130_fd_sc_hd__diode_2", 836],
+ ["sky130_fd_sc_hd__and4_2", 32],
+ ["sky130_fd_sc_hd__decap_12", 1],
+ ["sky130_fd_sc_hd__inv_1", 2048],
+ ["sky130_fd_sc_hd__dfxtp_1", 256],
+ ["sky130_fd_sc_hd__mux4_1", 64],
+ ["sky130_fd_sc_hd__clkbuf_4", 306],
+ ["sky130_fd_sc_hd__and3b_2", 20],
+ ["sky130_fd_sc_hd__clkbuf_16", 320],
+ ["sky130_fd_sc_hd__decap_3", 1],
+ ["sky130_fd_sc_hd__clkbuf_2", 700],
+ ["sky130_fd_sc_hd__and4bb_2", 96],
+ ["sky130_fd_sc_hd__decap_8", 1],
+ ["sky130_fd_sc_hd__nor4b_2", 32],
+ ["sky130_fd_sc_hd__and4b_2", 96],
+ ["sky130_fd_sc_hd__decap_4", 1],
+ ["sky130_fd_sc_hd__and3_2", 10],
+ ["sky130_fd_sc_hd__decap_6", 1],
+ ["sky130_fd_sc_hd__mux2_1", 32],
+ ["sky130_fd_sc_hd__conb_1", 32],
+ ["sky130_fd_sc_hd__nor3b_2", 10],
+ ["sky130_fd_sc_hd__and2b_2", 1],
+ ["sky130_fd_sc_hd__and2_2", 1 ]
+ ], [
+ ["sky130_fd_sc_hd__and2_1", 1024 ],
+ ["sky130_fd_sc_hd__dlxtp_1", 8192 ],
+ ["sky130_fd_sc_hd__ebufn_2", 8448 ],
+ ["sky130_fd_sc_hd__dlclkp_1", 1024 ],
+ ["sky130_fd_sc_hd__diode_2", 836 ],
+ ["sky130_fd_sc_hd__and4_2", 32 ],
+ ["sky130_fd_sc_hd__decap_12", 1 ],
+ ["sky130_fd_sc_hd__inv_1", 2048 ],
+ ["sky130_fd_sc_hd__dfxtp_1", 256 ],
+ ["sky130_fd_sc_hd__mux4_1", 64 ],
+ ["sky130_fd_sc_hd__clkbuf_4", 306 ],
+ ["sky130_fd_sc_hd__and3b_2", 20 ],
+ ["sky130_fd_sc_hd__clkbuf_16", 320 ],
+ ["sky130_fd_sc_hd__decap_3", 1 ],
+ ["sky130_fd_sc_hd__clkbuf_2", 700 ],
+ ["sky130_fd_sc_hd__and4bb_2", 96 ],
+ ["sky130_fd_sc_hd__decap_8", 1 ],
+ ["sky130_fd_sc_hd__nor4b_2", 32 ],
+ ["sky130_fd_sc_hd__and4b_2", 96 ],
+ ["sky130_fd_sc_hd__decap_4", 1 ],
+ ["sky130_fd_sc_hd__and3_2", 10 ],
+ ["sky130_fd_sc_hd__decap_6", 1 ],
+ ["sky130_fd_sc_hd__mux2_1", 32 ],
+ ["sky130_fd_sc_hd__conb_1", 32 ],
+ ["sky130_fd_sc_hd__nor3b_2", 10 ],
+ ["sky130_fd_sc_hd__and2b_2", 1 ],
+ ["sky130_fd_sc_hd__and2_2", 1 ]
+ ]
+ ],
+ "nets": [
+ 14632,
+ 14632
+ ],
+ "badnets": [
+ ],
+ "badelements": [
+ ],
+ "pins": [
+ [
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+ "Do0[1]",
+ "Do0[2]",
+ "Do0[3]",
+ "Do0[4]",
+ "Do0[5]",
+ "Do0[6]",
+ "Do0[7]",
+ "Do0[8]",
+ "Do0[9]",
+ "Do0[10]",
+ "Do0[11]",
+ "Do0[12]",
+ "Do0[13]",
+ "Do0[14]",
+ "Do0[15]",
+ "Do0[16]",
+ "Do0[17]",
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+ "Do0[19]",
+ "Do0[20]",
+ "Do0[21]",
+ "Do0[22]",
+ "Do0[23]",
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+ "Do0[25]",
+ "Do0[26]",
+ "Do0[27]",
+ "Do0[28]",
+ "Do0[29]",
+ "Do0[30]",
+ "Do0[31]",
+ "A0[7]",
+ "A0[6]",
+ "A0[5]",
+ "CLK",
+ "Di0[0]",
+ "Di0[10]",
+ "Di0[11]",
+ "Di0[12]",
+ "Di0[13]",
+ "Di0[14]",
+ "Di0[15]",
+ "Di0[16]",
+ "Di0[17]",
+ "Di0[18]",
+ "Di0[19]",
+ "Di0[1]",
+ "Di0[20]",
+ "Di0[21]",
+ "Di0[22]",
+ "Di0[23]",
+ "Di0[24]",
+ "Di0[25]",
+ "Di0[26]",
+ "Di0[27]",
+ "Di0[28]",
+ "Di0[29]",
+ "Di0[2]",
+ "Di0[30]",
+ "Di0[31]",
+ "Di0[3]",
+ "Di0[4]",
+ "Di0[5]",
+ "Di0[6]",
+ "Di0[7]",
+ "Di0[8]",
+ "Di0[9]",
+ "A0[3]",
+ "A0[4]",
+ "A0[0]",
+ "A0[1]",
+ "A0[2]",
+ "WE0[0]",
+ "WE0[1]",
+ "WE0[2]",
+ "WE0[3]",
+ "EN0",
+ "VGND",
+ "VPWR"
+ ], [
+ "Do0[0]",
+ "Do0[1]",
+ "Do0[2]",
+ "Do0[3]",
+ "Do0[4]",
+ "Do0[5]",
+ "Do0[6]",
+ "Do0[7]",
+ "Do0[8]",
+ "Do0[9]",
+ "Do0[10]",
+ "Do0[11]",
+ "Do0[12]",
+ "Do0[13]",
+ "Do0[14]",
+ "Do0[15]",
+ "Do0[16]",
+ "Do0[17]",
+ "Do0[18]",
+ "Do0[19]",
+ "Do0[20]",
+ "Do0[21]",
+ "Do0[22]",
+ "Do0[23]",
+ "Do0[24]",
+ "Do0[25]",
+ "Do0[26]",
+ "Do0[27]",
+ "Do0[28]",
+ "Do0[29]",
+ "Do0[30]",
+ "Do0[31]",
+ "A0[7]",
+ "A0[6]",
+ "A0[5]",
+ "CLK",
+ "Di0[0]",
+ "Di0[10]",
+ "Di0[11]",
+ "Di0[12]",
+ "Di0[13]",
+ "Di0[14]",
+ "Di0[15]",
+ "Di0[16]",
+ "Di0[17]",
+ "Di0[18]",
+ "Di0[19]",
+ "Di0[1]",
+ "Di0[20]",
+ "Di0[21]",
+ "Di0[22]",
+ "Di0[23]",
+ "Di0[24]",
+ "Di0[25]",
+ "Di0[26]",
+ "Di0[27]",
+ "Di0[28]",
+ "Di0[29]",
+ "Di0[2]",
+ "Di0[30]",
+ "Di0[31]",
+ "Di0[3]",
+ "Di0[4]",
+ "Di0[5]",
+ "Di0[6]",
+ "Di0[7]",
+ "Di0[8]",
+ "Di0[9]",
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+ "A0[4]",
+ "A0[0]",
+ "A0[1]",
+ "A0[2]",
+ "WE0[0]",
+ "WE0[1]",
+ "WE0[2]",
+ "WE0[3]",
+ "EN0",
+ "VGND",
+ "VPWR"
+ ]
+ ]
+ },
+ {
+ "name": [
+ "sky130_fd_sc_hd__o21bai_2",
+ "sky130_fd_sc_hd__o21bai_2"
+ ],
+ "devices": [
+ [
+ ["sky130_fd_pr__pfet_01v8_hvt", 4],
+ ["sky130_fd_pr__nfet_01v8", 4 ]
+ ], [
+ ["sky130_fd_pr__pfet_01v8_hvt", 4 ],
+ ["sky130_fd_pr__nfet_01v8", 4 ]
+ ]
+ ],
+ "nets": [
+ 11,
+ 11
+ ],
+ "badnets": [
+ ],
+ "badelements": [
+ ],
+ "pins": [
+ [
+ "VPB",
+ "VNB",
+ "Y",
+ "VPWR",
+ "VGND",
+ "B1_N",
+ "A1",
+ "A2"
+ ], [
+ "VPB",
+ "VNB",
+ "Y",
+ "VPWR",
+ "VGND",
+ "B1_N",
+ "A1",
+ "A2"
+ ]
+ ]
+ },
+ {
+ "name": [
+ "sky130_fd_sc_hd__o2bb2ai_4",
+ "sky130_fd_sc_hd__o2bb2ai_4"
+ ],
+ "devices": [
+ [
+ ["sky130_fd_pr__pfet_01v8_hvt", 5],
+ ["sky130_fd_pr__nfet_01v8", 5 ]
+ ], [
+ ["sky130_fd_pr__pfet_01v8_hvt", 5 ],
+ ["sky130_fd_pr__nfet_01v8", 5 ]
+ ]
+ ],
+ "nets": [
+ 13,
+ 13
+ ],
+ "badnets": [
+ ],
+ "badelements": [
+ ],
+ "pins": [
+ [
+ "VGND",
+ "Y",
+ "VPB",
+ "VNB",
+ "VPWR",
+ "A1_N",
+ "B2",
+ "B1",
+ "A2_N"
+ ], [
+ "VGND",
+ "Y",
+ "VPB",
+ "VNB",
+ "VPWR",
+ "A1_N",
+ "B2",
+ "B1",
+ "A2_N"
+ ]
+ ]
+ },
+ {
+ "name": [
+ "sky130_fd_sc_hd__o311ai_2",
+ "sky130_fd_sc_hd__o311ai_2"
+ ],
+ "devices": [
+ [
+ ["sky130_fd_pr__pfet_01v8_hvt", 5],
+ ["sky130_fd_pr__nfet_01v8", 5 ]
+ ], [
+ ["sky130_fd_pr__pfet_01v8_hvt", 5 ],
+ ["sky130_fd_pr__nfet_01v8", 5 ]
+ ]
+ ],
+ "nets": [
+ 14,
+ 14
+ ],
+ "badnets": [
+ ],
+ "badelements": [
+ ],
+ "pins": [
+ [
+ "Y",
+ "VNB",
+ "VPB",
+ "A3",
+ "A1",
+ "B1",
+ "C1",
+ "A2",
+ "VGND",
+ "VPWR"
+ ], [
+ "Y",
+ "VNB",
+ "VPB",
+ "A3",
+ "A1",
+ "B1",
+ "C1",
+ "A2",
+ "VGND",
+ "VPWR"
+ ]
+ ]
+ },
+ {
+ "name": [
+ "sky130_fd_sc_hd__a2111oi_2",
+ "sky130_fd_sc_hd__a2111oi_2"
+ ],
+ "devices": [
+ [
+ ["sky130_fd_pr__pfet_01v8_hvt", 7],
+ ["sky130_fd_pr__nfet_01v8", 7 ]
+ ], [
+ ["sky130_fd_pr__pfet_01v8_hvt", 7 ],
+ ["sky130_fd_pr__nfet_01v8", 7 ]
+ ]
+ ],
+ "nets": [
+ 16,
+ 16
+ ],
+ "badnets": [
+ ],
+ "badelements": [
+ ],
+ "pins": [
+ [
+ "VGND",
+ "Y",
+ "VNB",
+ "VPB",
+ "VPWR",
+ "B1",
+ "D1",
+ "A2",
+ "A1",
+ "C1"
+ ], [
+ "VGND",
+ "Y",
+ "VNB",
+ "VPB",
+ "VPWR",
+ "B1",
+ "D1",
+ "A2",
+ "A1",
+ "C1"
+ ]
+ ]
+ },
+ {
+ "name": [
+ "sky130_fd_sc_hd__nand4b_1",
+ "sky130_fd_sc_hd__nand4b_1"
+ ],
+ "devices": [
+ [
+ ["sky130_fd_pr__pfet_01v8_hvt", 5],
+ ["sky130_fd_pr__nfet_01v8", 5 ]
+ ], [
+ ["sky130_fd_pr__pfet_01v8_hvt", 5 ],
+ ["sky130_fd_pr__nfet_01v8", 5 ]
+ ]
+ ],
+ "nets": [
+ 13,
+ 13
+ ],
+ "badnets": [
+ ],
+ "badelements": [
+ ],
+ "pins": [
+ [
+ "A_N",
+ "C",
+ "D",
+ "B",
+ "VGND",
+ "Y",
+ "VPWR",
+ "VPB",
+ "VNB"
+ ], [
+ "A_N",
+ "C",
+ "D",
+ "B",
+ "VGND",
+ "Y",
+ "VPWR",
+ "VPB",
+ "VNB"
+ ]
+ ]
+ },
+ {
+ "name": [
+ "sky130_fd_sc_hd__nor3b_1",
+ "sky130_fd_sc_hd__nor3b_1"
+ ],
+ "devices": [
+ [
+ ["sky130_fd_pr__nfet_01v8", 4],
+ ["sky130_fd_pr__pfet_01v8_hvt", 4 ]
+ ], [
+ ["sky130_fd_pr__nfet_01v8", 4 ],
+ ["sky130_fd_pr__pfet_01v8_hvt", 4 ]
+ ]
+ ],
+ "nets": [
+ 11,
+ 11
+ ],
+ "badnets": [
+ ],
+ "badelements": [
+ ],
+ "pins": [
+ [
+ "VPWR",
+ "C_N",
+ "A",
+ "B",
+ "Y",
+ "VGND",
+ "VNB",
+ "VPB"
+ ], [
+ "VPWR",
+ "C_N",
+ "A",
+ "B",
+ "Y",
+ "VGND",
+ "VNB",
+ "VPB"
+ ]
+ ]
+ },
+ {
+ "name": [
+ "sky130_fd_sc_hd__a41oi_1",
+ "sky130_fd_sc_hd__a41oi_1"
+ ],
+ "devices": [
+ [
+ ["sky130_fd_pr__nfet_01v8", 5],
+ ["sky130_fd_pr__pfet_01v8_hvt", 5 ]
+ ], [
+ ["sky130_fd_pr__nfet_01v8", 5 ],
+ ["sky130_fd_pr__pfet_01v8_hvt", 5 ]
+ ]
+ ],
+ "nets": [
+ 14,
+ 14
+ ],
+ "badnets": [
+ ],
+ "badelements": [
+ ],
+ "pins": [
+ [
+ "Y",
+ "VPWR",
+ "VNB",
+ "VPB",
+ "A3",
+ "A2",
+ "A4",
+ "A1",
+ "VGND",
+ "B1"
+ ], [
+ "Y",
+ "VPWR",
+ "VNB",
+ "VPB",
+ "A3",
+ "A2",
+ "A4",
+ "A1",
+ "VGND",
+ "B1"
+ ]
+ ]
+ },
+ {
+ "name": [
+ "sky130_fd_sc_hd__a311oi_2",
+ "sky130_fd_sc_hd__a311oi_2"
+ ],
+ "devices": [
+ [
+ ["sky130_fd_pr__nfet_01v8", 5],
+ ["sky130_fd_pr__pfet_01v8_hvt", 5 ]
+ ], [
+ ["sky130_fd_pr__nfet_01v8", 5 ],
+ ["sky130_fd_pr__pfet_01v8_hvt", 5 ]
+ ]
+ ],
+ "nets": [
+ 14,
+ 14
+ ],
+ "badnets": [
+ ],
+ "badelements": [
+ ],
+ "pins": [
+ [
+ "VPWR",
+ "VGND",
+ "VPB",
+ "VNB",
+ "A2",
+ "A1",
+ "C1",
+ "B1",
+ "A3",
+ "Y"
+ ], [
+ "VPWR",
+ "VGND",
+ "VPB",
+ "VNB",
+ "A2",
+ "A1",
+ "C1",
+ "B1",
+ "A3",
+ "Y"
+ ]
+ ]
+ },
+ {
+ "name": [
+ "sky130_fd_sc_hd__o32ai_4",
+ "sky130_fd_sc_hd__o32ai_4"
+ ],
+ "devices": [
+ [
+ ["sky130_fd_pr__pfet_01v8_hvt", 5],
+ ["sky130_fd_pr__nfet_01v8", 5 ]
+ ], [
+ ["sky130_fd_pr__pfet_01v8_hvt", 5 ],
+ ["sky130_fd_pr__nfet_01v8", 5 ]
+ ]
+ ],
+ "nets": [
+ 14,
+ 14
+ ],
+ "badnets": [
+ ],
+ "badelements": [
+ ],
+ "pins": [
+ [
+ "Y",
+ "VGND",
+ "VNB",
+ "VPB",
+ "A3",
+ "VPWR",
+ "B1",
+ "A2",
+ "A1",
+ "B2"
+ ], [
+ "Y",
+ "VGND",
+ "VNB",
+ "VPB",
+ "A3",
+ "VPWR",
+ "B1",
+ "A2",
+ "A1",
+ "B2"
+ ]
+ ]
+ },
+ {
+ "name": [
+ "sky130_fd_sc_hd__a41oi_4",
+ "sky130_fd_sc_hd__a41oi_4"
+ ],
+ "devices": [
+ [
+ ["sky130_fd_pr__pfet_01v8_hvt", 5],
+ ["sky130_fd_pr__nfet_01v8", 5 ]
+ ], [
+ ["sky130_fd_pr__pfet_01v8_hvt", 5 ],
+ ["sky130_fd_pr__nfet_01v8", 5 ]
+ ]
+ ],
+ "nets": [
+ 14,
+ 14
+ ],
+ "badnets": [
+ ],
+ "badelements": [
+ ],
+ "pins": [
+ [
+ "Y",
+ "VPB",
+ "VNB",
+ "A1",
+ "VGND",
+ "B1",
+ "A3",
+ "A4",
+ "A2",
+ "VPWR"
+ ], [
+ "Y",
+ "VPB",
+ "VNB",
+ "A1",
+ "VGND",
+ "B1",
+ "A3",
+ "A4",
+ "A2",
+ "VPWR"
+ ]
+ ]
+ },
+ {
+ "name": [
+ "mgmt_core_wrapper",
+ "mgmt_core_wrapper"
+ ],
+ "devices": [
+ [
+ ["sky130_fd_sc_hd__decap_6", 1],
+ ["sky130_ef_sc_hd__decap_12", 1],
+ ["sky130_fd_sc_hd__diode_2", 5040],
+ ["sky130_fd_sc_hd__clkbuf_16", 578],
+ ["sky130_fd_sc_hd__decap_4", 1],
+ ["sky130_fd_sc_hd__decap_3", 1],
+ ["sky130_fd_sc_hd__decap_8", 1],
+ ["sky130_fd_sc_hd__a211o_1", 540],
+ ["sky130_fd_sc_hd__mux2_1", 3182],
+ ["sky130_fd_sc_hd__a211oi_2", 5],
+ ["sky130_fd_sc_hd__o211a_1", 1019],
+ ["sky130_fd_sc_hd__and4b_1", 42],
+ ["sky130_fd_sc_hd__o41a_1", 27],
+ ["sky130_fd_sc_hd__a221o_1", 265],
+ ["sky130_fd_sc_hd__a32o_1", 171],
+ ["sky130_fd_sc_hd__nor2_1", 215],
+ ["sky130_fd_sc_hd__dfxtp_1", 3755],
+ ["sky130_fd_sc_hd__o31a_1", 254],
+ ["sky130_fd_sc_hd__dlygate4sd3_1", 3154],
+ ["sky130_fd_sc_hd__dfxtp_4", 583],
+ ["sky130_fd_sc_hd__buf_6", 298],
+ ["sky130_fd_sc_hd__buf_12", 1138],
+ ["sky130_fd_sc_hd__or4b_4", 30],
+ ["sky130_fd_sc_hd__buf_8", 237],
+ ["sky130_fd_sc_hd__nand2_1", 341],
+ ["sky130_fd_sc_hd__buf_4", 110],
+ ["sky130_fd_sc_hd__a31o_1", 460],
+ ["sky130_fd_sc_hd__a21bo_1", 48],
+ ["sky130_fd_sc_hd__o21a_1", 314],
+ ["sky130_fd_sc_hd__a31o_4", 25],
+ ["sky130_fd_sc_hd__and3_4", 56],
+ ["sky130_fd_sc_hd__a211oi_4", 5],
+ ["sky130_fd_sc_hd__o221a_1", 293],
+ ["sky130_fd_sc_hd__o311a_1", 302],
+ ["sky130_fd_sc_hd__a21o_1", 746],
+ ["sky130_fd_sc_hd__a41o_1", 181],
+ ["sky130_fd_sc_hd__a31oi_1", 46],
+ ["sky130_fd_sc_hd__a22o_1", 428],
+ ["sky130_fd_sc_hd__or3b_1", 155],
+ ["sky130_fd_sc_hd__and3_1", 315],
+ ["sky130_fd_sc_hd__o22a_1", 60],
+ ["sky130_fd_sc_hd__a22o_2", 52],
+ ["sky130_fd_sc_hd__a22o_4", 60],
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+ ["sky130_fd_sc_hd__dfxtp_2", 389],
+ ["sky130_fd_sc_hd__and2_1", 107],
+ ["sky130_fd_sc_hd__o21ai_1", 384],
+ ["sky130_fd_sc_hd__and4_1", 150],
+ ["sky130_fd_sc_hd__a311oi_4", 18],
+ ["sky130_fd_sc_hd__a221o_4", 60],
+ ["sky130_fd_sc_hd__inv_2", 339],
+ ["sky130_fd_sc_hd__a311o_1", 165],
+ ["sky130_fd_sc_hd__mux4_2", 14],
+ ["sky130_fd_sc_hd__and3b_4", 6],
+ ["sky130_fd_sc_hd__a2111o_1", 15],
+ ["sky130_fd_sc_hd__nor4_1", 34],
+ ["sky130_fd_sc_hd__o21ai_4", 51],
+ ["sky130_fd_sc_hd__o21ba_1", 146],
+ ["sky130_fd_sc_hd__clkbuf_8", 147],
+ ["sky130_fd_sc_hd__a31oi_4", 16],
+ ["sky130_fd_sc_hd__nand4_1", 53],
+ ["sky130_fd_sc_hd__or4b_1", 178],
+ ["sky130_fd_sc_hd__mux4_1", 80],
+ ["sky130_fd_sc_hd__nor3_1", 46],
+ ["sky130_fd_sc_hd__nor2_2", 27],
+ ["sky130_fd_sc_hd__or2_1", 215],
+ ["sky130_fd_sc_hd__nand2_8", 27],
+ ["sky130_fd_sc_hd__a311oi_1", 44],
+ ["sky130_fd_sc_hd__clkinv_16", 26],
+ ["sky130_fd_sc_hd__nand3_1", 34],
+ ["sky130_fd_sc_hd__a221o_2", 38],
+ ["sky130_fd_sc_hd__a21o_4", 7],
+ ["sky130_fd_sc_hd__a2bb2o_1", 77],
+ ["sky130_fd_sc_hd__a21boi_1", 18],
+ ["sky130_fd_sc_hd__nand2_2", 27],
+ ["sky130_fd_sc_hd__a21oi_2", 18],
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+ ["sky130_fd_sc_hd__or4bb_1", 9],
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+ ["sky130_fd_sc_hd__mux2_4", 11],
+ ["sky130_fd_sc_hd__clkinv_4", 27],
+ ["sky130_fd_sc_hd__clkbuf_4", 48],
+ ["sky130_fd_sc_hd__o211ai_1", 20],
+ ["sky130_fd_sc_hd__nor2_4", 16],
+ ["sky130_fd_sc_hd__a21oi_4", 36],
+ ["sky130_fd_sc_hd__o2111ai_1", 29],
+ ["sky130_fd_sc_hd__nand2b_1", 66],
+ ["sky130_fd_sc_hd__or4bb_4", 11],
+ ["sky130_fd_sc_hd__and2_2", 8],
+ ["sky130_fd_sc_hd__and4b_4", 37],
+ ["sky130_fd_sc_hd__o2111a_1", 85],
+ ["sky130_fd_sc_hd__a2bb2o_4", 7],
+ ["sky130_fd_sc_hd__and4bb_1", 22],
+ ["sky130_fd_sc_hd__xnor2_1", 33],
+ ["sky130_fd_sc_hd__and4_2", 22],
+ ["sky130_fd_sc_hd__nand4_2", 14],
+ ["sky130_fd_sc_hd__clkbuf_1", 134],
+ ["sky130_fd_sc_hd__o22a_4", 5],
+ ["sky130_fd_sc_hd__clkbuf_2", 26],
+ ["sky130_fd_sc_hd__dlymetal6s2s_1", 5],
+ ["sky130_fd_sc_hd__buf_2", 13],
+ ["sky130_fd_sc_hd__xor2_1", 39],
+ ["sky130_fd_sc_hd__and4_4", 45],
+ ["sky130_fd_sc_hd__o32a_1", 27],
+ ["sky130_fd_sc_hd__or4b_2", 16],
+ ["sky130_fd_sc_hd__a22oi_2", 13],
+ ["sky130_fd_sc_hd__and2_4", 15],
+ ["sky130_fd_sc_hd__nand4_4", 21],
+ ["sky130_fd_sc_hd__a2111o_2", 4],
+ ["sky130_fd_sc_hd__o2bb2a_1", 53],
+ ["sky130_fd_sc_hd__and4b_2", 8],
+ ["sky130_fd_sc_hd__and3b_1", 67],
+ ["sky130_fd_sc_hd__a2111oi_1", 7],
+ ["sky130_fd_sc_hd__o2111ai_4", 10],
+ ["sky130_fd_sc_hd__o22ai_4", 7],
+ ["sky130_fd_sc_hd__a211o_2", 17],
+ ["sky130_fd_sc_hd__a32oi_4", 4],
+ ["sky130_fd_sc_hd__and2b_4", 11],
+ ["sky130_fd_sc_hd__clkinv_2", 28],
+ ["sky130_fd_sc_hd__conb_1", 11],
+ ["sky130_fd_sc_hd__o2bb2ai_2", 2],
+ ["sky130_fd_sc_hd__or3b_2", 8],
+ ["sky130_fd_sc_hd__or3b_4", 28],
+ ["sky130_fd_sc_hd__a22oi_1", 20],
+ ["sky130_fd_sc_hd__o31a_2", 14],
+ ["sky130_fd_sc_hd__or2_4", 27],
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+ ["sky130_fd_sc_hd__and4bb_4", 20],
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+ ["sky130_fd_sc_hd__o21ai_2", 33],
+ ["sky130_fd_sc_hd__or2_2", 7],
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+ ["sky130_fd_sc_hd__o211ai_4", 12],
+ ["sky130_fd_sc_hd__o311ai_1", 4],
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+ ["sky130_fd_sc_hd__o22ai_1", 6],
+ ["sky130_fd_sc_hd__nand2_4", 16],
+ ["sky130_fd_sc_hd__o21bai_4", 2],
+ ["sky130_fd_sc_hd__a211oi_1", 49],
+ ["sky130_fd_sc_hd__inv_4", 13],
+ ["sky130_fd_sc_hd__mux2_8", 7],
+ ["sky130_fd_sc_hd__inv_6", 9],
+ ["sky130_fd_sc_hd__a22oi_4", 21],
+ ["sky130_fd_sc_hd__nor2_8", 34],
+ ["sky130_fd_sc_hd__nor4_4", 13],
+ ["sky130_fd_sc_hd__a41o_2", 6],
+ ["sky130_fd_sc_hd__mux2_2", 18],
+ ["sky130_fd_sc_hd__nand2b_2", 4],
+ ["sky130_fd_sc_hd__o221ai_4", 12],
+ ["sky130_fd_sc_hd__a211o_4", 12],
+ ["sky130_fd_sc_hd__o2bb2a_2", 8],
+ ["sky130_fd_sc_hd__nand2b_4", 17],
+ ["sky130_fd_sc_hd__o21a_2", 5],
+ ["sky130_fd_sc_hd__o2111ai_2", 3],
+ ["sky130_fd_sc_hd__a311o_2", 8],
+ ["sky130_fd_sc_hd__a221oi_1", 7],
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+ ["sky130_fd_sc_hd__o2bb2ai_1", 13],
+ ["sky130_fd_sc_hd__o31a_4", 8],
+ ["sky130_fd_sc_hd__xor2_4", 9],
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+ ["sky130_fd_sc_hd__nor3_4", 10],
+ ["sky130_fd_sc_hd__o211ai_2", 5],
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+ ["sky130_fd_sc_hd__nand3b_1", 16],
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+ ["sky130_fd_sc_hd__o311a_2", 5],
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+ ["sky130_fd_sc_hd__o311a_4", 1],
+ ["sky130_fd_sc_hd__a41oi_2", 1],
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+ ["sky130_fd_sc_hd__a2bb2oi_1", 3],
+ ["sky130_fd_sc_hd__nor3b_2", 3],
+ ["sky130_fd_sc_hd__nor4b_4", 4],
+ ["sky130_fd_sc_hd__o32ai_1", 2],
+ ["sky130_fd_sc_hd__inv_8", 4],
+ ["sky130_fd_sc_hd__nand3b_4", 5],
+ ["sky130_fd_sc_hd__nor3b_4", 2],
+ ["RAM128", 1],
+ ["sky130_fd_sc_hd__nand3_4", 5],
+ ["sky130_fd_sc_hd__xnor2_4", 2],
+ ["sky130_fd_sc_hd__a2111oi_4", 1],
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+ ["sky130_fd_sc_hd__clkinv_8", 6],
+ ["sky130_fd_sc_hd__xnor2_2", 3],
+ ["sky130_fd_sc_hd__o41ai_2", 1],
+ ["sky130_fd_sc_hd__o31ai_4", 5],
+ ["sky130_fd_sc_hd__nor4b_2", 1],
+ ["sky130_fd_sc_hd__o31ai_2", 4],
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+ ["sky130_fd_sc_hd__nand3b_2", 7],
+ ["RAM256", 1],
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+ ["sky130_fd_sc_hd__a311oi_2", 1],
+ ["sky130_fd_sc_hd__o32ai_4", 1],
+ ["sky130_fd_sc_hd__a41oi_4", 1 ]
+ ], [
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+ ["sky130_ef_sc_hd__decap_12", 1 ],
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+ ["sky130_fd_sc_hd__clkbuf_16", 578 ],
+ ["sky130_fd_sc_hd__decap_4", 1 ],
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+ ["sky130_fd_sc_hd__a221o_1", 265 ],
+ ["sky130_fd_sc_hd__a32o_1", 171 ],
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+ ["sky130_fd_sc_hd__dfxtp_1", 3755 ],
+ ["sky130_fd_sc_hd__o31a_1", 254 ],
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+ ["sky130_fd_sc_hd__buf_4", 110 ],
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+ ["sky130_fd_sc_hd__a22o_1", 428 ],
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+ ["sky130_fd_sc_hd__a22o_2", 52 ],
+ ["sky130_fd_sc_hd__a22o_4", 60 ],
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+ ["sky130_fd_sc_hd__a311o_1", 165 ],
+ ["sky130_fd_sc_hd__mux4_2", 14 ],
+ ["sky130_fd_sc_hd__and3b_4", 6 ],
+ ["sky130_fd_sc_hd__a2111o_1", 15 ],
+ ["sky130_fd_sc_hd__nor4_1", 34 ],
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+ ["sky130_fd_sc_hd__o21ba_1", 146 ],
+ ["sky130_fd_sc_hd__clkbuf_8", 147 ],
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+ ["sky130_fd_sc_hd__nand4_1", 53 ],
+ ["sky130_fd_sc_hd__or4b_1", 178 ],
+ ["sky130_fd_sc_hd__mux4_1", 80 ],
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+ ["sky130_fd_sc_hd__or2_1", 215 ],
+ ["sky130_fd_sc_hd__nand2_8", 27 ],
+ ["sky130_fd_sc_hd__a311oi_1", 44 ],
+ ["sky130_fd_sc_hd__clkinv_16", 26 ],
+ ["sky130_fd_sc_hd__nand3_1", 34 ],
+ ["sky130_fd_sc_hd__a221o_2", 38 ],
+ ["sky130_fd_sc_hd__a21o_4", 7 ],
+ ["sky130_fd_sc_hd__a2bb2o_1", 77 ],
+ ["sky130_fd_sc_hd__a21boi_1", 18 ],
+ ["sky130_fd_sc_hd__nand2_2", 27 ],
+ ["sky130_fd_sc_hd__a21oi_2", 18 ],
+ ["sky130_fd_sc_hd__o21bai_1", 11 ],
+ ["sky130_fd_sc_hd__and3_2", 38 ],
+ ["sky130_fd_sc_hd__a21oi_1", 305 ],
+ ["sky130_fd_sc_hd__or4bb_1", 9 ],
+ ["sky130_fd_sc_hd__a221oi_4", 17 ],
+ ["sky130_fd_sc_hd__mux2_4", 11 ],
+ ["sky130_fd_sc_hd__clkinv_4", 27 ],
+ ["sky130_fd_sc_hd__clkbuf_4", 48 ],
+ ["sky130_fd_sc_hd__o211ai_1", 20 ],
+ ["sky130_fd_sc_hd__nor2_4", 16 ],
+ ["sky130_fd_sc_hd__a21oi_4", 36 ],
+ ["sky130_fd_sc_hd__o2111ai_1", 29 ],
+ ["sky130_fd_sc_hd__nand2b_1", 66 ],
+ ["sky130_fd_sc_hd__or4bb_4", 11 ],
+ ["sky130_fd_sc_hd__and2_2", 8 ],
+ ["sky130_fd_sc_hd__and4b_4", 37 ],
+ ["sky130_fd_sc_hd__o2111a_1", 85 ],
+ ["sky130_fd_sc_hd__a2bb2o_4", 7 ],
+ ["sky130_fd_sc_hd__and4bb_1", 22 ],
+ ["sky130_fd_sc_hd__xnor2_1", 33 ],
+ ["sky130_fd_sc_hd__and4_2", 22 ],
+ ["sky130_fd_sc_hd__nand4_2", 14 ],
+ ["sky130_fd_sc_hd__clkbuf_1", 134 ],
+ ["sky130_fd_sc_hd__o22a_4", 5 ],
+ ["sky130_fd_sc_hd__clkbuf_2", 26 ],
+ ["sky130_fd_sc_hd__dlymetal6s2s_1", 5 ],
+ ["sky130_fd_sc_hd__buf_2", 13 ],
+ ["sky130_fd_sc_hd__xor2_1", 39 ],
+ ["sky130_fd_sc_hd__and4_4", 45 ],
+ ["sky130_fd_sc_hd__o32a_1", 27 ],
+ ["sky130_fd_sc_hd__or4b_2", 16 ],
+ ["sky130_fd_sc_hd__a22oi_2", 13 ],
+ ["sky130_fd_sc_hd__and2_4", 15 ],
+ ["sky130_fd_sc_hd__nand4_4", 21 ],
+ ["sky130_fd_sc_hd__a2111o_2", 4 ],
+ ["sky130_fd_sc_hd__o2bb2a_1", 53 ],
+ ["sky130_fd_sc_hd__and4b_2", 8 ],
+ ["sky130_fd_sc_hd__and3b_1", 67 ],
+ ["sky130_fd_sc_hd__a2111oi_1", 7 ],
+ ["sky130_fd_sc_hd__o2111ai_4", 10 ],
+ ["sky130_fd_sc_hd__o22ai_4", 7 ],
+ ["sky130_fd_sc_hd__a211o_2", 17 ],
+ ["sky130_fd_sc_hd__a32oi_4", 4 ],
+ ["sky130_fd_sc_hd__and2b_4", 11 ],
+ ["sky130_fd_sc_hd__clkinv_2", 28 ],
+ ["sky130_fd_sc_hd__conb_1", 11 ],
+ ["sky130_fd_sc_hd__o2bb2ai_2", 2 ],
+ ["sky130_fd_sc_hd__or3b_2", 8 ],
+ ["sky130_fd_sc_hd__or3b_4", 28 ],
+ ["sky130_fd_sc_hd__a22oi_1", 20 ],
+ ["sky130_fd_sc_hd__o31a_2", 14 ],
+ ["sky130_fd_sc_hd__or2_4", 27 ],
+ ["sky130_fd_sc_hd__a21o_2", 6 ],
+ ["sky130_fd_sc_hd__a31o_2", 14 ],
+ ["sky130_fd_sc_hd__and4bb_4", 20 ],
+ ["sky130_fd_sc_hd__o41ai_1", 6 ],
+ ["sky130_fd_sc_hd__o21ba_2", 3 ],
+ ["sky130_fd_sc_hd__nor3_2", 10 ],
+ ["sky130_fd_sc_hd__a32o_2", 7 ],
+ ["sky130_fd_sc_hd__a32o_4", 9 ],
+ ["sky130_fd_sc_hd__o21ai_2", 33 ],
+ ["sky130_fd_sc_hd__or2_2", 7 ],
+ ["sky130_fd_sc_hd__nand3_2", 11 ],
+ ["sky130_fd_sc_hd__o211ai_4", 12 ],
+ ["sky130_fd_sc_hd__o311ai_1", 4 ],
+ ["sky130_fd_sc_hd__nor4b_1", 2 ],
+ ["sky130_fd_sc_hd__o31ai_1", 16 ],
+ ["sky130_fd_sc_hd__nor4_2", 14 ],
+ ["sky130_fd_sc_hd__o22ai_1", 6 ],
+ ["sky130_fd_sc_hd__nand2_4", 16 ],
+ ["sky130_fd_sc_hd__o21bai_4", 2 ],
+ ["sky130_fd_sc_hd__a211oi_1", 49 ],
+ ["sky130_fd_sc_hd__inv_4", 13 ],
+ ["sky130_fd_sc_hd__mux2_8", 7 ],
+ ["sky130_fd_sc_hd__inv_6", 9 ],
+ ["sky130_fd_sc_hd__a22oi_4", 21 ],
+ ["sky130_fd_sc_hd__nor2_8", 34 ],
+ ["sky130_fd_sc_hd__nor4_4", 13 ],
+ ["sky130_fd_sc_hd__a41o_2", 6 ],
+ ["sky130_fd_sc_hd__mux2_2", 18 ],
+ ["sky130_fd_sc_hd__nand2b_2", 4 ],
+ ["sky130_fd_sc_hd__o221ai_4", 12 ],
+ ["sky130_fd_sc_hd__a211o_4", 12 ],
+ ["sky130_fd_sc_hd__o2bb2a_2", 8 ],
+ ["sky130_fd_sc_hd__nand2b_4", 17 ],
+ ["sky130_fd_sc_hd__o21a_2", 5 ],
+ ["sky130_fd_sc_hd__o2111ai_2", 3 ],
+ ["sky130_fd_sc_hd__a311o_2", 8 ],
+ ["sky130_fd_sc_hd__a221oi_1", 7 ],
+ ["sky130_fd_sc_hd__o41a_4", 14 ],
+ ["sky130_fd_sc_hd__nand4b_2", 1 ],
+ ["sky130_fd_sc_hd__o2bb2ai_1", 13 ],
+ ["sky130_fd_sc_hd__o31a_4", 8 ],
+ ["sky130_fd_sc_hd__xor2_4", 9 ],
+ ["sky130_fd_sc_hd__a2bb2o_2", 5 ],
+ ["sky130_fd_sc_hd__nor3_4", 10 ],
+ ["sky130_fd_sc_hd__o211ai_2", 5 ],
+ ["sky130_fd_sc_hd__o311ai_4", 5 ],
+ ["sky130_fd_sc_hd__o211a_2", 13 ],
+ ["sky130_fd_sc_hd__nand3b_1", 16 ],
+ ["sky130_fd_sc_hd__o22a_2", 5 ],
+ ["sky130_fd_sc_hd__a2bb2oi_4", 1 ],
+ ["sky130_fd_sc_hd__and2b_2", 3 ],
+ ["sky130_fd_sc_hd__o21a_4", 14 ],
+ ["sky130_fd_sc_hd__a2bb2oi_2", 1 ],
+ ["sky130_fd_sc_hd__o311a_2", 5 ],
+ ["sky130_fd_sc_hd__o221ai_1", 8 ],
+ ["sky130_fd_sc_hd__and4bb_2", 4 ],
+ ["sky130_fd_sc_hd__inv_12", 2 ],
+ ["sky130_fd_sc_hd__o211a_4", 9 ],
+ ["sky130_fd_sc_hd__o311a_4", 1 ],
+ ["sky130_fd_sc_hd__a41oi_2", 1 ],
+ ["sky130_fd_sc_hd__nand4b_4", 3 ],
+ ["sky130_fd_sc_hd__xor2_2", 7 ],
+ ["sky130_fd_sc_hd__a2111o_4", 4 ],
+ ["sky130_fd_sc_hd__o41a_2", 6 ],
+ ["sky130_fd_sc_hd__o221a_2", 1 ],
+ ["sky130_fd_sc_hd__and3b_2", 2 ],
+ ["sky130_fd_sc_hd__a2bb2oi_1", 3 ],
+ ["sky130_fd_sc_hd__nor3b_2", 3 ],
+ ["sky130_fd_sc_hd__nor4b_4", 4 ],
+ ["sky130_fd_sc_hd__o32ai_1", 2 ],
+ ["sky130_fd_sc_hd__inv_8", 4 ],
+ ["sky130_fd_sc_hd__nand3b_4", 5 ],
+ ["sky130_fd_sc_hd__nor3b_4", 2 ],
+ ["RAM128", 1 ],
+ ["sky130_fd_sc_hd__nand3_4", 5 ],
+ ["sky130_fd_sc_hd__xnor2_4", 2 ],
+ ["sky130_fd_sc_hd__a2111oi_4", 1 ],
+ ["sky130_fd_sc_hd__a311o_4", 3 ],
+ ["sky130_fd_sc_hd__a221oi_2", 6 ],
+ ["sky130_fd_sc_hd__o22ai_2", 2 ],
+ ["sky130_fd_sc_hd__a31oi_2", 4 ],
+ ["sky130_fd_sc_hd__o2111a_2", 2 ],
+ ["sky130_fd_sc_hd__clkinv_8", 6 ],
+ ["sky130_fd_sc_hd__xnor2_2", 3 ],
+ ["sky130_fd_sc_hd__o41ai_2", 1 ],
+ ["sky130_fd_sc_hd__o31ai_4", 5 ],
+ ["sky130_fd_sc_hd__nor4b_2", 1 ],
+ ["sky130_fd_sc_hd__o31ai_2", 4 ],
+ ["sky130_fd_sc_hd__o2111a_4", 3 ],
+ ["sky130_fd_sc_hd__o2bb2a_4", 3 ],
+ ["sky130_fd_sc_hd__a41o_4", 2 ],
+ ["sky130_fd_sc_hd__a32oi_2", 1 ],
+ ["sky130_fd_sc_hd__a32oi_1", 2 ],
+ ["sky130_fd_sc_hd__a21boi_2", 1 ],
+ ["sky130_fd_sc_hd__nand3b_2", 7 ],
+ ["RAM256", 1 ],
+ ["sky130_fd_sc_hd__o21bai_2", 1 ],
+ ["sky130_fd_sc_hd__o2bb2ai_4", 1 ],
+ ["sky130_fd_sc_hd__o311ai_2", 3 ],
+ ["sky130_fd_sc_hd__a2111oi_2", 3 ],
+ ["sky130_fd_sc_hd__nand4b_1", 1 ],
+ ["sky130_fd_sc_hd__nor3b_1", 4 ],
+ ["sky130_fd_sc_hd__a41oi_1", 1 ],
+ ["sky130_fd_sc_hd__a311oi_2", 1 ],
+ ["sky130_fd_sc_hd__o32ai_4", 1 ],
+ ["sky130_fd_sc_hd__a41oi_4", 1 ]
+ ]
+ ],
+ "nets": [
+ 25043,
+ 25043
+ ],
+ "badnets": [
+ ],
+ "badelements": [
+ ],
+ "pins": [
+ [
+ "flash_io3_oeb",
+ "flash_io2_oeb",
+ "flash_io1_oeb",
+ "mprj_adr_o[0]",
+ "flash_io3_do",
+ "flash_io2_do",
+ "flash_io1_do",
+ "debug_out",
+ "trap",
+ "qspi_enabled",
+ "mprj_adr_o[1]",
+ "mprj_we_o",
+ "mprj_adr_o[29]",
+ "mprj_adr_o[9]",
+ "mprj_adr_o[27]",
+ "mprj_adr_o[7]",
+ "mprj_adr_o[31]",
+ "mprj_adr_o[30]",
+ "mprj_adr_o[28]",
+ "mprj_adr_o[25]",
+ "mprj_adr_o[5]",
+ "mprj_adr_o[21]",
+ "mprj_adr_o[16]",
+ "mprj_adr_o[15]",
+ "mprj_adr_o[14]",
+ "mprj_adr_o[3]",
+ "mprj_adr_o[2]",
+ "mprj_adr_o[13]",
+ "mprj_adr_o[4]",
+ "mprj_adr_o[20]",
+ "mprj_adr_o[12]",
+ "mprj_adr_o[11]",
+ "mprj_dat_o[22]",
+ "la_output[91]",
+ "mprj_dat_o[31]",
+ "mprj_dat_o[21]",
+ "mprj_adr_o[10]",
+ "la_output[90]",
+ "mprj_dat_o[30]",
+ "mprj_dat_o[10]",
+ "la_output[9]",
+ "la_output[89]",
+ "mprj_dat_o[29]",
+ "mprj_dat_o[19]",
+ "mprj_adr_o[18]",
+ "mprj_dat_o[9]",
+ "mprj_dat_o[18]",
+ "mprj_dat_o[17]",
+ "mprj_dat_o[26]",
+ "mprj_dat_o[16]",
+ "mprj_dat_o[15]",
+ "mprj_dat_o[24]",
+ "mprj_dat_o[14]",
+ "spi_csb",
+ "mprj_dat_o[23]",
+ "la_output[23]",
+ "la_output[69]",
+ "la_output[29]",
+ "la_output[19]",
+ "la_output[78]",
+ "la_output[48]",
+ "la_output[88]",
+ "la_output[87]",
+ "la_output[67]",
+ "la_output[17]",
+ "la_output[26]",
+ "la_output[16]",
+ "la_output[85]",
+ "la_output[66]",
+ "la_output[65]",
+ "la_output[84]",
+ "la_output[64]",
+ "la_output[54]",
+ "la_output[24]",
+ "la_output[83]",
+ "la_output[75]",
+ "la_output[73]",
+ "la_output[63]",
+ "la_output[82]",
+ "la_output[77]",
+ "la_output[74]",
+ "la_output[72]",
+ "la_output[71]",
+ "la_output[70]",
+ "la_output[81]",
+ "la_output[79]",
+ "la_output[93]",
+ "la_output[92]",
+ "hk_stb_o",
+ "la_iena[12]",
+ "ser_tx",
+ "mprj_cyc_o",
+ "rstb_l_out",
+ "spi_sck",
+ "mprj_stb_o",
+ "mprj_sel_o[3]",
+ "mprj_sel_o[1]",
+ "mprj_sel_o[0]",
+ "serial_clock_out",
+ "serial_resetn_out",
+ "serial_load_out",
+ "serial_data_2_out",
+ "la_oenb[86]",
+ "la_oenb[121]",
+ "la_oenb[10]",
+ "flash_clk",
+ "hk_cyc_o",
+ "la_oenb[49]",
+ "la_oenb[15]",
+ "la_oenb[12]",
+ "gpio_outenb_pad",
+ "gpio_inenb_pad",
+ "la_oenb[90]",
+ "la_oenb[88]",
+ "la_oenb[85]",
+ "la_oenb[59]",
+ "la_oenb[54]",
+ "la_oenb[45]",
+ "la_oenb[39]",
+ "la_oenb[38]",
+ "la_oenb[13]",
+ "la_iena[35]",
+ "la_iena[13]",
+ "la_oenb[94]",
+ "la_oenb[55]",
+ "la_oenb[44]",
+ "la_iena[8]",
+ "la_iena[36]",
+ "la_iena[25]",
+ "la_iena[14]",
+ "la_oenb[93]",
+ "la_oenb[91]",
+ "la_oenb[87]",
+ "la_oenb[78]",
+ "la_oenb[32]",
+ "la_iena[86]",
+ "la_oenb[73]",
+ "la_oenb[41]",
+ "la_oenb[25]",
+ "la_iena[15]",
+ "la_oenb[8]",
+ "la_oenb[61]",
+ "la_oenb[58]",
+ "la_oenb[56]",
+ "la_oenb[53]",
+ "la_oenb[51]",
+ "la_oenb[52]",
+ "la_oenb[50]",
+ "la_oenb[43]",
+ "la_oenb[35]",
+ "la_oenb[37]",
+ "la_oenb[34]",
+ "la_oenb[33]",
+ "la_oenb[14]",
+ "la_iena[32]",
+ "mprj_dat_o[12]",
+ "mprj_adr_o[22]",
+ "la_output[111]",
+ "la_output[101]",
+ "mprj_dat_o[11]",
+ "la_output[110]",
+ "la_output[100]",
+ "mprj_sel_o[2]",
+ "mprj_dat_o[20]",
+ "la_output[8]",
+ "la_output[10]",
+ "la_output[0]",
+ "mprj_dat_o[2]",
+ "mprj_dat_o[1]",
+ "mprj_dat_o[0]",
+ "mprj_adr_o[19]",
+ "la_output[99]",
+ "la_output[109]",
+ "user_irq_ena[0]",
+ "la_output[98]",
+ "la_output[108]",
+ "mprj_dat_o[28]",
+ "mprj_adr_o[17]",
+ "la_output[97]",
+ "la_output[107]",
+ "mprj_dat_o[8]",
+ "mprj_dat_o[27]",
+ "mprj_adr_o[8]",
+ "la_output[106]",
+ "spi_sdo",
+ "mprj_dat_o[7]",
+ "mprj_adr_o[26]",
+ "la_output[105]",
+ "mprj_dat_o[6]",
+ "mprj_dat_o[25]",
+ "mprj_adr_o[6]",
+ "la_output[104]",
+ "spi_enabled",
+ "mprj_dat_o[5]",
+ "la_output[103]",
+ "mprj_wb_iena",
+ "mprj_dat_o[4]",
+ "mprj_dat_o[3]",
+ "la_output[120]",
+ "la_output[14]",
+ "la_output[11]",
+ "la_output[13]",
+ "la_output[119]",
+ "la_output[32]",
+ "la_output[22]",
+ "la_output[12]",
+ "la_output[118]",
+ "la_output[41]",
+ "la_output[31]",
+ "la_output[21]",
+ "la_output[127]",
+ "la_output[117]",
+ "la_output[50]",
+ "la_output[30]",
+ "la_output[20]",
+ "la_output[126]",
+ "la_output[5]",
+ "la_output[4]",
+ "la_output[3]",
+ "la_output[2]",
+ "la_output[1]",
+ "la_output[125]",
+ "la_output[115]",
+ "la_output[49]",
+ "la_output[39]",
+ "la_output[124]",
+ "la_output[116]",
+ "la_output[114]",
+ "la_output[58]",
+ "la_output[38]",
+ "la_output[18]",
+ "la_output[123]",
+ "la_output[113]",
+ "la_output[57]",
+ "la_output[47]",
+ "la_output[37]",
+ "la_output[27]",
+ "la_output[122]",
+ "la_output[112]",
+ "la_output[86]",
+ "la_output[76]",
+ "la_output[68]",
+ "la_output[59]",
+ "la_output[56]",
+ "la_output[46]",
+ "la_output[36]",
+ "la_output[121]",
+ "la_output[55]",
+ "la_output[45]",
+ "la_output[35]",
+ "la_output[28]",
+ "la_output[25]",
+ "la_output[15]",
+ "la_output[44]",
+ "la_output[34]",
+ "user_irq_ena[2]",
+ "user_irq_ena[1]",
+ "la_output[53]",
+ "la_output[43]",
+ "la_output[33]",
+ "la_output[62]",
+ "la_output[52]",
+ "la_output[42]",
+ "la_output[40]",
+ "la_output[61]",
+ "la_output[51]",
+ "debug_oeb",
+ "la_output[80]",
+ "la_output[60]",
+ "debug_mode",
+ "la_output[7]",
+ "la_output[6]",
+ "gpio_out_pad",
+ "gpio_mode1_pad",
+ "la_output[96]",
+ "gpio_mode0_pad",
+ "la_output[95]",
+ "la_output[94]",
+ "mprj_adr_o[24]",
+ "mprj_dat_o[13]",
+ "mprj_adr_o[23]",
+ "la_output[102]",
+ "uart_enabled",
+ "porb_h_out",
+ "por_l_out",
+ "resetn_out",
+ "clk_out",
+ "flash_io0_oeb",
+ "flash_io0_do",
+ "la_oenb[99]",
+ "la_oenb[98]",
+ "la_oenb[97]",
+ "la_oenb[96]",
+ "la_oenb[95]",
+ "la_oenb[7]",
+ "la_oenb[71]",
+ "la_oenb[70]",
+ "la_oenb[6]",
+ "la_oenb[66]",
+ "la_oenb[60]",
+ "la_oenb[5]",
+ "la_oenb[57]",
+ "la_oenb[4]",
+ "la_oenb[42]",
+ "la_oenb[40]",
+ "la_oenb[46]",
+ "la_oenb[3]",
+ "la_oenb[31]",
+ "la_oenb[30]",
+ "la_oenb[2]",
+ "la_oenb[28]",
+ "la_oenb[22]",
+ "la_oenb[1]",
+ "la_oenb[16]",
+ "la_oenb[127]",
+ "la_oenb[126]",
+ "la_oenb[125]",
+ "la_oenb[124]",
+ "la_oenb[123]",
+ "la_oenb[122]",
+ "la_oenb[120]",
+ "la_oenb[119]",
+ "la_oenb[117]",
+ "la_oenb[116]",
+ "la_oenb[115]",
+ "la_oenb[114]",
+ "la_oenb[113]",
+ "la_oenb[111]",
+ "la_oenb[110]",
+ "la_oenb[109]",
+ "la_oenb[107]",
+ "la_oenb[106]",
+ "la_oenb[105]",
+ "la_oenb[104]",
+ "la_oenb[103]",
+ "la_oenb[102]",
+ "la_oenb[101]",
+ "la_oenb[100]",
+ "la_oenb[0]",
+ "la_iena[9]",
+ "la_iena[99]",
+ "la_iena[98]",
+ "la_iena[97]",
+ "la_iena[96]",
+ "la_iena[7]",
+ "la_iena[6]",
+ "la_iena[61]",
+ "la_iena[60]",
+ "la_iena[5]",
+ "la_iena[59]",
+ "la_iena[58]",
+ "la_iena[57]",
+ "la_iena[56]",
+ "la_iena[55]",
+ "la_iena[53]",
+ "la_iena[52]",
+ "la_iena[51]",
+ "la_iena[50]",
+ "la_iena[4]",
+ "la_iena[47]",
+ "la_iena[45]",
+ "la_iena[44]",
+ "la_iena[43]",
+ "la_iena[42]",
+ "la_iena[49]",
+ "la_iena[41]",
+ "la_iena[39]",
+ "la_iena[38]",
+ "la_iena[37]",
+ "la_iena[34]",
+ "la_iena[33]",
+ "la_iena[31]",
+ "la_iena[30]",
+ "la_iena[3]",
+ "la_iena[2]",
+ "la_iena[29]",
+ "la_iena[28]",
+ "la_iena[22]",
+ "la_iena[1]",
+ "la_iena[127]",
+ "la_iena[126]",
+ "la_iena[125]",
+ "la_iena[124]",
+ "la_iena[123]",
+ "la_iena[122]",
+ "la_iena[121]",
+ "la_iena[120]",
+ "la_iena[11]",
+ "la_iena[119]",
+ "la_iena[117]",
+ "la_iena[116]",
+ "la_iena[115]",
+ "la_iena[114]",
+ "la_iena[113]",
+ "la_iena[111]",
+ "la_iena[110]",
+ "la_iena[10]",
+ "la_iena[109]",
+ "la_iena[107]",
+ "la_iena[106]",
+ "la_iena[105]",
+ "la_iena[104]",
+ "la_iena[103]",
+ "la_iena[102]",
+ "la_iena[101]",
+ "la_iena[100]",
+ "la_iena[0]",
+ "flash_csb",
+ "spi_sdoenb",
+ "la_oenb[9]",
+ "la_oenb[92]",
+ "la_oenb[89]",
+ "la_oenb[84]",
+ "la_oenb[83]",
+ "la_oenb[82]",
+ "la_oenb[81]",
+ "la_oenb[80]",
+ "la_oenb[79]",
+ "la_oenb[77]",
+ "la_oenb[76]",
+ "la_oenb[75]",
+ "la_oenb[74]",
+ "la_oenb[72]",
+ "la_oenb[69]",
+ "la_oenb[68]",
+ "la_oenb[67]",
+ "la_oenb[65]",
+ "la_oenb[64]",
+ "la_oenb[63]",
+ "la_oenb[62]",
+ "la_oenb[48]",
+ "la_oenb[47]",
+ "la_oenb[36]",
+ "la_oenb[29]",
+ "la_oenb[26]",
+ "la_oenb[24]",
+ "la_oenb[27]",
+ "la_oenb[23]",
+ "la_oenb[21]",
+ "la_oenb[20]",
+ "la_oenb[19]",
+ "la_oenb[18]",
+ "la_oenb[17]",
+ "la_oenb[11]",
+ "la_oenb[118]",
+ "la_oenb[112]",
+ "la_oenb[108]",
+ "la_iena[95]",
+ "la_iena[94]",
+ "la_iena[92]",
+ "la_iena[93]",
+ "la_iena[91]",
+ "la_iena[90]",
+ "la_iena[89]",
+ "la_iena[88]",
+ "la_iena[87]",
+ "la_iena[85]",
+ "la_iena[84]",
+ "la_iena[83]",
+ "la_iena[82]",
+ "la_iena[81]",
+ "la_iena[80]",
+ "la_iena[79]",
+ "la_iena[78]",
+ "la_iena[76]",
+ "la_iena[75]",
+ "la_iena[73]",
+ "la_iena[77]",
+ "la_iena[74]",
+ "la_iena[72]",
+ "la_iena[71]",
+ "la_iena[70]",
+ "la_iena[69]",
+ "la_iena[68]",
+ "la_iena[67]",
+ "la_iena[66]",
+ "la_iena[65]",
+ "la_iena[64]",
+ "la_iena[63]",
+ "la_iena[62]",
+ "la_iena[54]",
+ "la_iena[48]",
+ "la_iena[46]",
+ "la_iena[40]",
+ "la_iena[26]",
+ "la_iena[24]",
+ "la_iena[23]",
+ "la_iena[27]",
+ "la_iena[21]",
+ "la_iena[20]",
+ "la_iena[18]",
+ "la_iena[19]",
+ "la_iena[17]",
+ "la_iena[16]",
+ "la_iena[118]",
+ "la_iena[112]",
+ "la_iena[108]",
+ "spi_sdi",
+ "serial_resetn_in",
+ "serial_clock_in",
+ "serial_load_in",
+ "serial_data_2_in",
+ "ser_rx",
+ "por_l_in",
+ "porb_h_in",
+ "mprj_dat_i[6]",
+ "mprj_dat_i[2]",
+ "mprj_dat_i[24]",
+ "mprj_dat_i[4]",
+ "mprj_dat_i[1]",
+ "mprj_ack_i",
+ "mprj_dat_i[0]",
+ "mprj_dat_i[9]",
+ "la_input[94]",
+ "la_input[93]",
+ "mprj_dat_i[31]",
+ "mprj_dat_i[30]",
+ "mprj_dat_i[29]",
+ "la_input[118]",
+ "la_input[91]",
+ "la_input[89]",
+ "la_input[87]",
+ "mprj_dat_i[16]",
+ "irq[0]",
+ "mprj_dat_i[20]",
+ "mprj_dat_i[19]",
+ "mprj_dat_i[10]",
+ "mprj_dat_i[15]",
+ "gpio_in_pad",
+ "mprj_dat_i[18]",
+ "mprj_dat_i[13]",
+ "la_input[95]",
+ "mprj_dat_i[7]",
+ "mprj_dat_i[5]",
+ "mprj_dat_i[3]",
+ "mprj_dat_i[14]",
+ "mprj_dat_i[8]",
+ "mprj_dat_i[12]",
+ "mprj_dat_i[11]",
+ "la_input[92]",
+ "mprj_dat_i[28]",
+ "mprj_dat_i[27]",
+ "mprj_dat_i[26]",
+ "mprj_dat_i[25]",
+ "mprj_dat_i[23]",
+ "mprj_dat_i[22]",
+ "mprj_dat_i[17]",
+ "debug_in",
+ "rstb_l_in",
+ "irq[2]",
+ "irq[1]",
+ "core_rstn",
+ "flash_io1_di",
+ "la_input[42]",
+ "la_input[41]",
+ "la_input[40]",
+ "la_input[39]",
+ "irq[4]",
+ "irq[5]",
+ "irq[3]",
+ "la_input[49]",
+ "la_input[70]",
+ "la_input[69]",
+ "la_input[68]",
+ "la_input[107]",
+ "la_input[56]",
+ "la_input[58]",
+ "la_input[55]",
+ "la_input[57]",
+ "la_input[66]",
+ "la_input[65]",
+ "la_input[67]",
+ "la_input[64]",
+ "la_input[63]",
+ "la_input[48]",
+ "la_input[45]",
+ "la_input[47]",
+ "la_input[46]",
+ "la_input[44]",
+ "la_input[43]",
+ "la_input[32]",
+ "la_input[30]",
+ "la_input[29]",
+ "la_input[31]",
+ "la_input[101]",
+ "la_input[99]",
+ "la_input[98]",
+ "la_input[97]",
+ "la_input[100]",
+ "la_input[37]",
+ "la_input[38]",
+ "la_input[35]",
+ "la_input[34]",
+ "la_input[36]",
+ "la_input[33]",
+ "la_input[77]",
+ "la_input[76]",
+ "la_input[75]",
+ "la_input[71]",
+ "la_input[74]",
+ "la_input[73]",
+ "la_input[72]",
+ "la_input[18]",
+ "la_input[17]",
+ "la_input[16]",
+ "la_input[15]",
+ "la_input[14]",
+ "la_input[13]",
+ "la_input[11]",
+ "la_input[12]",
+ "la_input[10]",
+ "la_input[103]",
+ "la_input[106]",
+ "la_input[104]",
+ "la_input[105]",
+ "la_input[102]",
+ "la_input[96]",
+ "la_input[90]",
+ "la_input[88]",
+ "la_input[86]",
+ "la_input[85]",
+ "la_input[84]",
+ "la_input[82]",
+ "la_input[80]",
+ "la_input[83]",
+ "la_input[81]",
+ "la_input[79]",
+ "la_input[78]",
+ "la_input[50]",
+ "la_input[54]",
+ "la_input[53]",
+ "la_input[51]",
+ "la_input[52]",
+ "la_input[27]",
+ "la_input[28]",
+ "la_input[26]",
+ "la_input[25]",
+ "la_input[24]",
+ "la_input[23]",
+ "la_input[22]",
+ "la_input[21]",
+ "la_input[20]",
+ "la_input[19]",
+ "resetn_in",
+ "clk_in",
+ "mprj_dat_i[21]",
+ "core_clk",
+ "hk_dat_i[1]",
+ "hk_dat_i[2]",
+ "hk_dat_i[6]",
+ "hk_dat_i[17]",
+ "hk_dat_i[15]",
+ "hk_dat_i[4]",
+ "hk_dat_i[9]",
+ "hk_dat_i[0]",
+ "hk_ack_i",
+ "hk_dat_i[13]",
+ "hk_dat_i[12]",
+ "hk_dat_i[11]",
+ "hk_dat_i[18]",
+ "hk_dat_i[16]",
+ "hk_dat_i[14]",
+ "hk_dat_i[19]",
+ "hk_dat_i[20]",
+ "hk_dat_i[22]",
+ "hk_dat_i[21]",
+ "hk_dat_i[23]",
+ "la_input[60]",
+ "la_input[59]",
+ "la_input[61]",
+ "la_input[62]",
+ "la_input[122]",
+ "la_input[120]",
+ "la_input[119]",
+ "la_input[124]",
+ "la_input[121]",
+ "la_input[123]",
+ "la_input[125]",
+ "la_input[127]",
+ "la_input[126]",
+ "la_input[9]",
+ "la_input[8]",
+ "la_input[5]",
+ "la_input[1]",
+ "la_input[4]",
+ "la_input[7]",
+ "la_input[6]",
+ "la_input[2]",
+ "la_input[3]",
+ "la_input[0]",
+ "la_input[109]",
+ "la_input[112]",
+ "la_input[115]",
+ "la_input[108]",
+ "la_input[113]",
+ "la_input[110]",
+ "la_input[114]",
+ "la_input[111]",
+ "la_input[116]",
+ "la_input[117]",
+ "hk_dat_i[30]",
+ "hk_dat_i[29]",
+ "hk_dat_i[31]",
+ "hk_dat_i[24]",
+ "hk_dat_i[27]",
+ "hk_dat_i[25]",
+ "hk_dat_i[28]",
+ "hk_dat_i[26]",
+ "hk_dat_i[8]",
+ "hk_dat_i[10]",
+ "hk_dat_i[5]",
+ "hk_dat_i[3]",
+ "hk_dat_i[7]",
+ "VGND",
+ "VPWR",
+ "flash_io0_di",
+ "flash_io2_di",
+ "flash_io3_di"
+ ], [
+ "flash_io3_oeb",
+ "flash_io2_oeb",
+ "flash_io1_oeb",
+ "mprj_adr_o[0]",
+ "flash_io3_do",
+ "flash_io2_do",
+ "flash_io1_do",
+ "debug_out",
+ "trap",
+ "qspi_enabled",
+ "mprj_adr_o[1]",
+ "mprj_we_o",
+ "mprj_adr_o[29]",
+ "mprj_adr_o[9]",
+ "mprj_adr_o[27]",
+ "mprj_adr_o[7]",
+ "mprj_adr_o[31]",
+ "mprj_adr_o[30]",
+ "mprj_adr_o[28]",
+ "mprj_adr_o[25]",
+ "mprj_adr_o[5]",
+ "mprj_adr_o[21]",
+ "mprj_adr_o[16]",
+ "mprj_adr_o[15]",
+ "mprj_adr_o[14]",
+ "mprj_adr_o[3]",
+ "mprj_adr_o[2]",
+ "mprj_adr_o[13]",
+ "mprj_adr_o[4]",
+ "mprj_adr_o[20]",
+ "mprj_adr_o[12]",
+ "mprj_adr_o[11]",
+ "mprj_dat_o[22]",
+ "la_output[91]",
+ "mprj_dat_o[31]",
+ "mprj_dat_o[21]",
+ "mprj_adr_o[10]",
+ "la_output[90]",
+ "mprj_dat_o[30]",
+ "mprj_dat_o[10]",
+ "la_output[9]",
+ "la_output[89]",
+ "mprj_dat_o[29]",
+ "mprj_dat_o[19]",
+ "mprj_adr_o[18]",
+ "mprj_dat_o[9]",
+ "mprj_dat_o[18]",
+ "mprj_dat_o[17]",
+ "mprj_dat_o[26]",
+ "mprj_dat_o[16]",
+ "mprj_dat_o[15]",
+ "mprj_dat_o[24]",
+ "mprj_dat_o[14]",
+ "spi_csb",
+ "mprj_dat_o[23]",
+ "la_output[23]",
+ "la_output[69]",
+ "la_output[29]",
+ "la_output[19]",
+ "la_output[78]",
+ "la_output[48]",
+ "la_output[88]",
+ "la_output[87]",
+ "la_output[67]",
+ "la_output[17]",
+ "la_output[26]",
+ "la_output[16]",
+ "la_output[85]",
+ "la_output[66]",
+ "la_output[65]",
+ "la_output[84]",
+ "la_output[64]",
+ "la_output[54]",
+ "la_output[24]",
+ "la_output[83]",
+ "la_output[75]",
+ "la_output[73]",
+ "la_output[63]",
+ "la_output[82]",
+ "la_output[77]",
+ "la_output[74]",
+ "la_output[72]",
+ "la_output[71]",
+ "la_output[70]",
+ "la_output[81]",
+ "la_output[79]",
+ "la_output[93]",
+ "la_output[92]",
+ "hk_stb_o",
+ "la_iena[12]",
+ "ser_tx",
+ "mprj_cyc_o",
+ "rstb_l_out",
+ "spi_sck",
+ "mprj_stb_o",
+ "mprj_sel_o[3]",
+ "mprj_sel_o[1]",
+ "mprj_sel_o[0]",
+ "serial_clock_out",
+ "serial_resetn_out",
+ "serial_load_out",
+ "serial_data_2_out",
+ "la_oenb[86]",
+ "la_oenb[121]",
+ "la_oenb[10]",
+ "flash_clk",
+ "hk_cyc_o",
+ "la_oenb[49]",
+ "la_oenb[15]",
+ "la_oenb[12]",
+ "gpio_outenb_pad",
+ "gpio_inenb_pad",
+ "la_oenb[90]",
+ "la_oenb[88]",
+ "la_oenb[85]",
+ "la_oenb[59]",
+ "la_oenb[54]",
+ "la_oenb[45]",
+ "la_oenb[39]",
+ "la_oenb[38]",
+ "la_oenb[13]",
+ "la_iena[35]",
+ "la_iena[13]",
+ "la_oenb[94]",
+ "la_oenb[55]",
+ "la_oenb[44]",
+ "la_iena[8]",
+ "la_iena[36]",
+ "la_iena[25]",
+ "la_iena[14]",
+ "la_oenb[93]",
+ "la_oenb[91]",
+ "la_oenb[87]",
+ "la_oenb[78]",
+ "la_oenb[32]",
+ "la_iena[86]",
+ "la_oenb[73]",
+ "la_oenb[41]",
+ "la_oenb[25]",
+ "la_iena[15]",
+ "la_oenb[8]",
+ "la_oenb[61]",
+ "la_oenb[58]",
+ "la_oenb[56]",
+ "la_oenb[53]",
+ "la_oenb[51]",
+ "la_oenb[52]",
+ "la_oenb[50]",
+ "la_oenb[43]",
+ "la_oenb[35]",
+ "la_oenb[37]",
+ "la_oenb[34]",
+ "la_oenb[33]",
+ "la_oenb[14]",
+ "la_iena[32]",
+ "mprj_dat_o[12]",
+ "mprj_adr_o[22]",
+ "la_output[111]",
+ "la_output[101]",
+ "mprj_dat_o[11]",
+ "la_output[110]",
+ "la_output[100]",
+ "mprj_sel_o[2]",
+ "mprj_dat_o[20]",
+ "la_output[8]",
+ "la_output[10]",
+ "la_output[0]",
+ "mprj_dat_o[2]",
+ "mprj_dat_o[1]",
+ "mprj_dat_o[0]",
+ "mprj_adr_o[19]",
+ "la_output[99]",
+ "la_output[109]",
+ "user_irq_ena[0]",
+ "la_output[98]",
+ "la_output[108]",
+ "mprj_dat_o[28]",
+ "mprj_adr_o[17]",
+ "la_output[97]",
+ "la_output[107]",
+ "mprj_dat_o[8]",
+ "mprj_dat_o[27]",
+ "mprj_adr_o[8]",
+ "la_output[106]",
+ "spi_sdo",
+ "mprj_dat_o[7]",
+ "mprj_adr_o[26]",
+ "la_output[105]",
+ "mprj_dat_o[6]",
+ "mprj_dat_o[25]",
+ "mprj_adr_o[6]",
+ "la_output[104]",
+ "spi_enabled",
+ "mprj_dat_o[5]",
+ "la_output[103]",
+ "mprj_wb_iena",
+ "mprj_dat_o[4]",
+ "mprj_dat_o[3]",
+ "la_output[120]",
+ "la_output[14]",
+ "la_output[11]",
+ "la_output[13]",
+ "la_output[119]",
+ "la_output[32]",
+ "la_output[22]",
+ "la_output[12]",
+ "la_output[118]",
+ "la_output[41]",
+ "la_output[31]",
+ "la_output[21]",
+ "la_output[127]",
+ "la_output[117]",
+ "la_output[50]",
+ "la_output[30]",
+ "la_output[20]",
+ "la_output[126]",
+ "la_output[5]",
+ "la_output[4]",
+ "la_output[3]",
+ "la_output[2]",
+ "la_output[1]",
+ "la_output[125]",
+ "la_output[115]",
+ "la_output[49]",
+ "la_output[39]",
+ "la_output[124]",
+ "la_output[116]",
+ "la_output[114]",
+ "la_output[58]",
+ "la_output[38]",
+ "la_output[18]",
+ "la_output[123]",
+ "la_output[113]",
+ "la_output[57]",
+ "la_output[47]",
+ "la_output[37]",
+ "la_output[27]",
+ "la_output[122]",
+ "la_output[112]",
+ "la_output[86]",
+ "la_output[76]",
+ "la_output[68]",
+ "la_output[59]",
+ "la_output[56]",
+ "la_output[46]",
+ "la_output[36]",
+ "la_output[121]",
+ "la_output[55]",
+ "la_output[45]",
+ "la_output[35]",
+ "la_output[28]",
+ "la_output[25]",
+ "la_output[15]",
+ "la_output[44]",
+ "la_output[34]",
+ "user_irq_ena[2]",
+ "user_irq_ena[1]",
+ "la_output[53]",
+ "la_output[43]",
+ "la_output[33]",
+ "la_output[62]",
+ "la_output[52]",
+ "la_output[42]",
+ "la_output[40]",
+ "la_output[61]",
+ "la_output[51]",
+ "debug_oeb",
+ "la_output[80]",
+ "la_output[60]",
+ "debug_mode",
+ "la_output[7]",
+ "la_output[6]",
+ "gpio_out_pad",
+ "gpio_mode1_pad",
+ "la_output[96]",
+ "gpio_mode0_pad",
+ "la_output[95]",
+ "la_output[94]",
+ "mprj_adr_o[24]",
+ "mprj_dat_o[13]",
+ "mprj_adr_o[23]",
+ "la_output[102]",
+ "uart_enabled",
+ "porb_h_out",
+ "por_l_out",
+ "resetn_out",
+ "clk_out",
+ "flash_io0_oeb",
+ "flash_io0_do",
+ "la_oenb[99]",
+ "la_oenb[98]",
+ "la_oenb[97]",
+ "la_oenb[96]",
+ "la_oenb[95]",
+ "la_oenb[7]",
+ "la_oenb[71]",
+ "la_oenb[70]",
+ "la_oenb[6]",
+ "la_oenb[66]",
+ "la_oenb[60]",
+ "la_oenb[5]",
+ "la_oenb[57]",
+ "la_oenb[4]",
+ "la_oenb[42]",
+ "la_oenb[40]",
+ "la_oenb[46]",
+ "la_oenb[3]",
+ "la_oenb[31]",
+ "la_oenb[30]",
+ "la_oenb[2]",
+ "la_oenb[28]",
+ "la_oenb[22]",
+ "la_oenb[1]",
+ "la_oenb[16]",
+ "la_oenb[127]",
+ "la_oenb[126]",
+ "la_oenb[125]",
+ "la_oenb[124]",
+ "la_oenb[123]",
+ "la_oenb[122]",
+ "la_oenb[120]",
+ "la_oenb[119]",
+ "la_oenb[117]",
+ "la_oenb[116]",
+ "la_oenb[115]",
+ "la_oenb[114]",
+ "la_oenb[113]",
+ "la_oenb[111]",
+ "la_oenb[110]",
+ "la_oenb[109]",
+ "la_oenb[107]",
+ "la_oenb[106]",
+ "la_oenb[105]",
+ "la_oenb[104]",
+ "la_oenb[103]",
+ "la_oenb[102]",
+ "la_oenb[101]",
+ "la_oenb[100]",
+ "la_oenb[0]",
+ "la_iena[9]",
+ "la_iena[99]",
+ "la_iena[98]",
+ "la_iena[97]",
+ "la_iena[96]",
+ "la_iena[7]",
+ "la_iena[6]",
+ "la_iena[61]",
+ "la_iena[60]",
+ "la_iena[5]",
+ "la_iena[59]",
+ "la_iena[58]",
+ "la_iena[57]",
+ "la_iena[56]",
+ "la_iena[55]",
+ "la_iena[53]",
+ "la_iena[52]",
+ "la_iena[51]",
+ "la_iena[50]",
+ "la_iena[4]",
+ "la_iena[47]",
+ "la_iena[45]",
+ "la_iena[44]",
+ "la_iena[43]",
+ "la_iena[42]",
+ "la_iena[49]",
+ "la_iena[41]",
+ "la_iena[39]",
+ "la_iena[38]",
+ "la_iena[37]",
+ "la_iena[34]",
+ "la_iena[33]",
+ "la_iena[31]",
+ "la_iena[30]",
+ "la_iena[3]",
+ "la_iena[2]",
+ "la_iena[29]",
+ "la_iena[28]",
+ "la_iena[22]",
+ "la_iena[1]",
+ "la_iena[127]",
+ "la_iena[126]",
+ "la_iena[125]",
+ "la_iena[124]",
+ "la_iena[123]",
+ "la_iena[122]",
+ "la_iena[121]",
+ "la_iena[120]",
+ "la_iena[11]",
+ "la_iena[119]",
+ "la_iena[117]",
+ "la_iena[116]",
+ "la_iena[115]",
+ "la_iena[114]",
+ "la_iena[113]",
+ "la_iena[111]",
+ "la_iena[110]",
+ "la_iena[10]",
+ "la_iena[109]",
+ "la_iena[107]",
+ "la_iena[106]",
+ "la_iena[105]",
+ "la_iena[104]",
+ "la_iena[103]",
+ "la_iena[102]",
+ "la_iena[101]",
+ "la_iena[100]",
+ "la_iena[0]",
+ "flash_csb",
+ "spi_sdoenb",
+ "la_oenb[9]",
+ "la_oenb[92]",
+ "la_oenb[89]",
+ "la_oenb[84]",
+ "la_oenb[83]",
+ "la_oenb[82]",
+ "la_oenb[81]",
+ "la_oenb[80]",
+ "la_oenb[79]",
+ "la_oenb[77]",
+ "la_oenb[76]",
+ "la_oenb[75]",
+ "la_oenb[74]",
+ "la_oenb[72]",
+ "la_oenb[69]",
+ "la_oenb[68]",
+ "la_oenb[67]",
+ "la_oenb[65]",
+ "la_oenb[64]",
+ "la_oenb[63]",
+ "la_oenb[62]",
+ "la_oenb[48]",
+ "la_oenb[47]",
+ "la_oenb[36]",
+ "la_oenb[29]",
+ "la_oenb[26]",
+ "la_oenb[24]",
+ "la_oenb[27]",
+ "la_oenb[23]",
+ "la_oenb[21]",
+ "la_oenb[20]",
+ "la_oenb[19]",
+ "la_oenb[18]",
+ "la_oenb[17]",
+ "la_oenb[11]",
+ "la_oenb[118]",
+ "la_oenb[112]",
+ "la_oenb[108]",
+ "la_iena[95]",
+ "la_iena[94]",
+ "la_iena[92]",
+ "la_iena[93]",
+ "la_iena[91]",
+ "la_iena[90]",
+ "la_iena[89]",
+ "la_iena[88]",
+ "la_iena[87]",
+ "la_iena[85]",
+ "la_iena[84]",
+ "la_iena[83]",
+ "la_iena[82]",
+ "la_iena[81]",
+ "la_iena[80]",
+ "la_iena[79]",
+ "la_iena[78]",
+ "la_iena[76]",
+ "la_iena[75]",
+ "la_iena[73]",
+ "la_iena[77]",
+ "la_iena[74]",
+ "la_iena[72]",
+ "la_iena[71]",
+ "la_iena[70]",
+ "la_iena[69]",
+ "la_iena[68]",
+ "la_iena[67]",
+ "la_iena[66]",
+ "la_iena[65]",
+ "la_iena[64]",
+ "la_iena[63]",
+ "la_iena[62]",
+ "la_iena[54]",
+ "la_iena[48]",
+ "la_iena[46]",
+ "la_iena[40]",
+ "la_iena[26]",
+ "la_iena[24]",
+ "la_iena[23]",
+ "la_iena[27]",
+ "la_iena[21]",
+ "la_iena[20]",
+ "la_iena[18]",
+ "la_iena[19]",
+ "la_iena[17]",
+ "la_iena[16]",
+ "la_iena[118]",
+ "la_iena[112]",
+ "la_iena[108]",
+ "spi_sdi",
+ "serial_resetn_in",
+ "serial_clock_in",
+ "serial_load_in",
+ "serial_data_2_in",
+ "ser_rx",
+ "por_l_in",
+ "porb_h_in",
+ "mprj_dat_i[6]",
+ "mprj_dat_i[2]",
+ "mprj_dat_i[24]",
+ "mprj_dat_i[4]",
+ "mprj_dat_i[1]",
+ "mprj_ack_i",
+ "mprj_dat_i[0]",
+ "mprj_dat_i[9]",
+ "la_input[94]",
+ "la_input[93]",
+ "mprj_dat_i[31]",
+ "mprj_dat_i[30]",
+ "mprj_dat_i[29]",
+ "la_input[118]",
+ "la_input[91]",
+ "la_input[89]",
+ "la_input[87]",
+ "mprj_dat_i[16]",
+ "irq[0]",
+ "mprj_dat_i[20]",
+ "mprj_dat_i[19]",
+ "mprj_dat_i[10]",
+ "mprj_dat_i[15]",
+ "gpio_in_pad",
+ "mprj_dat_i[18]",
+ "mprj_dat_i[13]",
+ "la_input[95]",
+ "mprj_dat_i[7]",
+ "mprj_dat_i[5]",
+ "mprj_dat_i[3]",
+ "mprj_dat_i[14]",
+ "mprj_dat_i[8]",
+ "mprj_dat_i[12]",
+ "mprj_dat_i[11]",
+ "la_input[92]",
+ "mprj_dat_i[28]",
+ "mprj_dat_i[27]",
+ "mprj_dat_i[26]",
+ "mprj_dat_i[25]",
+ "mprj_dat_i[23]",
+ "mprj_dat_i[22]",
+ "mprj_dat_i[17]",
+ "debug_in",
+ "rstb_l_in",
+ "irq[2]",
+ "irq[1]",
+ "core_rstn",
+ "flash_io1_di",
+ "la_input[42]",
+ "la_input[41]",
+ "la_input[40]",
+ "la_input[39]",
+ "irq[4]",
+ "irq[5]",
+ "irq[3]",
+ "la_input[49]",
+ "la_input[70]",
+ "la_input[69]",
+ "la_input[68]",
+ "la_input[107]",
+ "la_input[56]",
+ "la_input[58]",
+ "la_input[55]",
+ "la_input[57]",
+ "la_input[66]",
+ "la_input[65]",
+ "la_input[67]",
+ "la_input[64]",
+ "la_input[63]",
+ "la_input[48]",
+ "la_input[45]",
+ "la_input[47]",
+ "la_input[46]",
+ "la_input[44]",
+ "la_input[43]",
+ "la_input[32]",
+ "la_input[30]",
+ "la_input[29]",
+ "la_input[31]",
+ "la_input[101]",
+ "la_input[99]",
+ "la_input[98]",
+ "la_input[97]",
+ "la_input[100]",
+ "la_input[37]",
+ "la_input[38]",
+ "la_input[35]",
+ "la_input[34]",
+ "la_input[36]",
+ "la_input[33]",
+ "la_input[77]",
+ "la_input[76]",
+ "la_input[75]",
+ "la_input[71]",
+ "la_input[74]",
+ "la_input[73]",
+ "la_input[72]",
+ "la_input[18]",
+ "la_input[17]",
+ "la_input[16]",
+ "la_input[15]",
+ "la_input[14]",
+ "la_input[13]",
+ "la_input[11]",
+ "la_input[12]",
+ "la_input[10]",
+ "la_input[103]",
+ "la_input[106]",
+ "la_input[104]",
+ "la_input[105]",
+ "la_input[102]",
+ "la_input[96]",
+ "la_input[90]",
+ "la_input[88]",
+ "la_input[86]",
+ "la_input[85]",
+ "la_input[84]",
+ "la_input[82]",
+ "la_input[80]",
+ "la_input[83]",
+ "la_input[81]",
+ "la_input[79]",
+ "la_input[78]",
+ "la_input[50]",
+ "la_input[54]",
+ "la_input[53]",
+ "la_input[51]",
+ "la_input[52]",
+ "la_input[27]",
+ "la_input[28]",
+ "la_input[26]",
+ "la_input[25]",
+ "la_input[24]",
+ "la_input[23]",
+ "la_input[22]",
+ "la_input[21]",
+ "la_input[20]",
+ "la_input[19]",
+ "resetn_in",
+ "clk_in",
+ "mprj_dat_i[21]",
+ "core_clk",
+ "hk_dat_i[1]",
+ "hk_dat_i[2]",
+ "hk_dat_i[6]",
+ "hk_dat_i[17]",
+ "hk_dat_i[15]",
+ "hk_dat_i[4]",
+ "hk_dat_i[9]",
+ "hk_dat_i[0]",
+ "hk_ack_i",
+ "hk_dat_i[13]",
+ "hk_dat_i[12]",
+ "hk_dat_i[11]",
+ "hk_dat_i[18]",
+ "hk_dat_i[16]",
+ "hk_dat_i[14]",
+ "hk_dat_i[19]",
+ "hk_dat_i[20]",
+ "hk_dat_i[22]",
+ "hk_dat_i[21]",
+ "hk_dat_i[23]",
+ "la_input[60]",
+ "la_input[59]",
+ "la_input[61]",
+ "la_input[62]",
+ "la_input[122]",
+ "la_input[120]",
+ "la_input[119]",
+ "la_input[124]",
+ "la_input[121]",
+ "la_input[123]",
+ "la_input[125]",
+ "la_input[127]",
+ "la_input[126]",
+ "la_input[9]",
+ "la_input[8]",
+ "la_input[5]",
+ "la_input[1]",
+ "la_input[4]",
+ "la_input[7]",
+ "la_input[6]",
+ "la_input[2]",
+ "la_input[3]",
+ "la_input[0]",
+ "la_input[109]",
+ "la_input[112]",
+ "la_input[115]",
+ "la_input[108]",
+ "la_input[113]",
+ "la_input[110]",
+ "la_input[114]",
+ "la_input[111]",
+ "la_input[116]",
+ "la_input[117]",
+ "hk_dat_i[30]",
+ "hk_dat_i[29]",
+ "hk_dat_i[31]",
+ "hk_dat_i[24]",
+ "hk_dat_i[27]",
+ "hk_dat_i[25]",
+ "hk_dat_i[28]",
+ "hk_dat_i[26]",
+ "hk_dat_i[8]",
+ "hk_dat_i[10]",
+ "hk_dat_i[5]",
+ "hk_dat_i[3]",
+ "hk_dat_i[7]",
+ "VGND",
+ "VPWR",
+ "flash_io0_di",
+ "flash_io2_di",
+ "flash_io3_di"
+ ]
+ ]
+ }
+]
diff --git a/signoff/mgmt_core_wrapper/standalone_pvr/eco-mgmt_core_wrapper.lvs.report b/signoff/mgmt_core_wrapper/standalone_pvr/eco-mgmt_core_wrapper.lvs.report
new file mode 100644
index 0000000..25fe8a7
--- /dev/null
+++ b/signoff/mgmt_core_wrapper/standalone_pvr/eco-mgmt_core_wrapper.lvs.report
@@ -0,0 +1,7604 @@
+
+Circuit 1 cell sky130_fd_pr__pfet_01v8_hvt and Circuit 2 cell sky130_fd_pr__pfet_01v8_hvt are black boxes.
+
+Subcircuit pins:
+Circuit 1: sky130_fd_pr__pfet_01v8_hvt |Circuit 2: sky130_fd_pr__pfet_01v8_hvt
+-------------------------------------------|-------------------------------------------
+1 |1
+2 |2
+3 |3
+4 |4
+---------------------------------------------------------------------------------------
+Cell pin lists are equivalent.
+Device classes sky130_fd_pr__pfet_01v8_hvt and sky130_fd_pr__pfet_01v8_hvt are equivalent.
+
+Circuit 1 cell sky130_fd_pr__nfet_01v8 and Circuit 2 cell sky130_fd_pr__nfet_01v8 are black boxes.
+
+Subcircuit pins:
+Circuit 1: sky130_fd_pr__nfet_01v8 |Circuit 2: sky130_fd_pr__nfet_01v8
+-------------------------------------------|-------------------------------------------
+1 |1
+2 |2
+3 |3
+4 |4
+---------------------------------------------------------------------------------------
+Cell pin lists are equivalent.
+Device classes sky130_fd_pr__nfet_01v8 and sky130_fd_pr__nfet_01v8 are equivalent.
+
+Class sky130_fd_sc_hd__ebufn_2 (0): Merged 4 parallel devices.
+Class sky130_fd_sc_hd__ebufn_2 (1): Merged 4 parallel devices.
+Subcircuit summary:
+Circuit 1: sky130_fd_sc_hd__ebufn_2 |Circuit 2: sky130_fd_sc_hd__ebufn_2
+-------------------------------------------|-------------------------------------------
+sky130_fd_pr__pfet_01v8_hvt (6->4) |sky130_fd_pr__pfet_01v8_hvt (6->4)
+sky130_fd_pr__nfet_01v8 (6->4) |sky130_fd_pr__nfet_01v8 (6->4)
+Number of devices: 8 |Number of devices: 8
+Number of nets: 11 |Number of nets: 11
+---------------------------------------------------------------------------------------
+Netlists match uniquely.
+
+Subcircuit pins:
+Circuit 1: sky130_fd_sc_hd__ebufn_2 |Circuit 2: sky130_fd_sc_hd__ebufn_2
+-------------------------------------------|-------------------------------------------
+VGND |VGND
+TE_B |TE_B
+VPWR |VPWR
+VNB |VNB
+VPB |VPB
+Z |Z
+A |A
+---------------------------------------------------------------------------------------
+Cell pin lists are equivalent.
+Device classes sky130_fd_sc_hd__ebufn_2 and sky130_fd_sc_hd__ebufn_2 are equivalent.
+
+Subcircuit summary:
+Circuit 1: sky130_fd_sc_hd__dlclkp_1 |Circuit 2: sky130_fd_sc_hd__dlclkp_1
+-------------------------------------------|-------------------------------------------
+sky130_fd_pr__pfet_01v8_hvt (10) |sky130_fd_pr__pfet_01v8_hvt (10)
+sky130_fd_pr__nfet_01v8 (10) |sky130_fd_pr__nfet_01v8 (10)
+Number of devices: 20 |Number of devices: 20
+Number of nets: 17 |Number of nets: 17
+---------------------------------------------------------------------------------------
+Netlists match uniquely.
+
+Subcircuit pins:
+Circuit 1: sky130_fd_sc_hd__dlclkp_1 |Circuit 2: sky130_fd_sc_hd__dlclkp_1
+-------------------------------------------|-------------------------------------------
+VGND |VGND
+CLK |CLK
+VPB |VPB
+VNB |VNB
+VPWR |VPWR
+GCLK |GCLK
+GATE |GATE
+---------------------------------------------------------------------------------------
+Cell pin lists are equivalent.
+Device classes sky130_fd_sc_hd__dlclkp_1 and sky130_fd_sc_hd__dlclkp_1 are equivalent.
+
+Class sky130_fd_sc_hd__clkbuf_4 (0): Merged 6 parallel devices.
+Class sky130_fd_sc_hd__clkbuf_4 (1): Merged 6 parallel devices.
+Subcircuit summary:
+Circuit 1: sky130_fd_sc_hd__clkbuf_4 |Circuit 2: sky130_fd_sc_hd__clkbuf_4
+-------------------------------------------|-------------------------------------------
+sky130_fd_pr__pfet_01v8_hvt (5->2) |sky130_fd_pr__pfet_01v8_hvt (5->2)
+sky130_fd_pr__nfet_01v8 (5->2) |sky130_fd_pr__nfet_01v8 (5->2)
+Number of devices: 4 |Number of devices: 4
+Number of nets: 7 |Number of nets: 7
+---------------------------------------------------------------------------------------
+Netlists match uniquely.
+
+Subcircuit pins:
+Circuit 1: sky130_fd_sc_hd__clkbuf_4 |Circuit 2: sky130_fd_sc_hd__clkbuf_4
+-------------------------------------------|-------------------------------------------
+VPWR |VPWR
+X |X
+VPB |VPB
+A |A
+VGND |VGND
+VNB |VNB
+---------------------------------------------------------------------------------------
+Cell pin lists are equivalent.
+Device classes sky130_fd_sc_hd__clkbuf_4 and sky130_fd_sc_hd__clkbuf_4 are equivalent.
+
+Subcircuit summary:
+Circuit 1: sky130_fd_sc_hd__dlxtp_1 |Circuit 2: sky130_fd_sc_hd__dlxtp_1
+-------------------------------------------|-------------------------------------------
+sky130_fd_pr__nfet_01v8 (9) |sky130_fd_pr__nfet_01v8 (9)
+sky130_fd_pr__pfet_01v8_hvt (9) |sky130_fd_pr__pfet_01v8_hvt (9)
+Number of devices: 18 |Number of devices: 18
+Number of nets: 16 |Number of nets: 16
+---------------------------------------------------------------------------------------
+Netlists match uniquely.
+
+Subcircuit pins:
+Circuit 1: sky130_fd_sc_hd__dlxtp_1 |Circuit 2: sky130_fd_sc_hd__dlxtp_1
+-------------------------------------------|-------------------------------------------
+VPWR |VPWR
+VGND |VGND
+VPB |VPB
+VNB |VNB
+D |D
+Q |Q
+GATE |GATE
+---------------------------------------------------------------------------------------
+Cell pin lists are equivalent.
+Device classes sky130_fd_sc_hd__dlxtp_1 and sky130_fd_sc_hd__dlxtp_1 are equivalent.
+
+Class sky130_fd_sc_hd__and4bb_2 (0): Merged 2 parallel devices.
+Class sky130_fd_sc_hd__and4bb_2 (1): Merged 2 parallel devices.
+Subcircuit summary:
+Circuit 1: sky130_fd_sc_hd__and4bb_2 |Circuit 2: sky130_fd_sc_hd__and4bb_2
+-------------------------------------------|-------------------------------------------
+sky130_fd_pr__pfet_01v8_hvt (8->7) |sky130_fd_pr__pfet_01v8_hvt (8->7)
+sky130_fd_pr__nfet_01v8 (8->7) |sky130_fd_pr__nfet_01v8 (8->7)
+Number of devices: 14 |Number of devices: 14
+Number of nets: 15 |Number of nets: 15
+---------------------------------------------------------------------------------------
+Netlists match uniquely.
+
+Subcircuit pins:
+Circuit 1: sky130_fd_sc_hd__and4bb_2 |Circuit 2: sky130_fd_sc_hd__and4bb_2
+-------------------------------------------|-------------------------------------------
+VGND |VGND
+X |X
+D |D
+C |C
+B_N |B_N
+A_N |A_N
+VNB |VNB
+VPWR |VPWR
+VPB |VPB
+---------------------------------------------------------------------------------------
+Cell pin lists are equivalent.
+Device classes sky130_fd_sc_hd__and4bb_2 and sky130_fd_sc_hd__and4bb_2 are equivalent.
+
+Subcircuit summary:
+Circuit 1: sky130_fd_sc_hd__inv_1 |Circuit 2: sky130_fd_sc_hd__inv_1
+-------------------------------------------|-------------------------------------------
+sky130_fd_pr__nfet_01v8 (1) |sky130_fd_pr__nfet_01v8 (1)
+sky130_fd_pr__pfet_01v8_hvt (1) |sky130_fd_pr__pfet_01v8_hvt (1)
+Number of devices: 2 |Number of devices: 2
+Number of nets: 6 |Number of nets: 6
+---------------------------------------------------------------------------------------
+Netlists match uniquely.
+
+Subcircuit pins:
+Circuit 1: sky130_fd_sc_hd__inv_1 |Circuit 2: sky130_fd_sc_hd__inv_1
+-------------------------------------------|-------------------------------------------
+VGND |VGND
+VNB |VNB
+VPWR |VPWR
+VPB |VPB
+A |A
+Y |Y
+---------------------------------------------------------------------------------------
+Cell pin lists are equivalent.
+Device classes sky130_fd_sc_hd__inv_1 and sky130_fd_sc_hd__inv_1 are equivalent.
+
+Subcircuit summary:
+Circuit 1: sky130_fd_sc_hd__dfxtp_1 |Circuit 2: sky130_fd_sc_hd__dfxtp_1
+-------------------------------------------|-------------------------------------------
+sky130_fd_pr__nfet_01v8 (12) |sky130_fd_pr__nfet_01v8 (12)
+sky130_fd_pr__pfet_01v8_hvt (12) |sky130_fd_pr__pfet_01v8_hvt (12)
+Number of devices: 24 |Number of devices: 24
+Number of nets: 18 |Number of nets: 18
+---------------------------------------------------------------------------------------
+Netlists match uniquely.
+
+Subcircuit pins:
+Circuit 1: sky130_fd_sc_hd__dfxtp_1 |Circuit 2: sky130_fd_sc_hd__dfxtp_1
+-------------------------------------------|-------------------------------------------
+VPB |VPB
+VNB |VNB
+VGND |VGND
+VPWR |VPWR
+D |D
+Q |Q
+CLK |CLK
+---------------------------------------------------------------------------------------
+Cell pin lists are equivalent.
+Device classes sky130_fd_sc_hd__dfxtp_1 and sky130_fd_sc_hd__dfxtp_1 are equivalent.
+
+Subcircuit summary:
+Circuit 1: sky130_fd_sc_hd__and2_1 |Circuit 2: sky130_fd_sc_hd__and2_1
+-------------------------------------------|-------------------------------------------
+sky130_fd_pr__pfet_01v8_hvt (3) |sky130_fd_pr__pfet_01v8_hvt (3)
+sky130_fd_pr__nfet_01v8 (3) |sky130_fd_pr__nfet_01v8 (3)
+Number of devices: 6 |Number of devices: 6
+Number of nets: 9 |Number of nets: 9
+---------------------------------------------------------------------------------------
+Netlists match uniquely.
+
+Subcircuit pins:
+Circuit 1: sky130_fd_sc_hd__and2_1 |Circuit 2: sky130_fd_sc_hd__and2_1
+-------------------------------------------|-------------------------------------------
+VGND |VGND
+X |X
+A |A
+B |B
+VNB |VNB
+VPWR |VPWR
+VPB |VPB
+---------------------------------------------------------------------------------------
+Cell pin lists are equivalent.
+Device classes sky130_fd_sc_hd__and2_1 and sky130_fd_sc_hd__and2_1 are equivalent.
+
+Cell sky130_fd_sc_hd__diode_2 (0) disconnected node: VGND
+Cell sky130_fd_sc_hd__diode_2 (0) disconnected node: VPWR
+Cell sky130_fd_sc_hd__diode_2 (0) disconnected node: VPB
+Cell sky130_fd_sc_hd__diode_2 (1) disconnected node: VGND
+Cell sky130_fd_sc_hd__diode_2 (1) disconnected node: VPB
+Cell sky130_fd_sc_hd__diode_2 (1) disconnected node: VPWR
+Subcircuit summary:
+Circuit 1: sky130_fd_sc_hd__diode_2 |Circuit 2: sky130_fd_sc_hd__diode_2
+-------------------------------------------|-------------------------------------------
+sky130_fd_pr__diode_pw2nd_05v5 (1) |sky130_fd_pr__diode_pw2nd_05v5 (1)
+Number of devices: 1 |Number of devices: 1
+Number of nets: 2 |Number of nets: 2
+---------------------------------------------------------------------------------------
+Netlists match uniquely.
+
+Subcircuit pins:
+Circuit 1: sky130_fd_sc_hd__diode_2 |Circuit 2: sky130_fd_sc_hd__diode_2
+-------------------------------------------|-------------------------------------------
+VNB |VNB
+DIODE |DIODE
+VGND |VGND
+VPWR |VPWR
+VPB |VPB
+---------------------------------------------------------------------------------------
+Cell pin lists are equivalent.
+Device classes sky130_fd_sc_hd__diode_2 and sky130_fd_sc_hd__diode_2 are equivalent.
+
+Subcircuit summary:
+Circuit 1: sky130_fd_sc_hd__decap_12 |Circuit 2: sky130_fd_sc_hd__decap_12
+-------------------------------------------|-------------------------------------------
+sky130_fd_pr__pfet_01v8_hvt (1) |sky130_fd_pr__pfet_01v8_hvt (1)
+sky130_fd_pr__nfet_01v8 (1) |sky130_fd_pr__nfet_01v8 (1)
+Number of devices: 2 |Number of devices: 2
+Number of nets: 4 |Number of nets: 4
+---------------------------------------------------------------------------------------
+Netlists match uniquely.
+
+Subcircuit pins:
+Circuit 1: sky130_fd_sc_hd__decap_12 |Circuit 2: sky130_fd_sc_hd__decap_12
+-------------------------------------------|-------------------------------------------
+VPB |VPB
+VNB |VNB
+VPWR |VPWR
+VGND |VGND
+---------------------------------------------------------------------------------------
+Cell pin lists are equivalent.
+Device classes sky130_fd_sc_hd__decap_12 and sky130_fd_sc_hd__decap_12 are equivalent.
+
+Subcircuit summary:
+Circuit 1: sky130_fd_sc_hd__decap_8 |Circuit 2: sky130_fd_sc_hd__decap_8
+-------------------------------------------|-------------------------------------------
+sky130_fd_pr__pfet_01v8_hvt (1) |sky130_fd_pr__pfet_01v8_hvt (1)
+sky130_fd_pr__nfet_01v8 (1) |sky130_fd_pr__nfet_01v8 (1)
+Number of devices: 2 |Number of devices: 2
+Number of nets: 4 |Number of nets: 4
+---------------------------------------------------------------------------------------
+Netlists match uniquely.
+
+Subcircuit pins:
+Circuit 1: sky130_fd_sc_hd__decap_8 |Circuit 2: sky130_fd_sc_hd__decap_8
+-------------------------------------------|-------------------------------------------
+VPB |VPB
+VNB |VNB
+VPWR |VPWR
+VGND |VGND
+---------------------------------------------------------------------------------------
+Cell pin lists are equivalent.
+Device classes sky130_fd_sc_hd__decap_8 and sky130_fd_sc_hd__decap_8 are equivalent.
+
+Class sky130_fd_sc_hd__clkbuf_2 (0): Merged 2 parallel devices.
+Class sky130_fd_sc_hd__clkbuf_2 (1): Merged 2 parallel devices.
+Subcircuit summary:
+Circuit 1: sky130_fd_sc_hd__clkbuf_2 |Circuit 2: sky130_fd_sc_hd__clkbuf_2
+-------------------------------------------|-------------------------------------------
+sky130_fd_pr__pfet_01v8_hvt (3->2) |sky130_fd_pr__pfet_01v8_hvt (3->2)
+sky130_fd_pr__nfet_01v8 (3->2) |sky130_fd_pr__nfet_01v8 (3->2)
+Number of devices: 4 |Number of devices: 4
+Number of nets: 7 |Number of nets: 7
+---------------------------------------------------------------------------------------
+Netlists match uniquely.
+
+Subcircuit pins:
+Circuit 1: sky130_fd_sc_hd__clkbuf_2 |Circuit 2: sky130_fd_sc_hd__clkbuf_2
+-------------------------------------------|-------------------------------------------
+A |A
+VPWR |VPWR
+VPB |VPB
+VGND |VGND
+VNB |VNB
+X |X
+---------------------------------------------------------------------------------------
+Cell pin lists are equivalent.
+Device classes sky130_fd_sc_hd__clkbuf_2 and sky130_fd_sc_hd__clkbuf_2 are equivalent.
+
+Class sky130_fd_sc_hd__clkbuf_16 (0): Merged 36 parallel devices.
+Class sky130_fd_sc_hd__clkbuf_16 (1): Merged 36 parallel devices.
+Subcircuit summary:
+Circuit 1: sky130_fd_sc_hd__clkbuf_16 |Circuit 2: sky130_fd_sc_hd__clkbuf_16
+-------------------------------------------|-------------------------------------------
+sky130_fd_pr__pfet_01v8_hvt (20->2) |sky130_fd_pr__pfet_01v8_hvt (20->2)
+sky130_fd_pr__nfet_01v8 (20->2) |sky130_fd_pr__nfet_01v8 (20->2)
+Number of devices: 4 |Number of devices: 4
+Number of nets: 7 |Number of nets: 7
+---------------------------------------------------------------------------------------
+Netlists match uniquely.
+
+Subcircuit pins:
+Circuit 1: sky130_fd_sc_hd__clkbuf_16 |Circuit 2: sky130_fd_sc_hd__clkbuf_16
+-------------------------------------------|-------------------------------------------
+VPWR |VPWR
+X |X
+VPB |VPB
+VGND |VGND
+VNB |VNB
+A |A
+---------------------------------------------------------------------------------------
+Cell pin lists are equivalent.
+Device classes sky130_fd_sc_hd__clkbuf_16 and sky130_fd_sc_hd__clkbuf_16 are equivalent.
+
+Subcircuit summary:
+Circuit 1: sky130_fd_sc_hd__decap_4 |Circuit 2: sky130_fd_sc_hd__decap_4
+-------------------------------------------|-------------------------------------------
+sky130_fd_pr__pfet_01v8_hvt (1) |sky130_fd_pr__pfet_01v8_hvt (1)
+sky130_fd_pr__nfet_01v8 (1) |sky130_fd_pr__nfet_01v8 (1)
+Number of devices: 2 |Number of devices: 2
+Number of nets: 4 |Number of nets: 4
+---------------------------------------------------------------------------------------
+Netlists match uniquely.
+
+Subcircuit pins:
+Circuit 1: sky130_fd_sc_hd__decap_4 |Circuit 2: sky130_fd_sc_hd__decap_4
+-------------------------------------------|-------------------------------------------
+VPB |VPB
+VNB |VNB
+VPWR |VPWR
+VGND |VGND
+---------------------------------------------------------------------------------------
+Cell pin lists are equivalent.
+Device classes sky130_fd_sc_hd__decap_4 and sky130_fd_sc_hd__decap_4 are equivalent.
+
+Subcircuit summary:
+Circuit 1: sky130_fd_sc_hd__decap_6 |Circuit 2: sky130_fd_sc_hd__decap_6
+-------------------------------------------|-------------------------------------------
+sky130_fd_pr__pfet_01v8_hvt (1) |sky130_fd_pr__pfet_01v8_hvt (1)
+sky130_fd_pr__nfet_01v8 (1) |sky130_fd_pr__nfet_01v8 (1)
+Number of devices: 2 |Number of devices: 2
+Number of nets: 4 |Number of nets: 4
+---------------------------------------------------------------------------------------
+Netlists match uniquely.
+
+Subcircuit pins:
+Circuit 1: sky130_fd_sc_hd__decap_6 |Circuit 2: sky130_fd_sc_hd__decap_6
+-------------------------------------------|-------------------------------------------
+VPB |VPB
+VNB |VNB
+VPWR |VPWR
+VGND |VGND
+---------------------------------------------------------------------------------------
+Cell pin lists are equivalent.
+Device classes sky130_fd_sc_hd__decap_6 and sky130_fd_sc_hd__decap_6 are equivalent.
+
+Subcircuit summary:
+Circuit 1: sky130_fd_sc_hd__decap_3 |Circuit 2: sky130_fd_sc_hd__decap_3
+-------------------------------------------|-------------------------------------------
+sky130_fd_pr__pfet_01v8_hvt (1) |sky130_fd_pr__pfet_01v8_hvt (1)
+sky130_fd_pr__nfet_01v8 (1) |sky130_fd_pr__nfet_01v8 (1)
+Number of devices: 2 |Number of devices: 2
+Number of nets: 4 |Number of nets: 4
+---------------------------------------------------------------------------------------
+Netlists match uniquely.
+
+Subcircuit pins:
+Circuit 1: sky130_fd_sc_hd__decap_3 |Circuit 2: sky130_fd_sc_hd__decap_3
+-------------------------------------------|-------------------------------------------
+VPB |VPB
+VNB |VNB
+VPWR |VPWR
+VGND |VGND
+---------------------------------------------------------------------------------------
+Cell pin lists are equivalent.
+Device classes sky130_fd_sc_hd__decap_3 and sky130_fd_sc_hd__decap_3 are equivalent.
+
+Class sky130_fd_sc_hd__and4b_2 (0): Merged 2 parallel devices.
+Class sky130_fd_sc_hd__and4b_2 (1): Merged 2 parallel devices.
+Subcircuit summary:
+Circuit 1: sky130_fd_sc_hd__and4b_2 |Circuit 2: sky130_fd_sc_hd__and4b_2
+-------------------------------------------|-------------------------------------------
+sky130_fd_pr__pfet_01v8_hvt (7->6) |sky130_fd_pr__pfet_01v8_hvt (7->6)
+sky130_fd_pr__nfet_01v8 (7->6) |sky130_fd_pr__nfet_01v8 (7->6)
+Number of devices: 12 |Number of devices: 12
+Number of nets: 14 |Number of nets: 14
+---------------------------------------------------------------------------------------
+Netlists match uniquely.
+
+Subcircuit pins:
+Circuit 1: sky130_fd_sc_hd__and4b_2 |Circuit 2: sky130_fd_sc_hd__and4b_2
+-------------------------------------------|-------------------------------------------
+VGND |VGND
+X |X
+D |D
+A_N |A_N
+C |C
+B |B
+VPWR |VPWR
+VPB |VPB
+VNB |VNB
+---------------------------------------------------------------------------------------
+Cell pin lists are equivalent.
+Device classes sky130_fd_sc_hd__and4b_2 and sky130_fd_sc_hd__and4b_2 are equivalent.
+
+Subcircuit summary:
+Circuit 1: sky130_fd_sc_hd__mux4_1 |Circuit 2: sky130_fd_sc_hd__mux4_1
+-------------------------------------------|-------------------------------------------
+sky130_fd_pr__pfet_01v8_hvt (13) |sky130_fd_pr__pfet_01v8_hvt (13)
+sky130_fd_pr__nfet_01v8 (13) |sky130_fd_pr__nfet_01v8 (13)
+Number of devices: 26 |Number of devices: 26
+Number of nets: 24 |Number of nets: 24
+---------------------------------------------------------------------------------------
+Netlists match uniquely.
+
+Subcircuit pins:
+Circuit 1: sky130_fd_sc_hd__mux4_1 |Circuit 2: sky130_fd_sc_hd__mux4_1
+-------------------------------------------|-------------------------------------------
+S1 |S1
+VPWR |VPWR
+VGND |VGND
+VPB |VPB
+VNB |VNB
+X |X
+A1 |A1
+A3 |A3
+A0 |A0
+A2 |A2
+S0 |S0
+---------------------------------------------------------------------------------------
+Cell pin lists are equivalent.
+Device classes sky130_fd_sc_hd__mux4_1 and sky130_fd_sc_hd__mux4_1 are equivalent.
+
+Cell sky130_fd_sc_hd__conb_1 (0) disconnected node: VPB
+Cell sky130_fd_sc_hd__conb_1 (0) disconnected node: VNB
+Cell sky130_fd_sc_hd__conb_1 (1) disconnected node: VNB
+Cell sky130_fd_sc_hd__conb_1 (1) disconnected node: VPB
+Subcircuit summary:
+Circuit 1: sky130_fd_sc_hd__conb_1 |Circuit 2: sky130_fd_sc_hd__conb_1
+-------------------------------------------|-------------------------------------------
+sky130_fd_pr__res_generic_po (2) |sky130_fd_pr__res_generic_po (2)
+Number of devices: 2 |Number of devices: 2
+Number of nets: 4 |Number of nets: 4
+---------------------------------------------------------------------------------------
+Resolving automorphisms by property value.
+Resolving automorphisms by pin name.
+Netlists match uniquely.
+
+Subcircuit pins:
+Circuit 1: sky130_fd_sc_hd__conb_1 |Circuit 2: sky130_fd_sc_hd__conb_1
+-------------------------------------------|-------------------------------------------
+VGND |VGND
+LO |LO
+HI |HI
+VPWR |VPWR
+VPB |VPB
+VNB |VNB
+---------------------------------------------------------------------------------------
+Cell pin lists are equivalent.
+Device classes sky130_fd_sc_hd__conb_1 and sky130_fd_sc_hd__conb_1 are equivalent.
+
+Class sky130_fd_sc_hd__and4_2 (0): Merged 2 parallel devices.
+Class sky130_fd_sc_hd__and4_2 (1): Merged 2 parallel devices.
+Subcircuit summary:
+Circuit 1: sky130_fd_sc_hd__and4_2 |Circuit 2: sky130_fd_sc_hd__and4_2
+-------------------------------------------|-------------------------------------------
+sky130_fd_pr__nfet_01v8 (6->5) |sky130_fd_pr__nfet_01v8 (6->5)
+sky130_fd_pr__pfet_01v8_hvt (6->5) |sky130_fd_pr__pfet_01v8_hvt (6->5)
+Number of devices: 10 |Number of devices: 10
+Number of nets: 13 |Number of nets: 13
+---------------------------------------------------------------------------------------
+Netlists match uniquely.
+
+Subcircuit pins:
+Circuit 1: sky130_fd_sc_hd__and4_2 |Circuit 2: sky130_fd_sc_hd__and4_2
+-------------------------------------------|-------------------------------------------
+VPWR |VPWR
+VPB |VPB
+VNB |VNB
+VGND |VGND
+X |X
+A |A
+C |C
+B |B
+D |D
+---------------------------------------------------------------------------------------
+Cell pin lists are equivalent.
+Device classes sky130_fd_sc_hd__and4_2 and sky130_fd_sc_hd__and4_2 are equivalent.
+
+Class sky130_fd_sc_hd__nor4b_2 (0): Merged 8 parallel devices.
+Class sky130_fd_sc_hd__nor4b_2 (1): Merged 8 parallel devices.
+Subcircuit summary:
+Circuit 1: sky130_fd_sc_hd__nor4b_2 |Circuit 2: sky130_fd_sc_hd__nor4b_2
+-------------------------------------------|-------------------------------------------
+sky130_fd_pr__pfet_01v8_hvt (9->5) |sky130_fd_pr__pfet_01v8_hvt (9->5)
+sky130_fd_pr__nfet_01v8 (9->5) |sky130_fd_pr__nfet_01v8 (9->5)
+Number of devices: 10 |Number of devices: 10
+Number of nets: 13 |Number of nets: 13
+---------------------------------------------------------------------------------------
+Netlists match uniquely.
+
+Subcircuit pins:
+Circuit 1: sky130_fd_sc_hd__nor4b_2 |Circuit 2: sky130_fd_sc_hd__nor4b_2
+-------------------------------------------|-------------------------------------------
+VPB |VPB
+Y |Y
+VGND |VGND
+VNB |VNB
+D_N |D_N
+VPWR |VPWR
+A |A
+C |C
+B |B
+---------------------------------------------------------------------------------------
+Cell pin lists are equivalent.
+Device classes sky130_fd_sc_hd__nor4b_2 and sky130_fd_sc_hd__nor4b_2 are equivalent.
+
+Class sky130_fd_sc_hd__nor3b_2 (0): Merged 6 parallel devices.
+Class sky130_fd_sc_hd__nor3b_2 (1): Merged 6 parallel devices.
+Subcircuit summary:
+Circuit 1: sky130_fd_sc_hd__nor3b_2 |Circuit 2: sky130_fd_sc_hd__nor3b_2
+-------------------------------------------|-------------------------------------------
+sky130_fd_pr__pfet_01v8_hvt (7->4) |sky130_fd_pr__pfet_01v8_hvt (7->4)
+sky130_fd_pr__nfet_01v8 (7->4) |sky130_fd_pr__nfet_01v8 (7->4)
+Number of devices: 8 |Number of devices: 8
+Number of nets: 11 |Number of nets: 11
+---------------------------------------------------------------------------------------
+Netlists match uniquely.
+
+Subcircuit pins:
+Circuit 1: sky130_fd_sc_hd__nor3b_2 |Circuit 2: sky130_fd_sc_hd__nor3b_2
+-------------------------------------------|-------------------------------------------
+Y |Y
+VGND |VGND
+VNB |VNB
+VPB |VPB
+VPWR |VPWR
+A |A
+B |B
+C_N |C_N
+---------------------------------------------------------------------------------------
+Cell pin lists are equivalent.
+Device classes sky130_fd_sc_hd__nor3b_2 and sky130_fd_sc_hd__nor3b_2 are equivalent.
+
+Class sky130_fd_sc_hd__and3b_2 (0): Merged 2 parallel devices.
+Class sky130_fd_sc_hd__and3b_2 (1): Merged 2 parallel devices.
+Subcircuit summary:
+Circuit 1: sky130_fd_sc_hd__and3b_2 |Circuit 2: sky130_fd_sc_hd__and3b_2
+-------------------------------------------|-------------------------------------------
+sky130_fd_pr__pfet_01v8_hvt (6->5) |sky130_fd_pr__pfet_01v8_hvt (6->5)
+sky130_fd_pr__nfet_01v8 (6->5) |sky130_fd_pr__nfet_01v8 (6->5)
+Number of devices: 10 |Number of devices: 10
+Number of nets: 12 |Number of nets: 12
+---------------------------------------------------------------------------------------
+Netlists match uniquely.
+
+Subcircuit pins:
+Circuit 1: sky130_fd_sc_hd__and3b_2 |Circuit 2: sky130_fd_sc_hd__and3b_2
+-------------------------------------------|-------------------------------------------
+VGND |VGND
+VNB |VNB
+VPWR |VPWR
+VPB |VPB
+C |C
+X |X
+B |B
+A_N |A_N
+---------------------------------------------------------------------------------------
+Cell pin lists are equivalent.
+Device classes sky130_fd_sc_hd__and3b_2 and sky130_fd_sc_hd__and3b_2 are equivalent.
+
+Class sky130_fd_sc_hd__and3_2 (0): Merged 2 parallel devices.
+Class sky130_fd_sc_hd__and3_2 (1): Merged 2 parallel devices.
+Subcircuit summary:
+Circuit 1: sky130_fd_sc_hd__and3_2 |Circuit 2: sky130_fd_sc_hd__and3_2
+-------------------------------------------|-------------------------------------------
+sky130_fd_pr__pfet_01v8_hvt (5->4) |sky130_fd_pr__pfet_01v8_hvt (5->4)
+sky130_fd_pr__nfet_01v8 (5->4) |sky130_fd_pr__nfet_01v8 (5->4)
+Number of devices: 8 |Number of devices: 8
+Number of nets: 11 |Number of nets: 11
+---------------------------------------------------------------------------------------
+Netlists match uniquely.
+
+Subcircuit pins:
+Circuit 1: sky130_fd_sc_hd__and3_2 |Circuit 2: sky130_fd_sc_hd__and3_2
+-------------------------------------------|-------------------------------------------
+X |X
+VGND |VGND
+A |A
+C |C
+B |B
+VNB |VNB
+VPWR |VPWR
+VPB |VPB
+---------------------------------------------------------------------------------------
+Cell pin lists are equivalent.
+Device classes sky130_fd_sc_hd__and3_2 and sky130_fd_sc_hd__and3_2 are equivalent.
+
+Subcircuit summary:
+Circuit 1: sky130_fd_sc_hd__mux2_1 |Circuit 2: sky130_fd_sc_hd__mux2_1
+-------------------------------------------|-------------------------------------------
+sky130_fd_pr__pfet_01v8_hvt (6) |sky130_fd_pr__pfet_01v8_hvt (6)
+sky130_fd_pr__nfet_01v8 (6) |sky130_fd_pr__nfet_01v8 (6)
+Number of devices: 12 |Number of devices: 12
+Number of nets: 14 |Number of nets: 14
+---------------------------------------------------------------------------------------
+Netlists match uniquely.
+
+Subcircuit pins:
+Circuit 1: sky130_fd_sc_hd__mux2_1 |Circuit 2: sky130_fd_sc_hd__mux2_1
+-------------------------------------------|-------------------------------------------
+VPB |VPB
+VNB |VNB
+A0 |A0
+A1 |A1
+X |X
+VPWR |VPWR
+S |S
+VGND |VGND
+---------------------------------------------------------------------------------------
+Cell pin lists are equivalent.
+Device classes sky130_fd_sc_hd__mux2_1 and sky130_fd_sc_hd__mux2_1 are equivalent.
+
+Class sky130_fd_sc_hd__and2b_2 (0): Merged 2 parallel devices.
+Class sky130_fd_sc_hd__and2b_2 (1): Merged 2 parallel devices.
+Subcircuit summary:
+Circuit 1: sky130_fd_sc_hd__and2b_2 |Circuit 2: sky130_fd_sc_hd__and2b_2
+-------------------------------------------|-------------------------------------------
+sky130_fd_pr__pfet_01v8_hvt (5->4) |sky130_fd_pr__pfet_01v8_hvt (5->4)
+sky130_fd_pr__nfet_01v8 (5->4) |sky130_fd_pr__nfet_01v8 (5->4)
+Number of devices: 8 |Number of devices: 8
+Number of nets: 10 |Number of nets: 10
+---------------------------------------------------------------------------------------
+Netlists match uniquely.
+
+Subcircuit pins:
+Circuit 1: sky130_fd_sc_hd__and2b_2 |Circuit 2: sky130_fd_sc_hd__and2b_2
+-------------------------------------------|-------------------------------------------
+VGND |VGND
+X |X
+B |B
+A_N |A_N
+VPWR |VPWR
+VPB |VPB
+VNB |VNB
+---------------------------------------------------------------------------------------
+Cell pin lists are equivalent.
+Device classes sky130_fd_sc_hd__and2b_2 and sky130_fd_sc_hd__and2b_2 are equivalent.
+
+Class sky130_fd_sc_hd__and2_2 (0): Merged 2 parallel devices.
+Class sky130_fd_sc_hd__and2_2 (1): Merged 2 parallel devices.
+Subcircuit summary:
+Circuit 1: sky130_fd_sc_hd__and2_2 |Circuit 2: sky130_fd_sc_hd__and2_2
+-------------------------------------------|-------------------------------------------
+sky130_fd_pr__pfet_01v8_hvt (4->3) |sky130_fd_pr__pfet_01v8_hvt (4->3)
+sky130_fd_pr__nfet_01v8 (4->3) |sky130_fd_pr__nfet_01v8 (4->3)
+Number of devices: 6 |Number of devices: 6
+Number of nets: 9 |Number of nets: 9
+---------------------------------------------------------------------------------------
+Netlists match uniquely.
+
+Subcircuit pins:
+Circuit 1: sky130_fd_sc_hd__and2_2 |Circuit 2: sky130_fd_sc_hd__and2_2
+-------------------------------------------|-------------------------------------------
+VPWR |VPWR
+VPB |VPB
+VNB |VNB
+X |X
+A |A
+B |B
+VGND |VGND
+---------------------------------------------------------------------------------------
+Cell pin lists are equivalent.
+Device classes sky130_fd_sc_hd__and2_2 and sky130_fd_sc_hd__and2_2 are equivalent.
+
+Subcircuit summary:
+Circuit 1: sky130_ef_sc_hd__decap_12 |Circuit 2: sky130_ef_sc_hd__decap_12
+-------------------------------------------|-------------------------------------------
+sky130_fd_pr__pfet_01v8_hvt (1) |sky130_fd_pr__pfet_01v8_hvt (1)
+sky130_fd_pr__nfet_01v8 (1) |sky130_fd_pr__nfet_01v8 (1)
+Number of devices: 2 |Number of devices: 2
+Number of nets: 4 |Number of nets: 4
+---------------------------------------------------------------------------------------
+Netlists match uniquely.
+
+Subcircuit pins:
+Circuit 1: sky130_ef_sc_hd__decap_12 |Circuit 2: sky130_ef_sc_hd__decap_12
+-------------------------------------------|-------------------------------------------
+VPB |VPB
+VNB |VNB
+VPWR |VPWR
+VGND |VGND
+---------------------------------------------------------------------------------------
+Cell pin lists are equivalent.
+Device classes sky130_ef_sc_hd__decap_12 and sky130_ef_sc_hd__decap_12 are equivalent.
+
+Subcircuit summary:
+Circuit 1: sky130_fd_sc_hd__a211o_1 |Circuit 2: sky130_fd_sc_hd__a211o_1
+-------------------------------------------|-------------------------------------------
+sky130_fd_pr__pfet_01v8_hvt (5) |sky130_fd_pr__pfet_01v8_hvt (5)
+sky130_fd_pr__nfet_01v8 (5) |sky130_fd_pr__nfet_01v8 (5)
+Number of devices: 10 |Number of devices: 10
+Number of nets: 13 |Number of nets: 13
+---------------------------------------------------------------------------------------
+Netlists match uniquely.
+
+Subcircuit pins:
+Circuit 1: sky130_fd_sc_hd__a211o_1 |Circuit 2: sky130_fd_sc_hd__a211o_1
+-------------------------------------------|-------------------------------------------
+VGND |VGND
+VNB |VNB
+VPB |VPB
+A2 |A2
+X |X
+A1 |A1
+B1 |B1
+C1 |C1
+VPWR |VPWR
+---------------------------------------------------------------------------------------
+Cell pin lists are equivalent.
+Device classes sky130_fd_sc_hd__a211o_1 and sky130_fd_sc_hd__a211o_1 are equivalent.
+
+Class sky130_fd_sc_hd__a211oi_2 (0): Merged 8 parallel devices.
+Class sky130_fd_sc_hd__a211oi_2 (1): Merged 8 parallel devices.
+Subcircuit summary:
+Circuit 1: sky130_fd_sc_hd__a211oi_2 |Circuit 2: sky130_fd_sc_hd__a211oi_2
+-------------------------------------------|-------------------------------------------
+sky130_fd_pr__nfet_01v8 (8->4) |sky130_fd_pr__nfet_01v8 (8->4)
+sky130_fd_pr__pfet_01v8_hvt (8->4) |sky130_fd_pr__pfet_01v8_hvt (8->4)
+Number of devices: 8 |Number of devices: 8
+Number of nets: 12 |Number of nets: 12
+---------------------------------------------------------------------------------------
+Netlists match uniquely.
+
+Subcircuit pins:
+Circuit 1: sky130_fd_sc_hd__a211oi_2 |Circuit 2: sky130_fd_sc_hd__a211oi_2
+-------------------------------------------|-------------------------------------------
+VPB |VPB
+Y |Y
+VNB |VNB
+B1 |B1
+C1 |C1
+VPWR |VPWR
+A2 |A2
+A1 |A1
+VGND |VGND
+---------------------------------------------------------------------------------------
+Cell pin lists are equivalent.
+Device classes sky130_fd_sc_hd__a211oi_2 and sky130_fd_sc_hd__a211oi_2 are equivalent.
+
+Subcircuit summary:
+Circuit 1: sky130_fd_sc_hd__o211a_1 |Circuit 2: sky130_fd_sc_hd__o211a_1
+-------------------------------------------|-------------------------------------------
+sky130_fd_pr__nfet_01v8 (5) |sky130_fd_pr__nfet_01v8 (5)
+sky130_fd_pr__pfet_01v8_hvt (5) |sky130_fd_pr__pfet_01v8_hvt (5)
+Number of devices: 10 |Number of devices: 10
+Number of nets: 13 |Number of nets: 13
+---------------------------------------------------------------------------------------
+Netlists match uniquely.
+
+Subcircuit pins:
+Circuit 1: sky130_fd_sc_hd__o211a_1 |Circuit 2: sky130_fd_sc_hd__o211a_1
+-------------------------------------------|-------------------------------------------
+VPWR |VPWR
+VPB |VPB
+VNB |VNB
+C1 |C1
+A1 |A1
+B1 |B1
+A2 |A2
+X |X
+VGND |VGND
+---------------------------------------------------------------------------------------
+Cell pin lists are equivalent.
+Device classes sky130_fd_sc_hd__o211a_1 and sky130_fd_sc_hd__o211a_1 are equivalent.
+
+Subcircuit summary:
+Circuit 1: sky130_fd_sc_hd__and4b_1 |Circuit 2: sky130_fd_sc_hd__and4b_1
+-------------------------------------------|-------------------------------------------
+sky130_fd_pr__nfet_01v8 (6) |sky130_fd_pr__nfet_01v8 (6)
+sky130_fd_pr__pfet_01v8_hvt (6) |sky130_fd_pr__pfet_01v8_hvt (6)
+Number of devices: 12 |Number of devices: 12
+Number of nets: 14 |Number of nets: 14
+---------------------------------------------------------------------------------------
+Netlists match uniquely.
+
+Subcircuit pins:
+Circuit 1: sky130_fd_sc_hd__and4b_1 |Circuit 2: sky130_fd_sc_hd__and4b_1
+-------------------------------------------|-------------------------------------------
+VGND |VGND
+VPWR |VPWR
+VPB |VPB
+VNB |VNB
+X |X
+D |D
+A_N |A_N
+C |C
+B |B
+---------------------------------------------------------------------------------------
+Cell pin lists are equivalent.
+Device classes sky130_fd_sc_hd__and4b_1 and sky130_fd_sc_hd__and4b_1 are equivalent.
+
+Subcircuit summary:
+Circuit 1: sky130_fd_sc_hd__o41a_1 |Circuit 2: sky130_fd_sc_hd__o41a_1
+-------------------------------------------|-------------------------------------------
+sky130_fd_pr__nfet_01v8 (6) |sky130_fd_pr__nfet_01v8 (6)
+sky130_fd_pr__pfet_01v8_hvt (6) |sky130_fd_pr__pfet_01v8_hvt (6)
+Number of devices: 12 |Number of devices: 12
+Number of nets: 15 |Number of nets: 15
+---------------------------------------------------------------------------------------
+Netlists match uniquely.
+
+Subcircuit pins:
+Circuit 1: sky130_fd_sc_hd__o41a_1 |Circuit 2: sky130_fd_sc_hd__o41a_1
+-------------------------------------------|-------------------------------------------
+VPWR |VPWR
+VPB |VPB
+VNB |VNB
+A2 |A2
+A3 |A3
+A4 |A4
+B1 |B1
+A1 |A1
+X |X
+VGND |VGND
+---------------------------------------------------------------------------------------
+Cell pin lists are equivalent.
+Device classes sky130_fd_sc_hd__o41a_1 and sky130_fd_sc_hd__o41a_1 are equivalent.
+
+Subcircuit summary:
+Circuit 1: sky130_fd_sc_hd__a221o_1 |Circuit 2: sky130_fd_sc_hd__a221o_1
+-------------------------------------------|-------------------------------------------
+sky130_fd_pr__nfet_01v8 (6) |sky130_fd_pr__nfet_01v8 (6)
+sky130_fd_pr__pfet_01v8_hvt (6) |sky130_fd_pr__pfet_01v8_hvt (6)
+Number of devices: 12 |Number of devices: 12
+Number of nets: 15 |Number of nets: 15
+---------------------------------------------------------------------------------------
+Netlists match uniquely.
+
+Subcircuit pins:
+Circuit 1: sky130_fd_sc_hd__a221o_1 |Circuit 2: sky130_fd_sc_hd__a221o_1
+-------------------------------------------|-------------------------------------------
+VGND |VGND
+VPWR |VPWR
+VPB |VPB
+VNB |VNB
+X |X
+B1 |B1
+A1 |A1
+C1 |C1
+A2 |A2
+B2 |B2
+---------------------------------------------------------------------------------------
+Cell pin lists are equivalent.
+Device classes sky130_fd_sc_hd__a221o_1 and sky130_fd_sc_hd__a221o_1 are equivalent.
+
+Subcircuit summary:
+Circuit 1: sky130_fd_sc_hd__a32o_1 |Circuit 2: sky130_fd_sc_hd__a32o_1
+-------------------------------------------|-------------------------------------------
+sky130_fd_pr__nfet_01v8 (6) |sky130_fd_pr__nfet_01v8 (6)
+sky130_fd_pr__pfet_01v8_hvt (6) |sky130_fd_pr__pfet_01v8_hvt (6)
+Number of devices: 12 |Number of devices: 12
+Number of nets: 15 |Number of nets: 15
+---------------------------------------------------------------------------------------
+Netlists match uniquely.
+
+Subcircuit pins:
+Circuit 1: sky130_fd_sc_hd__a32o_1 |Circuit 2: sky130_fd_sc_hd__a32o_1
+-------------------------------------------|-------------------------------------------
+VGND |VGND
+VPWR |VPWR
+B2 |B2
+X |X
+B1 |B1
+A2 |A2
+A3 |A3
+A1 |A1
+VPB |VPB
+VNB |VNB
+---------------------------------------------------------------------------------------
+Cell pin lists are equivalent.
+Device classes sky130_fd_sc_hd__a32o_1 and sky130_fd_sc_hd__a32o_1 are equivalent.
+
+Subcircuit summary:
+Circuit 1: sky130_fd_sc_hd__nor2_1 |Circuit 2: sky130_fd_sc_hd__nor2_1
+-------------------------------------------|-------------------------------------------
+sky130_fd_pr__pfet_01v8_hvt (2) |sky130_fd_pr__pfet_01v8_hvt (2)
+sky130_fd_pr__nfet_01v8 (2) |sky130_fd_pr__nfet_01v8 (2)
+Number of devices: 4 |Number of devices: 4
+Number of nets: 8 |Number of nets: 8
+---------------------------------------------------------------------------------------
+Netlists match uniquely.
+
+Subcircuit pins:
+Circuit 1: sky130_fd_sc_hd__nor2_1 |Circuit 2: sky130_fd_sc_hd__nor2_1
+-------------------------------------------|-------------------------------------------
+Y |Y
+A |A
+VPB |VPB
+VGND |VGND
+VNB |VNB
+B |B
+VPWR |VPWR
+---------------------------------------------------------------------------------------
+Cell pin lists are equivalent.
+Device classes sky130_fd_sc_hd__nor2_1 and sky130_fd_sc_hd__nor2_1 are equivalent.
+
+Subcircuit summary:
+Circuit 1: sky130_fd_sc_hd__o31a_1 |Circuit 2: sky130_fd_sc_hd__o31a_1
+-------------------------------------------|-------------------------------------------
+sky130_fd_pr__nfet_01v8 (5) |sky130_fd_pr__nfet_01v8 (5)
+sky130_fd_pr__pfet_01v8_hvt (5) |sky130_fd_pr__pfet_01v8_hvt (5)
+Number of devices: 10 |Number of devices: 10
+Number of nets: 13 |Number of nets: 13
+---------------------------------------------------------------------------------------
+Netlists match uniquely.
+
+Subcircuit pins:
+Circuit 1: sky130_fd_sc_hd__o31a_1 |Circuit 2: sky130_fd_sc_hd__o31a_1
+-------------------------------------------|-------------------------------------------
+VPWR |VPWR
+VGND |VGND
+A2 |A2
+A1 |A1
+X |X
+B1 |B1
+A3 |A3
+VNB |VNB
+VPB |VPB
+---------------------------------------------------------------------------------------
+Cell pin lists are equivalent.
+Device classes sky130_fd_sc_hd__o31a_1 and sky130_fd_sc_hd__o31a_1 are equivalent.
+
+Subcircuit summary:
+Circuit 1: sky130_fd_sc_hd__dlygate4sd3_1 |Circuit 2: sky130_fd_sc_hd__dlygate4sd3_1
+-------------------------------------------|-------------------------------------------
+sky130_fd_pr__pfet_01v8_hvt (4) |sky130_fd_pr__pfet_01v8_hvt (4)
+sky130_fd_pr__nfet_01v8 (4) |sky130_fd_pr__nfet_01v8 (4)
+Number of devices: 8 |Number of devices: 8
+Number of nets: 9 |Number of nets: 9
+---------------------------------------------------------------------------------------
+Netlists match uniquely.
+
+Subcircuit pins:
+Circuit 1: sky130_fd_sc_hd__dlygate4sd3_1 |Circuit 2: sky130_fd_sc_hd__dlygate4sd3_1
+-------------------------------------------|-------------------------------------------
+A |A
+X |X
+VGND |VGND
+VNB |VNB
+VPWR |VPWR
+VPB |VPB
+---------------------------------------------------------------------------------------
+Cell pin lists are equivalent.
+Device classes sky130_fd_sc_hd__dlygate4sd3_1 and sky130_fd_sc_hd__dlygate4sd3_1 are equivalent.
+
+Class sky130_fd_sc_hd__dfxtp_4 (0): Merged 6 parallel devices.
+Class sky130_fd_sc_hd__dfxtp_4 (1): Merged 6 parallel devices.
+Subcircuit summary:
+Circuit 1: sky130_fd_sc_hd__dfxtp_4 |Circuit 2: sky130_fd_sc_hd__dfxtp_4
+-------------------------------------------|-------------------------------------------
+sky130_fd_pr__pfet_01v8_hvt (15->12) |sky130_fd_pr__pfet_01v8_hvt (15->12)
+sky130_fd_pr__nfet_01v8 (15->12) |sky130_fd_pr__nfet_01v8 (15->12)
+Number of devices: 24 |Number of devices: 24
+Number of nets: 18 |Number of nets: 18
+---------------------------------------------------------------------------------------
+Netlists match uniquely.
+
+Subcircuit pins:
+Circuit 1: sky130_fd_sc_hd__dfxtp_4 |Circuit 2: sky130_fd_sc_hd__dfxtp_4
+-------------------------------------------|-------------------------------------------
+VPB |VPB
+VNB |VNB
+VGND |VGND
+VPWR |VPWR
+Q |Q
+D |D
+CLK |CLK
+---------------------------------------------------------------------------------------
+Cell pin lists are equivalent.
+Device classes sky130_fd_sc_hd__dfxtp_4 and sky130_fd_sc_hd__dfxtp_4 are equivalent.
+
+Class sky130_fd_sc_hd__buf_6 (0): Merged 12 parallel devices.
+Class sky130_fd_sc_hd__buf_6 (1): Merged 12 parallel devices.
+Subcircuit summary:
+Circuit 1: sky130_fd_sc_hd__buf_6 |Circuit 2: sky130_fd_sc_hd__buf_6
+-------------------------------------------|-------------------------------------------
+sky130_fd_pr__pfet_01v8_hvt (8->2) |sky130_fd_pr__pfet_01v8_hvt (8->2)
+sky130_fd_pr__nfet_01v8 (8->2) |sky130_fd_pr__nfet_01v8 (8->2)
+Number of devices: 4 |Number of devices: 4
+Number of nets: 7 |Number of nets: 7
+---------------------------------------------------------------------------------------
+Netlists match uniquely.
+
+Subcircuit pins:
+Circuit 1: sky130_fd_sc_hd__buf_6 |Circuit 2: sky130_fd_sc_hd__buf_6
+-------------------------------------------|-------------------------------------------
+VGND |VGND
+X |X
+VNB |VNB
+A |A
+VPWR |VPWR
+VPB |VPB
+---------------------------------------------------------------------------------------
+Cell pin lists are equivalent.
+Device classes sky130_fd_sc_hd__buf_6 and sky130_fd_sc_hd__buf_6 are equivalent.
+
+Class sky130_fd_sc_hd__buf_12 (0): Merged 28 parallel devices.
+Class sky130_fd_sc_hd__buf_12 (1): Merged 28 parallel devices.
+Subcircuit summary:
+Circuit 1: sky130_fd_sc_hd__buf_12 |Circuit 2: sky130_fd_sc_hd__buf_12
+-------------------------------------------|-------------------------------------------
+sky130_fd_pr__nfet_01v8 (16->2) |sky130_fd_pr__nfet_01v8 (16->2)
+sky130_fd_pr__pfet_01v8_hvt (16->2) |sky130_fd_pr__pfet_01v8_hvt (16->2)
+Number of devices: 4 |Number of devices: 4
+Number of nets: 7 |Number of nets: 7
+---------------------------------------------------------------------------------------
+Netlists match uniquely.
+
+Subcircuit pins:
+Circuit 1: sky130_fd_sc_hd__buf_12 |Circuit 2: sky130_fd_sc_hd__buf_12
+-------------------------------------------|-------------------------------------------
+X |X
+VPWR |VPWR
+VPB |VPB
+VGND |VGND
+VNB |VNB
+A |A
+---------------------------------------------------------------------------------------
+Cell pin lists are equivalent.
+Device classes sky130_fd_sc_hd__buf_12 and sky130_fd_sc_hd__buf_12 are equivalent.
+
+Class sky130_fd_sc_hd__or4b_4 (0): Merged 6 parallel devices.
+Class sky130_fd_sc_hd__or4b_4 (1): Merged 6 parallel devices.
+Subcircuit summary:
+Circuit 1: sky130_fd_sc_hd__or4b_4 |Circuit 2: sky130_fd_sc_hd__or4b_4
+-------------------------------------------|-------------------------------------------
+sky130_fd_pr__pfet_01v8_hvt (9->6) |sky130_fd_pr__pfet_01v8_hvt (9->6)
+sky130_fd_pr__nfet_01v8 (9->6) |sky130_fd_pr__nfet_01v8 (9->6)
+Number of devices: 12 |Number of devices: 12
+Number of nets: 14 |Number of nets: 14
+---------------------------------------------------------------------------------------
+Netlists match uniquely.
+
+Subcircuit pins:
+Circuit 1: sky130_fd_sc_hd__or4b_4 |Circuit 2: sky130_fd_sc_hd__or4b_4
+-------------------------------------------|-------------------------------------------
+VPB |VPB
+VGND |VGND
+VNB |VNB
+VPWR |VPWR
+X |X
+B |B
+C |C
+A |A
+D_N |D_N
+---------------------------------------------------------------------------------------
+Cell pin lists are equivalent.
+Device classes sky130_fd_sc_hd__or4b_4 and sky130_fd_sc_hd__or4b_4 are equivalent.
+
+Class sky130_fd_sc_hd__buf_8 (0): Merged 18 parallel devices.
+Class sky130_fd_sc_hd__buf_8 (1): Merged 18 parallel devices.
+Subcircuit summary:
+Circuit 1: sky130_fd_sc_hd__buf_8 |Circuit 2: sky130_fd_sc_hd__buf_8
+-------------------------------------------|-------------------------------------------
+sky130_fd_pr__nfet_01v8 (11->2) |sky130_fd_pr__nfet_01v8 (11->2)
+sky130_fd_pr__pfet_01v8_hvt (11->2) |sky130_fd_pr__pfet_01v8_hvt (11->2)
+Number of devices: 4 |Number of devices: 4
+Number of nets: 7 |Number of nets: 7
+---------------------------------------------------------------------------------------
+Netlists match uniquely.
+
+Subcircuit pins:
+Circuit 1: sky130_fd_sc_hd__buf_8 |Circuit 2: sky130_fd_sc_hd__buf_8
+-------------------------------------------|-------------------------------------------
+X |X
+VGND |VGND
+VNB |VNB
+VPWR |VPWR
+VPB |VPB
+A |A
+---------------------------------------------------------------------------------------
+Cell pin lists are equivalent.
+Device classes sky130_fd_sc_hd__buf_8 and sky130_fd_sc_hd__buf_8 are equivalent.
+
+Subcircuit summary:
+Circuit 1: sky130_fd_sc_hd__nand2_1 |Circuit 2: sky130_fd_sc_hd__nand2_1
+-------------------------------------------|-------------------------------------------
+sky130_fd_pr__pfet_01v8_hvt (2) |sky130_fd_pr__pfet_01v8_hvt (2)
+sky130_fd_pr__nfet_01v8 (2) |sky130_fd_pr__nfet_01v8 (2)
+Number of devices: 4 |Number of devices: 4
+Number of nets: 8 |Number of nets: 8
+---------------------------------------------------------------------------------------
+Netlists match uniquely.
+
+Subcircuit pins:
+Circuit 1: sky130_fd_sc_hd__nand2_1 |Circuit 2: sky130_fd_sc_hd__nand2_1
+-------------------------------------------|-------------------------------------------
+VGND |VGND
+Y |Y
+A |A
+VPWR |VPWR
+VPB |VPB
+B |B
+VNB |VNB
+---------------------------------------------------------------------------------------
+Cell pin lists are equivalent.
+Device classes sky130_fd_sc_hd__nand2_1 and sky130_fd_sc_hd__nand2_1 are equivalent.
+
+Class sky130_fd_sc_hd__buf_4 (0): Merged 6 parallel devices.
+Class sky130_fd_sc_hd__buf_4 (1): Merged 6 parallel devices.
+Subcircuit summary:
+Circuit 1: sky130_fd_sc_hd__buf_4 |Circuit 2: sky130_fd_sc_hd__buf_4
+-------------------------------------------|-------------------------------------------
+sky130_fd_pr__pfet_01v8_hvt (5->2) |sky130_fd_pr__pfet_01v8_hvt (5->2)
+sky130_fd_pr__nfet_01v8 (5->2) |sky130_fd_pr__nfet_01v8 (5->2)
+Number of devices: 4 |Number of devices: 4
+Number of nets: 7 |Number of nets: 7
+---------------------------------------------------------------------------------------
+Netlists match uniquely.
+
+Subcircuit pins:
+Circuit 1: sky130_fd_sc_hd__buf_4 |Circuit 2: sky130_fd_sc_hd__buf_4
+-------------------------------------------|-------------------------------------------
+X |X
+VGND |VGND
+VNB |VNB
+VPWR |VPWR
+VPB |VPB
+A |A
+---------------------------------------------------------------------------------------
+Cell pin lists are equivalent.
+Device classes sky130_fd_sc_hd__buf_4 and sky130_fd_sc_hd__buf_4 are equivalent.
+
+Subcircuit summary:
+Circuit 1: sky130_fd_sc_hd__a31o_1 |Circuit 2: sky130_fd_sc_hd__a31o_1
+-------------------------------------------|-------------------------------------------
+sky130_fd_pr__pfet_01v8_hvt (5) |sky130_fd_pr__pfet_01v8_hvt (5)
+sky130_fd_pr__nfet_01v8 (5) |sky130_fd_pr__nfet_01v8 (5)
+Number of devices: 10 |Number of devices: 10
+Number of nets: 13 |Number of nets: 13
+---------------------------------------------------------------------------------------
+Netlists match uniquely.
+
+Subcircuit pins:
+Circuit 1: sky130_fd_sc_hd__a31o_1 |Circuit 2: sky130_fd_sc_hd__a31o_1
+-------------------------------------------|-------------------------------------------
+VGND |VGND
+B1 |B1
+X |X
+A2 |A2
+A1 |A1
+A3 |A3
+VNB |VNB
+VPB |VPB
+VPWR |VPWR
+---------------------------------------------------------------------------------------
+Cell pin lists are equivalent.
+Device classes sky130_fd_sc_hd__a31o_1 and sky130_fd_sc_hd__a31o_1 are equivalent.
+
+Subcircuit summary:
+Circuit 1: sky130_fd_sc_hd__a21bo_1 |Circuit 2: sky130_fd_sc_hd__a21bo_1
+-------------------------------------------|-------------------------------------------
+sky130_fd_pr__pfet_01v8_hvt (5) |sky130_fd_pr__pfet_01v8_hvt (5)
+sky130_fd_pr__nfet_01v8 (5) |sky130_fd_pr__nfet_01v8 (5)
+Number of devices: 10 |Number of devices: 10
+Number of nets: 12 |Number of nets: 12
+---------------------------------------------------------------------------------------
+Netlists match uniquely.
+
+Subcircuit pins:
+Circuit 1: sky130_fd_sc_hd__a21bo_1 |Circuit 2: sky130_fd_sc_hd__a21bo_1
+-------------------------------------------|-------------------------------------------
+X |X
+A2 |A2
+A1 |A1
+B1_N |B1_N
+VPB |VPB
+VNB |VNB
+VPWR |VPWR
+VGND |VGND
+---------------------------------------------------------------------------------------
+Cell pin lists are equivalent.
+Device classes sky130_fd_sc_hd__a21bo_1 and sky130_fd_sc_hd__a21bo_1 are equivalent.
+
+Subcircuit summary:
+Circuit 1: sky130_fd_sc_hd__o21a_1 |Circuit 2: sky130_fd_sc_hd__o21a_1
+-------------------------------------------|-------------------------------------------
+sky130_fd_pr__pfet_01v8_hvt (4) |sky130_fd_pr__pfet_01v8_hvt (4)
+sky130_fd_pr__nfet_01v8 (4) |sky130_fd_pr__nfet_01v8 (4)
+Number of devices: 8 |Number of devices: 8
+Number of nets: 11 |Number of nets: 11
+---------------------------------------------------------------------------------------
+Netlists match uniquely.
+
+Subcircuit pins:
+Circuit 1: sky130_fd_sc_hd__o21a_1 |Circuit 2: sky130_fd_sc_hd__o21a_1
+-------------------------------------------|-------------------------------------------
+VPB |VPB
+VNB |VNB
+A1 |A1
+B1 |B1
+X |X
+A2 |A2
+VPWR |VPWR
+VGND |VGND
+---------------------------------------------------------------------------------------
+Cell pin lists are equivalent.
+Device classes sky130_fd_sc_hd__o21a_1 and sky130_fd_sc_hd__o21a_1 are equivalent.
+
+Class sky130_fd_sc_hd__a31o_4 (0): Merged 11 parallel devices.
+Class sky130_fd_sc_hd__a31o_4 (1): Merged 11 parallel devices.
+Subcircuit summary:
+Circuit 1: sky130_fd_sc_hd__a31o_4 |Circuit 2: sky130_fd_sc_hd__a31o_4
+-------------------------------------------|-------------------------------------------
+sky130_fd_pr__pfet_01v8_hvt (12->5) |sky130_fd_pr__pfet_01v8_hvt (12->5)
+sky130_fd_pr__nfet_01v8 (12->8) |sky130_fd_pr__nfet_01v8 (12->8)
+Number of devices: 13 |Number of devices: 13
+Number of nets: 15 |Number of nets: 15
+---------------------------------------------------------------------------------------
+Resolving automorphisms by property value.
+Resolving automorphisms by pin name.
+Netlists match uniquely.
+
+Subcircuit pins:
+Circuit 1: sky130_fd_sc_hd__a31o_4 |Circuit 2: sky130_fd_sc_hd__a31o_4
+-------------------------------------------|-------------------------------------------
+VNB |VNB
+A2 |A2
+A1 |A1
+A3 |A3
+VPB |VPB
+B1 |B1
+X |X
+VGND |VGND
+VPWR |VPWR
+---------------------------------------------------------------------------------------
+Cell pin lists are equivalent.
+Device classes sky130_fd_sc_hd__a31o_4 and sky130_fd_sc_hd__a31o_4 are equivalent.
+
+Class sky130_fd_sc_hd__and3_4 (0): Merged 6 parallel devices.
+Class sky130_fd_sc_hd__and3_4 (1): Merged 6 parallel devices.
+Subcircuit summary:
+Circuit 1: sky130_fd_sc_hd__and3_4 |Circuit 2: sky130_fd_sc_hd__and3_4
+-------------------------------------------|-------------------------------------------
+sky130_fd_pr__pfet_01v8_hvt (7->4) |sky130_fd_pr__pfet_01v8_hvt (7->4)
+sky130_fd_pr__nfet_01v8 (7->4) |sky130_fd_pr__nfet_01v8 (7->4)
+Number of devices: 8 |Number of devices: 8
+Number of nets: 11 |Number of nets: 11
+---------------------------------------------------------------------------------------
+Netlists match uniquely.
+
+Subcircuit pins:
+Circuit 1: sky130_fd_sc_hd__and3_4 |Circuit 2: sky130_fd_sc_hd__and3_4
+-------------------------------------------|-------------------------------------------
+X |X
+VGND |VGND
+A |A
+C |C
+B |B
+VNB |VNB
+VPWR |VPWR
+VPB |VPB
+---------------------------------------------------------------------------------------
+Cell pin lists are equivalent.
+Device classes sky130_fd_sc_hd__and3_4 and sky130_fd_sc_hd__and3_4 are equivalent.
+
+Class sky130_fd_sc_hd__a211oi_4 (0): Merged 20 parallel devices.
+Class sky130_fd_sc_hd__a211oi_4 (1): Merged 20 parallel devices.
+Subcircuit summary:
+Circuit 1: sky130_fd_sc_hd__a211oi_4 |Circuit 2: sky130_fd_sc_hd__a211oi_4
+-------------------------------------------|-------------------------------------------
+sky130_fd_pr__nfet_01v8 (16->4) |sky130_fd_pr__nfet_01v8 (16->4)
+sky130_fd_pr__pfet_01v8_hvt (16->8) |sky130_fd_pr__pfet_01v8_hvt (16->8)
+Number of devices: 12 |Number of devices: 12
+Number of nets: 14 |Number of nets: 14
+---------------------------------------------------------------------------------------
+Resolving automorphisms by property value.
+Resolving automorphisms by pin name.
+Netlists match uniquely.
+
+Subcircuit pins:
+Circuit 1: sky130_fd_sc_hd__a211oi_4 |Circuit 2: sky130_fd_sc_hd__a211oi_4
+-------------------------------------------|-------------------------------------------
+VPB |VPB
+VGND |VGND
+C1 |C1
+VNB |VNB
+B1 |B1
+A1 |A1
+VPWR |VPWR
+A2 |A2
+Y |Y
+---------------------------------------------------------------------------------------
+Cell pin lists are equivalent.
+Device classes sky130_fd_sc_hd__a211oi_4 and sky130_fd_sc_hd__a211oi_4 are equivalent.
+
+Subcircuit summary:
+Circuit 1: sky130_fd_sc_hd__o221a_1 |Circuit 2: sky130_fd_sc_hd__o221a_1
+-------------------------------------------|-------------------------------------------
+sky130_fd_pr__nfet_01v8 (6) |sky130_fd_pr__nfet_01v8 (6)
+sky130_fd_pr__pfet_01v8_hvt (6) |sky130_fd_pr__pfet_01v8_hvt (6)
+Number of devices: 12 |Number of devices: 12
+Number of nets: 15 |Number of nets: 15
+---------------------------------------------------------------------------------------
+Netlists match uniquely.
+
+Subcircuit pins:
+Circuit 1: sky130_fd_sc_hd__o221a_1 |Circuit 2: sky130_fd_sc_hd__o221a_1
+-------------------------------------------|-------------------------------------------
+VPB |VPB
+VNB |VNB
+VGND |VGND
+X |X
+B1 |B1
+A1 |A1
+C1 |C1
+B2 |B2
+A2 |A2
+VPWR |VPWR
+---------------------------------------------------------------------------------------
+Cell pin lists are equivalent.
+Device classes sky130_fd_sc_hd__o221a_1 and sky130_fd_sc_hd__o221a_1 are equivalent.
+
+Subcircuit summary:
+Circuit 1: sky130_fd_sc_hd__o311a_1 |Circuit 2: sky130_fd_sc_hd__o311a_1
+-------------------------------------------|-------------------------------------------
+sky130_fd_pr__nfet_01v8 (6) |sky130_fd_pr__nfet_01v8 (6)
+sky130_fd_pr__pfet_01v8_hvt (6) |sky130_fd_pr__pfet_01v8_hvt (6)
+Number of devices: 12 |Number of devices: 12
+Number of nets: 15 |Number of nets: 15
+---------------------------------------------------------------------------------------
+Netlists match uniquely.
+
+Subcircuit pins:
+Circuit 1: sky130_fd_sc_hd__o311a_1 |Circuit 2: sky130_fd_sc_hd__o311a_1
+-------------------------------------------|-------------------------------------------
+VNB |VNB
+VPB |VPB
+VGND |VGND
+VPWR |VPWR
+B1 |B1
+A1 |A1
+C1 |C1
+A2 |A2
+X |X
+A3 |A3
+---------------------------------------------------------------------------------------
+Cell pin lists are equivalent.
+Device classes sky130_fd_sc_hd__o311a_1 and sky130_fd_sc_hd__o311a_1 are equivalent.
+
+Subcircuit summary:
+Circuit 1: sky130_fd_sc_hd__a21o_1 |Circuit 2: sky130_fd_sc_hd__a21o_1
+-------------------------------------------|-------------------------------------------
+sky130_fd_pr__nfet_01v8 (4) |sky130_fd_pr__nfet_01v8 (4)
+sky130_fd_pr__pfet_01v8_hvt (4) |sky130_fd_pr__pfet_01v8_hvt (4)
+Number of devices: 8 |Number of devices: 8
+Number of nets: 11 |Number of nets: 11
+---------------------------------------------------------------------------------------
+Netlists match uniquely.
+
+Subcircuit pins:
+Circuit 1: sky130_fd_sc_hd__a21o_1 |Circuit 2: sky130_fd_sc_hd__a21o_1
+-------------------------------------------|-------------------------------------------
+VNB |VNB
+VPB |VPB
+VGND |VGND
+VPWR |VPWR
+A2 |A2
+X |X
+B1 |B1
+A1 |A1
+---------------------------------------------------------------------------------------
+Cell pin lists are equivalent.
+Device classes sky130_fd_sc_hd__a21o_1 and sky130_fd_sc_hd__a21o_1 are equivalent.
+
+Subcircuit summary:
+Circuit 1: sky130_fd_sc_hd__a41o_1 |Circuit 2: sky130_fd_sc_hd__a41o_1
+-------------------------------------------|-------------------------------------------
+sky130_fd_pr__nfet_01v8 (6) |sky130_fd_pr__nfet_01v8 (6)
+sky130_fd_pr__pfet_01v8_hvt (6) |sky130_fd_pr__pfet_01v8_hvt (6)
+Number of devices: 12 |Number of devices: 12
+Number of nets: 15 |Number of nets: 15
+---------------------------------------------------------------------------------------
+Netlists match uniquely.
+
+Subcircuit pins:
+Circuit 1: sky130_fd_sc_hd__a41o_1 |Circuit 2: sky130_fd_sc_hd__a41o_1
+-------------------------------------------|-------------------------------------------
+VPWR |VPWR
+VGND |VGND
+VNB |VNB
+VPB |VPB
+B1 |B1
+A4 |A4
+A3 |A3
+A2 |A2
+A1 |A1
+X |X
+---------------------------------------------------------------------------------------
+Cell pin lists are equivalent.
+Device classes sky130_fd_sc_hd__a41o_1 and sky130_fd_sc_hd__a41o_1 are equivalent.
+
+Subcircuit summary:
+Circuit 1: sky130_fd_sc_hd__a31oi_1 |Circuit 2: sky130_fd_sc_hd__a31oi_1
+-------------------------------------------|-------------------------------------------
+sky130_fd_pr__nfet_01v8 (4) |sky130_fd_pr__nfet_01v8 (4)
+sky130_fd_pr__pfet_01v8_hvt (4) |sky130_fd_pr__pfet_01v8_hvt (4)
+Number of devices: 8 |Number of devices: 8
+Number of nets: 12 |Number of nets: 12
+---------------------------------------------------------------------------------------
+Netlists match uniquely.
+
+Subcircuit pins:
+Circuit 1: sky130_fd_sc_hd__a31oi_1 |Circuit 2: sky130_fd_sc_hd__a31oi_1
+-------------------------------------------|-------------------------------------------
+VPB |VPB
+VNB |VNB
+B1 |B1
+A1 |A1
+VGND |VGND
+A3 |A3
+A2 |A2
+Y |Y
+VPWR |VPWR
+---------------------------------------------------------------------------------------
+Cell pin lists are equivalent.
+Device classes sky130_fd_sc_hd__a31oi_1 and sky130_fd_sc_hd__a31oi_1 are equivalent.
+
+Subcircuit summary:
+Circuit 1: sky130_fd_sc_hd__a22o_1 |Circuit 2: sky130_fd_sc_hd__a22o_1
+-------------------------------------------|-------------------------------------------
+sky130_fd_pr__pfet_01v8_hvt (5) |sky130_fd_pr__pfet_01v8_hvt (5)
+sky130_fd_pr__nfet_01v8 (5) |sky130_fd_pr__nfet_01v8 (5)
+Number of devices: 10 |Number of devices: 10
+Number of nets: 13 |Number of nets: 13
+---------------------------------------------------------------------------------------
+Netlists match uniquely.
+
+Subcircuit pins:
+Circuit 1: sky130_fd_sc_hd__a22o_1 |Circuit 2: sky130_fd_sc_hd__a22o_1
+-------------------------------------------|-------------------------------------------
+VPB |VPB
+VNB |VNB
+A2 |A2
+A1 |A1
+B1 |B1
+X |X
+B2 |B2
+VPWR |VPWR
+VGND |VGND
+---------------------------------------------------------------------------------------
+Cell pin lists are equivalent.
+Device classes sky130_fd_sc_hd__a22o_1 and sky130_fd_sc_hd__a22o_1 are equivalent.
+
+Subcircuit summary:
+Circuit 1: sky130_fd_sc_hd__or3b_1 |Circuit 2: sky130_fd_sc_hd__or3b_1
+-------------------------------------------|-------------------------------------------
+sky130_fd_pr__nfet_01v8 (5) |sky130_fd_pr__nfet_01v8 (5)
+sky130_fd_pr__pfet_01v8_hvt (5) |sky130_fd_pr__pfet_01v8_hvt (5)
+Number of devices: 10 |Number of devices: 10
+Number of nets: 12 |Number of nets: 12
+---------------------------------------------------------------------------------------
+Netlists match uniquely.
+
+Subcircuit pins:
+Circuit 1: sky130_fd_sc_hd__or3b_1 |Circuit 2: sky130_fd_sc_hd__or3b_1
+-------------------------------------------|-------------------------------------------
+VPWR |VPWR
+VGND |VGND
+VNB |VNB
+VPB |VPB
+X |X
+B |B
+A |A
+C_N |C_N
+---------------------------------------------------------------------------------------
+Cell pin lists are equivalent.
+Device classes sky130_fd_sc_hd__or3b_1 and sky130_fd_sc_hd__or3b_1 are equivalent.
+
+Subcircuit summary:
+Circuit 1: sky130_fd_sc_hd__and3_1 |Circuit 2: sky130_fd_sc_hd__and3_1
+-------------------------------------------|-------------------------------------------
+sky130_fd_pr__pfet_01v8_hvt (4) |sky130_fd_pr__pfet_01v8_hvt (4)
+sky130_fd_pr__nfet_01v8 (4) |sky130_fd_pr__nfet_01v8 (4)
+Number of devices: 8 |Number of devices: 8
+Number of nets: 11 |Number of nets: 11
+---------------------------------------------------------------------------------------
+Netlists match uniquely.
+
+Subcircuit pins:
+Circuit 1: sky130_fd_sc_hd__and3_1 |Circuit 2: sky130_fd_sc_hd__and3_1
+-------------------------------------------|-------------------------------------------
+VGND |VGND
+A |A
+B |B
+C |C
+X |X
+VNB |VNB
+VPWR |VPWR
+VPB |VPB
+---------------------------------------------------------------------------------------
+Cell pin lists are equivalent.
+Device classes sky130_fd_sc_hd__and3_1 and sky130_fd_sc_hd__and3_1 are equivalent.
+
+Subcircuit summary:
+Circuit 1: sky130_fd_sc_hd__o22a_1 |Circuit 2: sky130_fd_sc_hd__o22a_1
+-------------------------------------------|-------------------------------------------
+sky130_fd_pr__nfet_01v8 (5) |sky130_fd_pr__nfet_01v8 (5)
+sky130_fd_pr__pfet_01v8_hvt (5) |sky130_fd_pr__pfet_01v8_hvt (5)
+Number of devices: 10 |Number of devices: 10
+Number of nets: 13 |Number of nets: 13
+---------------------------------------------------------------------------------------
+Netlists match uniquely.
+
+Subcircuit pins:
+Circuit 1: sky130_fd_sc_hd__o22a_1 |Circuit 2: sky130_fd_sc_hd__o22a_1
+-------------------------------------------|-------------------------------------------
+VPWR |VPWR
+VGND |VGND
+VPB |VPB
+VNB |VNB
+B1 |B1
+X |X
+B2 |B2
+A1 |A1
+A2 |A2
+---------------------------------------------------------------------------------------
+Cell pin lists are equivalent.
+Device classes sky130_fd_sc_hd__o22a_1 and sky130_fd_sc_hd__o22a_1 are equivalent.
+
+Class sky130_fd_sc_hd__a22o_2 (0): Merged 2 parallel devices.
+Class sky130_fd_sc_hd__a22o_2 (1): Merged 2 parallel devices.
+Subcircuit summary:
+Circuit 1: sky130_fd_sc_hd__a22o_2 |Circuit 2: sky130_fd_sc_hd__a22o_2
+-------------------------------------------|-------------------------------------------
+sky130_fd_pr__pfet_01v8_hvt (6->5) |sky130_fd_pr__pfet_01v8_hvt (6->5)
+sky130_fd_pr__nfet_01v8 (6->5) |sky130_fd_pr__nfet_01v8 (6->5)
+Number of devices: 10 |Number of devices: 10
+Number of nets: 13 |Number of nets: 13
+---------------------------------------------------------------------------------------
+Netlists match uniquely.
+
+Subcircuit pins:
+Circuit 1: sky130_fd_sc_hd__a22o_2 |Circuit 2: sky130_fd_sc_hd__a22o_2
+-------------------------------------------|-------------------------------------------
+VPB |VPB
+VNB |VNB
+X |X
+A2 |A2
+B1 |B1
+A1 |A1
+B2 |B2
+VPWR |VPWR
+VGND |VGND
+---------------------------------------------------------------------------------------
+Cell pin lists are equivalent.
+Device classes sky130_fd_sc_hd__a22o_2 and sky130_fd_sc_hd__a22o_2 are equivalent.
+
+Class sky130_fd_sc_hd__a22o_4 (0): Merged 14 parallel devices.
+Class sky130_fd_sc_hd__a22o_4 (1): Merged 14 parallel devices.
+Subcircuit summary:
+Circuit 1: sky130_fd_sc_hd__a22o_4 |Circuit 2: sky130_fd_sc_hd__a22o_4
+-------------------------------------------|-------------------------------------------
+sky130_fd_pr__pfet_01v8_hvt (12->5) |sky130_fd_pr__pfet_01v8_hvt (12->5)
+sky130_fd_pr__nfet_01v8 (12->5) |sky130_fd_pr__nfet_01v8 (12->5)
+Number of devices: 10 |Number of devices: 10
+Number of nets: 13 |Number of nets: 13
+---------------------------------------------------------------------------------------
+Netlists match uniquely.
+
+Subcircuit pins:
+Circuit 1: sky130_fd_sc_hd__a22o_4 |Circuit 2: sky130_fd_sc_hd__a22o_4
+-------------------------------------------|-------------------------------------------
+VPWR |VPWR
+VGND |VGND
+VPB |VPB
+VNB |VNB
+A1 |A1
+X |X
+B2 |B2
+A2 |A2
+B1 |B1
+---------------------------------------------------------------------------------------
+Cell pin lists are equivalent.
+Device classes sky130_fd_sc_hd__a22o_4 and sky130_fd_sc_hd__a22o_4 are equivalent.
+
+Subcircuit summary:
+Circuit 1: sky130_fd_sc_hd__and2b_1 |Circuit 2: sky130_fd_sc_hd__and2b_1
+-------------------------------------------|-------------------------------------------
+sky130_fd_pr__pfet_01v8_hvt (4) |sky130_fd_pr__pfet_01v8_hvt (4)
+sky130_fd_pr__nfet_01v8 (4) |sky130_fd_pr__nfet_01v8 (4)
+Number of devices: 8 |Number of devices: 8
+Number of nets: 10 |Number of nets: 10
+---------------------------------------------------------------------------------------
+Netlists match uniquely.
+
+Subcircuit pins:
+Circuit 1: sky130_fd_sc_hd__and2b_1 |Circuit 2: sky130_fd_sc_hd__and2b_1
+-------------------------------------------|-------------------------------------------
+VGND |VGND
+B |B
+X |X
+A_N |A_N
+VPWR |VPWR
+VPB |VPB
+VNB |VNB
+---------------------------------------------------------------------------------------
+Cell pin lists are equivalent.
+Device classes sky130_fd_sc_hd__and2b_1 and sky130_fd_sc_hd__and2b_1 are equivalent.
+
+Class sky130_fd_sc_hd__dfxtp_2 (0): Merged 2 parallel devices.
+Class sky130_fd_sc_hd__dfxtp_2 (1): Merged 2 parallel devices.
+Subcircuit summary:
+Circuit 1: sky130_fd_sc_hd__dfxtp_2 |Circuit 2: sky130_fd_sc_hd__dfxtp_2
+-------------------------------------------|-------------------------------------------
+sky130_fd_pr__nfet_01v8 (13->12) |sky130_fd_pr__nfet_01v8 (13->12)
+sky130_fd_pr__pfet_01v8_hvt (13->12) |sky130_fd_pr__pfet_01v8_hvt (13->12)
+Number of devices: 24 |Number of devices: 24
+Number of nets: 18 |Number of nets: 18
+---------------------------------------------------------------------------------------
+Netlists match uniquely.
+
+Subcircuit pins:
+Circuit 1: sky130_fd_sc_hd__dfxtp_2 |Circuit 2: sky130_fd_sc_hd__dfxtp_2
+-------------------------------------------|-------------------------------------------
+VPB |VPB
+VNB |VNB
+VGND |VGND
+VPWR |VPWR
+D |D
+Q |Q
+CLK |CLK
+---------------------------------------------------------------------------------------
+Cell pin lists are equivalent.
+Device classes sky130_fd_sc_hd__dfxtp_2 and sky130_fd_sc_hd__dfxtp_2 are equivalent.
+
+Subcircuit summary:
+Circuit 1: sky130_fd_sc_hd__o21ai_1 |Circuit 2: sky130_fd_sc_hd__o21ai_1
+-------------------------------------------|-------------------------------------------
+sky130_fd_pr__pfet_01v8_hvt (3) |sky130_fd_pr__pfet_01v8_hvt (3)
+sky130_fd_pr__nfet_01v8 (3) |sky130_fd_pr__nfet_01v8 (3)
+Number of devices: 6 |Number of devices: 6
+Number of nets: 10 |Number of nets: 10
+---------------------------------------------------------------------------------------
+Netlists match uniquely.
+
+Subcircuit pins:
+Circuit 1: sky130_fd_sc_hd__o21ai_1 |Circuit 2: sky130_fd_sc_hd__o21ai_1
+-------------------------------------------|-------------------------------------------
+A2 |A2
+B1 |B1
+VPWR |VPWR
+A1 |A1
+VGND |VGND
+Y |Y
+VPB |VPB
+VNB |VNB
+---------------------------------------------------------------------------------------
+Cell pin lists are equivalent.
+Device classes sky130_fd_sc_hd__o21ai_1 and sky130_fd_sc_hd__o21ai_1 are equivalent.
+
+Subcircuit summary:
+Circuit 1: sky130_fd_sc_hd__and4_1 |Circuit 2: sky130_fd_sc_hd__and4_1
+-------------------------------------------|-------------------------------------------
+sky130_fd_pr__pfet_01v8_hvt (5) |sky130_fd_pr__pfet_01v8_hvt (5)
+sky130_fd_pr__nfet_01v8 (5) |sky130_fd_pr__nfet_01v8 (5)
+Number of devices: 10 |Number of devices: 10
+Number of nets: 13 |Number of nets: 13
+---------------------------------------------------------------------------------------
+Netlists match uniquely.
+
+Subcircuit pins:
+Circuit 1: sky130_fd_sc_hd__and4_1 |Circuit 2: sky130_fd_sc_hd__and4_1
+-------------------------------------------|-------------------------------------------
+VNB |VNB
+VPWR |VPWR
+VPB |VPB
+VGND |VGND
+X |X
+D |D
+B |B
+C |C
+A |A
+---------------------------------------------------------------------------------------
+Cell pin lists are equivalent.
+Device classes sky130_fd_sc_hd__and4_1 and sky130_fd_sc_hd__and4_1 are equivalent.
+
+Class sky130_fd_sc_hd__a311oi_4 (0): Merged 30 parallel devices.
+Class sky130_fd_sc_hd__a311oi_4 (1): Merged 30 parallel devices.
+Subcircuit summary:
+Circuit 1: sky130_fd_sc_hd__a311oi_4 |Circuit 2: sky130_fd_sc_hd__a311oi_4
+-------------------------------------------|-------------------------------------------
+sky130_fd_pr__nfet_01v8 (20->5) |sky130_fd_pr__nfet_01v8 (20->5)
+sky130_fd_pr__pfet_01v8_hvt (20->5) |sky130_fd_pr__pfet_01v8_hvt (20->5)
+Number of devices: 10 |Number of devices: 10
+Number of nets: 14 |Number of nets: 14
+---------------------------------------------------------------------------------------
+Netlists match uniquely.
+
+Subcircuit pins:
+Circuit 1: sky130_fd_sc_hd__a311oi_4 |Circuit 2: sky130_fd_sc_hd__a311oi_4
+-------------------------------------------|-------------------------------------------
+Y |Y
+VPWR |VPWR
+VGND |VGND
+VPB |VPB
+VNB |VNB
+A1 |A1
+A2 |A2
+B1 |B1
+C1 |C1
+A3 |A3
+---------------------------------------------------------------------------------------
+Cell pin lists are equivalent.
+Device classes sky130_fd_sc_hd__a311oi_4 and sky130_fd_sc_hd__a311oi_4 are equivalent.
+
+Class sky130_fd_sc_hd__a221o_4 (0): Merged 16 parallel devices.
+Class sky130_fd_sc_hd__a221o_4 (1): Merged 16 parallel devices.
+Subcircuit summary:
+Circuit 1: sky130_fd_sc_hd__a221o_4 |Circuit 2: sky130_fd_sc_hd__a221o_4
+-------------------------------------------|-------------------------------------------
+sky130_fd_pr__nfet_01v8 (14->6) |sky130_fd_pr__nfet_01v8 (14->6)
+sky130_fd_pr__pfet_01v8_hvt (14->6) |sky130_fd_pr__pfet_01v8_hvt (14->6)
+Number of devices: 12 |Number of devices: 12
+Number of nets: 15 |Number of nets: 15
+---------------------------------------------------------------------------------------
+Netlists match uniquely.
+
+Subcircuit pins:
+Circuit 1: sky130_fd_sc_hd__a221o_4 |Circuit 2: sky130_fd_sc_hd__a221o_4
+-------------------------------------------|-------------------------------------------
+VPWR |VPWR
+VNB |VNB
+VPB |VPB
+C1 |C1
+B2 |B2
+A2 |A2
+A1 |A1
+B1 |B1
+X |X
+VGND |VGND
+---------------------------------------------------------------------------------------
+Cell pin lists are equivalent.
+Device classes sky130_fd_sc_hd__a221o_4 and sky130_fd_sc_hd__a221o_4 are equivalent.
+
+Class sky130_fd_sc_hd__inv_2 (0): Merged 2 parallel devices.
+Class sky130_fd_sc_hd__inv_2 (1): Merged 2 parallel devices.
+Subcircuit summary:
+Circuit 1: sky130_fd_sc_hd__inv_2 |Circuit 2: sky130_fd_sc_hd__inv_2
+-------------------------------------------|-------------------------------------------
+sky130_fd_pr__pfet_01v8_hvt (2->1) |sky130_fd_pr__pfet_01v8_hvt (2->1)
+sky130_fd_pr__nfet_01v8 (2->1) |sky130_fd_pr__nfet_01v8 (2->1)
+Number of devices: 2 |Number of devices: 2
+Number of nets: 6 |Number of nets: 6
+---------------------------------------------------------------------------------------
+Netlists match uniquely.
+
+Subcircuit pins:
+Circuit 1: sky130_fd_sc_hd__inv_2 |Circuit 2: sky130_fd_sc_hd__inv_2
+-------------------------------------------|-------------------------------------------
+VGND |VGND
+VNB |VNB
+VPWR |VPWR
+VPB |VPB
+Y |Y
+A |A
+---------------------------------------------------------------------------------------
+Cell pin lists are equivalent.
+Device classes sky130_fd_sc_hd__inv_2 and sky130_fd_sc_hd__inv_2 are equivalent.
+
+Subcircuit summary:
+Circuit 1: sky130_fd_sc_hd__a311o_1 |Circuit 2: sky130_fd_sc_hd__a311o_1
+-------------------------------------------|-------------------------------------------
+sky130_fd_pr__nfet_01v8 (6) |sky130_fd_pr__nfet_01v8 (6)
+sky130_fd_pr__pfet_01v8_hvt (6) |sky130_fd_pr__pfet_01v8_hvt (6)
+Number of devices: 12 |Number of devices: 12
+Number of nets: 15 |Number of nets: 15
+---------------------------------------------------------------------------------------
+Netlists match uniquely.
+
+Subcircuit pins:
+Circuit 1: sky130_fd_sc_hd__a311o_1 |Circuit 2: sky130_fd_sc_hd__a311o_1
+-------------------------------------------|-------------------------------------------
+VPWR |VPWR
+VGND |VGND
+A1 |A1
+A3 |A3
+B1 |B1
+C1 |C1
+A2 |A2
+X |X
+VPB |VPB
+VNB |VNB
+---------------------------------------------------------------------------------------
+Cell pin lists are equivalent.
+Device classes sky130_fd_sc_hd__a311o_1 and sky130_fd_sc_hd__a311o_1 are equivalent.
+
+Class sky130_fd_sc_hd__mux4_2 (0): Merged 2 parallel devices.
+Class sky130_fd_sc_hd__mux4_2 (1): Merged 2 parallel devices.
+Subcircuit summary:
+Circuit 1: sky130_fd_sc_hd__mux4_2 |Circuit 2: sky130_fd_sc_hd__mux4_2
+-------------------------------------------|-------------------------------------------
+sky130_fd_pr__pfet_01v8_hvt (14->13) |sky130_fd_pr__pfet_01v8_hvt (14->13)
+sky130_fd_pr__nfet_01v8 (14->13) |sky130_fd_pr__nfet_01v8 (14->13)
+Number of devices: 26 |Number of devices: 26
+Number of nets: 24 |Number of nets: 24
+---------------------------------------------------------------------------------------
+Netlists match uniquely.
+
+Subcircuit pins:
+Circuit 1: sky130_fd_sc_hd__mux4_2 |Circuit 2: sky130_fd_sc_hd__mux4_2
+-------------------------------------------|-------------------------------------------
+X |X
+A1 |A1
+A3 |A3
+A0 |A0
+A2 |A2
+S0 |S0
+VPB |VPB
+VNB |VNB
+VPWR |VPWR
+VGND |VGND
+S1 |S1
+---------------------------------------------------------------------------------------
+Cell pin lists are equivalent.
+Device classes sky130_fd_sc_hd__mux4_2 and sky130_fd_sc_hd__mux4_2 are equivalent.
+
+Class sky130_fd_sc_hd__and3b_4 (0): Merged 6 parallel devices.
+Class sky130_fd_sc_hd__and3b_4 (1): Merged 6 parallel devices.
+Subcircuit summary:
+Circuit 1: sky130_fd_sc_hd__and3b_4 |Circuit 2: sky130_fd_sc_hd__and3b_4
+-------------------------------------------|-------------------------------------------
+sky130_fd_pr__nfet_01v8 (8->5) |sky130_fd_pr__nfet_01v8 (8->5)
+sky130_fd_pr__pfet_01v8_hvt (8->5) |sky130_fd_pr__pfet_01v8_hvt (8->5)
+Number of devices: 10 |Number of devices: 10
+Number of nets: 12 |Number of nets: 12
+---------------------------------------------------------------------------------------
+Netlists match uniquely.
+
+Subcircuit pins:
+Circuit 1: sky130_fd_sc_hd__and3b_4 |Circuit 2: sky130_fd_sc_hd__and3b_4
+-------------------------------------------|-------------------------------------------
+VNB |VNB
+VPWR |VPWR
+VPB |VPB
+VGND |VGND
+X |X
+C |C
+B |B
+A_N |A_N
+---------------------------------------------------------------------------------------
+Cell pin lists are equivalent.
+Device classes sky130_fd_sc_hd__and3b_4 and sky130_fd_sc_hd__and3b_4 are equivalent.
+
+Subcircuit summary:
+Circuit 1: sky130_fd_sc_hd__a2111o_1 |Circuit 2: sky130_fd_sc_hd__a2111o_1
+-------------------------------------------|-------------------------------------------
+sky130_fd_pr__nfet_01v8 (6) |sky130_fd_pr__nfet_01v8 (6)
+sky130_fd_pr__pfet_01v8_hvt (6) |sky130_fd_pr__pfet_01v8_hvt (6)
+Number of devices: 12 |Number of devices: 12
+Number of nets: 15 |Number of nets: 15
+---------------------------------------------------------------------------------------
+Netlists match uniquely.
+
+Subcircuit pins:
+Circuit 1: sky130_fd_sc_hd__a2111o_1 |Circuit 2: sky130_fd_sc_hd__a2111o_1
+-------------------------------------------|-------------------------------------------
+VPWR |VPWR
+VNB |VNB
+VPB |VPB
+D1 |D1
+X |X
+A1 |A1
+B1 |B1
+A2 |A2
+C1 |C1
+VGND |VGND
+---------------------------------------------------------------------------------------
+Cell pin lists are equivalent.
+Device classes sky130_fd_sc_hd__a2111o_1 and sky130_fd_sc_hd__a2111o_1 are equivalent.
+
+Subcircuit summary:
+Circuit 1: sky130_fd_sc_hd__nor4_1 |Circuit 2: sky130_fd_sc_hd__nor4_1
+-------------------------------------------|-------------------------------------------
+sky130_fd_pr__nfet_01v8 (4) |sky130_fd_pr__nfet_01v8 (4)
+sky130_fd_pr__pfet_01v8_hvt (4) |sky130_fd_pr__pfet_01v8_hvt (4)
+Number of devices: 8 |Number of devices: 8
+Number of nets: 12 |Number of nets: 12
+---------------------------------------------------------------------------------------
+Netlists match uniquely.
+
+Subcircuit pins:
+Circuit 1: sky130_fd_sc_hd__nor4_1 |Circuit 2: sky130_fd_sc_hd__nor4_1
+-------------------------------------------|-------------------------------------------
+VPWR |VPWR
+VGND |VGND
+VNB |VNB
+VPB |VPB
+A |A
+C |C
+B |B
+D |D
+Y |Y
+---------------------------------------------------------------------------------------
+Cell pin lists are equivalent.
+Device classes sky130_fd_sc_hd__nor4_1 and sky130_fd_sc_hd__nor4_1 are equivalent.
+
+Class sky130_fd_sc_hd__o21ai_4 (0): Merged 18 parallel devices.
+Class sky130_fd_sc_hd__o21ai_4 (1): Merged 18 parallel devices.
+Subcircuit summary:
+Circuit 1: sky130_fd_sc_hd__o21ai_4 |Circuit 2: sky130_fd_sc_hd__o21ai_4
+-------------------------------------------|-------------------------------------------
+sky130_fd_pr__pfet_01v8_hvt (12->3) |sky130_fd_pr__pfet_01v8_hvt (12->3)
+sky130_fd_pr__nfet_01v8 (12->3) |sky130_fd_pr__nfet_01v8 (12->3)
+Number of devices: 6 |Number of devices: 6
+Number of nets: 10 |Number of nets: 10
+---------------------------------------------------------------------------------------
+Netlists match uniquely.
+
+Subcircuit pins:
+Circuit 1: sky130_fd_sc_hd__o21ai_4 |Circuit 2: sky130_fd_sc_hd__o21ai_4
+-------------------------------------------|-------------------------------------------
+Y |Y
+VPB |VPB
+VNB |VNB
+A2 |A2
+VGND |VGND
+A1 |A1
+B1 |B1
+VPWR |VPWR
+---------------------------------------------------------------------------------------
+Cell pin lists are equivalent.
+Device classes sky130_fd_sc_hd__o21ai_4 and sky130_fd_sc_hd__o21ai_4 are equivalent.
+
+Subcircuit summary:
+Circuit 1: sky130_fd_sc_hd__o21ba_1 |Circuit 2: sky130_fd_sc_hd__o21ba_1
+-------------------------------------------|-------------------------------------------
+sky130_fd_pr__nfet_01v8 (5) |sky130_fd_pr__nfet_01v8 (5)
+sky130_fd_pr__pfet_01v8_hvt (5) |sky130_fd_pr__pfet_01v8_hvt (5)
+Number of devices: 10 |Number of devices: 10
+Number of nets: 12 |Number of nets: 12
+---------------------------------------------------------------------------------------
+Netlists match uniquely.
+
+Subcircuit pins:
+Circuit 1: sky130_fd_sc_hd__o21ba_1 |Circuit 2: sky130_fd_sc_hd__o21ba_1
+-------------------------------------------|-------------------------------------------
+VNB |VNB
+VPB |VPB
+A2 |A2
+B1_N |B1_N
+A1 |A1
+X |X
+VGND |VGND
+VPWR |VPWR
+---------------------------------------------------------------------------------------
+Cell pin lists are equivalent.
+Device classes sky130_fd_sc_hd__o21ba_1 and sky130_fd_sc_hd__o21ba_1 are equivalent.
+
+Class sky130_fd_sc_hd__clkbuf_8 (0): Merged 16 parallel devices.
+Class sky130_fd_sc_hd__clkbuf_8 (1): Merged 16 parallel devices.
+Subcircuit summary:
+Circuit 1: sky130_fd_sc_hd__clkbuf_8 |Circuit 2: sky130_fd_sc_hd__clkbuf_8
+-------------------------------------------|-------------------------------------------
+sky130_fd_pr__pfet_01v8_hvt (10->2) |sky130_fd_pr__pfet_01v8_hvt (10->2)
+sky130_fd_pr__nfet_01v8 (10->2) |sky130_fd_pr__nfet_01v8 (10->2)
+Number of devices: 4 |Number of devices: 4
+Number of nets: 7 |Number of nets: 7
+---------------------------------------------------------------------------------------
+Netlists match uniquely.
+
+Subcircuit pins:
+Circuit 1: sky130_fd_sc_hd__clkbuf_8 |Circuit 2: sky130_fd_sc_hd__clkbuf_8
+-------------------------------------------|-------------------------------------------
+X |X
+VGND |VGND
+VNB |VNB
+A |A
+VPWR |VPWR
+VPB |VPB
+---------------------------------------------------------------------------------------
+Cell pin lists are equivalent.
+Device classes sky130_fd_sc_hd__clkbuf_8 and sky130_fd_sc_hd__clkbuf_8 are equivalent.
+
+Class sky130_fd_sc_hd__a31oi_4 (0): Merged 24 parallel devices.
+Class sky130_fd_sc_hd__a31oi_4 (1): Merged 24 parallel devices.
+Subcircuit summary:
+Circuit 1: sky130_fd_sc_hd__a31oi_4 |Circuit 2: sky130_fd_sc_hd__a31oi_4
+-------------------------------------------|-------------------------------------------
+sky130_fd_pr__nfet_01v8 (16->4) |sky130_fd_pr__nfet_01v8 (16->4)
+sky130_fd_pr__pfet_01v8_hvt (16->4) |sky130_fd_pr__pfet_01v8_hvt (16->4)
+Number of devices: 8 |Number of devices: 8
+Number of nets: 12 |Number of nets: 12
+---------------------------------------------------------------------------------------
+Netlists match uniquely.
+
+Subcircuit pins:
+Circuit 1: sky130_fd_sc_hd__a31oi_4 |Circuit 2: sky130_fd_sc_hd__a31oi_4
+-------------------------------------------|-------------------------------------------
+Y |Y
+VPWR |VPWR
+VPB |VPB
+VNB |VNB
+B1 |B1
+A1 |A1
+VGND |VGND
+A3 |A3
+A2 |A2
+---------------------------------------------------------------------------------------
+Cell pin lists are equivalent.
+Device classes sky130_fd_sc_hd__a31oi_4 and sky130_fd_sc_hd__a31oi_4 are equivalent.
+
+Subcircuit summary:
+Circuit 1: sky130_fd_sc_hd__nand4_1 |Circuit 2: sky130_fd_sc_hd__nand4_1
+-------------------------------------------|-------------------------------------------
+sky130_fd_pr__pfet_01v8_hvt (4) |sky130_fd_pr__pfet_01v8_hvt (4)
+sky130_fd_pr__nfet_01v8 (4) |sky130_fd_pr__nfet_01v8 (4)
+Number of devices: 8 |Number of devices: 8
+Number of nets: 12 |Number of nets: 12
+---------------------------------------------------------------------------------------
+Netlists match uniquely.
+
+Subcircuit pins:
+Circuit 1: sky130_fd_sc_hd__nand4_1 |Circuit 2: sky130_fd_sc_hd__nand4_1
+-------------------------------------------|-------------------------------------------
+VGND |VGND
+VNB |VNB
+VPWR |VPWR
+VPB |VPB
+A |A
+C |C
+B |B
+D |D
+Y |Y
+---------------------------------------------------------------------------------------
+Cell pin lists are equivalent.
+Device classes sky130_fd_sc_hd__nand4_1 and sky130_fd_sc_hd__nand4_1 are equivalent.
+
+Subcircuit summary:
+Circuit 1: sky130_fd_sc_hd__or4b_1 |Circuit 2: sky130_fd_sc_hd__or4b_1
+-------------------------------------------|-------------------------------------------
+sky130_fd_pr__pfet_01v8_hvt (6) |sky130_fd_pr__pfet_01v8_hvt (6)
+sky130_fd_pr__nfet_01v8 (6) |sky130_fd_pr__nfet_01v8 (6)
+Number of devices: 12 |Number of devices: 12
+Number of nets: 14 |Number of nets: 14
+---------------------------------------------------------------------------------------
+Netlists match uniquely.
+
+Subcircuit pins:
+Circuit 1: sky130_fd_sc_hd__or4b_1 |Circuit 2: sky130_fd_sc_hd__or4b_1
+-------------------------------------------|-------------------------------------------
+VGND |VGND
+VNB |VNB
+VPB |VPB
+VPWR |VPWR
+A |A
+B |B
+C |C
+X |X
+D_N |D_N
+---------------------------------------------------------------------------------------
+Cell pin lists are equivalent.
+Device classes sky130_fd_sc_hd__or4b_1 and sky130_fd_sc_hd__or4b_1 are equivalent.
+
+Subcircuit summary:
+Circuit 1: sky130_fd_sc_hd__nor3_1 |Circuit 2: sky130_fd_sc_hd__nor3_1
+-------------------------------------------|-------------------------------------------
+sky130_fd_pr__pfet_01v8_hvt (3) |sky130_fd_pr__pfet_01v8_hvt (3)
+sky130_fd_pr__nfet_01v8 (3) |sky130_fd_pr__nfet_01v8 (3)
+Number of devices: 6 |Number of devices: 6
+Number of nets: 10 |Number of nets: 10
+---------------------------------------------------------------------------------------
+Netlists match uniquely.
+
+Subcircuit pins:
+Circuit 1: sky130_fd_sc_hd__nor3_1 |Circuit 2: sky130_fd_sc_hd__nor3_1
+-------------------------------------------|-------------------------------------------
+Y |Y
+VGND |VGND
+VNB |VNB
+VPB |VPB
+A |A
+B |B
+C |C
+VPWR |VPWR
+---------------------------------------------------------------------------------------
+Cell pin lists are equivalent.
+Device classes sky130_fd_sc_hd__nor3_1 and sky130_fd_sc_hd__nor3_1 are equivalent.
+
+Class sky130_fd_sc_hd__nor2_2 (0): Merged 4 parallel devices.
+Class sky130_fd_sc_hd__nor2_2 (1): Merged 4 parallel devices.
+Subcircuit summary:
+Circuit 1: sky130_fd_sc_hd__nor2_2 |Circuit 2: sky130_fd_sc_hd__nor2_2
+-------------------------------------------|-------------------------------------------
+sky130_fd_pr__pfet_01v8_hvt (4->2) |sky130_fd_pr__pfet_01v8_hvt (4->2)
+sky130_fd_pr__nfet_01v8 (4->2) |sky130_fd_pr__nfet_01v8 (4->2)
+Number of devices: 4 |Number of devices: 4
+Number of nets: 8 |Number of nets: 8
+---------------------------------------------------------------------------------------
+Netlists match uniquely.
+
+Subcircuit pins:
+Circuit 1: sky130_fd_sc_hd__nor2_2 |Circuit 2: sky130_fd_sc_hd__nor2_2
+-------------------------------------------|-------------------------------------------
+VPWR |VPWR
+B |B
+VGND |VGND
+VNB |VNB
+A |A
+VPB |VPB
+Y |Y
+---------------------------------------------------------------------------------------
+Cell pin lists are equivalent.
+Device classes sky130_fd_sc_hd__nor2_2 and sky130_fd_sc_hd__nor2_2 are equivalent.
+
+Subcircuit summary:
+Circuit 1: sky130_fd_sc_hd__or2_1 |Circuit 2: sky130_fd_sc_hd__or2_1
+-------------------------------------------|-------------------------------------------
+sky130_fd_pr__nfet_01v8 (3) |sky130_fd_pr__nfet_01v8 (3)
+sky130_fd_pr__pfet_01v8_hvt (3) |sky130_fd_pr__pfet_01v8_hvt (3)
+Number of devices: 6 |Number of devices: 6
+Number of nets: 9 |Number of nets: 9
+---------------------------------------------------------------------------------------
+Netlists match uniquely.
+
+Subcircuit pins:
+Circuit 1: sky130_fd_sc_hd__or2_1 |Circuit 2: sky130_fd_sc_hd__or2_1
+-------------------------------------------|-------------------------------------------
+A |A
+VPWR |VPWR
+X |X
+B |B
+VPB |VPB
+VGND |VGND
+VNB |VNB
+---------------------------------------------------------------------------------------
+Cell pin lists are equivalent.
+Device classes sky130_fd_sc_hd__or2_1 and sky130_fd_sc_hd__or2_1 are equivalent.
+
+Class sky130_fd_sc_hd__nand2_8 (0): Merged 28 parallel devices.
+Class sky130_fd_sc_hd__nand2_8 (1): Merged 28 parallel devices.
+Subcircuit summary:
+Circuit 1: sky130_fd_sc_hd__nand2_8 |Circuit 2: sky130_fd_sc_hd__nand2_8
+-------------------------------------------|-------------------------------------------
+sky130_fd_pr__nfet_01v8 (16->2) |sky130_fd_pr__nfet_01v8 (16->2)
+sky130_fd_pr__pfet_01v8_hvt (16->2) |sky130_fd_pr__pfet_01v8_hvt (16->2)
+Number of devices: 4 |Number of devices: 4
+Number of nets: 8 |Number of nets: 8
+---------------------------------------------------------------------------------------
+Netlists match uniquely.
+
+Subcircuit pins:
+Circuit 1: sky130_fd_sc_hd__nand2_8 |Circuit 2: sky130_fd_sc_hd__nand2_8
+-------------------------------------------|-------------------------------------------
+Y |Y
+VGND |VGND
+A |A
+VPWR |VPWR
+VPB |VPB
+B |B
+VNB |VNB
+---------------------------------------------------------------------------------------
+Cell pin lists are equivalent.
+Device classes sky130_fd_sc_hd__nand2_8 and sky130_fd_sc_hd__nand2_8 are equivalent.
+
+Subcircuit summary:
+Circuit 1: sky130_fd_sc_hd__a311oi_1 |Circuit 2: sky130_fd_sc_hd__a311oi_1
+-------------------------------------------|-------------------------------------------
+sky130_fd_pr__nfet_01v8 (5) |sky130_fd_pr__nfet_01v8 (5)
+sky130_fd_pr__pfet_01v8_hvt (5) |sky130_fd_pr__pfet_01v8_hvt (5)
+Number of devices: 10 |Number of devices: 10
+Number of nets: 14 |Number of nets: 14
+---------------------------------------------------------------------------------------
+Netlists match uniquely.
+
+Subcircuit pins:
+Circuit 1: sky130_fd_sc_hd__a311oi_1 |Circuit 2: sky130_fd_sc_hd__a311oi_1
+-------------------------------------------|-------------------------------------------
+VPWR |VPWR
+VGND |VGND
+VPB |VPB
+VNB |VNB
+A1 |A1
+A2 |A2
+A3 |A3
+B1 |B1
+C1 |C1
+Y |Y
+---------------------------------------------------------------------------------------
+Cell pin lists are equivalent.
+Device classes sky130_fd_sc_hd__a311oi_1 and sky130_fd_sc_hd__a311oi_1 are equivalent.
+
+Class sky130_fd_sc_hd__clkinv_16 (0): Merged 38 parallel devices.
+Class sky130_fd_sc_hd__clkinv_16 (1): Merged 38 parallel devices.
+Subcircuit summary:
+Circuit 1: sky130_fd_sc_hd__clkinv_16 |Circuit 2: sky130_fd_sc_hd__clkinv_16
+-------------------------------------------|-------------------------------------------
+sky130_fd_pr__nfet_01v8 (16->1) |sky130_fd_pr__nfet_01v8 (16->1)
+sky130_fd_pr__pfet_01v8_hvt (24->1) |sky130_fd_pr__pfet_01v8_hvt (24->1)
+Number of devices: 2 |Number of devices: 2
+Number of nets: 6 |Number of nets: 6
+---------------------------------------------------------------------------------------
+Netlists match uniquely.
+
+Subcircuit pins:
+Circuit 1: sky130_fd_sc_hd__clkinv_16 |Circuit 2: sky130_fd_sc_hd__clkinv_16
+-------------------------------------------|-------------------------------------------
+Y |Y
+A |A
+VPWR |VPWR
+VPB |VPB
+VGND |VGND
+VNB |VNB
+---------------------------------------------------------------------------------------
+Cell pin lists are equivalent.
+Device classes sky130_fd_sc_hd__clkinv_16 and sky130_fd_sc_hd__clkinv_16 are equivalent.
+
+Subcircuit summary:
+Circuit 1: sky130_fd_sc_hd__nand3_1 |Circuit 2: sky130_fd_sc_hd__nand3_1
+-------------------------------------------|-------------------------------------------
+sky130_fd_pr__pfet_01v8_hvt (3) |sky130_fd_pr__pfet_01v8_hvt (3)
+sky130_fd_pr__nfet_01v8 (3) |sky130_fd_pr__nfet_01v8 (3)
+Number of devices: 6 |Number of devices: 6
+Number of nets: 10 |Number of nets: 10
+---------------------------------------------------------------------------------------
+Netlists match uniquely.
+
+Subcircuit pins:
+Circuit 1: sky130_fd_sc_hd__nand3_1 |Circuit 2: sky130_fd_sc_hd__nand3_1
+-------------------------------------------|-------------------------------------------
+VGND |VGND
+Y |Y
+A |A
+B |B
+C |C
+VPWR |VPWR
+VPB |VPB
+VNB |VNB
+---------------------------------------------------------------------------------------
+Cell pin lists are equivalent.
+Device classes sky130_fd_sc_hd__nand3_1 and sky130_fd_sc_hd__nand3_1 are equivalent.
+
+Class sky130_fd_sc_hd__a221o_2 (0): Merged 2 parallel devices.
+Class sky130_fd_sc_hd__a221o_2 (1): Merged 2 parallel devices.
+Subcircuit summary:
+Circuit 1: sky130_fd_sc_hd__a221o_2 |Circuit 2: sky130_fd_sc_hd__a221o_2
+-------------------------------------------|-------------------------------------------
+sky130_fd_pr__pfet_01v8_hvt (7->6) |sky130_fd_pr__pfet_01v8_hvt (7->6)
+sky130_fd_pr__nfet_01v8 (7->6) |sky130_fd_pr__nfet_01v8 (7->6)
+Number of devices: 12 |Number of devices: 12
+Number of nets: 15 |Number of nets: 15
+---------------------------------------------------------------------------------------
+Netlists match uniquely.
+
+Subcircuit pins:
+Circuit 1: sky130_fd_sc_hd__a221o_2 |Circuit 2: sky130_fd_sc_hd__a221o_2
+-------------------------------------------|-------------------------------------------
+VGND |VGND
+X |X
+B1 |B1
+A1 |A1
+C1 |C1
+A2 |A2
+B2 |B2
+VPB |VPB
+VNB |VNB
+VPWR |VPWR
+---------------------------------------------------------------------------------------
+Cell pin lists are equivalent.
+Device classes sky130_fd_sc_hd__a221o_2 and sky130_fd_sc_hd__a221o_2 are equivalent.
+
+Class sky130_fd_sc_hd__a21o_4 (0): Merged 10 parallel devices.
+Class sky130_fd_sc_hd__a21o_4 (1): Merged 10 parallel devices.
+Subcircuit summary:
+Circuit 1: sky130_fd_sc_hd__a21o_4 |Circuit 2: sky130_fd_sc_hd__a21o_4
+-------------------------------------------|-------------------------------------------
+sky130_fd_pr__nfet_01v8 (10->6) |sky130_fd_pr__nfet_01v8 (10->6)
+sky130_fd_pr__pfet_01v8_hvt (10->4) |sky130_fd_pr__pfet_01v8_hvt (10->4)
+Number of devices: 10 |Number of devices: 10
+Number of nets: 12 |Number of nets: 12
+---------------------------------------------------------------------------------------
+Resolving automorphisms by property value.
+Resolving automorphisms by pin name.
+Netlists match uniquely.
+
+Subcircuit pins:
+Circuit 1: sky130_fd_sc_hd__a21o_4 |Circuit 2: sky130_fd_sc_hd__a21o_4
+-------------------------------------------|-------------------------------------------
+VPWR |VPWR
+A2 |A2
+A1 |A1
+VNB |VNB
+X |X
+B1 |B1
+VPB |VPB
+VGND |VGND
+---------------------------------------------------------------------------------------
+Cell pin lists are equivalent.
+Device classes sky130_fd_sc_hd__a21o_4 and sky130_fd_sc_hd__a21o_4 are equivalent.
+
+Subcircuit summary:
+Circuit 1: sky130_fd_sc_hd__a2bb2o_1 |Circuit 2: sky130_fd_sc_hd__a2bb2o_1
+-------------------------------------------|-------------------------------------------
+sky130_fd_pr__pfet_01v8_hvt (6) |sky130_fd_pr__pfet_01v8_hvt (6)
+sky130_fd_pr__nfet_01v8 (6) |sky130_fd_pr__nfet_01v8 (6)
+Number of devices: 12 |Number of devices: 12
+Number of nets: 14 |Number of nets: 14
+---------------------------------------------------------------------------------------
+Netlists match uniquely.
+
+Subcircuit pins:
+Circuit 1: sky130_fd_sc_hd__a2bb2o_1 |Circuit 2: sky130_fd_sc_hd__a2bb2o_1
+-------------------------------------------|-------------------------------------------
+VPWR |VPWR
+VPB |VPB
+VNB |VNB
+A1_N |A1_N
+A2_N |A2_N
+X |X
+B2 |B2
+B1 |B1
+VGND |VGND
+---------------------------------------------------------------------------------------
+Cell pin lists are equivalent.
+Device classes sky130_fd_sc_hd__a2bb2o_1 and sky130_fd_sc_hd__a2bb2o_1 are equivalent.
+
+Subcircuit summary:
+Circuit 1: sky130_fd_sc_hd__a21boi_1 |Circuit 2: sky130_fd_sc_hd__a21boi_1
+-------------------------------------------|-------------------------------------------
+sky130_fd_pr__pfet_01v8_hvt (4) |sky130_fd_pr__pfet_01v8_hvt (4)
+sky130_fd_pr__nfet_01v8 (4) |sky130_fd_pr__nfet_01v8 (4)
+Number of devices: 8 |Number of devices: 8
+Number of nets: 11 |Number of nets: 11
+---------------------------------------------------------------------------------------
+Netlists match uniquely.
+
+Subcircuit pins:
+Circuit 1: sky130_fd_sc_hd__a21boi_1 |Circuit 2: sky130_fd_sc_hd__a21boi_1
+-------------------------------------------|-------------------------------------------
+A1 |A1
+A2 |A2
+B1_N |B1_N
+VNB |VNB
+VPB |VPB
+VGND |VGND
+Y |Y
+VPWR |VPWR
+---------------------------------------------------------------------------------------
+Cell pin lists are equivalent.
+Device classes sky130_fd_sc_hd__a21boi_1 and sky130_fd_sc_hd__a21boi_1 are equivalent.
+
+Class sky130_fd_sc_hd__nand2_2 (0): Merged 4 parallel devices.
+Class sky130_fd_sc_hd__nand2_2 (1): Merged 4 parallel devices.
+Subcircuit summary:
+Circuit 1: sky130_fd_sc_hd__nand2_2 |Circuit 2: sky130_fd_sc_hd__nand2_2
+-------------------------------------------|-------------------------------------------
+sky130_fd_pr__pfet_01v8_hvt (4->2) |sky130_fd_pr__pfet_01v8_hvt (4->2)
+sky130_fd_pr__nfet_01v8 (4->2) |sky130_fd_pr__nfet_01v8 (4->2)
+Number of devices: 4 |Number of devices: 4
+Number of nets: 8 |Number of nets: 8
+---------------------------------------------------------------------------------------
+Netlists match uniquely.
+
+Subcircuit pins:
+Circuit 1: sky130_fd_sc_hd__nand2_2 |Circuit 2: sky130_fd_sc_hd__nand2_2
+-------------------------------------------|-------------------------------------------
+VGND |VGND
+Y |Y
+A |A
+VNB |VNB
+B |B
+VPWR |VPWR
+VPB |VPB
+---------------------------------------------------------------------------------------
+Cell pin lists are equivalent.
+Device classes sky130_fd_sc_hd__nand2_2 and sky130_fd_sc_hd__nand2_2 are equivalent.
+
+Class sky130_fd_sc_hd__a21oi_2 (0): Merged 4 parallel devices.
+Class sky130_fd_sc_hd__a21oi_2 (1): Merged 4 parallel devices.
+Subcircuit summary:
+Circuit 1: sky130_fd_sc_hd__a21oi_2 |Circuit 2: sky130_fd_sc_hd__a21oi_2
+-------------------------------------------|-------------------------------------------
+sky130_fd_pr__nfet_01v8 (6->5) |sky130_fd_pr__nfet_01v8 (6->5)
+sky130_fd_pr__pfet_01v8_hvt (6->3) |sky130_fd_pr__pfet_01v8_hvt (6->3)
+Number of devices: 8 |Number of devices: 8
+Number of nets: 11 |Number of nets: 11
+---------------------------------------------------------------------------------------
+Resolving automorphisms by property value.
+Resolving automorphisms by pin name.
+Netlists match uniquely.
+
+Subcircuit pins:
+Circuit 1: sky130_fd_sc_hd__a21oi_2 |Circuit 2: sky130_fd_sc_hd__a21oi_2
+-------------------------------------------|-------------------------------------------
+Y |Y
+VNB |VNB
+VPWR |VPWR
+B1 |B1
+VGND |VGND
+A2 |A2
+A1 |A1
+VPB |VPB
+---------------------------------------------------------------------------------------
+Cell pin lists are equivalent.
+Device classes sky130_fd_sc_hd__a21oi_2 and sky130_fd_sc_hd__a21oi_2 are equivalent.
+
+Subcircuit summary:
+Circuit 1: sky130_fd_sc_hd__o21bai_1 |Circuit 2: sky130_fd_sc_hd__o21bai_1
+-------------------------------------------|-------------------------------------------
+sky130_fd_pr__pfet_01v8_hvt (4) |sky130_fd_pr__pfet_01v8_hvt (4)
+sky130_fd_pr__nfet_01v8 (4) |sky130_fd_pr__nfet_01v8 (4)
+Number of devices: 8 |Number of devices: 8
+Number of nets: 11 |Number of nets: 11
+---------------------------------------------------------------------------------------
+Netlists match uniquely.
+
+Subcircuit pins:
+Circuit 1: sky130_fd_sc_hd__o21bai_1 |Circuit 2: sky130_fd_sc_hd__o21bai_1
+-------------------------------------------|-------------------------------------------
+VNB |VNB
+VPB |VPB
+VGND |VGND
+Y |Y
+VPWR |VPWR
+A1 |A1
+A2 |A2
+B1_N |B1_N
+---------------------------------------------------------------------------------------
+Cell pin lists are equivalent.
+Device classes sky130_fd_sc_hd__o21bai_1 and sky130_fd_sc_hd__o21bai_1 are equivalent.
+
+Subcircuit summary:
+Circuit 1: sky130_fd_sc_hd__a21oi_1 |Circuit 2: sky130_fd_sc_hd__a21oi_1
+-------------------------------------------|-------------------------------------------
+sky130_fd_pr__nfet_01v8 (3) |sky130_fd_pr__nfet_01v8 (3)
+sky130_fd_pr__pfet_01v8_hvt (3) |sky130_fd_pr__pfet_01v8_hvt (3)
+Number of devices: 6 |Number of devices: 6
+Number of nets: 10 |Number of nets: 10
+---------------------------------------------------------------------------------------
+Netlists match uniquely.
+
+Subcircuit pins:
+Circuit 1: sky130_fd_sc_hd__a21oi_1 |Circuit 2: sky130_fd_sc_hd__a21oi_1
+-------------------------------------------|-------------------------------------------
+VNB |VNB
+VPB |VPB
+Y |Y
+A2 |A2
+VGND |VGND
+A1 |A1
+VPWR |VPWR
+B1 |B1
+---------------------------------------------------------------------------------------
+Cell pin lists are equivalent.
+Device classes sky130_fd_sc_hd__a21oi_1 and sky130_fd_sc_hd__a21oi_1 are equivalent.
+
+Subcircuit summary:
+Circuit 1: sky130_fd_sc_hd__or4bb_1 |Circuit 2: sky130_fd_sc_hd__or4bb_1
+-------------------------------------------|-------------------------------------------
+sky130_fd_pr__nfet_01v8 (7) |sky130_fd_pr__nfet_01v8 (7)
+sky130_fd_pr__pfet_01v8_hvt (7) |sky130_fd_pr__pfet_01v8_hvt (7)
+Number of devices: 14 |Number of devices: 14
+Number of nets: 15 |Number of nets: 15
+---------------------------------------------------------------------------------------
+Netlists match uniquely.
+
+Subcircuit pins:
+Circuit 1: sky130_fd_sc_hd__or4bb_1 |Circuit 2: sky130_fd_sc_hd__or4bb_1
+-------------------------------------------|-------------------------------------------
+VPWR |VPWR
+B |B
+A |A
+X |X
+D_N |D_N
+C_N |C_N
+VGND |VGND
+VNB |VNB
+VPB |VPB
+---------------------------------------------------------------------------------------
+Cell pin lists are equivalent.
+Device classes sky130_fd_sc_hd__or4bb_1 and sky130_fd_sc_hd__or4bb_1 are equivalent.
+
+Class sky130_fd_sc_hd__a221oi_4 (0): Merged 30 parallel devices.
+Class sky130_fd_sc_hd__a221oi_4 (1): Merged 30 parallel devices.
+Subcircuit summary:
+Circuit 1: sky130_fd_sc_hd__a221oi_4 |Circuit 2: sky130_fd_sc_hd__a221oi_4
+-------------------------------------------|-------------------------------------------
+sky130_fd_pr__nfet_01v8 (20->5) |sky130_fd_pr__nfet_01v8 (20->5)
+sky130_fd_pr__pfet_01v8_hvt (20->5) |sky130_fd_pr__pfet_01v8_hvt (20->5)
+Number of devices: 10 |Number of devices: 10
+Number of nets: 14 |Number of nets: 14
+---------------------------------------------------------------------------------------
+Netlists match uniquely.
+
+Subcircuit pins:
+Circuit 1: sky130_fd_sc_hd__a221oi_4 |Circuit 2: sky130_fd_sc_hd__a221oi_4
+-------------------------------------------|-------------------------------------------
+VGND |VGND
+VPB |VPB
+VNB |VNB
+B1 |B1
+C1 |C1
+A1 |A1
+A2 |A2
+VPWR |VPWR
+B2 |B2
+Y |Y
+---------------------------------------------------------------------------------------
+Cell pin lists are equivalent.
+Device classes sky130_fd_sc_hd__a221oi_4 and sky130_fd_sc_hd__a221oi_4 are equivalent.
+
+Class sky130_fd_sc_hd__mux2_4 (0): Merged 6 parallel devices.
+Class sky130_fd_sc_hd__mux2_4 (1): Merged 6 parallel devices.
+Subcircuit summary:
+Circuit 1: sky130_fd_sc_hd__mux2_4 |Circuit 2: sky130_fd_sc_hd__mux2_4
+-------------------------------------------|-------------------------------------------
+sky130_fd_pr__pfet_01v8_hvt (9->6) |sky130_fd_pr__pfet_01v8_hvt (9->6)
+sky130_fd_pr__nfet_01v8 (9->6) |sky130_fd_pr__nfet_01v8 (9->6)
+Number of devices: 12 |Number of devices: 12
+Number of nets: 14 |Number of nets: 14
+---------------------------------------------------------------------------------------
+Netlists match uniquely.
+
+Subcircuit pins:
+Circuit 1: sky130_fd_sc_hd__mux2_4 |Circuit 2: sky130_fd_sc_hd__mux2_4
+-------------------------------------------|-------------------------------------------
+VGND |VGND
+VPWR |VPWR
+S |S
+VNB |VNB
+VPB |VPB
+X |X
+A0 |A0
+A1 |A1
+---------------------------------------------------------------------------------------
+Cell pin lists are equivalent.
+Device classes sky130_fd_sc_hd__mux2_4 and sky130_fd_sc_hd__mux2_4 are equivalent.
+
+Class sky130_fd_sc_hd__clkinv_4 (0): Merged 8 parallel devices.
+Class sky130_fd_sc_hd__clkinv_4 (1): Merged 8 parallel devices.
+Subcircuit summary:
+Circuit 1: sky130_fd_sc_hd__clkinv_4 |Circuit 2: sky130_fd_sc_hd__clkinv_4
+-------------------------------------------|-------------------------------------------
+sky130_fd_pr__pfet_01v8_hvt (6->1) |sky130_fd_pr__pfet_01v8_hvt (6->1)
+sky130_fd_pr__nfet_01v8 (4->1) |sky130_fd_pr__nfet_01v8 (4->1)
+Number of devices: 2 |Number of devices: 2
+Number of nets: 6 |Number of nets: 6
+---------------------------------------------------------------------------------------
+Netlists match uniquely.
+
+Subcircuit pins:
+Circuit 1: sky130_fd_sc_hd__clkinv_4 |Circuit 2: sky130_fd_sc_hd__clkinv_4
+-------------------------------------------|-------------------------------------------
+VPWR |VPWR
+VPB |VPB
+VGND |VGND
+VNB |VNB
+A |A
+Y |Y
+---------------------------------------------------------------------------------------
+Cell pin lists are equivalent.
+Device classes sky130_fd_sc_hd__clkinv_4 and sky130_fd_sc_hd__clkinv_4 are equivalent.
+
+Subcircuit summary:
+Circuit 1: sky130_fd_sc_hd__o211ai_1 |Circuit 2: sky130_fd_sc_hd__o211ai_1
+-------------------------------------------|-------------------------------------------
+sky130_fd_pr__pfet_01v8_hvt (4) |sky130_fd_pr__pfet_01v8_hvt (4)
+sky130_fd_pr__nfet_01v8 (4) |sky130_fd_pr__nfet_01v8 (4)
+Number of devices: 8 |Number of devices: 8
+Number of nets: 12 |Number of nets: 12
+---------------------------------------------------------------------------------------
+Netlists match uniquely.
+
+Subcircuit pins:
+Circuit 1: sky130_fd_sc_hd__o211ai_1 |Circuit 2: sky130_fd_sc_hd__o211ai_1
+-------------------------------------------|-------------------------------------------
+Y |Y
+VPB |VPB
+VNB |VNB
+VPWR |VPWR
+A2 |A2
+A1 |A1
+VGND |VGND
+C1 |C1
+B1 |B1
+---------------------------------------------------------------------------------------
+Cell pin lists are equivalent.
+Device classes sky130_fd_sc_hd__o211ai_1 and sky130_fd_sc_hd__o211ai_1 are equivalent.
+
+Class sky130_fd_sc_hd__nor2_4 (0): Merged 12 parallel devices.
+Class sky130_fd_sc_hd__nor2_4 (1): Merged 12 parallel devices.
+Subcircuit summary:
+Circuit 1: sky130_fd_sc_hd__nor2_4 |Circuit 2: sky130_fd_sc_hd__nor2_4
+-------------------------------------------|-------------------------------------------
+sky130_fd_pr__pfet_01v8_hvt (8->2) |sky130_fd_pr__pfet_01v8_hvt (8->2)
+sky130_fd_pr__nfet_01v8 (8->2) |sky130_fd_pr__nfet_01v8 (8->2)
+Number of devices: 4 |Number of devices: 4
+Number of nets: 8 |Number of nets: 8
+---------------------------------------------------------------------------------------
+Netlists match uniquely.
+
+Subcircuit pins:
+Circuit 1: sky130_fd_sc_hd__nor2_4 |Circuit 2: sky130_fd_sc_hd__nor2_4
+-------------------------------------------|-------------------------------------------
+Y |Y
+B |B
+VPB |VPB
+A |A
+VGND |VGND
+VNB |VNB
+VPWR |VPWR
+---------------------------------------------------------------------------------------
+Cell pin lists are equivalent.
+Device classes sky130_fd_sc_hd__nor2_4 and sky130_fd_sc_hd__nor2_4 are equivalent.
+
+Class sky130_fd_sc_hd__a21oi_4 (0): Merged 18 parallel devices.
+Class sky130_fd_sc_hd__a21oi_4 (1): Merged 18 parallel devices.
+Subcircuit summary:
+Circuit 1: sky130_fd_sc_hd__a21oi_4 |Circuit 2: sky130_fd_sc_hd__a21oi_4
+-------------------------------------------|-------------------------------------------
+sky130_fd_pr__pfet_01v8_hvt (12->3) |sky130_fd_pr__pfet_01v8_hvt (12->3)
+sky130_fd_pr__nfet_01v8 (12->3) |sky130_fd_pr__nfet_01v8 (12->3)
+Number of devices: 6 |Number of devices: 6
+Number of nets: 10 |Number of nets: 10
+---------------------------------------------------------------------------------------
+Netlists match uniquely.
+
+Subcircuit pins:
+Circuit 1: sky130_fd_sc_hd__a21oi_4 |Circuit 2: sky130_fd_sc_hd__a21oi_4
+-------------------------------------------|-------------------------------------------
+A2 |A2
+VGND |VGND
+B1 |B1
+VPWR |VPWR
+A1 |A1
+VNB |VNB
+Y |Y
+VPB |VPB
+---------------------------------------------------------------------------------------
+Cell pin lists are equivalent.
+Device classes sky130_fd_sc_hd__a21oi_4 and sky130_fd_sc_hd__a21oi_4 are equivalent.
+
+Subcircuit summary:
+Circuit 1: sky130_fd_sc_hd__o2111ai_1 |Circuit 2: sky130_fd_sc_hd__o2111ai_1
+-------------------------------------------|-------------------------------------------
+sky130_fd_pr__pfet_01v8_hvt (5) |sky130_fd_pr__pfet_01v8_hvt (5)
+sky130_fd_pr__nfet_01v8 (5) |sky130_fd_pr__nfet_01v8 (5)
+Number of devices: 10 |Number of devices: 10
+Number of nets: 14 |Number of nets: 14
+---------------------------------------------------------------------------------------
+Netlists match uniquely.
+
+Subcircuit pins:
+Circuit 1: sky130_fd_sc_hd__o2111ai_1 |Circuit 2: sky130_fd_sc_hd__o2111ai_1
+-------------------------------------------|-------------------------------------------
+VNB |VNB
+Y |Y
+VPB |VPB
+B1 |B1
+A2 |A2
+VGND |VGND
+A1 |A1
+D1 |D1
+C1 |C1
+VPWR |VPWR
+---------------------------------------------------------------------------------------
+Cell pin lists are equivalent.
+Device classes sky130_fd_sc_hd__o2111ai_1 and sky130_fd_sc_hd__o2111ai_1 are equivalent.
+
+Subcircuit summary:
+Circuit 1: sky130_fd_sc_hd__nand2b_1 |Circuit 2: sky130_fd_sc_hd__nand2b_1
+-------------------------------------------|-------------------------------------------
+sky130_fd_pr__nfet_01v8 (3) |sky130_fd_pr__nfet_01v8 (3)
+sky130_fd_pr__pfet_01v8_hvt (3) |sky130_fd_pr__pfet_01v8_hvt (3)
+Number of devices: 6 |Number of devices: 6
+Number of nets: 9 |Number of nets: 9
+---------------------------------------------------------------------------------------
+Netlists match uniquely.
+
+Subcircuit pins:
+Circuit 1: sky130_fd_sc_hd__nand2b_1 |Circuit 2: sky130_fd_sc_hd__nand2b_1
+-------------------------------------------|-------------------------------------------
+Y |Y
+VNB |VNB
+VPWR |VPWR
+VPB |VPB
+A_N |A_N
+VGND |VGND
+B |B
+---------------------------------------------------------------------------------------
+Cell pin lists are equivalent.
+Device classes sky130_fd_sc_hd__nand2b_1 and sky130_fd_sc_hd__nand2b_1 are equivalent.
+
+Class sky130_fd_sc_hd__or4bb_4 (0): Merged 6 parallel devices.
+Class sky130_fd_sc_hd__or4bb_4 (1): Merged 6 parallel devices.
+Subcircuit summary:
+Circuit 1: sky130_fd_sc_hd__or4bb_4 |Circuit 2: sky130_fd_sc_hd__or4bb_4
+-------------------------------------------|-------------------------------------------
+sky130_fd_pr__pfet_01v8_hvt (10->7) |sky130_fd_pr__pfet_01v8_hvt (10->7)
+sky130_fd_pr__nfet_01v8 (10->7) |sky130_fd_pr__nfet_01v8 (10->7)
+Number of devices: 14 |Number of devices: 14
+Number of nets: 15 |Number of nets: 15
+---------------------------------------------------------------------------------------
+Netlists match uniquely.
+
+Subcircuit pins:
+Circuit 1: sky130_fd_sc_hd__or4bb_4 |Circuit 2: sky130_fd_sc_hd__or4bb_4
+-------------------------------------------|-------------------------------------------
+X |X
+B |B
+A |A
+D_N |D_N
+C_N |C_N
+VGND |VGND
+VNB |VNB
+VPB |VPB
+VPWR |VPWR
+---------------------------------------------------------------------------------------
+Cell pin lists are equivalent.
+Device classes sky130_fd_sc_hd__or4bb_4 and sky130_fd_sc_hd__or4bb_4 are equivalent.
+
+Class sky130_fd_sc_hd__and4b_4 (0): Merged 6 parallel devices.
+Class sky130_fd_sc_hd__and4b_4 (1): Merged 6 parallel devices.
+Subcircuit summary:
+Circuit 1: sky130_fd_sc_hd__and4b_4 |Circuit 2: sky130_fd_sc_hd__and4b_4
+-------------------------------------------|-------------------------------------------
+sky130_fd_pr__pfet_01v8_hvt (9->6) |sky130_fd_pr__pfet_01v8_hvt (9->6)
+sky130_fd_pr__nfet_01v8 (9->6) |sky130_fd_pr__nfet_01v8 (9->6)
+Number of devices: 12 |Number of devices: 12
+Number of nets: 14 |Number of nets: 14
+---------------------------------------------------------------------------------------
+Netlists match uniquely.
+
+Subcircuit pins:
+Circuit 1: sky130_fd_sc_hd__and4b_4 |Circuit 2: sky130_fd_sc_hd__and4b_4
+-------------------------------------------|-------------------------------------------
+VGND |VGND
+X |X
+D |D
+A_N |A_N
+C |C
+B |B
+VPWR |VPWR
+VPB |VPB
+VNB |VNB
+---------------------------------------------------------------------------------------
+Cell pin lists are equivalent.
+Device classes sky130_fd_sc_hd__and4b_4 and sky130_fd_sc_hd__and4b_4 are equivalent.
+
+Subcircuit summary:
+Circuit 1: sky130_fd_sc_hd__o2111a_1 |Circuit 2: sky130_fd_sc_hd__o2111a_1
+-------------------------------------------|-------------------------------------------
+sky130_fd_pr__pfet_01v8_hvt (6) |sky130_fd_pr__pfet_01v8_hvt (6)
+sky130_fd_pr__nfet_01v8 (6) |sky130_fd_pr__nfet_01v8 (6)
+Number of devices: 12 |Number of devices: 12
+Number of nets: 15 |Number of nets: 15
+---------------------------------------------------------------------------------------
+Netlists match uniquely.
+
+Subcircuit pins:
+Circuit 1: sky130_fd_sc_hd__o2111a_1 |Circuit 2: sky130_fd_sc_hd__o2111a_1
+-------------------------------------------|-------------------------------------------
+VPWR |VPWR
+VGND |VGND
+VPB |VPB
+VNB |VNB
+D1 |D1
+C1 |C1
+A1 |A1
+A2 |A2
+B1 |B1
+X |X
+---------------------------------------------------------------------------------------
+Cell pin lists are equivalent.
+Device classes sky130_fd_sc_hd__o2111a_1 and sky130_fd_sc_hd__o2111a_1 are equivalent.
+
+Class sky130_fd_sc_hd__a2bb2o_4 (0): Merged 16 parallel devices.
+Class sky130_fd_sc_hd__a2bb2o_4 (1): Merged 16 parallel devices.
+Subcircuit summary:
+Circuit 1: sky130_fd_sc_hd__a2bb2o_4 |Circuit 2: sky130_fd_sc_hd__a2bb2o_4
+-------------------------------------------|-------------------------------------------
+sky130_fd_pr__nfet_01v8 (14->6) |sky130_fd_pr__nfet_01v8 (14->6)
+sky130_fd_pr__pfet_01v8_hvt (14->6) |sky130_fd_pr__pfet_01v8_hvt (14->6)
+Number of devices: 12 |Number of devices: 12
+Number of nets: 14 |Number of nets: 14
+---------------------------------------------------------------------------------------
+Netlists match uniquely.
+
+Subcircuit pins:
+Circuit 1: sky130_fd_sc_hd__a2bb2o_4 |Circuit 2: sky130_fd_sc_hd__a2bb2o_4
+-------------------------------------------|-------------------------------------------
+VPWR |VPWR
+A2_N |A2_N
+X |X
+A1_N |A1_N
+B2 |B2
+B1 |B1
+VNB |VNB
+VPB |VPB
+VGND |VGND
+---------------------------------------------------------------------------------------
+Cell pin lists are equivalent.
+Device classes sky130_fd_sc_hd__a2bb2o_4 and sky130_fd_sc_hd__a2bb2o_4 are equivalent.
+
+Subcircuit summary:
+Circuit 1: sky130_fd_sc_hd__and4bb_1 |Circuit 2: sky130_fd_sc_hd__and4bb_1
+-------------------------------------------|-------------------------------------------
+sky130_fd_pr__pfet_01v8_hvt (7) |sky130_fd_pr__pfet_01v8_hvt (7)
+sky130_fd_pr__nfet_01v8 (7) |sky130_fd_pr__nfet_01v8 (7)
+Number of devices: 14 |Number of devices: 14
+Number of nets: 15 |Number of nets: 15
+---------------------------------------------------------------------------------------
+Netlists match uniquely.
+
+Subcircuit pins:
+Circuit 1: sky130_fd_sc_hd__and4bb_1 |Circuit 2: sky130_fd_sc_hd__and4bb_1
+-------------------------------------------|-------------------------------------------
+VGND |VGND
+C |C
+A_N |A_N
+B_N |B_N
+X |X
+D |D
+VPWR |VPWR
+VPB |VPB
+VNB |VNB
+---------------------------------------------------------------------------------------
+Cell pin lists are equivalent.
+Device classes sky130_fd_sc_hd__and4bb_1 and sky130_fd_sc_hd__and4bb_1 are equivalent.
+
+Subcircuit summary:
+Circuit 1: sky130_fd_sc_hd__xnor2_1 |Circuit 2: sky130_fd_sc_hd__xnor2_1
+-------------------------------------------|-------------------------------------------
+sky130_fd_pr__pfet_01v8_hvt (5) |sky130_fd_pr__pfet_01v8_hvt (5)
+sky130_fd_pr__nfet_01v8 (5) |sky130_fd_pr__nfet_01v8 (5)
+Number of devices: 10 |Number of devices: 10
+Number of nets: 11 |Number of nets: 11
+---------------------------------------------------------------------------------------
+Netlists match uniquely.
+
+Subcircuit pins:
+Circuit 1: sky130_fd_sc_hd__xnor2_1 |Circuit 2: sky130_fd_sc_hd__xnor2_1
+-------------------------------------------|-------------------------------------------
+Y |Y
+VGND |VGND
+VPB |VPB
+VNB |VNB
+VPWR |VPWR
+A |A
+B |B
+---------------------------------------------------------------------------------------
+Cell pin lists are equivalent.
+Device classes sky130_fd_sc_hd__xnor2_1 and sky130_fd_sc_hd__xnor2_1 are equivalent.
+
+Class sky130_fd_sc_hd__nand4_2 (0): Merged 8 parallel devices.
+Class sky130_fd_sc_hd__nand4_2 (1): Merged 8 parallel devices.
+Subcircuit summary:
+Circuit 1: sky130_fd_sc_hd__nand4_2 |Circuit 2: sky130_fd_sc_hd__nand4_2
+-------------------------------------------|-------------------------------------------
+sky130_fd_pr__pfet_01v8_hvt (8->4) |sky130_fd_pr__pfet_01v8_hvt (8->4)
+sky130_fd_pr__nfet_01v8 (8->4) |sky130_fd_pr__nfet_01v8 (8->4)
+Number of devices: 8 |Number of devices: 8
+Number of nets: 12 |Number of nets: 12
+---------------------------------------------------------------------------------------
+Netlists match uniquely.
+
+Subcircuit pins:
+Circuit 1: sky130_fd_sc_hd__nand4_2 |Circuit 2: sky130_fd_sc_hd__nand4_2
+-------------------------------------------|-------------------------------------------
+VGND |VGND
+Y |Y
+B |B
+C |C
+A |A
+D |D
+VPWR |VPWR
+VPB |VPB
+VNB |VNB
+---------------------------------------------------------------------------------------
+Cell pin lists are equivalent.
+Device classes sky130_fd_sc_hd__nand4_2 and sky130_fd_sc_hd__nand4_2 are equivalent.
+
+Subcircuit summary:
+Circuit 1: sky130_fd_sc_hd__clkbuf_1 |Circuit 2: sky130_fd_sc_hd__clkbuf_1
+-------------------------------------------|-------------------------------------------
+sky130_fd_pr__pfet_01v8_hvt (2) |sky130_fd_pr__pfet_01v8_hvt (2)
+sky130_fd_pr__nfet_01v8 (2) |sky130_fd_pr__nfet_01v8 (2)
+Number of devices: 4 |Number of devices: 4
+Number of nets: 7 |Number of nets: 7
+---------------------------------------------------------------------------------------
+Netlists match uniquely.
+
+Subcircuit pins:
+Circuit 1: sky130_fd_sc_hd__clkbuf_1 |Circuit 2: sky130_fd_sc_hd__clkbuf_1
+-------------------------------------------|-------------------------------------------
+VGND |VGND
+A |A
+VNB |VNB
+X |X
+VPWR |VPWR
+VPB |VPB
+---------------------------------------------------------------------------------------
+Cell pin lists are equivalent.
+Device classes sky130_fd_sc_hd__clkbuf_1 and sky130_fd_sc_hd__clkbuf_1 are equivalent.
+
+Class sky130_fd_sc_hd__o22a_4 (0): Merged 14 parallel devices.
+Class sky130_fd_sc_hd__o22a_4 (1): Merged 14 parallel devices.
+Subcircuit summary:
+Circuit 1: sky130_fd_sc_hd__o22a_4 |Circuit 2: sky130_fd_sc_hd__o22a_4
+-------------------------------------------|-------------------------------------------
+sky130_fd_pr__pfet_01v8_hvt (12->5) |sky130_fd_pr__pfet_01v8_hvt (12->5)
+sky130_fd_pr__nfet_01v8 (12->5) |sky130_fd_pr__nfet_01v8 (12->5)
+Number of devices: 10 |Number of devices: 10
+Number of nets: 13 |Number of nets: 13
+---------------------------------------------------------------------------------------
+Netlists match uniquely.
+
+Subcircuit pins:
+Circuit 1: sky130_fd_sc_hd__o22a_4 |Circuit 2: sky130_fd_sc_hd__o22a_4
+-------------------------------------------|-------------------------------------------
+VPB |VPB
+VNB |VNB
+A2 |A2
+X |X
+B1 |B1
+A1 |A1
+B2 |B2
+VPWR |VPWR
+VGND |VGND
+---------------------------------------------------------------------------------------
+Cell pin lists are equivalent.
+Device classes sky130_fd_sc_hd__o22a_4 and sky130_fd_sc_hd__o22a_4 are equivalent.
+
+Subcircuit summary:
+Circuit 1: sky130_fd_sc_hd__dlymetal6s2s_1 |Circuit 2: sky130_fd_sc_hd__dlymetal6s2s_1
+-------------------------------------------|-------------------------------------------
+sky130_fd_pr__pfet_01v8_hvt (6) |sky130_fd_pr__pfet_01v8_hvt (6)
+sky130_fd_pr__nfet_01v8 (6) |sky130_fd_pr__nfet_01v8 (6)
+Number of devices: 12 |Number of devices: 12
+Number of nets: 11 |Number of nets: 11
+---------------------------------------------------------------------------------------
+Netlists match uniquely.
+
+Subcircuit pins:
+Circuit 1: sky130_fd_sc_hd__dlymetal6s2s_1 |Circuit 2: sky130_fd_sc_hd__dlymetal6s2s_1
+-------------------------------------------|-------------------------------------------
+A |A
+VPWR |VPWR
+VPB |VPB
+VGND |VGND
+VNB |VNB
+X |X
+---------------------------------------------------------------------------------------
+Cell pin lists are equivalent.
+Device classes sky130_fd_sc_hd__dlymetal6s2s_1 and sky130_fd_sc_hd__dlymetal6s2s_1 are equivalent.
+
+Class sky130_fd_sc_hd__buf_2 (0): Merged 2 parallel devices.
+Class sky130_fd_sc_hd__buf_2 (1): Merged 2 parallel devices.
+Subcircuit summary:
+Circuit 1: sky130_fd_sc_hd__buf_2 |Circuit 2: sky130_fd_sc_hd__buf_2
+-------------------------------------------|-------------------------------------------
+sky130_fd_pr__pfet_01v8_hvt (3->2) |sky130_fd_pr__pfet_01v8_hvt (3->2)
+sky130_fd_pr__nfet_01v8 (3->2) |sky130_fd_pr__nfet_01v8 (3->2)
+Number of devices: 4 |Number of devices: 4
+Number of nets: 7 |Number of nets: 7
+---------------------------------------------------------------------------------------
+Netlists match uniquely.
+
+Subcircuit pins:
+Circuit 1: sky130_fd_sc_hd__buf_2 |Circuit 2: sky130_fd_sc_hd__buf_2
+-------------------------------------------|-------------------------------------------
+X |X
+VGND |VGND
+VNB |VNB
+A |A
+VPWR |VPWR
+VPB |VPB
+---------------------------------------------------------------------------------------
+Cell pin lists are equivalent.
+Device classes sky130_fd_sc_hd__buf_2 and sky130_fd_sc_hd__buf_2 are equivalent.
+
+Subcircuit summary:
+Circuit 1: sky130_fd_sc_hd__xor2_1 |Circuit 2: sky130_fd_sc_hd__xor2_1
+-------------------------------------------|-------------------------------------------
+sky130_fd_pr__pfet_01v8_hvt (5) |sky130_fd_pr__pfet_01v8_hvt (5)
+sky130_fd_pr__nfet_01v8 (5) |sky130_fd_pr__nfet_01v8 (5)
+Number of devices: 10 |Number of devices: 10
+Number of nets: 11 |Number of nets: 11
+---------------------------------------------------------------------------------------
+Netlists match uniquely.
+
+Subcircuit pins:
+Circuit 1: sky130_fd_sc_hd__xor2_1 |Circuit 2: sky130_fd_sc_hd__xor2_1
+-------------------------------------------|-------------------------------------------
+A |A
+VGND |VGND
+B |B
+VNB |VNB
+VPB |VPB
+X |X
+VPWR |VPWR
+---------------------------------------------------------------------------------------
+Cell pin lists are equivalent.
+Device classes sky130_fd_sc_hd__xor2_1 and sky130_fd_sc_hd__xor2_1 are equivalent.
+
+Class sky130_fd_sc_hd__and4_4 (0): Merged 6 parallel devices.
+Class sky130_fd_sc_hd__and4_4 (1): Merged 6 parallel devices.
+Subcircuit summary:
+Circuit 1: sky130_fd_sc_hd__and4_4 |Circuit 2: sky130_fd_sc_hd__and4_4
+-------------------------------------------|-------------------------------------------
+sky130_fd_pr__pfet_01v8_hvt (8->5) |sky130_fd_pr__pfet_01v8_hvt (8->5)
+sky130_fd_pr__nfet_01v8 (8->5) |sky130_fd_pr__nfet_01v8 (8->5)
+Number of devices: 10 |Number of devices: 10
+Number of nets: 13 |Number of nets: 13
+---------------------------------------------------------------------------------------
+Netlists match uniquely.
+
+Subcircuit pins:
+Circuit 1: sky130_fd_sc_hd__and4_4 |Circuit 2: sky130_fd_sc_hd__and4_4
+-------------------------------------------|-------------------------------------------
+VGND |VGND
+X |X
+C |C
+D |D
+B |B
+A |A
+VPWR |VPWR
+VPB |VPB
+VNB |VNB
+---------------------------------------------------------------------------------------
+Cell pin lists are equivalent.
+Device classes sky130_fd_sc_hd__and4_4 and sky130_fd_sc_hd__and4_4 are equivalent.
+
+Subcircuit summary:
+Circuit 1: sky130_fd_sc_hd__o32a_1 |Circuit 2: sky130_fd_sc_hd__o32a_1
+-------------------------------------------|-------------------------------------------
+sky130_fd_pr__nfet_01v8 (6) |sky130_fd_pr__nfet_01v8 (6)
+sky130_fd_pr__pfet_01v8_hvt (6) |sky130_fd_pr__pfet_01v8_hvt (6)
+Number of devices: 12 |Number of devices: 12
+Number of nets: 15 |Number of nets: 15
+---------------------------------------------------------------------------------------
+Netlists match uniquely.
+
+Subcircuit pins:
+Circuit 1: sky130_fd_sc_hd__o32a_1 |Circuit 2: sky130_fd_sc_hd__o32a_1
+-------------------------------------------|-------------------------------------------
+VGND |VGND
+VPWR |VPWR
+X |X
+A1 |A1
+B1 |B1
+A2 |A2
+B2 |B2
+A3 |A3
+VPB |VPB
+VNB |VNB
+---------------------------------------------------------------------------------------
+Cell pin lists are equivalent.
+Device classes sky130_fd_sc_hd__o32a_1 and sky130_fd_sc_hd__o32a_1 are equivalent.
+
+Class sky130_fd_sc_hd__or4b_2 (0): Merged 2 parallel devices.
+Class sky130_fd_sc_hd__or4b_2 (1): Merged 2 parallel devices.
+Subcircuit summary:
+Circuit 1: sky130_fd_sc_hd__or4b_2 |Circuit 2: sky130_fd_sc_hd__or4b_2
+-------------------------------------------|-------------------------------------------
+sky130_fd_pr__nfet_01v8 (7->6) |sky130_fd_pr__nfet_01v8 (7->6)
+sky130_fd_pr__pfet_01v8_hvt (7->6) |sky130_fd_pr__pfet_01v8_hvt (7->6)
+Number of devices: 12 |Number of devices: 12
+Number of nets: 14 |Number of nets: 14
+---------------------------------------------------------------------------------------
+Netlists match uniquely.
+
+Subcircuit pins:
+Circuit 1: sky130_fd_sc_hd__or4b_2 |Circuit 2: sky130_fd_sc_hd__or4b_2
+-------------------------------------------|-------------------------------------------
+VPWR |VPWR
+VGND |VGND
+VNB |VNB
+VPB |VPB
+X |X
+D_N |D_N
+B |B
+C |C
+A |A
+---------------------------------------------------------------------------------------
+Cell pin lists are equivalent.
+Device classes sky130_fd_sc_hd__or4b_2 and sky130_fd_sc_hd__or4b_2 are equivalent.
+
+Class sky130_fd_sc_hd__a22oi_2 (0): Merged 8 parallel devices.
+Class sky130_fd_sc_hd__a22oi_2 (1): Merged 8 parallel devices.
+Subcircuit summary:
+Circuit 1: sky130_fd_sc_hd__a22oi_2 |Circuit 2: sky130_fd_sc_hd__a22oi_2
+-------------------------------------------|-------------------------------------------
+sky130_fd_pr__pfet_01v8_hvt (8->4) |sky130_fd_pr__pfet_01v8_hvt (8->4)
+sky130_fd_pr__nfet_01v8 (8->4) |sky130_fd_pr__nfet_01v8 (8->4)
+Number of devices: 8 |Number of devices: 8
+Number of nets: 12 |Number of nets: 12
+---------------------------------------------------------------------------------------
+Netlists match uniquely.
+
+Subcircuit pins:
+Circuit 1: sky130_fd_sc_hd__a22oi_2 |Circuit 2: sky130_fd_sc_hd__a22oi_2
+-------------------------------------------|-------------------------------------------
+VGND |VGND
+A2 |A2
+A1 |A1
+VPWR |VPWR
+B1 |B1
+B2 |B2
+VNB |VNB
+Y |Y
+VPB |VPB
+---------------------------------------------------------------------------------------
+Cell pin lists are equivalent.
+Device classes sky130_fd_sc_hd__a22oi_2 and sky130_fd_sc_hd__a22oi_2 are equivalent.
+
+Class sky130_fd_sc_hd__and2_4 (0): Merged 6 parallel devices.
+Class sky130_fd_sc_hd__and2_4 (1): Merged 6 parallel devices.
+Subcircuit summary:
+Circuit 1: sky130_fd_sc_hd__and2_4 |Circuit 2: sky130_fd_sc_hd__and2_4
+-------------------------------------------|-------------------------------------------
+sky130_fd_pr__pfet_01v8_hvt (6->3) |sky130_fd_pr__pfet_01v8_hvt (6->3)
+sky130_fd_pr__nfet_01v8 (6->3) |sky130_fd_pr__nfet_01v8 (6->3)
+Number of devices: 6 |Number of devices: 6
+Number of nets: 9 |Number of nets: 9
+---------------------------------------------------------------------------------------
+Netlists match uniquely.
+
+Subcircuit pins:
+Circuit 1: sky130_fd_sc_hd__and2_4 |Circuit 2: sky130_fd_sc_hd__and2_4
+-------------------------------------------|-------------------------------------------
+B |B
+A |A
+VGND |VGND
+X |X
+VPWR |VPWR
+VPB |VPB
+VNB |VNB
+---------------------------------------------------------------------------------------
+Cell pin lists are equivalent.
+Device classes sky130_fd_sc_hd__and2_4 and sky130_fd_sc_hd__and2_4 are equivalent.
+
+Class sky130_fd_sc_hd__nand4_4 (0): Merged 24 parallel devices.
+Class sky130_fd_sc_hd__nand4_4 (1): Merged 24 parallel devices.
+Subcircuit summary:
+Circuit 1: sky130_fd_sc_hd__nand4_4 |Circuit 2: sky130_fd_sc_hd__nand4_4
+-------------------------------------------|-------------------------------------------
+sky130_fd_pr__nfet_01v8 (16->4) |sky130_fd_pr__nfet_01v8 (16->4)
+sky130_fd_pr__pfet_01v8_hvt (16->4) |sky130_fd_pr__pfet_01v8_hvt (16->4)
+Number of devices: 8 |Number of devices: 8
+Number of nets: 12 |Number of nets: 12
+---------------------------------------------------------------------------------------
+Netlists match uniquely.
+
+Subcircuit pins:
+Circuit 1: sky130_fd_sc_hd__nand4_4 |Circuit 2: sky130_fd_sc_hd__nand4_4
+-------------------------------------------|-------------------------------------------
+VGND |VGND
+Y |Y
+VPWR |VPWR
+VPB |VPB
+VNB |VNB
+A |A
+B |B
+C |C
+D |D
+---------------------------------------------------------------------------------------
+Cell pin lists are equivalent.
+Device classes sky130_fd_sc_hd__nand4_4 and sky130_fd_sc_hd__nand4_4 are equivalent.
+
+Class sky130_fd_sc_hd__a2111o_2 (0): Merged 2 parallel devices.
+Class sky130_fd_sc_hd__a2111o_2 (1): Merged 2 parallel devices.
+Subcircuit summary:
+Circuit 1: sky130_fd_sc_hd__a2111o_2 |Circuit 2: sky130_fd_sc_hd__a2111o_2
+-------------------------------------------|-------------------------------------------
+sky130_fd_pr__pfet_01v8_hvt (7->6) |sky130_fd_pr__pfet_01v8_hvt (7->6)
+sky130_fd_pr__nfet_01v8 (7->6) |sky130_fd_pr__nfet_01v8 (7->6)
+Number of devices: 12 |Number of devices: 12
+Number of nets: 15 |Number of nets: 15
+---------------------------------------------------------------------------------------
+Netlists match uniquely.
+
+Subcircuit pins:
+Circuit 1: sky130_fd_sc_hd__a2111o_2 |Circuit 2: sky130_fd_sc_hd__a2111o_2
+-------------------------------------------|-------------------------------------------
+VGND |VGND
+VNB |VNB
+VPB |VPB
+A1 |A1
+X |X
+A2 |A2
+D1 |D1
+C1 |C1
+B1 |B1
+VPWR |VPWR
+---------------------------------------------------------------------------------------
+Cell pin lists are equivalent.
+Device classes sky130_fd_sc_hd__a2111o_2 and sky130_fd_sc_hd__a2111o_2 are equivalent.
+
+Subcircuit summary:
+Circuit 1: sky130_fd_sc_hd__o2bb2a_1 |Circuit 2: sky130_fd_sc_hd__o2bb2a_1
+-------------------------------------------|-------------------------------------------
+sky130_fd_pr__pfet_01v8_hvt (6) |sky130_fd_pr__pfet_01v8_hvt (6)
+sky130_fd_pr__nfet_01v8 (6) |sky130_fd_pr__nfet_01v8 (6)
+Number of devices: 12 |Number of devices: 12
+Number of nets: 14 |Number of nets: 14
+---------------------------------------------------------------------------------------
+Netlists match uniquely.
+
+Subcircuit pins:
+Circuit 1: sky130_fd_sc_hd__o2bb2a_1 |Circuit 2: sky130_fd_sc_hd__o2bb2a_1
+-------------------------------------------|-------------------------------------------
+VGND |VGND
+VNB |VNB
+VPB |VPB
+A1_N |A1_N
+A2_N |A2_N
+X |X
+B1 |B1
+B2 |B2
+VPWR |VPWR
+---------------------------------------------------------------------------------------
+Cell pin lists are equivalent.
+Device classes sky130_fd_sc_hd__o2bb2a_1 and sky130_fd_sc_hd__o2bb2a_1 are equivalent.
+
+Subcircuit summary:
+Circuit 1: sky130_fd_sc_hd__and3b_1 |Circuit 2: sky130_fd_sc_hd__and3b_1
+-------------------------------------------|-------------------------------------------
+sky130_fd_pr__nfet_01v8 (5) |sky130_fd_pr__nfet_01v8 (5)
+sky130_fd_pr__pfet_01v8_hvt (5) |sky130_fd_pr__pfet_01v8_hvt (5)
+Number of devices: 10 |Number of devices: 10
+Number of nets: 12 |Number of nets: 12
+---------------------------------------------------------------------------------------
+Netlists match uniquely.
+
+Subcircuit pins:
+Circuit 1: sky130_fd_sc_hd__and3b_1 |Circuit 2: sky130_fd_sc_hd__and3b_1
+-------------------------------------------|-------------------------------------------
+VNB |VNB
+VPWR |VPWR
+VPB |VPB
+VGND |VGND
+X |X
+A_N |A_N
+C |C
+B |B
+---------------------------------------------------------------------------------------
+Cell pin lists are equivalent.
+Device classes sky130_fd_sc_hd__and3b_1 and sky130_fd_sc_hd__and3b_1 are equivalent.
+
+Subcircuit summary:
+Circuit 1: sky130_fd_sc_hd__a2111oi_1 |Circuit 2: sky130_fd_sc_hd__a2111oi_1
+-------------------------------------------|-------------------------------------------
+sky130_fd_pr__pfet_01v8_hvt (5) |sky130_fd_pr__pfet_01v8_hvt (5)
+sky130_fd_pr__nfet_01v8 (5) |sky130_fd_pr__nfet_01v8 (5)
+Number of devices: 10 |Number of devices: 10
+Number of nets: 14 |Number of nets: 14
+---------------------------------------------------------------------------------------
+Netlists match uniquely.
+
+Subcircuit pins:
+Circuit 1: sky130_fd_sc_hd__a2111oi_1 |Circuit 2: sky130_fd_sc_hd__a2111oi_1
+-------------------------------------------|-------------------------------------------
+VGND |VGND
+Y |Y
+VNB |VNB
+VPB |VPB
+C1 |C1
+B1 |B1
+A1 |A1
+D1 |D1
+VPWR |VPWR
+A2 |A2
+---------------------------------------------------------------------------------------
+Cell pin lists are equivalent.
+Device classes sky130_fd_sc_hd__a2111oi_1 and sky130_fd_sc_hd__a2111oi_1 are equivalent.
+
+Class sky130_fd_sc_hd__o2111ai_4 (0): Merged 30 parallel devices.
+Class sky130_fd_sc_hd__o2111ai_4 (1): Merged 30 parallel devices.
+Subcircuit summary:
+Circuit 1: sky130_fd_sc_hd__o2111ai_4 |Circuit 2: sky130_fd_sc_hd__o2111ai_4
+-------------------------------------------|-------------------------------------------
+sky130_fd_pr__nfet_01v8 (20->5) |sky130_fd_pr__nfet_01v8 (20->5)
+sky130_fd_pr__pfet_01v8_hvt (20->5) |sky130_fd_pr__pfet_01v8_hvt (20->5)
+Number of devices: 10 |Number of devices: 10
+Number of nets: 14 |Number of nets: 14
+---------------------------------------------------------------------------------------
+Netlists match uniquely.
+
+Subcircuit pins:
+Circuit 1: sky130_fd_sc_hd__o2111ai_4 |Circuit 2: sky130_fd_sc_hd__o2111ai_4
+-------------------------------------------|-------------------------------------------
+VPWR |VPWR
+VNB |VNB
+Y |Y
+VPB |VPB
+B1 |B1
+C1 |C1
+A1 |A1
+VGND |VGND
+A2 |A2
+D1 |D1
+---------------------------------------------------------------------------------------
+Cell pin lists are equivalent.
+Device classes sky130_fd_sc_hd__o2111ai_4 and sky130_fd_sc_hd__o2111ai_4 are equivalent.
+
+Class sky130_fd_sc_hd__o22ai_4 (0): Merged 24 parallel devices.
+Class sky130_fd_sc_hd__o22ai_4 (1): Merged 24 parallel devices.
+Subcircuit summary:
+Circuit 1: sky130_fd_sc_hd__o22ai_4 |Circuit 2: sky130_fd_sc_hd__o22ai_4
+-------------------------------------------|-------------------------------------------
+sky130_fd_pr__nfet_01v8 (16->4) |sky130_fd_pr__nfet_01v8 (16->4)
+sky130_fd_pr__pfet_01v8_hvt (16->4) |sky130_fd_pr__pfet_01v8_hvt (16->4)
+Number of devices: 8 |Number of devices: 8
+Number of nets: 12 |Number of nets: 12
+---------------------------------------------------------------------------------------
+Netlists match uniquely.
+
+Subcircuit pins:
+Circuit 1: sky130_fd_sc_hd__o22ai_4 |Circuit 2: sky130_fd_sc_hd__o22ai_4
+-------------------------------------------|-------------------------------------------
+B2 |B2
+A2 |A2
+VGND |VGND
+B1 |B1
+A1 |A1
+VPWR |VPWR
+Y |Y
+VPB |VPB
+VNB |VNB
+---------------------------------------------------------------------------------------
+Cell pin lists are equivalent.
+Device classes sky130_fd_sc_hd__o22ai_4 and sky130_fd_sc_hd__o22ai_4 are equivalent.
+
+Class sky130_fd_sc_hd__a211o_2 (0): Merged 2 parallel devices.
+Class sky130_fd_sc_hd__a211o_2 (1): Merged 2 parallel devices.
+Subcircuit summary:
+Circuit 1: sky130_fd_sc_hd__a211o_2 |Circuit 2: sky130_fd_sc_hd__a211o_2
+-------------------------------------------|-------------------------------------------
+sky130_fd_pr__nfet_01v8 (6->5) |sky130_fd_pr__nfet_01v8 (6->5)
+sky130_fd_pr__pfet_01v8_hvt (6->5) |sky130_fd_pr__pfet_01v8_hvt (6->5)
+Number of devices: 10 |Number of devices: 10
+Number of nets: 13 |Number of nets: 13
+---------------------------------------------------------------------------------------
+Netlists match uniquely.
+
+Subcircuit pins:
+Circuit 1: sky130_fd_sc_hd__a211o_2 |Circuit 2: sky130_fd_sc_hd__a211o_2
+-------------------------------------------|-------------------------------------------
+VPWR |VPWR
+VGND |VGND
+VPB |VPB
+VNB |VNB
+A1 |A1
+B1 |B1
+C1 |C1
+X |X
+A2 |A2
+---------------------------------------------------------------------------------------
+Cell pin lists are equivalent.
+Device classes sky130_fd_sc_hd__a211o_2 and sky130_fd_sc_hd__a211o_2 are equivalent.
+
+Class sky130_fd_sc_hd__a32oi_4 (0): Merged 30 parallel devices.
+Class sky130_fd_sc_hd__a32oi_4 (1): Merged 30 parallel devices.
+Subcircuit summary:
+Circuit 1: sky130_fd_sc_hd__a32oi_4 |Circuit 2: sky130_fd_sc_hd__a32oi_4
+-------------------------------------------|-------------------------------------------
+sky130_fd_pr__nfet_01v8 (20->5) |sky130_fd_pr__nfet_01v8 (20->5)
+sky130_fd_pr__pfet_01v8_hvt (20->5) |sky130_fd_pr__pfet_01v8_hvt (20->5)
+Number of devices: 10 |Number of devices: 10
+Number of nets: 14 |Number of nets: 14
+---------------------------------------------------------------------------------------
+Netlists match uniquely.
+
+Subcircuit pins:
+Circuit 1: sky130_fd_sc_hd__a32oi_4 |Circuit 2: sky130_fd_sc_hd__a32oi_4
+-------------------------------------------|-------------------------------------------
+VPWR |VPWR
+VNB |VNB
+VPB |VPB
+Y |Y
+A1 |A1
+B1 |B1
+B2 |B2
+A3 |A3
+A2 |A2
+VGND |VGND
+---------------------------------------------------------------------------------------
+Cell pin lists are equivalent.
+Device classes sky130_fd_sc_hd__a32oi_4 and sky130_fd_sc_hd__a32oi_4 are equivalent.
+
+Class sky130_fd_sc_hd__and2b_4 (0): Merged 6 parallel devices.
+Class sky130_fd_sc_hd__and2b_4 (1): Merged 6 parallel devices.
+Subcircuit summary:
+Circuit 1: sky130_fd_sc_hd__and2b_4 |Circuit 2: sky130_fd_sc_hd__and2b_4
+-------------------------------------------|-------------------------------------------
+sky130_fd_pr__nfet_01v8 (7->4) |sky130_fd_pr__nfet_01v8 (7->4)
+sky130_fd_pr__pfet_01v8_hvt (7->4) |sky130_fd_pr__pfet_01v8_hvt (7->4)
+Number of devices: 8 |Number of devices: 8
+Number of nets: 10 |Number of nets: 10
+---------------------------------------------------------------------------------------
+Netlists match uniquely.
+
+Subcircuit pins:
+Circuit 1: sky130_fd_sc_hd__and2b_4 |Circuit 2: sky130_fd_sc_hd__and2b_4
+-------------------------------------------|-------------------------------------------
+VPWR |VPWR
+VPB |VPB
+VNB |VNB
+VGND |VGND
+A_N |A_N
+X |X
+B |B
+---------------------------------------------------------------------------------------
+Cell pin lists are equivalent.
+Device classes sky130_fd_sc_hd__and2b_4 and sky130_fd_sc_hd__and2b_4 are equivalent.
+
+Class sky130_fd_sc_hd__clkinv_2 (0): Merged 3 parallel devices.
+Class sky130_fd_sc_hd__clkinv_2 (1): Merged 3 parallel devices.
+Subcircuit summary:
+Circuit 1: sky130_fd_sc_hd__clkinv_2 |Circuit 2: sky130_fd_sc_hd__clkinv_2
+-------------------------------------------|-------------------------------------------
+sky130_fd_pr__nfet_01v8 (2->1) |sky130_fd_pr__nfet_01v8 (2->1)
+sky130_fd_pr__pfet_01v8_hvt (3->1) |sky130_fd_pr__pfet_01v8_hvt (3->1)
+Number of devices: 2 |Number of devices: 2
+Number of nets: 6 |Number of nets: 6
+---------------------------------------------------------------------------------------
+Netlists match uniquely.
+
+Subcircuit pins:
+Circuit 1: sky130_fd_sc_hd__clkinv_2 |Circuit 2: sky130_fd_sc_hd__clkinv_2
+-------------------------------------------|-------------------------------------------
+VPWR |VPWR
+VPB |VPB
+VGND |VGND
+VNB |VNB
+Y |Y
+A |A
+---------------------------------------------------------------------------------------
+Cell pin lists are equivalent.
+Device classes sky130_fd_sc_hd__clkinv_2 and sky130_fd_sc_hd__clkinv_2 are equivalent.
+
+Class sky130_fd_sc_hd__o2bb2ai_2 (0): Merged 10 parallel devices.
+Class sky130_fd_sc_hd__o2bb2ai_2 (1): Merged 10 parallel devices.
+Subcircuit summary:
+Circuit 1: sky130_fd_sc_hd__o2bb2ai_2 |Circuit 2: sky130_fd_sc_hd__o2bb2ai_2
+-------------------------------------------|-------------------------------------------
+sky130_fd_pr__pfet_01v8_hvt (10->5) |sky130_fd_pr__pfet_01v8_hvt (10->5)
+sky130_fd_pr__nfet_01v8 (10->5) |sky130_fd_pr__nfet_01v8 (10->5)
+Number of devices: 10 |Number of devices: 10
+Number of nets: 13 |Number of nets: 13
+---------------------------------------------------------------------------------------
+Netlists match uniquely.
+
+Subcircuit pins:
+Circuit 1: sky130_fd_sc_hd__o2bb2ai_2 |Circuit 2: sky130_fd_sc_hd__o2bb2ai_2
+-------------------------------------------|-------------------------------------------
+VGND |VGND
+Y |Y
+VPWR |VPWR
+A1_N |A1_N
+B2 |B2
+A2_N |A2_N
+B1 |B1
+VNB |VNB
+VPB |VPB
+---------------------------------------------------------------------------------------
+Cell pin lists are equivalent.
+Device classes sky130_fd_sc_hd__o2bb2ai_2 and sky130_fd_sc_hd__o2bb2ai_2 are equivalent.
+
+Class sky130_fd_sc_hd__or3b_2 (0): Merged 2 parallel devices.
+Class sky130_fd_sc_hd__or3b_2 (1): Merged 2 parallel devices.
+Subcircuit summary:
+Circuit 1: sky130_fd_sc_hd__or3b_2 |Circuit 2: sky130_fd_sc_hd__or3b_2
+-------------------------------------------|-------------------------------------------
+sky130_fd_pr__pfet_01v8_hvt (6->5) |sky130_fd_pr__pfet_01v8_hvt (6->5)
+sky130_fd_pr__nfet_01v8 (6->5) |sky130_fd_pr__nfet_01v8 (6->5)
+Number of devices: 10 |Number of devices: 10
+Number of nets: 12 |Number of nets: 12
+---------------------------------------------------------------------------------------
+Netlists match uniquely.
+
+Subcircuit pins:
+Circuit 1: sky130_fd_sc_hd__or3b_2 |Circuit 2: sky130_fd_sc_hd__or3b_2
+-------------------------------------------|-------------------------------------------
+VGND |VGND
+VNB |VNB
+VPB |VPB
+VPWR |VPWR
+B |B
+X |X
+C_N |C_N
+A |A
+---------------------------------------------------------------------------------------
+Cell pin lists are equivalent.
+Device classes sky130_fd_sc_hd__or3b_2 and sky130_fd_sc_hd__or3b_2 are equivalent.
+
+Class sky130_fd_sc_hd__or3b_4 (0): Merged 6 parallel devices.
+Class sky130_fd_sc_hd__or3b_4 (1): Merged 6 parallel devices.
+Subcircuit summary:
+Circuit 1: sky130_fd_sc_hd__or3b_4 |Circuit 2: sky130_fd_sc_hd__or3b_4
+-------------------------------------------|-------------------------------------------
+sky130_fd_pr__pfet_01v8_hvt (8->5) |sky130_fd_pr__pfet_01v8_hvt (8->5)
+sky130_fd_pr__nfet_01v8 (8->5) |sky130_fd_pr__nfet_01v8 (8->5)
+Number of devices: 10 |Number of devices: 10
+Number of nets: 12 |Number of nets: 12
+---------------------------------------------------------------------------------------
+Netlists match uniquely.
+
+Subcircuit pins:
+Circuit 1: sky130_fd_sc_hd__or3b_4 |Circuit 2: sky130_fd_sc_hd__or3b_4
+-------------------------------------------|-------------------------------------------
+VPWR |VPWR
+VGND |VGND
+VNB |VNB
+VPB |VPB
+X |X
+B |B
+C_N |C_N
+A |A
+---------------------------------------------------------------------------------------
+Cell pin lists are equivalent.
+Device classes sky130_fd_sc_hd__or3b_4 and sky130_fd_sc_hd__or3b_4 are equivalent.
+
+Subcircuit summary:
+Circuit 1: sky130_fd_sc_hd__a22oi_1 |Circuit 2: sky130_fd_sc_hd__a22oi_1
+-------------------------------------------|-------------------------------------------
+sky130_fd_pr__nfet_01v8 (4) |sky130_fd_pr__nfet_01v8 (4)
+sky130_fd_pr__pfet_01v8_hvt (4) |sky130_fd_pr__pfet_01v8_hvt (4)
+Number of devices: 8 |Number of devices: 8
+Number of nets: 12 |Number of nets: 12
+---------------------------------------------------------------------------------------
+Netlists match uniquely.
+
+Subcircuit pins:
+Circuit 1: sky130_fd_sc_hd__a22oi_1 |Circuit 2: sky130_fd_sc_hd__a22oi_1
+-------------------------------------------|-------------------------------------------
+B1 |B1
+A2 |A2
+VPWR |VPWR
+A1 |A1
+VGND |VGND
+B2 |B2
+Y |Y
+VNB |VNB
+VPB |VPB
+---------------------------------------------------------------------------------------
+Cell pin lists are equivalent.
+Device classes sky130_fd_sc_hd__a22oi_1 and sky130_fd_sc_hd__a22oi_1 are equivalent.
+
+Class sky130_fd_sc_hd__o31a_2 (0): Merged 2 parallel devices.
+Class sky130_fd_sc_hd__o31a_2 (1): Merged 2 parallel devices.
+Subcircuit summary:
+Circuit 1: sky130_fd_sc_hd__o31a_2 |Circuit 2: sky130_fd_sc_hd__o31a_2
+-------------------------------------------|-------------------------------------------
+sky130_fd_pr__nfet_01v8 (6->5) |sky130_fd_pr__nfet_01v8 (6->5)
+sky130_fd_pr__pfet_01v8_hvt (6->5) |sky130_fd_pr__pfet_01v8_hvt (6->5)
+Number of devices: 10 |Number of devices: 10
+Number of nets: 13 |Number of nets: 13
+---------------------------------------------------------------------------------------
+Netlists match uniquely.
+
+Subcircuit pins:
+Circuit 1: sky130_fd_sc_hd__o31a_2 |Circuit 2: sky130_fd_sc_hd__o31a_2
+-------------------------------------------|-------------------------------------------
+VPWR |VPWR
+VGND |VGND
+A3 |A3
+X |X
+B1 |B1
+A1 |A1
+A2 |A2
+VPB |VPB
+VNB |VNB
+---------------------------------------------------------------------------------------
+Cell pin lists are equivalent.
+Device classes sky130_fd_sc_hd__o31a_2 and sky130_fd_sc_hd__o31a_2 are equivalent.
+
+Class sky130_fd_sc_hd__or2_4 (0): Merged 6 parallel devices.
+Class sky130_fd_sc_hd__or2_4 (1): Merged 6 parallel devices.
+Subcircuit summary:
+Circuit 1: sky130_fd_sc_hd__or2_4 |Circuit 2: sky130_fd_sc_hd__or2_4
+-------------------------------------------|-------------------------------------------
+sky130_fd_pr__pfet_01v8_hvt (6->3) |sky130_fd_pr__pfet_01v8_hvt (6->3)
+sky130_fd_pr__nfet_01v8 (6->3) |sky130_fd_pr__nfet_01v8 (6->3)
+Number of devices: 6 |Number of devices: 6
+Number of nets: 9 |Number of nets: 9
+---------------------------------------------------------------------------------------
+Netlists match uniquely.
+
+Subcircuit pins:
+Circuit 1: sky130_fd_sc_hd__or2_4 |Circuit 2: sky130_fd_sc_hd__or2_4
+-------------------------------------------|-------------------------------------------
+VPB |VPB
+VGND |VGND
+VNB |VNB
+B |B
+X |X
+VPWR |VPWR
+A |A
+---------------------------------------------------------------------------------------
+Cell pin lists are equivalent.
+Device classes sky130_fd_sc_hd__or2_4 and sky130_fd_sc_hd__or2_4 are equivalent.
+
+Class sky130_fd_sc_hd__a21o_2 (0): Merged 2 parallel devices.
+Class sky130_fd_sc_hd__a21o_2 (1): Merged 2 parallel devices.
+Subcircuit summary:
+Circuit 1: sky130_fd_sc_hd__a21o_2 |Circuit 2: sky130_fd_sc_hd__a21o_2
+-------------------------------------------|-------------------------------------------
+sky130_fd_pr__pfet_01v8_hvt (5->4) |sky130_fd_pr__pfet_01v8_hvt (5->4)
+sky130_fd_pr__nfet_01v8 (5->4) |sky130_fd_pr__nfet_01v8 (5->4)
+Number of devices: 8 |Number of devices: 8
+Number of nets: 11 |Number of nets: 11
+---------------------------------------------------------------------------------------
+Netlists match uniquely.
+
+Subcircuit pins:
+Circuit 1: sky130_fd_sc_hd__a21o_2 |Circuit 2: sky130_fd_sc_hd__a21o_2
+-------------------------------------------|-------------------------------------------
+VNB |VNB
+VPB |VPB
+A1 |A1
+X |X
+B1 |B1
+A2 |A2
+VPWR |VPWR
+VGND |VGND
+---------------------------------------------------------------------------------------
+Cell pin lists are equivalent.
+Device classes sky130_fd_sc_hd__a21o_2 and sky130_fd_sc_hd__a21o_2 are equivalent.
+
+Class sky130_fd_sc_hd__a31o_2 (0): Merged 2 parallel devices.
+Class sky130_fd_sc_hd__a31o_2 (1): Merged 2 parallel devices.
+Subcircuit summary:
+Circuit 1: sky130_fd_sc_hd__a31o_2 |Circuit 2: sky130_fd_sc_hd__a31o_2
+-------------------------------------------|-------------------------------------------
+sky130_fd_pr__pfet_01v8_hvt (6->5) |sky130_fd_pr__pfet_01v8_hvt (6->5)
+sky130_fd_pr__nfet_01v8 (6->5) |sky130_fd_pr__nfet_01v8 (6->5)
+Number of devices: 10 |Number of devices: 10
+Number of nets: 13 |Number of nets: 13
+---------------------------------------------------------------------------------------
+Netlists match uniquely.
+
+Subcircuit pins:
+Circuit 1: sky130_fd_sc_hd__a31o_2 |Circuit 2: sky130_fd_sc_hd__a31o_2
+-------------------------------------------|-------------------------------------------
+VGND |VGND
+VNB |VNB
+VPB |VPB
+A2 |A2
+A1 |A1
+B1 |B1
+A3 |A3
+X |X
+VPWR |VPWR
+---------------------------------------------------------------------------------------
+Cell pin lists are equivalent.
+Device classes sky130_fd_sc_hd__a31o_2 and sky130_fd_sc_hd__a31o_2 are equivalent.
+
+Class sky130_fd_sc_hd__and4bb_4 (0): Merged 6 parallel devices.
+Class sky130_fd_sc_hd__and4bb_4 (1): Merged 6 parallel devices.
+Subcircuit summary:
+Circuit 1: sky130_fd_sc_hd__and4bb_4 |Circuit 2: sky130_fd_sc_hd__and4bb_4
+-------------------------------------------|-------------------------------------------
+sky130_fd_pr__pfet_01v8_hvt (10->7) |sky130_fd_pr__pfet_01v8_hvt (10->7)
+sky130_fd_pr__nfet_01v8 (10->7) |sky130_fd_pr__nfet_01v8 (10->7)
+Number of devices: 14 |Number of devices: 14
+Number of nets: 15 |Number of nets: 15
+---------------------------------------------------------------------------------------
+Netlists match uniquely.
+
+Subcircuit pins:
+Circuit 1: sky130_fd_sc_hd__and4bb_4 |Circuit 2: sky130_fd_sc_hd__and4bb_4
+-------------------------------------------|-------------------------------------------
+VGND |VGND
+X |X
+C |C
+D |D
+B_N |B_N
+A_N |A_N
+VPWR |VPWR
+VPB |VPB
+VNB |VNB
+---------------------------------------------------------------------------------------
+Cell pin lists are equivalent.
+Device classes sky130_fd_sc_hd__and4bb_4 and sky130_fd_sc_hd__and4bb_4 are equivalent.
+
+Subcircuit summary:
+Circuit 1: sky130_fd_sc_hd__o41ai_1 |Circuit 2: sky130_fd_sc_hd__o41ai_1
+-------------------------------------------|-------------------------------------------
+sky130_fd_pr__pfet_01v8_hvt (5) |sky130_fd_pr__pfet_01v8_hvt (5)
+sky130_fd_pr__nfet_01v8 (5) |sky130_fd_pr__nfet_01v8 (5)
+Number of devices: 10 |Number of devices: 10
+Number of nets: 14 |Number of nets: 14
+---------------------------------------------------------------------------------------
+Netlists match uniquely.
+
+Subcircuit pins:
+Circuit 1: sky130_fd_sc_hd__o41ai_1 |Circuit 2: sky130_fd_sc_hd__o41ai_1
+-------------------------------------------|-------------------------------------------
+Y |Y
+VGND |VGND
+VPB |VPB
+VNB |VNB
+A2 |A2
+A1 |A1
+A3 |A3
+A4 |A4
+VPWR |VPWR
+B1 |B1
+---------------------------------------------------------------------------------------
+Cell pin lists are equivalent.
+Device classes sky130_fd_sc_hd__o41ai_1 and sky130_fd_sc_hd__o41ai_1 are equivalent.
+
+Class sky130_fd_sc_hd__o21ba_2 (0): Merged 2 parallel devices.
+Class sky130_fd_sc_hd__o21ba_2 (1): Merged 2 parallel devices.
+Subcircuit summary:
+Circuit 1: sky130_fd_sc_hd__o21ba_2 |Circuit 2: sky130_fd_sc_hd__o21ba_2
+-------------------------------------------|-------------------------------------------
+sky130_fd_pr__nfet_01v8 (6->5) |sky130_fd_pr__nfet_01v8 (6->5)
+sky130_fd_pr__pfet_01v8_hvt (6->5) |sky130_fd_pr__pfet_01v8_hvt (6->5)
+Number of devices: 10 |Number of devices: 10
+Number of nets: 12 |Number of nets: 12
+---------------------------------------------------------------------------------------
+Netlists match uniquely.
+
+Subcircuit pins:
+Circuit 1: sky130_fd_sc_hd__o21ba_2 |Circuit 2: sky130_fd_sc_hd__o21ba_2
+-------------------------------------------|-------------------------------------------
+VNB |VNB
+VPB |VPB
+X |X
+A2 |A2
+A1 |A1
+B1_N |B1_N
+VGND |VGND
+VPWR |VPWR
+---------------------------------------------------------------------------------------
+Cell pin lists are equivalent.
+Device classes sky130_fd_sc_hd__o21ba_2 and sky130_fd_sc_hd__o21ba_2 are equivalent.
+
+Class sky130_fd_sc_hd__nor3_2 (0): Merged 6 parallel devices.
+Class sky130_fd_sc_hd__nor3_2 (1): Merged 6 parallel devices.
+Subcircuit summary:
+Circuit 1: sky130_fd_sc_hd__nor3_2 |Circuit 2: sky130_fd_sc_hd__nor3_2
+-------------------------------------------|-------------------------------------------
+sky130_fd_pr__pfet_01v8_hvt (6->3) |sky130_fd_pr__pfet_01v8_hvt (6->3)
+sky130_fd_pr__nfet_01v8 (6->3) |sky130_fd_pr__nfet_01v8 (6->3)
+Number of devices: 6 |Number of devices: 6
+Number of nets: 10 |Number of nets: 10
+---------------------------------------------------------------------------------------
+Netlists match uniquely.
+
+Subcircuit pins:
+Circuit 1: sky130_fd_sc_hd__nor3_2 |Circuit 2: sky130_fd_sc_hd__nor3_2
+-------------------------------------------|-------------------------------------------
+VPWR |VPWR
+VGND |VGND
+VNB |VNB
+VPB |VPB
+B |B
+C |C
+A |A
+Y |Y
+---------------------------------------------------------------------------------------
+Cell pin lists are equivalent.
+Device classes sky130_fd_sc_hd__nor3_2 and sky130_fd_sc_hd__nor3_2 are equivalent.
+
+Class sky130_fd_sc_hd__a32o_2 (0): Merged 2 parallel devices.
+Class sky130_fd_sc_hd__a32o_2 (1): Merged 2 parallel devices.
+Subcircuit summary:
+Circuit 1: sky130_fd_sc_hd__a32o_2 |Circuit 2: sky130_fd_sc_hd__a32o_2
+-------------------------------------------|-------------------------------------------
+sky130_fd_pr__pfet_01v8_hvt (7->6) |sky130_fd_pr__pfet_01v8_hvt (7->6)
+sky130_fd_pr__nfet_01v8 (7->6) |sky130_fd_pr__nfet_01v8 (7->6)
+Number of devices: 12 |Number of devices: 12
+Number of nets: 15 |Number of nets: 15
+---------------------------------------------------------------------------------------
+Netlists match uniquely.
+
+Subcircuit pins:
+Circuit 1: sky130_fd_sc_hd__a32o_2 |Circuit 2: sky130_fd_sc_hd__a32o_2
+-------------------------------------------|-------------------------------------------
+VGND |VGND
+VNB |VNB
+VPB |VPB
+A2 |A2
+B2 |B2
+A1 |A1
+B1 |B1
+A3 |A3
+X |X
+VPWR |VPWR
+---------------------------------------------------------------------------------------
+Cell pin lists are equivalent.
+Device classes sky130_fd_sc_hd__a32o_2 and sky130_fd_sc_hd__a32o_2 are equivalent.
+
+Class sky130_fd_sc_hd__a32o_4 (0): Merged 16 parallel devices.
+Class sky130_fd_sc_hd__a32o_4 (1): Merged 16 parallel devices.
+Subcircuit summary:
+Circuit 1: sky130_fd_sc_hd__a32o_4 |Circuit 2: sky130_fd_sc_hd__a32o_4
+-------------------------------------------|-------------------------------------------
+sky130_fd_pr__nfet_01v8 (14->6) |sky130_fd_pr__nfet_01v8 (14->6)
+sky130_fd_pr__pfet_01v8_hvt (14->6) |sky130_fd_pr__pfet_01v8_hvt (14->6)
+Number of devices: 12 |Number of devices: 12
+Number of nets: 15 |Number of nets: 15
+---------------------------------------------------------------------------------------
+Netlists match uniquely.
+
+Subcircuit pins:
+Circuit 1: sky130_fd_sc_hd__a32o_4 |Circuit 2: sky130_fd_sc_hd__a32o_4
+-------------------------------------------|-------------------------------------------
+VPWR |VPWR
+VPB |VPB
+VNB |VNB
+B2 |B2
+A1 |A1
+B1 |B1
+A3 |A3
+A2 |A2
+X |X
+VGND |VGND
+---------------------------------------------------------------------------------------
+Cell pin lists are equivalent.
+Device classes sky130_fd_sc_hd__a32o_4 and sky130_fd_sc_hd__a32o_4 are equivalent.
+
+Class sky130_fd_sc_hd__o21ai_2 (0): Merged 6 parallel devices.
+Class sky130_fd_sc_hd__o21ai_2 (1): Merged 6 parallel devices.
+Subcircuit summary:
+Circuit 1: sky130_fd_sc_hd__o21ai_2 |Circuit 2: sky130_fd_sc_hd__o21ai_2
+-------------------------------------------|-------------------------------------------
+sky130_fd_pr__nfet_01v8 (6->3) |sky130_fd_pr__nfet_01v8 (6->3)
+sky130_fd_pr__pfet_01v8_hvt (6->3) |sky130_fd_pr__pfet_01v8_hvt (6->3)
+Number of devices: 6 |Number of devices: 6
+Number of nets: 10 |Number of nets: 10
+---------------------------------------------------------------------------------------
+Netlists match uniquely.
+
+Subcircuit pins:
+Circuit 1: sky130_fd_sc_hd__o21ai_2 |Circuit 2: sky130_fd_sc_hd__o21ai_2
+-------------------------------------------|-------------------------------------------
+Y |Y
+VPB |VPB
+VNB |VNB
+A2 |A2
+VGND |VGND
+VPWR |VPWR
+B1 |B1
+A1 |A1
+---------------------------------------------------------------------------------------
+Cell pin lists are equivalent.
+Device classes sky130_fd_sc_hd__o21ai_2 and sky130_fd_sc_hd__o21ai_2 are equivalent.
+
+Class sky130_fd_sc_hd__or2_2 (0): Merged 2 parallel devices.
+Class sky130_fd_sc_hd__or2_2 (1): Merged 2 parallel devices.
+Subcircuit summary:
+Circuit 1: sky130_fd_sc_hd__or2_2 |Circuit 2: sky130_fd_sc_hd__or2_2
+-------------------------------------------|-------------------------------------------
+sky130_fd_pr__pfet_01v8_hvt (4->3) |sky130_fd_pr__pfet_01v8_hvt (4->3)
+sky130_fd_pr__nfet_01v8 (4->3) |sky130_fd_pr__nfet_01v8 (4->3)
+Number of devices: 6 |Number of devices: 6
+Number of nets: 9 |Number of nets: 9
+---------------------------------------------------------------------------------------
+Netlists match uniquely.
+
+Subcircuit pins:
+Circuit 1: sky130_fd_sc_hd__or2_2 |Circuit 2: sky130_fd_sc_hd__or2_2
+-------------------------------------------|-------------------------------------------
+VPB |VPB
+VGND |VGND
+VNB |VNB
+B |B
+X |X
+VPWR |VPWR
+A |A
+---------------------------------------------------------------------------------------
+Cell pin lists are equivalent.
+Device classes sky130_fd_sc_hd__or2_2 and sky130_fd_sc_hd__or2_2 are equivalent.
+
+Class sky130_fd_sc_hd__nand3_2 (0): Merged 6 parallel devices.
+Class sky130_fd_sc_hd__nand3_2 (1): Merged 6 parallel devices.
+Subcircuit summary:
+Circuit 1: sky130_fd_sc_hd__nand3_2 |Circuit 2: sky130_fd_sc_hd__nand3_2
+-------------------------------------------|-------------------------------------------
+sky130_fd_pr__nfet_01v8 (6->3) |sky130_fd_pr__nfet_01v8 (6->3)
+sky130_fd_pr__pfet_01v8_hvt (6->3) |sky130_fd_pr__pfet_01v8_hvt (6->3)
+Number of devices: 6 |Number of devices: 6
+Number of nets: 10 |Number of nets: 10
+---------------------------------------------------------------------------------------
+Netlists match uniquely.
+
+Subcircuit pins:
+Circuit 1: sky130_fd_sc_hd__nand3_2 |Circuit 2: sky130_fd_sc_hd__nand3_2
+-------------------------------------------|-------------------------------------------
+Y |Y
+VNB |VNB
+VPWR |VPWR
+VPB |VPB
+C |C
+B |B
+A |A
+VGND |VGND
+---------------------------------------------------------------------------------------
+Cell pin lists are equivalent.
+Device classes sky130_fd_sc_hd__nand3_2 and sky130_fd_sc_hd__nand3_2 are equivalent.
+
+Class sky130_fd_sc_hd__o211ai_4 (0): Merged 20 parallel devices.
+Class sky130_fd_sc_hd__o211ai_4 (1): Merged 20 parallel devices.
+Subcircuit summary:
+Circuit 1: sky130_fd_sc_hd__o211ai_4 |Circuit 2: sky130_fd_sc_hd__o211ai_4
+-------------------------------------------|-------------------------------------------
+sky130_fd_pr__pfet_01v8_hvt (16->4) |sky130_fd_pr__pfet_01v8_hvt (16->4)
+sky130_fd_pr__nfet_01v8 (16->8) |sky130_fd_pr__nfet_01v8 (16->8)
+Number of devices: 12 |Number of devices: 12
+Number of nets: 14 |Number of nets: 14
+---------------------------------------------------------------------------------------
+Resolving automorphisms by property value.
+Resolving automorphisms by pin name.
+Netlists match uniquely.
+
+Subcircuit pins:
+Circuit 1: sky130_fd_sc_hd__o211ai_4 |Circuit 2: sky130_fd_sc_hd__o211ai_4
+-------------------------------------------|-------------------------------------------
+VNB |VNB
+Y |Y
+B1 |B1
+C1 |C1
+VPB |VPB
+A1 |A1
+VGND |VGND
+A2 |A2
+VPWR |VPWR
+---------------------------------------------------------------------------------------
+Cell pin lists are equivalent.
+Device classes sky130_fd_sc_hd__o211ai_4 and sky130_fd_sc_hd__o211ai_4 are equivalent.
+
+Subcircuit summary:
+Circuit 1: sky130_fd_sc_hd__o311ai_1 |Circuit 2: sky130_fd_sc_hd__o311ai_1
+-------------------------------------------|-------------------------------------------
+sky130_fd_pr__nfet_01v8 (5) |sky130_fd_pr__nfet_01v8 (5)
+sky130_fd_pr__pfet_01v8_hvt (5) |sky130_fd_pr__pfet_01v8_hvt (5)
+Number of devices: 10 |Number of devices: 10
+Number of nets: 14 |Number of nets: 14
+---------------------------------------------------------------------------------------
+Netlists match uniquely.
+
+Subcircuit pins:
+Circuit 1: sky130_fd_sc_hd__o311ai_1 |Circuit 2: sky130_fd_sc_hd__o311ai_1
+-------------------------------------------|-------------------------------------------
+VPB |VPB
+VNB |VNB
+Y |Y
+B1 |B1
+C1 |C1
+A3 |A3
+A2 |A2
+A1 |A1
+VPWR |VPWR
+VGND |VGND
+---------------------------------------------------------------------------------------
+Cell pin lists are equivalent.
+Device classes sky130_fd_sc_hd__o311ai_1 and sky130_fd_sc_hd__o311ai_1 are equivalent.
+
+Subcircuit summary:
+Circuit 1: sky130_fd_sc_hd__nor4b_1 |Circuit 2: sky130_fd_sc_hd__nor4b_1
+-------------------------------------------|-------------------------------------------
+sky130_fd_pr__nfet_01v8 (5) |sky130_fd_pr__nfet_01v8 (5)
+sky130_fd_pr__pfet_01v8_hvt (5) |sky130_fd_pr__pfet_01v8_hvt (5)
+Number of devices: 10 |Number of devices: 10
+Number of nets: 13 |Number of nets: 13
+---------------------------------------------------------------------------------------
+Netlists match uniquely.
+
+Subcircuit pins:
+Circuit 1: sky130_fd_sc_hd__nor4b_1 |Circuit 2: sky130_fd_sc_hd__nor4b_1
+-------------------------------------------|-------------------------------------------
+VPWR |VPWR
+D_N |D_N
+A |A
+C |C
+B |B
+VPB |VPB
+VGND |VGND
+VNB |VNB
+Y |Y
+---------------------------------------------------------------------------------------
+Cell pin lists are equivalent.
+Device classes sky130_fd_sc_hd__nor4b_1 and sky130_fd_sc_hd__nor4b_1 are equivalent.
+
+Subcircuit summary:
+Circuit 1: sky130_fd_sc_hd__o31ai_1 |Circuit 2: sky130_fd_sc_hd__o31ai_1
+-------------------------------------------|-------------------------------------------
+sky130_fd_pr__nfet_01v8 (4) |sky130_fd_pr__nfet_01v8 (4)
+sky130_fd_pr__pfet_01v8_hvt (4) |sky130_fd_pr__pfet_01v8_hvt (4)
+Number of devices: 8 |Number of devices: 8
+Number of nets: 12 |Number of nets: 12
+---------------------------------------------------------------------------------------
+Netlists match uniquely.
+
+Subcircuit pins:
+Circuit 1: sky130_fd_sc_hd__o31ai_1 |Circuit 2: sky130_fd_sc_hd__o31ai_1
+-------------------------------------------|-------------------------------------------
+VPB |VPB
+VNB |VNB
+A3 |A3
+B1 |B1
+VPWR |VPWR
+A1 |A1
+A2 |A2
+Y |Y
+VGND |VGND
+---------------------------------------------------------------------------------------
+Cell pin lists are equivalent.
+Device classes sky130_fd_sc_hd__o31ai_1 and sky130_fd_sc_hd__o31ai_1 are equivalent.
+
+Class sky130_fd_sc_hd__nor4_2 (0): Merged 8 parallel devices.
+Class sky130_fd_sc_hd__nor4_2 (1): Merged 8 parallel devices.
+Subcircuit summary:
+Circuit 1: sky130_fd_sc_hd__nor4_2 |Circuit 2: sky130_fd_sc_hd__nor4_2
+-------------------------------------------|-------------------------------------------
+sky130_fd_pr__pfet_01v8_hvt (8->4) |sky130_fd_pr__pfet_01v8_hvt (8->4)
+sky130_fd_pr__nfet_01v8 (8->4) |sky130_fd_pr__nfet_01v8 (8->4)
+Number of devices: 8 |Number of devices: 8
+Number of nets: 12 |Number of nets: 12
+---------------------------------------------------------------------------------------
+Netlists match uniquely.
+
+Subcircuit pins:
+Circuit 1: sky130_fd_sc_hd__nor4_2 |Circuit 2: sky130_fd_sc_hd__nor4_2
+-------------------------------------------|-------------------------------------------
+VPWR |VPWR
+Y |Y
+VGND |VGND
+VNB |VNB
+VPB |VPB
+A |A
+C |C
+B |B
+D |D
+---------------------------------------------------------------------------------------
+Cell pin lists are equivalent.
+Device classes sky130_fd_sc_hd__nor4_2 and sky130_fd_sc_hd__nor4_2 are equivalent.
+
+Subcircuit summary:
+Circuit 1: sky130_fd_sc_hd__o22ai_1 |Circuit 2: sky130_fd_sc_hd__o22ai_1
+-------------------------------------------|-------------------------------------------
+sky130_fd_pr__nfet_01v8 (4) |sky130_fd_pr__nfet_01v8 (4)
+sky130_fd_pr__pfet_01v8_hvt (4) |sky130_fd_pr__pfet_01v8_hvt (4)
+Number of devices: 8 |Number of devices: 8
+Number of nets: 12 |Number of nets: 12
+---------------------------------------------------------------------------------------
+Netlists match uniquely.
+
+Subcircuit pins:
+Circuit 1: sky130_fd_sc_hd__o22ai_1 |Circuit 2: sky130_fd_sc_hd__o22ai_1
+-------------------------------------------|-------------------------------------------
+Y |Y
+VPB |VPB
+VNB |VNB
+A2 |A2
+A1 |A1
+VPWR |VPWR
+B2 |B2
+VGND |VGND
+B1 |B1
+---------------------------------------------------------------------------------------
+Cell pin lists are equivalent.
+Device classes sky130_fd_sc_hd__o22ai_1 and sky130_fd_sc_hd__o22ai_1 are equivalent.
+
+Class sky130_fd_sc_hd__nand2_4 (0): Merged 12 parallel devices.
+Class sky130_fd_sc_hd__nand2_4 (1): Merged 12 parallel devices.
+Subcircuit summary:
+Circuit 1: sky130_fd_sc_hd__nand2_4 |Circuit 2: sky130_fd_sc_hd__nand2_4
+-------------------------------------------|-------------------------------------------
+sky130_fd_pr__nfet_01v8 (8->2) |sky130_fd_pr__nfet_01v8 (8->2)
+sky130_fd_pr__pfet_01v8_hvt (8->2) |sky130_fd_pr__pfet_01v8_hvt (8->2)
+Number of devices: 4 |Number of devices: 4
+Number of nets: 8 |Number of nets: 8
+---------------------------------------------------------------------------------------
+Netlists match uniquely.
+
+Subcircuit pins:
+Circuit 1: sky130_fd_sc_hd__nand2_4 |Circuit 2: sky130_fd_sc_hd__nand2_4
+-------------------------------------------|-------------------------------------------
+VGND |VGND
+Y |Y
+A |A
+VNB |VNB
+VPWR |VPWR
+VPB |VPB
+B |B
+---------------------------------------------------------------------------------------
+Cell pin lists are equivalent.
+Device classes sky130_fd_sc_hd__nand2_4 and sky130_fd_sc_hd__nand2_4 are equivalent.
+
+Class sky130_fd_sc_hd__o21bai_4 (0): Merged 18 parallel devices.
+Class sky130_fd_sc_hd__o21bai_4 (1): Merged 18 parallel devices.
+Subcircuit summary:
+Circuit 1: sky130_fd_sc_hd__o21bai_4 |Circuit 2: sky130_fd_sc_hd__o21bai_4
+-------------------------------------------|-------------------------------------------
+sky130_fd_pr__pfet_01v8_hvt (13->4) |sky130_fd_pr__pfet_01v8_hvt (13->4)
+sky130_fd_pr__nfet_01v8 (13->4) |sky130_fd_pr__nfet_01v8 (13->4)
+Number of devices: 8 |Number of devices: 8
+Number of nets: 11 |Number of nets: 11
+---------------------------------------------------------------------------------------
+Netlists match uniquely.
+
+Subcircuit pins:
+Circuit 1: sky130_fd_sc_hd__o21bai_4 |Circuit 2: sky130_fd_sc_hd__o21bai_4
+-------------------------------------------|-------------------------------------------
+A1 |A1
+A2 |A2
+B1_N |B1_N
+VNB |VNB
+VPB |VPB
+Y |Y
+VGND |VGND
+VPWR |VPWR
+---------------------------------------------------------------------------------------
+Cell pin lists are equivalent.
+Device classes sky130_fd_sc_hd__o21bai_4 and sky130_fd_sc_hd__o21bai_4 are equivalent.
+
+Subcircuit summary:
+Circuit 1: sky130_fd_sc_hd__a211oi_1 |Circuit 2: sky130_fd_sc_hd__a211oi_1
+-------------------------------------------|-------------------------------------------
+sky130_fd_pr__pfet_01v8_hvt (4) |sky130_fd_pr__pfet_01v8_hvt (4)
+sky130_fd_pr__nfet_01v8 (4) |sky130_fd_pr__nfet_01v8 (4)
+Number of devices: 8 |Number of devices: 8
+Number of nets: 12 |Number of nets: 12
+---------------------------------------------------------------------------------------
+Netlists match uniquely.
+
+Subcircuit pins:
+Circuit 1: sky130_fd_sc_hd__a211oi_1 |Circuit 2: sky130_fd_sc_hd__a211oi_1
+-------------------------------------------|-------------------------------------------
+VNB |VNB
+Y |Y
+VPB |VPB
+A2 |A2
+C1 |C1
+VPWR |VPWR
+A1 |A1
+B1 |B1
+VGND |VGND
+---------------------------------------------------------------------------------------
+Cell pin lists are equivalent.
+Device classes sky130_fd_sc_hd__a211oi_1 and sky130_fd_sc_hd__a211oi_1 are equivalent.
+
+Class sky130_fd_sc_hd__inv_4 (0): Merged 6 parallel devices.
+Class sky130_fd_sc_hd__inv_4 (1): Merged 6 parallel devices.
+Subcircuit summary:
+Circuit 1: sky130_fd_sc_hd__inv_4 |Circuit 2: sky130_fd_sc_hd__inv_4
+-------------------------------------------|-------------------------------------------
+sky130_fd_pr__pfet_01v8_hvt (4->1) |sky130_fd_pr__pfet_01v8_hvt (4->1)
+sky130_fd_pr__nfet_01v8 (4->1) |sky130_fd_pr__nfet_01v8 (4->1)
+Number of devices: 2 |Number of devices: 2
+Number of nets: 6 |Number of nets: 6
+---------------------------------------------------------------------------------------
+Netlists match uniquely.
+
+Subcircuit pins:
+Circuit 1: sky130_fd_sc_hd__inv_4 |Circuit 2: sky130_fd_sc_hd__inv_4
+-------------------------------------------|-------------------------------------------
+Y |Y
+A |A
+VGND |VGND
+VNB |VNB
+VPWR |VPWR
+VPB |VPB
+---------------------------------------------------------------------------------------
+Cell pin lists are equivalent.
+Device classes sky130_fd_sc_hd__inv_4 and sky130_fd_sc_hd__inv_4 are equivalent.
+
+Class sky130_fd_sc_hd__mux2_8 (0): Merged 22 parallel devices.
+Class sky130_fd_sc_hd__mux2_8 (1): Merged 22 parallel devices.
+Subcircuit summary:
+Circuit 1: sky130_fd_sc_hd__mux2_8 |Circuit 2: sky130_fd_sc_hd__mux2_8
+-------------------------------------------|-------------------------------------------
+sky130_fd_pr__nfet_01v8 (17->6) |sky130_fd_pr__nfet_01v8 (17->6)
+sky130_fd_pr__pfet_01v8_hvt (17->6) |sky130_fd_pr__pfet_01v8_hvt (17->6)
+Number of devices: 12 |Number of devices: 12
+Number of nets: 14 |Number of nets: 14
+---------------------------------------------------------------------------------------
+Netlists match uniquely.
+
+Subcircuit pins:
+Circuit 1: sky130_fd_sc_hd__mux2_8 |Circuit 2: sky130_fd_sc_hd__mux2_8
+-------------------------------------------|-------------------------------------------
+X |X
+A0 |A0
+A1 |A1
+VNB |VNB
+VPB |VPB
+VGND |VGND
+S |S
+VPWR |VPWR
+---------------------------------------------------------------------------------------
+Cell pin lists are equivalent.
+Device classes sky130_fd_sc_hd__mux2_8 and sky130_fd_sc_hd__mux2_8 are equivalent.
+
+Class sky130_fd_sc_hd__inv_6 (0): Merged 10 parallel devices.
+Class sky130_fd_sc_hd__inv_6 (1): Merged 10 parallel devices.
+Subcircuit summary:
+Circuit 1: sky130_fd_sc_hd__inv_6 |Circuit 2: sky130_fd_sc_hd__inv_6
+-------------------------------------------|-------------------------------------------
+sky130_fd_pr__pfet_01v8_hvt (6->1) |sky130_fd_pr__pfet_01v8_hvt (6->1)
+sky130_fd_pr__nfet_01v8 (6->1) |sky130_fd_pr__nfet_01v8 (6->1)
+Number of devices: 2 |Number of devices: 2
+Number of nets: 6 |Number of nets: 6
+---------------------------------------------------------------------------------------
+Netlists match uniquely.
+
+Subcircuit pins:
+Circuit 1: sky130_fd_sc_hd__inv_6 |Circuit 2: sky130_fd_sc_hd__inv_6
+-------------------------------------------|-------------------------------------------
+A |A
+Y |Y
+VPWR |VPWR
+VPB |VPB
+VGND |VGND
+VNB |VNB
+---------------------------------------------------------------------------------------
+Cell pin lists are equivalent.
+Device classes sky130_fd_sc_hd__inv_6 and sky130_fd_sc_hd__inv_6 are equivalent.
+
+Class sky130_fd_sc_hd__a22oi_4 (0): Merged 24 parallel devices.
+Class sky130_fd_sc_hd__a22oi_4 (1): Merged 24 parallel devices.
+Subcircuit summary:
+Circuit 1: sky130_fd_sc_hd__a22oi_4 |Circuit 2: sky130_fd_sc_hd__a22oi_4
+-------------------------------------------|-------------------------------------------
+sky130_fd_pr__nfet_01v8 (16->4) |sky130_fd_pr__nfet_01v8 (16->4)
+sky130_fd_pr__pfet_01v8_hvt (16->4) |sky130_fd_pr__pfet_01v8_hvt (16->4)
+Number of devices: 8 |Number of devices: 8
+Number of nets: 12 |Number of nets: 12
+---------------------------------------------------------------------------------------
+Netlists match uniquely.
+
+Subcircuit pins:
+Circuit 1: sky130_fd_sc_hd__a22oi_4 |Circuit 2: sky130_fd_sc_hd__a22oi_4
+-------------------------------------------|-------------------------------------------
+VPB |VPB
+Y |Y
+VNB |VNB
+VPWR |VPWR
+A2 |A2
+A1 |A1
+B1 |B1
+VGND |VGND
+B2 |B2
+---------------------------------------------------------------------------------------
+Cell pin lists are equivalent.
+Device classes sky130_fd_sc_hd__a22oi_4 and sky130_fd_sc_hd__a22oi_4 are equivalent.
+
+Class sky130_fd_sc_hd__nor2_8 (0): Merged 28 parallel devices.
+Class sky130_fd_sc_hd__nor2_8 (1): Merged 28 parallel devices.
+Subcircuit summary:
+Circuit 1: sky130_fd_sc_hd__nor2_8 |Circuit 2: sky130_fd_sc_hd__nor2_8
+-------------------------------------------|-------------------------------------------
+sky130_fd_pr__pfet_01v8_hvt (16->2) |sky130_fd_pr__pfet_01v8_hvt (16->2)
+sky130_fd_pr__nfet_01v8 (16->2) |sky130_fd_pr__nfet_01v8 (16->2)
+Number of devices: 4 |Number of devices: 4
+Number of nets: 8 |Number of nets: 8
+---------------------------------------------------------------------------------------
+Netlists match uniquely.
+
+Subcircuit pins:
+Circuit 1: sky130_fd_sc_hd__nor2_8 |Circuit 2: sky130_fd_sc_hd__nor2_8
+-------------------------------------------|-------------------------------------------
+Y |Y
+A |A
+VPB |VPB
+VGND |VGND
+VNB |VNB
+B |B
+VPWR |VPWR
+---------------------------------------------------------------------------------------
+Cell pin lists are equivalent.
+Device classes sky130_fd_sc_hd__nor2_8 and sky130_fd_sc_hd__nor2_8 are equivalent.
+
+Class sky130_fd_sc_hd__nor4_4 (0): Merged 24 parallel devices.
+Class sky130_fd_sc_hd__nor4_4 (1): Merged 24 parallel devices.
+Subcircuit summary:
+Circuit 1: sky130_fd_sc_hd__nor4_4 |Circuit 2: sky130_fd_sc_hd__nor4_4
+-------------------------------------------|-------------------------------------------
+sky130_fd_pr__pfet_01v8_hvt (16->4) |sky130_fd_pr__pfet_01v8_hvt (16->4)
+sky130_fd_pr__nfet_01v8 (16->4) |sky130_fd_pr__nfet_01v8 (16->4)
+Number of devices: 8 |Number of devices: 8
+Number of nets: 12 |Number of nets: 12
+---------------------------------------------------------------------------------------
+Netlists match uniquely.
+
+Subcircuit pins:
+Circuit 1: sky130_fd_sc_hd__nor4_4 |Circuit 2: sky130_fd_sc_hd__nor4_4
+-------------------------------------------|-------------------------------------------
+Y |Y
+VPB |VPB
+VGND |VGND
+VNB |VNB
+B |B
+C |C
+A |A
+D |D
+VPWR |VPWR
+---------------------------------------------------------------------------------------
+Cell pin lists are equivalent.
+Device classes sky130_fd_sc_hd__nor4_4 and sky130_fd_sc_hd__nor4_4 are equivalent.
+
+Class sky130_fd_sc_hd__a41o_2 (0): Merged 2 parallel devices.
+Class sky130_fd_sc_hd__a41o_2 (1): Merged 2 parallel devices.
+Subcircuit summary:
+Circuit 1: sky130_fd_sc_hd__a41o_2 |Circuit 2: sky130_fd_sc_hd__a41o_2
+-------------------------------------------|-------------------------------------------
+sky130_fd_pr__pfet_01v8_hvt (7->6) |sky130_fd_pr__pfet_01v8_hvt (7->6)
+sky130_fd_pr__nfet_01v8 (7->6) |sky130_fd_pr__nfet_01v8 (7->6)
+Number of devices: 12 |Number of devices: 12
+Number of nets: 15 |Number of nets: 15
+---------------------------------------------------------------------------------------
+Netlists match uniquely.
+
+Subcircuit pins:
+Circuit 1: sky130_fd_sc_hd__a41o_2 |Circuit 2: sky130_fd_sc_hd__a41o_2
+-------------------------------------------|-------------------------------------------
+VGND |VGND
+VNB |VNB
+VPB |VPB
+A3 |A3
+A2 |A2
+A4 |A4
+B1 |B1
+A1 |A1
+X |X
+VPWR |VPWR
+---------------------------------------------------------------------------------------
+Cell pin lists are equivalent.
+Device classes sky130_fd_sc_hd__a41o_2 and sky130_fd_sc_hd__a41o_2 are equivalent.
+
+Class sky130_fd_sc_hd__mux2_2 (0): Merged 2 parallel devices.
+Class sky130_fd_sc_hd__mux2_2 (1): Merged 2 parallel devices.
+Subcircuit summary:
+Circuit 1: sky130_fd_sc_hd__mux2_2 |Circuit 2: sky130_fd_sc_hd__mux2_2
+-------------------------------------------|-------------------------------------------
+sky130_fd_pr__pfet_01v8_hvt (7->6) |sky130_fd_pr__pfet_01v8_hvt (7->6)
+sky130_fd_pr__nfet_01v8 (7->6) |sky130_fd_pr__nfet_01v8 (7->6)
+Number of devices: 12 |Number of devices: 12
+Number of nets: 14 |Number of nets: 14
+---------------------------------------------------------------------------------------
+Netlists match uniquely.
+
+Subcircuit pins:
+Circuit 1: sky130_fd_sc_hd__mux2_2 |Circuit 2: sky130_fd_sc_hd__mux2_2
+-------------------------------------------|-------------------------------------------
+VNB |VNB
+VPB |VPB
+A1 |A1
+A0 |A0
+X |X
+VGND |VGND
+VPWR |VPWR
+S |S
+---------------------------------------------------------------------------------------
+Cell pin lists are equivalent.
+Device classes sky130_fd_sc_hd__mux2_2 and sky130_fd_sc_hd__mux2_2 are equivalent.
+
+Class sky130_fd_sc_hd__nand2b_2 (0): Merged 4 parallel devices.
+Class sky130_fd_sc_hd__nand2b_2 (1): Merged 4 parallel devices.
+Subcircuit summary:
+Circuit 1: sky130_fd_sc_hd__nand2b_2 |Circuit 2: sky130_fd_sc_hd__nand2b_2
+-------------------------------------------|-------------------------------------------
+sky130_fd_pr__pfet_01v8_hvt (5->3) |sky130_fd_pr__pfet_01v8_hvt (5->3)
+sky130_fd_pr__nfet_01v8 (5->3) |sky130_fd_pr__nfet_01v8 (5->3)
+Number of devices: 6 |Number of devices: 6
+Number of nets: 9 |Number of nets: 9
+---------------------------------------------------------------------------------------
+Netlists match uniquely.
+
+Subcircuit pins:
+Circuit 1: sky130_fd_sc_hd__nand2b_2 |Circuit 2: sky130_fd_sc_hd__nand2b_2
+-------------------------------------------|-------------------------------------------
+B |B
+VGND |VGND
+A_N |A_N
+VNB |VNB
+VPWR |VPWR
+Y |Y
+VPB |VPB
+---------------------------------------------------------------------------------------
+Cell pin lists are equivalent.
+Device classes sky130_fd_sc_hd__nand2b_2 and sky130_fd_sc_hd__nand2b_2 are equivalent.
+
+Class sky130_fd_sc_hd__o221ai_4 (0): Merged 30 parallel devices.
+Class sky130_fd_sc_hd__o221ai_4 (1): Merged 30 parallel devices.
+Subcircuit summary:
+Circuit 1: sky130_fd_sc_hd__o221ai_4 |Circuit 2: sky130_fd_sc_hd__o221ai_4
+-------------------------------------------|-------------------------------------------
+sky130_fd_pr__nfet_01v8 (20->5) |sky130_fd_pr__nfet_01v8 (20->5)
+sky130_fd_pr__pfet_01v8_hvt (20->5) |sky130_fd_pr__pfet_01v8_hvt (20->5)
+Number of devices: 10 |Number of devices: 10
+Number of nets: 14 |Number of nets: 14
+---------------------------------------------------------------------------------------
+Netlists match uniquely.
+
+Subcircuit pins:
+Circuit 1: sky130_fd_sc_hd__o221ai_4 |Circuit 2: sky130_fd_sc_hd__o221ai_4
+-------------------------------------------|-------------------------------------------
+VPWR |VPWR
+VPB |VPB
+VNB |VNB
+B2 |B2
+C1 |C1
+B1 |B1
+VGND |VGND
+A2 |A2
+A1 |A1
+Y |Y
+---------------------------------------------------------------------------------------
+Cell pin lists are equivalent.
+Device classes sky130_fd_sc_hd__o221ai_4 and sky130_fd_sc_hd__o221ai_4 are equivalent.
+
+Class sky130_fd_sc_hd__a211o_4 (0): Merged 10 parallel devices.
+Class sky130_fd_sc_hd__a211o_4 (1): Merged 10 parallel devices.
+Subcircuit summary:
+Circuit 1: sky130_fd_sc_hd__a211o_4 |Circuit 2: sky130_fd_sc_hd__a211o_4
+-------------------------------------------|-------------------------------------------
+sky130_fd_pr__pfet_01v8_hvt (12->7) |sky130_fd_pr__pfet_01v8_hvt (12->7)
+sky130_fd_pr__nfet_01v8 (12->7) |sky130_fd_pr__nfet_01v8 (12->7)
+Number of devices: 14 |Number of devices: 14
+Number of nets: 15 |Number of nets: 15
+---------------------------------------------------------------------------------------
+Resolving automorphisms by property value.
+Resolving automorphisms by pin name.
+Netlists match uniquely.
+
+Subcircuit pins:
+Circuit 1: sky130_fd_sc_hd__a211o_4 |Circuit 2: sky130_fd_sc_hd__a211o_4
+-------------------------------------------|-------------------------------------------
+VGND |VGND
+VPB |VPB
+VNB |VNB
+C1 |C1
+A2 |A2
+VPWR |VPWR
+A1 |A1
+B1 |B1
+X |X
+---------------------------------------------------------------------------------------
+Cell pin lists are equivalent.
+Device classes sky130_fd_sc_hd__a211o_4 and sky130_fd_sc_hd__a211o_4 are equivalent.
+
+Class sky130_fd_sc_hd__o2bb2a_2 (0): Merged 2 parallel devices.
+Class sky130_fd_sc_hd__o2bb2a_2 (1): Merged 2 parallel devices.
+Subcircuit summary:
+Circuit 1: sky130_fd_sc_hd__o2bb2a_2 |Circuit 2: sky130_fd_sc_hd__o2bb2a_2
+-------------------------------------------|-------------------------------------------
+sky130_fd_pr__nfet_01v8 (7->6) |sky130_fd_pr__nfet_01v8 (7->6)
+sky130_fd_pr__pfet_01v8_hvt (7->6) |sky130_fd_pr__pfet_01v8_hvt (7->6)
+Number of devices: 12 |Number of devices: 12
+Number of nets: 14 |Number of nets: 14
+---------------------------------------------------------------------------------------
+Netlists match uniquely.
+
+Subcircuit pins:
+Circuit 1: sky130_fd_sc_hd__o2bb2a_2 |Circuit 2: sky130_fd_sc_hd__o2bb2a_2
+-------------------------------------------|-------------------------------------------
+VPWR |VPWR
+VPB |VPB
+VNB |VNB
+VGND |VGND
+A1_N |A1_N
+A2_N |A2_N
+X |X
+B2 |B2
+B1 |B1
+---------------------------------------------------------------------------------------
+Cell pin lists are equivalent.
+Device classes sky130_fd_sc_hd__o2bb2a_2 and sky130_fd_sc_hd__o2bb2a_2 are equivalent.
+
+Class sky130_fd_sc_hd__nand2b_4 (0): Merged 12 parallel devices.
+Class sky130_fd_sc_hd__nand2b_4 (1): Merged 12 parallel devices.
+Subcircuit summary:
+Circuit 1: sky130_fd_sc_hd__nand2b_4 |Circuit 2: sky130_fd_sc_hd__nand2b_4
+-------------------------------------------|-------------------------------------------
+sky130_fd_pr__nfet_01v8 (9->3) |sky130_fd_pr__nfet_01v8 (9->3)
+sky130_fd_pr__pfet_01v8_hvt (9->3) |sky130_fd_pr__pfet_01v8_hvt (9->3)
+Number of devices: 6 |Number of devices: 6
+Number of nets: 9 |Number of nets: 9
+---------------------------------------------------------------------------------------
+Netlists match uniquely.
+
+Subcircuit pins:
+Circuit 1: sky130_fd_sc_hd__nand2b_4 |Circuit 2: sky130_fd_sc_hd__nand2b_4
+-------------------------------------------|-------------------------------------------
+VPWR |VPWR
+Y |Y
+VPB |VPB
+VNB |VNB
+B |B
+VGND |VGND
+A_N |A_N
+---------------------------------------------------------------------------------------
+Cell pin lists are equivalent.
+Device classes sky130_fd_sc_hd__nand2b_4 and sky130_fd_sc_hd__nand2b_4 are equivalent.
+
+Class sky130_fd_sc_hd__o21a_2 (0): Merged 2 parallel devices.
+Class sky130_fd_sc_hd__o21a_2 (1): Merged 2 parallel devices.
+Subcircuit summary:
+Circuit 1: sky130_fd_sc_hd__o21a_2 |Circuit 2: sky130_fd_sc_hd__o21a_2
+-------------------------------------------|-------------------------------------------
+sky130_fd_pr__pfet_01v8_hvt (5->4) |sky130_fd_pr__pfet_01v8_hvt (5->4)
+sky130_fd_pr__nfet_01v8 (5->4) |sky130_fd_pr__nfet_01v8 (5->4)
+Number of devices: 8 |Number of devices: 8
+Number of nets: 11 |Number of nets: 11
+---------------------------------------------------------------------------------------
+Netlists match uniquely.
+
+Subcircuit pins:
+Circuit 1: sky130_fd_sc_hd__o21a_2 |Circuit 2: sky130_fd_sc_hd__o21a_2
+-------------------------------------------|-------------------------------------------
+VNB |VNB
+VPB |VPB
+A2 |A2
+X |X
+A1 |A1
+B1 |B1
+VGND |VGND
+VPWR |VPWR
+---------------------------------------------------------------------------------------
+Cell pin lists are equivalent.
+Device classes sky130_fd_sc_hd__o21a_2 and sky130_fd_sc_hd__o21a_2 are equivalent.
+
+Class sky130_fd_sc_hd__o2111ai_2 (0): Merged 10 parallel devices.
+Class sky130_fd_sc_hd__o2111ai_2 (1): Merged 10 parallel devices.
+Subcircuit summary:
+Circuit 1: sky130_fd_sc_hd__o2111ai_2 |Circuit 2: sky130_fd_sc_hd__o2111ai_2
+-------------------------------------------|-------------------------------------------
+sky130_fd_pr__pfet_01v8_hvt (10->5) |sky130_fd_pr__pfet_01v8_hvt (10->5)
+sky130_fd_pr__nfet_01v8 (10->5) |sky130_fd_pr__nfet_01v8 (10->5)
+Number of devices: 10 |Number of devices: 10
+Number of nets: 14 |Number of nets: 14
+---------------------------------------------------------------------------------------
+Netlists match uniquely.
+
+Subcircuit pins:
+Circuit 1: sky130_fd_sc_hd__o2111ai_2 |Circuit 2: sky130_fd_sc_hd__o2111ai_2
+-------------------------------------------|-------------------------------------------
+VPWR |VPWR
+A2 |A2
+A1 |A1
+B1 |B1
+D1 |D1
+VGND |VGND
+C1 |C1
+Y |Y
+VPB |VPB
+VNB |VNB
+---------------------------------------------------------------------------------------
+Cell pin lists are equivalent.
+Device classes sky130_fd_sc_hd__o2111ai_2 and sky130_fd_sc_hd__o2111ai_2 are equivalent.
+
+Class sky130_fd_sc_hd__a311o_2 (0): Merged 2 parallel devices.
+Class sky130_fd_sc_hd__a311o_2 (1): Merged 2 parallel devices.
+Subcircuit summary:
+Circuit 1: sky130_fd_sc_hd__a311o_2 |Circuit 2: sky130_fd_sc_hd__a311o_2
+-------------------------------------------|-------------------------------------------
+sky130_fd_pr__pfet_01v8_hvt (7->6) |sky130_fd_pr__pfet_01v8_hvt (7->6)
+sky130_fd_pr__nfet_01v8 (7->6) |sky130_fd_pr__nfet_01v8 (7->6)
+Number of devices: 12 |Number of devices: 12
+Number of nets: 15 |Number of nets: 15
+---------------------------------------------------------------------------------------
+Netlists match uniquely.
+
+Subcircuit pins:
+Circuit 1: sky130_fd_sc_hd__a311o_2 |Circuit 2: sky130_fd_sc_hd__a311o_2
+-------------------------------------------|-------------------------------------------
+VPWR |VPWR
+VGND |VGND
+A2 |A2
+B1 |B1
+A3 |A3
+C1 |C1
+X |X
+A1 |A1
+VPB |VPB
+VNB |VNB
+---------------------------------------------------------------------------------------
+Cell pin lists are equivalent.
+Device classes sky130_fd_sc_hd__a311o_2 and sky130_fd_sc_hd__a311o_2 are equivalent.
+
+Subcircuit summary:
+Circuit 1: sky130_fd_sc_hd__a221oi_1 |Circuit 2: sky130_fd_sc_hd__a221oi_1
+-------------------------------------------|-------------------------------------------
+sky130_fd_pr__nfet_01v8 (5) |sky130_fd_pr__nfet_01v8 (5)
+sky130_fd_pr__pfet_01v8_hvt (5) |sky130_fd_pr__pfet_01v8_hvt (5)
+Number of devices: 10 |Number of devices: 10
+Number of nets: 14 |Number of nets: 14
+---------------------------------------------------------------------------------------
+Netlists match uniquely.
+
+Subcircuit pins:
+Circuit 1: sky130_fd_sc_hd__a221oi_1 |Circuit 2: sky130_fd_sc_hd__a221oi_1
+-------------------------------------------|-------------------------------------------
+VGND |VGND
+VNB |VNB
+VPB |VPB
+Y |Y
+B2 |B2
+A2 |A2
+VPWR |VPWR
+A1 |A1
+B1 |B1
+C1 |C1
+---------------------------------------------------------------------------------------
+Cell pin lists are equivalent.
+Device classes sky130_fd_sc_hd__a221oi_1 and sky130_fd_sc_hd__a221oi_1 are equivalent.
+
+Class sky130_fd_sc_hd__o41a_4 (0): Merged 16 parallel devices.
+Class sky130_fd_sc_hd__o41a_4 (1): Merged 16 parallel devices.
+Subcircuit summary:
+Circuit 1: sky130_fd_sc_hd__o41a_4 |Circuit 2: sky130_fd_sc_hd__o41a_4
+-------------------------------------------|-------------------------------------------
+sky130_fd_pr__nfet_01v8 (14->6) |sky130_fd_pr__nfet_01v8 (14->6)
+sky130_fd_pr__pfet_01v8_hvt (14->6) |sky130_fd_pr__pfet_01v8_hvt (14->6)
+Number of devices: 12 |Number of devices: 12
+Number of nets: 15 |Number of nets: 15
+---------------------------------------------------------------------------------------
+Netlists match uniquely.
+
+Subcircuit pins:
+Circuit 1: sky130_fd_sc_hd__o41a_4 |Circuit 2: sky130_fd_sc_hd__o41a_4
+-------------------------------------------|-------------------------------------------
+VPWR |VPWR
+VPB |VPB
+VNB |VNB
+A2 |A2
+A3 |A3
+A4 |A4
+B1 |B1
+X |X
+A1 |A1
+VGND |VGND
+---------------------------------------------------------------------------------------
+Cell pin lists are equivalent.
+Device classes sky130_fd_sc_hd__o41a_4 and sky130_fd_sc_hd__o41a_4 are equivalent.
+
+Class sky130_fd_sc_hd__nand4b_2 (0): Merged 8 parallel devices.
+Class sky130_fd_sc_hd__nand4b_2 (1): Merged 8 parallel devices.
+Subcircuit summary:
+Circuit 1: sky130_fd_sc_hd__nand4b_2 |Circuit 2: sky130_fd_sc_hd__nand4b_2
+-------------------------------------------|-------------------------------------------
+sky130_fd_pr__nfet_01v8 (9->5) |sky130_fd_pr__nfet_01v8 (9->5)
+sky130_fd_pr__pfet_01v8_hvt (9->5) |sky130_fd_pr__pfet_01v8_hvt (9->5)
+Number of devices: 10 |Number of devices: 10
+Number of nets: 13 |Number of nets: 13
+---------------------------------------------------------------------------------------
+Netlists match uniquely.
+
+Subcircuit pins:
+Circuit 1: sky130_fd_sc_hd__nand4b_2 |Circuit 2: sky130_fd_sc_hd__nand4b_2
+-------------------------------------------|-------------------------------------------
+C |C
+D |D
+B |B
+A_N |A_N
+VGND |VGND
+VPWR |VPWR
+Y |Y
+VPB |VPB
+VNB |VNB
+---------------------------------------------------------------------------------------
+Cell pin lists are equivalent.
+Device classes sky130_fd_sc_hd__nand4b_2 and sky130_fd_sc_hd__nand4b_2 are equivalent.
+
+Subcircuit summary:
+Circuit 1: sky130_fd_sc_hd__o2bb2ai_1 |Circuit 2: sky130_fd_sc_hd__o2bb2ai_1
+-------------------------------------------|-------------------------------------------
+sky130_fd_pr__pfet_01v8_hvt (5) |sky130_fd_pr__pfet_01v8_hvt (5)
+sky130_fd_pr__nfet_01v8 (5) |sky130_fd_pr__nfet_01v8 (5)
+Number of devices: 10 |Number of devices: 10
+Number of nets: 13 |Number of nets: 13
+---------------------------------------------------------------------------------------
+Netlists match uniquely.
+
+Subcircuit pins:
+Circuit 1: sky130_fd_sc_hd__o2bb2ai_1 |Circuit 2: sky130_fd_sc_hd__o2bb2ai_1
+-------------------------------------------|-------------------------------------------
+Y |Y
+VGND |VGND
+VPB |VPB
+VNB |VNB
+A2_N |A2_N
+B2 |B2
+B1 |B1
+A1_N |A1_N
+VPWR |VPWR
+---------------------------------------------------------------------------------------
+Cell pin lists are equivalent.
+Device classes sky130_fd_sc_hd__o2bb2ai_1 and sky130_fd_sc_hd__o2bb2ai_1 are equivalent.
+
+Class sky130_fd_sc_hd__o31a_4 (0): Merged 14 parallel devices.
+Class sky130_fd_sc_hd__o31a_4 (1): Merged 14 parallel devices.
+Subcircuit summary:
+Circuit 1: sky130_fd_sc_hd__o31a_4 |Circuit 2: sky130_fd_sc_hd__o31a_4
+-------------------------------------------|-------------------------------------------
+sky130_fd_pr__pfet_01v8_hvt (12->5) |sky130_fd_pr__pfet_01v8_hvt (12->5)
+sky130_fd_pr__nfet_01v8 (12->5) |sky130_fd_pr__nfet_01v8 (12->5)
+Number of devices: 10 |Number of devices: 10
+Number of nets: 13 |Number of nets: 13
+---------------------------------------------------------------------------------------
+Netlists match uniquely.
+
+Subcircuit pins:
+Circuit 1: sky130_fd_sc_hd__o31a_4 |Circuit 2: sky130_fd_sc_hd__o31a_4
+-------------------------------------------|-------------------------------------------
+VGND |VGND
+VPB |VPB
+VNB |VNB
+X |X
+A3 |A3
+A1 |A1
+B1 |B1
+A2 |A2
+VPWR |VPWR
+---------------------------------------------------------------------------------------
+Cell pin lists are equivalent.
+Device classes sky130_fd_sc_hd__o31a_4 and sky130_fd_sc_hd__o31a_4 are equivalent.
+
+Class sky130_fd_sc_hd__xor2_4 (0): Merged 30 parallel devices.
+Class sky130_fd_sc_hd__xor2_4 (1): Merged 30 parallel devices.
+Subcircuit summary:
+Circuit 1: sky130_fd_sc_hd__xor2_4 |Circuit 2: sky130_fd_sc_hd__xor2_4
+-------------------------------------------|-------------------------------------------
+sky130_fd_pr__pfet_01v8_hvt (20->5) |sky130_fd_pr__pfet_01v8_hvt (20->5)
+sky130_fd_pr__nfet_01v8 (20->5) |sky130_fd_pr__nfet_01v8 (20->5)
+Number of devices: 10 |Number of devices: 10
+Number of nets: 11 |Number of nets: 11
+---------------------------------------------------------------------------------------
+Netlists match uniquely.
+
+Subcircuit pins:
+Circuit 1: sky130_fd_sc_hd__xor2_4 |Circuit 2: sky130_fd_sc_hd__xor2_4
+-------------------------------------------|-------------------------------------------
+VPB |VPB
+VNB |VNB
+X |X
+VPWR |VPWR
+A |A
+VGND |VGND
+B |B
+---------------------------------------------------------------------------------------
+Cell pin lists are equivalent.
+Device classes sky130_fd_sc_hd__xor2_4 and sky130_fd_sc_hd__xor2_4 are equivalent.
+
+Class sky130_fd_sc_hd__a2bb2o_2 (0): Merged 2 parallel devices.
+Class sky130_fd_sc_hd__a2bb2o_2 (1): Merged 2 parallel devices.
+Subcircuit summary:
+Circuit 1: sky130_fd_sc_hd__a2bb2o_2 |Circuit 2: sky130_fd_sc_hd__a2bb2o_2
+-------------------------------------------|-------------------------------------------
+sky130_fd_pr__pfet_01v8_hvt (7->6) |sky130_fd_pr__pfet_01v8_hvt (7->6)
+sky130_fd_pr__nfet_01v8 (7->6) |sky130_fd_pr__nfet_01v8 (7->6)
+Number of devices: 12 |Number of devices: 12
+Number of nets: 14 |Number of nets: 14
+---------------------------------------------------------------------------------------
+Netlists match uniquely.
+
+Subcircuit pins:
+Circuit 1: sky130_fd_sc_hd__a2bb2o_2 |Circuit 2: sky130_fd_sc_hd__a2bb2o_2
+-------------------------------------------|-------------------------------------------
+VNB |VNB
+VPB |VPB
+A1_N |A1_N
+X |X
+B1 |B1
+B2 |B2
+A2_N |A2_N
+VGND |VGND
+VPWR |VPWR
+---------------------------------------------------------------------------------------
+Cell pin lists are equivalent.
+Device classes sky130_fd_sc_hd__a2bb2o_2 and sky130_fd_sc_hd__a2bb2o_2 are equivalent.
+
+Class sky130_fd_sc_hd__nor3_4 (0): Merged 18 parallel devices.
+Class sky130_fd_sc_hd__nor3_4 (1): Merged 18 parallel devices.
+Subcircuit summary:
+Circuit 1: sky130_fd_sc_hd__nor3_4 |Circuit 2: sky130_fd_sc_hd__nor3_4
+-------------------------------------------|-------------------------------------------
+sky130_fd_pr__pfet_01v8_hvt (12->3) |sky130_fd_pr__pfet_01v8_hvt (12->3)
+sky130_fd_pr__nfet_01v8 (12->3) |sky130_fd_pr__nfet_01v8 (12->3)
+Number of devices: 6 |Number of devices: 6
+Number of nets: 10 |Number of nets: 10
+---------------------------------------------------------------------------------------
+Netlists match uniquely.
+
+Subcircuit pins:
+Circuit 1: sky130_fd_sc_hd__nor3_4 |Circuit 2: sky130_fd_sc_hd__nor3_4
+-------------------------------------------|-------------------------------------------
+Y |Y
+VPB |VPB
+VGND |VGND
+VNB |VNB
+B |B
+A |A
+C |C
+VPWR |VPWR
+---------------------------------------------------------------------------------------
+Cell pin lists are equivalent.
+Device classes sky130_fd_sc_hd__nor3_4 and sky130_fd_sc_hd__nor3_4 are equivalent.
+
+Class sky130_fd_sc_hd__o211ai_2 (0): Merged 8 parallel devices.
+Class sky130_fd_sc_hd__o211ai_2 (1): Merged 8 parallel devices.
+Subcircuit summary:
+Circuit 1: sky130_fd_sc_hd__o211ai_2 |Circuit 2: sky130_fd_sc_hd__o211ai_2
+-------------------------------------------|-------------------------------------------
+sky130_fd_pr__nfet_01v8 (8->4) |sky130_fd_pr__nfet_01v8 (8->4)
+sky130_fd_pr__pfet_01v8_hvt (8->4) |sky130_fd_pr__pfet_01v8_hvt (8->4)
+Number of devices: 8 |Number of devices: 8
+Number of nets: 12 |Number of nets: 12
+---------------------------------------------------------------------------------------
+Netlists match uniquely.
+
+Subcircuit pins:
+Circuit 1: sky130_fd_sc_hd__o211ai_2 |Circuit 2: sky130_fd_sc_hd__o211ai_2
+-------------------------------------------|-------------------------------------------
+Y |Y
+VPB |VPB
+VNB |VNB
+A2 |A2
+C1 |C1
+A1 |A1
+B1 |B1
+VGND |VGND
+VPWR |VPWR
+---------------------------------------------------------------------------------------
+Cell pin lists are equivalent.
+Device classes sky130_fd_sc_hd__o211ai_2 and sky130_fd_sc_hd__o211ai_2 are equivalent.
+
+Class sky130_fd_sc_hd__o311ai_4 (0): Merged 30 parallel devices.
+Class sky130_fd_sc_hd__o311ai_4 (1): Merged 30 parallel devices.
+Subcircuit summary:
+Circuit 1: sky130_fd_sc_hd__o311ai_4 |Circuit 2: sky130_fd_sc_hd__o311ai_4
+-------------------------------------------|-------------------------------------------
+sky130_fd_pr__pfet_01v8_hvt (20->5) |sky130_fd_pr__pfet_01v8_hvt (20->5)
+sky130_fd_pr__nfet_01v8 (20->5) |sky130_fd_pr__nfet_01v8 (20->5)
+Number of devices: 10 |Number of devices: 10
+Number of nets: 14 |Number of nets: 14
+---------------------------------------------------------------------------------------
+Netlists match uniquely.
+
+Subcircuit pins:
+Circuit 1: sky130_fd_sc_hd__o311ai_4 |Circuit 2: sky130_fd_sc_hd__o311ai_4
+-------------------------------------------|-------------------------------------------
+Y |Y
+VPB |VPB
+VNB |VNB
+VPWR |VPWR
+VGND |VGND
+A1 |A1
+A3 |A3
+A2 |A2
+B1 |B1
+C1 |C1
+---------------------------------------------------------------------------------------
+Cell pin lists are equivalent.
+Device classes sky130_fd_sc_hd__o311ai_4 and sky130_fd_sc_hd__o311ai_4 are equivalent.
+
+Class sky130_fd_sc_hd__o211a_2 (0): Merged 2 parallel devices.
+Class sky130_fd_sc_hd__o211a_2 (1): Merged 2 parallel devices.
+Subcircuit summary:
+Circuit 1: sky130_fd_sc_hd__o211a_2 |Circuit 2: sky130_fd_sc_hd__o211a_2
+-------------------------------------------|-------------------------------------------
+sky130_fd_pr__pfet_01v8_hvt (6->5) |sky130_fd_pr__pfet_01v8_hvt (6->5)
+sky130_fd_pr__nfet_01v8 (6->5) |sky130_fd_pr__nfet_01v8 (6->5)
+Number of devices: 10 |Number of devices: 10
+Number of nets: 13 |Number of nets: 13
+---------------------------------------------------------------------------------------
+Netlists match uniquely.
+
+Subcircuit pins:
+Circuit 1: sky130_fd_sc_hd__o211a_2 |Circuit 2: sky130_fd_sc_hd__o211a_2
+-------------------------------------------|-------------------------------------------
+VGND |VGND
+VPB |VPB
+VNB |VNB
+VPWR |VPWR
+B1 |B1
+C1 |C1
+X |X
+A2 |A2
+A1 |A1
+---------------------------------------------------------------------------------------
+Cell pin lists are equivalent.
+Device classes sky130_fd_sc_hd__o211a_2 and sky130_fd_sc_hd__o211a_2 are equivalent.
+
+Subcircuit summary:
+Circuit 1: sky130_fd_sc_hd__nand3b_1 |Circuit 2: sky130_fd_sc_hd__nand3b_1
+-------------------------------------------|-------------------------------------------
+sky130_fd_pr__pfet_01v8_hvt (4) |sky130_fd_pr__pfet_01v8_hvt (4)
+sky130_fd_pr__nfet_01v8 (4) |sky130_fd_pr__nfet_01v8 (4)
+Number of devices: 8 |Number of devices: 8
+Number of nets: 11 |Number of nets: 11
+---------------------------------------------------------------------------------------
+Netlists match uniquely.
+
+Subcircuit pins:
+Circuit 1: sky130_fd_sc_hd__nand3b_1 |Circuit 2: sky130_fd_sc_hd__nand3b_1
+-------------------------------------------|-------------------------------------------
+A_N |A_N
+VGND |VGND
+B |B
+C |C
+VNB |VNB
+VPWR |VPWR
+VPB |VPB
+Y |Y
+---------------------------------------------------------------------------------------
+Cell pin lists are equivalent.
+Device classes sky130_fd_sc_hd__nand3b_1 and sky130_fd_sc_hd__nand3b_1 are equivalent.
+
+Class sky130_fd_sc_hd__o22a_2 (0): Merged 2 parallel devices.
+Class sky130_fd_sc_hd__o22a_2 (1): Merged 2 parallel devices.
+Subcircuit summary:
+Circuit 1: sky130_fd_sc_hd__o22a_2 |Circuit 2: sky130_fd_sc_hd__o22a_2
+-------------------------------------------|-------------------------------------------
+sky130_fd_pr__nfet_01v8 (6->5) |sky130_fd_pr__nfet_01v8 (6->5)
+sky130_fd_pr__pfet_01v8_hvt (6->5) |sky130_fd_pr__pfet_01v8_hvt (6->5)
+Number of devices: 10 |Number of devices: 10
+Number of nets: 13 |Number of nets: 13
+---------------------------------------------------------------------------------------
+Netlists match uniquely.
+
+Subcircuit pins:
+Circuit 1: sky130_fd_sc_hd__o22a_2 |Circuit 2: sky130_fd_sc_hd__o22a_2
+-------------------------------------------|-------------------------------------------
+VPWR |VPWR
+VGND |VGND
+VPB |VPB
+VNB |VNB
+X |X
+B2 |B2
+B1 |B1
+A2 |A2
+A1 |A1
+---------------------------------------------------------------------------------------
+Cell pin lists are equivalent.
+Device classes sky130_fd_sc_hd__o22a_2 and sky130_fd_sc_hd__o22a_2 are equivalent.
+
+Class sky130_fd_sc_hd__a2bb2oi_4 (0): Merged 30 parallel devices.
+Class sky130_fd_sc_hd__a2bb2oi_4 (1): Merged 30 parallel devices.
+Subcircuit summary:
+Circuit 1: sky130_fd_sc_hd__a2bb2oi_4 |Circuit 2: sky130_fd_sc_hd__a2bb2oi_4
+-------------------------------------------|-------------------------------------------
+sky130_fd_pr__nfet_01v8 (20->5) |sky130_fd_pr__nfet_01v8 (20->5)
+sky130_fd_pr__pfet_01v8_hvt (20->5) |sky130_fd_pr__pfet_01v8_hvt (20->5)
+Number of devices: 10 |Number of devices: 10
+Number of nets: 13 |Number of nets: 13
+---------------------------------------------------------------------------------------
+Netlists match uniquely.
+
+Subcircuit pins:
+Circuit 1: sky130_fd_sc_hd__a2bb2oi_4 |Circuit 2: sky130_fd_sc_hd__a2bb2oi_4
+-------------------------------------------|-------------------------------------------
+VGND |VGND
+VPB |VPB
+VNB |VNB
+A1_N |A1_N
+A2_N |A2_N
+B2 |B2
+B1 |B1
+Y |Y
+VPWR |VPWR
+---------------------------------------------------------------------------------------
+Cell pin lists are equivalent.
+Device classes sky130_fd_sc_hd__a2bb2oi_4 and sky130_fd_sc_hd__a2bb2oi_4 are equivalent.
+
+Class sky130_fd_sc_hd__o21a_4 (0): Merged 10 parallel devices.
+Class sky130_fd_sc_hd__o21a_4 (1): Merged 10 parallel devices.
+Subcircuit summary:
+Circuit 1: sky130_fd_sc_hd__o21a_4 |Circuit 2: sky130_fd_sc_hd__o21a_4
+-------------------------------------------|-------------------------------------------
+sky130_fd_pr__nfet_01v8 (10->4) |sky130_fd_pr__nfet_01v8 (10->4)
+sky130_fd_pr__pfet_01v8_hvt (10->6) |sky130_fd_pr__pfet_01v8_hvt (10->6)
+Number of devices: 10 |Number of devices: 10
+Number of nets: 12 |Number of nets: 12
+---------------------------------------------------------------------------------------
+Resolving automorphisms by property value.
+Resolving automorphisms by pin name.
+Netlists match uniquely.
+
+Subcircuit pins:
+Circuit 1: sky130_fd_sc_hd__o21a_4 |Circuit 2: sky130_fd_sc_hd__o21a_4
+-------------------------------------------|-------------------------------------------
+VNB |VNB
+VPWR |VPWR
+A2 |A2
+VGND |VGND
+A1 |A1
+VPB |VPB
+X |X
+B1 |B1
+---------------------------------------------------------------------------------------
+Cell pin lists are equivalent.
+Device classes sky130_fd_sc_hd__o21a_4 and sky130_fd_sc_hd__o21a_4 are equivalent.
+
+Class sky130_fd_sc_hd__a2bb2oi_2 (0): Merged 10 parallel devices.
+Class sky130_fd_sc_hd__a2bb2oi_2 (1): Merged 10 parallel devices.
+Subcircuit summary:
+Circuit 1: sky130_fd_sc_hd__a2bb2oi_2 |Circuit 2: sky130_fd_sc_hd__a2bb2oi_2
+-------------------------------------------|-------------------------------------------
+sky130_fd_pr__pfet_01v8_hvt (10->5) |sky130_fd_pr__pfet_01v8_hvt (10->5)
+sky130_fd_pr__nfet_01v8 (10->5) |sky130_fd_pr__nfet_01v8 (10->5)
+Number of devices: 10 |Number of devices: 10
+Number of nets: 13 |Number of nets: 13
+---------------------------------------------------------------------------------------
+Netlists match uniquely.
+
+Subcircuit pins:
+Circuit 1: sky130_fd_sc_hd__a2bb2oi_2 |Circuit 2: sky130_fd_sc_hd__a2bb2oi_2
+-------------------------------------------|-------------------------------------------
+VGND |VGND
+VNB |VNB
+VPB |VPB
+B2 |B2
+A2_N |A2_N
+A1_N |A1_N
+B1 |B1
+Y |Y
+VPWR |VPWR
+---------------------------------------------------------------------------------------
+Cell pin lists are equivalent.
+Device classes sky130_fd_sc_hd__a2bb2oi_2 and sky130_fd_sc_hd__a2bb2oi_2 are equivalent.
+
+Class sky130_fd_sc_hd__o311a_2 (0): Merged 2 parallel devices.
+Class sky130_fd_sc_hd__o311a_2 (1): Merged 2 parallel devices.
+Subcircuit summary:
+Circuit 1: sky130_fd_sc_hd__o311a_2 |Circuit 2: sky130_fd_sc_hd__o311a_2
+-------------------------------------------|-------------------------------------------
+sky130_fd_pr__pfet_01v8_hvt (7->6) |sky130_fd_pr__pfet_01v8_hvt (7->6)
+sky130_fd_pr__nfet_01v8 (7->6) |sky130_fd_pr__nfet_01v8 (7->6)
+Number of devices: 12 |Number of devices: 12
+Number of nets: 15 |Number of nets: 15
+---------------------------------------------------------------------------------------
+Netlists match uniquely.
+
+Subcircuit pins:
+Circuit 1: sky130_fd_sc_hd__o311a_2 |Circuit 2: sky130_fd_sc_hd__o311a_2
+-------------------------------------------|-------------------------------------------
+VPWR |VPWR
+VGND |VGND
+VPB |VPB
+VNB |VNB
+X |X
+A2 |A2
+B1 |B1
+A3 |A3
+A1 |A1
+C1 |C1
+---------------------------------------------------------------------------------------
+Cell pin lists are equivalent.
+Device classes sky130_fd_sc_hd__o311a_2 and sky130_fd_sc_hd__o311a_2 are equivalent.
+
+Subcircuit summary:
+Circuit 1: sky130_fd_sc_hd__o221ai_1 |Circuit 2: sky130_fd_sc_hd__o221ai_1
+-------------------------------------------|-------------------------------------------
+sky130_fd_pr__nfet_01v8 (5) |sky130_fd_pr__nfet_01v8 (5)
+sky130_fd_pr__pfet_01v8_hvt (5) |sky130_fd_pr__pfet_01v8_hvt (5)
+Number of devices: 10 |Number of devices: 10
+Number of nets: 14 |Number of nets: 14
+---------------------------------------------------------------------------------------
+Netlists match uniquely.
+
+Subcircuit pins:
+Circuit 1: sky130_fd_sc_hd__o221ai_1 |Circuit 2: sky130_fd_sc_hd__o221ai_1
+-------------------------------------------|-------------------------------------------
+VPB |VPB
+VNB |VNB
+Y |Y
+B1 |B1
+C1 |C1
+VGND |VGND
+A1 |A1
+A2 |A2
+B2 |B2
+VPWR |VPWR
+---------------------------------------------------------------------------------------
+Cell pin lists are equivalent.
+Device classes sky130_fd_sc_hd__o221ai_1 and sky130_fd_sc_hd__o221ai_1 are equivalent.
+
+Class sky130_fd_sc_hd__inv_12 (0): Merged 22 parallel devices.
+Class sky130_fd_sc_hd__inv_12 (1): Merged 22 parallel devices.
+Subcircuit summary:
+Circuit 1: sky130_fd_sc_hd__inv_12 |Circuit 2: sky130_fd_sc_hd__inv_12
+-------------------------------------------|-------------------------------------------
+sky130_fd_pr__pfet_01v8_hvt (12->1) |sky130_fd_pr__pfet_01v8_hvt (12->1)
+sky130_fd_pr__nfet_01v8 (12->1) |sky130_fd_pr__nfet_01v8 (12->1)
+Number of devices: 2 |Number of devices: 2
+Number of nets: 6 |Number of nets: 6
+---------------------------------------------------------------------------------------
+Netlists match uniquely.
+
+Subcircuit pins:
+Circuit 1: sky130_fd_sc_hd__inv_12 |Circuit 2: sky130_fd_sc_hd__inv_12
+-------------------------------------------|-------------------------------------------
+Y |Y
+A |A
+VGND |VGND
+VNB |VNB
+VPWR |VPWR
+VPB |VPB
+---------------------------------------------------------------------------------------
+Cell pin lists are equivalent.
+Device classes sky130_fd_sc_hd__inv_12 and sky130_fd_sc_hd__inv_12 are equivalent.
+
+Class sky130_fd_sc_hd__o211a_4 (0): Merged 10 parallel devices.
+Class sky130_fd_sc_hd__o211a_4 (1): Merged 10 parallel devices.
+Subcircuit summary:
+Circuit 1: sky130_fd_sc_hd__o211a_4 |Circuit 2: sky130_fd_sc_hd__o211a_4
+-------------------------------------------|-------------------------------------------
+sky130_fd_pr__nfet_01v8 (12->7) |sky130_fd_pr__nfet_01v8 (12->7)
+sky130_fd_pr__pfet_01v8_hvt (12->7) |sky130_fd_pr__pfet_01v8_hvt (12->7)
+Number of devices: 14 |Number of devices: 14
+Number of nets: 15 |Number of nets: 15
+---------------------------------------------------------------------------------------
+Resolving automorphisms by property value.
+Resolving automorphisms by pin name.
+Netlists match uniquely.
+
+Subcircuit pins:
+Circuit 1: sky130_fd_sc_hd__o211a_4 |Circuit 2: sky130_fd_sc_hd__o211a_4
+-------------------------------------------|-------------------------------------------
+X |X
+VPWR |VPWR
+VPB |VPB
+VNB |VNB
+B1 |B1
+C1 |C1
+A2 |A2
+VGND |VGND
+A1 |A1
+---------------------------------------------------------------------------------------
+Cell pin lists are equivalent.
+Device classes sky130_fd_sc_hd__o211a_4 and sky130_fd_sc_hd__o211a_4 are equivalent.
+
+Class sky130_fd_sc_hd__o311a_4 (0): Merged 16 parallel devices.
+Class sky130_fd_sc_hd__o311a_4 (1): Merged 16 parallel devices.
+Subcircuit summary:
+Circuit 1: sky130_fd_sc_hd__o311a_4 |Circuit 2: sky130_fd_sc_hd__o311a_4
+-------------------------------------------|-------------------------------------------
+sky130_fd_pr__pfet_01v8_hvt (14->6) |sky130_fd_pr__pfet_01v8_hvt (14->6)
+sky130_fd_pr__nfet_01v8 (14->6) |sky130_fd_pr__nfet_01v8 (14->6)
+Number of devices: 12 |Number of devices: 12
+Number of nets: 15 |Number of nets: 15
+---------------------------------------------------------------------------------------
+Netlists match uniquely.
+
+Subcircuit pins:
+Circuit 1: sky130_fd_sc_hd__o311a_4 |Circuit 2: sky130_fd_sc_hd__o311a_4
+-------------------------------------------|-------------------------------------------
+VPWR |VPWR
+VGND |VGND
+C1 |C1
+B1 |B1
+A1 |A1
+X |X
+A2 |A2
+A3 |A3
+VPB |VPB
+VNB |VNB
+---------------------------------------------------------------------------------------
+Cell pin lists are equivalent.
+Device classes sky130_fd_sc_hd__o311a_4 and sky130_fd_sc_hd__o311a_4 are equivalent.
+
+Class sky130_fd_sc_hd__a41oi_2 (0): Merged 10 parallel devices.
+Class sky130_fd_sc_hd__a41oi_2 (1): Merged 10 parallel devices.
+Subcircuit summary:
+Circuit 1: sky130_fd_sc_hd__a41oi_2 |Circuit 2: sky130_fd_sc_hd__a41oi_2
+-------------------------------------------|-------------------------------------------
+sky130_fd_pr__pfet_01v8_hvt (10->5) |sky130_fd_pr__pfet_01v8_hvt (10->5)
+sky130_fd_pr__nfet_01v8 (10->5) |sky130_fd_pr__nfet_01v8 (10->5)
+Number of devices: 10 |Number of devices: 10
+Number of nets: 14 |Number of nets: 14
+---------------------------------------------------------------------------------------
+Netlists match uniquely.
+
+Subcircuit pins:
+Circuit 1: sky130_fd_sc_hd__a41oi_2 |Circuit 2: sky130_fd_sc_hd__a41oi_2
+-------------------------------------------|-------------------------------------------
+VPWR |VPWR
+Y |Y
+A1 |A1
+B1 |B1
+VGND |VGND
+A3 |A3
+A2 |A2
+A4 |A4
+VNB |VNB
+VPB |VPB
+---------------------------------------------------------------------------------------
+Cell pin lists are equivalent.
+Device classes sky130_fd_sc_hd__a41oi_2 and sky130_fd_sc_hd__a41oi_2 are equivalent.
+
+Class sky130_fd_sc_hd__nand4b_4 (0): Merged 24 parallel devices.
+Class sky130_fd_sc_hd__nand4b_4 (1): Merged 24 parallel devices.
+Subcircuit summary:
+Circuit 1: sky130_fd_sc_hd__nand4b_4 |Circuit 2: sky130_fd_sc_hd__nand4b_4
+-------------------------------------------|-------------------------------------------
+sky130_fd_pr__nfet_01v8 (17->5) |sky130_fd_pr__nfet_01v8 (17->5)
+sky130_fd_pr__pfet_01v8_hvt (17->5) |sky130_fd_pr__pfet_01v8_hvt (17->5)
+Number of devices: 10 |Number of devices: 10
+Number of nets: 13 |Number of nets: 13
+---------------------------------------------------------------------------------------
+Netlists match uniquely.
+
+Subcircuit pins:
+Circuit 1: sky130_fd_sc_hd__nand4b_4 |Circuit 2: sky130_fd_sc_hd__nand4b_4
+-------------------------------------------|-------------------------------------------
+VNB |VNB
+VPWR |VPWR
+Y |Y
+VPB |VPB
+VGND |VGND
+D |D
+B |B
+C |C
+A_N |A_N
+---------------------------------------------------------------------------------------
+Cell pin lists are equivalent.
+Device classes sky130_fd_sc_hd__nand4b_4 and sky130_fd_sc_hd__nand4b_4 are equivalent.
+
+Class sky130_fd_sc_hd__xor2_2 (0): Merged 10 parallel devices.
+Class sky130_fd_sc_hd__xor2_2 (1): Merged 10 parallel devices.
+Subcircuit summary:
+Circuit 1: sky130_fd_sc_hd__xor2_2 |Circuit 2: sky130_fd_sc_hd__xor2_2
+-------------------------------------------|-------------------------------------------
+sky130_fd_pr__pfet_01v8_hvt (10->5) |sky130_fd_pr__pfet_01v8_hvt (10->5)
+sky130_fd_pr__nfet_01v8 (10->5) |sky130_fd_pr__nfet_01v8 (10->5)
+Number of devices: 10 |Number of devices: 10
+Number of nets: 11 |Number of nets: 11
+---------------------------------------------------------------------------------------
+Netlists match uniquely.
+
+Subcircuit pins:
+Circuit 1: sky130_fd_sc_hd__xor2_2 |Circuit 2: sky130_fd_sc_hd__xor2_2
+-------------------------------------------|-------------------------------------------
+VPB |VPB
+VNB |VNB
+VPWR |VPWR
+X |X
+A |A
+B |B
+VGND |VGND
+---------------------------------------------------------------------------------------
+Cell pin lists are equivalent.
+Device classes sky130_fd_sc_hd__xor2_2 and sky130_fd_sc_hd__xor2_2 are equivalent.
+
+Class sky130_fd_sc_hd__a2111o_4 (0): Merged 16 parallel devices.
+Class sky130_fd_sc_hd__a2111o_4 (1): Merged 16 parallel devices.
+Subcircuit summary:
+Circuit 1: sky130_fd_sc_hd__a2111o_4 |Circuit 2: sky130_fd_sc_hd__a2111o_4
+-------------------------------------------|-------------------------------------------
+sky130_fd_pr__pfet_01v8_hvt (14->6) |sky130_fd_pr__pfet_01v8_hvt (14->6)
+sky130_fd_pr__nfet_01v8 (14->6) |sky130_fd_pr__nfet_01v8 (14->6)
+Number of devices: 12 |Number of devices: 12
+Number of nets: 15 |Number of nets: 15
+---------------------------------------------------------------------------------------
+Netlists match uniquely.
+
+Subcircuit pins:
+Circuit 1: sky130_fd_sc_hd__a2111o_4 |Circuit 2: sky130_fd_sc_hd__a2111o_4
+-------------------------------------------|-------------------------------------------
+VPWR |VPWR
+VGND |VGND
+VPB |VPB
+VNB |VNB
+B1 |B1
+A1 |A1
+X |X
+D1 |D1
+C1 |C1
+A2 |A2
+---------------------------------------------------------------------------------------
+Cell pin lists are equivalent.
+Device classes sky130_fd_sc_hd__a2111o_4 and sky130_fd_sc_hd__a2111o_4 are equivalent.
+
+Class sky130_fd_sc_hd__o41a_2 (0): Merged 2 parallel devices.
+Class sky130_fd_sc_hd__o41a_2 (1): Merged 2 parallel devices.
+Subcircuit summary:
+Circuit 1: sky130_fd_sc_hd__o41a_2 |Circuit 2: sky130_fd_sc_hd__o41a_2
+-------------------------------------------|-------------------------------------------
+sky130_fd_pr__nfet_01v8 (7->6) |sky130_fd_pr__nfet_01v8 (7->6)
+sky130_fd_pr__pfet_01v8_hvt (7->6) |sky130_fd_pr__pfet_01v8_hvt (7->6)
+Number of devices: 12 |Number of devices: 12
+Number of nets: 15 |Number of nets: 15
+---------------------------------------------------------------------------------------
+Netlists match uniquely.
+
+Subcircuit pins:
+Circuit 1: sky130_fd_sc_hd__o41a_2 |Circuit 2: sky130_fd_sc_hd__o41a_2
+-------------------------------------------|-------------------------------------------
+VPWR |VPWR
+VPB |VPB
+VNB |VNB
+B1 |B1
+A3 |A3
+A2 |A2
+A1 |A1
+A4 |A4
+X |X
+VGND |VGND
+---------------------------------------------------------------------------------------
+Cell pin lists are equivalent.
+Device classes sky130_fd_sc_hd__o41a_2 and sky130_fd_sc_hd__o41a_2 are equivalent.
+
+Class sky130_fd_sc_hd__o221a_2 (0): Merged 2 parallel devices.
+Class sky130_fd_sc_hd__o221a_2 (1): Merged 2 parallel devices.
+Subcircuit summary:
+Circuit 1: sky130_fd_sc_hd__o221a_2 |Circuit 2: sky130_fd_sc_hd__o221a_2
+-------------------------------------------|-------------------------------------------
+sky130_fd_pr__pfet_01v8_hvt (7->6) |sky130_fd_pr__pfet_01v8_hvt (7->6)
+sky130_fd_pr__nfet_01v8 (7->6) |sky130_fd_pr__nfet_01v8 (7->6)
+Number of devices: 12 |Number of devices: 12
+Number of nets: 15 |Number of nets: 15
+---------------------------------------------------------------------------------------
+Netlists match uniquely.
+
+Subcircuit pins:
+Circuit 1: sky130_fd_sc_hd__o221a_2 |Circuit 2: sky130_fd_sc_hd__o221a_2
+-------------------------------------------|-------------------------------------------
+VGND |VGND
+X |X
+C1 |C1
+A2 |A2
+B2 |B2
+B1 |B1
+A1 |A1
+VNB |VNB
+VPB |VPB
+VPWR |VPWR
+---------------------------------------------------------------------------------------
+Cell pin lists are equivalent.
+Device classes sky130_fd_sc_hd__o221a_2 and sky130_fd_sc_hd__o221a_2 are equivalent.
+
+Subcircuit summary:
+Circuit 1: sky130_fd_sc_hd__a2bb2oi_1 |Circuit 2: sky130_fd_sc_hd__a2bb2oi_1
+-------------------------------------------|-------------------------------------------
+sky130_fd_pr__pfet_01v8_hvt (5) |sky130_fd_pr__pfet_01v8_hvt (5)
+sky130_fd_pr__nfet_01v8 (5) |sky130_fd_pr__nfet_01v8 (5)
+Number of devices: 10 |Number of devices: 10
+Number of nets: 13 |Number of nets: 13
+---------------------------------------------------------------------------------------
+Netlists match uniquely.
+
+Subcircuit pins:
+Circuit 1: sky130_fd_sc_hd__a2bb2oi_1 |Circuit 2: sky130_fd_sc_hd__a2bb2oi_1
+-------------------------------------------|-------------------------------------------
+VGND |VGND
+Y |Y
+VPWR |VPWR
+A2_N |A2_N
+B1 |B1
+B2 |B2
+A1_N |A1_N
+VPB |VPB
+VNB |VNB
+---------------------------------------------------------------------------------------
+Cell pin lists are equivalent.
+Device classes sky130_fd_sc_hd__a2bb2oi_1 and sky130_fd_sc_hd__a2bb2oi_1 are equivalent.
+
+Class sky130_fd_sc_hd__nor4b_4 (0): Merged 24 parallel devices.
+Class sky130_fd_sc_hd__nor4b_4 (1): Merged 24 parallel devices.
+Subcircuit summary:
+Circuit 1: sky130_fd_sc_hd__nor4b_4 |Circuit 2: sky130_fd_sc_hd__nor4b_4
+-------------------------------------------|-------------------------------------------
+sky130_fd_pr__nfet_01v8 (17->5) |sky130_fd_pr__nfet_01v8 (17->5)
+sky130_fd_pr__pfet_01v8_hvt (17->5) |sky130_fd_pr__pfet_01v8_hvt (17->5)
+Number of devices: 10 |Number of devices: 10
+Number of nets: 13 |Number of nets: 13
+---------------------------------------------------------------------------------------
+Netlists match uniquely.
+
+Subcircuit pins:
+Circuit 1: sky130_fd_sc_hd__nor4b_4 |Circuit 2: sky130_fd_sc_hd__nor4b_4
+-------------------------------------------|-------------------------------------------
+C |C
+A |A
+B |B
+D_N |D_N
+VPWR |VPWR
+Y |Y
+VPB |VPB
+VGND |VGND
+VNB |VNB
+---------------------------------------------------------------------------------------
+Cell pin lists are equivalent.
+Device classes sky130_fd_sc_hd__nor4b_4 and sky130_fd_sc_hd__nor4b_4 are equivalent.
+
+Subcircuit summary:
+Circuit 1: sky130_fd_sc_hd__o32ai_1 |Circuit 2: sky130_fd_sc_hd__o32ai_1
+-------------------------------------------|-------------------------------------------
+sky130_fd_pr__nfet_01v8 (5) |sky130_fd_pr__nfet_01v8 (5)
+sky130_fd_pr__pfet_01v8_hvt (5) |sky130_fd_pr__pfet_01v8_hvt (5)
+Number of devices: 10 |Number of devices: 10
+Number of nets: 14 |Number of nets: 14
+---------------------------------------------------------------------------------------
+Netlists match uniquely.
+
+Subcircuit pins:
+Circuit 1: sky130_fd_sc_hd__o32ai_1 |Circuit 2: sky130_fd_sc_hd__o32ai_1
+-------------------------------------------|-------------------------------------------
+Y |Y
+VPB |VPB
+VNB |VNB
+B2 |B2
+VPWR |VPWR
+A1 |A1
+A2 |A2
+A3 |A3
+B1 |B1
+VGND |VGND
+---------------------------------------------------------------------------------------
+Cell pin lists are equivalent.
+Device classes sky130_fd_sc_hd__o32ai_1 and sky130_fd_sc_hd__o32ai_1 are equivalent.
+
+Class sky130_fd_sc_hd__inv_8 (0): Merged 14 parallel devices.
+Class sky130_fd_sc_hd__inv_8 (1): Merged 14 parallel devices.
+Subcircuit summary:
+Circuit 1: sky130_fd_sc_hd__inv_8 |Circuit 2: sky130_fd_sc_hd__inv_8
+-------------------------------------------|-------------------------------------------
+sky130_fd_pr__pfet_01v8_hvt (8->1) |sky130_fd_pr__pfet_01v8_hvt (8->1)
+sky130_fd_pr__nfet_01v8 (8->1) |sky130_fd_pr__nfet_01v8 (8->1)
+Number of devices: 2 |Number of devices: 2
+Number of nets: 6 |Number of nets: 6
+---------------------------------------------------------------------------------------
+Netlists match uniquely.
+
+Subcircuit pins:
+Circuit 1: sky130_fd_sc_hd__inv_8 |Circuit 2: sky130_fd_sc_hd__inv_8
+-------------------------------------------|-------------------------------------------
+A |A
+Y |Y
+VGND |VGND
+VNB |VNB
+VPWR |VPWR
+VPB |VPB
+---------------------------------------------------------------------------------------
+Cell pin lists are equivalent.
+Device classes sky130_fd_sc_hd__inv_8 and sky130_fd_sc_hd__inv_8 are equivalent.
+
+Class sky130_fd_sc_hd__nand3b_4 (0): Merged 18 parallel devices.
+Class sky130_fd_sc_hd__nand3b_4 (1): Merged 18 parallel devices.
+Subcircuit summary:
+Circuit 1: sky130_fd_sc_hd__nand3b_4 |Circuit 2: sky130_fd_sc_hd__nand3b_4
+-------------------------------------------|-------------------------------------------
+sky130_fd_pr__nfet_01v8 (13->4) |sky130_fd_pr__nfet_01v8 (13->4)
+sky130_fd_pr__pfet_01v8_hvt (13->4) |sky130_fd_pr__pfet_01v8_hvt (13->4)
+Number of devices: 8 |Number of devices: 8
+Number of nets: 11 |Number of nets: 11
+---------------------------------------------------------------------------------------
+Netlists match uniquely.
+
+Subcircuit pins:
+Circuit 1: sky130_fd_sc_hd__nand3b_4 |Circuit 2: sky130_fd_sc_hd__nand3b_4
+-------------------------------------------|-------------------------------------------
+VNB |VNB
+VPWR |VPWR
+Y |Y
+VPB |VPB
+B |B
+C |C
+VGND |VGND
+A_N |A_N
+---------------------------------------------------------------------------------------
+Cell pin lists are equivalent.
+Device classes sky130_fd_sc_hd__nand3b_4 and sky130_fd_sc_hd__nand3b_4 are equivalent.
+
+Class sky130_fd_sc_hd__nor3b_4 (0): Merged 18 parallel devices.
+Class sky130_fd_sc_hd__nor3b_4 (1): Merged 18 parallel devices.
+Subcircuit summary:
+Circuit 1: sky130_fd_sc_hd__nor3b_4 |Circuit 2: sky130_fd_sc_hd__nor3b_4
+-------------------------------------------|-------------------------------------------
+sky130_fd_pr__nfet_01v8 (13->4) |sky130_fd_pr__nfet_01v8 (13->4)
+sky130_fd_pr__pfet_01v8_hvt (13->4) |sky130_fd_pr__pfet_01v8_hvt (13->4)
+Number of devices: 8 |Number of devices: 8
+Number of nets: 11 |Number of nets: 11
+---------------------------------------------------------------------------------------
+Netlists match uniquely.
+
+Subcircuit pins:
+Circuit 1: sky130_fd_sc_hd__nor3b_4 |Circuit 2: sky130_fd_sc_hd__nor3b_4
+-------------------------------------------|-------------------------------------------
+VPWR |VPWR
+A |A
+B |B
+C_N |C_N
+VPB |VPB
+VGND |VGND
+Y |Y
+VNB |VNB
+---------------------------------------------------------------------------------------
+Cell pin lists are equivalent.
+Device classes sky130_fd_sc_hd__nor3b_4 and sky130_fd_sc_hd__nor3b_4 are equivalent.
+
+Class RAM128 (0): Merged 1013 parallel devices.
+Class RAM128 (1): Merged 1013 parallel devices.
+Subcircuit summary:
+Circuit 1: RAM128 |Circuit 2: RAM128
+-------------------------------------------|-------------------------------------------
+sky130_fd_sc_hd__ebufn_2 (4224) |sky130_fd_sc_hd__ebufn_2 (4224)
+sky130_fd_sc_hd__dlclkp_1 (512) |sky130_fd_sc_hd__dlclkp_1 (512)
+sky130_fd_sc_hd__clkbuf_4 (153) |sky130_fd_sc_hd__clkbuf_4 (153)
+sky130_fd_sc_hd__dlxtp_1 (4096) |sky130_fd_sc_hd__dlxtp_1 (4096)
+sky130_fd_sc_hd__and4bb_2 (48) |sky130_fd_sc_hd__and4bb_2 (48)
+sky130_fd_sc_hd__inv_1 (1024) |sky130_fd_sc_hd__inv_1 (1024)
+sky130_fd_sc_hd__dfxtp_1 (128) |sky130_fd_sc_hd__dfxtp_1 (128)
+sky130_fd_sc_hd__and2_1 (512) |sky130_fd_sc_hd__and2_1 (512)
+sky130_fd_sc_hd__diode_2 (770->386) |sky130_fd_sc_hd__diode_2 (770->386)
+sky130_fd_sc_hd__decap_12 (475->1) |sky130_fd_sc_hd__decap_12 (475->1)
+sky130_fd_sc_hd__decap_8 (55->1) |sky130_fd_sc_hd__decap_8 (55->1)
+sky130_fd_sc_hd__clkbuf_2 (348) |sky130_fd_sc_hd__clkbuf_2 (348)
+sky130_fd_sc_hd__clkbuf_16 (160) |sky130_fd_sc_hd__clkbuf_16 (160)
+sky130_fd_sc_hd__decap_4 (30->1) |sky130_fd_sc_hd__decap_4 (30->1)
+sky130_fd_sc_hd__decap_6 (12->1) |sky130_fd_sc_hd__decap_6 (12->1)
+sky130_fd_sc_hd__decap_3 (62->1) |sky130_fd_sc_hd__decap_3 (62->1)
+sky130_fd_sc_hd__and4b_2 (48) |sky130_fd_sc_hd__and4b_2 (48)
+sky130_fd_sc_hd__mux4_1 (32) |sky130_fd_sc_hd__mux4_1 (32)
+sky130_fd_sc_hd__conb_1 (16) |sky130_fd_sc_hd__conb_1 (16)
+sky130_fd_sc_hd__and4_2 (16) |sky130_fd_sc_hd__and4_2 (16)
+sky130_fd_sc_hd__nor4b_2 (16) |sky130_fd_sc_hd__nor4b_2 (16)
+sky130_fd_sc_hd__nor3b_2 (5) |sky130_fd_sc_hd__nor3b_2 (5)
+sky130_fd_sc_hd__and3b_2 (10) |sky130_fd_sc_hd__and3b_2 (10)
+sky130_fd_sc_hd__and3_2 (5) |sky130_fd_sc_hd__and3_2 (5)
+Number of devices: 11744 |Number of devices: 11744
+Number of nets: 7320 |Number of nets: 7320
+---------------------------------------------------------------------------------------
+Resolving automorphisms by property value.
+Resolving automorphisms by pin name.
+Netlists match uniquely.
+
+Subcircuit pins:
+Circuit 1: RAM128 |Circuit 2: RAM128
+-------------------------------------------|-------------------------------------------
+A0[5] |A0[5]
+A0[6] |A0[6]
+CLK |CLK
+Di0[0] |Di0[0]
+Di0[10] |Di0[10]
+Di0[11] |Di0[11]
+Di0[12] |Di0[12]
+Di0[13] |Di0[13]
+Di0[14] |Di0[14]
+Di0[15] |Di0[15]
+Di0[16] |Di0[16]
+Di0[17] |Di0[17]
+Di0[18] |Di0[18]
+Di0[19] |Di0[19]
+Di0[1] |Di0[1]
+Di0[20] |Di0[20]
+Di0[21] |Di0[21]
+Di0[22] |Di0[22]
+Di0[23] |Di0[23]
+Di0[24] |Di0[24]
+Di0[25] |Di0[25]
+Di0[26] |Di0[26]
+Di0[27] |Di0[27]
+Di0[28] |Di0[28]
+Di0[29] |Di0[29]
+Di0[2] |Di0[2]
+Di0[30] |Di0[30]
+Di0[31] |Di0[31]
+Di0[3] |Di0[3]
+Di0[4] |Di0[4]
+Di0[5] |Di0[5]
+Di0[6] |Di0[6]
+Di0[7] |Di0[7]
+Di0[8] |Di0[8]
+Di0[9] |Di0[9]
+Do0[0] |Do0[0]
+Do0[1] |Do0[1]
+Do0[2] |Do0[2]
+Do0[3] |Do0[3]
+Do0[4] |Do0[4]
+Do0[5] |Do0[5]
+Do0[6] |Do0[6]
+Do0[7] |Do0[7]
+Do0[8] |Do0[8]
+Do0[9] |Do0[9]
+Do0[10] |Do0[10]
+Do0[11] |Do0[11]
+Do0[12] |Do0[12]
+Do0[13] |Do0[13]
+Do0[14] |Do0[14]
+Do0[15] |Do0[15]
+Do0[16] |Do0[16]
+Do0[17] |Do0[17]
+Do0[18] |Do0[18]
+Do0[19] |Do0[19]
+Do0[20] |Do0[20]
+Do0[21] |Do0[21]
+Do0[22] |Do0[22]
+Do0[23] |Do0[23]
+Do0[24] |Do0[24]
+Do0[25] |Do0[25]
+Do0[26] |Do0[26]
+Do0[27] |Do0[27]
+Do0[28] |Do0[28]
+Do0[29] |Do0[29]
+Do0[30] |Do0[30]
+Do0[31] |Do0[31]
+EN0 |EN0
+A0[3] |A0[3]
+A0[4] |A0[4]
+A0[0] |A0[0]
+A0[1] |A0[1]
+A0[2] |A0[2]
+WE0[0] |WE0[0]
+WE0[1] |WE0[1]
+WE0[2] |WE0[2]
+WE0[3] |WE0[3]
+VGND |VGND
+VPWR |VPWR
+---------------------------------------------------------------------------------------
+Cell pin lists are equivalent.
+Device classes RAM128 and RAM128 are equivalent.
+
+Class sky130_fd_sc_hd__nand3_4 (0): Merged 18 parallel devices.
+Class sky130_fd_sc_hd__nand3_4 (1): Merged 18 parallel devices.
+Subcircuit summary:
+Circuit 1: sky130_fd_sc_hd__nand3_4 |Circuit 2: sky130_fd_sc_hd__nand3_4
+-------------------------------------------|-------------------------------------------
+sky130_fd_pr__nfet_01v8 (12->3) |sky130_fd_pr__nfet_01v8 (12->3)
+sky130_fd_pr__pfet_01v8_hvt (12->3) |sky130_fd_pr__pfet_01v8_hvt (12->3)
+Number of devices: 6 |Number of devices: 6
+Number of nets: 10 |Number of nets: 10
+---------------------------------------------------------------------------------------
+Netlists match uniquely.
+
+Subcircuit pins:
+Circuit 1: sky130_fd_sc_hd__nand3_4 |Circuit 2: sky130_fd_sc_hd__nand3_4
+-------------------------------------------|-------------------------------------------
+VGND |VGND
+Y |Y
+VNB |VNB
+VPWR |VPWR
+VPB |VPB
+A |A
+B |B
+C |C
+---------------------------------------------------------------------------------------
+Cell pin lists are equivalent.
+Device classes sky130_fd_sc_hd__nand3_4 and sky130_fd_sc_hd__nand3_4 are equivalent.
+
+Class sky130_fd_sc_hd__xnor2_4 (0): Merged 30 parallel devices.
+Class sky130_fd_sc_hd__xnor2_4 (1): Merged 30 parallel devices.
+Subcircuit summary:
+Circuit 1: sky130_fd_sc_hd__xnor2_4 |Circuit 2: sky130_fd_sc_hd__xnor2_4
+-------------------------------------------|-------------------------------------------
+sky130_fd_pr__nfet_01v8 (20->5) |sky130_fd_pr__nfet_01v8 (20->5)
+sky130_fd_pr__pfet_01v8_hvt (20->5) |sky130_fd_pr__pfet_01v8_hvt (20->5)
+Number of devices: 10 |Number of devices: 10
+Number of nets: 11 |Number of nets: 11
+---------------------------------------------------------------------------------------
+Netlists match uniquely.
+
+Subcircuit pins:
+Circuit 1: sky130_fd_sc_hd__xnor2_4 |Circuit 2: sky130_fd_sc_hd__xnor2_4
+-------------------------------------------|-------------------------------------------
+VNB |VNB
+VPB |VPB
+A |A
+B |B
+VPWR |VPWR
+VGND |VGND
+Y |Y
+---------------------------------------------------------------------------------------
+Cell pin lists are equivalent.
+Device classes sky130_fd_sc_hd__xnor2_4 and sky130_fd_sc_hd__xnor2_4 are equivalent.
+
+Class sky130_fd_sc_hd__a2111oi_4 (0): Merged 30 parallel devices.
+Class sky130_fd_sc_hd__a2111oi_4 (1): Merged 30 parallel devices.
+Subcircuit summary:
+Circuit 1: sky130_fd_sc_hd__a2111oi_4 |Circuit 2: sky130_fd_sc_hd__a2111oi_4
+-------------------------------------------|-------------------------------------------
+sky130_fd_pr__nfet_01v8 (20->5) |sky130_fd_pr__nfet_01v8 (20->5)
+sky130_fd_pr__pfet_01v8_hvt (20->5) |sky130_fd_pr__pfet_01v8_hvt (20->5)
+Number of devices: 10 |Number of devices: 10
+Number of nets: 14 |Number of nets: 14
+---------------------------------------------------------------------------------------
+Netlists match uniquely.
+
+Subcircuit pins:
+Circuit 1: sky130_fd_sc_hd__a2111oi_4 |Circuit 2: sky130_fd_sc_hd__a2111oi_4
+-------------------------------------------|-------------------------------------------
+VGND |VGND
+VPWR |VPWR
+A1 |A1
+A2 |A2
+C1 |C1
+D1 |D1
+B1 |B1
+VPB |VPB
+Y |Y
+VNB |VNB
+---------------------------------------------------------------------------------------
+Cell pin lists are equivalent.
+Device classes sky130_fd_sc_hd__a2111oi_4 and sky130_fd_sc_hd__a2111oi_4 are equivalent.
+
+Class sky130_fd_sc_hd__a311o_4 (0): Merged 16 parallel devices.
+Class sky130_fd_sc_hd__a311o_4 (1): Merged 16 parallel devices.
+Subcircuit summary:
+Circuit 1: sky130_fd_sc_hd__a311o_4 |Circuit 2: sky130_fd_sc_hd__a311o_4
+-------------------------------------------|-------------------------------------------
+sky130_fd_pr__pfet_01v8_hvt (14->6) |sky130_fd_pr__pfet_01v8_hvt (14->6)
+sky130_fd_pr__nfet_01v8 (14->6) |sky130_fd_pr__nfet_01v8 (14->6)
+Number of devices: 12 |Number of devices: 12
+Number of nets: 15 |Number of nets: 15
+---------------------------------------------------------------------------------------
+Netlists match uniquely.
+
+Subcircuit pins:
+Circuit 1: sky130_fd_sc_hd__a311o_4 |Circuit 2: sky130_fd_sc_hd__a311o_4
+-------------------------------------------|-------------------------------------------
+X |X
+A1 |A1
+B1 |B1
+A2 |A2
+A3 |A3
+C1 |C1
+VNB |VNB
+VPB |VPB
+VGND |VGND
+VPWR |VPWR
+---------------------------------------------------------------------------------------
+Cell pin lists are equivalent.
+Device classes sky130_fd_sc_hd__a311o_4 and sky130_fd_sc_hd__a311o_4 are equivalent.
+
+Class sky130_fd_sc_hd__a221oi_2 (0): Merged 10 parallel devices.
+Class sky130_fd_sc_hd__a221oi_2 (1): Merged 10 parallel devices.
+Subcircuit summary:
+Circuit 1: sky130_fd_sc_hd__a221oi_2 |Circuit 2: sky130_fd_sc_hd__a221oi_2
+-------------------------------------------|-------------------------------------------
+sky130_fd_pr__nfet_01v8 (10->5) |sky130_fd_pr__nfet_01v8 (10->5)
+sky130_fd_pr__pfet_01v8_hvt (10->5) |sky130_fd_pr__pfet_01v8_hvt (10->5)
+Number of devices: 10 |Number of devices: 10
+Number of nets: 14 |Number of nets: 14
+---------------------------------------------------------------------------------------
+Netlists match uniquely.
+
+Subcircuit pins:
+Circuit 1: sky130_fd_sc_hd__a221oi_2 |Circuit 2: sky130_fd_sc_hd__a221oi_2
+-------------------------------------------|-------------------------------------------
+VGND |VGND
+VPB |VPB
+VNB |VNB
+VPWR |VPWR
+A1 |A1
+B1 |B1
+A2 |A2
+C1 |C1
+B2 |B2
+Y |Y
+---------------------------------------------------------------------------------------
+Cell pin lists are equivalent.
+Device classes sky130_fd_sc_hd__a221oi_2 and sky130_fd_sc_hd__a221oi_2 are equivalent.
+
+Class sky130_fd_sc_hd__o22ai_2 (0): Merged 8 parallel devices.
+Class sky130_fd_sc_hd__o22ai_2 (1): Merged 8 parallel devices.
+Subcircuit summary:
+Circuit 1: sky130_fd_sc_hd__o22ai_2 |Circuit 2: sky130_fd_sc_hd__o22ai_2
+-------------------------------------------|-------------------------------------------
+sky130_fd_pr__pfet_01v8_hvt (8->4) |sky130_fd_pr__pfet_01v8_hvt (8->4)
+sky130_fd_pr__nfet_01v8 (8->4) |sky130_fd_pr__nfet_01v8 (8->4)
+Number of devices: 8 |Number of devices: 8
+Number of nets: 12 |Number of nets: 12
+---------------------------------------------------------------------------------------
+Netlists match uniquely.
+
+Subcircuit pins:
+Circuit 1: sky130_fd_sc_hd__o22ai_2 |Circuit 2: sky130_fd_sc_hd__o22ai_2
+-------------------------------------------|-------------------------------------------
+B2 |B2
+VPWR |VPWR
+B1 |B1
+A2 |A2
+VGND |VGND
+A1 |A1
+Y |Y
+VNB |VNB
+VPB |VPB
+---------------------------------------------------------------------------------------
+Cell pin lists are equivalent.
+Device classes sky130_fd_sc_hd__o22ai_2 and sky130_fd_sc_hd__o22ai_2 are equivalent.
+
+Class sky130_fd_sc_hd__a31oi_2 (0): Merged 8 parallel devices.
+Class sky130_fd_sc_hd__a31oi_2 (1): Merged 8 parallel devices.
+Subcircuit summary:
+Circuit 1: sky130_fd_sc_hd__a31oi_2 |Circuit 2: sky130_fd_sc_hd__a31oi_2
+-------------------------------------------|-------------------------------------------
+sky130_fd_pr__nfet_01v8 (8->4) |sky130_fd_pr__nfet_01v8 (8->4)
+sky130_fd_pr__pfet_01v8_hvt (8->4) |sky130_fd_pr__pfet_01v8_hvt (8->4)
+Number of devices: 8 |Number of devices: 8
+Number of nets: 12 |Number of nets: 12
+---------------------------------------------------------------------------------------
+Netlists match uniquely.
+
+Subcircuit pins:
+Circuit 1: sky130_fd_sc_hd__a31oi_2 |Circuit 2: sky130_fd_sc_hd__a31oi_2
+-------------------------------------------|-------------------------------------------
+VNB |VNB
+VPB |VPB
+Y |Y
+VPWR |VPWR
+VGND |VGND
+A1 |A1
+B1 |B1
+A3 |A3
+A2 |A2
+---------------------------------------------------------------------------------------
+Cell pin lists are equivalent.
+Device classes sky130_fd_sc_hd__a31oi_2 and sky130_fd_sc_hd__a31oi_2 are equivalent.
+
+Class sky130_fd_sc_hd__o2111a_2 (0): Merged 2 parallel devices.
+Class sky130_fd_sc_hd__o2111a_2 (1): Merged 2 parallel devices.
+Subcircuit summary:
+Circuit 1: sky130_fd_sc_hd__o2111a_2 |Circuit 2: sky130_fd_sc_hd__o2111a_2
+-------------------------------------------|-------------------------------------------
+sky130_fd_pr__pfet_01v8_hvt (7->6) |sky130_fd_pr__pfet_01v8_hvt (7->6)
+sky130_fd_pr__nfet_01v8 (7->6) |sky130_fd_pr__nfet_01v8 (7->6)
+Number of devices: 12 |Number of devices: 12
+Number of nets: 15 |Number of nets: 15
+---------------------------------------------------------------------------------------
+Netlists match uniquely.
+
+Subcircuit pins:
+Circuit 1: sky130_fd_sc_hd__o2111a_2 |Circuit 2: sky130_fd_sc_hd__o2111a_2
+-------------------------------------------|-------------------------------------------
+VGND |VGND
+VNB |VNB
+VPB |VPB
+C1 |C1
+X |X
+B1 |B1
+A2 |A2
+A1 |A1
+D1 |D1
+VPWR |VPWR
+---------------------------------------------------------------------------------------
+Cell pin lists are equivalent.
+Device classes sky130_fd_sc_hd__o2111a_2 and sky130_fd_sc_hd__o2111a_2 are equivalent.
+
+Class sky130_fd_sc_hd__clkinv_8 (0): Merged 18 parallel devices.
+Class sky130_fd_sc_hd__clkinv_8 (1): Merged 18 parallel devices.
+Subcircuit summary:
+Circuit 1: sky130_fd_sc_hd__clkinv_8 |Circuit 2: sky130_fd_sc_hd__clkinv_8
+-------------------------------------------|-------------------------------------------
+sky130_fd_pr__nfet_01v8 (8->1) |sky130_fd_pr__nfet_01v8 (8->1)
+sky130_fd_pr__pfet_01v8_hvt (12->1) |sky130_fd_pr__pfet_01v8_hvt (12->1)
+Number of devices: 2 |Number of devices: 2
+Number of nets: 6 |Number of nets: 6
+---------------------------------------------------------------------------------------
+Netlists match uniquely.
+
+Subcircuit pins:
+Circuit 1: sky130_fd_sc_hd__clkinv_8 |Circuit 2: sky130_fd_sc_hd__clkinv_8
+-------------------------------------------|-------------------------------------------
+VPWR |VPWR
+VPB |VPB
+VGND |VGND
+VNB |VNB
+Y |Y
+A |A
+---------------------------------------------------------------------------------------
+Cell pin lists are equivalent.
+Device classes sky130_fd_sc_hd__clkinv_8 and sky130_fd_sc_hd__clkinv_8 are equivalent.
+
+Class sky130_fd_sc_hd__xnor2_2 (0): Merged 10 parallel devices.
+Class sky130_fd_sc_hd__xnor2_2 (1): Merged 10 parallel devices.
+Subcircuit summary:
+Circuit 1: sky130_fd_sc_hd__xnor2_2 |Circuit 2: sky130_fd_sc_hd__xnor2_2
+-------------------------------------------|-------------------------------------------
+sky130_fd_pr__pfet_01v8_hvt (10->5) |sky130_fd_pr__pfet_01v8_hvt (10->5)
+sky130_fd_pr__nfet_01v8 (10->5) |sky130_fd_pr__nfet_01v8 (10->5)
+Number of devices: 10 |Number of devices: 10
+Number of nets: 11 |Number of nets: 11
+---------------------------------------------------------------------------------------
+Netlists match uniquely.
+
+Subcircuit pins:
+Circuit 1: sky130_fd_sc_hd__xnor2_2 |Circuit 2: sky130_fd_sc_hd__xnor2_2
+-------------------------------------------|-------------------------------------------
+VGND |VGND
+Y |Y
+VPWR |VPWR
+B |B
+A |A
+VPB |VPB
+VNB |VNB
+---------------------------------------------------------------------------------------
+Cell pin lists are equivalent.
+Device classes sky130_fd_sc_hd__xnor2_2 and sky130_fd_sc_hd__xnor2_2 are equivalent.
+
+Class sky130_fd_sc_hd__o41ai_2 (0): Merged 10 parallel devices.
+Class sky130_fd_sc_hd__o41ai_2 (1): Merged 10 parallel devices.
+Subcircuit summary:
+Circuit 1: sky130_fd_sc_hd__o41ai_2 |Circuit 2: sky130_fd_sc_hd__o41ai_2
+-------------------------------------------|-------------------------------------------
+sky130_fd_pr__nfet_01v8 (10->5) |sky130_fd_pr__nfet_01v8 (10->5)
+sky130_fd_pr__pfet_01v8_hvt (10->5) |sky130_fd_pr__pfet_01v8_hvt (10->5)
+Number of devices: 10 |Number of devices: 10
+Number of nets: 14 |Number of nets: 14
+---------------------------------------------------------------------------------------
+Netlists match uniquely.
+
+Subcircuit pins:
+Circuit 1: sky130_fd_sc_hd__o41ai_2 |Circuit 2: sky130_fd_sc_hd__o41ai_2
+-------------------------------------------|-------------------------------------------
+Y |Y
+VGND |VGND
+A1 |A1
+A3 |A3
+A2 |A2
+A4 |A4
+B1 |B1
+VPWR |VPWR
+VPB |VPB
+VNB |VNB
+---------------------------------------------------------------------------------------
+Cell pin lists are equivalent.
+Device classes sky130_fd_sc_hd__o41ai_2 and sky130_fd_sc_hd__o41ai_2 are equivalent.
+
+Class sky130_fd_sc_hd__o31ai_4 (0): Merged 24 parallel devices.
+Class sky130_fd_sc_hd__o31ai_4 (1): Merged 24 parallel devices.
+Subcircuit summary:
+Circuit 1: sky130_fd_sc_hd__o31ai_4 |Circuit 2: sky130_fd_sc_hd__o31ai_4
+-------------------------------------------|-------------------------------------------
+sky130_fd_pr__pfet_01v8_hvt (16->4) |sky130_fd_pr__pfet_01v8_hvt (16->4)
+sky130_fd_pr__nfet_01v8 (16->4) |sky130_fd_pr__nfet_01v8 (16->4)
+Number of devices: 8 |Number of devices: 8
+Number of nets: 12 |Number of nets: 12
+---------------------------------------------------------------------------------------
+Netlists match uniquely.
+
+Subcircuit pins:
+Circuit 1: sky130_fd_sc_hd__o31ai_4 |Circuit 2: sky130_fd_sc_hd__o31ai_4
+-------------------------------------------|-------------------------------------------
+VPB |VPB
+VNB |VNB
+A2 |A2
+A1 |A1
+VPWR |VPWR
+B1 |B1
+A3 |A3
+VGND |VGND
+Y |Y
+---------------------------------------------------------------------------------------
+Cell pin lists are equivalent.
+Device classes sky130_fd_sc_hd__o31ai_4 and sky130_fd_sc_hd__o31ai_4 are equivalent.
+
+Class sky130_fd_sc_hd__o31ai_2 (0): Merged 8 parallel devices.
+Class sky130_fd_sc_hd__o31ai_2 (1): Merged 8 parallel devices.
+Subcircuit summary:
+Circuit 1: sky130_fd_sc_hd__o31ai_2 |Circuit 2: sky130_fd_sc_hd__o31ai_2
+-------------------------------------------|-------------------------------------------
+sky130_fd_pr__pfet_01v8_hvt (8->4) |sky130_fd_pr__pfet_01v8_hvt (8->4)
+sky130_fd_pr__nfet_01v8 (8->4) |sky130_fd_pr__nfet_01v8 (8->4)
+Number of devices: 8 |Number of devices: 8
+Number of nets: 12 |Number of nets: 12
+---------------------------------------------------------------------------------------
+Netlists match uniquely.
+
+Subcircuit pins:
+Circuit 1: sky130_fd_sc_hd__o31ai_2 |Circuit 2: sky130_fd_sc_hd__o31ai_2
+-------------------------------------------|-------------------------------------------
+VPB |VPB
+VNB |VNB
+Y |Y
+VGND |VGND
+VPWR |VPWR
+A1 |A1
+A2 |A2
+B1 |B1
+A3 |A3
+---------------------------------------------------------------------------------------
+Cell pin lists are equivalent.
+Device classes sky130_fd_sc_hd__o31ai_2 and sky130_fd_sc_hd__o31ai_2 are equivalent.
+
+Class sky130_fd_sc_hd__o2111a_4 (0): Merged 12 parallel devices.
+Class sky130_fd_sc_hd__o2111a_4 (1): Merged 12 parallel devices.
+Subcircuit summary:
+Circuit 1: sky130_fd_sc_hd__o2111a_4 |Circuit 2: sky130_fd_sc_hd__o2111a_4
+-------------------------------------------|-------------------------------------------
+sky130_fd_pr__nfet_01v8 (14->8) |sky130_fd_pr__nfet_01v8 (14->8)
+sky130_fd_pr__pfet_01v8_hvt (14->8) |sky130_fd_pr__pfet_01v8_hvt (14->8)
+Number of devices: 16 |Number of devices: 16
+Number of nets: 17 |Number of nets: 17
+---------------------------------------------------------------------------------------
+Resolving automorphisms by property value.
+Resolving automorphisms by pin name.
+Netlists match uniquely.
+
+Subcircuit pins:
+Circuit 1: sky130_fd_sc_hd__o2111a_4 |Circuit 2: sky130_fd_sc_hd__o2111a_4
+-------------------------------------------|-------------------------------------------
+VPWR |VPWR
+X |X
+D1 |D1
+VNB |VNB
+VPB |VPB
+VGND |VGND
+A2 |A2
+A1 |A1
+B1 |B1
+C1 |C1
+---------------------------------------------------------------------------------------
+Cell pin lists are equivalent.
+Device classes sky130_fd_sc_hd__o2111a_4 and sky130_fd_sc_hd__o2111a_4 are equivalent.
+
+Class sky130_fd_sc_hd__o2bb2a_4 (0): Merged 16 parallel devices.
+Class sky130_fd_sc_hd__o2bb2a_4 (1): Merged 16 parallel devices.
+Subcircuit summary:
+Circuit 1: sky130_fd_sc_hd__o2bb2a_4 |Circuit 2: sky130_fd_sc_hd__o2bb2a_4
+-------------------------------------------|-------------------------------------------
+sky130_fd_pr__nfet_01v8 (14->6) |sky130_fd_pr__nfet_01v8 (14->6)
+sky130_fd_pr__pfet_01v8_hvt (14->6) |sky130_fd_pr__pfet_01v8_hvt (14->6)
+Number of devices: 12 |Number of devices: 12
+Number of nets: 14 |Number of nets: 14
+---------------------------------------------------------------------------------------
+Netlists match uniquely.
+
+Subcircuit pins:
+Circuit 1: sky130_fd_sc_hd__o2bb2a_4 |Circuit 2: sky130_fd_sc_hd__o2bb2a_4
+-------------------------------------------|-------------------------------------------
+VGND |VGND
+A2_N |A2_N
+X |X
+A1_N |A1_N
+B2 |B2
+B1 |B1
+VNB |VNB
+VPB |VPB
+VPWR |VPWR
+---------------------------------------------------------------------------------------
+Cell pin lists are equivalent.
+Device classes sky130_fd_sc_hd__o2bb2a_4 and sky130_fd_sc_hd__o2bb2a_4 are equivalent.
+
+Class sky130_fd_sc_hd__a41o_4 (0): Merged 16 parallel devices.
+Class sky130_fd_sc_hd__a41o_4 (1): Merged 16 parallel devices.
+Subcircuit summary:
+Circuit 1: sky130_fd_sc_hd__a41o_4 |Circuit 2: sky130_fd_sc_hd__a41o_4
+-------------------------------------------|-------------------------------------------
+sky130_fd_pr__nfet_01v8 (14->6) |sky130_fd_pr__nfet_01v8 (14->6)
+sky130_fd_pr__pfet_01v8_hvt (14->6) |sky130_fd_pr__pfet_01v8_hvt (14->6)
+Number of devices: 12 |Number of devices: 12
+Number of nets: 15 |Number of nets: 15
+---------------------------------------------------------------------------------------
+Netlists match uniquely.
+
+Subcircuit pins:
+Circuit 1: sky130_fd_sc_hd__a41o_4 |Circuit 2: sky130_fd_sc_hd__a41o_4
+-------------------------------------------|-------------------------------------------
+VGND |VGND
+VPB |VPB
+VNB |VNB
+VPWR |VPWR
+A3 |A3
+A2 |A2
+A1 |A1
+B1 |B1
+X |X
+A4 |A4
+---------------------------------------------------------------------------------------
+Cell pin lists are equivalent.
+Device classes sky130_fd_sc_hd__a41o_4 and sky130_fd_sc_hd__a41o_4 are equivalent.
+
+Class sky130_fd_sc_hd__a32oi_2 (0): Merged 10 parallel devices.
+Class sky130_fd_sc_hd__a32oi_2 (1): Merged 10 parallel devices.
+Subcircuit summary:
+Circuit 1: sky130_fd_sc_hd__a32oi_2 |Circuit 2: sky130_fd_sc_hd__a32oi_2
+-------------------------------------------|-------------------------------------------
+sky130_fd_pr__nfet_01v8 (10->5) |sky130_fd_pr__nfet_01v8 (10->5)
+sky130_fd_pr__pfet_01v8_hvt (10->5) |sky130_fd_pr__pfet_01v8_hvt (10->5)
+Number of devices: 10 |Number of devices: 10
+Number of nets: 14 |Number of nets: 14
+---------------------------------------------------------------------------------------
+Netlists match uniquely.
+
+Subcircuit pins:
+Circuit 1: sky130_fd_sc_hd__a32oi_2 |Circuit 2: sky130_fd_sc_hd__a32oi_2
+-------------------------------------------|-------------------------------------------
+VPWR |VPWR
+VNB |VNB
+VPB |VPB
+B1 |B1
+A1 |A1
+A3 |A3
+A2 |A2
+VGND |VGND
+B2 |B2
+Y |Y
+---------------------------------------------------------------------------------------
+Cell pin lists are equivalent.
+Device classes sky130_fd_sc_hd__a32oi_2 and sky130_fd_sc_hd__a32oi_2 are equivalent.
+
+Subcircuit summary:
+Circuit 1: sky130_fd_sc_hd__a32oi_1 |Circuit 2: sky130_fd_sc_hd__a32oi_1
+-------------------------------------------|-------------------------------------------
+sky130_fd_pr__pfet_01v8_hvt (5) |sky130_fd_pr__pfet_01v8_hvt (5)
+sky130_fd_pr__nfet_01v8 (5) |sky130_fd_pr__nfet_01v8 (5)
+Number of devices: 10 |Number of devices: 10
+Number of nets: 14 |Number of nets: 14
+---------------------------------------------------------------------------------------
+Netlists match uniquely.
+
+Subcircuit pins:
+Circuit 1: sky130_fd_sc_hd__a32oi_1 |Circuit 2: sky130_fd_sc_hd__a32oi_1
+-------------------------------------------|-------------------------------------------
+Y |Y
+VPB |VPB
+VNB |VNB
+A1 |A1
+A2 |A2
+A3 |A3
+B1 |B1
+VGND |VGND
+B2 |B2
+VPWR |VPWR
+---------------------------------------------------------------------------------------
+Cell pin lists are equivalent.
+Device classes sky130_fd_sc_hd__a32oi_1 and sky130_fd_sc_hd__a32oi_1 are equivalent.
+
+Class sky130_fd_sc_hd__a21boi_2 (0): Merged 4 parallel devices.
+Class sky130_fd_sc_hd__a21boi_2 (1): Merged 4 parallel devices.
+Subcircuit summary:
+Circuit 1: sky130_fd_sc_hd__a21boi_2 |Circuit 2: sky130_fd_sc_hd__a21boi_2
+-------------------------------------------|-------------------------------------------
+sky130_fd_pr__nfet_01v8 (7->6) |sky130_fd_pr__nfet_01v8 (7->6)
+sky130_fd_pr__pfet_01v8_hvt (7->4) |sky130_fd_pr__pfet_01v8_hvt (7->4)
+Number of devices: 10 |Number of devices: 10
+Number of nets: 12 |Number of nets: 12
+---------------------------------------------------------------------------------------
+Resolving automorphisms by property value.
+Resolving automorphisms by pin name.
+Netlists match uniquely.
+
+Subcircuit pins:
+Circuit 1: sky130_fd_sc_hd__a21boi_2 |Circuit 2: sky130_fd_sc_hd__a21boi_2
+-------------------------------------------|-------------------------------------------
+B1_N |B1_N
+VPWR |VPWR
+A1 |A1
+A2 |A2
+VNB |VNB
+Y |Y
+VGND |VGND
+VPB |VPB
+---------------------------------------------------------------------------------------
+Cell pin lists are equivalent.
+Device classes sky130_fd_sc_hd__a21boi_2 and sky130_fd_sc_hd__a21boi_2 are equivalent.
+
+Class sky130_fd_sc_hd__nand3b_2 (0): Merged 6 parallel devices.
+Class sky130_fd_sc_hd__nand3b_2 (1): Merged 6 parallel devices.
+Subcircuit summary:
+Circuit 1: sky130_fd_sc_hd__nand3b_2 |Circuit 2: sky130_fd_sc_hd__nand3b_2
+-------------------------------------------|-------------------------------------------
+sky130_fd_pr__nfet_01v8 (7->4) |sky130_fd_pr__nfet_01v8 (7->4)
+sky130_fd_pr__pfet_01v8_hvt (7->4) |sky130_fd_pr__pfet_01v8_hvt (7->4)
+Number of devices: 8 |Number of devices: 8
+Number of nets: 11 |Number of nets: 11
+---------------------------------------------------------------------------------------
+Netlists match uniquely.
+
+Subcircuit pins:
+Circuit 1: sky130_fd_sc_hd__nand3b_2 |Circuit 2: sky130_fd_sc_hd__nand3b_2
+-------------------------------------------|-------------------------------------------
+VPWR |VPWR
+Y |Y
+VPB |VPB
+VNB |VNB
+C |C
+B |B
+VGND |VGND
+A_N |A_N
+---------------------------------------------------------------------------------------
+Cell pin lists are equivalent.
+Device classes sky130_fd_sc_hd__nand3b_2 and sky130_fd_sc_hd__nand3b_2 are equivalent.
+
+Class RAM256 (0): Merged 2411 parallel devices.
+Class RAM256 (1): Merged 2411 parallel devices.
+Subcircuit summary:
+Circuit 1: RAM256 |Circuit 2: RAM256
+-------------------------------------------|-------------------------------------------
+sky130_fd_sc_hd__and2_1 (1024) |sky130_fd_sc_hd__and2_1 (1024)
+sky130_fd_sc_hd__dlxtp_1 (8192) |sky130_fd_sc_hd__dlxtp_1 (8192)
+sky130_fd_sc_hd__ebufn_2 (8448) |sky130_fd_sc_hd__ebufn_2 (8448)
+sky130_fd_sc_hd__dlclkp_1 (1024) |sky130_fd_sc_hd__dlclkp_1 (1024)
+sky130_fd_sc_hd__diode_2 (1604->836) |sky130_fd_sc_hd__diode_2 (1604->836)
+sky130_fd_sc_hd__and4_2 (32) |sky130_fd_sc_hd__and4_2 (32)
+sky130_fd_sc_hd__decap_12 (1319->1) |sky130_fd_sc_hd__decap_12 (1319->1)
+sky130_fd_sc_hd__inv_1 (2048) |sky130_fd_sc_hd__inv_1 (2048)
+sky130_fd_sc_hd__dfxtp_1 (256) |sky130_fd_sc_hd__dfxtp_1 (256)
+sky130_fd_sc_hd__mux4_1 (64) |sky130_fd_sc_hd__mux4_1 (64)
+sky130_fd_sc_hd__clkbuf_4 (306) |sky130_fd_sc_hd__clkbuf_4 (306)
+sky130_fd_sc_hd__and3b_2 (20) |sky130_fd_sc_hd__and3b_2 (20)
+sky130_fd_sc_hd__clkbuf_16 (320) |sky130_fd_sc_hd__clkbuf_16 (320)
+sky130_fd_sc_hd__decap_3 (148->1) |sky130_fd_sc_hd__decap_3 (148->1)
+sky130_fd_sc_hd__clkbuf_2 (700) |sky130_fd_sc_hd__clkbuf_2 (700)
+sky130_fd_sc_hd__and4bb_2 (96) |sky130_fd_sc_hd__and4bb_2 (96)
+sky130_fd_sc_hd__decap_8 (102->1) |sky130_fd_sc_hd__decap_8 (102->1)
+sky130_fd_sc_hd__nor4b_2 (32) |sky130_fd_sc_hd__nor4b_2 (32)
+sky130_fd_sc_hd__and4b_2 (96) |sky130_fd_sc_hd__and4b_2 (96)
+sky130_fd_sc_hd__decap_4 (25->1) |sky130_fd_sc_hd__decap_4 (25->1)
+sky130_fd_sc_hd__and3_2 (10) |sky130_fd_sc_hd__and3_2 (10)
+sky130_fd_sc_hd__decap_6 (54->1) |sky130_fd_sc_hd__decap_6 (54->1)
+sky130_fd_sc_hd__mux2_1 (32) |sky130_fd_sc_hd__mux2_1 (32)
+sky130_fd_sc_hd__conb_1 (32) |sky130_fd_sc_hd__conb_1 (32)
+sky130_fd_sc_hd__nor3b_2 (10) |sky130_fd_sc_hd__nor3b_2 (10)
+sky130_fd_sc_hd__and2b_2 (1) |sky130_fd_sc_hd__and2b_2 (1)
+sky130_fd_sc_hd__and2_2 (1) |sky130_fd_sc_hd__and2_2 (1)
+Number of devices: 23585 |Number of devices: 23585
+Number of nets: 14632 |Number of nets: 14632
+---------------------------------------------------------------------------------------
+Resolving automorphisms by property value.
+Resolving automorphisms by pin name.
+Netlists match uniquely.
+
+Subcircuit pins:
+Circuit 1: RAM256 |Circuit 2: RAM256
+-------------------------------------------|-------------------------------------------
+Do0[0] |Do0[0]
+Do0[1] |Do0[1]
+Do0[2] |Do0[2]
+Do0[3] |Do0[3]
+Do0[4] |Do0[4]
+Do0[5] |Do0[5]
+Do0[6] |Do0[6]
+Do0[7] |Do0[7]
+Do0[8] |Do0[8]
+Do0[9] |Do0[9]
+Do0[10] |Do0[10]
+Do0[11] |Do0[11]
+Do0[12] |Do0[12]
+Do0[13] |Do0[13]
+Do0[14] |Do0[14]
+Do0[15] |Do0[15]
+Do0[16] |Do0[16]
+Do0[17] |Do0[17]
+Do0[18] |Do0[18]
+Do0[19] |Do0[19]
+Do0[20] |Do0[20]
+Do0[21] |Do0[21]
+Do0[22] |Do0[22]
+Do0[23] |Do0[23]
+Do0[24] |Do0[24]
+Do0[25] |Do0[25]
+Do0[26] |Do0[26]
+Do0[27] |Do0[27]
+Do0[28] |Do0[28]
+Do0[29] |Do0[29]
+Do0[30] |Do0[30]
+Do0[31] |Do0[31]
+A0[7] |A0[7]
+A0[6] |A0[6]
+A0[5] |A0[5]
+CLK |CLK
+Di0[0] |Di0[0]
+Di0[10] |Di0[10]
+Di0[11] |Di0[11]
+Di0[12] |Di0[12]
+Di0[13] |Di0[13]
+Di0[14] |Di0[14]
+Di0[15] |Di0[15]
+Di0[16] |Di0[16]
+Di0[17] |Di0[17]
+Di0[18] |Di0[18]
+Di0[19] |Di0[19]
+Di0[1] |Di0[1]
+Di0[20] |Di0[20]
+Di0[21] |Di0[21]
+Di0[22] |Di0[22]
+Di0[23] |Di0[23]
+Di0[24] |Di0[24]
+Di0[25] |Di0[25]
+Di0[26] |Di0[26]
+Di0[27] |Di0[27]
+Di0[28] |Di0[28]
+Di0[29] |Di0[29]
+Di0[2] |Di0[2]
+Di0[30] |Di0[30]
+Di0[31] |Di0[31]
+Di0[3] |Di0[3]
+Di0[4] |Di0[4]
+Di0[5] |Di0[5]
+Di0[6] |Di0[6]
+Di0[7] |Di0[7]
+Di0[8] |Di0[8]
+Di0[9] |Di0[9]
+A0[3] |A0[3]
+A0[4] |A0[4]
+A0[0] |A0[0]
+A0[1] |A0[1]
+A0[2] |A0[2]
+WE0[0] |WE0[0]
+WE0[1] |WE0[1]
+WE0[2] |WE0[2]
+WE0[3] |WE0[3]
+EN0 |EN0
+VGND |VGND
+VPWR |VPWR
+---------------------------------------------------------------------------------------
+Cell pin lists are equivalent.
+Device classes RAM256 and RAM256 are equivalent.
+
+Class sky130_fd_sc_hd__o21bai_2 (0): Merged 6 parallel devices.
+Class sky130_fd_sc_hd__o21bai_2 (1): Merged 6 parallel devices.
+Subcircuit summary:
+Circuit 1: sky130_fd_sc_hd__o21bai_2 |Circuit 2: sky130_fd_sc_hd__o21bai_2
+-------------------------------------------|-------------------------------------------
+sky130_fd_pr__pfet_01v8_hvt (7->4) |sky130_fd_pr__pfet_01v8_hvt (7->4)
+sky130_fd_pr__nfet_01v8 (7->4) |sky130_fd_pr__nfet_01v8 (7->4)
+Number of devices: 8 |Number of devices: 8
+Number of nets: 11 |Number of nets: 11
+---------------------------------------------------------------------------------------
+Netlists match uniquely.
+
+Subcircuit pins:
+Circuit 1: sky130_fd_sc_hd__o21bai_2 |Circuit 2: sky130_fd_sc_hd__o21bai_2
+-------------------------------------------|-------------------------------------------
+VPB |VPB
+VNB |VNB
+Y |Y
+VPWR |VPWR
+VGND |VGND
+B1_N |B1_N
+A1 |A1
+A2 |A2
+---------------------------------------------------------------------------------------
+Cell pin lists are equivalent.
+Device classes sky130_fd_sc_hd__o21bai_2 and sky130_fd_sc_hd__o21bai_2 are equivalent.
+
+Class sky130_fd_sc_hd__o2bb2ai_4 (0): Merged 30 parallel devices.
+Class sky130_fd_sc_hd__o2bb2ai_4 (1): Merged 30 parallel devices.
+Subcircuit summary:
+Circuit 1: sky130_fd_sc_hd__o2bb2ai_4 |Circuit 2: sky130_fd_sc_hd__o2bb2ai_4
+-------------------------------------------|-------------------------------------------
+sky130_fd_pr__pfet_01v8_hvt (20->5) |sky130_fd_pr__pfet_01v8_hvt (20->5)
+sky130_fd_pr__nfet_01v8 (20->5) |sky130_fd_pr__nfet_01v8 (20->5)
+Number of devices: 10 |Number of devices: 10
+Number of nets: 13 |Number of nets: 13
+---------------------------------------------------------------------------------------
+Netlists match uniquely.
+
+Subcircuit pins:
+Circuit 1: sky130_fd_sc_hd__o2bb2ai_4 |Circuit 2: sky130_fd_sc_hd__o2bb2ai_4
+-------------------------------------------|-------------------------------------------
+VGND |VGND
+Y |Y
+VPB |VPB
+VNB |VNB
+VPWR |VPWR
+A1_N |A1_N
+B2 |B2
+B1 |B1
+A2_N |A2_N
+---------------------------------------------------------------------------------------
+Cell pin lists are equivalent.
+Device classes sky130_fd_sc_hd__o2bb2ai_4 and sky130_fd_sc_hd__o2bb2ai_4 are equivalent.
+
+Class sky130_fd_sc_hd__o311ai_2 (0): Merged 10 parallel devices.
+Class sky130_fd_sc_hd__o311ai_2 (1): Merged 10 parallel devices.
+Subcircuit summary:
+Circuit 1: sky130_fd_sc_hd__o311ai_2 |Circuit 2: sky130_fd_sc_hd__o311ai_2
+-------------------------------------------|-------------------------------------------
+sky130_fd_pr__pfet_01v8_hvt (10->5) |sky130_fd_pr__pfet_01v8_hvt (10->5)
+sky130_fd_pr__nfet_01v8 (10->5) |sky130_fd_pr__nfet_01v8 (10->5)
+Number of devices: 10 |Number of devices: 10
+Number of nets: 14 |Number of nets: 14
+---------------------------------------------------------------------------------------
+Netlists match uniquely.
+
+Subcircuit pins:
+Circuit 1: sky130_fd_sc_hd__o311ai_2 |Circuit 2: sky130_fd_sc_hd__o311ai_2
+-------------------------------------------|-------------------------------------------
+Y |Y
+VNB |VNB
+VPB |VPB
+A3 |A3
+A1 |A1
+B1 |B1
+C1 |C1
+A2 |A2
+VGND |VGND
+VPWR |VPWR
+---------------------------------------------------------------------------------------
+Cell pin lists are equivalent.
+Device classes sky130_fd_sc_hd__o311ai_2 and sky130_fd_sc_hd__o311ai_2 are equivalent.
+
+Class sky130_fd_sc_hd__a2111oi_2 (0): Merged 6 parallel devices.
+Class sky130_fd_sc_hd__a2111oi_2 (1): Merged 6 parallel devices.
+Subcircuit summary:
+Circuit 1: sky130_fd_sc_hd__a2111oi_2 |Circuit 2: sky130_fd_sc_hd__a2111oi_2
+-------------------------------------------|-------------------------------------------
+sky130_fd_pr__pfet_01v8_hvt (10->7) |sky130_fd_pr__pfet_01v8_hvt (10->7)
+sky130_fd_pr__nfet_01v8 (10->7) |sky130_fd_pr__nfet_01v8 (10->7)
+Number of devices: 14 |Number of devices: 14
+Number of nets: 16 |Number of nets: 16
+---------------------------------------------------------------------------------------
+Resolving automorphisms by property value.
+Resolving automorphisms by pin name.
+Netlists match uniquely.
+
+Subcircuit pins:
+Circuit 1: sky130_fd_sc_hd__a2111oi_2 |Circuit 2: sky130_fd_sc_hd__a2111oi_2
+-------------------------------------------|-------------------------------------------
+VGND |VGND
+Y |Y
+VNB |VNB
+VPB |VPB
+VPWR |VPWR
+B1 |B1
+D1 |D1
+A2 |A2
+A1 |A1
+C1 |C1
+---------------------------------------------------------------------------------------
+Cell pin lists are equivalent.
+Device classes sky130_fd_sc_hd__a2111oi_2 and sky130_fd_sc_hd__a2111oi_2 are equivalent.
+
+Subcircuit summary:
+Circuit 1: sky130_fd_sc_hd__nand4b_1 |Circuit 2: sky130_fd_sc_hd__nand4b_1
+-------------------------------------------|-------------------------------------------
+sky130_fd_pr__pfet_01v8_hvt (5) |sky130_fd_pr__pfet_01v8_hvt (5)
+sky130_fd_pr__nfet_01v8 (5) |sky130_fd_pr__nfet_01v8 (5)
+Number of devices: 10 |Number of devices: 10
+Number of nets: 13 |Number of nets: 13
+---------------------------------------------------------------------------------------
+Netlists match uniquely.
+
+Subcircuit pins:
+Circuit 1: sky130_fd_sc_hd__nand4b_1 |Circuit 2: sky130_fd_sc_hd__nand4b_1
+-------------------------------------------|-------------------------------------------
+A_N |A_N
+C |C
+D |D
+B |B
+VGND |VGND
+Y |Y
+VPWR |VPWR
+VPB |VPB
+VNB |VNB
+---------------------------------------------------------------------------------------
+Cell pin lists are equivalent.
+Device classes sky130_fd_sc_hd__nand4b_1 and sky130_fd_sc_hd__nand4b_1 are equivalent.
+
+Subcircuit summary:
+Circuit 1: sky130_fd_sc_hd__nor3b_1 |Circuit 2: sky130_fd_sc_hd__nor3b_1
+-------------------------------------------|-------------------------------------------
+sky130_fd_pr__nfet_01v8 (4) |sky130_fd_pr__nfet_01v8 (4)
+sky130_fd_pr__pfet_01v8_hvt (4) |sky130_fd_pr__pfet_01v8_hvt (4)
+Number of devices: 8 |Number of devices: 8
+Number of nets: 11 |Number of nets: 11
+---------------------------------------------------------------------------------------
+Netlists match uniquely.
+
+Subcircuit pins:
+Circuit 1: sky130_fd_sc_hd__nor3b_1 |Circuit 2: sky130_fd_sc_hd__nor3b_1
+-------------------------------------------|-------------------------------------------
+VPWR |VPWR
+C_N |C_N
+A |A
+B |B
+Y |Y
+VGND |VGND
+VNB |VNB
+VPB |VPB
+---------------------------------------------------------------------------------------
+Cell pin lists are equivalent.
+Device classes sky130_fd_sc_hd__nor3b_1 and sky130_fd_sc_hd__nor3b_1 are equivalent.
+
+Subcircuit summary:
+Circuit 1: sky130_fd_sc_hd__a41oi_1 |Circuit 2: sky130_fd_sc_hd__a41oi_1
+-------------------------------------------|-------------------------------------------
+sky130_fd_pr__nfet_01v8 (5) |sky130_fd_pr__nfet_01v8 (5)
+sky130_fd_pr__pfet_01v8_hvt (5) |sky130_fd_pr__pfet_01v8_hvt (5)
+Number of devices: 10 |Number of devices: 10
+Number of nets: 14 |Number of nets: 14
+---------------------------------------------------------------------------------------
+Netlists match uniquely.
+
+Subcircuit pins:
+Circuit 1: sky130_fd_sc_hd__a41oi_1 |Circuit 2: sky130_fd_sc_hd__a41oi_1
+-------------------------------------------|-------------------------------------------
+Y |Y
+VPWR |VPWR
+VNB |VNB
+VPB |VPB
+A3 |A3
+A2 |A2
+A4 |A4
+A1 |A1
+VGND |VGND
+B1 |B1
+---------------------------------------------------------------------------------------
+Cell pin lists are equivalent.
+Device classes sky130_fd_sc_hd__a41oi_1 and sky130_fd_sc_hd__a41oi_1 are equivalent.
+
+Class sky130_fd_sc_hd__a311oi_2 (0): Merged 10 parallel devices.
+Class sky130_fd_sc_hd__a311oi_2 (1): Merged 10 parallel devices.
+Subcircuit summary:
+Circuit 1: sky130_fd_sc_hd__a311oi_2 |Circuit 2: sky130_fd_sc_hd__a311oi_2
+-------------------------------------------|-------------------------------------------
+sky130_fd_pr__nfet_01v8 (10->5) |sky130_fd_pr__nfet_01v8 (10->5)
+sky130_fd_pr__pfet_01v8_hvt (10->5) |sky130_fd_pr__pfet_01v8_hvt (10->5)
+Number of devices: 10 |Number of devices: 10
+Number of nets: 14 |Number of nets: 14
+---------------------------------------------------------------------------------------
+Netlists match uniquely.
+
+Subcircuit pins:
+Circuit 1: sky130_fd_sc_hd__a311oi_2 |Circuit 2: sky130_fd_sc_hd__a311oi_2
+-------------------------------------------|-------------------------------------------
+VPWR |VPWR
+VGND |VGND
+VPB |VPB
+VNB |VNB
+A2 |A2
+A1 |A1
+C1 |C1
+B1 |B1
+A3 |A3
+Y |Y
+---------------------------------------------------------------------------------------
+Cell pin lists are equivalent.
+Device classes sky130_fd_sc_hd__a311oi_2 and sky130_fd_sc_hd__a311oi_2 are equivalent.
+
+Class sky130_fd_sc_hd__o32ai_4 (0): Merged 30 parallel devices.
+Class sky130_fd_sc_hd__o32ai_4 (1): Merged 30 parallel devices.
+Subcircuit summary:
+Circuit 1: sky130_fd_sc_hd__o32ai_4 |Circuit 2: sky130_fd_sc_hd__o32ai_4
+-------------------------------------------|-------------------------------------------
+sky130_fd_pr__pfet_01v8_hvt (20->5) |sky130_fd_pr__pfet_01v8_hvt (20->5)
+sky130_fd_pr__nfet_01v8 (20->5) |sky130_fd_pr__nfet_01v8 (20->5)
+Number of devices: 10 |Number of devices: 10
+Number of nets: 14 |Number of nets: 14
+---------------------------------------------------------------------------------------
+Netlists match uniquely.
+
+Subcircuit pins:
+Circuit 1: sky130_fd_sc_hd__o32ai_4 |Circuit 2: sky130_fd_sc_hd__o32ai_4
+-------------------------------------------|-------------------------------------------
+Y |Y
+VGND |VGND
+VNB |VNB
+VPB |VPB
+A3 |A3
+VPWR |VPWR
+B1 |B1
+A2 |A2
+A1 |A1
+B2 |B2
+---------------------------------------------------------------------------------------
+Cell pin lists are equivalent.
+Device classes sky130_fd_sc_hd__o32ai_4 and sky130_fd_sc_hd__o32ai_4 are equivalent.
+
+Class sky130_fd_sc_hd__a41oi_4 (0): Merged 30 parallel devices.
+Class sky130_fd_sc_hd__a41oi_4 (1): Merged 30 parallel devices.
+Subcircuit summary:
+Circuit 1: sky130_fd_sc_hd__a41oi_4 |Circuit 2: sky130_fd_sc_hd__a41oi_4
+-------------------------------------------|-------------------------------------------
+sky130_fd_pr__pfet_01v8_hvt (20->5) |sky130_fd_pr__pfet_01v8_hvt (20->5)
+sky130_fd_pr__nfet_01v8 (20->5) |sky130_fd_pr__nfet_01v8 (20->5)
+Number of devices: 10 |Number of devices: 10
+Number of nets: 14 |Number of nets: 14
+---------------------------------------------------------------------------------------
+Netlists match uniquely.
+
+Subcircuit pins:
+Circuit 1: sky130_fd_sc_hd__a41oi_4 |Circuit 2: sky130_fd_sc_hd__a41oi_4
+-------------------------------------------|-------------------------------------------
+Y |Y
+VPB |VPB
+VNB |VNB
+A1 |A1
+VGND |VGND
+B1 |B1
+A3 |A3
+A4 |A4
+A2 |A2
+VPWR |VPWR
+---------------------------------------------------------------------------------------
+Cell pin lists are equivalent.
+Device classes sky130_fd_sc_hd__a41oi_4 and sky130_fd_sc_hd__a41oi_4 are equivalent.
+
+Cell mgmt_core_wrapper (0) disconnected node: flash_io0_di
+Cell mgmt_core_wrapper (0) disconnected node: flash_io2_di
+Cell mgmt_core_wrapper (0) disconnected node: flash_io3_di
+Cell mgmt_core_wrapper (1) disconnected node: flash_io0_di
+Cell mgmt_core_wrapper (1) disconnected node: flash_io2_di
+Cell mgmt_core_wrapper (1) disconnected node: flash_io3_di
+Class mgmt_core_wrapper (0): Merged 117481 parallel devices.
+Class mgmt_core_wrapper (1): Merged 117481 parallel devices.
+Cell mgmt_core_wrapper (0) disconnected node: flash_io0_di
+Cell mgmt_core_wrapper (0) disconnected node: flash_io2_di
+Cell mgmt_core_wrapper (0) disconnected node: flash_io3_di
+Cell mgmt_core_wrapper (1) disconnected node: flash_io0_di
+Cell mgmt_core_wrapper (1) disconnected node: flash_io2_di
+Cell mgmt_core_wrapper (1) disconnected node: flash_io3_di
+Subcircuit summary:
+Circuit 1: mgmt_core_wrapper |Circuit 2: mgmt_core_wrapper
+-------------------------------------------|-------------------------------------------
+sky130_fd_sc_hd__decap_6 (10271->1) |sky130_fd_sc_hd__decap_6 (10271->1)
+sky130_ef_sc_hd__decap_12 (48747->1) |sky130_ef_sc_hd__decap_12 (48747->1)
+sky130_fd_sc_hd__diode_2 (37950->5040) |sky130_fd_sc_hd__diode_2 (37950->5040)
+sky130_fd_sc_hd__clkbuf_16 (578) |sky130_fd_sc_hd__clkbuf_16 (578)
+sky130_fd_sc_hd__decap_4 (9275->1) |sky130_fd_sc_hd__decap_4 (9275->1)
+sky130_fd_sc_hd__decap_3 (8721->1) |sky130_fd_sc_hd__decap_3 (8721->1)
+sky130_fd_sc_hd__decap_8 (7562->1) |sky130_fd_sc_hd__decap_8 (7562->1)
+sky130_fd_sc_hd__a211o_1 (540) |sky130_fd_sc_hd__a211o_1 (540)
+sky130_fd_sc_hd__mux2_1 (3182) |sky130_fd_sc_hd__mux2_1 (3182)
+sky130_fd_sc_hd__a211oi_2 (5) |sky130_fd_sc_hd__a211oi_2 (5)
+sky130_fd_sc_hd__o211a_1 (1019) |sky130_fd_sc_hd__o211a_1 (1019)
+sky130_fd_sc_hd__and4b_1 (42) |sky130_fd_sc_hd__and4b_1 (42)
+sky130_fd_sc_hd__o41a_1 (27) |sky130_fd_sc_hd__o41a_1 (27)
+sky130_fd_sc_hd__a221o_1 (265) |sky130_fd_sc_hd__a221o_1 (265)
+sky130_fd_sc_hd__a32o_1 (171) |sky130_fd_sc_hd__a32o_1 (171)
+sky130_fd_sc_hd__nor2_1 (215) |sky130_fd_sc_hd__nor2_1 (215)
+sky130_fd_sc_hd__dfxtp_1 (3755) |sky130_fd_sc_hd__dfxtp_1 (3755)
+sky130_fd_sc_hd__o31a_1 (254) |sky130_fd_sc_hd__o31a_1 (254)
+sky130_fd_sc_hd__dlygate4sd3_1 (3154) |sky130_fd_sc_hd__dlygate4sd3_1 (3154)
+sky130_fd_sc_hd__dfxtp_4 (583) |sky130_fd_sc_hd__dfxtp_4 (583)
+sky130_fd_sc_hd__buf_6 (298) |sky130_fd_sc_hd__buf_6 (298)
+sky130_fd_sc_hd__buf_12 (1138) |sky130_fd_sc_hd__buf_12 (1138)
+sky130_fd_sc_hd__or4b_4 (30) |sky130_fd_sc_hd__or4b_4 (30)
+sky130_fd_sc_hd__buf_8 (237) |sky130_fd_sc_hd__buf_8 (237)
+sky130_fd_sc_hd__nand2_1 (341) |sky130_fd_sc_hd__nand2_1 (341)
+sky130_fd_sc_hd__buf_4 (110) |sky130_fd_sc_hd__buf_4 (110)
+sky130_fd_sc_hd__a31o_1 (460) |sky130_fd_sc_hd__a31o_1 (460)
+sky130_fd_sc_hd__a21bo_1 (48) |sky130_fd_sc_hd__a21bo_1 (48)
+sky130_fd_sc_hd__o21a_1 (314) |sky130_fd_sc_hd__o21a_1 (314)
+sky130_fd_sc_hd__a31o_4 (25) |sky130_fd_sc_hd__a31o_4 (25)
+sky130_fd_sc_hd__and3_4 (56) |sky130_fd_sc_hd__and3_4 (56)
+sky130_fd_sc_hd__a211oi_4 (5) |sky130_fd_sc_hd__a211oi_4 (5)
+sky130_fd_sc_hd__o221a_1 (293) |sky130_fd_sc_hd__o221a_1 (293)
+sky130_fd_sc_hd__o311a_1 (302) |sky130_fd_sc_hd__o311a_1 (302)
+sky130_fd_sc_hd__a21o_1 (746) |sky130_fd_sc_hd__a21o_1 (746)
+sky130_fd_sc_hd__a41o_1 (181) |sky130_fd_sc_hd__a41o_1 (181)
+sky130_fd_sc_hd__a31oi_1 (46) |sky130_fd_sc_hd__a31oi_1 (46)
+sky130_fd_sc_hd__a22o_1 (428) |sky130_fd_sc_hd__a22o_1 (428)
+sky130_fd_sc_hd__or3b_1 (155) |sky130_fd_sc_hd__or3b_1 (155)
+sky130_fd_sc_hd__and3_1 (315) |sky130_fd_sc_hd__and3_1 (315)
+sky130_fd_sc_hd__o22a_1 (60) |sky130_fd_sc_hd__o22a_1 (60)
+sky130_fd_sc_hd__a22o_2 (52) |sky130_fd_sc_hd__a22o_2 (52)
+sky130_fd_sc_hd__a22o_4 (60) |sky130_fd_sc_hd__a22o_4 (60)
+sky130_fd_sc_hd__and2b_1 (23) |sky130_fd_sc_hd__and2b_1 (23)
+sky130_fd_sc_hd__dfxtp_2 (389) |sky130_fd_sc_hd__dfxtp_2 (389)
+sky130_fd_sc_hd__and2_1 (107) |sky130_fd_sc_hd__and2_1 (107)
+sky130_fd_sc_hd__o21ai_1 (384) |sky130_fd_sc_hd__o21ai_1 (384)
+sky130_fd_sc_hd__and4_1 (150) |sky130_fd_sc_hd__and4_1 (150)
+sky130_fd_sc_hd__a311oi_4 (18) |sky130_fd_sc_hd__a311oi_4 (18)
+sky130_fd_sc_hd__a221o_4 (60) |sky130_fd_sc_hd__a221o_4 (60)
+sky130_fd_sc_hd__inv_2 (339) |sky130_fd_sc_hd__inv_2 (339)
+sky130_fd_sc_hd__a311o_1 (165) |sky130_fd_sc_hd__a311o_1 (165)
+sky130_fd_sc_hd__mux4_2 (14) |sky130_fd_sc_hd__mux4_2 (14)
+sky130_fd_sc_hd__and3b_4 (6) |sky130_fd_sc_hd__and3b_4 (6)
+sky130_fd_sc_hd__a2111o_1 (15) |sky130_fd_sc_hd__a2111o_1 (15)
+sky130_fd_sc_hd__nor4_1 (34) |sky130_fd_sc_hd__nor4_1 (34)
+sky130_fd_sc_hd__o21ai_4 (51) |sky130_fd_sc_hd__o21ai_4 (51)
+sky130_fd_sc_hd__o21ba_1 (146) |sky130_fd_sc_hd__o21ba_1 (146)
+sky130_fd_sc_hd__clkbuf_8 (147) |sky130_fd_sc_hd__clkbuf_8 (147)
+sky130_fd_sc_hd__a31oi_4 (16) |sky130_fd_sc_hd__a31oi_4 (16)
+sky130_fd_sc_hd__nand4_1 (53) |sky130_fd_sc_hd__nand4_1 (53)
+sky130_fd_sc_hd__or4b_1 (178) |sky130_fd_sc_hd__or4b_1 (178)
+sky130_fd_sc_hd__mux4_1 (80) |sky130_fd_sc_hd__mux4_1 (80)
+sky130_fd_sc_hd__nor3_1 (46) |sky130_fd_sc_hd__nor3_1 (46)
+sky130_fd_sc_hd__nor2_2 (27) |sky130_fd_sc_hd__nor2_2 (27)
+sky130_fd_sc_hd__or2_1 (215) |sky130_fd_sc_hd__or2_1 (215)
+sky130_fd_sc_hd__nand2_8 (27) |sky130_fd_sc_hd__nand2_8 (27)
+sky130_fd_sc_hd__a311oi_1 (44) |sky130_fd_sc_hd__a311oi_1 (44)
+sky130_fd_sc_hd__clkinv_16 (26) |sky130_fd_sc_hd__clkinv_16 (26)
+sky130_fd_sc_hd__nand3_1 (34) |sky130_fd_sc_hd__nand3_1 (34)
+sky130_fd_sc_hd__a221o_2 (38) |sky130_fd_sc_hd__a221o_2 (38)
+sky130_fd_sc_hd__a21o_4 (7) |sky130_fd_sc_hd__a21o_4 (7)
+sky130_fd_sc_hd__a2bb2o_1 (77) |sky130_fd_sc_hd__a2bb2o_1 (77)
+sky130_fd_sc_hd__a21boi_1 (18) |sky130_fd_sc_hd__a21boi_1 (18)
+sky130_fd_sc_hd__nand2_2 (27) |sky130_fd_sc_hd__nand2_2 (27)
+sky130_fd_sc_hd__a21oi_2 (18) |sky130_fd_sc_hd__a21oi_2 (18)
+sky130_fd_sc_hd__o21bai_1 (11) |sky130_fd_sc_hd__o21bai_1 (11)
+sky130_fd_sc_hd__and3_2 (38) |sky130_fd_sc_hd__and3_2 (38)
+sky130_fd_sc_hd__a21oi_1 (305) |sky130_fd_sc_hd__a21oi_1 (305)
+sky130_fd_sc_hd__or4bb_1 (9) |sky130_fd_sc_hd__or4bb_1 (9)
+sky130_fd_sc_hd__a221oi_4 (17) |sky130_fd_sc_hd__a221oi_4 (17)
+sky130_fd_sc_hd__mux2_4 (11) |sky130_fd_sc_hd__mux2_4 (11)
+sky130_fd_sc_hd__clkinv_4 (27) |sky130_fd_sc_hd__clkinv_4 (27)
+sky130_fd_sc_hd__clkbuf_4 (48) |sky130_fd_sc_hd__clkbuf_4 (48)
+sky130_fd_sc_hd__o211ai_1 (20) |sky130_fd_sc_hd__o211ai_1 (20)
+sky130_fd_sc_hd__nor2_4 (16) |sky130_fd_sc_hd__nor2_4 (16)
+sky130_fd_sc_hd__a21oi_4 (36) |sky130_fd_sc_hd__a21oi_4 (36)
+sky130_fd_sc_hd__o2111ai_1 (29) |sky130_fd_sc_hd__o2111ai_1 (29)
+sky130_fd_sc_hd__nand2b_1 (66) |sky130_fd_sc_hd__nand2b_1 (66)
+sky130_fd_sc_hd__or4bb_4 (11) |sky130_fd_sc_hd__or4bb_4 (11)
+sky130_fd_sc_hd__and2_2 (8) |sky130_fd_sc_hd__and2_2 (8)
+sky130_fd_sc_hd__and4b_4 (37) |sky130_fd_sc_hd__and4b_4 (37)
+sky130_fd_sc_hd__o2111a_1 (85) |sky130_fd_sc_hd__o2111a_1 (85)
+sky130_fd_sc_hd__a2bb2o_4 (7) |sky130_fd_sc_hd__a2bb2o_4 (7)
+sky130_fd_sc_hd__and4bb_1 (22) |sky130_fd_sc_hd__and4bb_1 (22)
+sky130_fd_sc_hd__xnor2_1 (33) |sky130_fd_sc_hd__xnor2_1 (33)
+sky130_fd_sc_hd__and4_2 (22) |sky130_fd_sc_hd__and4_2 (22)
+sky130_fd_sc_hd__nand4_2 (14) |sky130_fd_sc_hd__nand4_2 (14)
+sky130_fd_sc_hd__clkbuf_1 (134) |sky130_fd_sc_hd__clkbuf_1 (134)
+sky130_fd_sc_hd__o22a_4 (5) |sky130_fd_sc_hd__o22a_4 (5)
+sky130_fd_sc_hd__clkbuf_2 (26) |sky130_fd_sc_hd__clkbuf_2 (26)
+sky130_fd_sc_hd__dlymetal6s2s_1 (5) |sky130_fd_sc_hd__dlymetal6s2s_1 (5)
+sky130_fd_sc_hd__buf_2 (13) |sky130_fd_sc_hd__buf_2 (13)
+sky130_fd_sc_hd__xor2_1 (39) |sky130_fd_sc_hd__xor2_1 (39)
+sky130_fd_sc_hd__and4_4 (45) |sky130_fd_sc_hd__and4_4 (45)
+sky130_fd_sc_hd__o32a_1 (27) |sky130_fd_sc_hd__o32a_1 (27)
+sky130_fd_sc_hd__or4b_2 (16) |sky130_fd_sc_hd__or4b_2 (16)
+sky130_fd_sc_hd__a22oi_2 (13) |sky130_fd_sc_hd__a22oi_2 (13)
+sky130_fd_sc_hd__and2_4 (15) |sky130_fd_sc_hd__and2_4 (15)
+sky130_fd_sc_hd__nand4_4 (21) |sky130_fd_sc_hd__nand4_4 (21)
+sky130_fd_sc_hd__a2111o_2 (4) |sky130_fd_sc_hd__a2111o_2 (4)
+sky130_fd_sc_hd__o2bb2a_1 (53) |sky130_fd_sc_hd__o2bb2a_1 (53)
+sky130_fd_sc_hd__and4b_2 (8) |sky130_fd_sc_hd__and4b_2 (8)
+sky130_fd_sc_hd__and3b_1 (67) |sky130_fd_sc_hd__and3b_1 (67)
+sky130_fd_sc_hd__a2111oi_1 (7) |sky130_fd_sc_hd__a2111oi_1 (7)
+sky130_fd_sc_hd__o2111ai_4 (10) |sky130_fd_sc_hd__o2111ai_4 (10)
+sky130_fd_sc_hd__o22ai_4 (7) |sky130_fd_sc_hd__o22ai_4 (7)
+sky130_fd_sc_hd__a211o_2 (17) |sky130_fd_sc_hd__a211o_2 (17)
+sky130_fd_sc_hd__a32oi_4 (4) |sky130_fd_sc_hd__a32oi_4 (4)
+sky130_fd_sc_hd__and2b_4 (11) |sky130_fd_sc_hd__and2b_4 (11)
+sky130_fd_sc_hd__clkinv_2 (28) |sky130_fd_sc_hd__clkinv_2 (28)
+sky130_fd_sc_hd__conb_1 (11) |sky130_fd_sc_hd__conb_1 (11)
+sky130_fd_sc_hd__o2bb2ai_2 (2) |sky130_fd_sc_hd__o2bb2ai_2 (2)
+sky130_fd_sc_hd__or3b_2 (8) |sky130_fd_sc_hd__or3b_2 (8)
+sky130_fd_sc_hd__or3b_4 (28) |sky130_fd_sc_hd__or3b_4 (28)
+sky130_fd_sc_hd__a22oi_1 (20) |sky130_fd_sc_hd__a22oi_1 (20)
+sky130_fd_sc_hd__o31a_2 (14) |sky130_fd_sc_hd__o31a_2 (14)
+sky130_fd_sc_hd__or2_4 (27) |sky130_fd_sc_hd__or2_4 (27)
+sky130_fd_sc_hd__a21o_2 (6) |sky130_fd_sc_hd__a21o_2 (6)
+sky130_fd_sc_hd__a31o_2 (14) |sky130_fd_sc_hd__a31o_2 (14)
+sky130_fd_sc_hd__and4bb_4 (20) |sky130_fd_sc_hd__and4bb_4 (20)
+sky130_fd_sc_hd__o41ai_1 (6) |sky130_fd_sc_hd__o41ai_1 (6)
+sky130_fd_sc_hd__o21ba_2 (3) |sky130_fd_sc_hd__o21ba_2 (3)
+sky130_fd_sc_hd__nor3_2 (10) |sky130_fd_sc_hd__nor3_2 (10)
+sky130_fd_sc_hd__a32o_2 (7) |sky130_fd_sc_hd__a32o_2 (7)
+sky130_fd_sc_hd__a32o_4 (9) |sky130_fd_sc_hd__a32o_4 (9)
+sky130_fd_sc_hd__o21ai_2 (33) |sky130_fd_sc_hd__o21ai_2 (33)
+sky130_fd_sc_hd__or2_2 (7) |sky130_fd_sc_hd__or2_2 (7)
+sky130_fd_sc_hd__nand3_2 (11) |sky130_fd_sc_hd__nand3_2 (11)
+sky130_fd_sc_hd__o211ai_4 (12) |sky130_fd_sc_hd__o211ai_4 (12)
+sky130_fd_sc_hd__o311ai_1 (4) |sky130_fd_sc_hd__o311ai_1 (4)
+sky130_fd_sc_hd__nor4b_1 (2) |sky130_fd_sc_hd__nor4b_1 (2)
+sky130_fd_sc_hd__o31ai_1 (16) |sky130_fd_sc_hd__o31ai_1 (16)
+sky130_fd_sc_hd__nor4_2 (14) |sky130_fd_sc_hd__nor4_2 (14)
+sky130_fd_sc_hd__o22ai_1 (6) |sky130_fd_sc_hd__o22ai_1 (6)
+sky130_fd_sc_hd__nand2_4 (16) |sky130_fd_sc_hd__nand2_4 (16)
+sky130_fd_sc_hd__o21bai_4 (2) |sky130_fd_sc_hd__o21bai_4 (2)
+sky130_fd_sc_hd__a211oi_1 (49) |sky130_fd_sc_hd__a211oi_1 (49)
+sky130_fd_sc_hd__inv_4 (13) |sky130_fd_sc_hd__inv_4 (13)
+sky130_fd_sc_hd__mux2_8 (7) |sky130_fd_sc_hd__mux2_8 (7)
+sky130_fd_sc_hd__inv_6 (9) |sky130_fd_sc_hd__inv_6 (9)
+sky130_fd_sc_hd__a22oi_4 (21) |sky130_fd_sc_hd__a22oi_4 (21)
+sky130_fd_sc_hd__nor2_8 (34) |sky130_fd_sc_hd__nor2_8 (34)
+sky130_fd_sc_hd__nor4_4 (13) |sky130_fd_sc_hd__nor4_4 (13)
+sky130_fd_sc_hd__a41o_2 (6) |sky130_fd_sc_hd__a41o_2 (6)
+sky130_fd_sc_hd__mux2_2 (18) |sky130_fd_sc_hd__mux2_2 (18)
+sky130_fd_sc_hd__nand2b_2 (4) |sky130_fd_sc_hd__nand2b_2 (4)
+sky130_fd_sc_hd__o221ai_4 (12) |sky130_fd_sc_hd__o221ai_4 (12)
+sky130_fd_sc_hd__a211o_4 (12) |sky130_fd_sc_hd__a211o_4 (12)
+sky130_fd_sc_hd__o2bb2a_2 (8) |sky130_fd_sc_hd__o2bb2a_2 (8)
+sky130_fd_sc_hd__nand2b_4 (17) |sky130_fd_sc_hd__nand2b_4 (17)
+sky130_fd_sc_hd__o21a_2 (5) |sky130_fd_sc_hd__o21a_2 (5)
+sky130_fd_sc_hd__o2111ai_2 (3) |sky130_fd_sc_hd__o2111ai_2 (3)
+sky130_fd_sc_hd__a311o_2 (8) |sky130_fd_sc_hd__a311o_2 (8)
+sky130_fd_sc_hd__a221oi_1 (7) |sky130_fd_sc_hd__a221oi_1 (7)
+sky130_fd_sc_hd__o41a_4 (14) |sky130_fd_sc_hd__o41a_4 (14)
+sky130_fd_sc_hd__nand4b_2 (1) |sky130_fd_sc_hd__nand4b_2 (1)
+sky130_fd_sc_hd__o2bb2ai_1 (13) |sky130_fd_sc_hd__o2bb2ai_1 (13)
+sky130_fd_sc_hd__o31a_4 (8) |sky130_fd_sc_hd__o31a_4 (8)
+sky130_fd_sc_hd__xor2_4 (9) |sky130_fd_sc_hd__xor2_4 (9)
+sky130_fd_sc_hd__a2bb2o_2 (5) |sky130_fd_sc_hd__a2bb2o_2 (5)
+sky130_fd_sc_hd__nor3_4 (10) |sky130_fd_sc_hd__nor3_4 (10)
+sky130_fd_sc_hd__o211ai_2 (5) |sky130_fd_sc_hd__o211ai_2 (5)
+sky130_fd_sc_hd__o311ai_4 (5) |sky130_fd_sc_hd__o311ai_4 (5)
+sky130_fd_sc_hd__o211a_2 (13) |sky130_fd_sc_hd__o211a_2 (13)
+sky130_fd_sc_hd__nand3b_1 (16) |sky130_fd_sc_hd__nand3b_1 (16)
+sky130_fd_sc_hd__o22a_2 (5) |sky130_fd_sc_hd__o22a_2 (5)
+sky130_fd_sc_hd__a2bb2oi_4 (1) |sky130_fd_sc_hd__a2bb2oi_4 (1)
+sky130_fd_sc_hd__and2b_2 (3) |sky130_fd_sc_hd__and2b_2 (3)
+sky130_fd_sc_hd__o21a_4 (14) |sky130_fd_sc_hd__o21a_4 (14)
+sky130_fd_sc_hd__a2bb2oi_2 (1) |sky130_fd_sc_hd__a2bb2oi_2 (1)
+sky130_fd_sc_hd__o311a_2 (5) |sky130_fd_sc_hd__o311a_2 (5)
+sky130_fd_sc_hd__o221ai_1 (8) |sky130_fd_sc_hd__o221ai_1 (8)
+sky130_fd_sc_hd__and4bb_2 (4) |sky130_fd_sc_hd__and4bb_2 (4)
+sky130_fd_sc_hd__inv_12 (2) |sky130_fd_sc_hd__inv_12 (2)
+sky130_fd_sc_hd__o211a_4 (9) |sky130_fd_sc_hd__o211a_4 (9)
+sky130_fd_sc_hd__o311a_4 (1) |sky130_fd_sc_hd__o311a_4 (1)
+sky130_fd_sc_hd__a41oi_2 (1) |sky130_fd_sc_hd__a41oi_2 (1)
+sky130_fd_sc_hd__nand4b_4 (3) |sky130_fd_sc_hd__nand4b_4 (3)
+sky130_fd_sc_hd__xor2_2 (7) |sky130_fd_sc_hd__xor2_2 (7)
+sky130_fd_sc_hd__a2111o_4 (4) |sky130_fd_sc_hd__a2111o_4 (4)
+sky130_fd_sc_hd__o41a_2 (6) |sky130_fd_sc_hd__o41a_2 (6)
+sky130_fd_sc_hd__o221a_2 (1) |sky130_fd_sc_hd__o221a_2 (1)
+sky130_fd_sc_hd__and3b_2 (2) |sky130_fd_sc_hd__and3b_2 (2)
+sky130_fd_sc_hd__a2bb2oi_1 (3) |sky130_fd_sc_hd__a2bb2oi_1 (3)
+sky130_fd_sc_hd__nor3b_2 (3) |sky130_fd_sc_hd__nor3b_2 (3)
+sky130_fd_sc_hd__nor4b_4 (4) |sky130_fd_sc_hd__nor4b_4 (4)
+sky130_fd_sc_hd__o32ai_1 (2) |sky130_fd_sc_hd__o32ai_1 (2)
+sky130_fd_sc_hd__inv_8 (4) |sky130_fd_sc_hd__inv_8 (4)
+sky130_fd_sc_hd__nand3b_4 (5) |sky130_fd_sc_hd__nand3b_4 (5)
+sky130_fd_sc_hd__nor3b_4 (2) |sky130_fd_sc_hd__nor3b_4 (2)
+RAM128 (1) |RAM128 (1)
+sky130_fd_sc_hd__nand3_4 (5) |sky130_fd_sc_hd__nand3_4 (5)
+sky130_fd_sc_hd__xnor2_4 (2) |sky130_fd_sc_hd__xnor2_4 (2)
+sky130_fd_sc_hd__a2111oi_4 (1) |sky130_fd_sc_hd__a2111oi_4 (1)
+sky130_fd_sc_hd__a311o_4 (3) |sky130_fd_sc_hd__a311o_4 (3)
+sky130_fd_sc_hd__a221oi_2 (6) |sky130_fd_sc_hd__a221oi_2 (6)
+sky130_fd_sc_hd__o22ai_2 (2) |sky130_fd_sc_hd__o22ai_2 (2)
+sky130_fd_sc_hd__a31oi_2 (4) |sky130_fd_sc_hd__a31oi_2 (4)
+sky130_fd_sc_hd__o2111a_2 (2) |sky130_fd_sc_hd__o2111a_2 (2)
+sky130_fd_sc_hd__clkinv_8 (6) |sky130_fd_sc_hd__clkinv_8 (6)
+sky130_fd_sc_hd__xnor2_2 (3) |sky130_fd_sc_hd__xnor2_2 (3)
+sky130_fd_sc_hd__o41ai_2 (1) |sky130_fd_sc_hd__o41ai_2 (1)
+sky130_fd_sc_hd__o31ai_4 (5) |sky130_fd_sc_hd__o31ai_4 (5)
+sky130_fd_sc_hd__nor4b_2 (1) |sky130_fd_sc_hd__nor4b_2 (1)
+sky130_fd_sc_hd__o31ai_2 (4) |sky130_fd_sc_hd__o31ai_2 (4)
+sky130_fd_sc_hd__o2111a_4 (3) |sky130_fd_sc_hd__o2111a_4 (3)
+sky130_fd_sc_hd__o2bb2a_4 (3) |sky130_fd_sc_hd__o2bb2a_4 (3)
+sky130_fd_sc_hd__a41o_4 (2) |sky130_fd_sc_hd__a41o_4 (2)
+sky130_fd_sc_hd__a32oi_2 (1) |sky130_fd_sc_hd__a32oi_2 (1)
+sky130_fd_sc_hd__a32oi_1 (2) |sky130_fd_sc_hd__a32oi_1 (2)
+sky130_fd_sc_hd__a21boi_2 (1) |sky130_fd_sc_hd__a21boi_2 (1)
+sky130_fd_sc_hd__nand3b_2 (7) |sky130_fd_sc_hd__nand3b_2 (7)
+RAM256 (1) |RAM256 (1)
+sky130_fd_sc_hd__o21bai_2 (1) |sky130_fd_sc_hd__o21bai_2 (1)
+sky130_fd_sc_hd__o2bb2ai_4 (1) |sky130_fd_sc_hd__o2bb2ai_4 (1)
+sky130_fd_sc_hd__o311ai_2 (3) |sky130_fd_sc_hd__o311ai_2 (3)
+sky130_fd_sc_hd__a2111oi_2 (3) |sky130_fd_sc_hd__a2111oi_2 (3)
+sky130_fd_sc_hd__nand4b_1 (1) |sky130_fd_sc_hd__nand4b_1 (1)
+sky130_fd_sc_hd__nor3b_1 (4) |sky130_fd_sc_hd__nor3b_1 (4)
+sky130_fd_sc_hd__a41oi_1 (1) |sky130_fd_sc_hd__a41oi_1 (1)
+sky130_fd_sc_hd__a311oi_2 (1) |sky130_fd_sc_hd__a311oi_2 (1)
+sky130_fd_sc_hd__o32ai_4 (1) |sky130_fd_sc_hd__o32ai_4 (1)
+sky130_fd_sc_hd__a41oi_4 (1) |sky130_fd_sc_hd__a41oi_4 (1)
+Number of devices: 29797 |Number of devices: 29797
+Number of nets: 25043 |Number of nets: 25043
+---------------------------------------------------------------------------------------
+Resolving automorphisms by property value.
+Resolving automorphisms by pin name.
+Netlists match uniquely.
+
+Subcircuit pins:
+Circuit 1: mgmt_core_wrapper |Circuit 2: mgmt_core_wrapper
+-------------------------------------------|-------------------------------------------
+flash_io3_oeb |flash_io3_oeb
+flash_io2_oeb |flash_io2_oeb
+flash_io1_oeb |flash_io1_oeb
+mprj_adr_o[0] |mprj_adr_o[0]
+flash_io3_do |flash_io3_do
+flash_io2_do |flash_io2_do
+flash_io1_do |flash_io1_do
+debug_out |debug_out
+trap |trap
+qspi_enabled |qspi_enabled
+mprj_adr_o[1] |mprj_adr_o[1]
+mprj_we_o |mprj_we_o
+mprj_adr_o[29] |mprj_adr_o[29]
+mprj_adr_o[9] |mprj_adr_o[9]
+mprj_adr_o[27] |mprj_adr_o[27]
+mprj_adr_o[7] |mprj_adr_o[7]
+mprj_adr_o[31] |mprj_adr_o[31]
+mprj_adr_o[30] |mprj_adr_o[30]
+mprj_adr_o[28] |mprj_adr_o[28]
+mprj_adr_o[25] |mprj_adr_o[25]
+mprj_adr_o[5] |mprj_adr_o[5]
+mprj_adr_o[21] |mprj_adr_o[21]
+mprj_adr_o[16] |mprj_adr_o[16]
+mprj_adr_o[15] |mprj_adr_o[15]
+mprj_adr_o[14] |mprj_adr_o[14]
+mprj_adr_o[3] |mprj_adr_o[3]
+mprj_adr_o[2] |mprj_adr_o[2]
+mprj_adr_o[13] |mprj_adr_o[13]
+mprj_adr_o[4] |mprj_adr_o[4]
+mprj_adr_o[20] |mprj_adr_o[20]
+mprj_adr_o[12] |mprj_adr_o[12]
+mprj_adr_o[11] |mprj_adr_o[11]
+mprj_dat_o[22] |mprj_dat_o[22]
+la_output[91] |la_output[91]
+mprj_dat_o[31] |mprj_dat_o[31]
+mprj_dat_o[21] |mprj_dat_o[21]
+mprj_adr_o[10] |mprj_adr_o[10]
+la_output[90] |la_output[90]
+mprj_dat_o[30] |mprj_dat_o[30]
+mprj_dat_o[10] |mprj_dat_o[10]
+la_output[9] |la_output[9]
+la_output[89] |la_output[89]
+mprj_dat_o[29] |mprj_dat_o[29]
+mprj_dat_o[19] |mprj_dat_o[19]
+mprj_adr_o[18] |mprj_adr_o[18]
+mprj_dat_o[9] |mprj_dat_o[9]
+mprj_dat_o[18] |mprj_dat_o[18]
+mprj_dat_o[17] |mprj_dat_o[17]
+mprj_dat_o[26] |mprj_dat_o[26]
+mprj_dat_o[16] |mprj_dat_o[16]
+mprj_dat_o[15] |mprj_dat_o[15]
+mprj_dat_o[24] |mprj_dat_o[24]
+mprj_dat_o[14] |mprj_dat_o[14]
+spi_csb |spi_csb
+mprj_dat_o[23] |mprj_dat_o[23]
+la_output[23] |la_output[23]
+la_output[69] |la_output[69]
+la_output[29] |la_output[29]
+la_output[19] |la_output[19]
+la_output[78] |la_output[78]
+la_output[48] |la_output[48]
+la_output[88] |la_output[88]
+la_output[87] |la_output[87]
+la_output[67] |la_output[67]
+la_output[17] |la_output[17]
+la_output[26] |la_output[26]
+la_output[16] |la_output[16]
+la_output[85] |la_output[85]
+la_output[66] |la_output[66]
+la_output[65] |la_output[65]
+la_output[84] |la_output[84]
+la_output[64] |la_output[64]
+la_output[54] |la_output[54]
+la_output[24] |la_output[24]
+la_output[83] |la_output[83]
+la_output[75] |la_output[75]
+la_output[73] |la_output[73]
+la_output[63] |la_output[63]
+la_output[82] |la_output[82]
+la_output[77] |la_output[77]
+la_output[74] |la_output[74]
+la_output[72] |la_output[72]
+la_output[71] |la_output[71]
+la_output[70] |la_output[70]
+la_output[81] |la_output[81]
+la_output[79] |la_output[79]
+la_output[93] |la_output[93]
+la_output[92] |la_output[92]
+hk_stb_o |hk_stb_o
+la_iena[12] |la_iena[12]
+ser_tx |ser_tx
+mprj_cyc_o |mprj_cyc_o
+rstb_l_out |rstb_l_out
+spi_sck |spi_sck
+mprj_stb_o |mprj_stb_o
+mprj_sel_o[3] |mprj_sel_o[3]
+mprj_sel_o[1] |mprj_sel_o[1]
+mprj_sel_o[0] |mprj_sel_o[0]
+serial_clock_out |serial_clock_out
+serial_resetn_out |serial_resetn_out
+serial_load_out |serial_load_out
+serial_data_2_out |serial_data_2_out
+la_oenb[86] |la_oenb[86]
+la_oenb[121] |la_oenb[121]
+la_oenb[10] |la_oenb[10]
+flash_clk |flash_clk
+hk_cyc_o |hk_cyc_o
+la_oenb[49] |la_oenb[49]
+la_oenb[15] |la_oenb[15]
+la_oenb[12] |la_oenb[12]
+gpio_outenb_pad |gpio_outenb_pad
+gpio_inenb_pad |gpio_inenb_pad
+la_oenb[90] |la_oenb[90]
+la_oenb[88] |la_oenb[88]
+la_oenb[85] |la_oenb[85]
+la_oenb[59] |la_oenb[59]
+la_oenb[54] |la_oenb[54]
+la_oenb[45] |la_oenb[45]
+la_oenb[39] |la_oenb[39]
+la_oenb[38] |la_oenb[38]
+la_oenb[13] |la_oenb[13]
+la_iena[35] |la_iena[35]
+la_iena[13] |la_iena[13]
+la_oenb[94] |la_oenb[94]
+la_oenb[55] |la_oenb[55]
+la_oenb[44] |la_oenb[44]
+la_iena[8] |la_iena[8]
+la_iena[36] |la_iena[36]
+la_iena[25] |la_iena[25]
+la_iena[14] |la_iena[14]
+la_oenb[93] |la_oenb[93]
+la_oenb[91] |la_oenb[91]
+la_oenb[87] |la_oenb[87]
+la_oenb[78] |la_oenb[78]
+la_oenb[32] |la_oenb[32]
+la_iena[86] |la_iena[86]
+la_oenb[73] |la_oenb[73]
+la_oenb[41] |la_oenb[41]
+la_oenb[25] |la_oenb[25]
+la_iena[15] |la_iena[15]
+la_oenb[8] |la_oenb[8]
+la_oenb[61] |la_oenb[61]
+la_oenb[58] |la_oenb[58]
+la_oenb[56] |la_oenb[56]
+la_oenb[53] |la_oenb[53]
+la_oenb[51] |la_oenb[51]
+la_oenb[52] |la_oenb[52]
+la_oenb[50] |la_oenb[50]
+la_oenb[43] |la_oenb[43]
+la_oenb[35] |la_oenb[35]
+la_oenb[37] |la_oenb[37]
+la_oenb[34] |la_oenb[34]
+la_oenb[33] |la_oenb[33]
+la_oenb[14] |la_oenb[14]
+la_iena[32] |la_iena[32]
+mprj_dat_o[12] |mprj_dat_o[12]
+mprj_adr_o[22] |mprj_adr_o[22]
+la_output[111] |la_output[111]
+la_output[101] |la_output[101]
+mprj_dat_o[11] |mprj_dat_o[11]
+la_output[110] |la_output[110]
+la_output[100] |la_output[100]
+mprj_sel_o[2] |mprj_sel_o[2]
+mprj_dat_o[20] |mprj_dat_o[20]
+la_output[8] |la_output[8]
+la_output[10] |la_output[10]
+la_output[0] |la_output[0]
+mprj_dat_o[2] |mprj_dat_o[2]
+mprj_dat_o[1] |mprj_dat_o[1]
+mprj_dat_o[0] |mprj_dat_o[0]
+mprj_adr_o[19] |mprj_adr_o[19]
+la_output[99] |la_output[99]
+la_output[109] |la_output[109]
+user_irq_ena[0] |user_irq_ena[0]
+la_output[98] |la_output[98]
+la_output[108] |la_output[108]
+mprj_dat_o[28] |mprj_dat_o[28]
+mprj_adr_o[17] |mprj_adr_o[17]
+la_output[97] |la_output[97]
+la_output[107] |la_output[107]
+mprj_dat_o[8] |mprj_dat_o[8]
+mprj_dat_o[27] |mprj_dat_o[27]
+mprj_adr_o[8] |mprj_adr_o[8]
+la_output[106] |la_output[106]
+spi_sdo |spi_sdo
+mprj_dat_o[7] |mprj_dat_o[7]
+mprj_adr_o[26] |mprj_adr_o[26]
+la_output[105] |la_output[105]
+mprj_dat_o[6] |mprj_dat_o[6]
+mprj_dat_o[25] |mprj_dat_o[25]
+mprj_adr_o[6] |mprj_adr_o[6]
+la_output[104] |la_output[104]
+spi_enabled |spi_enabled
+mprj_dat_o[5] |mprj_dat_o[5]
+la_output[103] |la_output[103]
+mprj_wb_iena |mprj_wb_iena
+mprj_dat_o[4] |mprj_dat_o[4]
+mprj_dat_o[3] |mprj_dat_o[3]
+la_output[120] |la_output[120]
+la_output[14] |la_output[14]
+la_output[11] |la_output[11]
+la_output[13] |la_output[13]
+la_output[119] |la_output[119]
+la_output[32] |la_output[32]
+la_output[22] |la_output[22]
+la_output[12] |la_output[12]
+la_output[118] |la_output[118]
+la_output[41] |la_output[41]
+la_output[31] |la_output[31]
+la_output[21] |la_output[21]
+la_output[127] |la_output[127]
+la_output[117] |la_output[117]
+la_output[50] |la_output[50]
+la_output[30] |la_output[30]
+la_output[20] |la_output[20]
+la_output[126] |la_output[126]
+la_output[5] |la_output[5]
+la_output[4] |la_output[4]
+la_output[3] |la_output[3]
+la_output[2] |la_output[2]
+la_output[1] |la_output[1]
+la_output[125] |la_output[125]
+la_output[115] |la_output[115]
+la_output[49] |la_output[49]
+la_output[39] |la_output[39]
+la_output[124] |la_output[124]
+la_output[116] |la_output[116]
+la_output[114] |la_output[114]
+la_output[58] |la_output[58]
+la_output[38] |la_output[38]
+la_output[18] |la_output[18]
+la_output[123] |la_output[123]
+la_output[113] |la_output[113]
+la_output[57] |la_output[57]
+la_output[47] |la_output[47]
+la_output[37] |la_output[37]
+la_output[27] |la_output[27]
+la_output[122] |la_output[122]
+la_output[112] |la_output[112]
+la_output[86] |la_output[86]
+la_output[76] |la_output[76]
+la_output[68] |la_output[68]
+la_output[59] |la_output[59]
+la_output[56] |la_output[56]
+la_output[46] |la_output[46]
+la_output[36] |la_output[36]
+la_output[121] |la_output[121]
+la_output[55] |la_output[55]
+la_output[45] |la_output[45]
+la_output[35] |la_output[35]
+la_output[28] |la_output[28]
+la_output[25] |la_output[25]
+la_output[15] |la_output[15]
+la_output[44] |la_output[44]
+la_output[34] |la_output[34]
+user_irq_ena[2] |user_irq_ena[2]
+user_irq_ena[1] |user_irq_ena[1]
+la_output[53] |la_output[53]
+la_output[43] |la_output[43]
+la_output[33] |la_output[33]
+la_output[62] |la_output[62]
+la_output[52] |la_output[52]
+la_output[42] |la_output[42]
+la_output[40] |la_output[40]
+la_output[61] |la_output[61]
+la_output[51] |la_output[51]
+debug_oeb |debug_oeb
+la_output[80] |la_output[80]
+la_output[60] |la_output[60]
+debug_mode |debug_mode
+la_output[7] |la_output[7]
+la_output[6] |la_output[6]
+gpio_out_pad |gpio_out_pad
+gpio_mode1_pad |gpio_mode1_pad
+la_output[96] |la_output[96]
+gpio_mode0_pad |gpio_mode0_pad
+la_output[95] |la_output[95]
+la_output[94] |la_output[94]
+mprj_adr_o[24] |mprj_adr_o[24]
+mprj_dat_o[13] |mprj_dat_o[13]
+mprj_adr_o[23] |mprj_adr_o[23]
+la_output[102] |la_output[102]
+uart_enabled |uart_enabled
+porb_h_out |porb_h_out
+por_l_out |por_l_out
+resetn_out |resetn_out
+clk_out |clk_out
+flash_io0_oeb |flash_io0_oeb
+flash_io0_do |flash_io0_do
+la_oenb[99] |la_oenb[99]
+la_oenb[98] |la_oenb[98]
+la_oenb[97] |la_oenb[97]
+la_oenb[96] |la_oenb[96]
+la_oenb[95] |la_oenb[95]
+la_oenb[7] |la_oenb[7]
+la_oenb[71] |la_oenb[71]
+la_oenb[70] |la_oenb[70]
+la_oenb[6] |la_oenb[6]
+la_oenb[66] |la_oenb[66]
+la_oenb[60] |la_oenb[60]
+la_oenb[5] |la_oenb[5]
+la_oenb[57] |la_oenb[57]
+la_oenb[4] |la_oenb[4]
+la_oenb[42] |la_oenb[42]
+la_oenb[40] |la_oenb[40]
+la_oenb[46] |la_oenb[46]
+la_oenb[3] |la_oenb[3]
+la_oenb[31] |la_oenb[31]
+la_oenb[30] |la_oenb[30]
+la_oenb[2] |la_oenb[2]
+la_oenb[28] |la_oenb[28]
+la_oenb[22] |la_oenb[22]
+la_oenb[1] |la_oenb[1]
+la_oenb[16] |la_oenb[16]
+la_oenb[127] |la_oenb[127]
+la_oenb[126] |la_oenb[126]
+la_oenb[125] |la_oenb[125]
+la_oenb[124] |la_oenb[124]
+la_oenb[123] |la_oenb[123]
+la_oenb[122] |la_oenb[122]
+la_oenb[120] |la_oenb[120]
+la_oenb[119] |la_oenb[119]
+la_oenb[117] |la_oenb[117]
+la_oenb[116] |la_oenb[116]
+la_oenb[115] |la_oenb[115]
+la_oenb[114] |la_oenb[114]
+la_oenb[113] |la_oenb[113]
+la_oenb[111] |la_oenb[111]
+la_oenb[110] |la_oenb[110]
+la_oenb[109] |la_oenb[109]
+la_oenb[107] |la_oenb[107]
+la_oenb[106] |la_oenb[106]
+la_oenb[105] |la_oenb[105]
+la_oenb[104] |la_oenb[104]
+la_oenb[103] |la_oenb[103]
+la_oenb[102] |la_oenb[102]
+la_oenb[101] |la_oenb[101]
+la_oenb[100] |la_oenb[100]
+la_oenb[0] |la_oenb[0]
+la_iena[9] |la_iena[9]
+la_iena[99] |la_iena[99]
+la_iena[98] |la_iena[98]
+la_iena[97] |la_iena[97]
+la_iena[96] |la_iena[96]
+la_iena[7] |la_iena[7]
+la_iena[6] |la_iena[6]
+la_iena[61] |la_iena[61]
+la_iena[60] |la_iena[60]
+la_iena[5] |la_iena[5]
+la_iena[59] |la_iena[59]
+la_iena[58] |la_iena[58]
+la_iena[57] |la_iena[57]
+la_iena[56] |la_iena[56]
+la_iena[55] |la_iena[55]
+la_iena[53] |la_iena[53]
+la_iena[52] |la_iena[52]
+la_iena[51] |la_iena[51]
+la_iena[50] |la_iena[50]
+la_iena[4] |la_iena[4]
+la_iena[47] |la_iena[47]
+la_iena[45] |la_iena[45]
+la_iena[44] |la_iena[44]
+la_iena[43] |la_iena[43]
+la_iena[42] |la_iena[42]
+la_iena[49] |la_iena[49]
+la_iena[41] |la_iena[41]
+la_iena[39] |la_iena[39]
+la_iena[38] |la_iena[38]
+la_iena[37] |la_iena[37]
+la_iena[34] |la_iena[34]
+la_iena[33] |la_iena[33]
+la_iena[31] |la_iena[31]
+la_iena[30] |la_iena[30]
+la_iena[3] |la_iena[3]
+la_iena[2] |la_iena[2]
+la_iena[29] |la_iena[29]
+la_iena[28] |la_iena[28]
+la_iena[22] |la_iena[22]
+la_iena[1] |la_iena[1]
+la_iena[127] |la_iena[127]
+la_iena[126] |la_iena[126]
+la_iena[125] |la_iena[125]
+la_iena[124] |la_iena[124]
+la_iena[123] |la_iena[123]
+la_iena[122] |la_iena[122]
+la_iena[121] |la_iena[121]
+la_iena[120] |la_iena[120]
+la_iena[11] |la_iena[11]
+la_iena[119] |la_iena[119]
+la_iena[117] |la_iena[117]
+la_iena[116] |la_iena[116]
+la_iena[115] |la_iena[115]
+la_iena[114] |la_iena[114]
+la_iena[113] |la_iena[113]
+la_iena[111] |la_iena[111]
+la_iena[110] |la_iena[110]
+la_iena[10] |la_iena[10]
+la_iena[109] |la_iena[109]
+la_iena[107] |la_iena[107]
+la_iena[106] |la_iena[106]
+la_iena[105] |la_iena[105]
+la_iena[104] |la_iena[104]
+la_iena[103] |la_iena[103]
+la_iena[102] |la_iena[102]
+la_iena[101] |la_iena[101]
+la_iena[100] |la_iena[100]
+la_iena[0] |la_iena[0]
+flash_csb |flash_csb
+spi_sdoenb |spi_sdoenb
+la_oenb[9] |la_oenb[9]
+la_oenb[92] |la_oenb[92]
+la_oenb[89] |la_oenb[89]
+la_oenb[84] |la_oenb[84]
+la_oenb[83] |la_oenb[83]
+la_oenb[82] |la_oenb[82]
+la_oenb[81] |la_oenb[81]
+la_oenb[80] |la_oenb[80]
+la_oenb[79] |la_oenb[79]
+la_oenb[77] |la_oenb[77]
+la_oenb[76] |la_oenb[76]
+la_oenb[75] |la_oenb[75]
+la_oenb[74] |la_oenb[74]
+la_oenb[72] |la_oenb[72]
+la_oenb[69] |la_oenb[69]
+la_oenb[68] |la_oenb[68]
+la_oenb[67] |la_oenb[67]
+la_oenb[65] |la_oenb[65]
+la_oenb[64] |la_oenb[64]
+la_oenb[63] |la_oenb[63]
+la_oenb[62] |la_oenb[62]
+la_oenb[48] |la_oenb[48]
+la_oenb[47] |la_oenb[47]
+la_oenb[36] |la_oenb[36]
+la_oenb[29] |la_oenb[29]
+la_oenb[26] |la_oenb[26]
+la_oenb[24] |la_oenb[24]
+la_oenb[27] |la_oenb[27]
+la_oenb[23] |la_oenb[23]
+la_oenb[21] |la_oenb[21]
+la_oenb[20] |la_oenb[20]
+la_oenb[19] |la_oenb[19]
+la_oenb[18] |la_oenb[18]
+la_oenb[17] |la_oenb[17]
+la_oenb[11] |la_oenb[11]
+la_oenb[118] |la_oenb[118]
+la_oenb[112] |la_oenb[112]
+la_oenb[108] |la_oenb[108]
+la_iena[95] |la_iena[95]
+la_iena[94] |la_iena[94]
+la_iena[92] |la_iena[92]
+la_iena[93] |la_iena[93]
+la_iena[91] |la_iena[91]
+la_iena[90] |la_iena[90]
+la_iena[89] |la_iena[89]
+la_iena[88] |la_iena[88]
+la_iena[87] |la_iena[87]
+la_iena[85] |la_iena[85]
+la_iena[84] |la_iena[84]
+la_iena[83] |la_iena[83]
+la_iena[82] |la_iena[82]
+la_iena[81] |la_iena[81]
+la_iena[80] |la_iena[80]
+la_iena[79] |la_iena[79]
+la_iena[78] |la_iena[78]
+la_iena[76] |la_iena[76]
+la_iena[75] |la_iena[75]
+la_iena[73] |la_iena[73]
+la_iena[77] |la_iena[77]
+la_iena[74] |la_iena[74]
+la_iena[72] |la_iena[72]
+la_iena[71] |la_iena[71]
+la_iena[70] |la_iena[70]
+la_iena[69] |la_iena[69]
+la_iena[68] |la_iena[68]
+la_iena[67] |la_iena[67]
+la_iena[66] |la_iena[66]
+la_iena[65] |la_iena[65]
+la_iena[64] |la_iena[64]
+la_iena[63] |la_iena[63]
+la_iena[62] |la_iena[62]
+la_iena[54] |la_iena[54]
+la_iena[48] |la_iena[48]
+la_iena[46] |la_iena[46]
+la_iena[40] |la_iena[40]
+la_iena[26] |la_iena[26]
+la_iena[24] |la_iena[24]
+la_iena[23] |la_iena[23]
+la_iena[27] |la_iena[27]
+la_iena[21] |la_iena[21]
+la_iena[20] |la_iena[20]
+la_iena[18] |la_iena[18]
+la_iena[19] |la_iena[19]
+la_iena[17] |la_iena[17]
+la_iena[16] |la_iena[16]
+la_iena[118] |la_iena[118]
+la_iena[112] |la_iena[112]
+la_iena[108] |la_iena[108]
+spi_sdi |spi_sdi
+serial_resetn_in |serial_resetn_in
+serial_clock_in |serial_clock_in
+serial_load_in |serial_load_in
+serial_data_2_in |serial_data_2_in
+ser_rx |ser_rx
+por_l_in |por_l_in
+porb_h_in |porb_h_in
+mprj_dat_i[6] |mprj_dat_i[6]
+mprj_dat_i[2] |mprj_dat_i[2]
+mprj_dat_i[24] |mprj_dat_i[24]
+mprj_dat_i[4] |mprj_dat_i[4]
+mprj_dat_i[1] |mprj_dat_i[1]
+mprj_ack_i |mprj_ack_i
+mprj_dat_i[0] |mprj_dat_i[0]
+mprj_dat_i[9] |mprj_dat_i[9]
+la_input[94] |la_input[94]
+la_input[93] |la_input[93]
+mprj_dat_i[31] |mprj_dat_i[31]
+mprj_dat_i[30] |mprj_dat_i[30]
+mprj_dat_i[29] |mprj_dat_i[29]
+la_input[118] |la_input[118]
+la_input[91] |la_input[91]
+la_input[89] |la_input[89]
+la_input[87] |la_input[87]
+mprj_dat_i[16] |mprj_dat_i[16]
+irq[0] |irq[0]
+mprj_dat_i[20] |mprj_dat_i[20]
+mprj_dat_i[19] |mprj_dat_i[19]
+mprj_dat_i[10] |mprj_dat_i[10]
+mprj_dat_i[15] |mprj_dat_i[15]
+gpio_in_pad |gpio_in_pad
+mprj_dat_i[18] |mprj_dat_i[18]
+mprj_dat_i[13] |mprj_dat_i[13]
+la_input[95] |la_input[95]
+mprj_dat_i[7] |mprj_dat_i[7]
+mprj_dat_i[5] |mprj_dat_i[5]
+mprj_dat_i[3] |mprj_dat_i[3]
+mprj_dat_i[14] |mprj_dat_i[14]
+mprj_dat_i[8] |mprj_dat_i[8]
+mprj_dat_i[12] |mprj_dat_i[12]
+mprj_dat_i[11] |mprj_dat_i[11]
+la_input[92] |la_input[92]
+mprj_dat_i[28] |mprj_dat_i[28]
+mprj_dat_i[27] |mprj_dat_i[27]
+mprj_dat_i[26] |mprj_dat_i[26]
+mprj_dat_i[25] |mprj_dat_i[25]
+mprj_dat_i[23] |mprj_dat_i[23]
+mprj_dat_i[22] |mprj_dat_i[22]
+mprj_dat_i[17] |mprj_dat_i[17]
+debug_in |debug_in
+rstb_l_in |rstb_l_in
+irq[2] |irq[2]
+irq[1] |irq[1]
+core_rstn |core_rstn
+flash_io1_di |flash_io1_di
+la_input[42] |la_input[42]
+la_input[41] |la_input[41]
+la_input[40] |la_input[40]
+la_input[39] |la_input[39]
+irq[4] |irq[4]
+irq[5] |irq[5]
+irq[3] |irq[3]
+la_input[49] |la_input[49]
+la_input[70] |la_input[70]
+la_input[69] |la_input[69]
+la_input[68] |la_input[68]
+la_input[107] |la_input[107]
+la_input[56] |la_input[56]
+la_input[58] |la_input[58]
+la_input[55] |la_input[55]
+la_input[57] |la_input[57]
+la_input[66] |la_input[66]
+la_input[65] |la_input[65]
+la_input[67] |la_input[67]
+la_input[64] |la_input[64]
+la_input[63] |la_input[63]
+la_input[48] |la_input[48]
+la_input[45] |la_input[45]
+la_input[47] |la_input[47]
+la_input[46] |la_input[46]
+la_input[44] |la_input[44]
+la_input[43] |la_input[43]
+la_input[32] |la_input[32]
+la_input[30] |la_input[30]
+la_input[29] |la_input[29]
+la_input[31] |la_input[31]
+la_input[101] |la_input[101]
+la_input[99] |la_input[99]
+la_input[98] |la_input[98]
+la_input[97] |la_input[97]
+la_input[100] |la_input[100]
+la_input[37] |la_input[37]
+la_input[38] |la_input[38]
+la_input[35] |la_input[35]
+la_input[34] |la_input[34]
+la_input[36] |la_input[36]
+la_input[33] |la_input[33]
+la_input[77] |la_input[77]
+la_input[76] |la_input[76]
+la_input[75] |la_input[75]
+la_input[71] |la_input[71]
+la_input[74] |la_input[74]
+la_input[73] |la_input[73]
+la_input[72] |la_input[72]
+la_input[18] |la_input[18]
+la_input[17] |la_input[17]
+la_input[16] |la_input[16]
+la_input[15] |la_input[15]
+la_input[14] |la_input[14]
+la_input[13] |la_input[13]
+la_input[11] |la_input[11]
+la_input[12] |la_input[12]
+la_input[10] |la_input[10]
+la_input[103] |la_input[103]
+la_input[106] |la_input[106]
+la_input[104] |la_input[104]
+la_input[105] |la_input[105]
+la_input[102] |la_input[102]
+la_input[96] |la_input[96]
+la_input[90] |la_input[90]
+la_input[88] |la_input[88]
+la_input[86] |la_input[86]
+la_input[85] |la_input[85]
+la_input[84] |la_input[84]
+la_input[82] |la_input[82]
+la_input[80] |la_input[80]
+la_input[83] |la_input[83]
+la_input[81] |la_input[81]
+la_input[79] |la_input[79]
+la_input[78] |la_input[78]
+la_input[50] |la_input[50]
+la_input[54] |la_input[54]
+la_input[53] |la_input[53]
+la_input[51] |la_input[51]
+la_input[52] |la_input[52]
+la_input[27] |la_input[27]
+la_input[28] |la_input[28]
+la_input[26] |la_input[26]
+la_input[25] |la_input[25]
+la_input[24] |la_input[24]
+la_input[23] |la_input[23]
+la_input[22] |la_input[22]
+la_input[21] |la_input[21]
+la_input[20] |la_input[20]
+la_input[19] |la_input[19]
+resetn_in |resetn_in
+clk_in |clk_in
+mprj_dat_i[21] |mprj_dat_i[21]
+core_clk |core_clk
+hk_dat_i[1] |hk_dat_i[1]
+hk_dat_i[2] |hk_dat_i[2]
+hk_dat_i[6] |hk_dat_i[6]
+hk_dat_i[17] |hk_dat_i[17]
+hk_dat_i[15] |hk_dat_i[15]
+hk_dat_i[4] |hk_dat_i[4]
+hk_dat_i[9] |hk_dat_i[9]
+hk_dat_i[0] |hk_dat_i[0]
+hk_ack_i |hk_ack_i
+hk_dat_i[13] |hk_dat_i[13]
+hk_dat_i[12] |hk_dat_i[12]
+hk_dat_i[11] |hk_dat_i[11]
+hk_dat_i[18] |hk_dat_i[18]
+hk_dat_i[16] |hk_dat_i[16]
+hk_dat_i[14] |hk_dat_i[14]
+hk_dat_i[19] |hk_dat_i[19]
+hk_dat_i[20] |hk_dat_i[20]
+hk_dat_i[22] |hk_dat_i[22]
+hk_dat_i[21] |hk_dat_i[21]
+hk_dat_i[23] |hk_dat_i[23]
+la_input[60] |la_input[60]
+la_input[59] |la_input[59]
+la_input[61] |la_input[61]
+la_input[62] |la_input[62]
+la_input[122] |la_input[122]
+la_input[120] |la_input[120]
+la_input[119] |la_input[119]
+la_input[124] |la_input[124]
+la_input[121] |la_input[121]
+la_input[123] |la_input[123]
+la_input[125] |la_input[125]
+la_input[127] |la_input[127]
+la_input[126] |la_input[126]
+la_input[9] |la_input[9]
+la_input[8] |la_input[8]
+la_input[5] |la_input[5]
+la_input[1] |la_input[1]
+la_input[4] |la_input[4]
+la_input[7] |la_input[7]
+la_input[6] |la_input[6]
+la_input[2] |la_input[2]
+la_input[3] |la_input[3]
+la_input[0] |la_input[0]
+la_input[109] |la_input[109]
+la_input[112] |la_input[112]
+la_input[115] |la_input[115]
+la_input[108] |la_input[108]
+la_input[113] |la_input[113]
+la_input[110] |la_input[110]
+la_input[114] |la_input[114]
+la_input[111] |la_input[111]
+la_input[116] |la_input[116]
+la_input[117] |la_input[117]
+hk_dat_i[30] |hk_dat_i[30]
+hk_dat_i[29] |hk_dat_i[29]
+hk_dat_i[31] |hk_dat_i[31]
+hk_dat_i[24] |hk_dat_i[24]
+hk_dat_i[27] |hk_dat_i[27]
+hk_dat_i[25] |hk_dat_i[25]
+hk_dat_i[28] |hk_dat_i[28]
+hk_dat_i[26] |hk_dat_i[26]
+hk_dat_i[8] |hk_dat_i[8]
+hk_dat_i[10] |hk_dat_i[10]
+hk_dat_i[5] |hk_dat_i[5]
+hk_dat_i[3] |hk_dat_i[3]
+hk_dat_i[7] |hk_dat_i[7]
+VGND |VGND
+VPWR |VPWR
+flash_io0_di |flash_io0_di
+flash_io2_di |flash_io2_di
+flash_io3_di |flash_io3_di
+---------------------------------------------------------------------------------------
+Cell pin lists are equivalent.
+Device classes mgmt_core_wrapper and mgmt_core_wrapper are equivalent.
+
+Final result: Circuits match uniquely.
+.
diff --git a/signoff/mgmt_core_wrapper/standalone_pvr/eco-mgmt_core_wrapper.unflattened b/signoff/mgmt_core_wrapper/standalone_pvr/eco-mgmt_core_wrapper.unflattened
new file mode 100644
index 0000000..e69de29
diff --git a/signoff/mgmt_core_wrapper/standalone_pvr/eco-mgmt_core_wrapper_klayout_drc.xml b/signoff/mgmt_core_wrapper/standalone_pvr/eco-mgmt_core_wrapper_klayout_drc.xml
new file mode 100644
index 0000000..5161fcd
--- /dev/null
+++ b/signoff/mgmt_core_wrapper/standalone_pvr/eco-mgmt_core_wrapper_klayout_drc.xml
@@ -0,0 +1,873 @@
+
+
+ SKY130 DRC runset
+
+ drc: script='tech-files/sky130A_mr.drc'
+ mgmt_core_wrapper
+
+
+
+
+ dnwell.2
+ dnwell.2 : min. dnwell width : 3.0um
+
+
+
+
+ nwell.1
+ nwell.1 : min. nwell width : 0.84um
+
+
+
+
+ nwell.2a
+ nwell.2a : min. nwell spacing (merged if less) : 1.27um
+
+
+
+
+ nwell.6
+ nwell.6 : min enclosure of nwellHole by dnwell : 1.03um
+
+
+
+
+ hvtp.1
+ hvtp.1 : min. hvtp width : 0.38um
+
+
+
+
+ hvtp.2
+ hvtp.2 : min. hvtp spacing : 0.38um
+
+
+
+
+ hvtr.1
+ hvtr.1 : min. hvtr width : 0.38um
+
+
+
+
+ hvtr.2
+ hvtr.2 : min. hvtr spacing : 0.38um
+
+
+
+
+ hvtr.2_a
+ hvtr.2_a : hvtr must not overlap hvtp
+
+
+
+
+ lvtn.1a
+ lvtn.1a : min. lvtn width : 0.38um
+
+
+
+
+ lvtn.2
+ lvtn.2 : min. lvtn spacing : 0.38um
+
+
+
+
+ ncm.1
+ ncm.1 : min. ncm width : 0.38um
+
+
+
+
+ ncm.2a
+ ncm.2a : min. ncm spacing : 0.38um
+
+
+
+
+ difftap.1
+ difftap.1 : min. diff width across areaid:ce : 0.15um
+
+
+
+
+ difftap.1_a
+ difftap.1_a : min. diff width in periphery : 0.15um
+
+
+
+
+ difftap.1_b
+ difftap.1_b : min. tap width across areaid:ce : 0.15um
+
+
+
+
+ difftap.1_c
+ difftap.1_c : min. tap width in periphery : 0.15um
+
+
+
+
+ difftap.3
+ difftap.3 : min. difftap spacing : 0.27um
+
+
+
+
+ tunm.1
+ tunm.1 : min. tunm width : 0.41um
+
+
+
+
+ tunm.2
+ tunm.2 : min. tunm spacing : 0.5um
+
+
+
+
+ poly.1a
+ poly.1a : min. poly width : 0.15um
+
+
+
+
+ poly.2
+ poly.2 : min. poly spacing : 0.21um
+
+
+
+
+ rpm.1a
+ rpm.1a : min. rpm width : 1.27um
+
+
+
+
+ rpm.2
+ rpm.2 : min. rpm spacing : 0.84um
+
+
+
+
+ urpm.1a
+ urpm.1a : min. rpm width : 1.27um
+
+
+
+
+ urpm.2
+ urpm.2 : min. rpm spacing : 0.84um
+
+
+
+
+ npc.1
+ npc.1 : min. npc width : 0.27um
+
+
+
+
+ npc.2
+ npc.2 : min. npc spacing, should be manually merged if less than : 0.27um
+
+
+
+
+ nsd.1
+ nsd.1 : min. nsdm width : 0.38um
+
+
+
+
+ nsd.2
+ nsd.2 : min. nsdm spacing, should be manually merged if less than : 0.38um
+
+
+
+
+ psd.1
+ psd.1 : min. psdm width : 0.38um
+
+
+
+
+ psd.2
+ psd.2 : min. psdm spacing, should be manually merged if less than : 0.38um
+
+
+
+
+ licon.1
+ licon.1 : licon should be rectangle
+
+
+
+
+ licon.1_a/b
+ licon.1_a/b : minimum/maximum width of licon : 0.17um
+
+
+
+
+ licon.13
+ licon.13 : min. difftap licon spacing to npc : 0.09um
+
+
+
+
+ licon.13_a
+ licon.13_a : licon of diffTap in periphery must not overlap npc
+
+
+
+
+ licon.17
+ licon.17 : Licons may not overlap both poly and (diff or tap)
+
+
+
+
+ capm.1
+ capm.1 : min. capm width : 1.0um
+
+
+
+
+ capm.2a
+ capm.2a : min. capm spacing : 0.84um
+
+
+
+
+ capm.2b
+ capm.2b : min. capm spacing : 1.2um
+
+
+
+
+ capm.2b_a
+ capm.2b_a : min. spacing of m3_bot_plate : 1.2um
+
+
+
+
+ capm.3
+ capm.3 : min. capm and m3 enclosure of m3 : 0.14um
+
+
+
+
+ capm.3_a
+ capm.3_a : min. m3 enclosure of capm : 0.14um
+
+
+
+
+ capm.4
+ capm.4 : min. capm enclosure of via3 : 0.14um
+
+
+
+
+ capm.5
+ capm.5 : min. capm spacing to via3 : 0.14um
+
+
+
+
+ capm.11
+ capm.11 : Min spacing of capm and met3 not overlapping capm : 0.5um
+
+
+
+
+ cap2m.1
+ cap2m.1 : min. cap2m width : 1.0um
+
+
+
+
+ cap2m.2a
+ cap2m.2a : min. cap2m spacing : 0.84um
+
+
+
+
+ cap2m.2b
+ cap2m.2b : min. cap2m spacing : 1.2um
+
+
+
+
+ cap2m.2b_a
+ cap2m.2b_a : min. spacing of m4_bot_plate : 1.2um
+
+
+
+
+ cap2m.3
+ cap2m.3 : min. m4 enclosure of cap2m : 0.14um
+
+
+
+
+ cap2m.3_a
+ cap2m.3_a : min. m4 enclosure of cap2m : 0.14um
+
+
+
+
+ cap2m.4
+ cap2m.4 : min. cap2m enclosure of via4 : 0.14um
+
+
+
+
+ cap2m.5
+ cap2m.5 : min. cap2m spacing to via4 : 0.14um
+
+
+
+
+ cap2m.11
+ cap2m.11 : Min spacing of cap2m and met4 not overlapping cap2m : 0.5um
+
+
+
+
+ li.1
+ li.1 : min. li width : 0.17um
+
+
+
+
+ li.3
+ li.3 : min. li spacing : 0.17um
+
+
+
+
+ li.5
+ li.5 : min. li enclosure of licon of 2 adjacent edges : 0.08um
+
+
+
+
+ li.6
+ li.6 : min. li area : 0.0561um²
+
+
+
+
+ ct.1
+ ct.1: non-ring mcon should be rectangular
+
+
+
+
+ ct.1_a
+ ct.1_a : minimum width of mcon : 0.17um
+
+
+
+
+ ct.1_b
+ ct.1_b : maximum length of mcon : 0.17um
+
+
+
+
+ ct.2
+ ct.2 : min. mcon spacing : 0.19um
+
+
+
+
+ ct.3
+ ct.3 : min. width of ring-shaped mcon : 0.17um
+
+
+
+
+ ct.3_a
+ ct.3_a : max. width of ring-shaped mcon : 0.175um
+
+
+
+
+ ct.3_b
+ ct.3_b: ring-shaped mcon must be enclosed by areaid_sl
+
+
+
+
+ ct.4
+ ct.4 : mcon should covered by li
+
+
+
+
+ m1.1
+ m1.1 : min. m1 width : 0.14um
+
+
+
+
+ m1.2
+ m1.2 : min. m1 spacing : 0.14um
+
+
+
+
+ m1.3ab
+ m1.3ab : min. 3um.m1 spacing m1 : 0.28um
+
+
+
+
+ 791_m1.4
+ 791_m1.4 : min. m1 enclosure of mcon : 0.03um
+
+
+
+
+ m1.4
+ m1.4 : mcon periphery must be enclosed by m1
+
+
+
+
+ m1.4a
+ m1.4a : min. m1 enclosure of mcon for specific cells : 0.005um
+
+
+
+
+ m1.4a_a
+ m1.4a_a : mcon periph must be enclosed by met1 for specific cells
+
+
+
+
+ m1.6
+ m1.6 : min. m1 area : 0.083um²
+
+
+
+
+ m1.7
+ m1.7 : min. m1 with holes area : 0.14um²
+
+
+
+
+ m1.5
+ m1.5 : min. m1 enclosure of mcon of 2 adjacent edges : 0.06um
+
+
+
+
+ via.1a
+ via.1a : via outside of moduleCut should be rectangular
+
+
+
+
+ via.1a_a
+ via.1a_a : min. width of via outside of moduleCut : 0.15um
+
+
+
+
+ via.1a_b
+ via.1a_b : maximum length of via : 0.15um
+
+
+
+
+ via.2
+ via.2 : min. via spacing : 0.17um
+
+
+
+
+ via.3
+ via.3 : min. width of ring-shaped via : 0.2um
+
+
+
+
+ via.3_a
+ via.3_a : max. width of ring-shaped via : 0.205um
+
+
+
+
+ via.3_b
+ via.3_b: ring-shaped via must be enclosed by areaid_sl
+
+
+
+
+ via.4a
+ via.4a : min. m1 enclosure of 0.15um via : 0.055um
+
+
+
+
+ via.4a_a
+ via.4a_a : 0.15um via must be enclosed by met1
+
+
+
+
+ via.5a
+ via.5a : min. m1 enclosure of 0.15um via of 2 adjacent edges : 0.085um
+
+
+
+
+ m2.1
+ m2.1 : min. m2 width : 0.14um
+
+
+
+
+ m2.2
+ m2.2 : min. m2 spacing : 0.14um
+
+
+
+
+ m2.3ab
+ m2.3ab : min. 3um.m2 spacing m2 : 0.28um
+
+
+
+
+ m2.6
+ m2.6 : min. m2 area : 0.0676um²
+
+
+
+
+ m2.7
+ m2.7 : min. m2 holes area : 0.14um²
+
+
+
+
+ m2.4
+ m2.4 : min. m2 enclosure of via : 0.055um
+
+
+
+
+ m2.4_a
+ m2.4_a : via in periphery must be enclosed by met2
+
+
+
+
+ m2.5
+ m2.5 : min. m2 enclosure of via of 2 adjacent edges : 0.085um
+
+
+
+
+ via2.1a
+ via2.1a : via2 outside of moduleCut should be rectangular
+
+
+
+
+ via2.1a_a
+ via2.1a_a : min. width of via2 outside of moduleCut : 0.2um
+
+
+
+
+ via2.1a_b
+ via2.1a_b : maximum length of via2 : 0.2um
+
+
+
+
+ via2.2
+ via2.2 : min. via2 spacing : 0.2um
+
+
+
+
+ via2.3
+ via2.3 : min. width of ring-shaped via2 : 0.2um
+
+
+
+
+ via2.3_a
+ via2.3_a : max. width of ring-shaped via2 : 0.205um
+
+
+
+
+ via2.3_b
+ via2.3_b: ring-shaped via2 must be enclosed by areaid_sl
+
+
+
+
+ via2.4
+ via2.4 : min. m2 enclosure of via2 : 0.04um
+
+
+
+
+ via2.4_a
+ via2.4_a : via must be enclosed by met2
+
+
+
+
+ via2.5
+ via2.5 : min. m3 enclosure of via2 of 2 adjacent edges : 0.085um
+
+
+
+
+ m3.1
+ m3.1 : min. m3 width : 0.3um
+
+
+
+
+ m3.2
+ m3.2 : min. m3 spacing : 0.3um
+
+
+
+
+ m3.3cd
+ m3.3cd : min. 3um.m3 spacing m3 : 0.4um
+
+
+
+
+ m3.4
+ m3.4 : min. m3 enclosure of via2 : 0.065um
+
+
+
+
+ m3.4_a
+ m3.4_a : via2 must be enclosed by met3
+
+
+
+
+ via3.1
+ via3.1 : via3 outside of moduleCut should be rectangular
+
+
+
+
+ via3.1_a
+ via3.1_a : min. width of via3 outside of moduleCut : 0.2um
+
+
+
+
+ via3.1_b
+ via3.1_b : maximum length of via3 : 0.2um
+
+
+
+
+ via3.2
+ via3.2 : min. via3 spacing : 0.2um
+
+
+
+
+ via3.4
+ via3.4 : min. m3 enclosure of via3 : 0.06um
+
+
+
+
+ via3.4_a
+ via3.4_a : non-ring via3 must be enclosed by met3
+
+
+
+
+ via3.5
+ via3.5 : min. m3 enclosure of via3 of 2 adjacent edges : 0.09um
+
+
+
+
+ m4.1
+ m4.1 : min. m4 width : 0.3um
+
+
+
+
+ m4.2
+ m4.2 : min. m4 spacing : 0.3um
+
+
+
+
+ m4.4a
+ m4.4a : min. m4 area : 0.240um²
+
+
+
+
+ m4.5ab
+ m4.5ab : min. 3um.m4 spacing m4 : 0.4um
+
+
+
+
+ m4.3
+ m4.3 : min. m4 enclosure of via3 : 0.065um
+
+
+
+
+ m4.3_a
+ m4.3_a : via3 must be enclosed by met4
+
+
+
+
+ via4.1
+ via4.1 : via4 outside of moduleCut should be rectangular
+
+
+
+
+ via4.1_a
+ via4.1_a : min. width of via4 outside of moduleCut : 0.8um
+
+
+
+
+ via4.1_b
+ via4.1_b : maximum length of via4 : 0.8um
+
+
+
+
+ via4.2
+ via4.2 : min. via4 spacing : 0.8um
+
+
+
+
+ via4.3
+ via4.3 : min. width of ring-shaped via4 : 0.8um
+
+
+
+
+ via4.3_a
+ via4.3_a : max. width of ring-shaped via4 : 0.805um
+
+
+
+
+ via4.3_b
+ via4.3_b: ring-shaped via4 must be enclosed by areaid_sl
+
+
+
+
+ via4.4
+ via4.4 : min. m4 enclosure of via4 : 0.19um
+
+
+
+
+ via4.4_a
+ via4.4_a : m4 must enclose all via4
+
+
+
+
+ m5.1
+ m5.1 : min. m5 width : 1.6um
+
+
+
+
+ m5.2
+ m5.2 : min. m5 spacing : 1.6um
+
+
+
+
+ m5.3
+ m5.3 : min. m5 enclosure of via4 : 0.31um
+
+
+
+
+ m5.3_a
+ m5.3_a : via must be enclosed by m5
+
+
+
+
+ m5.4
+ m5.4 : min. m5 area : 4.0um²
+
+
+
+
+ pad.2
+ pad.2 : min. pad spacing : 1.27um
+
+
+
+
+ hvi.1
+ hvi.1 : min. hvi width : 0.6um
+
+
+
+
+ hvi.2a
+ hvi.2a : min. hvi spacing : 0.7um
+
+
+
+
+ hvntm.1
+ hvntm.1 : min. hvntm width : 0.7um
+
+
+
+
+ hvntm.2
+ hvntm.2 : min. hvntm spacing : 0.7um
+
+
+
+
+
+
+ mgmt_core_wrapper
+
+
+
+ |
+
+
+
+