From 9325c1951ca81a9bcfab649cdb31100982ad442b Mon Sep 17 00:00:00 2001
From: MartinRoehm <martin.roehm@student.uni-tuebingen.de>
Date: Mon, 8 Apr 2024 10:00:04 +0200
Subject: [PATCH 01/19] implement pipeline stall for data hazards

---
 .../uarch/riscv/pipeline.py                   | 64 +++++++++++++++++++
 .../uarch/riscv/pipeline_registers.py         |  3 +-
 .../uarch/riscv/riscv_performance_metrics.py  |  2 +
 architecture_simulator/uarch/riscv/stages.py  | 17 +++--
 tests/test_riscv_pipeline.py                  | 15 +++++
 tests/test_riscv_simulation.py                |  6 +-
 6 files changed, 98 insertions(+), 9 deletions(-)

diff --git a/architecture_simulator/uarch/riscv/pipeline.py b/architecture_simulator/uarch/riscv/pipeline.py
index ae50ea50..81006630 100644
--- a/architecture_simulator/uarch/riscv/pipeline.py
+++ b/architecture_simulator/uarch/riscv/pipeline.py
@@ -42,6 +42,11 @@ def __init__(
             PipelineRegister()
         ] * self.num_stages
 
+        # if != None: [stage to cause stall, remaining duration]
+        self.stalled: list[int] | None = None
+        # holds the old content of the first stage, since the first stage must not be rerun
+        self.stalled_pipeline_reg: PipelineRegister | None = None
+
     def step(self):
         """the pipeline step method, this is the central part of the pipeline! Every time it is called, it does one
         whole step of the pipeline, and every stage gets executed once in their execution ordering
@@ -50,6 +55,34 @@ def step(self):
         next_pipeline_registers = [None] * self.num_stages
         for index in self.execution_ordering:
             try:
+                if self.stalled is not None:
+                    if index == 0:  # first stage must not be recomputed when stalling
+                        next_pipeline_registers[0] = self.pipeline_registers[0]
+                        continue
+                    elif (
+                        index == 1
+                    ):  # second stage must get the old content of the pipelineregister of the first stage when stalling
+                        tmp = self.pipeline_registers[0]
+                        self.pipeline_registers[0] = self.stalled_pipeline_reg
+                        next_pipeline_registers[index] = self.stages[index].behavior(
+                            pipeline_registers=self.pipeline_registers,
+                            index_of_own_input_register=(index - 1),
+                            state=self.state,
+                        )
+                        self.pipeline_registers[0] = tmp
+                        continue
+                    elif (
+                        index == self.stalled[0] + 1
+                    ):  # first stage after the stalled stages must get and empty PipelineRegister while stalling
+                        tmp = self.pipeline_registers[self.stalled[0]]
+                        self.pipeline_registers[self.stalled[0]] = PipelineRegister()
+                        next_pipeline_registers[index] = self.stages[index].behavior(
+                            pipeline_registers=self.pipeline_registers,
+                            index_of_own_input_register=(index - 1),
+                            state=self.state,
+                        )
+                        self.pipeline_registers[self.stalled[0]] = tmp
+                        continue
                 next_pipeline_registers[index] = self.stages[index].behavior(
                     pipeline_registers=self.pipeline_registers,
                     index_of_own_input_register=(index - 1),
@@ -68,8 +101,33 @@ def step(self):
                     )
                 else:
                     raise
+
+        # Check if a stage has produced a stall signal
+        for index, pipeline_register in reversed(
+            list(enumerate(next_pipeline_registers))
+        ):
+            if (
+                pipeline_register is not None
+                and pipeline_register.stall_signal is not None
+                and (self.stalled is None or index > self.stalled[0])
+            ):
+                self.stalled = [index, pipeline_register.stall_signal.duration + 1]
+                self.state.performance_metrics.stalls += 1
+                break
+
+        # Keep the old value of the first pipeline register
+        if self.stalled and self.stalled_pipeline_reg is None:
+            self.stalled_pipeline_reg = self.pipeline_registers[0]
+
         self.pipeline_registers = next_pipeline_registers
 
+        # Check if done stalling
+        if self.stalled is not None:
+            self.stalled[1] -= 1
+            if self.stalled[1] == 0:
+                self.stalled = None
+                self.stalled_pipeline_reg = None
+
         # if one of the stages wants to flush, do so (starting from the back makes sense)
         for index, pipeline_register in reversed(
             list(enumerate(self.pipeline_registers))
@@ -84,6 +142,12 @@ def step(self):
                     PipelineRegister()
                 ] * num_to_flush
                 self.state.program_counter = flush_signal.address
+
+                # Unstall stages that have been flushed
+                if self.stalled is not None and self.stalled[0] < num_to_flush:
+                    self.stalled = None
+                    self.stalled_pipeline_reg = None
+
                 break  # break since we don't care about the previous stages
 
     def is_empty(self) -> bool:
diff --git a/architecture_simulator/uarch/riscv/pipeline_registers.py b/architecture_simulator/uarch/riscv/pipeline_registers.py
index 9f1b8770..fcd69dcf 100644
--- a/architecture_simulator/uarch/riscv/pipeline_registers.py
+++ b/architecture_simulator/uarch/riscv/pipeline_registers.py
@@ -7,7 +7,7 @@
 
 if TYPE_CHECKING:
     from architecture_simulator.isa.riscv.instruction_types import RiscvInstruction
-    from .stages import FlushSignal
+    from .stages import FlushSignal, StallSignal
 
 
 @dataclass
@@ -19,6 +19,7 @@ class PipelineRegister:
     instruction: RiscvInstruction = field(default_factory=EmptyInstruction)
     address_of_instruction: Optional[int] = None
     flush_signal: Optional[FlushSignal] = None
+    stall_signal: Optional[StallSignal] = None
     abbreviation = "Single"
 
 
diff --git a/architecture_simulator/uarch/riscv/riscv_performance_metrics.py b/architecture_simulator/uarch/riscv/riscv_performance_metrics.py
index 101fc26f..e4e76415 100644
--- a/architecture_simulator/uarch/riscv/riscv_performance_metrics.py
+++ b/architecture_simulator/uarch/riscv/riscv_performance_metrics.py
@@ -8,6 +8,7 @@ class RiscvPerformanceMetrics(PerformanceMetrics):
     branch_count: int = 0
     procedure_count: int = 0
     flushes: int = 0
+    stalls: int = 0
     cycles: int = 0
 
     def __repr__(self) -> str:
@@ -25,6 +26,7 @@ def __repr__(self) -> str:
         representation += f"branches: {self.branch_count}\n"
         representation += f"procedures: {self.procedure_count}\n"
         representation += f"cycles: {self.cycles}\n"
+        representation += f"stalls: {self.stalls}\n"
         representation += f"flushes: {self.flushes}\n"
         if not self.instruction_count == 0:
             representation += f"cycles per instruction: {(self.cycles / self.instruction_count):.2f}\n"
diff --git a/architecture_simulator/uarch/riscv/stages.py b/architecture_simulator/uarch/riscv/stages.py
index 8fd157c7..856457cb 100644
--- a/architecture_simulator/uarch/riscv/stages.py
+++ b/architecture_simulator/uarch/riscv/stages.py
@@ -153,7 +153,7 @@ def behavior(
         write_register = pipeline_register.instruction.get_write_register()
 
         # Data Hazard Detection
-        flush_signal = None
+        stall_signal = None
         if self.detect_data_hazards:
             # Put all the write registers of later stages, that are not done ahead of this stage into a list
             write_registers_of_later_stages = [
@@ -168,10 +168,7 @@ def behavior(
                     continue
                 if register_read_addr_1 == register or register_read_addr_2 == register:
                     assert pipeline_register.address_of_instruction is not None
-                    flush_signal = FlushSignal(
-                        inclusive=True,
-                        address=pipeline_register.address_of_instruction,
-                    )
+                    stall_signal = StallSignal(2)
                     break
 
         # gets the control unit signals that are generated in the ID stage
@@ -186,7 +183,7 @@ def behavior(
             write_register=write_register,
             control_unit_signals=control_unit_signals,
             branch_prediction=pipeline_register.branch_prediction,
-            flush_signal=flush_signal,
+            stall_signal=stall_signal,
             pc_plus_instruction_length=pipeline_register.pc_plus_instruction_length,
             address_of_instruction=pipeline_register.address_of_instruction,
         )
@@ -571,3 +568,11 @@ class FlushSignal:
     inclusive: bool
     # address to return to
     address: int
+
+
+@dataclass
+class StallSignal:
+    """A signal that this stage and all previous stages should be stalled for a duration of cycles"""
+
+    # how many cycles to stall
+    duration: int
diff --git a/tests/test_riscv_pipeline.py b/tests/test_riscv_pipeline.py
index 7ad52552..4a922067 100644
--- a/tests/test_riscv_pipeline.py
+++ b/tests/test_riscv_pipeline.py
@@ -1381,3 +1381,18 @@ def test_fix_too_many_flushes(self):
 
         self.assert_steps(simulation=simulation, steps=9)
         self.assertEqual(simulation.state.register_file.registers[2], 2)
+
+    def test_stall(self):
+        program = """
+        addi x1, x0, 11
+        addi x2, x1, 22
+        """
+
+        sim = RiscvSimulation(mode="five_stage_pipeline")
+
+        sim.load_program(program)
+        sim.run()
+        self.assertEqual(sim.state.register_file.registers[2], 33)
+        self.assertEqual(sim.state.performance_metrics.cycles, 8)
+        self.assertEqual(sim.state.performance_metrics.stalls, 1)
+        self.assertEqual(sim.state.performance_metrics.flushes, 0)
diff --git a/tests/test_riscv_simulation.py b/tests/test_riscv_simulation.py
index f69fd8f6..a775fd88 100644
--- a/tests/test_riscv_simulation.py
+++ b/tests/test_riscv_simulation.py
@@ -269,7 +269,8 @@ def test_five_stage_performance_metrics_2(self):
         """
         simulation.load_program(program=programm)
         simulation.run()
-        self.assertEqual(simulation.state.performance_metrics.flushes, 2)
+        self.assertEqual(simulation.state.performance_metrics.flushes, 1)
+        self.assertEqual(simulation.state.performance_metrics.stalls, 1)
         self.assertEqual(simulation.state.performance_metrics.cycles, 12)
 
     def test_off_by_one_fix(self):
@@ -332,7 +333,8 @@ def test_five_stage_performance_metrics_3(self):
         self.assertEqual(simulation.state.register_file.registers[3], 160)
         self.assertEqual(simulation.state.performance_metrics.instruction_count, 32)
         self.assertEqual(simulation.state.performance_metrics.branch_count, 9)
-        self.assertEqual(simulation.state.performance_metrics.flushes, 20)
+        self.assertEqual(simulation.state.performance_metrics.flushes, 9)
+        self.assertEqual(simulation.state.performance_metrics.stalls, 11)
 
     def test_has_started(self):
         sim = RiscvSimulation()

From 3bfa5caaf682467dff8c288eabf707f2967ea6a1 Mon Sep 17 00:00:00 2001
From: MartinRoehm <martin.roehm@student.uni-tuebingen.de>
Date: Mon, 8 Apr 2024 12:09:09 +0200
Subject: [PATCH 02/19] add stalls for ecall

---
 .../uarch/riscv/pipeline.py                   | 35 +++++++++++--------
 .../uarch/riscv/pipeline_registers.py         |  3 ++
 architecture_simulator/uarch/riscv/stages.py  | 18 +++++-----
 tests/test_ecalls.py                          | 24 ++++++++++++-
 4 files changed, 56 insertions(+), 24 deletions(-)

diff --git a/architecture_simulator/uarch/riscv/pipeline.py b/architecture_simulator/uarch/riscv/pipeline.py
index 81006630..4564be5d 100644
--- a/architecture_simulator/uarch/riscv/pipeline.py
+++ b/architecture_simulator/uarch/riscv/pipeline.py
@@ -45,7 +45,7 @@ def __init__(
         # if != None: [stage to cause stall, remaining duration]
         self.stalled: list[int] | None = None
         # holds the old content of the first stage, since the first stage must not be rerun
-        self.stalled_pipeline_reg: PipelineRegister | None = None
+        self.stalled_pipeline_regs: list[PipelineRegister] | None = None
 
     def step(self):
         """the pipeline step method, this is the central part of the pipeline! Every time it is called, it does one
@@ -60,28 +60,30 @@ def step(self):
                         next_pipeline_registers[0] = self.pipeline_registers[0]
                         continue
                     elif (
-                        index == 1
-                    ):  # second stage must get the old content of the pipelineregister of the first stage when stalling
-                        tmp = self.pipeline_registers[0]
-                        self.pipeline_registers[0] = self.stalled_pipeline_reg
+                        index == self.stalled[0] + 1
+                    ):  # first stage after the stalled stages must get an empty PipelineRegister while stalling
+                        tmp = self.pipeline_registers[self.stalled[0]]
+                        self.pipeline_registers[self.stalled[0]] = PipelineRegister()
                         next_pipeline_registers[index] = self.stages[index].behavior(
                             pipeline_registers=self.pipeline_registers,
                             index_of_own_input_register=(index - 1),
                             state=self.state,
                         )
-                        self.pipeline_registers[0] = tmp
+                        self.pipeline_registers[self.stalled[0]] = tmp
                         continue
                     elif (
-                        index == self.stalled[0] + 1
-                    ):  # first stage after the stalled stages must get and empty PipelineRegister while stalling
-                        tmp = self.pipeline_registers[self.stalled[0]]
-                        self.pipeline_registers[self.stalled[0]] = PipelineRegister()
+                        index <= self.stalled[0]
+                    ):  # Other stalled stages should get the old PipelineRegister values NOTE: This is fine, because the only instruction that stalls in EX is ecall and ecall does not get it´s register values from the previous PipelineRegister
+                        tmp = self.pipeline_registers[index - 1]
+                        self.pipeline_registers[index - 1] = self.stalled_pipeline_regs[
+                            index - 1
+                        ]
                         next_pipeline_registers[index] = self.stages[index].behavior(
                             pipeline_registers=self.pipeline_registers,
                             index_of_own_input_register=(index - 1),
                             state=self.state,
                         )
-                        self.pipeline_registers[self.stalled[0]] = tmp
+                        self.pipeline_registers[index - 1] = tmp
                         continue
                 next_pipeline_registers[index] = self.stages[index].behavior(
                     pipeline_registers=self.pipeline_registers,
@@ -116,8 +118,11 @@ def step(self):
                 break
 
         # Keep the old value of the first pipeline register
-        if self.stalled and self.stalled_pipeline_reg is None:
-            self.stalled_pipeline_reg = self.pipeline_registers[0]
+        if self.stalled and self.stalled_pipeline_regs is None:
+            self.stalled_pipeline_regs = self.pipeline_registers[: self.stalled[0]]
+
+            for reg in self.stalled_pipeline_regs:
+                reg.is_of_stalled_value = True
 
         self.pipeline_registers = next_pipeline_registers
 
@@ -126,7 +131,7 @@ def step(self):
             self.stalled[1] -= 1
             if self.stalled[1] == 0:
                 self.stalled = None
-                self.stalled_pipeline_reg = None
+                self.stalled_pipeline_regs = None
 
         # if one of the stages wants to flush, do so (starting from the back makes sense)
         for index, pipeline_register in reversed(
@@ -146,7 +151,7 @@ def step(self):
                 # Unstall stages that have been flushed
                 if self.stalled is not None and self.stalled[0] < num_to_flush:
                     self.stalled = None
-                    self.stalled_pipeline_reg = None
+                    self.stalled_pipeline_regs = None
 
                 break  # break since we don't care about the previous stages
 
diff --git a/architecture_simulator/uarch/riscv/pipeline_registers.py b/architecture_simulator/uarch/riscv/pipeline_registers.py
index fcd69dcf..71dd00ea 100644
--- a/architecture_simulator/uarch/riscv/pipeline_registers.py
+++ b/architecture_simulator/uarch/riscv/pipeline_registers.py
@@ -22,6 +22,9 @@ class PipelineRegister:
     stall_signal: Optional[StallSignal] = None
     abbreviation = "Single"
 
+    # True, if the register is being separately preserved by the pipeline for stalling
+    is_of_stalled_value: bool = False
+
 
 @dataclass
 class InstructionFetchPipelineRegister(PipelineRegister):
diff --git a/architecture_simulator/uarch/riscv/stages.py b/architecture_simulator/uarch/riscv/stages.py
index 856457cb..2d724f65 100644
--- a/architecture_simulator/uarch/riscv/stages.py
+++ b/architecture_simulator/uarch/riscv/stages.py
@@ -236,21 +236,23 @@ def behavior(
         )
 
         # ECALL needs some special behavior (flush and print to output)
-        flush_signal = None
+        stall_signal = None
         if isinstance(pipeline_register.instruction, ECALL):
-            # assume that all further stages need to be empty
-            for other_pr in pipeline_registers[index_of_own_input_register + 1 : -1]:
+            # assume that all further stages need to be empty, unless this stage is already stalled and the value of the next register is only for display purposes
+            for other_pr in pipeline_registers[
+                index_of_own_input_register
+                + 1
+                + int(pipeline_register.is_of_stalled_value) : -1
+            ]:
                 if not isinstance(other_pr.instruction, EmptyInstruction):
                     assert pipeline_register.address_of_instruction is not None
-                    flush_signal = FlushSignal(
-                        True, pipeline_register.address_of_instruction
-                    )
+                    stall_signal = StallSignal(2)
                     break
-            if flush_signal is None:
+            if stall_signal is None:
                 pipeline_register.instruction.behavior(state)
 
         return ExecutePipelineRegister(
-            flush_signal=flush_signal,
+            stall_signal=stall_signal,
             instruction=pipeline_register.instruction,
             alu_in_1=alu_in_1,
             alu_in_2=alu_in_2,
diff --git a/tests/test_ecalls.py b/tests/test_ecalls.py
index 16e329a3..8449109d 100644
--- a/tests/test_ecalls.py
+++ b/tests/test_ecalls.py
@@ -93,4 +93,26 @@ def test_five_stage_ecalls(self):
         )
         simulation.run()
         self.assertEqual(simulation.get_output(), "Kaesekuchen ist toll.")
-        self.assertEqual(simulation.get_performance_metrics().cycles, 13)
+        self.assertEqual(simulation.get_performance_metrics().cycles, 12)
+
+    def test_five_stage_ecalls_2(self):
+        simulation = RiscvSimulation(mode="five_stage_pipeline")
+        simulation.load_program(
+            """
+.data
+    kaesekuchen: .string "Kaesekuchen ist toll."
+.text
+la a0, kaesekuchen
+li a7, 2
+beq zero, zero, label
+nop
+nop
+nop
+label:
+add a7, a7, a7
+ecall
+"""
+        )
+        simulation.run()
+        self.assertEqual(simulation.get_output(), "Kaesekuchen ist toll.")
+        # NOTE: This works, because the ecall reads the register values directly and not out of the pipeline registers

From e1402be76f35c1af5fb402b539fc9a413b432fa4 Mon Sep 17 00:00:00 2001
From: MartinRoehm <martin.roehm@student.uni-tuebingen.de>
Date: Thu, 11 Apr 2024 11:14:53 +0200
Subject: [PATCH 03/19] add comments and tests for pipeline stall

---
 .../uarch/riscv/pipeline.py                   | 12 +++++-----
 tests/test_riscv_pipeline.py                  | 22 +++++++++++++++++++
 2 files changed, 29 insertions(+), 5 deletions(-)

diff --git a/architecture_simulator/uarch/riscv/pipeline.py b/architecture_simulator/uarch/riscv/pipeline.py
index 4564be5d..e2a86ef8 100644
--- a/architecture_simulator/uarch/riscv/pipeline.py
+++ b/architecture_simulator/uarch/riscv/pipeline.py
@@ -42,9 +42,9 @@ def __init__(
             PipelineRegister()
         ] * self.num_stages
 
-        # if != None: [stage to cause stall, remaining duration]
+        # if != None: [index of stage to cause stall, remaining duration of stall]
         self.stalled: list[int] | None = None
-        # holds the old content of the first stage, since the first stage must not be rerun
+        # holds the old contents of pipeline registers that are used as input for stalled stages
         self.stalled_pipeline_regs: list[PipelineRegister] | None = None
 
     def step(self):
@@ -73,7 +73,7 @@ def step(self):
                         continue
                     elif (
                         index <= self.stalled[0]
-                    ):  # Other stalled stages should get the old PipelineRegister values NOTE: This is fine, because the only instruction that stalls in EX is ecall and ecall does not get it´s register values from the previous PipelineRegister
+                    ):  # other stalled stages should get the old PipelineRegister values stored in stalled_pipeline_regs
                         tmp = self.pipeline_registers[index - 1]
                         self.pipeline_registers[index - 1] = self.stalled_pipeline_regs[
                             index - 1
@@ -85,11 +85,13 @@ def step(self):
                         )
                         self.pipeline_registers[index - 1] = tmp
                         continue
+
                 next_pipeline_registers[index] = self.stages[index].behavior(
                     pipeline_registers=self.pipeline_registers,
                     index_of_own_input_register=(index - 1),
                     state=self.state,
                 )
+
             except Exception as e:
                 if index - 1 >= 0:
                     raise InstructionExecutionException(
@@ -104,7 +106,7 @@ def step(self):
                 else:
                     raise
 
-        # Check if a stage has produced a stall signal
+        # Check if a stage has produced a meaningfull stall signal
         for index, pipeline_register in reversed(
             list(enumerate(next_pipeline_registers))
         ):
@@ -117,7 +119,7 @@ def step(self):
                 self.state.performance_metrics.stalls += 1
                 break
 
-        # Keep the old value of the first pipeline register
+        # keep PipelineRegister values in stalled_pipeline_regs
         if self.stalled and self.stalled_pipeline_regs is None:
             self.stalled_pipeline_regs = self.pipeline_registers[: self.stalled[0]]
 
diff --git a/tests/test_riscv_pipeline.py b/tests/test_riscv_pipeline.py
index 4a922067..881a5b18 100644
--- a/tests/test_riscv_pipeline.py
+++ b/tests/test_riscv_pipeline.py
@@ -1396,3 +1396,25 @@ def test_stall(self):
         self.assertEqual(sim.state.performance_metrics.cycles, 8)
         self.assertEqual(sim.state.performance_metrics.stalls, 1)
         self.assertEqual(sim.state.performance_metrics.flushes, 0)
+
+    def test_stall_2(self):
+        program = """
+        add x0, x0, x0
+        add x0, x0, x0
+        addi x1, x0, 11
+        addi x2, x1, 3
+        addi x3, x1, 4
+        addi x4, x2, 100
+        """
+
+        sim = RiscvSimulation(mode="five_stage_pipeline")
+
+        sim.load_program(program)
+        sim.run()
+        self.assertEqual(sim.state.register_file.registers[1], 11)
+        self.assertEqual(sim.state.register_file.registers[2], 14)
+        self.assertEqual(sim.state.register_file.registers[3], 15)
+        self.assertEqual(sim.state.register_file.registers[4], 114)
+        self.assertEqual(sim.state.performance_metrics.cycles, 14)
+        self.assertEqual(sim.state.performance_metrics.stalls, 2)
+        self.assertEqual(sim.state.performance_metrics.flushes, 0)

From 45cb08e2fd2ffbef001aed7813bf403ba2beb58f Mon Sep 17 00:00:00 2001
From: MartinRoehm <martin.roehm@student.uni-tuebingen.de>
Date: Tue, 23 Apr 2024 09:59:16 +0200
Subject: [PATCH 04/19] make addr in jal, x0, addr an abs value

---
 architecture_simulator/isa/riscv/instruction_types.py  | 5 +++--
 architecture_simulator/isa/riscv/riscv_parser.py       | 3 +++
 architecture_simulator/isa/riscv/rv32i_instructions.py | 4 ++--
 3 files changed, 8 insertions(+), 4 deletions(-)

diff --git a/architecture_simulator/isa/riscv/instruction_types.py b/architecture_simulator/isa/riscv/instruction_types.py
index a925df66..e00a111b 100644
--- a/architecture_simulator/isa/riscv/instruction_types.py
+++ b/architecture_simulator/isa/riscv/instruction_types.py
@@ -416,13 +416,14 @@ def access_register_file(
 
 
 class JTypeInstruction(RiscvInstruction):
-    def __init__(self, rd: int, imm: int, **args):
+    def __init__(self, rd: int, imm: int, abs_addr: int, **args):
         super().__init__(**args)
         self.rd = rd
         self.imm = (imm & (2**20) - 1) - (imm & 2**20)  # 21-bit sext
+        self.abs_addr = abs_addr
 
     def __repr__(self) -> str:
-        return f"{self.mnemonic} x{self.rd}, {self.imm}"
+        return f"{self.mnemonic} x{self.rd}, {self.abs_addr}"
 
     def control_unit_signals(self) -> ControlUnitSignals:
         return ControlUnitSignals(
diff --git a/architecture_simulator/isa/riscv/riscv_parser.py b/architecture_simulator/isa/riscv/riscv_parser.py
index 832a32d6..81619745 100644
--- a/architecture_simulator/isa/riscv/riscv_parser.py
+++ b/architecture_simulator/isa/riscv/riscv_parser.py
@@ -748,11 +748,14 @@ def _write_instructions(self) -> None:
                     line_number=line_number,
                     line=line,
                 )
+                if line_parsed.get("imm"):
+                    imm_val -= address_count
 
                 instructions.append(
                     instruction_class(
                         rd=self._convert_register_name(line_parsed.rd),
                         imm=imm_val,
+                        abs_addr=imm_val + address_count,
                     )
                 )
             elif issubclass(instruction_class, instruction_types.CSRTypeInstruction):
diff --git a/architecture_simulator/isa/riscv/rv32i_instructions.py b/architecture_simulator/isa/riscv/rv32i_instructions.py
index ece39060..fdb224f9 100644
--- a/architecture_simulator/isa/riscv/rv32i_instructions.py
+++ b/architecture_simulator/isa/riscv/rv32i_instructions.py
@@ -1217,8 +1217,8 @@ def alu_compute(
 
 
 class JAL(JTypeInstruction):
-    def __init__(self, rd: int, imm: int):
-        super().__init__(rd, imm, mnemonic="jal")
+    def __init__(self, rd: int, imm: int, abs_addr: int):
+        super().__init__(rd, imm, abs_addr, mnemonic="jal")
 
     def behavior(
         self, architectural_state: RiscvArchitecturalState

From 00e7ef5f2a846dba551132571f4745596606cd8b Mon Sep 17 00:00:00 2001
From: MartinRoehm <martin.roehm@student.uni-tuebingen.de>
Date: Mon, 8 Apr 2024 10:00:04 +0200
Subject: [PATCH 05/19] implement pipeline stall for data hazards

---
 .../uarch/riscv/pipeline.py                   | 64 +++++++++++++++++++
 .../uarch/riscv/pipeline_registers.py         |  3 +-
 .../uarch/riscv/riscv_performance_metrics.py  |  2 +
 architecture_simulator/uarch/riscv/stages.py  | 17 +++--
 tests/test_riscv_pipeline.py                  | 15 +++++
 tests/test_riscv_simulation.py                |  6 +-
 6 files changed, 98 insertions(+), 9 deletions(-)

diff --git a/architecture_simulator/uarch/riscv/pipeline.py b/architecture_simulator/uarch/riscv/pipeline.py
index ae50ea50..81006630 100644
--- a/architecture_simulator/uarch/riscv/pipeline.py
+++ b/architecture_simulator/uarch/riscv/pipeline.py
@@ -42,6 +42,11 @@ def __init__(
             PipelineRegister()
         ] * self.num_stages
 
+        # if != None: [stage to cause stall, remaining duration]
+        self.stalled: list[int] | None = None
+        # holds the old content of the first stage, since the first stage must not be rerun
+        self.stalled_pipeline_reg: PipelineRegister | None = None
+
     def step(self):
         """the pipeline step method, this is the central part of the pipeline! Every time it is called, it does one
         whole step of the pipeline, and every stage gets executed once in their execution ordering
@@ -50,6 +55,34 @@ def step(self):
         next_pipeline_registers = [None] * self.num_stages
         for index in self.execution_ordering:
             try:
+                if self.stalled is not None:
+                    if index == 0:  # first stage must not be recomputed when stalling
+                        next_pipeline_registers[0] = self.pipeline_registers[0]
+                        continue
+                    elif (
+                        index == 1
+                    ):  # second stage must get the old content of the pipelineregister of the first stage when stalling
+                        tmp = self.pipeline_registers[0]
+                        self.pipeline_registers[0] = self.stalled_pipeline_reg
+                        next_pipeline_registers[index] = self.stages[index].behavior(
+                            pipeline_registers=self.pipeline_registers,
+                            index_of_own_input_register=(index - 1),
+                            state=self.state,
+                        )
+                        self.pipeline_registers[0] = tmp
+                        continue
+                    elif (
+                        index == self.stalled[0] + 1
+                    ):  # first stage after the stalled stages must get and empty PipelineRegister while stalling
+                        tmp = self.pipeline_registers[self.stalled[0]]
+                        self.pipeline_registers[self.stalled[0]] = PipelineRegister()
+                        next_pipeline_registers[index] = self.stages[index].behavior(
+                            pipeline_registers=self.pipeline_registers,
+                            index_of_own_input_register=(index - 1),
+                            state=self.state,
+                        )
+                        self.pipeline_registers[self.stalled[0]] = tmp
+                        continue
                 next_pipeline_registers[index] = self.stages[index].behavior(
                     pipeline_registers=self.pipeline_registers,
                     index_of_own_input_register=(index - 1),
@@ -68,8 +101,33 @@ def step(self):
                     )
                 else:
                     raise
+
+        # Check if a stage has produced a stall signal
+        for index, pipeline_register in reversed(
+            list(enumerate(next_pipeline_registers))
+        ):
+            if (
+                pipeline_register is not None
+                and pipeline_register.stall_signal is not None
+                and (self.stalled is None or index > self.stalled[0])
+            ):
+                self.stalled = [index, pipeline_register.stall_signal.duration + 1]
+                self.state.performance_metrics.stalls += 1
+                break
+
+        # Keep the old value of the first pipeline register
+        if self.stalled and self.stalled_pipeline_reg is None:
+            self.stalled_pipeline_reg = self.pipeline_registers[0]
+
         self.pipeline_registers = next_pipeline_registers
 
+        # Check if done stalling
+        if self.stalled is not None:
+            self.stalled[1] -= 1
+            if self.stalled[1] == 0:
+                self.stalled = None
+                self.stalled_pipeline_reg = None
+
         # if one of the stages wants to flush, do so (starting from the back makes sense)
         for index, pipeline_register in reversed(
             list(enumerate(self.pipeline_registers))
@@ -84,6 +142,12 @@ def step(self):
                     PipelineRegister()
                 ] * num_to_flush
                 self.state.program_counter = flush_signal.address
+
+                # Unstall stages that have been flushed
+                if self.stalled is not None and self.stalled[0] < num_to_flush:
+                    self.stalled = None
+                    self.stalled_pipeline_reg = None
+
                 break  # break since we don't care about the previous stages
 
     def is_empty(self) -> bool:
diff --git a/architecture_simulator/uarch/riscv/pipeline_registers.py b/architecture_simulator/uarch/riscv/pipeline_registers.py
index 9f1b8770..fcd69dcf 100644
--- a/architecture_simulator/uarch/riscv/pipeline_registers.py
+++ b/architecture_simulator/uarch/riscv/pipeline_registers.py
@@ -7,7 +7,7 @@
 
 if TYPE_CHECKING:
     from architecture_simulator.isa.riscv.instruction_types import RiscvInstruction
-    from .stages import FlushSignal
+    from .stages import FlushSignal, StallSignal
 
 
 @dataclass
@@ -19,6 +19,7 @@ class PipelineRegister:
     instruction: RiscvInstruction = field(default_factory=EmptyInstruction)
     address_of_instruction: Optional[int] = None
     flush_signal: Optional[FlushSignal] = None
+    stall_signal: Optional[StallSignal] = None
     abbreviation = "Single"
 
 
diff --git a/architecture_simulator/uarch/riscv/riscv_performance_metrics.py b/architecture_simulator/uarch/riscv/riscv_performance_metrics.py
index 101fc26f..e4e76415 100644
--- a/architecture_simulator/uarch/riscv/riscv_performance_metrics.py
+++ b/architecture_simulator/uarch/riscv/riscv_performance_metrics.py
@@ -8,6 +8,7 @@ class RiscvPerformanceMetrics(PerformanceMetrics):
     branch_count: int = 0
     procedure_count: int = 0
     flushes: int = 0
+    stalls: int = 0
     cycles: int = 0
 
     def __repr__(self) -> str:
@@ -25,6 +26,7 @@ def __repr__(self) -> str:
         representation += f"branches: {self.branch_count}\n"
         representation += f"procedures: {self.procedure_count}\n"
         representation += f"cycles: {self.cycles}\n"
+        representation += f"stalls: {self.stalls}\n"
         representation += f"flushes: {self.flushes}\n"
         if not self.instruction_count == 0:
             representation += f"cycles per instruction: {(self.cycles / self.instruction_count):.2f}\n"
diff --git a/architecture_simulator/uarch/riscv/stages.py b/architecture_simulator/uarch/riscv/stages.py
index 8fd157c7..856457cb 100644
--- a/architecture_simulator/uarch/riscv/stages.py
+++ b/architecture_simulator/uarch/riscv/stages.py
@@ -153,7 +153,7 @@ def behavior(
         write_register = pipeline_register.instruction.get_write_register()
 
         # Data Hazard Detection
-        flush_signal = None
+        stall_signal = None
         if self.detect_data_hazards:
             # Put all the write registers of later stages, that are not done ahead of this stage into a list
             write_registers_of_later_stages = [
@@ -168,10 +168,7 @@ def behavior(
                     continue
                 if register_read_addr_1 == register or register_read_addr_2 == register:
                     assert pipeline_register.address_of_instruction is not None
-                    flush_signal = FlushSignal(
-                        inclusive=True,
-                        address=pipeline_register.address_of_instruction,
-                    )
+                    stall_signal = StallSignal(2)
                     break
 
         # gets the control unit signals that are generated in the ID stage
@@ -186,7 +183,7 @@ def behavior(
             write_register=write_register,
             control_unit_signals=control_unit_signals,
             branch_prediction=pipeline_register.branch_prediction,
-            flush_signal=flush_signal,
+            stall_signal=stall_signal,
             pc_plus_instruction_length=pipeline_register.pc_plus_instruction_length,
             address_of_instruction=pipeline_register.address_of_instruction,
         )
@@ -571,3 +568,11 @@ class FlushSignal:
     inclusive: bool
     # address to return to
     address: int
+
+
+@dataclass
+class StallSignal:
+    """A signal that this stage and all previous stages should be stalled for a duration of cycles"""
+
+    # how many cycles to stall
+    duration: int
diff --git a/tests/test_riscv_pipeline.py b/tests/test_riscv_pipeline.py
index 7ad52552..4a922067 100644
--- a/tests/test_riscv_pipeline.py
+++ b/tests/test_riscv_pipeline.py
@@ -1381,3 +1381,18 @@ def test_fix_too_many_flushes(self):
 
         self.assert_steps(simulation=simulation, steps=9)
         self.assertEqual(simulation.state.register_file.registers[2], 2)
+
+    def test_stall(self):
+        program = """
+        addi x1, x0, 11
+        addi x2, x1, 22
+        """
+
+        sim = RiscvSimulation(mode="five_stage_pipeline")
+
+        sim.load_program(program)
+        sim.run()
+        self.assertEqual(sim.state.register_file.registers[2], 33)
+        self.assertEqual(sim.state.performance_metrics.cycles, 8)
+        self.assertEqual(sim.state.performance_metrics.stalls, 1)
+        self.assertEqual(sim.state.performance_metrics.flushes, 0)
diff --git a/tests/test_riscv_simulation.py b/tests/test_riscv_simulation.py
index f69fd8f6..a775fd88 100644
--- a/tests/test_riscv_simulation.py
+++ b/tests/test_riscv_simulation.py
@@ -269,7 +269,8 @@ def test_five_stage_performance_metrics_2(self):
         """
         simulation.load_program(program=programm)
         simulation.run()
-        self.assertEqual(simulation.state.performance_metrics.flushes, 2)
+        self.assertEqual(simulation.state.performance_metrics.flushes, 1)
+        self.assertEqual(simulation.state.performance_metrics.stalls, 1)
         self.assertEqual(simulation.state.performance_metrics.cycles, 12)
 
     def test_off_by_one_fix(self):
@@ -332,7 +333,8 @@ def test_five_stage_performance_metrics_3(self):
         self.assertEqual(simulation.state.register_file.registers[3], 160)
         self.assertEqual(simulation.state.performance_metrics.instruction_count, 32)
         self.assertEqual(simulation.state.performance_metrics.branch_count, 9)
-        self.assertEqual(simulation.state.performance_metrics.flushes, 20)
+        self.assertEqual(simulation.state.performance_metrics.flushes, 9)
+        self.assertEqual(simulation.state.performance_metrics.stalls, 11)
 
     def test_has_started(self):
         sim = RiscvSimulation()

From 8480352a1e4563855422e89b79eb22f735f89c3c Mon Sep 17 00:00:00 2001
From: MartinRoehm <martin.roehm@student.uni-tuebingen.de>
Date: Mon, 8 Apr 2024 12:09:09 +0200
Subject: [PATCH 06/19] add stalls for ecall

---
 .../uarch/riscv/pipeline.py                   | 35 +++++++++++--------
 .../uarch/riscv/pipeline_registers.py         |  3 ++
 architecture_simulator/uarch/riscv/stages.py  | 18 +++++-----
 tests/test_ecalls.py                          | 24 ++++++++++++-
 4 files changed, 56 insertions(+), 24 deletions(-)

diff --git a/architecture_simulator/uarch/riscv/pipeline.py b/architecture_simulator/uarch/riscv/pipeline.py
index 81006630..4564be5d 100644
--- a/architecture_simulator/uarch/riscv/pipeline.py
+++ b/architecture_simulator/uarch/riscv/pipeline.py
@@ -45,7 +45,7 @@ def __init__(
         # if != None: [stage to cause stall, remaining duration]
         self.stalled: list[int] | None = None
         # holds the old content of the first stage, since the first stage must not be rerun
-        self.stalled_pipeline_reg: PipelineRegister | None = None
+        self.stalled_pipeline_regs: list[PipelineRegister] | None = None
 
     def step(self):
         """the pipeline step method, this is the central part of the pipeline! Every time it is called, it does one
@@ -60,28 +60,30 @@ def step(self):
                         next_pipeline_registers[0] = self.pipeline_registers[0]
                         continue
                     elif (
-                        index == 1
-                    ):  # second stage must get the old content of the pipelineregister of the first stage when stalling
-                        tmp = self.pipeline_registers[0]
-                        self.pipeline_registers[0] = self.stalled_pipeline_reg
+                        index == self.stalled[0] + 1
+                    ):  # first stage after the stalled stages must get an empty PipelineRegister while stalling
+                        tmp = self.pipeline_registers[self.stalled[0]]
+                        self.pipeline_registers[self.stalled[0]] = PipelineRegister()
                         next_pipeline_registers[index] = self.stages[index].behavior(
                             pipeline_registers=self.pipeline_registers,
                             index_of_own_input_register=(index - 1),
                             state=self.state,
                         )
-                        self.pipeline_registers[0] = tmp
+                        self.pipeline_registers[self.stalled[0]] = tmp
                         continue
                     elif (
-                        index == self.stalled[0] + 1
-                    ):  # first stage after the stalled stages must get and empty PipelineRegister while stalling
-                        tmp = self.pipeline_registers[self.stalled[0]]
-                        self.pipeline_registers[self.stalled[0]] = PipelineRegister()
+                        index <= self.stalled[0]
+                    ):  # Other stalled stages should get the old PipelineRegister values NOTE: This is fine, because the only instruction that stalls in EX is ecall and ecall does not get it´s register values from the previous PipelineRegister
+                        tmp = self.pipeline_registers[index - 1]
+                        self.pipeline_registers[index - 1] = self.stalled_pipeline_regs[
+                            index - 1
+                        ]
                         next_pipeline_registers[index] = self.stages[index].behavior(
                             pipeline_registers=self.pipeline_registers,
                             index_of_own_input_register=(index - 1),
                             state=self.state,
                         )
-                        self.pipeline_registers[self.stalled[0]] = tmp
+                        self.pipeline_registers[index - 1] = tmp
                         continue
                 next_pipeline_registers[index] = self.stages[index].behavior(
                     pipeline_registers=self.pipeline_registers,
@@ -116,8 +118,11 @@ def step(self):
                 break
 
         # Keep the old value of the first pipeline register
-        if self.stalled and self.stalled_pipeline_reg is None:
-            self.stalled_pipeline_reg = self.pipeline_registers[0]
+        if self.stalled and self.stalled_pipeline_regs is None:
+            self.stalled_pipeline_regs = self.pipeline_registers[: self.stalled[0]]
+
+            for reg in self.stalled_pipeline_regs:
+                reg.is_of_stalled_value = True
 
         self.pipeline_registers = next_pipeline_registers
 
@@ -126,7 +131,7 @@ def step(self):
             self.stalled[1] -= 1
             if self.stalled[1] == 0:
                 self.stalled = None
-                self.stalled_pipeline_reg = None
+                self.stalled_pipeline_regs = None
 
         # if one of the stages wants to flush, do so (starting from the back makes sense)
         for index, pipeline_register in reversed(
@@ -146,7 +151,7 @@ def step(self):
                 # Unstall stages that have been flushed
                 if self.stalled is not None and self.stalled[0] < num_to_flush:
                     self.stalled = None
-                    self.stalled_pipeline_reg = None
+                    self.stalled_pipeline_regs = None
 
                 break  # break since we don't care about the previous stages
 
diff --git a/architecture_simulator/uarch/riscv/pipeline_registers.py b/architecture_simulator/uarch/riscv/pipeline_registers.py
index fcd69dcf..71dd00ea 100644
--- a/architecture_simulator/uarch/riscv/pipeline_registers.py
+++ b/architecture_simulator/uarch/riscv/pipeline_registers.py
@@ -22,6 +22,9 @@ class PipelineRegister:
     stall_signal: Optional[StallSignal] = None
     abbreviation = "Single"
 
+    # True, if the register is being separately preserved by the pipeline for stalling
+    is_of_stalled_value: bool = False
+
 
 @dataclass
 class InstructionFetchPipelineRegister(PipelineRegister):
diff --git a/architecture_simulator/uarch/riscv/stages.py b/architecture_simulator/uarch/riscv/stages.py
index 856457cb..2d724f65 100644
--- a/architecture_simulator/uarch/riscv/stages.py
+++ b/architecture_simulator/uarch/riscv/stages.py
@@ -236,21 +236,23 @@ def behavior(
         )
 
         # ECALL needs some special behavior (flush and print to output)
-        flush_signal = None
+        stall_signal = None
         if isinstance(pipeline_register.instruction, ECALL):
-            # assume that all further stages need to be empty
-            for other_pr in pipeline_registers[index_of_own_input_register + 1 : -1]:
+            # assume that all further stages need to be empty, unless this stage is already stalled and the value of the next register is only for display purposes
+            for other_pr in pipeline_registers[
+                index_of_own_input_register
+                + 1
+                + int(pipeline_register.is_of_stalled_value) : -1
+            ]:
                 if not isinstance(other_pr.instruction, EmptyInstruction):
                     assert pipeline_register.address_of_instruction is not None
-                    flush_signal = FlushSignal(
-                        True, pipeline_register.address_of_instruction
-                    )
+                    stall_signal = StallSignal(2)
                     break
-            if flush_signal is None:
+            if stall_signal is None:
                 pipeline_register.instruction.behavior(state)
 
         return ExecutePipelineRegister(
-            flush_signal=flush_signal,
+            stall_signal=stall_signal,
             instruction=pipeline_register.instruction,
             alu_in_1=alu_in_1,
             alu_in_2=alu_in_2,
diff --git a/tests/test_ecalls.py b/tests/test_ecalls.py
index 16e329a3..8449109d 100644
--- a/tests/test_ecalls.py
+++ b/tests/test_ecalls.py
@@ -93,4 +93,26 @@ def test_five_stage_ecalls(self):
         )
         simulation.run()
         self.assertEqual(simulation.get_output(), "Kaesekuchen ist toll.")
-        self.assertEqual(simulation.get_performance_metrics().cycles, 13)
+        self.assertEqual(simulation.get_performance_metrics().cycles, 12)
+
+    def test_five_stage_ecalls_2(self):
+        simulation = RiscvSimulation(mode="five_stage_pipeline")
+        simulation.load_program(
+            """
+.data
+    kaesekuchen: .string "Kaesekuchen ist toll."
+.text
+la a0, kaesekuchen
+li a7, 2
+beq zero, zero, label
+nop
+nop
+nop
+label:
+add a7, a7, a7
+ecall
+"""
+        )
+        simulation.run()
+        self.assertEqual(simulation.get_output(), "Kaesekuchen ist toll.")
+        # NOTE: This works, because the ecall reads the register values directly and not out of the pipeline registers

From 826f9427d60bdfb3bbd87c5f27a6a8c850f098c1 Mon Sep 17 00:00:00 2001
From: MartinRoehm <martin.roehm@student.uni-tuebingen.de>
Date: Thu, 11 Apr 2024 11:14:53 +0200
Subject: [PATCH 07/19] add comments and tests for pipeline stall

---
 .../uarch/riscv/pipeline.py                   | 12 +++++-----
 tests/test_riscv_pipeline.py                  | 22 +++++++++++++++++++
 2 files changed, 29 insertions(+), 5 deletions(-)

diff --git a/architecture_simulator/uarch/riscv/pipeline.py b/architecture_simulator/uarch/riscv/pipeline.py
index 4564be5d..e2a86ef8 100644
--- a/architecture_simulator/uarch/riscv/pipeline.py
+++ b/architecture_simulator/uarch/riscv/pipeline.py
@@ -42,9 +42,9 @@ def __init__(
             PipelineRegister()
         ] * self.num_stages
 
-        # if != None: [stage to cause stall, remaining duration]
+        # if != None: [index of stage to cause stall, remaining duration of stall]
         self.stalled: list[int] | None = None
-        # holds the old content of the first stage, since the first stage must not be rerun
+        # holds the old contents of pipeline registers that are used as input for stalled stages
         self.stalled_pipeline_regs: list[PipelineRegister] | None = None
 
     def step(self):
@@ -73,7 +73,7 @@ def step(self):
                         continue
                     elif (
                         index <= self.stalled[0]
-                    ):  # Other stalled stages should get the old PipelineRegister values NOTE: This is fine, because the only instruction that stalls in EX is ecall and ecall does not get it´s register values from the previous PipelineRegister
+                    ):  # other stalled stages should get the old PipelineRegister values stored in stalled_pipeline_regs
                         tmp = self.pipeline_registers[index - 1]
                         self.pipeline_registers[index - 1] = self.stalled_pipeline_regs[
                             index - 1
@@ -85,11 +85,13 @@ def step(self):
                         )
                         self.pipeline_registers[index - 1] = tmp
                         continue
+
                 next_pipeline_registers[index] = self.stages[index].behavior(
                     pipeline_registers=self.pipeline_registers,
                     index_of_own_input_register=(index - 1),
                     state=self.state,
                 )
+
             except Exception as e:
                 if index - 1 >= 0:
                     raise InstructionExecutionException(
@@ -104,7 +106,7 @@ def step(self):
                 else:
                     raise
 
-        # Check if a stage has produced a stall signal
+        # Check if a stage has produced a meaningfull stall signal
         for index, pipeline_register in reversed(
             list(enumerate(next_pipeline_registers))
         ):
@@ -117,7 +119,7 @@ def step(self):
                 self.state.performance_metrics.stalls += 1
                 break
 
-        # Keep the old value of the first pipeline register
+        # keep PipelineRegister values in stalled_pipeline_regs
         if self.stalled and self.stalled_pipeline_regs is None:
             self.stalled_pipeline_regs = self.pipeline_registers[: self.stalled[0]]
 
diff --git a/tests/test_riscv_pipeline.py b/tests/test_riscv_pipeline.py
index 4a922067..881a5b18 100644
--- a/tests/test_riscv_pipeline.py
+++ b/tests/test_riscv_pipeline.py
@@ -1396,3 +1396,25 @@ def test_stall(self):
         self.assertEqual(sim.state.performance_metrics.cycles, 8)
         self.assertEqual(sim.state.performance_metrics.stalls, 1)
         self.assertEqual(sim.state.performance_metrics.flushes, 0)
+
+    def test_stall_2(self):
+        program = """
+        add x0, x0, x0
+        add x0, x0, x0
+        addi x1, x0, 11
+        addi x2, x1, 3
+        addi x3, x1, 4
+        addi x4, x2, 100
+        """
+
+        sim = RiscvSimulation(mode="five_stage_pipeline")
+
+        sim.load_program(program)
+        sim.run()
+        self.assertEqual(sim.state.register_file.registers[1], 11)
+        self.assertEqual(sim.state.register_file.registers[2], 14)
+        self.assertEqual(sim.state.register_file.registers[3], 15)
+        self.assertEqual(sim.state.register_file.registers[4], 114)
+        self.assertEqual(sim.state.performance_metrics.cycles, 14)
+        self.assertEqual(sim.state.performance_metrics.stalls, 2)
+        self.assertEqual(sim.state.performance_metrics.flushes, 0)

From e0a92adf2446c3b66a6b67a0c4431481d0acff78 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Richard=20M=C3=BCller?=
 <ri.mueller@student.uni-tuebingen.de>
Date: Fri, 12 Apr 2024 10:40:07 +0200
Subject: [PATCH 08/19] Exit codes now get printed again

---
 webgui/src/components/riscv/RiscvRegistersOutput.vue | 1 +
 1 file changed, 1 insertion(+)

diff --git a/webgui/src/components/riscv/RiscvRegistersOutput.vue b/webgui/src/components/riscv/RiscvRegistersOutput.vue
index 0d4b6cbe..3bbf67e8 100644
--- a/webgui/src/components/riscv/RiscvRegistersOutput.vue
+++ b/webgui/src/components/riscv/RiscvRegistersOutput.vue
@@ -17,6 +17,7 @@ const additionalMessageGetter = () => simulationStore.output;
             class="output"
             :simulation-store="simulationStore"
             :additional-message-getter
+            :exit-code="simulationStore.exitCode"
         />
     </div>
 </template>

From 34018a3512699cea39b40b53b9f7df744336e246 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Richard=20M=C3=BCller?=
 <ri.mueller@student.uni-tuebingen.de>
Date: Mon, 15 Apr 2024 08:37:49 +0200
Subject: [PATCH 09/19] Added the performance metrics tooltip to Toy

---
 webgui/src/components/toy/ToyControlBar.vue | 11 ++++++++++-
 1 file changed, 10 insertions(+), 1 deletion(-)

diff --git a/webgui/src/components/toy/ToyControlBar.vue b/webgui/src/components/toy/ToyControlBar.vue
index 5ccaec10..f9d9eeee 100644
--- a/webgui/src/components/toy/ToyControlBar.vue
+++ b/webgui/src/components/toy/ToyControlBar.vue
@@ -3,6 +3,10 @@
 import ToyElementToggle from "./ToyElementToggle.vue";
 import ToyControlButtons from "./ToyControlButtons.vue";
 import ToyVisToggle from "./ToyVisToggle.vue";
+import PerformanceMetrics from "../PerformanceMetrics.vue";
+import { useToySimulationStore } from "@/js/toy_simulation_store";
+
+const simulationStore = useToySimulationStore();
 </script>
 
 <template>
@@ -10,6 +14,10 @@ import ToyVisToggle from "./ToyVisToggle.vue";
         <ToyControlButtons />
         <ToyElementToggle class="ms-3" />
         <ToyVisToggle class="ms-auto me-3" />
+        <PerformanceMetrics
+            :simulation-store
+            class="performance-metrics me-3"
+        />
         <button
             class="archsim-icon-button settings-button"
             title="settings"
@@ -22,7 +30,8 @@ import ToyVisToggle from "./ToyVisToggle.vue";
 </template>
 
 <style scoped>
-.settings-button {
+.settings-button,
+.performance-metrics {
     font-size: 1.5rem;
 }
 

From 981c248b4b05202b8ac9192cd2244204db910804 Mon Sep 17 00:00:00 2001
From: MartinRoehm <martin.roehm@student.uni-tuebingen.de>
Date: Tue, 23 Apr 2024 10:11:09 +0200
Subject: [PATCH 10/19] fix jal related tests

---
 .../isa/riscv/instruction_types.py            |  2 +-
 tests/test_riscv_instructions.py              | 26 +++++++++----------
 tests/test_riscv_parser.py                    | 11 ++++----
 tests/test_riscv_simulation.py                |  4 +--
 4 files changed, 22 insertions(+), 21 deletions(-)

diff --git a/architecture_simulator/isa/riscv/instruction_types.py b/architecture_simulator/isa/riscv/instruction_types.py
index e00a111b..b4ac81f9 100644
--- a/architecture_simulator/isa/riscv/instruction_types.py
+++ b/architecture_simulator/isa/riscv/instruction_types.py
@@ -420,7 +420,7 @@ def __init__(self, rd: int, imm: int, abs_addr: int, **args):
         super().__init__(**args)
         self.rd = rd
         self.imm = (imm & (2**20) - 1) - (imm & 2**20)  # 21-bit sext
-        self.abs_addr = abs_addr
+        self.abs_addr = abs_addr  # only used in __repr__
 
     def __repr__(self) -> str:
         return f"{self.mnemonic} x{self.rd}, {self.abs_addr}"
diff --git a/tests/test_riscv_instructions.py b/tests/test_riscv_instructions.py
index 178c1ef8..f0506c22 100644
--- a/tests/test_riscv_instructions.py
+++ b/tests/test_riscv_instructions.py
@@ -2196,49 +2196,49 @@ def test_auipc(self):
         self.assertEqual(int(state.register_file.registers[0]), fixedint.UInt32(-4092))
 
     def test_jtype(self):
-        jtype = JAL(rd=0, imm=0)
+        jtype = JAL(rd=0, imm=0, abs_addr=-1)
         self.assertEqual(jtype.imm, 0)
-        jtype = JAL(rd=0, imm=2)
+        jtype = JAL(rd=0, imm=2, abs_addr=-1)
         self.assertEqual(jtype.imm, 2)
-        jtype = JAL(rd=0, imm=-2)
+        jtype = JAL(rd=0, imm=-2, abs_addr=-1)
         self.assertEqual(jtype.imm, -2)
-        jtype = JAL(rd=0, imm=(2**20) - 2)
+        jtype = JAL(rd=0, imm=(2**20) - 2, abs_addr=-1)
         self.assertEqual(jtype.imm, (2**20) - 2)
-        jtype = JAL(rd=0, imm=-(2**20))
+        jtype = JAL(rd=0, imm=-(2**20), abs_addr=-1)
         self.assertEqual(jtype.imm, -(2**20))
-        jtype = JAL(rd=0, imm=(2**20))
+        jtype = JAL(rd=0, imm=(2**20), abs_addr=-1)
         self.assertEqual(jtype.imm, -(2**20))
-        jtype = JAL(rd=0, imm=-(2**20) - 2)
+        jtype = JAL(rd=0, imm=-(2**20) - 2, abs_addr=-1)
         self.assertEqual(jtype.imm, (2**20) - 2)
 
     def test_jal(self):
         state = RiscvArchitecturalState(register_file=RegisterFile(registers=[1, 1, 1]))
         state.program_counter = 0
-        jal_1 = JAL(rd=0, imm=4)
+        jal_1 = JAL(rd=0, imm=4, abs_addr=-1)
         state = jal_1.behavior(state)
         self.assertEqual(state.program_counter, 0)
         self.assertEqual(int(state.register_file.registers[0]), 4)
 
         state.program_counter = 2
-        jal_2 = JAL(rd=0, imm=10)
+        jal_2 = JAL(rd=0, imm=10, abs_addr=-1)
         state = jal_2.behavior(state)
         self.assertEqual(state.program_counter, 8)
         self.assertEqual(int(state.register_file.registers[0]), 6)
 
         state.program_counter = 2
-        jal_3 = JAL(rd=0, imm=8)
+        jal_3 = JAL(rd=0, imm=8, abs_addr=-1)
         state = jal_3.behavior(state)
         self.assertEqual(state.program_counter, 6)
         self.assertEqual(int(state.register_file.registers[0]), 6)
 
         state.program_counter = 4
-        jal_4 = JAL(rd=1, imm=8)
+        jal_4 = JAL(rd=1, imm=8, abs_addr=-1)
         state = jal_4.behavior(state)
         self.assertEqual(state.program_counter, 8)
         self.assertEqual(int(state.register_file.registers[1]), 8)
 
         state.program_counter = 8
-        jal_5 = JAL(rd=1, imm=10)
+        jal_5 = JAL(rd=1, imm=10, abs_addr=-1)
         state = jal_5.behavior(state)
         self.assertEqual(state.program_counter, 14)
         self.assertEqual(int(state.register_file.registers[1]), 12)
@@ -2412,7 +2412,7 @@ def test_repr_1(self):
         self.assertEqual(u_type_ex_auipc.__repr__(), "auipc x31, -4")
 
         # Test J-Type
-        j_type_ex_jal = JAL(rd=23, imm=60)
+        j_type_ex_jal = JAL(rd=23, imm=60, abs_addr=60)
         self.assertEqual(j_type_ex_jal.__repr__(), "jal x23, 60")
 
         # TODO: Change me, if Fence gets implemented
diff --git a/tests/test_riscv_parser.py b/tests/test_riscv_parser.py
index fd032ab2..60a28c6d 100644
--- a/tests/test_riscv_parser.py
+++ b/tests/test_riscv_parser.py
@@ -198,7 +198,8 @@ def assert_inst_values(self, instr):
         # jal x20, 220
         self.assertIsInstance(instr[6], JAL)
         self.assertEqual(instr[6].rd, 20)
-        self.assertEqual(instr[6].imm, 220)
+        self.assertEqual(instr[6].imm, 196)
+        self.assertEqual(instr[6].abs_addr, 220)
 
         # bne x3, x10, Banane
         self.assertIsInstance(instr[7], BNE)
@@ -461,8 +462,8 @@ def test_neg_imm_where_lables_are_accepted(self):
         self.assertEqual(instr[0].imm, -4)
         self.assertEqual(instr[1].imm, -4)
         self.assertEqual(instr[2].imm, 8)
-        self.assertEqual(instr[3].imm, -12)
-        self.assertEqual(instr[4].imm, 8)
+        self.assertEqual(instr[3].imm, -24)
+        self.assertEqual(instr[4].imm, -8)
         self.assertEqual(instr[5].imm, -20)
 
     def test_hex_imm(self):
@@ -487,7 +488,7 @@ def test_hex_imm(self):
         self.assertEqual(instr[3].imm, 0x11)
         self.assertEqual(instr[4].imm, -0xAC)
         self.assertEqual(instr[5].imm, -0xAF)
-        self.assertEqual(instr[6].imm, 0x3A)
+        self.assertEqual(instr[6].imm, 34)
         self.assertEqual(instr[7].csr, 0x448)
         self.assertEqual(instr[8].csr, 0x448)
         self.assertEqual(instr[8].uimm, 0x1F)
@@ -514,7 +515,7 @@ def test_bin_imm(self):
         self.assertEqual(instr[3].imm, 0x11)
         self.assertEqual(instr[4].imm, -0xAC)
         self.assertEqual(instr[5].imm, -0xAF)
-        self.assertEqual(instr[6].imm, 0x3A)
+        self.assertEqual(instr[6].imm, 34)
         self.assertEqual(instr[7].csr, 0x448)
         self.assertEqual(instr[8].csr, 0x448)
         self.assertEqual(instr[8].uimm, 0x1F)
diff --git a/tests/test_riscv_simulation.py b/tests/test_riscv_simulation.py
index a775fd88..862cef4f 100644
--- a/tests/test_riscv_simulation.py
+++ b/tests/test_riscv_simulation.py
@@ -116,10 +116,10 @@ def test_run_simulation(self):
         )
         simulation.state.instruction_memory.instructions = {
             0: ADDI(rd=3, rs1=0, imm=8),
-            4: JAL(rd=2, imm=8),
+            4: JAL(rd=2, imm=8, abs_addr=12),
             8: ADDI(rd=1, rs1=1, imm=1),
             12: BEQ(rs1=0, rs2=0, imm=4),
-            16: JAL(rd=2, imm=4),
+            16: JAL(rd=2, imm=4, abs_addr=20),
             20: ADDI(rd=1, rs1=1, imm=-10),
         }
         simulation.run()

From 0e969ee61c287b72c4d1a8a2c3c8561cb906444b Mon Sep 17 00:00:00 2001
From: MartinRoehm <martin.roehm@student.uni-tuebingen.de>
Date: Tue, 23 Apr 2024 09:59:16 +0200
Subject: [PATCH 11/19] make addr in jal, x0, addr an abs value

---
 architecture_simulator/isa/riscv/instruction_types.py  | 5 +++--
 architecture_simulator/isa/riscv/riscv_parser.py       | 3 +++
 architecture_simulator/isa/riscv/rv32i_instructions.py | 4 ++--
 3 files changed, 8 insertions(+), 4 deletions(-)

diff --git a/architecture_simulator/isa/riscv/instruction_types.py b/architecture_simulator/isa/riscv/instruction_types.py
index a925df66..e00a111b 100644
--- a/architecture_simulator/isa/riscv/instruction_types.py
+++ b/architecture_simulator/isa/riscv/instruction_types.py
@@ -416,13 +416,14 @@ def access_register_file(
 
 
 class JTypeInstruction(RiscvInstruction):
-    def __init__(self, rd: int, imm: int, **args):
+    def __init__(self, rd: int, imm: int, abs_addr: int, **args):
         super().__init__(**args)
         self.rd = rd
         self.imm = (imm & (2**20) - 1) - (imm & 2**20)  # 21-bit sext
+        self.abs_addr = abs_addr
 
     def __repr__(self) -> str:
-        return f"{self.mnemonic} x{self.rd}, {self.imm}"
+        return f"{self.mnemonic} x{self.rd}, {self.abs_addr}"
 
     def control_unit_signals(self) -> ControlUnitSignals:
         return ControlUnitSignals(
diff --git a/architecture_simulator/isa/riscv/riscv_parser.py b/architecture_simulator/isa/riscv/riscv_parser.py
index 832a32d6..81619745 100644
--- a/architecture_simulator/isa/riscv/riscv_parser.py
+++ b/architecture_simulator/isa/riscv/riscv_parser.py
@@ -748,11 +748,14 @@ def _write_instructions(self) -> None:
                     line_number=line_number,
                     line=line,
                 )
+                if line_parsed.get("imm"):
+                    imm_val -= address_count
 
                 instructions.append(
                     instruction_class(
                         rd=self._convert_register_name(line_parsed.rd),
                         imm=imm_val,
+                        abs_addr=imm_val + address_count,
                     )
                 )
             elif issubclass(instruction_class, instruction_types.CSRTypeInstruction):
diff --git a/architecture_simulator/isa/riscv/rv32i_instructions.py b/architecture_simulator/isa/riscv/rv32i_instructions.py
index ece39060..fdb224f9 100644
--- a/architecture_simulator/isa/riscv/rv32i_instructions.py
+++ b/architecture_simulator/isa/riscv/rv32i_instructions.py
@@ -1217,8 +1217,8 @@ def alu_compute(
 
 
 class JAL(JTypeInstruction):
-    def __init__(self, rd: int, imm: int):
-        super().__init__(rd, imm, mnemonic="jal")
+    def __init__(self, rd: int, imm: int, abs_addr: int):
+        super().__init__(rd, imm, abs_addr, mnemonic="jal")
 
     def behavior(
         self, architectural_state: RiscvArchitecturalState

From 6ebbbff93a2dbcba2751227a020e1e9815d9752e Mon Sep 17 00:00:00 2001
From: MartinRoehm <martin.roehm@student.uni-tuebingen.de>
Date: Tue, 23 Apr 2024 10:11:09 +0200
Subject: [PATCH 12/19] fix jal related tests

---
 .../isa/riscv/instruction_types.py            |  2 +-
 tests/test_riscv_instructions.py              | 26 +++++++++----------
 tests/test_riscv_parser.py                    | 11 ++++----
 tests/test_riscv_simulation.py                |  4 +--
 4 files changed, 22 insertions(+), 21 deletions(-)

diff --git a/architecture_simulator/isa/riscv/instruction_types.py b/architecture_simulator/isa/riscv/instruction_types.py
index e00a111b..b4ac81f9 100644
--- a/architecture_simulator/isa/riscv/instruction_types.py
+++ b/architecture_simulator/isa/riscv/instruction_types.py
@@ -420,7 +420,7 @@ def __init__(self, rd: int, imm: int, abs_addr: int, **args):
         super().__init__(**args)
         self.rd = rd
         self.imm = (imm & (2**20) - 1) - (imm & 2**20)  # 21-bit sext
-        self.abs_addr = abs_addr
+        self.abs_addr = abs_addr  # only used in __repr__
 
     def __repr__(self) -> str:
         return f"{self.mnemonic} x{self.rd}, {self.abs_addr}"
diff --git a/tests/test_riscv_instructions.py b/tests/test_riscv_instructions.py
index 178c1ef8..f0506c22 100644
--- a/tests/test_riscv_instructions.py
+++ b/tests/test_riscv_instructions.py
@@ -2196,49 +2196,49 @@ def test_auipc(self):
         self.assertEqual(int(state.register_file.registers[0]), fixedint.UInt32(-4092))
 
     def test_jtype(self):
-        jtype = JAL(rd=0, imm=0)
+        jtype = JAL(rd=0, imm=0, abs_addr=-1)
         self.assertEqual(jtype.imm, 0)
-        jtype = JAL(rd=0, imm=2)
+        jtype = JAL(rd=0, imm=2, abs_addr=-1)
         self.assertEqual(jtype.imm, 2)
-        jtype = JAL(rd=0, imm=-2)
+        jtype = JAL(rd=0, imm=-2, abs_addr=-1)
         self.assertEqual(jtype.imm, -2)
-        jtype = JAL(rd=0, imm=(2**20) - 2)
+        jtype = JAL(rd=0, imm=(2**20) - 2, abs_addr=-1)
         self.assertEqual(jtype.imm, (2**20) - 2)
-        jtype = JAL(rd=0, imm=-(2**20))
+        jtype = JAL(rd=0, imm=-(2**20), abs_addr=-1)
         self.assertEqual(jtype.imm, -(2**20))
-        jtype = JAL(rd=0, imm=(2**20))
+        jtype = JAL(rd=0, imm=(2**20), abs_addr=-1)
         self.assertEqual(jtype.imm, -(2**20))
-        jtype = JAL(rd=0, imm=-(2**20) - 2)
+        jtype = JAL(rd=0, imm=-(2**20) - 2, abs_addr=-1)
         self.assertEqual(jtype.imm, (2**20) - 2)
 
     def test_jal(self):
         state = RiscvArchitecturalState(register_file=RegisterFile(registers=[1, 1, 1]))
         state.program_counter = 0
-        jal_1 = JAL(rd=0, imm=4)
+        jal_1 = JAL(rd=0, imm=4, abs_addr=-1)
         state = jal_1.behavior(state)
         self.assertEqual(state.program_counter, 0)
         self.assertEqual(int(state.register_file.registers[0]), 4)
 
         state.program_counter = 2
-        jal_2 = JAL(rd=0, imm=10)
+        jal_2 = JAL(rd=0, imm=10, abs_addr=-1)
         state = jal_2.behavior(state)
         self.assertEqual(state.program_counter, 8)
         self.assertEqual(int(state.register_file.registers[0]), 6)
 
         state.program_counter = 2
-        jal_3 = JAL(rd=0, imm=8)
+        jal_3 = JAL(rd=0, imm=8, abs_addr=-1)
         state = jal_3.behavior(state)
         self.assertEqual(state.program_counter, 6)
         self.assertEqual(int(state.register_file.registers[0]), 6)
 
         state.program_counter = 4
-        jal_4 = JAL(rd=1, imm=8)
+        jal_4 = JAL(rd=1, imm=8, abs_addr=-1)
         state = jal_4.behavior(state)
         self.assertEqual(state.program_counter, 8)
         self.assertEqual(int(state.register_file.registers[1]), 8)
 
         state.program_counter = 8
-        jal_5 = JAL(rd=1, imm=10)
+        jal_5 = JAL(rd=1, imm=10, abs_addr=-1)
         state = jal_5.behavior(state)
         self.assertEqual(state.program_counter, 14)
         self.assertEqual(int(state.register_file.registers[1]), 12)
@@ -2412,7 +2412,7 @@ def test_repr_1(self):
         self.assertEqual(u_type_ex_auipc.__repr__(), "auipc x31, -4")
 
         # Test J-Type
-        j_type_ex_jal = JAL(rd=23, imm=60)
+        j_type_ex_jal = JAL(rd=23, imm=60, abs_addr=60)
         self.assertEqual(j_type_ex_jal.__repr__(), "jal x23, 60")
 
         # TODO: Change me, if Fence gets implemented
diff --git a/tests/test_riscv_parser.py b/tests/test_riscv_parser.py
index fd032ab2..60a28c6d 100644
--- a/tests/test_riscv_parser.py
+++ b/tests/test_riscv_parser.py
@@ -198,7 +198,8 @@ def assert_inst_values(self, instr):
         # jal x20, 220
         self.assertIsInstance(instr[6], JAL)
         self.assertEqual(instr[6].rd, 20)
-        self.assertEqual(instr[6].imm, 220)
+        self.assertEqual(instr[6].imm, 196)
+        self.assertEqual(instr[6].abs_addr, 220)
 
         # bne x3, x10, Banane
         self.assertIsInstance(instr[7], BNE)
@@ -461,8 +462,8 @@ def test_neg_imm_where_lables_are_accepted(self):
         self.assertEqual(instr[0].imm, -4)
         self.assertEqual(instr[1].imm, -4)
         self.assertEqual(instr[2].imm, 8)
-        self.assertEqual(instr[3].imm, -12)
-        self.assertEqual(instr[4].imm, 8)
+        self.assertEqual(instr[3].imm, -24)
+        self.assertEqual(instr[4].imm, -8)
         self.assertEqual(instr[5].imm, -20)
 
     def test_hex_imm(self):
@@ -487,7 +488,7 @@ def test_hex_imm(self):
         self.assertEqual(instr[3].imm, 0x11)
         self.assertEqual(instr[4].imm, -0xAC)
         self.assertEqual(instr[5].imm, -0xAF)
-        self.assertEqual(instr[6].imm, 0x3A)
+        self.assertEqual(instr[6].imm, 34)
         self.assertEqual(instr[7].csr, 0x448)
         self.assertEqual(instr[8].csr, 0x448)
         self.assertEqual(instr[8].uimm, 0x1F)
@@ -514,7 +515,7 @@ def test_bin_imm(self):
         self.assertEqual(instr[3].imm, 0x11)
         self.assertEqual(instr[4].imm, -0xAC)
         self.assertEqual(instr[5].imm, -0xAF)
-        self.assertEqual(instr[6].imm, 0x3A)
+        self.assertEqual(instr[6].imm, 34)
         self.assertEqual(instr[7].csr, 0x448)
         self.assertEqual(instr[8].csr, 0x448)
         self.assertEqual(instr[8].uimm, 0x1F)
diff --git a/tests/test_riscv_simulation.py b/tests/test_riscv_simulation.py
index a775fd88..862cef4f 100644
--- a/tests/test_riscv_simulation.py
+++ b/tests/test_riscv_simulation.py
@@ -116,10 +116,10 @@ def test_run_simulation(self):
         )
         simulation.state.instruction_memory.instructions = {
             0: ADDI(rd=3, rs1=0, imm=8),
-            4: JAL(rd=2, imm=8),
+            4: JAL(rd=2, imm=8, abs_addr=12),
             8: ADDI(rd=1, rs1=1, imm=1),
             12: BEQ(rs1=0, rs2=0, imm=4),
-            16: JAL(rd=2, imm=4),
+            16: JAL(rd=2, imm=4, abs_addr=20),
             20: ADDI(rd=1, rs1=1, imm=-10),
         }
         simulation.run()

From 35ff8a74657310f9de4b1e4fd6e48fb67bdf9686 Mon Sep 17 00:00:00 2001
From: MartinRoehm <martin.roehm@student.uni-tuebingen.de>
Date: Tue, 23 Apr 2024 11:39:13 +0200
Subject: [PATCH 13/19] update jal help page

---
 webgui/src/components/riscv/RiscvHelp.vue | 9 +++++----
 1 file changed, 5 insertions(+), 4 deletions(-)

diff --git a/webgui/src/components/riscv/RiscvHelp.vue b/webgui/src/components/riscv/RiscvHelp.vue
index 483b8897..c1ba06d5 100644
--- a/webgui/src/components/riscv/RiscvHelp.vue
+++ b/webgui/src/components/riscv/RiscvHelp.vue
@@ -661,8 +661,9 @@
 
         <h3 id="j-type">J-Type</h3>
         <p>
-            The immediate (<code>imm</code>) has a length of 21 bits and is sign
-            extended to 32 bits.<br />
+            The address to jump to (<code>addr</code>), is encoded relative to
+            the current pc in a 21 bit immediate that is sign extended to 32
+            bits and added to the current pc.<br />
             Offsets are optional, and in hexadecimal format.
         </p>
         <div class="table-responsive">
@@ -678,12 +679,12 @@
                     <tr>
                         <td>
                             <code
-                                >JAL rd, imm<br />
+                                >JAL rd, addr<br />
                                 JAL rd, label+offset</code
                             >
                         </td>
                         <td>
-                            <code>rd = PC + 4; PC = PC + imm</code>
+                            <code>rd = PC + 4; PC = addr</code>
                         </td>
                         <td>
                             Jump and link.

From 9b85b1048ef593f5a4c19e97038fe4923e26034f Mon Sep 17 00:00:00 2001
From: Michael Kuhn <michael.kuhn@uni-tuebingen.de>
Date: Tue, 23 Apr 2024 13:06:56 +0200
Subject: [PATCH 14/19] handle python package as normal asset

---
 .github/workflows/python-publish.yml |  3 ---
 .gitlab-ci.yml                       |  2 --
 build.sh                             |  3 ---
 webgui/src/main.js                   |  3 ++-
 webgui/vite.config.js                | 10 ++++++++++
 5 files changed, 12 insertions(+), 9 deletions(-)

diff --git a/.github/workflows/python-publish.yml b/.github/workflows/python-publish.yml
index 4f23b8bc..241179de 100644
--- a/.github/workflows/python-publish.yml
+++ b/.github/workflows/python-publish.yml
@@ -50,9 +50,6 @@ jobs:
           pip install build
       - name: Build package
         run: python -m build
-      - name: Copy package to 'webgui'
-        run: |
-          cp dist/*.whl webgui/public/
       - name: Use Node.js
         uses: actions/setup-node@v3
         with:
diff --git a/.gitlab-ci.yml b/.gitlab-ci.yml
index e74eb0bd..a45553b3 100644
--- a/.gitlab-ci.yml
+++ b/.gitlab-ci.yml
@@ -48,8 +48,6 @@ build_webgui:
     - "build_py"
   image: node:20-alpine
   script:
-    - mkdir -p webgui/public
-    - cp dist/*.whl webgui/public
     - npm install
     - npm run build-dev-atreus
   artifacts:
diff --git a/build.sh b/build.sh
index 6a085426..af841d0a 100755
--- a/build.sh
+++ b/build.sh
@@ -5,9 +5,6 @@ set -e
 
 # build python package
 python -m build
-# ensure public folder is present and copy python package
-mkdir -p webgui/public/
-cp dist/*.whl webgui/public/
 # ensure custom markers are present in the svg
 python build_svg.py
 # ensure js packages are available and run npm scripts
diff --git a/webgui/src/main.js b/webgui/src/main.js
index a71c3298..9b43c69a 100644
--- a/webgui/src/main.js
+++ b/webgui/src/main.js
@@ -1,6 +1,7 @@
 import "./scss/styles.scss";
 import "./css/main.css";
 import "./css/splitjs.css";
+import architectureSimulatorPackageUrl from "../../dist/architecture_simulator-0.1.0-py3-none-any.whl";
 
 import { createApp } from "vue";
 
@@ -27,7 +28,7 @@ async function initializePyodide() {
     });
     await pyodide.loadPackage("micropip");
     const micropip = pyodide.pyimport("micropip");
-    await micropip.install("architecture_simulator-0.1.0-py3-none-any.whl");
+    await micropip.install(architectureSimulatorPackageUrl);
     await pyodide.runPython(`
 from architecture_simulator.gui.webgui import *
 `);
diff --git a/webgui/vite.config.js b/webgui/vite.config.js
index 8e03c391..3b7db74e 100644
--- a/webgui/vite.config.js
+++ b/webgui/vite.config.js
@@ -11,4 +11,14 @@ export default defineConfig({
             "@": fileURLToPath(new URL("./src", import.meta.url)),
         },
     },
+    assetsInclude: ["**/*.whl"],
+    build: {
+        rollupOptions: {
+            output: {
+                assetFileNames() {
+                    return "assets/[hash]/[name][extname]";
+                },
+            },
+        },
+    },
 });

From 7b878991b8596a1b0406cc108a54c6a08d209bc8 Mon Sep 17 00:00:00 2001
From: Michael Kuhn <michael.kuhn@uni-tuebingen.de>
Date: Wed, 24 Apr 2024 10:54:38 +0200
Subject: [PATCH 15/19] added dhrystone testcase

---
 tests/riscv_programs/dhrystone.s | 557 +++++++++++++++++++++++++++++++
 tests/test_dhrystone.py          |  13 +
 2 files changed, 570 insertions(+)
 create mode 100644 tests/riscv_programs/dhrystone.s
 create mode 100644 tests/test_dhrystone.py

diff --git a/tests/riscv_programs/dhrystone.s b/tests/riscv_programs/dhrystone.s
new file mode 100644
index 00000000..fc97bda1
--- /dev/null
+++ b/tests/riscv_programs/dhrystone.s
@@ -0,0 +1,557 @@
+
+main:
+addi	sp,sp,-128
+sw	ra,124(sp)
+sw	s0,120(sp)
+sw	s1,116(sp)
+sw	s2,112(sp)
+sw	s3,108(sp)
+sw	s4,104(sp)
+sw	s5,100(sp)
+sw	s6,96(sp)
+sw	s7,92(sp)
+sw	s8,88(sp)
+lui	a5,0x4
+addi	a5,a5,128 # 4080 <REC1>
+lui	a4,0x7
+sw	a5,-1796(a4) # 68fc <Next_Ptr_Glob>
+addi	a3,a5,64
+lui	a4,0x7
+sw	a3,-1792(a4) # 6900 <Ptr_Glob>
+sw	a5,64(a5)
+sw	zero,68(a5)
+addi	a4,zero,2
+sw	a4,72(a5)
+addi	a4,zero,40
+sw	a4,76(a5)
+lui	a4,0x4
+addi	a4,a4,0 # 4000 <Proc_6+0x385c>
+lw	t1,0(a4)
+lw	a7,4(a4)
+lw	a6,8(a4)
+lw	a0,12(a4)
+lw	a1,16(a4)
+lw	a2,20(a4)
+lw	a3,24(a4)
+sw	t1,80(a5)
+sw	a7,84(a5)
+sw	a6,88(a5)
+sw	a0,92(a5)
+sw	a1,96(a5)
+sw	a2,100(a5)
+sw	a3,104(a5)
+lhu	a3,28(a4)
+sh	a3,108(a5)
+lbu	a4,30(a4)
+sb	a4,110(a5)
+lui	a5,0x4
+addi	a5,a5,32 # 4020 <Proc_6+0x387c>
+lw	a7,0(a5)
+lw	a6,4(a5)
+lw	a0,8(a5)
+lw	a1,12(a5)
+lw	a2,16(a5)
+lw	a3,20(a5)
+lw	a4,24(a5)
+sw	a7,36(sp)
+sw	a6,40(sp)
+sw	a0,44(sp)
+sw	a1,48(sp)
+sw	a2,52(sp)
+sw	a3,56(sp)
+sw	a4,60(sp)
+lhu	a4,28(a5)
+sh	a4,64(sp)
+lbu	a5,30(a5)
+sb	a5,66(sp)
+lui	a5,0x5
+addi	a4,zero,10
+sw	a4,-2012(a5) # 4824 <Arr_2_Glob+0x65c>
+addi	s4,zero,1
+lui	s2,0x4
+addi	s2,s2,64 # 4040 <Proc_6+0x389c>
+lui	s8,0x7
+lui	s7,0x4
+addi	s7,s7,256 # 4100 <Arr_1_Glob>
+lui	s1,0x4
+addi	s1,s1,96 # 4060 <Proc_6+0x38bc>
+lui	s6,0x7
+jal	zero, main+0x1e4
+addi	s0,s0,1
+andi	s0,s0,255
+lbu	a5,-1808(s3)
+bltu	a5,s0, main+0x1bc
+addi	a1,zero,67
+addi	a0,s0,0
+jal	ra, Func_1
+lw	a5,68(sp)
+bne	a0,a5, main+0x134
+addi	a1,sp,68
+addi	a0,zero,0
+jal	ra, Proc_6
+lw	a6,0(s1)
+lw	a0,4(s1)
+lw	a1,8(s1)
+lw	a2,12(s1)
+lw	a3,16(s1)
+lw	a4,20(s1)
+lw	a5,24(s1)
+sw	a6,4(sp)
+sw	a0,8(sp)
+sw	a1,12(sp)
+sw	a2,16(sp)
+sw	a3,20(sp)
+sw	a4,24(sp)
+sw	a5,28(sp)
+lhu	a5,28(s1)
+sh	a5,32(sp)
+lbu	a5,30(s1)
+sb	a5,34(sp)
+sw	s4,-1800(s6) # 68f8 <Int_Glob>
+addi	s5,s4,0
+jal	zero, main+0x134
+addi	s5,zero,3
+slli	a5,s5,0x1
+add	a5,a5,s5
+lw	a4,72(sp)
+div	a5,a5,a4
+sw	a5,76(sp)
+addi	a0,sp,76
+jal	ra, Proc_2
+addi	s4,s4,1
+addi	a5,zero,51
+beq	s4,a5, main+0x2b4
+jal	ra, Proc_5
+jal	ra, Proc_4
+lw	a6,0(s2)
+lw	a0,4(s2)
+lw	a1,8(s2)
+lw	a2,12(s2)
+lw	a3,16(s2)
+lw	a4,20(s2)
+lw	a5,24(s2)
+sw	a6,4(sp)
+sw	a0,8(sp)
+sw	a1,12(sp)
+sw	a2,16(sp)
+sw	a3,20(sp)
+sw	a4,24(sp)
+sw	a5,28(sp)
+lhu	a5,28(s2)
+sh	a5,32(sp)
+lbu	a5,30(s2)
+sb	a5,34(sp)
+addi	a5,zero,1
+sw	a5,68(sp)
+addi	a1,sp,4
+addi	a0,sp,36
+jal	ra, Func_2
+sltiu	a0,a0,1
+sw	a0,-1804(s8) # 68f4 <Bool_Glob>
+addi	a5,zero,7
+sw	a5,72(sp)
+addi	a2,sp,72
+addi	a1,zero,3
+addi	a0,zero,2
+jal	ra, Proc_7
+addi	a5,zero,3
+sw	a5,76(sp)
+lw	a3,72(sp)
+addi	a2,zero,3
+lui	a1,0x4
+addi	a1,a1,456 # 41c8 <Arr_2_Glob>
+addi	a0,s7,0
+jal	ra, Proc_8
+lui	a5,0x7
+lw	a0,-1792(a5) # 6900 <Ptr_Glob>
+jal	ra, Proc_1
+lui	a5,0x7
+lbu	a4,-1808(a5) # 68f0 <Ch_2_Glob>
+addi	a5,zero,64
+bgeu	a5,a4, main+0x1b8
+addi	s0,zero,65
+addi	s5,zero,3
+lui	s3,0x7
+jal	zero, main+0x144
+addi	a7,zero,10
+ecall
+lw	ra,124(sp)
+lw	s0,120(sp)
+lw	s1,116(sp)
+lw	s2,112(sp)
+lw	s3,108(sp)
+lw	s4,104(sp)
+lw	s5,100(sp)
+lw	s6,96(sp)
+lw	s7,92(sp)
+lw	s8,88(sp)
+addi	sp,sp,128
+jalr	zero,0(ra)
+
+strcmp:
+or	a4,a0,a1
+addi	t2,zero,-1
+andi	a4,a4,3
+bne	a4,zero, strcmp+0x10c
+lui	a5,0x7f7f8
+addi	a5,a5,-129 # 7f7f7f7f <Ptr_Glob+0x7f7f167f>
+lw	a2,0(a0)
+lw	a3,0(a1)
+and	t0,a2,a5
+or	t1,a2,a5
+add	t0,t0,a5
+or	t0,t0,t1
+bne	t0,t2, strcmp+0x134
+bne	a2,a3, strcmp+0xc0
+lw	a2,4(a0)
+lw	a3,4(a1)
+and	t0,a2,a5
+or	t1,a2,a5
+add	t0,t0,a5
+or	t0,t0,t1
+bne	t0,t2, strcmp+0x12c
+bne	a2,a3, strcmp+0xc0
+lw	a2,8(a0)
+lw	a3,8(a1)
+and	t0,a2,a5
+or	t1,a2,a5
+add	t0,t0,a5
+or	t0,t0,t1
+bne	t0,t2, strcmp+0x140
+bne	a2,a3, strcmp+0xc0
+lw	a2,12(a0)
+lw	a3,12(a1)
+and	t0,a2,a5
+or	t1,a2,a5
+add	t0,t0,a5
+or	t0,t0,t1
+bne	t0,t2, strcmp+0x154
+bne	a2,a3, strcmp+0xc0
+lw	a2,16(a0)
+lw	a3,16(a1)
+and	t0,a2,a5
+or	t1,a2,a5
+add	t0,t0,a5
+or	t0,t0,t1
+bne	t0,t2, strcmp+0x168
+addi	a0,a0,20
+addi	a1,a1,20
+beq	a2,a3, strcmp+0x18
+slli	a4,a2,0x10
+slli	a5,a3,0x10
+bne	a4,a5, strcmp+0xe4
+srli	a4,a2,0x10
+srli	a5,a3,0x10
+sub	a0,a4,a5
+andi	a1,a0,255
+bne	a1,zero, strcmp+0xfc
+jalr	zero,0(ra)
+srli	a4,a4,0x10
+srli	a5,a5,0x10
+sub	a0,a4,a5
+andi	a1,a0,255
+bne	a1,zero, strcmp+0xfc
+jalr	zero,0(ra)
+andi	a4,a4,255
+andi	a5,a5,255
+sub	a0,a4,a5
+jalr	zero,0(ra)
+lbu	a2,0(a0)
+lbu	a3,0(a1)
+addi	a0,a0,1
+addi	a1,a1,1
+bne	a2,a3, strcmp+0x124
+bne	a2,zero, strcmp+0x10c
+sub	a0,a2,a3
+jalr	zero,0(ra)
+addi	a0,a0,4
+addi	a1,a1,4
+bne	a2,a3, strcmp+0x10c
+addi	a0,zero,0
+jalr	zero,0(ra)
+addi	a0,a0,8
+addi	a1,a1,8
+bne	a2,a3, strcmp+0x10c
+addi	a0,zero,0
+jalr	zero,0(ra)
+addi	a0,a0,12
+addi	a1,a1,12
+bne	a2,a3, strcmp+0x10c
+addi	a0,zero,0
+jalr	zero,0(ra)
+addi	a0,a0,16
+addi	a1,a1,16
+bne	a2,a3, strcmp+0x10c
+addi	a0,zero,0
+jalr	zero,0(ra)
+
+Proc_2:
+lui	a5,0x7
+lbu	a4,-1807(a5) # 68f1 <Ch_1_Glob>
+addi	a5,zero,65
+beq	a4,a5, Proc_2+0x14
+jalr	zero,0(ra)
+lw	a5,0(a0)
+addi	a5,a5,9
+lui	a4,0x7
+lw	a4,-1800(a4) # 68f8 <Int_Glob>
+sub	a5,a5,a4
+sw	a5,0(a0)
+jal	zero, Proc_2+0x10
+
+Proc_3:
+addi	sp,sp,-16
+sw	ra,12(sp)
+lui	a5,0x7
+lw	a5,-1792(a5) # 6900 <Ptr_Glob>
+beq	a5,zero, Proc_3+0x1c
+lw	a5,0(a5)
+sw	a5,0(a0)
+lui	a5,0x7
+lw	a2,-1792(a5) # 6900 <Ptr_Glob>
+addi	a2,a2,12
+lui	a5,0x7
+lw	a1,-1800(a5) # 68f8 <Int_Glob>
+addi	a0,zero,10
+jal	ra, Proc_7
+lw	ra,12(sp)
+addi	sp,sp,16
+jalr	zero,0(ra)
+
+Proc_1:
+addi	sp,sp,-16
+sw	ra,12(sp)
+sw	s0,8(sp)
+sw	s1,4(sp)
+addi	s1,a0,0
+lw	s0,0(a0)
+lui	a5,0x7
+lw	a5,-1792(a5) # 6900 <Ptr_Glob>
+lw	t4,0(a5)
+lw	t3,4(a5)
+lw	t1,8(a5)
+lw	a7,16(a5)
+lw	a6,20(a5)
+lw	a0,24(a5)
+lw	a1,28(a5)
+lw	a2,32(a5)
+lw	a3,36(a5)
+lw	a4,40(a5)
+lw	a5,44(a5)
+sw	t4,0(s0)
+sw	t3,4(s0)
+sw	t1,8(s0)
+sw	a7,16(s0)
+sw	a6,20(s0)
+sw	a0,24(s0)
+sw	a1,28(s0)
+sw	a2,32(s0)
+sw	a3,36(s0)
+sw	a4,40(s0)
+sw	a5,44(s0)
+addi	a5,zero,5
+sw	a5,12(s1)
+sw	a5,12(s0)
+lw	a5,0(s1)
+sw	a5,0(s0)
+addi	a0,s0,0
+jal	ra, Proc_3
+lw	a5,4(s0)
+beq	a5,zero, Proc_1+0x114
+lw	a5,0(s1)
+lw	t5,0(a5)
+lw	t4,4(a5)
+lw	t3,8(a5)
+lw	t1,12(a5)
+lw	a7,16(a5)
+lw	a6,20(a5)
+lw	a0,24(a5)
+lw	a1,28(a5)
+lw	a2,32(a5)
+lw	a3,36(a5)
+lw	a4,40(a5)
+lw	a5,44(a5)
+sw	t5,0(s1)
+sw	t4,4(s1)
+sw	t3,8(s1)
+sw	t1,12(s1)
+sw	a7,16(s1)
+sw	a6,20(s1)
+sw	a0,24(s1)
+sw	a1,28(s1)
+sw	a2,32(s1)
+sw	a3,36(s1)
+sw	a4,40(s1)
+sw	a5,44(s1)
+lw	ra,12(sp)
+lw	s0,8(sp)
+lw	s1,4(sp)
+addi	sp,sp,16
+jalr	zero,0(ra)
+addi	a5,zero,6
+sw	a5,12(s0)
+addi	a1,s0,8
+lw	a0,8(s1)
+jal	ra, Proc_6
+lui	a5,0x7
+lw	a5,-1792(a5) # 6900 <Ptr_Glob>
+lw	a5,0(a5)
+sw	a5,0(s0)
+addi	a2,s0,12
+addi	a1,zero,10
+lw	a0,12(s0)
+jal	ra, Proc_7
+jal	zero, Proc_1+0x100
+
+Proc_4:
+lui	a4,0x7
+lui	a5,0x7
+lbu	a5,-1807(a5) # 68f1 <Ch_1_Glob>
+addi	a5,a5,-65
+sltiu	a5,a5,1
+lw	a3,-1804(a4) # 68f4 <Bool_Glob>
+or	a5,a5,a3
+sw	a5,-1804(a4)
+lui	a5,0x7
+addi	a4,zero,66
+sb	a4,-1808(a5) # 68f0 <Ch_2_Glob>
+jalr	zero,0(ra)
+
+Proc_5:
+lui	a5,0x7
+addi	a4,zero,65
+sb	a4,-1807(a5) # 68f1 <Ch_1_Glob>
+lui	a5,0x7
+sw	zero,-1804(a5) # 68f4 <Bool_Glob>
+jalr	zero,0(ra)
+
+Proc_7:
+addi	a0,a0,2
+add	a0,a0,a1
+sw	a0,0(a2)
+jalr	zero,0(ra)
+
+Proc_8:
+addi	a4,a2,5
+slli	a6,a4,0x2
+add	a0,a0,a6
+sw	a3,0(a0)
+sw	a3,4(a0)
+sw	a4,120(a0)
+addi	a3,zero,200
+mul	a3,a4,a3
+slli	a5,a2,0x2
+add	a5,a5,a3
+add	a5,a1,a5
+sw	a4,20(a5)
+sw	a4,24(a5)
+lw	a4,16(a5)
+addi	a4,a4,1
+sw	a4,16(a5)
+lw	a4,0(a0)
+add	a1,a1,a3
+lui	a5,0x1
+add	a5,a5,a1
+add	a5,a5,a6
+sw	a4,-96(a5) # fa0 <Proc_6+0x7fc>
+lui	a5,0x7
+addi	a4,zero,5
+sw	a4,-1800(a5) # 68f8 <Int_Glob>
+jalr	zero,0(ra)
+
+Func_1:
+andi	a0,a0,255
+andi	a1,a1,255
+beq	a0,a1, Func_1+0x14
+addi	a0,zero,0
+jalr	zero,0(ra)
+lui	a5,0x7
+sb	a0,-1807(a5) # 68f1 <Ch_1_Glob>
+addi	a0,zero,1
+jalr	zero,0(ra)
+
+Func_2:
+addi	sp,sp,-32
+sw	ra,28(sp)
+sw	s0,24(sp)
+sw	s1,20(sp)
+sw	s2,16(sp)
+sw	s3,12(sp)
+addi	s1,a0,0
+addi	s2,a1,0
+addi	s0,zero,2
+addi	s3,zero,2
+add	a4,s2,s0
+add	a5,s1,s0
+lbu	a1,1(a4)
+lbu	a0,0(a5)
+jal	ra, Func_1
+sltiu	a0,a0,1
+add	s0,s0,a0
+bge	s3,s0, Func_2+0x28
+addi	a1,s2,0
+addi	a0,s1,0
+jal	ra, strcmp
+addi	a5,zero,0
+bge	zero,a0, Func_2+0x6c
+addi	s0,s0,7
+lui	a5,0x7
+sw	s0,-1800(a5) # 68f8 <Int_Glob>
+addi	a5,zero,1
+addi	a0,a5,0
+lw	ra,28(sp)
+lw	s0,24(sp)
+lw	s1,20(sp)
+lw	s2,16(sp)
+lw	s3,12(sp)
+addi	sp,sp,32
+jalr	zero,0(ra)
+
+Func_3:
+addi	a0,a0,-2
+sltiu	a0,a0,1
+jalr	zero,0(ra)
+
+Proc_6:
+addi	sp,sp,-16
+sw	ra,12(sp)
+sw	s0,8(sp)
+sw	s1,4(sp)
+addi	s0,a0,0
+addi	s1,a1,0
+jal	ra, Func_3
+addi	a5,s0,0
+bne	a0,zero, Proc_6+0x28
+addi	a5,zero,3
+sw	a5,0(s1)
+addi	a5,zero,2
+beq	s0,a5, Proc_6+0x8c
+bltu	a5,s0, Proc_6+0x54
+beq	s0,zero, Proc_6+0x68
+lui	a5,0x7
+lw	a4,-1800(a5) # 68f8 <Int_Glob>
+addi	a5,zero,100
+bge	a5,a4, Proc_6+0x80
+sw	zero,0(s1)
+jal	zero, Proc_6+0x6c
+addi	a5,zero,4
+bne	s0,a5, Proc_6+0x6c
+addi	a5,zero,2
+sw	a5,0(s1)
+jal	zero, Proc_6+0x6c
+sw	zero,0(s1)
+lw	ra,12(sp)
+lw	s0,8(sp)
+lw	s1,4(sp)
+addi	sp,sp,16
+jalr	zero,0(ra)
+addi	a5,zero,3
+sw	a5,0(s1)
+jal	zero, Proc_6+0x6c
+addi	a5,zero,1
+sw	a5,0(s1)
+jal	zero, Proc_6+0x6c
+
+
+.data
+rodata: .word 0x44485259, 0x53544f4e, 0x45205052, 0x4f475241, 0x4d2c2053, 0x4f4d4520, 0x53545249, 0x4e470000, 0x44485259, 0x53544f4e, 0x45205052, 0x4f475241, 0x4d2c2031, 0x27535420, 0x53545249, 0x4e470000, 0x44485259, 0x53544f4e, 0x45205052, 0x4f475241, 0x4d2c2032, 0x274e4420, 0x53545249, 0x4e470000, 0x44485259, 0x53544f4e, 0x45205052, 0x4f475241, 0x4d2c2033, 0x27524420, 0x53545249, 0x4e4700
diff --git a/tests/test_dhrystone.py b/tests/test_dhrystone.py
new file mode 100644
index 00000000..2eb8743a
--- /dev/null
+++ b/tests/test_dhrystone.py
@@ -0,0 +1,13 @@
+from unittest import TestCase
+from architecture_simulator.simulation.riscv_simulation import RiscvSimulation
+from fixedint import UInt32
+from pathlib import Path
+
+
+class TestDhrystone(TestCase):
+    def test_dhrystone(self) -> UInt32:
+        simulation = RiscvSimulation()
+        dhry_path = Path(__file__).parent / "riscv_programs" / "dhrystone.s"
+        simulation.load_program(dhry_path.read_text())
+        simulation.run()
+        return simulation.state.register_file.registers[10]

From 83e7ed64e3de08fd09ec33212c49f735349d159a Mon Sep 17 00:00:00 2001
From: Michael Kuhn <michael.kuhn@uni-tuebingen.de>
Date: Wed, 24 Apr 2024 10:55:21 +0200
Subject: [PATCH 16/19] fix promt

---
 architecture_simulator/cli/cli.py | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/architecture_simulator/cli/cli.py b/architecture_simulator/cli/cli.py
index beedbef3..7874c14c 100644
--- a/architecture_simulator/cli/cli.py
+++ b/architecture_simulator/cli/cli.py
@@ -106,7 +106,7 @@ def main():
     while True:
         read_command = []
         try:
-            read_command = session.prompt(">>>").strip().lower().split()
+            read_command = session.prompt(">>> ").strip().lower().split()
         except KeyboardInterrupt:
             break
         except EOFError:

From 0add9312816b0727af25ff2b584a8ebf565206d8 Mon Sep 17 00:00:00 2001
From: Michael Kuhn <michael.kuhn@uni-tuebingen.de>
Date: Wed, 24 Apr 2024 10:58:18 +0200
Subject: [PATCH 17/19] print instruction memory only on load

---
 architecture_simulator/cli/cli.py | 5 +++--
 1 file changed, 3 insertions(+), 2 deletions(-)

diff --git a/architecture_simulator/cli/cli.py b/architecture_simulator/cli/cli.py
index 7874c14c..1f942f0d 100644
--- a/architecture_simulator/cli/cli.py
+++ b/architecture_simulator/cli/cli.py
@@ -175,8 +175,6 @@ def display(sim: Union[ToySimulation, RiscvSimulation], display_mode: str) -> st
             res += hline
         res += f"PC: {sim.state.program_counter} | Instruction at PC: {'#####' if not sim.state.instruction_at_pc() else str(sim.state.instruction_memory.read_instruction(sim.state.program_counter))}\n"
         res += hline
-        res += "Instruction Memory:\n"
-        res += instr_mem_repr(sim)
         res += hline
         res += "Performance Metrics:\n"
         res += sim.state.performance_metrics.__repr__()
@@ -598,6 +596,9 @@ def __call__(
             output = "The provided file caused a parsing exception:\n"
             output += e.__repr__() + "\n"
             return CommandResult(output, sim)
+        if isinstance(new_sim, RiscvSimulation):
+            print("Instruction Memory:")
+            print(instr_mem_repr(new_sim))
         # Excecute load or step argument
         if "-run" in command:
             run_command = RunCommand()

From 29267e6f4172abc596833925fcf1ce2b9d274f0f Mon Sep 17 00:00:00 2001
From: Michael Kuhn <michael.kuhn@uni-tuebingen.de>
Date: Wed, 24 Apr 2024 10:59:10 +0200
Subject: [PATCH 18/19] print pc in hex

---
 architecture_simulator/cli/cli.py | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/architecture_simulator/cli/cli.py b/architecture_simulator/cli/cli.py
index 1f942f0d..a3c0dbf9 100644
--- a/architecture_simulator/cli/cli.py
+++ b/architecture_simulator/cli/cli.py
@@ -173,7 +173,7 @@ def display(sim: Union[ToySimulation, RiscvSimulation], display_mode: str) -> st
         if sim.mode == "five_stage_pipeline":
             res += five_stage_pipeline_repr(sim.state.pipeline.pipeline_registers)
             res += hline
-        res += f"PC: {sim.state.program_counter} | Instruction at PC: {'#####' if not sim.state.instruction_at_pc() else str(sim.state.instruction_memory.read_instruction(sim.state.program_counter))}\n"
+        res += f"PC: {hex(sim.state.program_counter)} | Instruction at PC: {'#####' if not sim.state.instruction_at_pc() else str(sim.state.instruction_memory.read_instruction(sim.state.program_counter))}\n"
         res += hline
         res += hline
         res += "Performance Metrics:\n"

From 1eac0a1dc2f2fd1af83c35240f939abe6c4a974b Mon Sep 17 00:00:00 2001
From: Michael Kuhn <michael.kuhn@uni-tuebingen.de>
Date: Wed, 24 Apr 2024 12:17:34 +0200
Subject: [PATCH 19/19] update version string

---
 pyproject.toml     | 2 +-
 webgui/src/main.js | 2 +-
 2 files changed, 2 insertions(+), 2 deletions(-)

diff --git a/pyproject.toml b/pyproject.toml
index e56bb3c7..8457cf69 100644
--- a/pyproject.toml
+++ b/pyproject.toml
@@ -1,6 +1,6 @@
 [project]
 name = "architecture-simulator"
-version = "0.1.0"
+version = "1.3.0"
 readme = "README.md"
 requires-python = ">=3.10"
 dependencies = ["pyparsing","fixedint","prompt-toolkit"]
diff --git a/webgui/src/main.js b/webgui/src/main.js
index 9b43c69a..b98e481a 100644
--- a/webgui/src/main.js
+++ b/webgui/src/main.js
@@ -1,7 +1,7 @@
 import "./scss/styles.scss";
 import "./css/main.css";
 import "./css/splitjs.css";
-import architectureSimulatorPackageUrl from "../../dist/architecture_simulator-0.1.0-py3-none-any.whl";
+import architectureSimulatorPackageUrl from "../../dist/architecture_simulator-1.3.0-py3-none-any.whl";
 
 import { createApp } from "vue";