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base repository: embassy-rs/embassy
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base: 62e07f4bd073aeef9ea708c9c0ccd166b52e9bdf
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head repository: embassy-rs/embassy
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compare: 9c8b89ef322392bcd5fc2a19e1ed9378e8cdebef
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28 changes: 28 additions & 0 deletions embassy-net/CHANGELOG.md
Original file line number Diff line number Diff line change
@@ -7,6 +7,34 @@ and this project adheres to [Semantic Versioning](https://semver.org/spec/v2.0.0

## Unreleased

No unreleased changes yet... Quick, go send a PR!

## 0.5 - 2024-11-28

- Refactor the API structure, simplifying lifetimes and generics.
- Stack is now a thin handle that implements `Copy+Clone`. Instead of passing `&Stack` around, you can now pass `Stack`.
- `Stack` and `DnsSocket` no longer need a generic parameter for the device driver.
- The `run()` method has been moved to a new `Runner` struct.
- Sockets are covariant wrt their lifetime.
- An implication of the refactor is now you need only one `StaticCell` instead of two if you need to share the network stack between tasks.
- Use standard `core::net` IP types instead of custom ones from smoltcp.
- Update to `smoltcp` v0.12.
- Add `mdns` Cargo feature.
- dns: properly handle `AddrType::Either` in `get_host_by_name()`
- dns: truncate instead of panic if the DHCP server gives us more DNS servers than the configured maximum.
- stack: add `wait_link_up()`, `wait_link_down()`, `wait_config_down()`.
- tcp: Add `recv_queue()`, `send_queue()`.
- tcp: Add `wait_read_ready()`, `wait_write_ready()`.
- tcp: allow setting timeout through `embedded-nal` client.
- tcp: fix `flush()` hanging forever if socket is closed with pending data.
- tcp: fix `flush()` not waiting for ACK of FIN.
- tcp: implement `ReadReady`, `WriteReady` traits from `embedded-io`.
- udp, raw: Add `wait_send_ready()`, `wait_recv_ready()`, `flush()`.
- udp: add `recv_from_with()`, `send_to_with()` methods, allowing for IO with one less copy.
- udp: send/recv now takes/returns full `UdpMetadata` instead of just the remote `IpEndpoint`.
- raw: add raw sockets.


## 0.4 - 2024-01-11

- Update to `embassy-time` v0.3.
4 changes: 2 additions & 2 deletions embassy-net/Cargo.toml
Original file line number Diff line number Diff line change
@@ -1,6 +1,6 @@
[package]
name = "embassy-net"
version = "0.4.0"
version = "0.5.0"
edition = "2021"
license = "MIT OR Apache-2.0"
description = "Async TCP/IP network stack for embedded systems"
@@ -68,7 +68,7 @@ multicast = ["smoltcp/multicast"]
defmt = { version = "0.3.8", optional = true }
log = { version = "0.4.14", optional = true }

smoltcp = { git="https://github.com/smoltcp-rs/smoltcp", rev="fe0b4d102253465850cd1cf39cd33d4721a4a8d5", default-features = false, features = [
smoltcp = { version = "0.12.0", default-features = false, features = [
"socket",
"async",
] }
8 changes: 6 additions & 2 deletions embassy-stm32/Cargo.toml
Original file line number Diff line number Diff line change
@@ -72,7 +72,7 @@ rand_core = "0.6.3"
sdio-host = "0.5.0"
critical-section = "1.1"
#stm32-metapac = { version = "15" }
stm32-metapac = { git = "https://github.com/embassy-rs/stm32-data-generated", tag = "stm32-data-04833817666290047257c65c6547d28e1bd10dc9" }
stm32-metapac = { git = "https://github.com/embassy-rs/stm32-data-generated", tag = "stm32-data-ab0ec4c19f81854189bab8215544ccd1256e1045" }

vcell = "0.1.3"
nb = "1.0.0"
@@ -101,7 +101,7 @@ proc-macro2 = "1.0.36"
quote = "1.0.15"

#stm32-metapac = { version = "15", default-features = false, features = ["metadata"]}
stm32-metapac = { git = "https://github.com/embassy-rs/stm32-data-generated", tag = "stm32-data-04833817666290047257c65c6547d28e1bd10dc9", default-features = false, features = ["metadata"] }
stm32-metapac = { git = "https://github.com/embassy-rs/stm32-data-generated", tag = "stm32-data-ab0ec4c19f81854189bab8215544ccd1256e1045", default-features = false, features = ["metadata"] }

[features]
default = ["rt"]
@@ -138,6 +138,10 @@ trustzone-secure = []
## There are no plans to make this stable.
unstable-pac = []

## Enable this feature to disable the overclocking check.
## DO NOT ENABLE THIS FEATURE UNLESS YOU KNOW WHAT YOU'RE DOING.
unchecked-overclocking = []

#! ## Time

## Enables additional driver features that depend on embassy-time
16 changes: 13 additions & 3 deletions embassy-stm32/src/flash/u5.rs
Original file line number Diff line number Diff line change
@@ -1,7 +1,7 @@
use core::ptr::write_volatile;
use core::sync::atomic::{fence, Ordering};

use super::{FlashRegion, FlashSector, FLASH_REGIONS, WRITE_SIZE};
use super::{FlashBank, FlashRegion, FlashSector, FLASH_REGIONS, WRITE_SIZE};
use crate::flash::Error;
use crate::pac;

@@ -70,12 +70,22 @@ pub(crate) unsafe fn blocking_erase_sector(sector: &FlashSector) -> Result<(), E
#[cfg(feature = "trustzone-secure")]
pac::FLASH.seccr().modify(|w| {
w.set_per(pac::flash::vals::SeccrPer::B_0X1);
w.set_pnb(sector.index_in_bank)
w.set_pnb(sector.index_in_bank);
// TODO: add check for bank swap
w.set_bker(match sector.bank {
FlashBank::Bank1 => pac::flash::vals::SeccrBker::B_0X0,
FlashBank::Bank2 => pac::flash::vals::SeccrBker::B_0X1,
});
});
#[cfg(not(feature = "trustzone-secure"))]
pac::FLASH.nscr().modify(|w| {
w.set_per(pac::flash::vals::NscrPer::B_0X1);
w.set_pnb(sector.index_in_bank)
w.set_pnb(sector.index_in_bank);
// TODO: add check for bank swap
w.set_bker(match sector.bank {
FlashBank::Bank1 => pac::flash::vals::NscrBker::B_0X0,
FlashBank::Bank2 => pac::flash::vals::NscrBker::B_0X1,
});
});

#[cfg(feature = "trustzone-secure")]
22 changes: 22 additions & 0 deletions embassy-stm32/src/fmt.rs
Original file line number Diff line number Diff line change
@@ -6,6 +6,28 @@ use core::fmt::{Debug, Display, LowerHex};
#[cfg(all(feature = "defmt", feature = "log"))]
compile_error!("You may not enable both `defmt` and `log` features.");

#[collapse_debuginfo(yes)]
macro_rules! rcc_assert {
($($x:tt)*) => {
{
#[cfg(not(feature = "unchecked-overclocking"))]
{
#[cfg(not(feature = "defmt"))]
::core::assert!($($x)*);
#[cfg(feature = "defmt")]
::defmt::assert!($($x)*);
}
#[cfg(feature = "unchecked-overclocking")]
{
#[cfg(feature = "log")]
::log::warn!("`rcc_assert!` skipped: `unchecked-overclocking` feature is enabled.");
#[cfg(feature = "defmt")]
::defmt::warn!("`rcc_assert!` skipped: `unchecked-overclocking` feature is enabled.");
}
}
};
}

#[collapse_debuginfo(yes)]
macro_rules! assert {
($($x:tt)*) => {
10 changes: 5 additions & 5 deletions embassy-stm32/src/rcc/c0.rs
Original file line number Diff line number Diff line change
@@ -110,8 +110,8 @@ pub(crate) unsafe fn init(config: Config) {
}
Some(hse) => {
match hse.mode {
HseMode::Bypass => assert!(max::HSE_BYP.contains(&hse.freq)),
HseMode::Oscillator => assert!(max::HSE_OSC.contains(&hse.freq)),
HseMode::Bypass => rcc_assert!(max::HSE_BYP.contains(&hse.freq)),
HseMode::Oscillator => rcc_assert!(max::HSE_OSC.contains(&hse.freq)),
}

RCC.cr().modify(|w| w.set_hsebyp(hse.mode != HseMode::Oscillator));
@@ -127,14 +127,14 @@ pub(crate) unsafe fn init(config: Config) {
_ => unreachable!(),
};

assert!(max::SYSCLK.contains(&sys));
rcc_assert!(max::SYSCLK.contains(&sys));

// Calculate the AHB frequency (HCLK), among other things so we can calculate the correct flash read latency.
let hclk = sys / config.ahb_pre;
assert!(max::HCLK.contains(&hclk));
rcc_assert!(max::HCLK.contains(&hclk));

let (pclk1, pclk1_tim) = super::util::calc_pclk(hclk, config.apb1_pre);
assert!(max::PCLK.contains(&pclk1));
rcc_assert!(max::PCLK.contains(&pclk1));

let latency = match hclk.0 {
..=24_000_000 => Latency::WS0,
16 changes: 8 additions & 8 deletions embassy-stm32/src/rcc/f013.rs
Original file line number Diff line number Diff line change
@@ -158,8 +158,8 @@ pub(crate) unsafe fn init(config: Config) {
}
Some(hse) => {
match hse.mode {
HseMode::Bypass => assert!(max::HSE_BYP.contains(&hse.freq)),
HseMode::Oscillator => assert!(max::HSE_OSC.contains(&hse.freq)),
HseMode::Bypass => rcc_assert!(max::HSE_BYP.contains(&hse.freq)),
HseMode::Oscillator => rcc_assert!(max::HSE_OSC.contains(&hse.freq)),
}

RCC.cr().modify(|w| w.set_hsebyp(hse.mode != HseMode::Oscillator));
@@ -192,9 +192,9 @@ pub(crate) unsafe fn init(config: Config) {
PllSource::HSI48 => (Pllsrc::HSI48_DIV_PREDIV, unwrap!(hsi48)),
};
let in_freq = src_freq / pll.prediv;
assert!(max::PLL_IN.contains(&in_freq));
rcc_assert!(max::PLL_IN.contains(&in_freq));
let out_freq = in_freq * pll.mul;
assert!(max::PLL_OUT.contains(&out_freq));
rcc_assert!(max::PLL_OUT.contains(&out_freq));

#[cfg(not(stm32f1))]
RCC.cfgr2().modify(|w| w.set_prediv(pll.prediv));
@@ -239,15 +239,15 @@ pub(crate) unsafe fn init(config: Config) {
#[cfg(stm32f0)]
let (pclk2, pclk2_tim) = (pclk1, pclk1_tim);

assert!(max::HCLK.contains(&hclk));
assert!(max::PCLK1.contains(&pclk1));
rcc_assert!(max::HCLK.contains(&hclk));
rcc_assert!(max::PCLK1.contains(&pclk1));
#[cfg(not(stm32f0))]
assert!(max::PCLK2.contains(&pclk2));
rcc_assert!(max::PCLK2.contains(&pclk2));

#[cfg(stm32f1)]
let adc = pclk2 / config.adc_pre;
#[cfg(stm32f1)]
assert!(max::ADC.contains(&adc));
rcc_assert!(max::ADC.contains(&adc));

// Set latency based on HCLK frquency
#[cfg(stm32f0)]
12 changes: 6 additions & 6 deletions embassy-stm32/src/rcc/f247.rs
Original file line number Diff line number Diff line change
@@ -170,8 +170,8 @@ pub(crate) unsafe fn init(config: Config) {
}
Some(hse) => {
match hse.mode {
HseMode::Bypass => assert!(max::HSE_BYP.contains(&hse.freq)),
HseMode::Oscillator => assert!(max::HSE_OSC.contains(&hse.freq)),
HseMode::Bypass => rcc_assert!(max::HSE_BYP.contains(&hse.freq)),
HseMode::Oscillator => rcc_assert!(max::HSE_OSC.contains(&hse.freq)),
}

RCC.cr().modify(|w| w.set_hsebyp(hse.mode != HseMode::Oscillator));
@@ -205,10 +205,10 @@ pub(crate) unsafe fn init(config: Config) {
let (pclk1, pclk1_tim) = super::util::calc_pclk(hclk, config.apb1_pre);
let (pclk2, pclk2_tim) = super::util::calc_pclk(hclk, config.apb2_pre);

assert!(max::SYSCLK.contains(&sys));
assert!(max::HCLK.contains(&hclk));
assert!(max::PCLK1.contains(&pclk1));
assert!(max::PCLK2.contains(&pclk2));
rcc_assert!(max::SYSCLK.contains(&sys));
rcc_assert!(max::HCLK.contains(&hclk));
rcc_assert!(max::PCLK1.contains(&pclk1));
rcc_assert!(max::PCLK2.contains(&pclk2));

let rtc = config.ls.init();

21 changes: 10 additions & 11 deletions embassy-stm32/src/rcc/g0.rs
Original file line number Diff line number Diff line change
@@ -140,8 +140,8 @@ pub(crate) unsafe fn init(config: Config) {
}
Some(hse) => {
match hse.mode {
HseMode::Bypass => assert!(max::HSE_BYP.contains(&hse.freq)),
HseMode::Oscillator => assert!(max::HSE_OSC.contains(&hse.freq)),
HseMode::Bypass => rcc_assert!(max::HSE_BYP.contains(&hse.freq)),
HseMode::Oscillator => rcc_assert!(max::HSE_OSC.contains(&hse.freq)),
}

RCC.cr().modify(|w| w.set_hsebyp(hse.mode != HseMode::Oscillator));
@@ -169,10 +169,9 @@ pub(crate) unsafe fn init(config: Config) {
while RCC.cr().read().pllrdy() {}

let in_freq = src_freq / pll_config.prediv;
assert!(max::PLL_IN.contains(&in_freq));
rcc_assert!(max::PLL_IN.contains(&in_freq));
let internal_freq = in_freq * pll_config.mul;

assert!(max::PLL_VCO.contains(&internal_freq));
rcc_assert!(max::PLL_VCO.contains(&internal_freq));

RCC.pllcfgr().write(|w| {
w.set_plln(pll_config.mul);
@@ -186,7 +185,7 @@ pub(crate) unsafe fn init(config: Config) {
w.set_pllpen(true);
});
let freq = internal_freq / div_p;
assert!(max::PLL_P.contains(&freq));
rcc_assert!(max::PLL_P.contains(&freq));
freq
});

@@ -196,7 +195,7 @@ pub(crate) unsafe fn init(config: Config) {
w.set_pllqen(true);
});
let freq = internal_freq / div_q;
assert!(max::PLL_Q.contains(&freq));
rcc_assert!(max::PLL_Q.contains(&freq));
freq
});

@@ -206,7 +205,7 @@ pub(crate) unsafe fn init(config: Config) {
w.set_pllren(true);
});
let freq = internal_freq / div_r;
assert!(max::PLL_R.contains(&freq));
rcc_assert!(max::PLL_R.contains(&freq));
freq
});

@@ -229,14 +228,14 @@ pub(crate) unsafe fn init(config: Config) {
_ => unreachable!(),
};

assert!(max::SYSCLK.contains(&sys));
rcc_assert!(max::SYSCLK.contains(&sys));

// Calculate the AHB frequency (HCLK), among other things so we can calculate the correct flash read latency.
let hclk = sys / config.ahb_pre;
assert!(max::HCLK.contains(&hclk));
rcc_assert!(max::HCLK.contains(&hclk));

let (pclk1, pclk1_tim) = super::util::calc_pclk(hclk, config.apb1_pre);
assert!(max::PCLK.contains(&pclk1));
rcc_assert!(max::PCLK.contains(&pclk1));

let latency = match (config.voltage_range, hclk.0) {
(VoltageRange::RANGE1, ..=24_000_000) => Latency::WS0,
22 changes: 11 additions & 11 deletions embassy-stm32/src/rcc/g4.rs
Original file line number Diff line number Diff line change
@@ -141,8 +141,8 @@ pub(crate) unsafe fn init(config: Config) {
}
Some(hse) => {
match hse.mode {
HseMode::Bypass => assert!(max::HSE_BYP.contains(&hse.freq)),
HseMode::Oscillator => assert!(max::HSE_OSC.contains(&hse.freq)),
HseMode::Bypass => rcc_assert!(max::HSE_BYP.contains(&hse.freq)),
HseMode::Oscillator => rcc_assert!(max::HSE_OSC.contains(&hse.freq)),
}

RCC.cr().modify(|w| w.set_hsebyp(hse.mode != HseMode::Oscillator));
@@ -169,10 +169,10 @@ pub(crate) unsafe fn init(config: Config) {
while RCC.cr().read().pllrdy() {}

let in_freq = src_freq / pll_config.prediv;
assert!(max::PLL_IN.contains(&in_freq));
rcc_assert!(max::PLL_IN.contains(&in_freq));
let internal_freq = in_freq * pll_config.mul;

assert!(max::PLL_VCO.contains(&internal_freq));
rcc_assert!(max::PLL_VCO.contains(&internal_freq));

RCC.pllcfgr().write(|w| {
w.set_plln(pll_config.mul);
@@ -186,7 +186,7 @@ pub(crate) unsafe fn init(config: Config) {
w.set_pllpen(true);
});
let freq = internal_freq / div_p;
assert!(max::PLL_P.contains(&freq));
rcc_assert!(max::PLL_P.contains(&freq));
freq
});

@@ -196,7 +196,7 @@ pub(crate) unsafe fn init(config: Config) {
w.set_pllqen(true);
});
let freq = internal_freq / div_q;
assert!(max::PLL_Q.contains(&freq));
rcc_assert!(max::PLL_Q.contains(&freq));
freq
});

@@ -206,7 +206,7 @@ pub(crate) unsafe fn init(config: Config) {
w.set_pllren(true);
});
let freq = internal_freq / div_r;
assert!(max::PLL_R.contains(&freq));
rcc_assert!(max::PLL_R.contains(&freq));
freq
});

@@ -229,16 +229,16 @@ pub(crate) unsafe fn init(config: Config) {
_ => unreachable!(),
};

assert!(max::SYSCLK.contains(&sys));
rcc_assert!(max::SYSCLK.contains(&sys));

// Calculate the AHB frequency (HCLK), among other things so we can calculate the correct flash read latency.
let hclk = sys / config.ahb_pre;
assert!(max::HCLK.contains(&hclk));
rcc_assert!(max::HCLK.contains(&hclk));

let (pclk1, pclk1_tim) = super::util::calc_pclk(hclk, config.apb1_pre);
let (pclk2, pclk2_tim) = super::util::calc_pclk(hclk, config.apb2_pre);
assert!(max::PCLK.contains(&pclk2));
assert!(max::PCLK.contains(&pclk2));
rcc_assert!(max::PCLK.contains(&pclk1));
rcc_assert!(max::PCLK.contains(&pclk2));

// Configure Core Boost mode ([RM0440] p234 – inverted because setting r1mode to 0 enables boost mode!)
if config.boost {
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