diff --git a/src/rp2040/adc.rs b/src/rp2040/adc.rs index 1027f21b..88b82c78 100644 --- a/src/rp2040/adc.rs +++ b/src/rp2040/adc.rs @@ -17,47 +17,47 @@ impl Adc { #[doc = "ADC Control and Status"] #[inline(always)] pub const fn cs(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(0usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x0usize) as _) } } #[doc = "Result of most recent ADC conversion"] #[inline(always)] pub const fn result(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(4usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x04usize) as _) } } #[doc = "FIFO control and status"] #[inline(always)] pub const fn fcs(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(8usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x08usize) as _) } } #[doc = "Conversion result FIFO"] #[inline(always)] pub const fn fifo(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(12usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x0cusize) as _) } } #[doc = "Clock divider. If non-zero, CS_START_MANY will start conversions at regular intervals rather than back-to-back. The divider is reset when either of these fields are written. Total period is 1 + INT + FRAC / 256"] #[inline(always)] pub const fn div(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(16usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x10usize) as _) } } #[doc = "Raw Interrupts"] #[inline(always)] pub const fn intr(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(20usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x14usize) as _) } } #[doc = "Interrupt Enable"] #[inline(always)] pub const fn inte(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(24usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x18usize) as _) } } #[doc = "Interrupt Force"] #[inline(always)] pub const fn intf(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(28usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x1cusize) as _) } } #[doc = "Interrupt status after masking & forcing"] #[inline(always)] pub const fn ints(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(32usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x20usize) as _) } } } pub mod regs; diff --git a/src/rp2040/busctrl.rs b/src/rp2040/busctrl.rs index c0c2fd7a..475a3c8b 100644 --- a/src/rp2040/busctrl.rs +++ b/src/rp2040/busctrl.rs @@ -17,26 +17,26 @@ impl Busctrl { #[doc = "Set the priority of each master for bus arbitration."] #[inline(always)] pub const fn bus_priority(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(0usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x0usize) as _) } } #[doc = "Bus priority acknowledge"] #[inline(always)] pub const fn bus_priority_ack( self, ) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(4usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x04usize) as _) } } #[doc = "Bus fabric performance counter 0"] #[inline(always)] pub const fn perfctr(self, n: usize) -> crate::common::Reg { assert!(n < 4usize); - unsafe { crate::common::Reg::from_ptr(self.ptr.add(8usize + n * 8usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x08usize + n * 8usize) as _) } } #[doc = "Bus fabric performance event select for PERFCTR0"] #[inline(always)] pub const fn perfsel(self, n: usize) -> crate::common::Reg { assert!(n < 4usize); - unsafe { crate::common::Reg::from_ptr(self.ptr.add(12usize + n * 8usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x0cusize + n * 8usize) as _) } } } pub mod regs; diff --git a/src/rp2040/busctrl/regs.rs b/src/rp2040/busctrl/regs.rs index 2c37899b..dabc0980 100644 --- a/src/rp2040/busctrl/regs.rs +++ b/src/rp2040/busctrl/regs.rs @@ -77,18 +77,18 @@ impl Default for BusPriorityAck { BusPriorityAck(0) } } -#[doc = "Bus fabric performance counter 1"] +#[doc = "Bus fabric performance counter 2"] #[repr(transparent)] #[derive(Copy, Clone, Eq, PartialEq)] pub struct Perfctr(pub u32); impl Perfctr { - #[doc = "Busfabric saturating performance counter 1 Count some event signal from the busfabric arbiters. Write any value to clear. Select an event to count using PERFSEL1"] + #[doc = "Busfabric saturating performance counter 2 Count some event signal from the busfabric arbiters. Write any value to clear. Select an event to count using PERFSEL2"] #[inline(always)] pub const fn perfctr(&self) -> u32 { let val = (self.0 >> 0usize) & 0x00ff_ffff; val as u32 } - #[doc = "Busfabric saturating performance counter 1 Count some event signal from the busfabric arbiters. Write any value to clear. Select an event to count using PERFSEL1"] + #[doc = "Busfabric saturating performance counter 2 Count some event signal from the busfabric arbiters. Write any value to clear. Select an event to count using PERFSEL2"] #[inline(always)] pub fn set_perfctr(&mut self, val: u32) { self.0 = (self.0 & !(0x00ff_ffff << 0usize)) | (((val as u32) & 0x00ff_ffff) << 0usize); @@ -100,18 +100,18 @@ impl Default for Perfctr { Perfctr(0) } } -#[doc = "Bus fabric performance event select for PERFCTR1"] +#[doc = "Bus fabric performance event select for PERFCTR0"] #[repr(transparent)] #[derive(Copy, Clone, Eq, PartialEq)] pub struct Perfsel(pub u32); impl Perfsel { - #[doc = "Select an event for PERFCTR1. Count either contested accesses, or all accesses, on a downstream port of the main crossbar."] + #[doc = "Select an event for PERFCTR0. Count either contested accesses, or all accesses, on a downstream port of the main crossbar."] #[inline(always)] pub const fn perfsel(&self) -> super::vals::Perfsel { let val = (self.0 >> 0usize) & 0x1f; super::vals::Perfsel::from_bits(val as u8) } - #[doc = "Select an event for PERFCTR1. Count either contested accesses, or all accesses, on a downstream port of the main crossbar."] + #[doc = "Select an event for PERFCTR0. Count either contested accesses, or all accesses, on a downstream port of the main crossbar."] #[inline(always)] pub fn set_perfsel(&mut self, val: super::vals::Perfsel) { self.0 = (self.0 & !(0x1f << 0usize)) | (((val.to_bits() as u32) & 0x1f) << 0usize); diff --git a/src/rp2040/busctrl/vals.rs b/src/rp2040/busctrl/vals.rs index f88e41e4..09e9357b 100644 --- a/src/rp2040/busctrl/vals.rs +++ b/src/rp2040/busctrl/vals.rs @@ -1,7 +1,7 @@ #[repr(u8)] #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] pub enum Perfsel { - APB_CONTESTED = 0, + APB_CONTESTED = 0x0, APB = 0x01, FASTPERI_CONTESTED = 0x02, FASTPERI = 0x03, diff --git a/src/rp2040/clocks.rs b/src/rp2040/clocks.rs index 3dc733e3..67bea956 100644 --- a/src/rp2040/clocks.rs +++ b/src/rp2040/clocks.rs @@ -20,7 +20,7 @@ impl Clocks { n: usize, ) -> crate::common::Reg { assert!(n < 4usize); - unsafe { crate::common::Reg::from_ptr(self.ptr.add(0usize + n * 12usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x0usize + n * 12usize) as _) } } #[doc = "Clock divisor, can be changed on-the-fly"] #[inline(always)] @@ -29,205 +29,205 @@ impl Clocks { n: usize, ) -> crate::common::Reg { assert!(n < 4usize); - unsafe { crate::common::Reg::from_ptr(self.ptr.add(4usize + n * 12usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x04usize + n * 12usize) as _) } } #[doc = "Indicates which SRC is currently selected by the glitchless mux (one-hot)."] #[inline(always)] pub const fn clk_gpout_selected(self, n: usize) -> crate::common::Reg { assert!(n < 4usize); - unsafe { crate::common::Reg::from_ptr(self.ptr.add(8usize + n * 12usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x08usize + n * 12usize) as _) } } #[doc = "Clock control, can be changed on-the-fly (except for auxsrc)"] #[inline(always)] pub const fn clk_ref_ctrl(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(48usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x30usize) as _) } } #[doc = "Clock divisor, can be changed on-the-fly"] #[inline(always)] pub const fn clk_ref_div(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(52usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x34usize) as _) } } #[doc = "Indicates which SRC is currently selected by the glitchless mux (one-hot)."] #[inline(always)] pub const fn clk_ref_selected(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(56usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x38usize) as _) } } #[doc = "Clock control, can be changed on-the-fly (except for auxsrc)"] #[inline(always)] pub const fn clk_sys_ctrl(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(60usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x3cusize) as _) } } #[doc = "Clock divisor, can be changed on-the-fly"] #[inline(always)] pub const fn clk_sys_div(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(64usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x40usize) as _) } } #[doc = "Indicates which SRC is currently selected by the glitchless mux (one-hot)."] #[inline(always)] pub const fn clk_sys_selected(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(68usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x44usize) as _) } } #[doc = "Clock control, can be changed on-the-fly (except for auxsrc)"] #[inline(always)] pub const fn clk_peri_ctrl(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(72usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x48usize) as _) } } #[doc = "Clock divisor, can be changed on-the-fly"] #[inline(always)] pub const fn clk_peri_div(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(76usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x4cusize) as _) } } #[doc = "Indicates which SRC is currently selected by the glitchless mux (one-hot)."] #[inline(always)] pub const fn clk_peri_selected(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(80usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x50usize) as _) } } #[doc = "Clock control, can be changed on-the-fly (except for auxsrc)"] #[inline(always)] pub const fn clk_usb_ctrl(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(84usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x54usize) as _) } } #[doc = "Clock divisor, can be changed on-the-fly"] #[inline(always)] pub const fn clk_usb_div(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(88usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x58usize) as _) } } #[doc = "Indicates which SRC is currently selected by the glitchless mux (one-hot)."] #[inline(always)] pub const fn clk_usb_selected(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(92usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x5cusize) as _) } } #[doc = "Clock control, can be changed on-the-fly (except for auxsrc)"] #[inline(always)] pub const fn clk_adc_ctrl(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(96usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x60usize) as _) } } #[doc = "Clock divisor, can be changed on-the-fly"] #[inline(always)] pub const fn clk_adc_div(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(100usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x64usize) as _) } } #[doc = "Indicates which SRC is currently selected by the glitchless mux (one-hot)."] #[inline(always)] pub const fn clk_adc_selected(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(104usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x68usize) as _) } } #[doc = "Clock control, can be changed on-the-fly (except for auxsrc)"] #[inline(always)] pub const fn clk_rtc_ctrl(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(108usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x6cusize) as _) } } #[doc = "Clock divisor, can be changed on-the-fly"] #[inline(always)] pub const fn clk_rtc_div(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(112usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x70usize) as _) } } #[doc = "Indicates which SRC is currently selected by the glitchless mux (one-hot)."] #[inline(always)] pub const fn clk_rtc_selected(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(116usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x74usize) as _) } } #[inline(always)] pub const fn clk_sys_resus_ctrl( self, ) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(120usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x78usize) as _) } } #[inline(always)] pub const fn clk_sys_resus_status( self, ) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(124usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x7cusize) as _) } } #[doc = "Reference clock frequency in kHz"] #[inline(always)] pub const fn fc0_ref_khz(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(128usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x80usize) as _) } } #[doc = "Minimum pass frequency in kHz. This is optional. Set to 0 if you are not using the pass/fail flags"] #[inline(always)] pub const fn fc0_min_khz(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(132usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x84usize) as _) } } #[doc = "Maximum pass frequency in kHz. This is optional. Set to 0x1ffffff if you are not using the pass/fail flags"] #[inline(always)] pub const fn fc0_max_khz(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(136usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x88usize) as _) } } #[doc = "Delays the start of frequency counting to allow the mux to settle Delay is measured in multiples of the reference clock period"] #[inline(always)] pub const fn fc0_delay(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(140usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x8cusize) as _) } } #[doc = "The test interval is 0.98us * 2**interval, but let's call it 1us * 2**interval The default gives a test interval of 250us"] #[inline(always)] pub const fn fc0_interval(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(144usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x90usize) as _) } } #[doc = "Clock sent to frequency counter, set to 0 when not required Writing to this register initiates the frequency count"] #[inline(always)] pub const fn fc0_src(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(148usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x94usize) as _) } } #[doc = "Frequency counter status"] #[inline(always)] pub const fn fc0_status(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(152usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x98usize) as _) } } #[doc = "Result of frequency measurement, only valid when status_done=1"] #[inline(always)] pub const fn fc0_result(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(156usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x9cusize) as _) } } #[doc = "enable clock in wake mode"] #[inline(always)] pub const fn wake_en0(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(160usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0xa0usize) as _) } } #[doc = "enable clock in wake mode"] #[inline(always)] pub const fn wake_en1(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(164usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0xa4usize) as _) } } #[doc = "enable clock in sleep mode"] #[inline(always)] pub const fn sleep_en0(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(168usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0xa8usize) as _) } } #[doc = "enable clock in sleep mode"] #[inline(always)] pub const fn sleep_en1(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(172usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0xacusize) as _) } } #[doc = "indicates the state of the clock enable"] #[inline(always)] pub const fn enabled0(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(176usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0xb0usize) as _) } } #[doc = "indicates the state of the clock enable"] #[inline(always)] pub const fn enabled1(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(180usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0xb4usize) as _) } } #[doc = "Raw Interrupts"] #[inline(always)] pub const fn intr(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(184usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0xb8usize) as _) } } #[doc = "Interrupt Enable"] #[inline(always)] pub const fn inte(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(188usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0xbcusize) as _) } } #[doc = "Interrupt Force"] #[inline(always)] pub const fn intf(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(192usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0xc0usize) as _) } } #[doc = "Interrupt status after masking & forcing"] #[inline(always)] pub const fn ints(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(196usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0xc4usize) as _) } } } pub mod regs; diff --git a/src/rp2040/clocks/vals.rs b/src/rp2040/clocks/vals.rs index d47fbe3e..7c0c57d9 100644 --- a/src/rp2040/clocks/vals.rs +++ b/src/rp2040/clocks/vals.rs @@ -1,7 +1,7 @@ #[repr(u8)] #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] pub enum ClkAdcCtrlAuxsrc { - CLKSRC_PLL_USB = 0, + CLKSRC_PLL_USB = 0x0, CLKSRC_PLL_SYS = 0x01, ROSC_CLKSRC_PH = 0x02, XOSC_CLKSRC = 0x03, @@ -35,7 +35,7 @@ impl From for u8 { #[repr(u8)] #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] pub enum ClkGpoutCtrlAuxsrc { - CLKSRC_PLL_SYS = 0, + CLKSRC_PLL_SYS = 0x0, CLKSRC_GPIN0 = 0x01, CLKSRC_GPIN1 = 0x02, CLKSRC_PLL_USB = 0x03, @@ -77,7 +77,7 @@ impl From for u8 { #[repr(u8)] #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] pub enum ClkPeriCtrlAuxsrc { - CLK_SYS = 0, + CLK_SYS = 0x0, CLKSRC_PLL_SYS = 0x01, CLKSRC_PLL_USB = 0x02, ROSC_CLKSRC_PH = 0x03, @@ -111,7 +111,7 @@ impl From for u8 { #[repr(u8)] #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] pub enum ClkRefCtrlAuxsrc { - CLKSRC_PLL_USB = 0, + CLKSRC_PLL_USB = 0x0, CLKSRC_GPIN0 = 0x01, CLKSRC_GPIN1 = 0x02, _RESERVED_3 = 0x03, @@ -141,7 +141,7 @@ impl From for u8 { #[repr(u8)] #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] pub enum ClkRefCtrlSrc { - ROSC_CLKSRC_PH = 0, + ROSC_CLKSRC_PH = 0x0, CLKSRC_CLK_REF_AUX = 0x01, XOSC_CLKSRC = 0x02, _RESERVED_3 = 0x03, @@ -171,7 +171,7 @@ impl From for u8 { #[repr(u8)] #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] pub enum ClkRtcCtrlAuxsrc { - CLKSRC_PLL_USB = 0, + CLKSRC_PLL_USB = 0x0, CLKSRC_PLL_SYS = 0x01, ROSC_CLKSRC_PH = 0x02, XOSC_CLKSRC = 0x03, @@ -205,7 +205,7 @@ impl From for u8 { #[repr(u8)] #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] pub enum ClkSysCtrlAuxsrc { - CLKSRC_PLL_SYS = 0, + CLKSRC_PLL_SYS = 0x0, CLKSRC_PLL_USB = 0x01, ROSC_CLKSRC = 0x02, XOSC_CLKSRC = 0x03, @@ -239,7 +239,7 @@ impl From for u8 { #[repr(u8)] #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] pub enum ClkSysCtrlSrc { - CLK_REF = 0, + CLK_REF = 0x0, CLKSRC_CLK_SYS_AUX = 0x01, } impl ClkSysCtrlSrc { @@ -267,7 +267,7 @@ impl From for u8 { #[repr(u8)] #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] pub enum ClkUsbCtrlAuxsrc { - CLKSRC_PLL_USB = 0, + CLKSRC_PLL_USB = 0x0, CLKSRC_PLL_SYS = 0x01, ROSC_CLKSRC_PH = 0x02, XOSC_CLKSRC = 0x03, @@ -301,7 +301,7 @@ impl From for u8 { #[repr(u8)] #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] pub enum Fc0src { - NULL = 0, + NULL = 0x0, PLL_SYS_CLKSRC_PRIMARY = 0x01, PLL_USB_CLKSRC_PRIMARY = 0x02, ROSC_CLKSRC = 0x03, diff --git a/src/rp2040/dma.rs b/src/rp2040/dma.rs index 0ed538a8..72f20701 100644 --- a/src/rp2040/dma.rs +++ b/src/rp2040/dma.rs @@ -13,95 +13,95 @@ impl Channel { pub const fn as_ptr(&self) -> *mut () { self.ptr as _ } - #[doc = "DMA Channel 4 Read Address pointer"] + #[doc = "DMA Channel 5 Read Address pointer"] #[inline(always)] pub const fn read_addr(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(0usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x0usize) as _) } } - #[doc = "DMA Channel 4 Write Address pointer"] + #[doc = "DMA Channel 5 Write Address pointer"] #[inline(always)] pub const fn write_addr(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(4usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x04usize) as _) } } - #[doc = "DMA Channel 4 Transfer Count"] + #[doc = "DMA Channel 5 Transfer Count"] #[inline(always)] pub const fn trans_count(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(8usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x08usize) as _) } } - #[doc = "DMA Channel 4 Control and Status"] + #[doc = "DMA Channel 5 Control and Status"] #[inline(always)] pub const fn ctrl_trig(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(12usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x0cusize) as _) } } - #[doc = "Alias for channel 4 CTRL register"] + #[doc = "Alias for channel 5 CTRL register"] #[inline(always)] pub const fn al1_ctrl(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(16usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x10usize) as _) } } - #[doc = "Alias for channel 4 READ_ADDR register"] + #[doc = "Alias for channel 5 READ_ADDR register"] #[inline(always)] pub const fn al1_read_addr(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(20usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x14usize) as _) } } - #[doc = "Alias for channel 4 WRITE_ADDR register"] + #[doc = "Alias for channel 5 WRITE_ADDR register"] #[inline(always)] pub const fn al1_write_addr(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(24usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x18usize) as _) } } - #[doc = "Alias for channel 4 TRANS_COUNT register This is a trigger register (0xc). Writing a nonzero value will reload the channel counter and start the channel."] + #[doc = "Alias for channel 5 TRANS_COUNT register This is a trigger register (0xc). Writing a nonzero value will reload the channel counter and start the channel."] #[inline(always)] pub const fn al1_trans_count_trig(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(28usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x1cusize) as _) } } - #[doc = "Alias for channel 4 CTRL register"] + #[doc = "Alias for channel 5 CTRL register"] #[inline(always)] pub const fn al2_ctrl(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(32usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x20usize) as _) } } - #[doc = "Alias for channel 4 TRANS_COUNT register"] + #[doc = "Alias for channel 5 TRANS_COUNT register"] #[inline(always)] pub const fn al2_trans_count(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(36usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x24usize) as _) } } - #[doc = "Alias for channel 4 READ_ADDR register"] + #[doc = "Alias for channel 5 READ_ADDR register"] #[inline(always)] pub const fn al2_read_addr(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(40usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x28usize) as _) } } - #[doc = "Alias for channel 4 WRITE_ADDR register This is a trigger register (0xc). Writing a nonzero value will reload the channel counter and start the channel."] + #[doc = "Alias for channel 5 WRITE_ADDR register This is a trigger register (0xc). Writing a nonzero value will reload the channel counter and start the channel."] #[inline(always)] pub const fn al2_write_addr_trig(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(44usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x2cusize) as _) } } - #[doc = "Alias for channel 4 CTRL register"] + #[doc = "Alias for channel 5 CTRL register"] #[inline(always)] pub const fn al3_ctrl(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(48usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x30usize) as _) } } - #[doc = "Alias for channel 4 WRITE_ADDR register"] + #[doc = "Alias for channel 5 WRITE_ADDR register"] #[inline(always)] pub const fn al3_write_addr(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(52usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x34usize) as _) } } - #[doc = "Alias for channel 4 TRANS_COUNT register"] + #[doc = "Alias for channel 5 TRANS_COUNT register"] #[inline(always)] pub const fn al3_trans_count(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(56usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x38usize) as _) } } - #[doc = "Alias for channel 4 READ_ADDR register This is a trigger register (0xc). Writing a nonzero value will reload the channel counter and start the channel."] + #[doc = "Alias for channel 5 READ_ADDR register This is a trigger register (0xc). Writing a nonzero value will reload the channel counter and start the channel."] #[inline(always)] pub const fn al3_read_addr_trig(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(60usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x3cusize) as _) } } #[doc = "Read: get channel DREQ counter (i.e. how many accesses the DMA expects it can perform on the peripheral without overflow/underflow. Write any value: clears the counter, and cause channel to re-initiate DREQ handshake."] #[inline(always)] pub const fn dbg_ctdreq(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(2048usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x0800usize) as _) } } #[doc = "Read to get channel TRANS_COUNT reload value, i.e. the length of the next transfer"] #[inline(always)] pub const fn dbg_tcr(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(2052usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x0804usize) as _) } } } #[doc = "DMA with separate read and write masters"] @@ -123,85 +123,69 @@ impl Dma { #[inline(always)] pub const fn ch(self, n: usize) -> Channel { assert!(n < 12usize); - unsafe { Channel::from_ptr(self.ptr.add(0usize + n * 64usize) as _) } + unsafe { Channel::from_ptr(self.ptr.add(0x0usize + n * 64usize) as _) } } #[doc = "Interrupt Status (raw)"] #[inline(always)] - pub const fn intr(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(1024usize) as _) } + pub const fn intr(self, n: usize) -> crate::common::Reg { + assert!(n < 2usize); + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x0400usize + n * 16usize) as _) } } #[doc = "Interrupt Enables for IRQ 0"] #[inline(always)] - pub const fn inte0(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(1028usize) as _) } + pub const fn inte(self, n: usize) -> crate::common::Reg { + assert!(n < 2usize); + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x0404usize + n * 16usize) as _) } } #[doc = "Force Interrupts"] #[inline(always)] - pub const fn intf0(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(1032usize) as _) } + pub const fn intf(self, n: usize) -> crate::common::Reg { + assert!(n < 2usize); + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x0408usize + n * 16usize) as _) } } #[doc = "Interrupt Status for IRQ 0"] #[inline(always)] - pub const fn ints0(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(1036usize) as _) } - } - #[doc = "Interrupt Status (raw)"] - #[inline(always)] - pub const fn intr1(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(1040usize) as _) } - } - #[doc = "Interrupt Enables for IRQ 1"] - #[inline(always)] - pub const fn inte1(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(1044usize) as _) } - } - #[doc = "Force Interrupts for IRQ 1"] - #[inline(always)] - pub const fn intf1(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(1048usize) as _) } - } - #[doc = "Interrupt Status (masked) for IRQ 1"] - #[inline(always)] - pub const fn ints1(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(1052usize) as _) } + pub const fn ints(self, n: usize) -> crate::common::Reg { + assert!(n < 2usize); + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x040cusize + n * 16usize) as _) } } #[doc = "Pacing (X/Y) Fractional Timer The pacing timer produces TREQ assertions at a rate set by ((X/Y) * sys_clk). This equation is evaluated every sys_clk cycles and therefore can only generate TREQs at a rate of 1 per sys_clk (i.e. permanent TREQ) or less."] #[inline(always)] pub const fn timer(self, n: usize) -> crate::common::Reg { assert!(n < 4usize); - unsafe { crate::common::Reg::from_ptr(self.ptr.add(1056usize + n * 4usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x0420usize + n * 4usize) as _) } } #[doc = "Trigger one or more channels simultaneously"] #[inline(always)] pub const fn multi_chan_trigger( self, ) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(1072usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x0430usize) as _) } } #[doc = "Sniffer Control"] #[inline(always)] pub const fn sniff_ctrl(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(1076usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x0434usize) as _) } } #[doc = "Data accumulator for sniff hardware"] #[inline(always)] pub const fn sniff_data(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(1080usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x0438usize) as _) } } #[doc = "Debug RAF, WAF, TDF levels"] #[inline(always)] pub const fn fifo_levels(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(1088usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x0440usize) as _) } } #[doc = "Abort an in-progress transfer sequence on one or more channels"] #[inline(always)] pub const fn chan_abort(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(1092usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x0444usize) as _) } } #[doc = "The number of channels this DMA instance is equipped with. This DMA supports up to 16 hardware channels, but can be configured with as few as one, to minimise silicon area."] #[inline(always)] pub const fn n_channels(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(1096usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x0448usize) as _) } } } pub mod regs; diff --git a/src/rp2040/dma/regs.rs b/src/rp2040/dma/regs.rs index 57173a2a..c67ad077 100644 --- a/src/rp2040/dma/regs.rs +++ b/src/rp2040/dma/regs.rs @@ -21,7 +21,7 @@ impl Default for ChanAbort { ChanAbort(0) } } -#[doc = "DMA Channel 10 Control and Status"] +#[doc = "DMA Channel 5 Control and Status"] #[repr(transparent)] #[derive(Copy, Clone, Eq, PartialEq)] pub struct CtrlTrig(pub u32); @@ -275,190 +275,6 @@ impl Default for FifoLevels { FifoLevels(0) } } -#[doc = "Interrupt Enables for IRQ 0"] -#[repr(transparent)] -#[derive(Copy, Clone, Eq, PartialEq)] -pub struct Inte0(pub u32); -impl Inte0 { - #[doc = "Set bit n to pass interrupts from channel n to DMA IRQ 0."] - #[inline(always)] - pub const fn inte0(&self) -> u16 { - let val = (self.0 >> 0usize) & 0xffff; - val as u16 - } - #[doc = "Set bit n to pass interrupts from channel n to DMA IRQ 0."] - #[inline(always)] - pub fn set_inte0(&mut self, val: u16) { - self.0 = (self.0 & !(0xffff << 0usize)) | (((val as u32) & 0xffff) << 0usize); - } -} -impl Default for Inte0 { - #[inline(always)] - fn default() -> Inte0 { - Inte0(0) - } -} -#[doc = "Interrupt Enables for IRQ 1"] -#[repr(transparent)] -#[derive(Copy, Clone, Eq, PartialEq)] -pub struct Inte1(pub u32); -impl Inte1 { - #[doc = "Set bit n to pass interrupts from channel n to DMA IRQ 1."] - #[inline(always)] - pub const fn inte1(&self) -> u16 { - let val = (self.0 >> 0usize) & 0xffff; - val as u16 - } - #[doc = "Set bit n to pass interrupts from channel n to DMA IRQ 1."] - #[inline(always)] - pub fn set_inte1(&mut self, val: u16) { - self.0 = (self.0 & !(0xffff << 0usize)) | (((val as u32) & 0xffff) << 0usize); - } -} -impl Default for Inte1 { - #[inline(always)] - fn default() -> Inte1 { - Inte1(0) - } -} -#[doc = "Force Interrupts"] -#[repr(transparent)] -#[derive(Copy, Clone, Eq, PartialEq)] -pub struct Intf0(pub u32); -impl Intf0 { - #[doc = "Write 1s to force the corresponding bits in INTE0. The interrupt remains asserted until INTF0 is cleared."] - #[inline(always)] - pub const fn intf0(&self) -> u16 { - let val = (self.0 >> 0usize) & 0xffff; - val as u16 - } - #[doc = "Write 1s to force the corresponding bits in INTE0. The interrupt remains asserted until INTF0 is cleared."] - #[inline(always)] - pub fn set_intf0(&mut self, val: u16) { - self.0 = (self.0 & !(0xffff << 0usize)) | (((val as u32) & 0xffff) << 0usize); - } -} -impl Default for Intf0 { - #[inline(always)] - fn default() -> Intf0 { - Intf0(0) - } -} -#[doc = "Force Interrupts for IRQ 1"] -#[repr(transparent)] -#[derive(Copy, Clone, Eq, PartialEq)] -pub struct Intf1(pub u32); -impl Intf1 { - #[doc = "Write 1s to force the corresponding bits in INTE0. The interrupt remains asserted until INTF0 is cleared."] - #[inline(always)] - pub const fn intf1(&self) -> u16 { - let val = (self.0 >> 0usize) & 0xffff; - val as u16 - } - #[doc = "Write 1s to force the corresponding bits in INTE0. The interrupt remains asserted until INTF0 is cleared."] - #[inline(always)] - pub fn set_intf1(&mut self, val: u16) { - self.0 = (self.0 & !(0xffff << 0usize)) | (((val as u32) & 0xffff) << 0usize); - } -} -impl Default for Intf1 { - #[inline(always)] - fn default() -> Intf1 { - Intf1(0) - } -} -#[doc = "Interrupt Status (raw)"] -#[repr(transparent)] -#[derive(Copy, Clone, Eq, PartialEq)] -pub struct Intr(pub u32); -impl Intr { - #[doc = "Raw interrupt status for DMA Channels 0..15. Bit n corresponds to channel n. Ignores any masking or forcing. Channel interrupts can be cleared by writing a bit mask to INTR, INTS0 or INTS1. Channel interrupts can be routed to either of two system-level IRQs based on INTE0 and INTE1. This can be used vector different channel interrupts to different ISRs: this might be done to allow NVIC IRQ preemption for more time-critical channels, or to spread IRQ load across different cores. It is also valid to ignore this behaviour and just use INTE0/INTS0/IRQ 0."] - #[inline(always)] - pub const fn intr(&self) -> u16 { - let val = (self.0 >> 0usize) & 0xffff; - val as u16 - } - #[doc = "Raw interrupt status for DMA Channels 0..15. Bit n corresponds to channel n. Ignores any masking or forcing. Channel interrupts can be cleared by writing a bit mask to INTR, INTS0 or INTS1. Channel interrupts can be routed to either of two system-level IRQs based on INTE0 and INTE1. This can be used vector different channel interrupts to different ISRs: this might be done to allow NVIC IRQ preemption for more time-critical channels, or to spread IRQ load across different cores. It is also valid to ignore this behaviour and just use INTE0/INTS0/IRQ 0."] - #[inline(always)] - pub fn set_intr(&mut self, val: u16) { - self.0 = (self.0 & !(0xffff << 0usize)) | (((val as u32) & 0xffff) << 0usize); - } -} -impl Default for Intr { - #[inline(always)] - fn default() -> Intr { - Intr(0) - } -} -#[doc = "Interrupt Status (raw)"] -#[repr(transparent)] -#[derive(Copy, Clone, Eq, PartialEq)] -pub struct Intr1(pub u32); -impl Intr1 { - #[doc = "Raw interrupt status for DMA Channels 0..15. Bit n corresponds to channel n. Ignores any masking or forcing. Channel interrupts can be cleared by writing a bit mask to INTR, INTS0 or INTS1. Channel interrupts can be routed to either of two system-level IRQs based on INTE0 and INTE1. This can be used vector different channel interrupts to different ISRs: this might be done to allow NVIC IRQ preemption for more time-critical channels, or to spread IRQ load across different cores. It is also valid to ignore this behaviour and just use INTE0/INTS0/IRQ 0."] - #[inline(always)] - pub const fn intr1(&self) -> u16 { - let val = (self.0 >> 0usize) & 0xffff; - val as u16 - } - #[doc = "Raw interrupt status for DMA Channels 0..15. Bit n corresponds to channel n. Ignores any masking or forcing. Channel interrupts can be cleared by writing a bit mask to INTR, INTS0 or INTS1. Channel interrupts can be routed to either of two system-level IRQs based on INTE0 and INTE1. This can be used vector different channel interrupts to different ISRs: this might be done to allow NVIC IRQ preemption for more time-critical channels, or to spread IRQ load across different cores. It is also valid to ignore this behaviour and just use INTE0/INTS0/IRQ 0."] - #[inline(always)] - pub fn set_intr1(&mut self, val: u16) { - self.0 = (self.0 & !(0xffff << 0usize)) | (((val as u32) & 0xffff) << 0usize); - } -} -impl Default for Intr1 { - #[inline(always)] - fn default() -> Intr1 { - Intr1(0) - } -} -#[doc = "Interrupt Status for IRQ 0"] -#[repr(transparent)] -#[derive(Copy, Clone, Eq, PartialEq)] -pub struct Ints0(pub u32); -impl Ints0 { - #[doc = "Indicates active channel interrupt requests which are currently causing IRQ 0 to be asserted. Channel interrupts can be cleared by writing a bit mask here."] - #[inline(always)] - pub const fn ints0(&self) -> u16 { - let val = (self.0 >> 0usize) & 0xffff; - val as u16 - } - #[doc = "Indicates active channel interrupt requests which are currently causing IRQ 0 to be asserted. Channel interrupts can be cleared by writing a bit mask here."] - #[inline(always)] - pub fn set_ints0(&mut self, val: u16) { - self.0 = (self.0 & !(0xffff << 0usize)) | (((val as u32) & 0xffff) << 0usize); - } -} -impl Default for Ints0 { - #[inline(always)] - fn default() -> Ints0 { - Ints0(0) - } -} -#[doc = "Interrupt Status (masked) for IRQ 1"] -#[repr(transparent)] -#[derive(Copy, Clone, Eq, PartialEq)] -pub struct Ints1(pub u32); -impl Ints1 { - #[doc = "Indicates active channel interrupt requests which are currently causing IRQ 1 to be asserted. Channel interrupts can be cleared by writing a bit mask here."] - #[inline(always)] - pub const fn ints1(&self) -> u16 { - let val = (self.0 >> 0usize) & 0xffff; - val as u16 - } - #[doc = "Indicates active channel interrupt requests which are currently causing IRQ 1 to be asserted. Channel interrupts can be cleared by writing a bit mask here."] - #[inline(always)] - pub fn set_ints1(&mut self, val: u16) { - self.0 = (self.0 & !(0xffff << 0usize)) | (((val as u32) & 0xffff) << 0usize); - } -} -impl Default for Ints1 { - #[inline(always)] - fn default() -> Ints1 { - Ints1(0) - } -} #[doc = "Trigger one or more channels simultaneously"] #[repr(transparent)] #[derive(Copy, Clone, Eq, PartialEq)] diff --git a/src/rp2040/dma/vals.rs b/src/rp2040/dma/vals.rs index 16ff1a32..5f00342a 100644 --- a/src/rp2040/dma/vals.rs +++ b/src/rp2040/dma/vals.rs @@ -2,7 +2,7 @@ #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] pub enum Calc { #[doc = "Calculate a CRC-32 (IEEE802.3 polynomial)"] - CRC32 = 0, + CRC32 = 0x0, #[doc = "Calculate a CRC-32 (IEEE802.3 polynomial) with bit reversed data"] CRC32R = 0x01, #[doc = "Calculate a CRC-16-CCITT"] @@ -49,7 +49,7 @@ impl From for u8 { #[repr(u8)] #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] pub enum DataSize { - SIZE_BYTE = 0, + SIZE_BYTE = 0x0, SIZE_HALFWORD = 0x01, SIZE_WORD = 0x02, _RESERVED_3 = 0x03, @@ -80,7 +80,7 @@ impl From for u8 { #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] pub enum TreqSel { #[doc = "Select PIO0's TX FIFO 0 as TREQ"] - PIO0_TX0 = 0, + PIO0_TX0 = 0x0, #[doc = "Select PIO0's TX FIFO 1 as TREQ"] PIO0_TX1 = 0x01, #[doc = "Select PIO0's TX FIFO 2 as TREQ"] diff --git a/src/rp2040/i2c.rs b/src/rp2040/i2c.rs index c752f5d1..1580aa4b 100644 --- a/src/rp2040/i2c.rs +++ b/src/rp2040/i2c.rs @@ -17,236 +17,236 @@ impl I2c { #[doc = "I2C Control Register. This register can be written only when the DW_apb_i2c is disabled, which corresponds to the IC_ENABLE\\[0\\] register being set to 0. Writes at other times have no effect. Read/Write Access: - bit 10 is read only. - bit 11 is read only - bit 16 is read only - bit 17 is read only - bits 18 and 19 are read only."] #[inline(always)] pub const fn ic_con(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(0usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x0usize) as _) } } #[doc = "I2C Target Address Register This register is 12 bits wide, and bits 31:12 are reserved. This register can be written to only when IC_ENABLE\\[0\\] is set to 0. Note: If the software or application is aware that the DW_apb_i2c is not using the TAR address for the pending commands in the Tx FIFO, then it is possible to update the TAR address even while the Tx FIFO has entries (IC_STATUS\\[2\\]= 0). - It is not necessary to perform any write to this register if DW_apb_i2c is enabled as an I2C slave only."] #[inline(always)] pub const fn ic_tar(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(4usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x04usize) as _) } } #[doc = "I2C Slave Address Register"] #[inline(always)] pub const fn ic_sar(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(8usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x08usize) as _) } } #[doc = "I2C Rx/Tx Data Buffer and Command Register; this is the register the CPU writes to when filling the TX FIFO and the CPU reads from when retrieving bytes from RX FIFO. The size of the register changes as follows: Write: - 11 bits when IC_EMPTYFIFO_HOLD_MASTER_EN=1 - 9 bits when IC_EMPTYFIFO_HOLD_MASTER_EN=0 Read: - 12 bits when IC_FIRST_DATA_BYTE_STATUS = 1 - 8 bits when IC_FIRST_DATA_BYTE_STATUS = 0 Note: In order for the DW_apb_i2c to continue acknowledging reads, a read command should be written for every byte that is to be received; otherwise the DW_apb_i2c will stop acknowledging."] #[inline(always)] pub const fn ic_data_cmd(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(16usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x10usize) as _) } } #[doc = "Standard Speed I2C Clock SCL High Count Register"] #[inline(always)] pub const fn ic_ss_scl_hcnt(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(20usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x14usize) as _) } } #[doc = "Standard Speed I2C Clock SCL Low Count Register"] #[inline(always)] pub const fn ic_ss_scl_lcnt(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(24usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x18usize) as _) } } #[doc = "Fast Mode or Fast Mode Plus I2C Clock SCL High Count Register"] #[inline(always)] pub const fn ic_fs_scl_hcnt(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(28usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x1cusize) as _) } } #[doc = "Fast Mode or Fast Mode Plus I2C Clock SCL Low Count Register"] #[inline(always)] pub const fn ic_fs_scl_lcnt(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(32usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x20usize) as _) } } #[doc = "I2C Interrupt Status Register Each bit in this register has a corresponding mask bit in the IC_INTR_MASK register. These bits are cleared by reading the matching interrupt clear register. The unmasked raw versions of these bits are available in the IC_RAW_INTR_STAT register."] #[inline(always)] pub const fn ic_intr_stat(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(44usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x2cusize) as _) } } #[doc = "I2C Interrupt Mask Register. These bits mask their corresponding interrupt status bits. This register is active low; a value of 0 masks the interrupt, whereas a value of 1 unmasks the interrupt."] #[inline(always)] pub const fn ic_intr_mask(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(48usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x30usize) as _) } } #[doc = "I2C Raw Interrupt Status Register Unlike the IC_INTR_STAT register, these bits are not masked so they always show the true status of the DW_apb_i2c."] #[inline(always)] pub const fn ic_raw_intr_stat( self, ) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(52usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x34usize) as _) } } #[doc = "I2C Receive FIFO Threshold Register"] #[inline(always)] pub const fn ic_rx_tl(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(56usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x38usize) as _) } } #[doc = "I2C Transmit FIFO Threshold Register"] #[inline(always)] pub const fn ic_tx_tl(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(60usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x3cusize) as _) } } #[doc = "Clear Combined and Individual Interrupt Register"] #[inline(always)] pub const fn ic_clr_intr(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(64usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x40usize) as _) } } #[doc = "Clear RX_UNDER Interrupt Register"] #[inline(always)] pub const fn ic_clr_rx_under( self, ) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(68usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x44usize) as _) } } #[doc = "Clear RX_OVER Interrupt Register"] #[inline(always)] pub const fn ic_clr_rx_over(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(72usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x48usize) as _) } } #[doc = "Clear TX_OVER Interrupt Register"] #[inline(always)] pub const fn ic_clr_tx_over(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(76usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x4cusize) as _) } } #[doc = "Clear RD_REQ Interrupt Register"] #[inline(always)] pub const fn ic_clr_rd_req(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(80usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x50usize) as _) } } #[doc = "Clear TX_ABRT Interrupt Register"] #[inline(always)] pub const fn ic_clr_tx_abrt(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(84usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x54usize) as _) } } #[doc = "Clear RX_DONE Interrupt Register"] #[inline(always)] pub const fn ic_clr_rx_done(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(88usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x58usize) as _) } } #[doc = "Clear ACTIVITY Interrupt Register"] #[inline(always)] pub const fn ic_clr_activity( self, ) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(92usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x5cusize) as _) } } #[doc = "Clear STOP_DET Interrupt Register"] #[inline(always)] pub const fn ic_clr_stop_det( self, ) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(96usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x60usize) as _) } } #[doc = "Clear START_DET Interrupt Register"] #[inline(always)] pub const fn ic_clr_start_det( self, ) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(100usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x64usize) as _) } } #[doc = "Clear GEN_CALL Interrupt Register"] #[inline(always)] pub const fn ic_clr_gen_call( self, ) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(104usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x68usize) as _) } } #[doc = "I2C Enable Register"] #[inline(always)] pub const fn ic_enable(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(108usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x6cusize) as _) } } #[doc = "I2C Status Register This is a read-only register used to indicate the current transfer status and FIFO status. The status register may be read at any time. None of the bits in this register request an interrupt. When the I2C is disabled by writing 0 in bit 0 of the IC_ENABLE register: - Bits 1 and 2 are set to 1 - Bits 3 and 10 are set to 0 When the master or slave state machines goes to idle and ic_en=0: - Bits 5 and 6 are set to 0"] #[inline(always)] pub const fn ic_status(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(112usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x70usize) as _) } } #[doc = "I2C Transmit FIFO Level Register This register contains the number of valid data entries in the transmit FIFO buffer. It is cleared whenever: - The I2C is disabled - There is a transmit abort - that is, TX_ABRT bit is set in the IC_RAW_INTR_STAT register - The slave bulk transmit mode is aborted The register increments whenever data is placed into the transmit FIFO and decrements when data is taken from the transmit FIFO."] #[inline(always)] pub const fn ic_txflr(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(116usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x74usize) as _) } } #[doc = "I2C Receive FIFO Level Register This register contains the number of valid data entries in the receive FIFO buffer. It is cleared whenever: - The I2C is disabled - Whenever there is a transmit abort caused by any of the events tracked in IC_TX_ABRT_SOURCE The register increments whenever data is placed into the receive FIFO and decrements when data is taken from the receive FIFO."] #[inline(always)] pub const fn ic_rxflr(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(120usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x78usize) as _) } } #[doc = "I2C SDA Hold Time Length Register The bits \\[15:0\\] of this register are used to control the hold time of SDA during transmit in both slave and master mode (after SCL goes from HIGH to LOW). The bits \\[23:16\\] of this register are used to extend the SDA transition (if any) whenever SCL is HIGH in the receiver in either master or slave mode. Writes to this register succeed only when IC_ENABLE\\[0\\]=0. The values in this register are in units of ic_clk period. The value programmed in IC_SDA_TX_HOLD must be greater than the minimum hold time in each mode (one cycle in master mode, seven cycles in slave mode) for the value to be implemented. The programmed SDA hold time during transmit (IC_SDA_TX_HOLD) cannot exceed at any time the duration of the low part of scl. Therefore the programmed value cannot be larger than N_SCL_LOW-2, where N_SCL_LOW is the duration of the low part of the scl period measured in ic_clk cycles."] #[inline(always)] pub const fn ic_sda_hold(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(124usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x7cusize) as _) } } #[doc = "I2C Transmit Abort Source Register This register has 32 bits that indicate the source of the TX_ABRT bit. Except for Bit 9, this register is cleared whenever the IC_CLR_TX_ABRT register or the IC_CLR_INTR register is read. To clear Bit 9, the source of the ABRT_SBYTE_NORSTRT must be fixed first; RESTART must be enabled (IC_CON\\[5\\]=1), the SPECIAL bit must be cleared (IC_TAR\\[11\\]), or the GC_OR_START bit must be cleared (IC_TAR\\[10\\]). Once the source of the ABRT_SBYTE_NORSTRT is fixed, then this bit can be cleared in the same manner as other bits in this register. If the source of the ABRT_SBYTE_NORSTRT is not fixed before attempting to clear this bit, Bit 9 clears for one cycle and is then re-asserted."] #[inline(always)] pub const fn ic_tx_abrt_source( self, ) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(128usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x80usize) as _) } } #[doc = "Generate Slave Data NACK Register The register is used to generate a NACK for the data part of a transfer when DW_apb_i2c is acting as a slave-receiver. This register only exists when the IC_SLV_DATA_NACK_ONLY parameter is set to 1. When this parameter disabled, this register does not exist and writing to the register's address has no effect. A write can occur on this register if both of the following conditions are met: - DW_apb_i2c is disabled (IC_ENABLE\\[0\\] = 0) - Slave part is inactive (IC_STATUS\\[6\\] = 0) Note: The IC_STATUS\\[6\\] is a register read-back location for the internal slv_activity signal; the user should poll this before writing the ic_slv_data_nack_only bit."] #[inline(always)] pub const fn ic_slv_data_nack_only( self, ) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(132usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x84usize) as _) } } #[doc = "DMA Control Register The register is used to enable the DMA Controller interface operation. There is a separate bit for transmit and receive. This can be programmed regardless of the state of IC_ENABLE."] #[inline(always)] pub const fn ic_dma_cr(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(136usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x88usize) as _) } } #[doc = "DMA Transmit Data Level Register"] #[inline(always)] pub const fn ic_dma_tdlr(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(140usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x8cusize) as _) } } #[doc = "I2C Receive Data Level Register"] #[inline(always)] pub const fn ic_dma_rdlr(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(144usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x90usize) as _) } } #[doc = "I2C SDA Setup Register This register controls the amount of time delay (in terms of number of ic_clk clock periods) introduced in the rising edge of SCL - relative to SDA changing - when DW_apb_i2c services a read request in a slave-transmitter operation. The relevant I2C requirement is tSU:DAT (note 4) as detailed in the I2C Bus Specification. This register must be programmed with a value equal to or greater than 2. Writes to this register succeed only when IC_ENABLE\\[0\\] = 0. Note: The length of setup time is calculated using \\[(IC_SDA_SETUP - 1) * (ic_clk_period)\\], so if the user requires 10 ic_clk periods of setup time, they should program a value of 11. The IC_SDA_SETUP register is only used by the DW_apb_i2c when operating as a slave transmitter."] #[inline(always)] pub const fn ic_sda_setup(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(148usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x94usize) as _) } } #[doc = "I2C ACK General Call Register The register controls whether DW_apb_i2c responds with a ACK or NACK when it receives an I2C General Call address. This register is applicable only when the DW_apb_i2c is in slave mode."] #[inline(always)] pub const fn ic_ack_general_call( self, ) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(152usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x98usize) as _) } } #[doc = "I2C Enable Status Register The register is used to report the DW_apb_i2c hardware status when the IC_ENABLE\\[0\\] register is set from 1 to 0; that is, when DW_apb_i2c is disabled. If IC_ENABLE\\[0\\] has been set to 1, bits 2:1 are forced to 0, and bit 0 is forced to 1. If IC_ENABLE\\[0\\] has been set to 0, bits 2:1 is only be valid as soon as bit 0 is read as '0'. Note: When IC_ENABLE\\[0\\] has been set to 0, a delay occurs for bit 0 to be read as 0 because disabling the DW_apb_i2c depends on I2C bus activities."] #[inline(always)] pub const fn ic_enable_status( self, ) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(156usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x9cusize) as _) } } #[doc = "I2C SS, FS or FM+ spike suppression limit This register is used to store the duration, measured in ic_clk cycles, of the longest spike that is filtered out by the spike suppression logic when the component is operating in SS, FS or FM+ modes. The relevant I2C requirement is tSP (table 4) as detailed in the I2C Bus Specification. This register must be programmed with a minimum value of 1."] #[inline(always)] pub const fn ic_fs_spklen(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(160usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0xa0usize) as _) } } #[doc = "Clear RESTART_DET Interrupt Register"] #[inline(always)] pub const fn ic_clr_restart_det( self, ) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(168usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0xa8usize) as _) } } #[doc = "Component Parameter Register 1 Note This register is not implemented and therefore reads as 0. If it was implemented it would be a constant read-only register that contains encoded information about the component's parameter settings. Fields shown below are the settings for those parameters"] #[inline(always)] pub const fn ic_comp_param_1( self, ) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(244usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0xf4usize) as _) } } #[doc = "I2C Component Version Register"] #[inline(always)] pub const fn ic_comp_version(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(248usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0xf8usize) as _) } } #[doc = "I2C Component Type Register"] #[inline(always)] pub const fn ic_comp_type(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(252usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0xfcusize) as _) } } } pub mod regs; diff --git a/src/rp2040/i2c/vals.rs b/src/rp2040/i2c/vals.rs index 41e0860e..3755ac03 100644 --- a/src/rp2040/i2c/vals.rs +++ b/src/rp2040/i2c/vals.rs @@ -1,7 +1,7 @@ #[repr(u8)] #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] pub enum Speed { - _RESERVED_0 = 0, + _RESERVED_0 = 0x0, #[doc = "Standard Speed mode of operation"] STANDARD = 0x01, #[doc = "Fast or Fast Plus mode of operation"] diff --git a/src/rp2040/io.rs b/src/rp2040/io.rs index 6af22042..afc66885 100644 --- a/src/rp2040/io.rs +++ b/src/rp2040/io.rs @@ -16,12 +16,12 @@ impl Gpio { #[doc = "GPIO status"] #[inline(always)] pub const fn status(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(0usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x0usize) as _) } } #[doc = "GPIO control including function select and overrides."] #[inline(always)] pub const fn ctrl(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(4usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x04usize) as _) } } } #[derive(Copy, Clone, Eq, PartialEq)] @@ -39,23 +39,23 @@ impl Int { pub const fn as_ptr(&self) -> *mut () { self.ptr as _ } - #[doc = "Interrupt Enable for proc0"] + #[doc = "Interrupt Enable for proc1"] #[inline(always)] pub const fn inte(self, n: usize) -> crate::common::Reg { assert!(n < 4usize); - unsafe { crate::common::Reg::from_ptr(self.ptr.add(0usize + n * 4usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x0usize + n * 4usize) as _) } } - #[doc = "Interrupt Force for proc0"] + #[doc = "Interrupt Force for proc1"] #[inline(always)] pub const fn intf(self, n: usize) -> crate::common::Reg { assert!(n < 4usize); - unsafe { crate::common::Reg::from_ptr(self.ptr.add(16usize + n * 4usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x10usize + n * 4usize) as _) } } - #[doc = "Interrupt status after masking & forcing for proc0"] + #[doc = "Interrupt status after masking & forcing for proc1"] #[inline(always)] pub const fn ints(self, n: usize) -> crate::common::Reg { assert!(n < 4usize); - unsafe { crate::common::Reg::from_ptr(self.ptr.add(32usize + n * 4usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x20usize + n * 4usize) as _) } } } #[derive(Copy, Clone, Eq, PartialEq)] @@ -76,22 +76,22 @@ impl Io { #[inline(always)] pub const fn gpio(self, n: usize) -> Gpio { assert!(n < 30usize); - unsafe { Gpio::from_ptr(self.ptr.add(0usize + n * 8usize) as _) } + unsafe { Gpio::from_ptr(self.ptr.add(0x0usize + n * 8usize) as _) } } #[doc = "Raw Interrupts"] #[inline(always)] pub const fn intr(self, n: usize) -> crate::common::Reg { assert!(n < 4usize); - unsafe { crate::common::Reg::from_ptr(self.ptr.add(240usize + n * 4usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0xf0usize + n * 4usize) as _) } } #[inline(always)] pub const fn int_proc(self, n: usize) -> Int { assert!(n < 2usize); - unsafe { Int::from_ptr(self.ptr.add(256usize + n * 48usize) as _) } + unsafe { Int::from_ptr(self.ptr.add(0x0100usize + n * 48usize) as _) } } #[inline(always)] pub const fn int_dormant_wake(self) -> Int { - unsafe { Int::from_ptr(self.ptr.add(352usize) as _) } + unsafe { Int::from_ptr(self.ptr.add(0x0160usize) as _) } } } pub mod regs; diff --git a/src/rp2040/io/regs.rs b/src/rp2040/io/regs.rs index 6af45e8c..524c6d61 100644 --- a/src/rp2040/io/regs.rs +++ b/src/rp2040/io/regs.rs @@ -157,7 +157,7 @@ impl Default for GpioStatus { GpioStatus(0) } } -#[doc = "Interrupt Force for proc0"] +#[doc = "Interrupt status after masking & forcing for proc1"] #[repr(transparent)] #[derive(Copy, Clone, Eq, PartialEq)] pub struct Int(pub u32); diff --git a/src/rp2040/io/vals.rs b/src/rp2040/io/vals.rs index 91264334..7ad8b463 100644 --- a/src/rp2040/io/vals.rs +++ b/src/rp2040/io/vals.rs @@ -1,7 +1,7 @@ #[repr(u8)] #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] pub enum Gpio0ctrlFuncsel { - JTAG_TCK = 0, + JTAG_TCK = 0x0, SPI0_RX = 0x01, UART0_TX = 0x02, I2C0_SDA = 0x03, @@ -59,7 +59,7 @@ impl From for u8 { #[repr(u8)] #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] pub enum Gpio10ctrlFuncsel { - _RESERVED_0 = 0, + _RESERVED_0 = 0x0, SPI1_SCLK = 0x01, UART1_CTS = 0x02, I2C1_SDA = 0x03, @@ -117,7 +117,7 @@ impl From for u8 { #[repr(u8)] #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] pub enum Gpio11ctrlFuncsel { - _RESERVED_0 = 0, + _RESERVED_0 = 0x0, SPI1_TX = 0x01, UART1_RTS = 0x02, I2C1_SCL = 0x03, @@ -175,7 +175,7 @@ impl From for u8 { #[repr(u8)] #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] pub enum Gpio12ctrlFuncsel { - _RESERVED_0 = 0, + _RESERVED_0 = 0x0, SPI1_RX = 0x01, UART0_TX = 0x02, I2C0_SDA = 0x03, @@ -233,7 +233,7 @@ impl From for u8 { #[repr(u8)] #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] pub enum Gpio13ctrlFuncsel { - _RESERVED_0 = 0, + _RESERVED_0 = 0x0, SPI1_SS_N = 0x01, UART0_RX = 0x02, I2C0_SCL = 0x03, @@ -291,7 +291,7 @@ impl From for u8 { #[repr(u8)] #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] pub enum Gpio14ctrlFuncsel { - _RESERVED_0 = 0, + _RESERVED_0 = 0x0, SPI1_SCLK = 0x01, UART0_CTS = 0x02, I2C1_SDA = 0x03, @@ -349,7 +349,7 @@ impl From for u8 { #[repr(u8)] #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] pub enum Gpio15ctrlFuncsel { - _RESERVED_0 = 0, + _RESERVED_0 = 0x0, SPI1_TX = 0x01, UART0_RTS = 0x02, I2C1_SCL = 0x03, @@ -407,7 +407,7 @@ impl From for u8 { #[repr(u8)] #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] pub enum Gpio16ctrlFuncsel { - _RESERVED_0 = 0, + _RESERVED_0 = 0x0, SPI0_RX = 0x01, UART0_TX = 0x02, I2C0_SDA = 0x03, @@ -465,7 +465,7 @@ impl From for u8 { #[repr(u8)] #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] pub enum Gpio17ctrlFuncsel { - _RESERVED_0 = 0, + _RESERVED_0 = 0x0, SPI0_SS_N = 0x01, UART0_RX = 0x02, I2C0_SCL = 0x03, @@ -523,7 +523,7 @@ impl From for u8 { #[repr(u8)] #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] pub enum Gpio18ctrlFuncsel { - _RESERVED_0 = 0, + _RESERVED_0 = 0x0, SPI0_SCLK = 0x01, UART0_CTS = 0x02, I2C1_SDA = 0x03, @@ -581,7 +581,7 @@ impl From for u8 { #[repr(u8)] #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] pub enum Gpio19ctrlFuncsel { - _RESERVED_0 = 0, + _RESERVED_0 = 0x0, SPI0_TX = 0x01, UART0_RTS = 0x02, I2C1_SCL = 0x03, @@ -639,7 +639,7 @@ impl From for u8 { #[repr(u8)] #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] pub enum Gpio1ctrlFuncsel { - JTAG_TMS = 0, + JTAG_TMS = 0x0, SPI0_SS_N = 0x01, UART0_RX = 0x02, I2C0_SCL = 0x03, @@ -697,7 +697,7 @@ impl From for u8 { #[repr(u8)] #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] pub enum Gpio20ctrlFuncsel { - _RESERVED_0 = 0, + _RESERVED_0 = 0x0, SPI0_RX = 0x01, UART1_TX = 0x02, I2C0_SDA = 0x03, @@ -755,7 +755,7 @@ impl From for u8 { #[repr(u8)] #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] pub enum Gpio21ctrlFuncsel { - _RESERVED_0 = 0, + _RESERVED_0 = 0x0, SPI0_SS_N = 0x01, UART1_RX = 0x02, I2C0_SCL = 0x03, @@ -813,7 +813,7 @@ impl From for u8 { #[repr(u8)] #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] pub enum Gpio22ctrlFuncsel { - _RESERVED_0 = 0, + _RESERVED_0 = 0x0, SPI0_SCLK = 0x01, UART1_CTS = 0x02, I2C1_SDA = 0x03, @@ -871,7 +871,7 @@ impl From for u8 { #[repr(u8)] #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] pub enum Gpio23ctrlFuncsel { - _RESERVED_0 = 0, + _RESERVED_0 = 0x0, SPI0_TX = 0x01, UART1_RTS = 0x02, I2C1_SCL = 0x03, @@ -929,7 +929,7 @@ impl From for u8 { #[repr(u8)] #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] pub enum Gpio24ctrlFuncsel { - _RESERVED_0 = 0, + _RESERVED_0 = 0x0, SPI1_RX = 0x01, UART1_TX = 0x02, I2C0_SDA = 0x03, @@ -987,7 +987,7 @@ impl From for u8 { #[repr(u8)] #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] pub enum Gpio25ctrlFuncsel { - _RESERVED_0 = 0, + _RESERVED_0 = 0x0, SPI1_SS_N = 0x01, UART1_RX = 0x02, I2C0_SCL = 0x03, @@ -1045,7 +1045,7 @@ impl From for u8 { #[repr(u8)] #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] pub enum Gpio26ctrlFuncsel { - _RESERVED_0 = 0, + _RESERVED_0 = 0x0, SPI1_SCLK = 0x01, UART1_CTS = 0x02, I2C1_SDA = 0x03, @@ -1103,7 +1103,7 @@ impl From for u8 { #[repr(u8)] #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] pub enum Gpio27ctrlFuncsel { - _RESERVED_0 = 0, + _RESERVED_0 = 0x0, SPI1_TX = 0x01, UART1_RTS = 0x02, I2C1_SCL = 0x03, @@ -1161,7 +1161,7 @@ impl From for u8 { #[repr(u8)] #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] pub enum Gpio28ctrlFuncsel { - _RESERVED_0 = 0, + _RESERVED_0 = 0x0, SPI1_RX = 0x01, UART0_TX = 0x02, I2C0_SDA = 0x03, @@ -1219,7 +1219,7 @@ impl From for u8 { #[repr(u8)] #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] pub enum Gpio29ctrlFuncsel { - _RESERVED_0 = 0, + _RESERVED_0 = 0x0, SPI1_SS_N = 0x01, UART0_RX = 0x02, I2C0_SCL = 0x03, @@ -1277,7 +1277,7 @@ impl From for u8 { #[repr(u8)] #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] pub enum Gpio2ctrlFuncsel { - JTAG_TDI = 0, + JTAG_TDI = 0x0, SPI0_SCLK = 0x01, UART0_CTS = 0x02, I2C1_SDA = 0x03, @@ -1335,7 +1335,7 @@ impl From for u8 { #[repr(u8)] #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] pub enum Gpio3ctrlFuncsel { - JTAG_TDO = 0, + JTAG_TDO = 0x0, SPI0_TX = 0x01, UART0_RTS = 0x02, I2C1_SCL = 0x03, @@ -1393,7 +1393,7 @@ impl From for u8 { #[repr(u8)] #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] pub enum Gpio4ctrlFuncsel { - _RESERVED_0 = 0, + _RESERVED_0 = 0x0, SPI0_RX = 0x01, UART1_TX = 0x02, I2C0_SDA = 0x03, @@ -1451,7 +1451,7 @@ impl From for u8 { #[repr(u8)] #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] pub enum Gpio5ctrlFuncsel { - _RESERVED_0 = 0, + _RESERVED_0 = 0x0, SPI0_SS_N = 0x01, UART1_RX = 0x02, I2C0_SCL = 0x03, @@ -1509,7 +1509,7 @@ impl From for u8 { #[repr(u8)] #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] pub enum Gpio6ctrlFuncsel { - _RESERVED_0 = 0, + _RESERVED_0 = 0x0, SPI0_SCLK = 0x01, UART1_CTS = 0x02, I2C1_SDA = 0x03, @@ -1567,7 +1567,7 @@ impl From for u8 { #[repr(u8)] #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] pub enum Gpio7ctrlFuncsel { - _RESERVED_0 = 0, + _RESERVED_0 = 0x0, SPI0_TX = 0x01, UART1_RTS = 0x02, I2C1_SCL = 0x03, @@ -1625,7 +1625,7 @@ impl From for u8 { #[repr(u8)] #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] pub enum Gpio8ctrlFuncsel { - _RESERVED_0 = 0, + _RESERVED_0 = 0x0, SPI1_RX = 0x01, UART1_TX = 0x02, I2C0_SDA = 0x03, @@ -1683,7 +1683,7 @@ impl From for u8 { #[repr(u8)] #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] pub enum Gpio9ctrlFuncsel { - _RESERVED_0 = 0, + _RESERVED_0 = 0x0, SPI1_SS_N = 0x01, UART1_RX = 0x02, I2C0_SCL = 0x03, @@ -1742,7 +1742,7 @@ impl From for u8 { #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] pub enum Inover { #[doc = "don't invert the peri input"] - NORMAL = 0, + NORMAL = 0x0, #[doc = "invert the peri input"] INVERT = 0x01, #[doc = "drive peri input low"] @@ -1776,7 +1776,7 @@ impl From for u8 { #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] pub enum Irqover { #[doc = "don't invert the interrupt"] - NORMAL = 0, + NORMAL = 0x0, #[doc = "invert the interrupt"] INVERT = 0x01, #[doc = "drive interrupt low"] @@ -1810,7 +1810,7 @@ impl From for u8 { #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] pub enum Oeover { #[doc = "drive output enable from peripheral signal selected by funcsel"] - NORMAL = 0, + NORMAL = 0x0, #[doc = "drive output enable from inverse of peripheral signal selected by funcsel"] INVERT = 0x01, #[doc = "disable output"] @@ -1844,7 +1844,7 @@ impl From for u8 { #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] pub enum Outover { #[doc = "drive output from peripheral signal selected by funcsel"] - NORMAL = 0, + NORMAL = 0x0, #[doc = "drive output from inverse of peripheral signal selected by funcsel"] INVERT = 0x01, #[doc = "drive output low"] diff --git a/src/rp2040/pads.rs b/src/rp2040/pads.rs index 8e46b22b..15bb1465 100644 --- a/src/rp2040/pads.rs +++ b/src/rp2040/pads.rs @@ -18,13 +18,13 @@ impl Pads { pub const fn voltage_select( self, ) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(0usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x0usize) as _) } } #[doc = "Pad control register"] #[inline(always)] pub const fn gpio(self, n: usize) -> crate::common::Reg { assert!(n < 32usize); - unsafe { crate::common::Reg::from_ptr(self.ptr.add(4usize + n * 4usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x04usize + n * 4usize) as _) } } } pub mod regs; diff --git a/src/rp2040/pads/vals.rs b/src/rp2040/pads/vals.rs index f9e7d6c3..110c4b00 100644 --- a/src/rp2040/pads/vals.rs +++ b/src/rp2040/pads/vals.rs @@ -1,7 +1,7 @@ #[repr(u8)] #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] pub enum Drive { - _2MA = 0, + _2MA = 0x0, _4MA = 0x01, _8MA = 0x02, _12MA = 0x03, @@ -32,7 +32,7 @@ impl From for u8 { #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] pub enum VoltageSelect { #[doc = "Set voltage to 3.3V (DVDD >= 2V5)"] - _3V3 = 0, + _3V3 = 0x0, #[doc = "Set voltage to 1.8V (DVDD <= 1V8)"] _1V8 = 0x01, } diff --git a/src/rp2040/pio.rs b/src/rp2040/pio.rs index 7eb55ace..61062cda 100644 --- a/src/rp2040/pio.rs +++ b/src/rp2040/pio.rs @@ -16,17 +16,17 @@ impl Irq { #[doc = "Interrupt Enable for irq1"] #[inline(always)] pub const fn inte(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(0usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x0usize) as _) } } #[doc = "Interrupt Force for irq1"] #[inline(always)] pub const fn intf(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(4usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x04usize) as _) } } #[doc = "Interrupt status after masking & forcing for irq1"] #[inline(always)] pub const fn ints(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(8usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x08usize) as _) } } } #[doc = "Programmable IO block"] @@ -48,64 +48,64 @@ impl Pio { #[doc = "PIO control register"] #[inline(always)] pub const fn ctrl(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(0usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x0usize) as _) } } #[doc = "FIFO status register"] #[inline(always)] pub const fn fstat(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(4usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x04usize) as _) } } #[doc = "FIFO debug register"] #[inline(always)] pub const fn fdebug(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(8usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x08usize) as _) } } #[doc = "FIFO levels"] #[inline(always)] pub const fn flevel(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(12usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x0cusize) as _) } } #[doc = "Direct write access to the TX FIFO for this state machine. Each write pushes one word to the FIFO. Attempting to write to a full FIFO has no effect on the FIFO state or contents, and sets the sticky FDEBUG_TXOVER error flag for this FIFO."] #[inline(always)] pub const fn txf(self, n: usize) -> crate::common::Reg { assert!(n < 4usize); - unsafe { crate::common::Reg::from_ptr(self.ptr.add(16usize + n * 4usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x10usize + n * 4usize) as _) } } #[doc = "Direct read access to the RX FIFO for this state machine. Each read pops one word from the FIFO. Attempting to read from an empty FIFO has no effect on the FIFO state, and sets the sticky FDEBUG_RXUNDER error flag for this FIFO. The data returned to the system on a read from an empty FIFO is undefined."] #[inline(always)] pub const fn rxf(self, n: usize) -> crate::common::Reg { assert!(n < 4usize); - unsafe { crate::common::Reg::from_ptr(self.ptr.add(32usize + n * 4usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x20usize + n * 4usize) as _) } } #[doc = "State machine IRQ flags register. Write 1 to clear. There are 8 state machine IRQ flags, which can be set, cleared, and waited on by the state machines. There's no fixed association between flags and state machines -- any state machine can use any flag. Any of the 8 flags can be used for timing synchronisation between state machines, using IRQ and WAIT instructions. The lower four of these flags are also routed out to system-level interrupt requests, alongside FIFO status interrupts -- see e.g. IRQ0_INTE."] #[inline(always)] pub const fn irq(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(48usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x30usize) as _) } } #[doc = "Writing a 1 to each of these bits will forcibly assert the corresponding IRQ. Note this is different to the INTF register: writing here affects PIO internal state. INTF just asserts the processor-facing IRQ signal for testing ISRs, and is not visible to the state machines."] #[inline(always)] pub const fn irq_force(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(52usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x34usize) as _) } } #[doc = "There is a 2-flipflop synchronizer on each GPIO input, which protects PIO logic from metastabilities. This increases input delay, and for fast synchronous IO (e.g. SPI) these synchronizers may need to be bypassed. Each bit in this register corresponds to one GPIO. 0 -> input is synchronized (default) 1 -> synchronizer is bypassed If in doubt, leave this register as all zeroes."] #[inline(always)] pub const fn input_sync_bypass(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(56usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x38usize) as _) } } #[doc = "Read to sample the pad output values PIO is currently driving to the GPIOs. On RP2040 there are 30 GPIOs, so the two most significant bits are hardwired to 0."] #[inline(always)] pub const fn dbg_padout(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(60usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x3cusize) as _) } } #[doc = "Read to sample the pad output enables (direction) PIO is currently driving to the GPIOs. On RP2040 there are 30 GPIOs, so the two most significant bits are hardwired to 0."] #[inline(always)] pub const fn dbg_padoe(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(64usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x40usize) as _) } } #[doc = "The PIO hardware has some free parameters that may vary between chip products. These should be provided in the chip datasheet, but are also exposed here."] #[inline(always)] pub const fn dbg_cfginfo(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(68usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x44usize) as _) } } #[doc = "Write-only access to instruction memory location 0"] #[inline(always)] @@ -114,22 +114,22 @@ impl Pio { n: usize, ) -> crate::common::Reg { assert!(n < 32usize); - unsafe { crate::common::Reg::from_ptr(self.ptr.add(72usize + n * 4usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x48usize + n * 4usize) as _) } } #[inline(always)] pub const fn sm(self, n: usize) -> StateMachine { assert!(n < 4usize); - unsafe { StateMachine::from_ptr(self.ptr.add(200usize + n * 24usize) as _) } + unsafe { StateMachine::from_ptr(self.ptr.add(0xc8usize + n * 24usize) as _) } } #[doc = "Raw Interrupts"] #[inline(always)] pub const fn intr(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(296usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x0128usize) as _) } } #[inline(always)] pub const fn irqs(self, n: usize) -> Irq { assert!(n < 2usize); - unsafe { Irq::from_ptr(self.ptr.add(300usize + n * 12usize) as _) } + unsafe { Irq::from_ptr(self.ptr.add(0x012cusize + n * 12usize) as _) } } } #[derive(Copy, Clone, Eq, PartialEq)] @@ -147,35 +147,35 @@ impl StateMachine { pub const fn as_ptr(&self) -> *mut () { self.ptr as _ } - #[doc = "Clock divisor register for state machine 2 Frequency = clock freq / (CLKDIV_INT + CLKDIV_FRAC / 256)"] + #[doc = "Clock divisor register for state machine 3 Frequency = clock freq / (CLKDIV_INT + CLKDIV_FRAC / 256)"] #[inline(always)] pub const fn clkdiv(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(0usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x0usize) as _) } } - #[doc = "Execution/behavioural settings for state machine 2"] + #[doc = "Execution/behavioural settings for state machine 3"] #[inline(always)] pub const fn execctrl(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(4usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x04usize) as _) } } - #[doc = "Control behaviour of the input/output shift registers for state machine 2"] + #[doc = "Control behaviour of the input/output shift registers for state machine 3"] #[inline(always)] pub const fn shiftctrl(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(8usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x08usize) as _) } } - #[doc = "Current instruction address of state machine 2"] + #[doc = "Current instruction address of state machine 3"] #[inline(always)] pub const fn addr(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(12usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x0cusize) as _) } } - #[doc = "Read to see the instruction currently addressed by state machine 2's program counter Write to execute an instruction immediately (including jumps) and then resume execution."] + #[doc = "Read to see the instruction currently addressed by state machine 3's program counter Write to execute an instruction immediately (including jumps) and then resume execution."] #[inline(always)] pub const fn instr(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(16usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x10usize) as _) } } #[doc = "State machine pin control"] #[inline(always)] pub const fn pinctrl(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(20usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x14usize) as _) } } } pub mod regs; diff --git a/src/rp2040/pio/regs.rs b/src/rp2040/pio/regs.rs index 7fdd0207..029b4362 100644 --- a/src/rp2040/pio/regs.rs +++ b/src/rp2040/pio/regs.rs @@ -284,7 +284,7 @@ impl Default for Fstat { Fstat(0) } } -#[doc = "Write-only access to instruction memory location 23"] +#[doc = "Write-only access to instruction memory location 30"] #[repr(transparent)] #[derive(Copy, Clone, Eq, PartialEq)] pub struct InstrMem(pub u32); @@ -305,7 +305,7 @@ impl Default for InstrMem { InstrMem(0) } } -#[doc = "Interrupt status after masking & forcing for irq1"] +#[doc = "Interrupt status after masking & forcing for irq0"] #[repr(transparent)] #[derive(Copy, Clone, Eq, PartialEq)] pub struct Intr(pub u32); @@ -467,7 +467,7 @@ impl Default for IrqForce { IrqForce(0) } } -#[doc = "Current instruction address of state machine 2"] +#[doc = "Current instruction address of state machine 3"] #[repr(transparent)] #[derive(Copy, Clone, Eq, PartialEq)] pub struct SmAddr(pub u32); @@ -488,7 +488,7 @@ impl Default for SmAddr { SmAddr(0) } } -#[doc = "Clock divisor register for state machine 2 Frequency = clock freq / (CLKDIV_INT + CLKDIV_FRAC / 256)"] +#[doc = "Clock divisor register for state machine 0 Frequency = clock freq / (CLKDIV_INT + CLKDIV_FRAC / 256)"] #[repr(transparent)] #[derive(Copy, Clone, Eq, PartialEq)] pub struct SmClkdiv(pub u32); @@ -765,7 +765,7 @@ impl Default for SmPinctrl { SmPinctrl(0) } } -#[doc = "Control behaviour of the input/output shift registers for state machine 1"] +#[doc = "Control behaviour of the input/output shift registers for state machine 0"] #[repr(transparent)] #[derive(Copy, Clone, Eq, PartialEq)] pub struct SmShiftctrl(pub u32); diff --git a/src/rp2040/pio/vals.rs b/src/rp2040/pio/vals.rs index 0a80df0a..9eb4bd7a 100644 --- a/src/rp2040/pio/vals.rs +++ b/src/rp2040/pio/vals.rs @@ -2,7 +2,7 @@ #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] pub enum SmExecctrlStatusSel { #[doc = "All-ones if TX FIFO level < N, otherwise all-zeroes"] - TXLEVEL = 0, + TXLEVEL = 0x0, #[doc = "All-ones if RX FIFO level < N, otherwise all-zeroes"] RXLEVEL = 0x01, } diff --git a/src/rp2040/pll.rs b/src/rp2040/pll.rs index 75d6350e..d5bc862b 100644 --- a/src/rp2040/pll.rs +++ b/src/rp2040/pll.rs @@ -16,22 +16,22 @@ impl Pll { #[doc = "Control and Status GENERAL CONSTRAINTS: Reference clock frequency min=5MHz, max=800MHz Feedback divider min=16, max=320 VCO frequency min=750MHz, max=1600MHz"] #[inline(always)] pub const fn cs(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(0usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x0usize) as _) } } #[doc = "Controls the PLL power modes."] #[inline(always)] pub const fn pwr(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(4usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x04usize) as _) } } #[doc = "Feedback divisor (note: this PLL does not support fractional division)"] #[inline(always)] pub const fn fbdiv_int(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(8usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x08usize) as _) } } #[doc = "Controls the PLL post dividers for the primary output (note: this PLL does not have a secondary output) the primary output is driven from VCO divided by postdiv1*postdiv2"] #[inline(always)] pub const fn prim(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(12usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x0cusize) as _) } } } pub mod regs; diff --git a/src/rp2040/psm.rs b/src/rp2040/psm.rs index a8ad311d..3ad3fee7 100644 --- a/src/rp2040/psm.rs +++ b/src/rp2040/psm.rs @@ -16,22 +16,22 @@ impl Psm { #[doc = "Force block out of reset (i.e. power it on)"] #[inline(always)] pub const fn frce_on(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(0usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x0usize) as _) } } #[doc = "Force into reset (i.e. power it off)"] #[inline(always)] pub const fn frce_off(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(4usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x04usize) as _) } } #[doc = "Set to 1 if this peripheral should be reset when the watchdog fires."] #[inline(always)] pub const fn wdsel(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(8usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x08usize) as _) } } #[doc = "Indicates the peripheral's registers are ready to access."] #[inline(always)] pub const fn done(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(12usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x0cusize) as _) } } } pub mod regs; diff --git a/src/rp2040/pwm.rs b/src/rp2040/pwm.rs index e5f9a8dc..009e6804 100644 --- a/src/rp2040/pwm.rs +++ b/src/rp2040/pwm.rs @@ -16,27 +16,27 @@ impl Channel { #[doc = "Control and status register"] #[inline(always)] pub const fn csr(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(0usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x0usize) as _) } } #[doc = "INT and FRAC form a fixed-point fractional number. Counting rate is system clock frequency divided by this number. Fractional division uses simple 1st-order sigma-delta."] #[inline(always)] pub const fn div(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(4usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x04usize) as _) } } #[doc = "Direct access to the PWM counter"] #[inline(always)] pub const fn ctr(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(8usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x08usize) as _) } } #[doc = "Counter compare values"] #[inline(always)] pub const fn cc(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(12usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x0cusize) as _) } } #[doc = "Counter wrap value"] #[inline(always)] pub const fn top(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(16usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x10usize) as _) } } } #[doc = "Simple PWM"] @@ -58,32 +58,32 @@ impl Pwm { #[inline(always)] pub const fn ch(self, n: usize) -> Channel { assert!(n < 8usize); - unsafe { Channel::from_ptr(self.ptr.add(0usize + n * 20usize) as _) } + unsafe { Channel::from_ptr(self.ptr.add(0x0usize + n * 20usize) as _) } } #[doc = "This register aliases the CSR_EN bits for all channels. Writing to this register allows multiple channels to be enabled or disabled simultaneously, so they can run in perfect sync. For each channel, there is only one physical EN register bit, which can be accessed through here or CHx_CSR."] #[inline(always)] pub const fn en(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(160usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0xa0usize) as _) } } #[doc = "Raw Interrupts"] #[inline(always)] pub const fn intr(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(164usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0xa4usize) as _) } } #[doc = "Interrupt Enable"] #[inline(always)] pub const fn inte(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(168usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0xa8usize) as _) } } #[doc = "Interrupt Force"] #[inline(always)] pub const fn intf(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(172usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0xacusize) as _) } } #[doc = "Interrupt status after masking & forcing"] #[inline(always)] pub const fn ints(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(176usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0xb0usize) as _) } } } pub mod regs; diff --git a/src/rp2040/pwm/vals.rs b/src/rp2040/pwm/vals.rs index d71aae43..68721469 100644 --- a/src/rp2040/pwm/vals.rs +++ b/src/rp2040/pwm/vals.rs @@ -2,7 +2,7 @@ #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] pub enum Divmode { #[doc = "Free-running counting at rate dictated by fractional divider"] - DIV = 0, + DIV = 0x0, #[doc = "Fractional divider operation is gated by the PWM B pin."] LEVEL = 0x01, #[doc = "Counter advances with each rising edge of the PWM B pin."] diff --git a/src/rp2040/resets.rs b/src/rp2040/resets.rs index 3ab453af..884b3d46 100644 --- a/src/rp2040/resets.rs +++ b/src/rp2040/resets.rs @@ -16,17 +16,17 @@ impl Resets { #[doc = "Reset control. If a bit is set it means the peripheral is in reset. 0 means the peripheral's reset is deasserted."] #[inline(always)] pub const fn reset(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(0usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x0usize) as _) } } #[doc = "Watchdog select. If a bit is set then the watchdog will reset this peripheral when the watchdog fires."] #[inline(always)] pub const fn wdsel(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(4usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x04usize) as _) } } #[doc = "Reset done. If a bit is set then a reset done signal has been returned by the peripheral. This indicates that the peripheral's registers are ready to be accessed."] #[inline(always)] pub const fn reset_done(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(8usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x08usize) as _) } } } pub mod regs; diff --git a/src/rp2040/resets/regs.rs b/src/rp2040/resets/regs.rs index 22118fa1..0a9c9666 100644 --- a/src/rp2040/resets/regs.rs +++ b/src/rp2040/resets/regs.rs @@ -1,4 +1,4 @@ -#[doc = "Reset done. If a bit is set then a reset done signal has been returned by the peripheral. This indicates that the peripheral's registers are ready to be accessed."] +#[doc = "Reset control. If a bit is set it means the peripheral is in reset. 0 means the peripheral's reset is deasserted."] #[repr(transparent)] #[derive(Copy, Clone, Eq, PartialEq)] pub struct Peripherals(pub u32); diff --git a/src/rp2040/rosc.rs b/src/rp2040/rosc.rs index be5d2ae4..3fd32148 100644 --- a/src/rp2040/rosc.rs +++ b/src/rp2040/rosc.rs @@ -16,47 +16,47 @@ impl Rosc { #[doc = "Ring Oscillator control"] #[inline(always)] pub const fn ctrl(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(0usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x0usize) as _) } } #[doc = "The FREQA & FREQB registers control the frequency by controlling the drive strength of each stage The drive strength has 4 levels determined by the number of bits set Increasing the number of bits set increases the drive strength and increases the oscillation frequency 0 bits set is the default drive strength 1 bit set doubles the drive strength 2 bits set triples drive strength 3 bits set quadruples drive strength"] #[inline(always)] pub const fn freqa(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(4usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x04usize) as _) } } #[doc = "For a detailed description see freqa register"] #[inline(always)] pub const fn freqb(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(8usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x08usize) as _) } } #[doc = "Ring Oscillator pause control"] #[inline(always)] pub const fn dormant(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(12usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x0cusize) as _) } } #[doc = "Controls the output divider"] #[inline(always)] pub const fn div(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(16usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x10usize) as _) } } #[doc = "Controls the phase shifted output"] #[inline(always)] pub const fn phase(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(20usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x14usize) as _) } } #[doc = "Ring Oscillator Status"] #[inline(always)] pub const fn status(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(24usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x18usize) as _) } } #[doc = "This just reads the state of the oscillator output so randomness is compromised if the ring oscillator is stopped or run at a harmonic of the bus frequency"] #[inline(always)] pub const fn randombit(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(28usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x1cusize) as _) } } #[doc = "A down counter running at the ROSC frequency which counts to zero and stops. To start the counter write a non-zero value. Can be used for short software pauses when setting up time sensitive hardware."] #[inline(always)] pub const fn count(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(32usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x20usize) as _) } } } pub mod regs; diff --git a/src/rp2040/rtc.rs b/src/rp2040/rtc.rs index 9424c84f..93adb5b9 100644 --- a/src/rp2040/rtc.rs +++ b/src/rp2040/rtc.rs @@ -17,62 +17,62 @@ impl Rtc { #[doc = "Divider minus 1 for the 1 second counter. Safe to change the value when RTC is not enabled."] #[inline(always)] pub const fn clkdiv_m1(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(0usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x0usize) as _) } } #[doc = "RTC setup register 0"] #[inline(always)] pub const fn setup_0(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(4usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x04usize) as _) } } #[doc = "RTC setup register 1"] #[inline(always)] pub const fn setup_1(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(8usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x08usize) as _) } } #[doc = "RTC Control and status"] #[inline(always)] pub const fn ctrl(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(12usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x0cusize) as _) } } #[doc = "Interrupt setup register 0"] #[inline(always)] pub const fn irq_setup_0(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(16usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x10usize) as _) } } #[doc = "Interrupt setup register 1"] #[inline(always)] pub const fn irq_setup_1(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(20usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x14usize) as _) } } #[doc = "RTC register 1."] #[inline(always)] pub const fn rtc_1(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(24usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x18usize) as _) } } #[doc = "RTC register 0 Read this before RTC 1!"] #[inline(always)] pub const fn rtc_0(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(28usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x1cusize) as _) } } #[doc = "Raw Interrupts"] #[inline(always)] pub const fn intr(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(32usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x20usize) as _) } } #[doc = "Interrupt Enable"] #[inline(always)] pub const fn inte(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(36usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x24usize) as _) } } #[doc = "Interrupt Force"] #[inline(always)] pub const fn intf(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(40usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x28usize) as _) } } #[doc = "Interrupt status after masking & forcing"] #[inline(always)] pub const fn ints(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(44usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x2cusize) as _) } } } pub mod regs; diff --git a/src/rp2040/rtc/regs.rs b/src/rp2040/rtc/regs.rs index 17714b9e..da3ac3a8 100644 --- a/src/rp2040/rtc/regs.rs +++ b/src/rp2040/rtc/regs.rs @@ -75,7 +75,7 @@ impl Default for Ctrl { Ctrl(0) } } -#[doc = "Raw Interrupts"] +#[doc = "Interrupt Enable"] #[repr(transparent)] #[derive(Copy, Clone, Eq, PartialEq)] pub struct Int(pub u32); diff --git a/src/rp2040/sio.rs b/src/rp2040/sio.rs index 9f17277f..09db97ab 100644 --- a/src/rp2040/sio.rs +++ b/src/rp2040/sio.rs @@ -16,37 +16,37 @@ impl Div { #[doc = "Divider unsigned dividend Write to the DIVIDEND operand of the divider, i.e. the p in `p / q`. Any operand write starts a new calculation. The results appear in QUOTIENT, REMAINDER. UDIVIDEND/SDIVIDEND are aliases of the same internal register. The U alias starts an unsigned calculation, and the S alias starts a signed calculation."] #[inline(always)] pub const fn udividend(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(0usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x0usize) as _) } } #[doc = "Divider unsigned divisor Write to the DIVISOR operand of the divider, i.e. the q in `p / q`. Any operand write starts a new calculation. The results appear in QUOTIENT, REMAINDER. UDIVISOR/SDIVISOR are aliases of the same internal register. The U alias starts an unsigned calculation, and the S alias starts a signed calculation."] #[inline(always)] pub const fn udivisor(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(4usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x04usize) as _) } } #[doc = "Divider signed dividend The same as UDIVIDEND, but starts a signed calculation, rather than unsigned."] #[inline(always)] pub const fn sdividend(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(8usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x08usize) as _) } } #[doc = "Divider signed divisor The same as UDIVISOR, but starts a signed calculation, rather than unsigned."] #[inline(always)] pub const fn sdivisor(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(12usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x0cusize) as _) } } #[doc = "Divider result quotient The result of `DIVIDEND / DIVISOR` (division). Contents undefined while CSR_READY is low. For signed calculations, QUOTIENT is negative when the signs of DIVIDEND and DIVISOR differ. This register can be written to directly, for context save/restore purposes. This halts any in-progress calculation and sets the CSR_READY and CSR_DIRTY flags. Reading from QUOTIENT clears the CSR_DIRTY flag, so should read results in the order REMAINDER, QUOTIENT if CSR_DIRTY is used."] #[inline(always)] pub const fn quotient(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(16usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x10usize) as _) } } #[doc = "Divider result remainder The result of `DIVIDEND % DIVISOR` (modulo). Contents undefined while CSR_READY is low. For signed calculations, REMAINDER is negative only when DIVIDEND is negative. This register can be written to directly, for context save/restore purposes. This halts any in-progress calculation and sets the CSR_READY and CSR_DIRTY flags."] #[inline(always)] pub const fn remainder(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(20usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x14usize) as _) } } #[doc = "Control and status register for divider."] #[inline(always)] pub const fn csr(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(24usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x18usize) as _) } } } #[derive(Copy, Clone, Eq, PartialEq)] @@ -67,17 +67,17 @@ impl Fifo { #[doc = "Status register for inter-core FIFOs (mailboxes). There is one FIFO in the core 0 -> core 1 direction, and one core 1 -> core 0. Both are 32 bits wide and 8 words deep. Core 0 can see the read side of the 1->0 FIFO (RX), and the write side of 0->1 FIFO (TX). Core 1 can see the read side of the 0->1 FIFO (RX), and the write side of 1->0 FIFO (TX). The SIO IRQ for each core is the logical OR of the VLD, WOF and ROE fields of its FIFO_ST register."] #[inline(always)] pub const fn st(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(0usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x0usize) as _) } } #[doc = "Write access to this core's TX FIFO"] #[inline(always)] pub const fn wr(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(4usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x04usize) as _) } } #[doc = "Read access to this core's RX FIFO"] #[inline(always)] pub const fn rd(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(8usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x08usize) as _) } } } #[derive(Copy, Clone, Eq, PartialEq)] @@ -95,25 +95,25 @@ impl Gpio { pub const fn as_ptr(&self) -> *mut () { self.ptr as _ } - #[doc = "GPIO output value"] + #[doc = "GPIO output enable"] #[inline(always)] pub const fn value(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(0usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x0usize) as _) } } - #[doc = "GPIO output value set"] + #[doc = "GPIO output enable set"] #[inline(always)] pub const fn value_set(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(4usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x04usize) as _) } } - #[doc = "GPIO output value clear"] + #[doc = "GPIO output enable clear"] #[inline(always)] pub const fn value_clr(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(8usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x08usize) as _) } } - #[doc = "GPIO output value XOR"] + #[doc = "GPIO output enable XOR"] #[inline(always)] pub const fn value_xor(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(12usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x0cusize) as _) } } } #[derive(Copy, Clone, Eq, PartialEq)] @@ -134,82 +134,82 @@ impl Interp { #[doc = "Read/write access to accumulator 0"] #[inline(always)] pub const fn accum0(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(0usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x0usize) as _) } } #[doc = "Read/write access to accumulator 1"] #[inline(always)] pub const fn accum1(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(4usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x04usize) as _) } } #[doc = "Read/write access to BASE0 register."] #[inline(always)] pub const fn base0(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(8usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x08usize) as _) } } #[doc = "Read/write access to BASE1 register."] #[inline(always)] pub const fn base1(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(12usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x0cusize) as _) } } #[doc = "Read/write access to BASE2 register."] #[inline(always)] pub const fn base2(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(16usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x10usize) as _) } } #[doc = "Read LANE0 result, and simultaneously write lane results to both accumulators (POP)."] #[inline(always)] pub const fn pop_lane0(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(20usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x14usize) as _) } } #[doc = "Read LANE1 result, and simultaneously write lane results to both accumulators (POP)."] #[inline(always)] pub const fn pop_lane1(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(24usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x18usize) as _) } } #[doc = "Read FULL result, and simultaneously write lane results to both accumulators (POP)."] #[inline(always)] pub const fn pop_full(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(28usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x1cusize) as _) } } #[doc = "Read LANE0 result, without altering any internal state (PEEK)."] #[inline(always)] pub const fn peek_lane0(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(32usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x20usize) as _) } } #[doc = "Read LANE1 result, without altering any internal state (PEEK)."] #[inline(always)] pub const fn peek_lane1(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(36usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x24usize) as _) } } #[doc = "Read FULL result, without altering any internal state (PEEK)."] #[inline(always)] pub const fn peek_full(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(40usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x28usize) as _) } } #[doc = "Control register for lane 0"] #[inline(always)] - pub const fn ctrl_lane0(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(44usize) as _) } + pub const fn ctrl_lane0(self) -> crate::common::Reg { + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x2cusize) as _) } } #[doc = "Control register for lane 1"] #[inline(always)] - pub const fn ctrl_lane1(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(48usize) as _) } + pub const fn ctrl_lane1(self) -> crate::common::Reg { + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x30usize) as _) } } #[doc = "Values written here are atomically added to ACCUM0 Reading yields lane 0's raw shift and mask value (BASE0 not added)."] #[inline(always)] - pub const fn accum0_add(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(52usize) as _) } + pub const fn accum0_add(self) -> crate::common::Reg { + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x34usize) as _) } } #[doc = "Values written here are atomically added to ACCUM1 Reading yields lane 1's raw shift and mask value (BASE1 not added)."] #[inline(always)] - pub const fn accum1_add(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(56usize) as _) } + pub const fn accum1_add(self) -> crate::common::Reg { + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x38usize) as _) } } #[doc = "On write, the lower 16 bits go to BASE0, upper bits to BASE1 simultaneously. Each half is sign-extended to 32 bits if that lane's SIGNED flag is set."] #[inline(always)] pub const fn base_1and0(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(60usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x3cusize) as _) } } } #[doc = "Single-cycle IO block Provides core-local and inter-core hardware for the two processors, with single-cycle access."] @@ -231,47 +231,47 @@ impl Sio { #[doc = "Processor core identifier"] #[inline(always)] pub const fn cpuid(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(0usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x0usize) as _) } } #[doc = "Input value for GPIO pins"] #[inline(always)] pub const fn gpio_in(self, n: usize) -> crate::common::Reg { assert!(n < 2usize); - unsafe { crate::common::Reg::from_ptr(self.ptr.add(4usize + n * 4usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x04usize + n * 4usize) as _) } } #[inline(always)] pub const fn gpio_out(self, n: usize) -> Gpio { assert!(n < 2usize); - unsafe { Gpio::from_ptr(self.ptr.add(16usize + n * 32usize) as _) } + unsafe { Gpio::from_ptr(self.ptr.add(0x10usize + n * 32usize) as _) } } #[inline(always)] pub const fn gpio_oe(self, n: usize) -> Gpio { assert!(n < 2usize); - unsafe { Gpio::from_ptr(self.ptr.add(32usize + n * 32usize) as _) } + unsafe { Gpio::from_ptr(self.ptr.add(0x20usize + n * 32usize) as _) } } #[inline(always)] pub const fn fifo(self) -> Fifo { - unsafe { Fifo::from_ptr(self.ptr.add(80usize) as _) } + unsafe { Fifo::from_ptr(self.ptr.add(0x50usize) as _) } } #[doc = "Spinlock state A bitmap containing the state of all 32 spinlocks (1=locked). Mainly intended for debugging."] #[inline(always)] pub const fn spinlock_st(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(92usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x5cusize) as _) } } #[inline(always)] pub const fn div(self) -> Div { - unsafe { Div::from_ptr(self.ptr.add(96usize) as _) } + unsafe { Div::from_ptr(self.ptr.add(0x60usize) as _) } } #[inline(always)] pub const fn interp(self, n: usize) -> Interp { assert!(n < 2usize); - unsafe { Interp::from_ptr(self.ptr.add(128usize + n * 64usize) as _) } + unsafe { Interp::from_ptr(self.ptr.add(0x80usize + n * 64usize) as _) } } #[doc = "Reading from a spinlock address will: - Return 0 if lock is already locked - Otherwise return nonzero, and simultaneously claim the lock Writing (any value) releases the lock. If core 0 and core 1 attempt to claim the same lock simultaneously, core 0 wins. The value returned on success is 0x1 << lock number."] #[inline(always)] pub const fn spinlock(self, n: usize) -> crate::common::Reg { assert!(n < 32usize); - unsafe { crate::common::Reg::from_ptr(self.ptr.add(256usize + n * 4usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x0100usize + n * 4usize) as _) } } } pub mod regs; diff --git a/src/rp2040/spi.rs b/src/rp2040/spi.rs index 0a4f215e..68bcf1ef 100644 --- a/src/rp2040/spi.rs +++ b/src/rp2040/spi.rs @@ -16,92 +16,92 @@ impl Spi { #[doc = "Control register 0, SSPCR0 on page 3-4"] #[inline(always)] pub const fn cr0(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(0usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x0usize) as _) } } #[doc = "Control register 1, SSPCR1 on page 3-5"] #[inline(always)] pub const fn cr1(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(4usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x04usize) as _) } } #[doc = "Data register, SSPDR on page 3-6"] #[inline(always)] pub const fn dr(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(8usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x08usize) as _) } } #[doc = "Status register, SSPSR on page 3-7"] #[inline(always)] pub const fn sr(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(12usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x0cusize) as _) } } #[doc = "Clock prescale register, SSPCPSR on page 3-8"] #[inline(always)] pub const fn cpsr(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(16usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x10usize) as _) } } #[doc = "Interrupt mask set or clear register, SSPIMSC on page 3-9"] #[inline(always)] pub const fn imsc(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(20usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x14usize) as _) } } #[doc = "Raw interrupt status register, SSPRIS on page 3-10"] #[inline(always)] pub const fn ris(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(24usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x18usize) as _) } } #[doc = "Masked interrupt status register, SSPMIS on page 3-11"] #[inline(always)] pub const fn mis(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(28usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x1cusize) as _) } } #[doc = "Interrupt clear register, SSPICR on page 3-11"] #[inline(always)] pub const fn icr(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(32usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x20usize) as _) } } #[doc = "DMA control register, SSPDMACR on page 3-12"] #[inline(always)] pub const fn dmacr(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(36usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x24usize) as _) } } #[doc = "Peripheral identification registers, SSPPeriphID0-3 on page 3-13"] #[inline(always)] pub const fn periphid0(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(4064usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x0fe0usize) as _) } } #[doc = "Peripheral identification registers, SSPPeriphID0-3 on page 3-13"] #[inline(always)] pub const fn periphid1(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(4068usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x0fe4usize) as _) } } #[doc = "Peripheral identification registers, SSPPeriphID0-3 on page 3-13"] #[inline(always)] pub const fn periphid2(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(4072usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x0fe8usize) as _) } } #[doc = "Peripheral identification registers, SSPPeriphID0-3 on page 3-13"] #[inline(always)] pub const fn periphid3(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(4076usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x0fecusize) as _) } } #[doc = "PrimeCell identification registers, SSPPCellID0-3 on page 3-16"] #[inline(always)] pub const fn pcellid0(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(4080usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x0ff0usize) as _) } } #[doc = "PrimeCell identification registers, SSPPCellID0-3 on page 3-16"] #[inline(always)] pub const fn pcellid1(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(4084usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x0ff4usize) as _) } } #[doc = "PrimeCell identification registers, SSPPCellID0-3 on page 3-16"] #[inline(always)] pub const fn pcellid2(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(4088usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x0ff8usize) as _) } } #[doc = "PrimeCell identification registers, SSPPCellID0-3 on page 3-16"] #[inline(always)] pub const fn pcellid3(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(4092usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x0ffcusize) as _) } } } pub mod regs; diff --git a/src/rp2040/ssi.rs b/src/rp2040/ssi.rs index f921539f..d163f98f 100644 --- a/src/rp2040/ssi.rs +++ b/src/rp2040/ssi.rs @@ -17,142 +17,142 @@ impl Ssi { #[doc = "Control register 0"] #[inline(always)] pub const fn ctrlr0(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(0usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x0usize) as _) } } #[doc = "Master Control register 1"] #[inline(always)] pub const fn ctrlr1(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(4usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x04usize) as _) } } #[doc = "SSI Enable"] #[inline(always)] pub const fn ssienr(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(8usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x08usize) as _) } } #[doc = "Microwire Control"] #[inline(always)] pub const fn mwcr(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(12usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x0cusize) as _) } } #[doc = "Slave enable"] #[inline(always)] pub const fn ser(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(16usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x10usize) as _) } } #[doc = "Baud rate"] #[inline(always)] pub const fn baudr(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(20usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x14usize) as _) } } #[doc = "TX FIFO threshold level"] #[inline(always)] pub const fn txftlr(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(24usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x18usize) as _) } } #[doc = "RX FIFO threshold level"] #[inline(always)] pub const fn rxftlr(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(28usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x1cusize) as _) } } #[doc = "TX FIFO level"] #[inline(always)] pub const fn txflr(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(32usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x20usize) as _) } } #[doc = "RX FIFO level"] #[inline(always)] pub const fn rxflr(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(36usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x24usize) as _) } } #[doc = "Status register"] #[inline(always)] pub const fn sr(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(40usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x28usize) as _) } } #[doc = "Interrupt mask"] #[inline(always)] pub const fn imr(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(44usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x2cusize) as _) } } #[doc = "Interrupt status"] #[inline(always)] pub const fn isr(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(48usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x30usize) as _) } } #[doc = "Raw interrupt status"] #[inline(always)] pub const fn risr(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(52usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x34usize) as _) } } #[doc = "TX FIFO overflow interrupt clear"] #[inline(always)] pub const fn txoicr(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(56usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x38usize) as _) } } #[doc = "RX FIFO overflow interrupt clear"] #[inline(always)] pub const fn rxoicr(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(60usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x3cusize) as _) } } #[doc = "RX FIFO underflow interrupt clear"] #[inline(always)] pub const fn rxuicr(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(64usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x40usize) as _) } } #[doc = "Multi-master interrupt clear"] #[inline(always)] pub const fn msticr(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(68usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x44usize) as _) } } #[doc = "Interrupt clear"] #[inline(always)] pub const fn icr(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(72usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x48usize) as _) } } #[doc = "DMA control"] #[inline(always)] pub const fn dmacr(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(76usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x4cusize) as _) } } #[doc = "DMA TX data level"] #[inline(always)] pub const fn dmatdlr(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(80usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x50usize) as _) } } #[doc = "DMA RX data level"] #[inline(always)] pub const fn dmardlr(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(84usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x54usize) as _) } } #[doc = "Identification register"] #[inline(always)] pub const fn idr(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(88usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x58usize) as _) } } #[doc = "Version ID"] #[inline(always)] pub const fn ssi_version_id(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(92usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x5cusize) as _) } } #[doc = "Data Register 0 (of 36)"] #[inline(always)] pub const fn dr0(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(96usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x60usize) as _) } } #[doc = "RX sample delay"] #[inline(always)] pub const fn rx_sample_dly(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(240usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0xf0usize) as _) } } #[doc = "SPI control"] #[inline(always)] pub const fn spi_ctrlr0(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(244usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0xf4usize) as _) } } #[doc = "TX drive edge"] #[inline(always)] pub const fn txd_drive_edge(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(248usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0xf8usize) as _) } } } pub mod regs; diff --git a/src/rp2040/ssi/vals.rs b/src/rp2040/ssi/vals.rs index 27d0365b..16f880c4 100644 --- a/src/rp2040/ssi/vals.rs +++ b/src/rp2040/ssi/vals.rs @@ -2,7 +2,7 @@ #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] pub enum InstL { #[doc = "No instruction"] - NONE = 0, + NONE = 0x0, #[doc = "4-bit instruction"] _4B = 0x01, #[doc = "8-bit instruction"] @@ -36,7 +36,7 @@ impl From for u8 { #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] pub enum SpiFrf { #[doc = "Standard 1-bit SPI frame format; 1 bit per SCK, full-duplex"] - STD = 0, + STD = 0x0, #[doc = "Dual-SPI frame format; two bits per SCK, half-duplex"] DUAL = 0x01, #[doc = "Quad-SPI frame format; four bits per SCK, half-duplex"] @@ -69,7 +69,7 @@ impl From for u8 { #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] pub enum Tmod { #[doc = "Both transmit and receive"] - TX_AND_RX = 0, + TX_AND_RX = 0x0, #[doc = "Transmit only (not for FRF == 0, standard SPI mode)"] TX_ONLY = 0x01, #[doc = "Receive only (not for FRF == 0, standard SPI mode)"] @@ -103,7 +103,7 @@ impl From for u8 { #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] pub enum TransType { #[doc = "Command and address both in standard SPI frame format"] - _1C1A = 0, + _1C1A = 0x0, #[doc = "Command in standard SPI format, address in format specified by FRF"] _1C2A = 0x01, #[doc = "Command and address both in format specified by FRF (e.g. Dual-SPI)"] diff --git a/src/rp2040/syscfg.rs b/src/rp2040/syscfg.rs index 951a62e8..935c0d7e 100644 --- a/src/rp2040/syscfg.rs +++ b/src/rp2040/syscfg.rs @@ -17,41 +17,41 @@ impl Syscfg { #[doc = "Processor core 0 NMI source mask"] #[inline(always)] pub const fn proc0_nmi_mask(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(0usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x0usize) as _) } } #[doc = "Processor core 1 NMI source mask"] #[inline(always)] pub const fn proc1_nmi_mask(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(4usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x04usize) as _) } } #[doc = "Configuration for processors"] #[inline(always)] pub const fn proc_config(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(8usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x08usize) as _) } } #[doc = "For each bit, if 1, bypass the input synchronizer between that GPIO and the GPIO input register in the SIO. The input synchronizers should generally be unbypassed, to avoid injecting metastabilities into processors. If you're feeling brave, you can bypass to save two cycles of input latency. This register applies to GPIO 0...29."] #[inline(always)] pub const fn proc_in_sync_bypass( self, ) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(12usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x0cusize) as _) } } #[doc = "For each bit, if 1, bypass the input synchronizer between that GPIO and the GPIO input register in the SIO. The input synchronizers should generally be unbypassed, to avoid injecting metastabilities into processors. If you're feeling brave, you can bypass to save two cycles of input latency. This register applies to GPIO 30...35 (the QSPI IOs)."] #[inline(always)] pub const fn proc_in_sync_bypass_hi( self, ) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(16usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x10usize) as _) } } #[doc = "Directly control the SWD debug port of either processor"] #[inline(always)] pub const fn dbgforce(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(20usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x14usize) as _) } } #[doc = "Control power downs to memories. Set high to power down memories. Use with extreme caution"] #[inline(always)] pub const fn mempowerdown(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(24usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x18usize) as _) } } } pub mod regs; diff --git a/src/rp2040/sysinfo.rs b/src/rp2040/sysinfo.rs index 23a44473..3fd096a3 100644 --- a/src/rp2040/sysinfo.rs +++ b/src/rp2040/sysinfo.rs @@ -16,17 +16,17 @@ impl Sysinfo { #[doc = "JEDEC JEP-106 compliant chip identifier."] #[inline(always)] pub const fn chip_id(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(0usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x0usize) as _) } } #[doc = "Platform register. Allows software to know what environment it is running in."] #[inline(always)] pub const fn platform(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(4usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x04usize) as _) } } #[doc = "Git hash of the chip source. Used to identify chip version."] #[inline(always)] pub const fn gitref_rp2040(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(16usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x10usize) as _) } } } pub mod regs; diff --git a/src/rp2040/tbman.rs b/src/rp2040/tbman.rs index eeba4c24..3ad25729 100644 --- a/src/rp2040/tbman.rs +++ b/src/rp2040/tbman.rs @@ -17,7 +17,7 @@ impl Tbman { #[doc = "Indicates the type of platform in use"] #[inline(always)] pub const fn platform(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(0usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x0usize) as _) } } } pub mod regs; diff --git a/src/rp2040/timer.rs b/src/rp2040/timer.rs index 97645e5a..d9d8cfb6 100644 --- a/src/rp2040/timer.rs +++ b/src/rp2040/timer.rs @@ -17,73 +17,73 @@ impl Timer { #[doc = "Write to bits 63:32 of time always write timelw before timehw"] #[inline(always)] pub const fn timehw(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(0usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x0usize) as _) } } #[doc = "Write to bits 31:0 of time writes do not get copied to time until timehw is written"] #[inline(always)] pub const fn timelw(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(4usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x04usize) as _) } } #[doc = "Read from bits 63:32 of time always read timelr before timehr"] #[inline(always)] pub const fn timehr(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(8usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x08usize) as _) } } #[doc = "Read from bits 31:0 of time"] #[inline(always)] pub const fn timelr(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(12usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x0cusize) as _) } } #[doc = "Arm alarm 0, and configure the time it will fire. Once armed, the alarm fires when TIMER_ALARM0 == TIMELR. The alarm will disarm itself once it fires, and can be disarmed early using the ARMED status register."] #[inline(always)] pub const fn alarm(self, n: usize) -> crate::common::Reg { assert!(n < 4usize); - unsafe { crate::common::Reg::from_ptr(self.ptr.add(16usize + n * 4usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x10usize + n * 4usize) as _) } } #[doc = "Indicates the armed/disarmed status of each alarm. A write to the corresponding ALARMx register arms the alarm. Alarms automatically disarm upon firing, but writing ones here will disarm immediately without waiting to fire."] #[inline(always)] pub const fn armed(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(32usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x20usize) as _) } } #[doc = "Raw read from bits 63:32 of time (no side effects)"] #[inline(always)] pub const fn timerawh(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(36usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x24usize) as _) } } #[doc = "Raw read from bits 31:0 of time (no side effects)"] #[inline(always)] pub const fn timerawl(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(40usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x28usize) as _) } } #[doc = "Set bits high to enable pause when the corresponding debug ports are active"] #[inline(always)] pub const fn dbgpause(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(44usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x2cusize) as _) } } #[doc = "Set high to pause the timer"] #[inline(always)] pub const fn pause(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(48usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x30usize) as _) } } #[doc = "Raw Interrupts"] #[inline(always)] pub const fn intr(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(52usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x34usize) as _) } } #[doc = "Interrupt Enable"] #[inline(always)] pub const fn inte(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(56usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x38usize) as _) } } #[doc = "Interrupt Force"] #[inline(always)] pub const fn intf(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(60usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x3cusize) as _) } } #[doc = "Interrupt status after masking & forcing"] #[inline(always)] pub const fn ints(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(64usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x40usize) as _) } } } pub mod regs; diff --git a/src/rp2040/uart.rs b/src/rp2040/uart.rs index 078cce38..d64805b0 100644 --- a/src/rp2040/uart.rs +++ b/src/rp2040/uart.rs @@ -16,112 +16,112 @@ impl Uart { #[doc = "Data Register, UARTDR"] #[inline(always)] pub const fn uartdr(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(0usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x0usize) as _) } } #[doc = "Receive Status Register/Error Clear Register, UARTRSR/UARTECR"] #[inline(always)] pub const fn uartrsr(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(4usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x04usize) as _) } } #[doc = "Flag Register, UARTFR"] #[inline(always)] pub const fn uartfr(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(24usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x18usize) as _) } } #[doc = "IrDA Low-Power Counter Register, UARTILPR"] #[inline(always)] pub const fn uartilpr(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(32usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x20usize) as _) } } #[doc = "Integer Baud Rate Register, UARTIBRD"] #[inline(always)] pub const fn uartibrd(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(36usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x24usize) as _) } } #[doc = "Fractional Baud Rate Register, UARTFBRD"] #[inline(always)] pub const fn uartfbrd(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(40usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x28usize) as _) } } #[doc = "Line Control Register, UARTLCR_H"] #[inline(always)] pub const fn uartlcr_h(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(44usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x2cusize) as _) } } #[doc = "Control Register, UARTCR"] #[inline(always)] pub const fn uartcr(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(48usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x30usize) as _) } } #[doc = "Interrupt FIFO Level Select Register, UARTIFLS"] #[inline(always)] pub const fn uartifls(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(52usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x34usize) as _) } } #[doc = "Interrupt Mask Set/Clear Register, UARTIMSC"] #[inline(always)] pub const fn uartimsc(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(56usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x38usize) as _) } } #[doc = "Raw Interrupt Status Register, UARTRIS"] #[inline(always)] pub const fn uartris(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(60usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x3cusize) as _) } } #[doc = "Masked Interrupt Status Register, UARTMIS"] #[inline(always)] pub const fn uartmis(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(64usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x40usize) as _) } } #[doc = "Interrupt Clear Register, UARTICR"] #[inline(always)] pub const fn uarticr(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(68usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x44usize) as _) } } #[doc = "DMA Control Register, UARTDMACR"] #[inline(always)] pub const fn uartdmacr(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(72usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x48usize) as _) } } #[doc = "UARTPeriphID0 Register"] #[inline(always)] pub const fn uartperiphid0(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(4064usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x0fe0usize) as _) } } #[doc = "UARTPeriphID1 Register"] #[inline(always)] pub const fn uartperiphid1(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(4068usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x0fe4usize) as _) } } #[doc = "UARTPeriphID2 Register"] #[inline(always)] pub const fn uartperiphid2(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(4072usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x0fe8usize) as _) } } #[doc = "UARTPeriphID3 Register"] #[inline(always)] pub const fn uartperiphid3(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(4076usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x0fecusize) as _) } } #[doc = "UARTPCellID0 Register"] #[inline(always)] pub const fn uartpcellid0(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(4080usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x0ff0usize) as _) } } #[doc = "UARTPCellID1 Register"] #[inline(always)] pub const fn uartpcellid1(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(4084usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x0ff4usize) as _) } } #[doc = "UARTPCellID2 Register"] #[inline(always)] pub const fn uartpcellid2(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(4088usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x0ff8usize) as _) } } #[doc = "UARTPCellID3 Register"] #[inline(always)] pub const fn uartpcellid3(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(4092usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x0ffcusize) as _) } } } pub mod regs; diff --git a/src/rp2040/usb.rs b/src/rp2040/usb.rs index 1664ac6d..c707753e 100644 --- a/src/rp2040/usb.rs +++ b/src/rp2040/usb.rs @@ -17,7 +17,7 @@ impl Usb { #[doc = "Device address and endpoint control"] #[inline(always)] pub const fn addr_endp(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(0usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x0usize) as _) } } #[doc = "Interrupt endpoint 1. Only valid for HOST mode."] #[inline(always)] @@ -26,122 +26,122 @@ impl Usb { n: usize, ) -> crate::common::Reg { assert!(n < 15usize); - unsafe { crate::common::Reg::from_ptr(self.ptr.add(4usize + n * 4usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x04usize + n * 4usize) as _) } } #[doc = "Main control register"] #[inline(always)] pub const fn main_ctrl(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(64usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x40usize) as _) } } #[doc = "Set the SOF (Start of Frame) frame number in the host controller. The SOF packet is sent every 1ms and the host will increment the frame number by 1 each time."] #[inline(always)] pub const fn sof_wr(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(68usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x44usize) as _) } } #[doc = "Read the last SOF (Start of Frame) frame number seen. In device mode the last SOF received from the host. In host mode the last SOF sent by the host."] #[inline(always)] pub const fn sof_rd(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(72usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x48usize) as _) } } #[doc = "SIE control register"] #[inline(always)] pub const fn sie_ctrl(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(76usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x4cusize) as _) } } #[doc = "SIE status register"] #[inline(always)] pub const fn sie_status(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(80usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x50usize) as _) } } #[doc = "interrupt endpoint control register"] #[inline(always)] pub const fn int_ep_ctrl(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(84usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x54usize) as _) } } #[doc = "Buffer status register. A bit set here indicates that a buffer has completed on the endpoint (if the buffer interrupt is enabled). It is possible for 2 buffers to be completed, so clearing the buffer status bit may instantly re set it on the next clock cycle."] #[inline(always)] pub const fn buff_status(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(88usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x58usize) as _) } } #[doc = "Which of the double buffers should be handled. Only valid if using an interrupt per buffer (i.e. not per 2 buffers). Not valid for host interrupt endpoint polling because they are only single buffered."] #[inline(always)] pub const fn buff_cpu_should_handle( self, ) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(92usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x5cusize) as _) } } #[doc = "Device only: Can be set to ignore the buffer control register for this endpoint in case you would like to revoke a buffer. A NAK will be sent for every access to the endpoint until this bit is cleared. A corresponding bit in `EP_ABORT_DONE` is set when it is safe to modify the buffer control register."] #[inline(always)] pub const fn ep_abort(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(96usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x60usize) as _) } } #[doc = "Device only: Used in conjunction with `EP_ABORT`. Set once an endpoint is idle so the programmer knows it is safe to modify the buffer control register."] #[inline(always)] pub const fn ep_abort_done(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(100usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x64usize) as _) } } #[doc = "Device: this bit must be set in conjunction with the `STALL` bit in the buffer control register to send a STALL on EP0. The device controller clears these bits when a SETUP packet is received because the USB spec requires that a STALL condition is cleared when a SETUP packet is received."] #[inline(always)] pub const fn ep_stall_arm(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(104usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x68usize) as _) } } #[doc = "Used by the host controller. Sets the wait time in microseconds before trying again if the device replies with a NAK."] #[inline(always)] pub const fn nak_poll(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(108usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x6cusize) as _) } } #[doc = "Device: bits are set when the `IRQ_ON_NAK` or `IRQ_ON_STALL` bits are set. For EP0 this comes from `SIE_CTRL`. For all other endpoints it comes from the endpoint control register."] #[inline(always)] pub const fn ep_status_stall_nak( self, ) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(112usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x70usize) as _) } } #[doc = "Where to connect the USB controller. Should be to_phy by default."] #[inline(always)] pub const fn usb_muxing(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(116usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x74usize) as _) } } #[doc = "Overrides for the power signals in the event that the VBUS signals are not hooked up to GPIO. Set the value of the override and then the override enable so switch over to the override value."] #[inline(always)] pub const fn usb_pwr(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(120usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x78usize) as _) } } #[doc = "Note that most functions are driven directly from usb_fsls controller. This register allows more detailed control/status from the USB PHY. Useful for debug but not expected to be used in normal operation Use in conjunction with usbphy_direct_override register"] #[inline(always)] pub const fn usbphy_direct(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(124usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x7cusize) as _) } } #[inline(always)] pub const fn usbphy_direct_override( self, ) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(128usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x80usize) as _) } } #[doc = "Note that most functions are driven directly from usb_fsls controller. This register allows more detailed control/status from the USB PHY. Useful for debug but not expected to be used in normal operation"] #[inline(always)] pub const fn usbphy_trim(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(132usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x84usize) as _) } } #[doc = "Raw Interrupts"] #[inline(always)] pub const fn intr(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(140usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x8cusize) as _) } } #[doc = "Interrupt Enable"] #[inline(always)] pub const fn inte(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(144usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x90usize) as _) } } #[doc = "Interrupt Force"] #[inline(always)] pub const fn intf(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(148usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x94usize) as _) } } #[doc = "Interrupt status after masking & forcing"] #[inline(always)] pub const fn ints(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(152usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x98usize) as _) } } } pub mod regs; diff --git a/src/rp2040/usb/regs.rs b/src/rp2040/usb/regs.rs index d8bc87f1..8a6ae214 100644 --- a/src/rp2040/usb/regs.rs +++ b/src/rp2040/usb/regs.rs @@ -32,7 +32,7 @@ impl Default for AddrEndp { AddrEndp(0) } } -#[doc = "Interrupt endpoint 1. Only valid for HOST mode."] +#[doc = "Interrupt endpoint 13. Only valid for HOST mode."] #[repr(transparent)] #[derive(Copy, Clone, Eq, PartialEq)] pub struct AddrEndpX(pub u32); @@ -308,7 +308,7 @@ impl Default for EpStatusStallNak { EpStatusStallNak(0) } } -#[doc = "Interrupt Enable"] +#[doc = "Interrupt Force"] #[repr(transparent)] #[derive(Copy, Clone, Eq, PartialEq)] pub struct Int(pub u32); diff --git a/src/rp2040/usb_dpram.rs b/src/rp2040/usb_dpram.rs index ec3eec2a..ca45a368 100644 --- a/src/rp2040/usb_dpram.rs +++ b/src/rp2040/usb_dpram.rs @@ -19,14 +19,14 @@ impl UsbDpram { pub const fn setup_packet_low( self, ) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(0usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x0usize) as _) } } #[doc = "Bytes 4-7 of the setup packet from the host."] #[inline(always)] pub const fn setup_packet_high( self, ) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(4usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x04usize) as _) } } #[inline(always)] pub const fn ep_in_control( @@ -34,7 +34,7 @@ impl UsbDpram { n: usize, ) -> crate::common::Reg { assert!(n < 15usize); - unsafe { crate::common::Reg::from_ptr(self.ptr.add(8usize + n * 8usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x08usize + n * 8usize) as _) } } #[inline(always)] pub const fn ep_out_control( @@ -42,7 +42,7 @@ impl UsbDpram { n: usize, ) -> crate::common::Reg { assert!(n < 15usize); - unsafe { crate::common::Reg::from_ptr(self.ptr.add(12usize + n * 8usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x0cusize + n * 8usize) as _) } } #[doc = "Buffer control for both buffers of an endpoint. Fields ending in a _1 are for buffer 1. Fields ending in a _0 are for buffer 0. Buffer 1 controls are only valid if the endpoint is in double buffered mode."] #[inline(always)] @@ -51,7 +51,7 @@ impl UsbDpram { n: usize, ) -> crate::common::Reg { assert!(n < 16usize); - unsafe { crate::common::Reg::from_ptr(self.ptr.add(128usize + n * 8usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x80usize + n * 8usize) as _) } } #[doc = "Buffer control for both buffers of an endpoint. Fields ending in a _1 are for buffer 1. Fields ending in a _0 are for buffer 0. Buffer 1 controls are only valid if the endpoint is in double buffered mode."] #[inline(always)] @@ -60,7 +60,7 @@ impl UsbDpram { n: usize, ) -> crate::common::Reg { assert!(n < 16usize); - unsafe { crate::common::Reg::from_ptr(self.ptr.add(132usize + n * 8usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x84usize + n * 8usize) as _) } } } pub mod regs; diff --git a/src/rp2040/usb_dpram/vals.rs b/src/rp2040/usb_dpram/vals.rs index d0e39228..c1e350b1 100644 --- a/src/rp2040/usb_dpram/vals.rs +++ b/src/rp2040/usb_dpram/vals.rs @@ -1,7 +1,7 @@ #[repr(u8)] #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] pub enum EpBufferControlDoubleBufferIsoOffset { - _128 = 0, + _128 = 0x0, _256 = 0x01, _512 = 0x02, _1024 = 0x03, @@ -31,7 +31,7 @@ impl From for u8 { #[repr(u8)] #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] pub enum EpControlEndpointType { - CONTROL = 0, + CONTROL = 0x0, ISOCHRONOUS = 0x01, BULK = 0x02, INTERRUPT = 0x03, diff --git a/src/rp2040/vreg_and_chip_reset.rs b/src/rp2040/vreg_and_chip_reset.rs index c9d9d30f..5131d693 100644 --- a/src/rp2040/vreg_and_chip_reset.rs +++ b/src/rp2040/vreg_and_chip_reset.rs @@ -17,17 +17,17 @@ impl VregAndChipReset { #[doc = "Voltage regulator control and status"] #[inline(always)] pub const fn vreg(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(0usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x0usize) as _) } } #[doc = "brown-out detection control"] #[inline(always)] pub const fn bod(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(4usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x04usize) as _) } } #[doc = "Chip reset control and status"] #[inline(always)] pub const fn chip_reset(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(8usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x08usize) as _) } } } pub mod regs; diff --git a/src/rp2040/watchdog.rs b/src/rp2040/watchdog.rs index 2f460235..f4439155 100644 --- a/src/rp2040/watchdog.rs +++ b/src/rp2040/watchdog.rs @@ -16,62 +16,62 @@ impl Watchdog { #[doc = "Watchdog control The rst_wdsel register determines which subsystems are reset when the watchdog is triggered. The watchdog can be triggered in software."] #[inline(always)] pub const fn ctrl(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(0usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x0usize) as _) } } #[doc = "Load the watchdog timer. The maximum setting is 0xffffff which corresponds to 0xffffff / 2 ticks before triggering a watchdog reset (see errata RP2040-E1)."] #[inline(always)] pub const fn load(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(4usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x04usize) as _) } } #[doc = "Logs the reason for the last reset. Both bits are zero for the case of a hardware reset."] #[inline(always)] pub const fn reason(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(8usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x08usize) as _) } } #[doc = "Scratch register. Information persists through soft reset of the chip."] #[inline(always)] pub const fn scratch0(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(12usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x0cusize) as _) } } #[doc = "Scratch register. Information persists through soft reset of the chip."] #[inline(always)] pub const fn scratch1(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(16usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x10usize) as _) } } #[doc = "Scratch register. Information persists through soft reset of the chip."] #[inline(always)] pub const fn scratch2(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(20usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x14usize) as _) } } #[doc = "Scratch register. Information persists through soft reset of the chip."] #[inline(always)] pub const fn scratch3(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(24usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x18usize) as _) } } #[doc = "Scratch register. Information persists through soft reset of the chip."] #[inline(always)] pub const fn scratch4(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(28usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x1cusize) as _) } } #[doc = "Scratch register. Information persists through soft reset of the chip."] #[inline(always)] pub const fn scratch5(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(32usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x20usize) as _) } } #[doc = "Scratch register. Information persists through soft reset of the chip."] #[inline(always)] pub const fn scratch6(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(36usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x24usize) as _) } } #[doc = "Scratch register. Information persists through soft reset of the chip."] #[inline(always)] pub const fn scratch7(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(40usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x28usize) as _) } } #[doc = "Controls the tick generator"] #[inline(always)] pub const fn tick(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(44usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x2cusize) as _) } } } pub mod regs; diff --git a/src/rp2040/xip_ctrl.rs b/src/rp2040/xip_ctrl.rs index a1841a4e..c6ec99f3 100644 --- a/src/rp2040/xip_ctrl.rs +++ b/src/rp2040/xip_ctrl.rs @@ -17,42 +17,42 @@ impl XipCtrl { #[doc = "Cache control"] #[inline(always)] pub const fn ctrl(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(0usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x0usize) as _) } } #[doc = "Cache Flush control"] #[inline(always)] pub const fn flush(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(4usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x04usize) as _) } } #[doc = "Cache Status"] #[inline(always)] pub const fn stat(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(8usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x08usize) as _) } } #[doc = "Cache Hit counter"] #[inline(always)] pub const fn ctr_hit(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(12usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x0cusize) as _) } } #[doc = "Cache Access counter"] #[inline(always)] pub const fn ctr_acc(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(16usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x10usize) as _) } } #[doc = "FIFO stream address"] #[inline(always)] pub const fn stream_addr(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(20usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x14usize) as _) } } #[doc = "FIFO stream control"] #[inline(always)] pub const fn stream_ctr(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(24usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x18usize) as _) } } #[doc = "FIFO stream data"] #[inline(always)] pub const fn stream_fifo(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(28usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x1cusize) as _) } } } pub mod regs; diff --git a/src/rp2040/xosc.rs b/src/rp2040/xosc.rs index 3f7af636..3aaa4bcc 100644 --- a/src/rp2040/xosc.rs +++ b/src/rp2040/xosc.rs @@ -17,27 +17,27 @@ impl Xosc { #[doc = "Crystal Oscillator Control"] #[inline(always)] pub const fn ctrl(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(0usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x0usize) as _) } } #[doc = "Crystal Oscillator Status"] #[inline(always)] pub const fn status(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(4usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x04usize) as _) } } #[doc = "Crystal Oscillator pause control"] #[inline(always)] pub const fn dormant(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(8usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x08usize) as _) } } #[doc = "Controls the startup delay"] #[inline(always)] pub const fn startup(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(12usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x0cusize) as _) } } #[doc = "A down counter running at the xosc frequency which counts to zero and stops. To start the counter write a non-zero value. Can be used for short software pauses when setting up time sensitive hardware."] #[inline(always)] pub const fn count(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(28usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x1cusize) as _) } } } pub mod regs; diff --git a/src/rp2040/xosc/vals.rs b/src/rp2040/xosc/vals.rs index 237095e3..21352ef7 100644 --- a/src/rp2040/xosc/vals.rs +++ b/src/rp2040/xosc/vals.rs @@ -84,7 +84,7 @@ impl From for u16 { #[repr(u8)] #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] pub enum StatusFreqRange { - _1_15MHZ = 0, + _1_15MHZ = 0x0, RESERVED_1 = 0x01, RESERVED_2 = 0x02, RESERVED_3 = 0x03, diff --git a/src/rp235x/accessctrl.rs b/src/rp235x/accessctrl.rs index 1a1861b1..af9b5fb4 100644 --- a/src/rp235x/accessctrl.rs +++ b/src/rp235x/accessctrl.rs @@ -17,301 +17,253 @@ impl Accessctrl { #[doc = "Once a LOCK bit is written to 1, ACCESSCTRL silently ignores writes from that master. LOCK is writable only by a Secure, Privileged processor or debugger. LOCK bits are only writable when their value is zero. Once set, they can never be cleared, except by a full reset of ACCESSCTRL Setting the LOCK bit does not affect whether an access raises a bus error. Unprivileged writes, or writes from the DMA, will continue to raise bus errors. All other accesses will continue not to."] #[inline(always)] pub const fn lock(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(0usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x0usize) as _) } } #[doc = "Force core 1's bus accesses to always be Non-secure, no matter the core's internal state. Useful for schemes where one core is designated as the Non-secure core, since some peripherals may filter individual registers internally based on security state but not on master ID."] #[inline(always)] pub const fn force_core_ns(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(4usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x04usize) as _) } } #[doc = "Write 1 to reset all ACCESSCTRL configuration, except for the LOCK and FORCE_CORE_NS registers. This bit is used in the RP2350 bootrom to quickly restore ACCESSCTRL to a known state during the boot path. Note that, like all registers in ACCESSCTRL, this register is not writable when the writer's corresponding LOCK bit is set, therefore a master which has been locked out of ACCESSCTRL can not use the CFGRESET register to disturb its contents."] #[inline(always)] pub const fn cfgreset(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(8usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x08usize) as _) } } #[doc = "Control whether GPIO0...31 are accessible to Non-secure code. Writable only by a Secure, Privileged processor or debugger. 0 -> Secure access only 1 -> Secure + Non-secure access"] #[inline(always)] pub const fn gpio_nsmask0(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(12usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x0cusize) as _) } } #[doc = "Control whether GPIO32..47 are accessible to Non-secure code, and whether QSPI and USB bitbang are accessible through the Non-secure SIO. Writable only by a Secure, Privileged processor or debugger."] #[inline(always)] pub const fn gpio_nsmask1(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(16usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x10usize) as _) } } #[doc = "Control whether debugger, DMA, core 0 and core 1 can access ROM, and at what security/privilege levels they can do so. Defaults to fully open access. This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set."] #[inline(always)] - pub const fn rom(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(20usize) as _) } + pub const fn rom(self) -> crate::common::Reg { + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x14usize) as _) } } #[doc = "Control whether debugger, DMA, core 0 and core 1 can access XIP_MAIN, and at what security/privilege levels they can do so. Defaults to fully open access. This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set."] #[inline(always)] - pub const fn xip_main(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(24usize) as _) } + pub const fn xip_main(self) -> crate::common::Reg { + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x18usize) as _) } } #[doc = "Control whether debugger, DMA, core 0 and core 1 can access SRAM0, and at what security/privilege levels they can do so. Defaults to fully open access. This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set."] #[inline(always)] - pub const fn sram0(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(28usize) as _) } - } - #[doc = "Control whether debugger, DMA, core 0 and core 1 can access SRAM1, and at what security/privilege levels they can do so. Defaults to fully open access. This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set."] - #[inline(always)] - pub const fn sram1(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(32usize) as _) } - } - #[doc = "Control whether debugger, DMA, core 0 and core 1 can access SRAM2, and at what security/privilege levels they can do so. Defaults to fully open access. This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set."] - #[inline(always)] - pub const fn sram2(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(36usize) as _) } - } - #[doc = "Control whether debugger, DMA, core 0 and core 1 can access SRAM3, and at what security/privilege levels they can do so. Defaults to fully open access. This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set."] - #[inline(always)] - pub const fn sram3(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(40usize) as _) } - } - #[doc = "Control whether debugger, DMA, core 0 and core 1 can access SRAM4, and at what security/privilege levels they can do so. Defaults to fully open access. This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set."] - #[inline(always)] - pub const fn sram4(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(44usize) as _) } - } - #[doc = "Control whether debugger, DMA, core 0 and core 1 can access SRAM5, and at what security/privilege levels they can do so. Defaults to fully open access. This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set."] - #[inline(always)] - pub const fn sram5(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(48usize) as _) } - } - #[doc = "Control whether debugger, DMA, core 0 and core 1 can access SRAM6, and at what security/privilege levels they can do so. Defaults to fully open access. This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set."] - #[inline(always)] - pub const fn sram6(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(52usize) as _) } - } - #[doc = "Control whether debugger, DMA, core 0 and core 1 can access SRAM7, and at what security/privilege levels they can do so. Defaults to fully open access. This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set."] - #[inline(always)] - pub const fn sram7(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(56usize) as _) } - } - #[doc = "Control whether debugger, DMA, core 0 and core 1 can access SRAM8, and at what security/privilege levels they can do so. Defaults to fully open access. This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set."] - #[inline(always)] - pub const fn sram8(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(60usize) as _) } - } - #[doc = "Control whether debugger, DMA, core 0 and core 1 can access SRAM9, and at what security/privilege levels they can do so. Defaults to fully open access. This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set."] - #[inline(always)] - pub const fn sram9(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(64usize) as _) } + pub const fn sram(self, n: usize) -> crate::common::Reg { + assert!(n < 10usize); + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x1cusize + n * 4usize) as _) } } #[doc = "Control whether debugger, DMA, core 0 and core 1 can access DMA, and at what security/privilege levels they can do so. Defaults to Secure access from any master. This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set."] #[inline(always)] - pub const fn dma(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(68usize) as _) } + pub const fn dma(self) -> crate::common::Reg { + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x44usize) as _) } } #[doc = "Control whether debugger, DMA, core 0 and core 1 can access USBCTRL, and at what security/privilege levels they can do so. Defaults to Secure access from any master. This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set."] #[inline(always)] - pub const fn usbctrl(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(72usize) as _) } + pub const fn usbctrl(self) -> crate::common::Reg { + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x48usize) as _) } } #[doc = "Control whether debugger, DMA, core 0 and core 1 can access PIO0, and at what security/privilege levels they can do so. Defaults to Secure access from any master. This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set."] #[inline(always)] - pub const fn pio0(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(76usize) as _) } + pub const fn pio0(self) -> crate::common::Reg { + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x4cusize) as _) } } #[doc = "Control whether debugger, DMA, core 0 and core 1 can access PIO1, and at what security/privilege levels they can do so. Defaults to Secure access from any master. This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set."] #[inline(always)] - pub const fn pio1(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(80usize) as _) } + pub const fn pio1(self) -> crate::common::Reg { + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x50usize) as _) } } #[doc = "Control whether debugger, DMA, core 0 and core 1 can access PIO2, and at what security/privilege levels they can do so. Defaults to Secure access from any master. This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set."] #[inline(always)] - pub const fn pio2(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(84usize) as _) } + pub const fn pio2(self) -> crate::common::Reg { + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x54usize) as _) } } #[doc = "Control whether debugger, DMA, core 0 and core 1 can access CORESIGHT_TRACE, and at what security/privilege levels they can do so. Defaults to Secure, Privileged processor or debug access only. This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set."] #[inline(always)] - pub const fn coresight_trace( - self, - ) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(88usize) as _) } + pub const fn coresight_trace(self) -> crate::common::Reg { + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x58usize) as _) } } #[doc = "Control whether debugger, DMA, core 0 and core 1 can access CORESIGHT_PERIPH, and at what security/privilege levels they can do so. Defaults to Secure, Privileged processor or debug access only. This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set."] #[inline(always)] - pub const fn coresight_periph( - self, - ) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(92usize) as _) } + pub const fn coresight_periph(self) -> crate::common::Reg { + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x5cusize) as _) } } #[doc = "Control whether debugger, DMA, core 0 and core 1 can access SYSINFO, and at what security/privilege levels they can do so. Defaults to fully open access. This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set."] #[inline(always)] - pub const fn sysinfo(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(96usize) as _) } + pub const fn sysinfo(self) -> crate::common::Reg { + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x60usize) as _) } } #[doc = "Control whether debugger, DMA, core 0 and core 1 can access RESETS, and at what security/privilege levels they can do so. Defaults to Secure access from any master. This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set."] #[inline(always)] - pub const fn resets(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(100usize) as _) } + pub const fn resets(self) -> crate::common::Reg { + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x64usize) as _) } } #[doc = "Control whether debugger, DMA, core 0 and core 1 can access IO_BANK0, and at what security/privilege levels they can do so. Defaults to Secure access from any master. This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set."] #[inline(always)] - pub const fn io_bank0(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(104usize) as _) } + pub const fn io_bank0(self) -> crate::common::Reg { + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x68usize) as _) } } #[doc = "Control whether debugger, DMA, core 0 and core 1 can access IO_BANK1, and at what security/privilege levels they can do so. Defaults to Secure access from any master. This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set."] #[inline(always)] - pub const fn io_bank1(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(108usize) as _) } + pub const fn io_bank1(self) -> crate::common::Reg { + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x6cusize) as _) } } #[doc = "Control whether debugger, DMA, core 0 and core 1 can access PADS_BANK0, and at what security/privilege levels they can do so. Defaults to Secure access from any master. This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set."] #[inline(always)] - pub const fn pads_bank0(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(112usize) as _) } + pub const fn pads_bank0(self) -> crate::common::Reg { + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x70usize) as _) } } #[doc = "Control whether debugger, DMA, core 0 and core 1 can access PADS_QSPI, and at what security/privilege levels they can do so. Defaults to Secure access from any master. This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set."] #[inline(always)] - pub const fn pads_qspi(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(116usize) as _) } + pub const fn pads_qspi(self) -> crate::common::Reg { + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x74usize) as _) } } #[doc = "Control whether debugger, DMA, core 0 and core 1 can access BUSCTRL, and at what security/privilege levels they can do so. Defaults to Secure access from any master. This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set."] #[inline(always)] - pub const fn busctrl(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(120usize) as _) } + pub const fn busctrl(self) -> crate::common::Reg { + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x78usize) as _) } } #[doc = "Control whether debugger, DMA, core 0 and core 1 can access ADC0, and at what security/privilege levels they can do so. Defaults to Secure access from any master. This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set."] #[inline(always)] - pub const fn adc0(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(124usize) as _) } + pub const fn adc0(self) -> crate::common::Reg { + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x7cusize) as _) } } #[doc = "Control whether debugger, DMA, core 0 and core 1 can access HSTX, and at what security/privilege levels they can do so. Defaults to Secure access from any master. This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set."] #[inline(always)] - pub const fn hstx(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(128usize) as _) } + pub const fn hstx(self) -> crate::common::Reg { + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x80usize) as _) } } #[doc = "Control whether debugger, DMA, core 0 and core 1 can access I2C0, and at what security/privilege levels they can do so. Defaults to Secure access from any master. This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set."] #[inline(always)] - pub const fn i2c0(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(132usize) as _) } + pub const fn i2c0(self) -> crate::common::Reg { + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x84usize) as _) } } #[doc = "Control whether debugger, DMA, core 0 and core 1 can access I2C1, and at what security/privilege levels they can do so. Defaults to Secure access from any master. This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set."] #[inline(always)] - pub const fn i2c1(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(136usize) as _) } + pub const fn i2c1(self) -> crate::common::Reg { + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x88usize) as _) } } #[doc = "Control whether debugger, DMA, core 0 and core 1 can access PWM, and at what security/privilege levels they can do so. Defaults to Secure access from any master. This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set."] #[inline(always)] - pub const fn pwm(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(140usize) as _) } + pub const fn pwm(self) -> crate::common::Reg { + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x8cusize) as _) } } #[doc = "Control whether debugger, DMA, core 0 and core 1 can access SPI0, and at what security/privilege levels they can do so. Defaults to Secure access from any master. This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set."] #[inline(always)] - pub const fn spi0(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(144usize) as _) } + pub const fn spi0(self) -> crate::common::Reg { + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x90usize) as _) } } #[doc = "Control whether debugger, DMA, core 0 and core 1 can access SPI1, and at what security/privilege levels they can do so. Defaults to Secure access from any master. This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set."] #[inline(always)] - pub const fn spi1(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(148usize) as _) } + pub const fn spi1(self) -> crate::common::Reg { + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x94usize) as _) } } #[doc = "Control whether debugger, DMA, core 0 and core 1 can access TIMER0, and at what security/privilege levels they can do so. Defaults to Secure access from any master. This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set."] #[inline(always)] - pub const fn timer0(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(152usize) as _) } + pub const fn timer0(self) -> crate::common::Reg { + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x98usize) as _) } } #[doc = "Control whether debugger, DMA, core 0 and core 1 can access TIMER1, and at what security/privilege levels they can do so. Defaults to Secure access from any master. This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set."] #[inline(always)] - pub const fn timer1(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(156usize) as _) } + pub const fn timer1(self) -> crate::common::Reg { + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x9cusize) as _) } } #[doc = "Control whether debugger, DMA, core 0 and core 1 can access UART0, and at what security/privilege levels they can do so. Defaults to Secure access from any master. This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set."] #[inline(always)] - pub const fn uart0(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(160usize) as _) } + pub const fn uart0(self) -> crate::common::Reg { + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0xa0usize) as _) } } #[doc = "Control whether debugger, DMA, core 0 and core 1 can access UART1, and at what security/privilege levels they can do so. Defaults to Secure access from any master. This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set."] #[inline(always)] - pub const fn uart1(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(164usize) as _) } + pub const fn uart1(self) -> crate::common::Reg { + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0xa4usize) as _) } } #[doc = "Control whether debugger, DMA, core 0 and core 1 can access OTP, and at what security/privilege levels they can do so. Defaults to Secure access from any master. This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set."] #[inline(always)] - pub const fn otp(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(168usize) as _) } + pub const fn otp(self) -> crate::common::Reg { + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0xa8usize) as _) } } #[doc = "Control whether debugger, DMA, core 0 and core 1 can access TBMAN, and at what security/privilege levels they can do so. Defaults to Secure access from any master. This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set."] #[inline(always)] - pub const fn tbman(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(172usize) as _) } + pub const fn tbman(self) -> crate::common::Reg { + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0xacusize) as _) } } #[doc = "Control whether debugger, DMA, core 0 and core 1 can access POWMAN, and at what security/privilege levels they can do so. Defaults to Secure, Privileged processor or debug access only. This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set."] #[inline(always)] - pub const fn powman(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(176usize) as _) } + pub const fn powman(self) -> crate::common::Reg { + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0xb0usize) as _) } } #[doc = "Control whether debugger, DMA, core 0 and core 1 can access TRNG, and at what security/privilege levels they can do so. Defaults to Secure, Privileged processor or debug access only. This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set."] #[inline(always)] - pub const fn trng(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(180usize) as _) } + pub const fn trng(self) -> crate::common::Reg { + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0xb4usize) as _) } } #[doc = "Control whether debugger, DMA, core 0 and core 1 can access SHA256, and at what security/privilege levels they can do so. Defaults to Secure, Privileged access only. This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set."] #[inline(always)] - pub const fn sha256(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(184usize) as _) } + pub const fn sha256(self) -> crate::common::Reg { + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0xb8usize) as _) } } #[doc = "Control whether debugger, DMA, core 0 and core 1 can access SYSCFG, and at what security/privilege levels they can do so. Defaults to Secure, Privileged processor or debug access only. This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set."] #[inline(always)] - pub const fn syscfg(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(188usize) as _) } + pub const fn syscfg(self) -> crate::common::Reg { + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0xbcusize) as _) } } #[doc = "Control whether debugger, DMA, core 0 and core 1 can access CLOCKS, and at what security/privilege levels they can do so. Defaults to Secure, Privileged processor or debug access only. This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set."] #[inline(always)] - pub const fn clocks(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(192usize) as _) } + pub const fn clocks(self) -> crate::common::Reg { + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0xc0usize) as _) } } #[doc = "Control whether debugger, DMA, core 0 and core 1 can access XOSC, and at what security/privilege levels they can do so. Defaults to Secure, Privileged processor or debug access only. This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set."] #[inline(always)] - pub const fn xosc(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(196usize) as _) } + pub const fn xosc(self) -> crate::common::Reg { + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0xc4usize) as _) } } #[doc = "Control whether debugger, DMA, core 0 and core 1 can access ROSC, and at what security/privilege levels they can do so. Defaults to Secure, Privileged processor or debug access only. This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set."] #[inline(always)] - pub const fn rosc(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(200usize) as _) } + pub const fn rosc(self) -> crate::common::Reg { + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0xc8usize) as _) } } #[doc = "Control whether debugger, DMA, core 0 and core 1 can access PLL_SYS, and at what security/privilege levels they can do so. Defaults to Secure, Privileged processor or debug access only. This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set."] #[inline(always)] - pub const fn pll_sys(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(204usize) as _) } + pub const fn pll_sys(self) -> crate::common::Reg { + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0xccusize) as _) } } #[doc = "Control whether debugger, DMA, core 0 and core 1 can access PLL_USB, and at what security/privilege levels they can do so. Defaults to Secure, Privileged processor or debug access only. This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set."] #[inline(always)] - pub const fn pll_usb(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(208usize) as _) } + pub const fn pll_usb(self) -> crate::common::Reg { + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0xd0usize) as _) } } #[doc = "Control whether debugger, DMA, core 0 and core 1 can access TICKS, and at what security/privilege levels they can do so. Defaults to Secure, Privileged processor or debug access only. This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set."] #[inline(always)] - pub const fn ticks(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(212usize) as _) } + pub const fn ticks(self) -> crate::common::Reg { + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0xd4usize) as _) } } #[doc = "Control whether debugger, DMA, core 0 and core 1 can access WATCHDOG, and at what security/privilege levels they can do so. Defaults to Secure, Privileged processor or debug access only. This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set."] #[inline(always)] - pub const fn watchdog(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(216usize) as _) } + pub const fn watchdog(self) -> crate::common::Reg { + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0xd8usize) as _) } } #[doc = "Control whether debugger, DMA, core 0 and core 1 can access RSM, and at what security/privilege levels they can do so. Defaults to Secure, Privileged processor or debug access only. This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set."] #[inline(always)] - pub const fn rsm(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(220usize) as _) } + pub const fn rsm(self) -> crate::common::Reg { + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0xdcusize) as _) } } #[doc = "Control whether debugger, DMA, core 0 and core 1 can access XIP_CTRL, and at what security/privilege levels they can do so. Defaults to Secure, Privileged processor or debug access only. This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set."] #[inline(always)] - pub const fn xip_ctrl(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(224usize) as _) } + pub const fn xip_ctrl(self) -> crate::common::Reg { + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0xe0usize) as _) } } #[doc = "Control whether debugger, DMA, core 0 and core 1 can access XIP_QMI, and at what security/privilege levels they can do so. Defaults to Secure, Privileged processor or debug access only. This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set."] #[inline(always)] - pub const fn xip_qmi(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(228usize) as _) } + pub const fn xip_qmi(self) -> crate::common::Reg { + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0xe4usize) as _) } } #[doc = "Control whether debugger, DMA, core 0 and core 1 can access XIP_AUX, and at what security/privilege levels they can do so. Defaults to Secure, Privileged access only. This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set."] #[inline(always)] - pub const fn xip_aux(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(232usize) as _) } + pub const fn xip_aux(self) -> crate::common::Reg { + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0xe8usize) as _) } } } pub mod regs; diff --git a/src/rp235x/accessctrl/regs.rs b/src/rp235x/accessctrl/regs.rs index 7ba666b4..555c108f 100644 --- a/src/rp235x/accessctrl/regs.rs +++ b/src/rp235x/accessctrl/regs.rs @@ -1,201 +1,101 @@ -#[doc = "Control whether debugger, DMA, core 0 and core 1 can access ADC0, and at what security/privilege levels they can do so. Defaults to Secure access from any master. This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set."] -#[repr(transparent)] -#[derive(Copy, Clone, Eq, PartialEq)] -pub struct Adc0(pub u32); -impl Adc0 { - #[doc = "If 1, and NSP is also set, ADC0 can be accessed from a Non-secure, Unprivileged context. This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set."] - #[inline(always)] - pub const fn nsu(&self) -> bool { - let val = (self.0 >> 0usize) & 0x01; - val != 0 - } - #[doc = "If 1, and NSP is also set, ADC0 can be accessed from a Non-secure, Unprivileged context. This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set."] - #[inline(always)] - pub fn set_nsu(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize); - } - #[doc = "If 1, ADC0 can be accessed from a Non-secure, Privileged context."] - #[inline(always)] - pub const fn nsp(&self) -> bool { - let val = (self.0 >> 1usize) & 0x01; - val != 0 - } - #[doc = "If 1, ADC0 can be accessed from a Non-secure, Privileged context."] - #[inline(always)] - pub fn set_nsp(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize); - } - #[doc = "If 1, and SP is also set, ADC0 can be accessed from a Secure, Unprivileged context."] - #[inline(always)] - pub const fn su(&self) -> bool { - let val = (self.0 >> 2usize) & 0x01; - val != 0 - } - #[doc = "If 1, and SP is also set, ADC0 can be accessed from a Secure, Unprivileged context."] - #[inline(always)] - pub fn set_su(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 2usize)) | (((val as u32) & 0x01) << 2usize); - } - #[doc = "If 1, ADC0 can be accessed from a Secure, Privileged context."] - #[inline(always)] - pub const fn sp(&self) -> bool { - let val = (self.0 >> 3usize) & 0x01; - val != 0 - } - #[doc = "If 1, ADC0 can be accessed from a Secure, Privileged context."] - #[inline(always)] - pub fn set_sp(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 3usize)) | (((val as u32) & 0x01) << 3usize); - } - #[doc = "If 1, ADC0 can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] - #[inline(always)] - pub const fn core0(&self) -> bool { - let val = (self.0 >> 4usize) & 0x01; - val != 0 - } - #[doc = "If 1, ADC0 can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] - #[inline(always)] - pub fn set_core0(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 4usize)) | (((val as u32) & 0x01) << 4usize); - } - #[doc = "If 1, ADC0 can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] - #[inline(always)] - pub const fn core1(&self) -> bool { - let val = (self.0 >> 5usize) & 0x01; - val != 0 - } - #[doc = "If 1, ADC0 can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] - #[inline(always)] - pub fn set_core1(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 5usize)) | (((val as u32) & 0x01) << 5usize); - } - #[doc = "If 1, ADC0 can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] - #[inline(always)] - pub const fn dma(&self) -> bool { - let val = (self.0 >> 6usize) & 0x01; - val != 0 - } - #[doc = "If 1, ADC0 can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] - #[inline(always)] - pub fn set_dma(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 6usize)) | (((val as u32) & 0x01) << 6usize); - } - #[doc = "If 1, ADC0 can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] - #[inline(always)] - pub const fn dbg(&self) -> bool { - let val = (self.0 >> 7usize) & 0x01; - val != 0 - } - #[doc = "If 1, ADC0 can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] - #[inline(always)] - pub fn set_dbg(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 7usize)) | (((val as u32) & 0x01) << 7usize); - } -} -impl Default for Adc0 { - #[inline(always)] - fn default() -> Adc0 { - Adc0(0) - } -} -#[doc = "Control whether debugger, DMA, core 0 and core 1 can access BUSCTRL, and at what security/privilege levels they can do so. Defaults to Secure access from any master. This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set."] +#[doc = "Control whether debugger, DMA, core 0 and core 1 can access TIMER0, and at what security/privilege levels they can do so. Defaults to Secure access from any master. This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set."] #[repr(transparent)] #[derive(Copy, Clone, Eq, PartialEq)] -pub struct Busctrl(pub u32); -impl Busctrl { - #[doc = "If 1, and NSP is also set, BUSCTRL can be accessed from a Non-secure, Unprivileged context. This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set."] +pub struct Access(pub u32); +impl Access { + #[doc = "If 1, and NSP is also set, TIMER0 can be accessed from a Non-secure, Unprivileged context. This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set."] #[inline(always)] pub const fn nsu(&self) -> bool { let val = (self.0 >> 0usize) & 0x01; val != 0 } - #[doc = "If 1, and NSP is also set, BUSCTRL can be accessed from a Non-secure, Unprivileged context. This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set."] + #[doc = "If 1, and NSP is also set, TIMER0 can be accessed from a Non-secure, Unprivileged context. This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set."] #[inline(always)] pub fn set_nsu(&mut self, val: bool) { self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize); } - #[doc = "If 1, BUSCTRL can be accessed from a Non-secure, Privileged context."] + #[doc = "If 1, TIMER0 can be accessed from a Non-secure, Privileged context."] #[inline(always)] pub const fn nsp(&self) -> bool { let val = (self.0 >> 1usize) & 0x01; val != 0 } - #[doc = "If 1, BUSCTRL can be accessed from a Non-secure, Privileged context."] + #[doc = "If 1, TIMER0 can be accessed from a Non-secure, Privileged context."] #[inline(always)] pub fn set_nsp(&mut self, val: bool) { self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize); } - #[doc = "If 1, and SP is also set, BUSCTRL can be accessed from a Secure, Unprivileged context."] + #[doc = "If 1, and SP is also set, TIMER0 can be accessed from a Secure, Unprivileged context."] #[inline(always)] pub const fn su(&self) -> bool { let val = (self.0 >> 2usize) & 0x01; val != 0 } - #[doc = "If 1, and SP is also set, BUSCTRL can be accessed from a Secure, Unprivileged context."] + #[doc = "If 1, and SP is also set, TIMER0 can be accessed from a Secure, Unprivileged context."] #[inline(always)] pub fn set_su(&mut self, val: bool) { self.0 = (self.0 & !(0x01 << 2usize)) | (((val as u32) & 0x01) << 2usize); } - #[doc = "If 1, BUSCTRL can be accessed from a Secure, Privileged context."] + #[doc = "If 1, TIMER0 can be accessed from a Secure, Privileged context."] #[inline(always)] pub const fn sp(&self) -> bool { let val = (self.0 >> 3usize) & 0x01; val != 0 } - #[doc = "If 1, BUSCTRL can be accessed from a Secure, Privileged context."] + #[doc = "If 1, TIMER0 can be accessed from a Secure, Privileged context."] #[inline(always)] pub fn set_sp(&mut self, val: bool) { self.0 = (self.0 & !(0x01 << 3usize)) | (((val as u32) & 0x01) << 3usize); } - #[doc = "If 1, BUSCTRL can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] + #[doc = "If 1, TIMER0 can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] #[inline(always)] pub const fn core0(&self) -> bool { let val = (self.0 >> 4usize) & 0x01; val != 0 } - #[doc = "If 1, BUSCTRL can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] + #[doc = "If 1, TIMER0 can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] #[inline(always)] pub fn set_core0(&mut self, val: bool) { self.0 = (self.0 & !(0x01 << 4usize)) | (((val as u32) & 0x01) << 4usize); } - #[doc = "If 1, BUSCTRL can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] + #[doc = "If 1, TIMER0 can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] #[inline(always)] pub const fn core1(&self) -> bool { let val = (self.0 >> 5usize) & 0x01; val != 0 } - #[doc = "If 1, BUSCTRL can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] + #[doc = "If 1, TIMER0 can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] #[inline(always)] pub fn set_core1(&mut self, val: bool) { self.0 = (self.0 & !(0x01 << 5usize)) | (((val as u32) & 0x01) << 5usize); } - #[doc = "If 1, BUSCTRL can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] + #[doc = "If 1, TIMER0 can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] #[inline(always)] pub const fn dma(&self) -> bool { let val = (self.0 >> 6usize) & 0x01; val != 0 } - #[doc = "If 1, BUSCTRL can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] + #[doc = "If 1, TIMER0 can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] #[inline(always)] pub fn set_dma(&mut self, val: bool) { self.0 = (self.0 & !(0x01 << 6usize)) | (((val as u32) & 0x01) << 6usize); } - #[doc = "If 1, BUSCTRL can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] + #[doc = "If 1, TIMER0 can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] #[inline(always)] pub const fn dbg(&self) -> bool { let val = (self.0 >> 7usize) & 0x01; val != 0 } - #[doc = "If 1, BUSCTRL can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] + #[doc = "If 1, TIMER0 can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] #[inline(always)] pub fn set_dbg(&mut self, val: bool) { self.0 = (self.0 & !(0x01 << 7usize)) | (((val as u32) & 0x01) << 7usize); } } -impl Default for Busctrl { +impl Default for Access { #[inline(always)] - fn default() -> Busctrl { - Busctrl(0) + fn default() -> Access { + Access(0) } } #[doc = "Write 1 to reset all ACCESSCTRL configuration, except for the LOCK and FORCE_CORE_NS registers. This bit is used in the RP2350 bootrom to quickly restore ACCESSCTRL to a known state during the boot path. Note that, like all registers in ACCESSCTRL, this register is not writable when the writer's corresponding LOCK bit is set, therefore a master which has been locked out of ACCESSCTRL can not use the CFGRESET register to disturb its contents."] @@ -219,5338 +119,138 @@ impl Default for Cfgreset { Cfgreset(0) } } -#[doc = "Control whether debugger, DMA, core 0 and core 1 can access CLOCKS, and at what security/privilege levels they can do so. Defaults to Secure, Privileged processor or debug access only. This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set."] +#[doc = "Force core 1's bus accesses to always be Non-secure, no matter the core's internal state. Useful for schemes where one core is designated as the Non-secure core, since some peripherals may filter individual registers internally based on security state but not on master ID."] #[repr(transparent)] #[derive(Copy, Clone, Eq, PartialEq)] -pub struct Clocks(pub u32); -impl Clocks { - #[doc = "If 1, and NSP is also set, CLOCKS can be accessed from a Non-secure, Unprivileged context. This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set."] - #[inline(always)] - pub const fn nsu(&self) -> bool { - let val = (self.0 >> 0usize) & 0x01; - val != 0 - } - #[doc = "If 1, and NSP is also set, CLOCKS can be accessed from a Non-secure, Unprivileged context. This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set."] - #[inline(always)] - pub fn set_nsu(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize); - } - #[doc = "If 1, CLOCKS can be accessed from a Non-secure, Privileged context."] +pub struct ForceCoreNs(pub u32); +impl ForceCoreNs { #[inline(always)] - pub const fn nsp(&self) -> bool { + pub const fn core1(&self) -> bool { let val = (self.0 >> 1usize) & 0x01; val != 0 } - #[doc = "If 1, CLOCKS can be accessed from a Non-secure, Privileged context."] #[inline(always)] - pub fn set_nsp(&mut self, val: bool) { + pub fn set_core1(&mut self, val: bool) { self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize); } - #[doc = "If 1, and SP is also set, CLOCKS can be accessed from a Secure, Unprivileged context."] +} +impl Default for ForceCoreNs { #[inline(always)] - pub const fn su(&self) -> bool { - let val = (self.0 >> 2usize) & 0x01; - val != 0 + fn default() -> ForceCoreNs { + ForceCoreNs(0) } - #[doc = "If 1, and SP is also set, CLOCKS can be accessed from a Secure, Unprivileged context."] +} +#[doc = "Control whether GPIO32..47 are accessible to Non-secure code, and whether QSPI and USB bitbang are accessible through the Non-secure SIO. Writable only by a Secure, Privileged processor or debugger."] +#[repr(transparent)] +#[derive(Copy, Clone, Eq, PartialEq)] +pub struct GpioNsmask1(pub u32); +impl GpioNsmask1 { #[inline(always)] - pub fn set_su(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 2usize)) | (((val as u32) & 0x01) << 2usize); + pub const fn gpio(&self) -> u16 { + let val = (self.0 >> 0usize) & 0xffff; + val as u16 } - #[doc = "If 1, CLOCKS can be accessed from a Secure, Privileged context."] #[inline(always)] - pub const fn sp(&self) -> bool { - let val = (self.0 >> 3usize) & 0x01; + pub fn set_gpio(&mut self, val: u16) { + self.0 = (self.0 & !(0xffff << 0usize)) | (((val as u32) & 0xffff) << 0usize); + } + #[inline(always)] + pub const fn usb_dp(&self) -> bool { + let val = (self.0 >> 24usize) & 0x01; val != 0 } - #[doc = "If 1, CLOCKS can be accessed from a Secure, Privileged context."] #[inline(always)] - pub fn set_sp(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 3usize)) | (((val as u32) & 0x01) << 3usize); + pub fn set_usb_dp(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 24usize)) | (((val as u32) & 0x01) << 24usize); } - #[doc = "If 1, CLOCKS can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] #[inline(always)] - pub const fn core0(&self) -> bool { - let val = (self.0 >> 4usize) & 0x01; + pub const fn usb_dm(&self) -> bool { + let val = (self.0 >> 25usize) & 0x01; val != 0 } - #[doc = "If 1, CLOCKS can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] #[inline(always)] - pub fn set_core0(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 4usize)) | (((val as u32) & 0x01) << 4usize); + pub fn set_usb_dm(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 25usize)) | (((val as u32) & 0x01) << 25usize); } - #[doc = "If 1, CLOCKS can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] #[inline(always)] - pub const fn core1(&self) -> bool { - let val = (self.0 >> 5usize) & 0x01; + pub const fn qspi_sck(&self) -> bool { + let val = (self.0 >> 26usize) & 0x01; val != 0 } - #[doc = "If 1, CLOCKS can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] #[inline(always)] - pub fn set_core1(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 5usize)) | (((val as u32) & 0x01) << 5usize); + pub fn set_qspi_sck(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 26usize)) | (((val as u32) & 0x01) << 26usize); } - #[doc = "If 1, CLOCKS can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] #[inline(always)] - pub const fn dma(&self) -> bool { - let val = (self.0 >> 6usize) & 0x01; + pub const fn qspi_csn(&self) -> bool { + let val = (self.0 >> 27usize) & 0x01; val != 0 } - #[doc = "If 1, CLOCKS can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] #[inline(always)] - pub fn set_dma(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 6usize)) | (((val as u32) & 0x01) << 6usize); + pub fn set_qspi_csn(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 27usize)) | (((val as u32) & 0x01) << 27usize); } - #[doc = "If 1, CLOCKS can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] #[inline(always)] - pub const fn dbg(&self) -> bool { - let val = (self.0 >> 7usize) & 0x01; - val != 0 + pub const fn qspi_sd(&self) -> u8 { + let val = (self.0 >> 28usize) & 0x0f; + val as u8 } - #[doc = "If 1, CLOCKS can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] #[inline(always)] - pub fn set_dbg(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 7usize)) | (((val as u32) & 0x01) << 7usize); + pub fn set_qspi_sd(&mut self, val: u8) { + self.0 = (self.0 & !(0x0f << 28usize)) | (((val as u32) & 0x0f) << 28usize); } } -impl Default for Clocks { +impl Default for GpioNsmask1 { #[inline(always)] - fn default() -> Clocks { - Clocks(0) + fn default() -> GpioNsmask1 { + GpioNsmask1(0) } } -#[doc = "Control whether debugger, DMA, core 0 and core 1 can access CORESIGHT_PERIPH, and at what security/privilege levels they can do so. Defaults to Secure, Privileged processor or debug access only. This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set."] +#[doc = "Once a LOCK bit is written to 1, ACCESSCTRL silently ignores writes from that master. LOCK is writable only by a Secure, Privileged processor or debugger. LOCK bits are only writable when their value is zero. Once set, they can never be cleared, except by a full reset of ACCESSCTRL Setting the LOCK bit does not affect whether an access raises a bus error. Unprivileged writes, or writes from the DMA, will continue to raise bus errors. All other accesses will continue not to."] #[repr(transparent)] #[derive(Copy, Clone, Eq, PartialEq)] -pub struct CoresightPeriph(pub u32); -impl CoresightPeriph { - #[doc = "If 1, and NSP is also set, CORESIGHT_PERIPH can be accessed from a Non-secure, Unprivileged context. This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set."] +pub struct Lock(pub u32); +impl Lock { #[inline(always)] - pub const fn nsu(&self) -> bool { + pub const fn core0(&self) -> bool { let val = (self.0 >> 0usize) & 0x01; val != 0 } - #[doc = "If 1, and NSP is also set, CORESIGHT_PERIPH can be accessed from a Non-secure, Unprivileged context. This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set."] #[inline(always)] - pub fn set_nsu(&mut self, val: bool) { + pub fn set_core0(&mut self, val: bool) { self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize); } - #[doc = "If 1, CORESIGHT_PERIPH can be accessed from a Non-secure, Privileged context."] #[inline(always)] - pub const fn nsp(&self) -> bool { + pub const fn core1(&self) -> bool { let val = (self.0 >> 1usize) & 0x01; val != 0 } - #[doc = "If 1, CORESIGHT_PERIPH can be accessed from a Non-secure, Privileged context."] #[inline(always)] - pub fn set_nsp(&mut self, val: bool) { + pub fn set_core1(&mut self, val: bool) { self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize); } - #[doc = "If 1, and SP is also set, CORESIGHT_PERIPH can be accessed from a Secure, Unprivileged context."] #[inline(always)] - pub const fn su(&self) -> bool { + pub const fn dma(&self) -> bool { let val = (self.0 >> 2usize) & 0x01; val != 0 } - #[doc = "If 1, and SP is also set, CORESIGHT_PERIPH can be accessed from a Secure, Unprivileged context."] #[inline(always)] - pub fn set_su(&mut self, val: bool) { + pub fn set_dma(&mut self, val: bool) { self.0 = (self.0 & !(0x01 << 2usize)) | (((val as u32) & 0x01) << 2usize); } - #[doc = "If 1, CORESIGHT_PERIPH can be accessed from a Secure, Privileged context."] #[inline(always)] - pub const fn sp(&self) -> bool { + pub const fn debug(&self) -> bool { let val = (self.0 >> 3usize) & 0x01; val != 0 } - #[doc = "If 1, CORESIGHT_PERIPH can be accessed from a Secure, Privileged context."] #[inline(always)] - pub fn set_sp(&mut self, val: bool) { + pub fn set_debug(&mut self, val: bool) { self.0 = (self.0 & !(0x01 << 3usize)) | (((val as u32) & 0x01) << 3usize); } - #[doc = "If 1, CORESIGHT_PERIPH can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] - #[inline(always)] - pub const fn core0(&self) -> bool { - let val = (self.0 >> 4usize) & 0x01; - val != 0 - } - #[doc = "If 1, CORESIGHT_PERIPH can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] - #[inline(always)] - pub fn set_core0(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 4usize)) | (((val as u32) & 0x01) << 4usize); - } - #[doc = "If 1, CORESIGHT_PERIPH can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] - #[inline(always)] - pub const fn core1(&self) -> bool { - let val = (self.0 >> 5usize) & 0x01; - val != 0 - } - #[doc = "If 1, CORESIGHT_PERIPH can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] - #[inline(always)] - pub fn set_core1(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 5usize)) | (((val as u32) & 0x01) << 5usize); - } - #[doc = "If 1, CORESIGHT_PERIPH can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] - #[inline(always)] - pub const fn dma(&self) -> bool { - let val = (self.0 >> 6usize) & 0x01; - val != 0 - } - #[doc = "If 1, CORESIGHT_PERIPH can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] - #[inline(always)] - pub fn set_dma(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 6usize)) | (((val as u32) & 0x01) << 6usize); - } - #[doc = "If 1, CORESIGHT_PERIPH can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] - #[inline(always)] - pub const fn dbg(&self) -> bool { - let val = (self.0 >> 7usize) & 0x01; - val != 0 - } - #[doc = "If 1, CORESIGHT_PERIPH can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] - #[inline(always)] - pub fn set_dbg(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 7usize)) | (((val as u32) & 0x01) << 7usize); - } -} -impl Default for CoresightPeriph { - #[inline(always)] - fn default() -> CoresightPeriph { - CoresightPeriph(0) - } } -#[doc = "Control whether debugger, DMA, core 0 and core 1 can access CORESIGHT_TRACE, and at what security/privilege levels they can do so. Defaults to Secure, Privileged processor or debug access only. This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set."] -#[repr(transparent)] -#[derive(Copy, Clone, Eq, PartialEq)] -pub struct CoresightTrace(pub u32); -impl CoresightTrace { - #[doc = "If 1, and NSP is also set, CORESIGHT_TRACE can be accessed from a Non-secure, Unprivileged context. This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set."] - #[inline(always)] - pub const fn nsu(&self) -> bool { - let val = (self.0 >> 0usize) & 0x01; - val != 0 - } - #[doc = "If 1, and NSP is also set, CORESIGHT_TRACE can be accessed from a Non-secure, Unprivileged context. This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set."] - #[inline(always)] - pub fn set_nsu(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize); - } - #[doc = "If 1, CORESIGHT_TRACE can be accessed from a Non-secure, Privileged context."] - #[inline(always)] - pub const fn nsp(&self) -> bool { - let val = (self.0 >> 1usize) & 0x01; - val != 0 - } - #[doc = "If 1, CORESIGHT_TRACE can be accessed from a Non-secure, Privileged context."] +impl Default for Lock { #[inline(always)] - pub fn set_nsp(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize); - } - #[doc = "If 1, and SP is also set, CORESIGHT_TRACE can be accessed from a Secure, Unprivileged context."] - #[inline(always)] - pub const fn su(&self) -> bool { - let val = (self.0 >> 2usize) & 0x01; - val != 0 - } - #[doc = "If 1, and SP is also set, CORESIGHT_TRACE can be accessed from a Secure, Unprivileged context."] - #[inline(always)] - pub fn set_su(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 2usize)) | (((val as u32) & 0x01) << 2usize); - } - #[doc = "If 1, CORESIGHT_TRACE can be accessed from a Secure, Privileged context."] - #[inline(always)] - pub const fn sp(&self) -> bool { - let val = (self.0 >> 3usize) & 0x01; - val != 0 - } - #[doc = "If 1, CORESIGHT_TRACE can be accessed from a Secure, Privileged context."] - #[inline(always)] - pub fn set_sp(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 3usize)) | (((val as u32) & 0x01) << 3usize); - } - #[doc = "If 1, CORESIGHT_TRACE can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] - #[inline(always)] - pub const fn core0(&self) -> bool { - let val = (self.0 >> 4usize) & 0x01; - val != 0 - } - #[doc = "If 1, CORESIGHT_TRACE can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] - #[inline(always)] - pub fn set_core0(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 4usize)) | (((val as u32) & 0x01) << 4usize); - } - #[doc = "If 1, CORESIGHT_TRACE can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] - #[inline(always)] - pub const fn core1(&self) -> bool { - let val = (self.0 >> 5usize) & 0x01; - val != 0 - } - #[doc = "If 1, CORESIGHT_TRACE can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] - #[inline(always)] - pub fn set_core1(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 5usize)) | (((val as u32) & 0x01) << 5usize); - } - #[doc = "If 1, CORESIGHT_TRACE can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] - #[inline(always)] - pub const fn dma(&self) -> bool { - let val = (self.0 >> 6usize) & 0x01; - val != 0 - } - #[doc = "If 1, CORESIGHT_TRACE can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] - #[inline(always)] - pub fn set_dma(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 6usize)) | (((val as u32) & 0x01) << 6usize); - } - #[doc = "If 1, CORESIGHT_TRACE can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] - #[inline(always)] - pub const fn dbg(&self) -> bool { - let val = (self.0 >> 7usize) & 0x01; - val != 0 - } - #[doc = "If 1, CORESIGHT_TRACE can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] - #[inline(always)] - pub fn set_dbg(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 7usize)) | (((val as u32) & 0x01) << 7usize); - } -} -impl Default for CoresightTrace { - #[inline(always)] - fn default() -> CoresightTrace { - CoresightTrace(0) - } -} -#[doc = "Control whether debugger, DMA, core 0 and core 1 can access DMA, and at what security/privilege levels they can do so. Defaults to Secure access from any master. This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set."] -#[repr(transparent)] -#[derive(Copy, Clone, Eq, PartialEq)] -pub struct Dma(pub u32); -impl Dma { - #[doc = "If 1, and NSP is also set, DMA can be accessed from a Non-secure, Unprivileged context. This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set."] - #[inline(always)] - pub const fn nsu(&self) -> bool { - let val = (self.0 >> 0usize) & 0x01; - val != 0 - } - #[doc = "If 1, and NSP is also set, DMA can be accessed from a Non-secure, Unprivileged context. This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set."] - #[inline(always)] - pub fn set_nsu(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize); - } - #[doc = "If 1, DMA can be accessed from a Non-secure, Privileged context."] - #[inline(always)] - pub const fn nsp(&self) -> bool { - let val = (self.0 >> 1usize) & 0x01; - val != 0 - } - #[doc = "If 1, DMA can be accessed from a Non-secure, Privileged context."] - #[inline(always)] - pub fn set_nsp(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize); - } - #[doc = "If 1, and SP is also set, DMA can be accessed from a Secure, Unprivileged context."] - #[inline(always)] - pub const fn su(&self) -> bool { - let val = (self.0 >> 2usize) & 0x01; - val != 0 - } - #[doc = "If 1, and SP is also set, DMA can be accessed from a Secure, Unprivileged context."] - #[inline(always)] - pub fn set_su(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 2usize)) | (((val as u32) & 0x01) << 2usize); - } - #[doc = "If 1, DMA can be accessed from a Secure, Privileged context."] - #[inline(always)] - pub const fn sp(&self) -> bool { - let val = (self.0 >> 3usize) & 0x01; - val != 0 - } - #[doc = "If 1, DMA can be accessed from a Secure, Privileged context."] - #[inline(always)] - pub fn set_sp(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 3usize)) | (((val as u32) & 0x01) << 3usize); - } - #[doc = "If 1, DMA can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] - #[inline(always)] - pub const fn core0(&self) -> bool { - let val = (self.0 >> 4usize) & 0x01; - val != 0 - } - #[doc = "If 1, DMA can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] - #[inline(always)] - pub fn set_core0(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 4usize)) | (((val as u32) & 0x01) << 4usize); - } - #[doc = "If 1, DMA can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] - #[inline(always)] - pub const fn core1(&self) -> bool { - let val = (self.0 >> 5usize) & 0x01; - val != 0 - } - #[doc = "If 1, DMA can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] - #[inline(always)] - pub fn set_core1(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 5usize)) | (((val as u32) & 0x01) << 5usize); - } - #[doc = "If 1, DMA can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] - #[inline(always)] - pub const fn dma(&self) -> bool { - let val = (self.0 >> 6usize) & 0x01; - val != 0 - } - #[doc = "If 1, DMA can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] - #[inline(always)] - pub fn set_dma(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 6usize)) | (((val as u32) & 0x01) << 6usize); - } - #[doc = "If 1, DMA can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] - #[inline(always)] - pub const fn dbg(&self) -> bool { - let val = (self.0 >> 7usize) & 0x01; - val != 0 - } - #[doc = "If 1, DMA can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] - #[inline(always)] - pub fn set_dbg(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 7usize)) | (((val as u32) & 0x01) << 7usize); - } -} -impl Default for Dma { - #[inline(always)] - fn default() -> Dma { - Dma(0) - } -} -#[doc = "Force core 1's bus accesses to always be Non-secure, no matter the core's internal state. Useful for schemes where one core is designated as the Non-secure core, since some peripherals may filter individual registers internally based on security state but not on master ID."] -#[repr(transparent)] -#[derive(Copy, Clone, Eq, PartialEq)] -pub struct ForceCoreNs(pub u32); -impl ForceCoreNs { - #[inline(always)] - pub const fn core1(&self) -> bool { - let val = (self.0 >> 1usize) & 0x01; - val != 0 - } - #[inline(always)] - pub fn set_core1(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize); - } -} -impl Default for ForceCoreNs { - #[inline(always)] - fn default() -> ForceCoreNs { - ForceCoreNs(0) - } -} -#[doc = "Control whether GPIO32..47 are accessible to Non-secure code, and whether QSPI and USB bitbang are accessible through the Non-secure SIO. Writable only by a Secure, Privileged processor or debugger."] -#[repr(transparent)] -#[derive(Copy, Clone, Eq, PartialEq)] -pub struct GpioNsmask1(pub u32); -impl GpioNsmask1 { - #[inline(always)] - pub const fn gpio(&self) -> u16 { - let val = (self.0 >> 0usize) & 0xffff; - val as u16 - } - #[inline(always)] - pub fn set_gpio(&mut self, val: u16) { - self.0 = (self.0 & !(0xffff << 0usize)) | (((val as u32) & 0xffff) << 0usize); - } - #[inline(always)] - pub const fn usb_dp(&self) -> bool { - let val = (self.0 >> 24usize) & 0x01; - val != 0 - } - #[inline(always)] - pub fn set_usb_dp(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 24usize)) | (((val as u32) & 0x01) << 24usize); - } - #[inline(always)] - pub const fn usb_dm(&self) -> bool { - let val = (self.0 >> 25usize) & 0x01; - val != 0 - } - #[inline(always)] - pub fn set_usb_dm(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 25usize)) | (((val as u32) & 0x01) << 25usize); - } - #[inline(always)] - pub const fn qspi_sck(&self) -> bool { - let val = (self.0 >> 26usize) & 0x01; - val != 0 - } - #[inline(always)] - pub fn set_qspi_sck(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 26usize)) | (((val as u32) & 0x01) << 26usize); - } - #[inline(always)] - pub const fn qspi_csn(&self) -> bool { - let val = (self.0 >> 27usize) & 0x01; - val != 0 - } - #[inline(always)] - pub fn set_qspi_csn(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 27usize)) | (((val as u32) & 0x01) << 27usize); - } - #[inline(always)] - pub const fn qspi_sd(&self) -> u8 { - let val = (self.0 >> 28usize) & 0x0f; - val as u8 - } - #[inline(always)] - pub fn set_qspi_sd(&mut self, val: u8) { - self.0 = (self.0 & !(0x0f << 28usize)) | (((val as u32) & 0x0f) << 28usize); - } -} -impl Default for GpioNsmask1 { - #[inline(always)] - fn default() -> GpioNsmask1 { - GpioNsmask1(0) - } -} -#[doc = "Control whether debugger, DMA, core 0 and core 1 can access HSTX, and at what security/privilege levels they can do so. Defaults to Secure access from any master. This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set."] -#[repr(transparent)] -#[derive(Copy, Clone, Eq, PartialEq)] -pub struct Hstx(pub u32); -impl Hstx { - #[doc = "If 1, and NSP is also set, HSTX can be accessed from a Non-secure, Unprivileged context. This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set."] - #[inline(always)] - pub const fn nsu(&self) -> bool { - let val = (self.0 >> 0usize) & 0x01; - val != 0 - } - #[doc = "If 1, and NSP is also set, HSTX can be accessed from a Non-secure, Unprivileged context. This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set."] - #[inline(always)] - pub fn set_nsu(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize); - } - #[doc = "If 1, HSTX can be accessed from a Non-secure, Privileged context."] - #[inline(always)] - pub const fn nsp(&self) -> bool { - let val = (self.0 >> 1usize) & 0x01; - val != 0 - } - #[doc = "If 1, HSTX can be accessed from a Non-secure, Privileged context."] - #[inline(always)] - pub fn set_nsp(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize); - } - #[doc = "If 1, and SP is also set, HSTX can be accessed from a Secure, Unprivileged context."] - #[inline(always)] - pub const fn su(&self) -> bool { - let val = (self.0 >> 2usize) & 0x01; - val != 0 - } - #[doc = "If 1, and SP is also set, HSTX can be accessed from a Secure, Unprivileged context."] - #[inline(always)] - pub fn set_su(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 2usize)) | (((val as u32) & 0x01) << 2usize); - } - #[doc = "If 1, HSTX can be accessed from a Secure, Privileged context."] - #[inline(always)] - pub const fn sp(&self) -> bool { - let val = (self.0 >> 3usize) & 0x01; - val != 0 - } - #[doc = "If 1, HSTX can be accessed from a Secure, Privileged context."] - #[inline(always)] - pub fn set_sp(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 3usize)) | (((val as u32) & 0x01) << 3usize); - } - #[doc = "If 1, HSTX can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] - #[inline(always)] - pub const fn core0(&self) -> bool { - let val = (self.0 >> 4usize) & 0x01; - val != 0 - } - #[doc = "If 1, HSTX can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] - #[inline(always)] - pub fn set_core0(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 4usize)) | (((val as u32) & 0x01) << 4usize); - } - #[doc = "If 1, HSTX can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] - #[inline(always)] - pub const fn core1(&self) -> bool { - let val = (self.0 >> 5usize) & 0x01; - val != 0 - } - #[doc = "If 1, HSTX can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] - #[inline(always)] - pub fn set_core1(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 5usize)) | (((val as u32) & 0x01) << 5usize); - } - #[doc = "If 1, HSTX can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] - #[inline(always)] - pub const fn dma(&self) -> bool { - let val = (self.0 >> 6usize) & 0x01; - val != 0 - } - #[doc = "If 1, HSTX can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] - #[inline(always)] - pub fn set_dma(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 6usize)) | (((val as u32) & 0x01) << 6usize); - } - #[doc = "If 1, HSTX can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] - #[inline(always)] - pub const fn dbg(&self) -> bool { - let val = (self.0 >> 7usize) & 0x01; - val != 0 - } - #[doc = "If 1, HSTX can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] - #[inline(always)] - pub fn set_dbg(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 7usize)) | (((val as u32) & 0x01) << 7usize); - } -} -impl Default for Hstx { - #[inline(always)] - fn default() -> Hstx { - Hstx(0) - } -} -#[doc = "Control whether debugger, DMA, core 0 and core 1 can access I2C0, and at what security/privilege levels they can do so. Defaults to Secure access from any master. This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set."] -#[repr(transparent)] -#[derive(Copy, Clone, Eq, PartialEq)] -pub struct I2c0(pub u32); -impl I2c0 { - #[doc = "If 1, and NSP is also set, I2C0 can be accessed from a Non-secure, Unprivileged context. This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set."] - #[inline(always)] - pub const fn nsu(&self) -> bool { - let val = (self.0 >> 0usize) & 0x01; - val != 0 - } - #[doc = "If 1, and NSP is also set, I2C0 can be accessed from a Non-secure, Unprivileged context. This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set."] - #[inline(always)] - pub fn set_nsu(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize); - } - #[doc = "If 1, I2C0 can be accessed from a Non-secure, Privileged context."] - #[inline(always)] - pub const fn nsp(&self) -> bool { - let val = (self.0 >> 1usize) & 0x01; - val != 0 - } - #[doc = "If 1, I2C0 can be accessed from a Non-secure, Privileged context."] - #[inline(always)] - pub fn set_nsp(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize); - } - #[doc = "If 1, and SP is also set, I2C0 can be accessed from a Secure, Unprivileged context."] - #[inline(always)] - pub const fn su(&self) -> bool { - let val = (self.0 >> 2usize) & 0x01; - val != 0 - } - #[doc = "If 1, and SP is also set, I2C0 can be accessed from a Secure, Unprivileged context."] - #[inline(always)] - pub fn set_su(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 2usize)) | (((val as u32) & 0x01) << 2usize); - } - #[doc = "If 1, I2C0 can be accessed from a Secure, Privileged context."] - #[inline(always)] - pub const fn sp(&self) -> bool { - let val = (self.0 >> 3usize) & 0x01; - val != 0 - } - #[doc = "If 1, I2C0 can be accessed from a Secure, Privileged context."] - #[inline(always)] - pub fn set_sp(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 3usize)) | (((val as u32) & 0x01) << 3usize); - } - #[doc = "If 1, I2C0 can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] - #[inline(always)] - pub const fn core0(&self) -> bool { - let val = (self.0 >> 4usize) & 0x01; - val != 0 - } - #[doc = "If 1, I2C0 can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] - #[inline(always)] - pub fn set_core0(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 4usize)) | (((val as u32) & 0x01) << 4usize); - } - #[doc = "If 1, I2C0 can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] - #[inline(always)] - pub const fn core1(&self) -> bool { - let val = (self.0 >> 5usize) & 0x01; - val != 0 - } - #[doc = "If 1, I2C0 can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] - #[inline(always)] - pub fn set_core1(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 5usize)) | (((val as u32) & 0x01) << 5usize); - } - #[doc = "If 1, I2C0 can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] - #[inline(always)] - pub const fn dma(&self) -> bool { - let val = (self.0 >> 6usize) & 0x01; - val != 0 - } - #[doc = "If 1, I2C0 can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] - #[inline(always)] - pub fn set_dma(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 6usize)) | (((val as u32) & 0x01) << 6usize); - } - #[doc = "If 1, I2C0 can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] - #[inline(always)] - pub const fn dbg(&self) -> bool { - let val = (self.0 >> 7usize) & 0x01; - val != 0 - } - #[doc = "If 1, I2C0 can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] - #[inline(always)] - pub fn set_dbg(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 7usize)) | (((val as u32) & 0x01) << 7usize); - } -} -impl Default for I2c0 { - #[inline(always)] - fn default() -> I2c0 { - I2c0(0) - } -} -#[doc = "Control whether debugger, DMA, core 0 and core 1 can access I2C1, and at what security/privilege levels they can do so. Defaults to Secure access from any master. This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set."] -#[repr(transparent)] -#[derive(Copy, Clone, Eq, PartialEq)] -pub struct I2c1(pub u32); -impl I2c1 { - #[doc = "If 1, and NSP is also set, I2C1 can be accessed from a Non-secure, Unprivileged context. This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set."] - #[inline(always)] - pub const fn nsu(&self) -> bool { - let val = (self.0 >> 0usize) & 0x01; - val != 0 - } - #[doc = "If 1, and NSP is also set, I2C1 can be accessed from a Non-secure, Unprivileged context. This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set."] - #[inline(always)] - pub fn set_nsu(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize); - } - #[doc = "If 1, I2C1 can be accessed from a Non-secure, Privileged context."] - #[inline(always)] - pub const fn nsp(&self) -> bool { - let val = (self.0 >> 1usize) & 0x01; - val != 0 - } - #[doc = "If 1, I2C1 can be accessed from a Non-secure, Privileged context."] - #[inline(always)] - pub fn set_nsp(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize); - } - #[doc = "If 1, and SP is also set, I2C1 can be accessed from a Secure, Unprivileged context."] - #[inline(always)] - pub const fn su(&self) -> bool { - let val = (self.0 >> 2usize) & 0x01; - val != 0 - } - #[doc = "If 1, and SP is also set, I2C1 can be accessed from a Secure, Unprivileged context."] - #[inline(always)] - pub fn set_su(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 2usize)) | (((val as u32) & 0x01) << 2usize); - } - #[doc = "If 1, I2C1 can be accessed from a Secure, Privileged context."] - #[inline(always)] - pub const fn sp(&self) -> bool { - let val = (self.0 >> 3usize) & 0x01; - val != 0 - } - #[doc = "If 1, I2C1 can be accessed from a Secure, Privileged context."] - #[inline(always)] - pub fn set_sp(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 3usize)) | (((val as u32) & 0x01) << 3usize); - } - #[doc = "If 1, I2C1 can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] - #[inline(always)] - pub const fn core0(&self) -> bool { - let val = (self.0 >> 4usize) & 0x01; - val != 0 - } - #[doc = "If 1, I2C1 can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] - #[inline(always)] - pub fn set_core0(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 4usize)) | (((val as u32) & 0x01) << 4usize); - } - #[doc = "If 1, I2C1 can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] - #[inline(always)] - pub const fn core1(&self) -> bool { - let val = (self.0 >> 5usize) & 0x01; - val != 0 - } - #[doc = "If 1, I2C1 can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] - #[inline(always)] - pub fn set_core1(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 5usize)) | (((val as u32) & 0x01) << 5usize); - } - #[doc = "If 1, I2C1 can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] - #[inline(always)] - pub const fn dma(&self) -> bool { - let val = (self.0 >> 6usize) & 0x01; - val != 0 - } - #[doc = "If 1, I2C1 can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] - #[inline(always)] - pub fn set_dma(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 6usize)) | (((val as u32) & 0x01) << 6usize); - } - #[doc = "If 1, I2C1 can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] - #[inline(always)] - pub const fn dbg(&self) -> bool { - let val = (self.0 >> 7usize) & 0x01; - val != 0 - } - #[doc = "If 1, I2C1 can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] - #[inline(always)] - pub fn set_dbg(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 7usize)) | (((val as u32) & 0x01) << 7usize); - } -} -impl Default for I2c1 { - #[inline(always)] - fn default() -> I2c1 { - I2c1(0) - } -} -#[doc = "Control whether debugger, DMA, core 0 and core 1 can access IO_BANK0, and at what security/privilege levels they can do so. Defaults to Secure access from any master. This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set."] -#[repr(transparent)] -#[derive(Copy, Clone, Eq, PartialEq)] -pub struct IoBank0(pub u32); -impl IoBank0 { - #[doc = "If 1, and NSP is also set, IO_BANK0 can be accessed from a Non-secure, Unprivileged context. This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set."] - #[inline(always)] - pub const fn nsu(&self) -> bool { - let val = (self.0 >> 0usize) & 0x01; - val != 0 - } - #[doc = "If 1, and NSP is also set, IO_BANK0 can be accessed from a Non-secure, Unprivileged context. This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set."] - #[inline(always)] - pub fn set_nsu(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize); - } - #[doc = "If 1, IO_BANK0 can be accessed from a Non-secure, Privileged context."] - #[inline(always)] - pub const fn nsp(&self) -> bool { - let val = (self.0 >> 1usize) & 0x01; - val != 0 - } - #[doc = "If 1, IO_BANK0 can be accessed from a Non-secure, Privileged context."] - #[inline(always)] - pub fn set_nsp(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize); - } - #[doc = "If 1, and SP is also set, IO_BANK0 can be accessed from a Secure, Unprivileged context."] - #[inline(always)] - pub const fn su(&self) -> bool { - let val = (self.0 >> 2usize) & 0x01; - val != 0 - } - #[doc = "If 1, and SP is also set, IO_BANK0 can be accessed from a Secure, Unprivileged context."] - #[inline(always)] - pub fn set_su(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 2usize)) | (((val as u32) & 0x01) << 2usize); - } - #[doc = "If 1, IO_BANK0 can be accessed from a Secure, Privileged context."] - #[inline(always)] - pub const fn sp(&self) -> bool { - let val = (self.0 >> 3usize) & 0x01; - val != 0 - } - #[doc = "If 1, IO_BANK0 can be accessed from a Secure, Privileged context."] - #[inline(always)] - pub fn set_sp(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 3usize)) | (((val as u32) & 0x01) << 3usize); - } - #[doc = "If 1, IO_BANK0 can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] - #[inline(always)] - pub const fn core0(&self) -> bool { - let val = (self.0 >> 4usize) & 0x01; - val != 0 - } - #[doc = "If 1, IO_BANK0 can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] - #[inline(always)] - pub fn set_core0(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 4usize)) | (((val as u32) & 0x01) << 4usize); - } - #[doc = "If 1, IO_BANK0 can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] - #[inline(always)] - pub const fn core1(&self) -> bool { - let val = (self.0 >> 5usize) & 0x01; - val != 0 - } - #[doc = "If 1, IO_BANK0 can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] - #[inline(always)] - pub fn set_core1(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 5usize)) | (((val as u32) & 0x01) << 5usize); - } - #[doc = "If 1, IO_BANK0 can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] - #[inline(always)] - pub const fn dma(&self) -> bool { - let val = (self.0 >> 6usize) & 0x01; - val != 0 - } - #[doc = "If 1, IO_BANK0 can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] - #[inline(always)] - pub fn set_dma(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 6usize)) | (((val as u32) & 0x01) << 6usize); - } - #[doc = "If 1, IO_BANK0 can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] - #[inline(always)] - pub const fn dbg(&self) -> bool { - let val = (self.0 >> 7usize) & 0x01; - val != 0 - } - #[doc = "If 1, IO_BANK0 can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] - #[inline(always)] - pub fn set_dbg(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 7usize)) | (((val as u32) & 0x01) << 7usize); - } -} -impl Default for IoBank0 { - #[inline(always)] - fn default() -> IoBank0 { - IoBank0(0) - } -} -#[doc = "Control whether debugger, DMA, core 0 and core 1 can access IO_BANK1, and at what security/privilege levels they can do so. Defaults to Secure access from any master. This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set."] -#[repr(transparent)] -#[derive(Copy, Clone, Eq, PartialEq)] -pub struct IoBank1(pub u32); -impl IoBank1 { - #[doc = "If 1, and NSP is also set, IO_BANK1 can be accessed from a Non-secure, Unprivileged context. This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set."] - #[inline(always)] - pub const fn nsu(&self) -> bool { - let val = (self.0 >> 0usize) & 0x01; - val != 0 - } - #[doc = "If 1, and NSP is also set, IO_BANK1 can be accessed from a Non-secure, Unprivileged context. This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set."] - #[inline(always)] - pub fn set_nsu(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize); - } - #[doc = "If 1, IO_BANK1 can be accessed from a Non-secure, Privileged context."] - #[inline(always)] - pub const fn nsp(&self) -> bool { - let val = (self.0 >> 1usize) & 0x01; - val != 0 - } - #[doc = "If 1, IO_BANK1 can be accessed from a Non-secure, Privileged context."] - #[inline(always)] - pub fn set_nsp(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize); - } - #[doc = "If 1, and SP is also set, IO_BANK1 can be accessed from a Secure, Unprivileged context."] - #[inline(always)] - pub const fn su(&self) -> bool { - let val = (self.0 >> 2usize) & 0x01; - val != 0 - } - #[doc = "If 1, and SP is also set, IO_BANK1 can be accessed from a Secure, Unprivileged context."] - #[inline(always)] - pub fn set_su(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 2usize)) | (((val as u32) & 0x01) << 2usize); - } - #[doc = "If 1, IO_BANK1 can be accessed from a Secure, Privileged context."] - #[inline(always)] - pub const fn sp(&self) -> bool { - let val = (self.0 >> 3usize) & 0x01; - val != 0 - } - #[doc = "If 1, IO_BANK1 can be accessed from a Secure, Privileged context."] - #[inline(always)] - pub fn set_sp(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 3usize)) | (((val as u32) & 0x01) << 3usize); - } - #[doc = "If 1, IO_BANK1 can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] - #[inline(always)] - pub const fn core0(&self) -> bool { - let val = (self.0 >> 4usize) & 0x01; - val != 0 - } - #[doc = "If 1, IO_BANK1 can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] - #[inline(always)] - pub fn set_core0(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 4usize)) | (((val as u32) & 0x01) << 4usize); - } - #[doc = "If 1, IO_BANK1 can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] - #[inline(always)] - pub const fn core1(&self) -> bool { - let val = (self.0 >> 5usize) & 0x01; - val != 0 - } - #[doc = "If 1, IO_BANK1 can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] - #[inline(always)] - pub fn set_core1(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 5usize)) | (((val as u32) & 0x01) << 5usize); - } - #[doc = "If 1, IO_BANK1 can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] - #[inline(always)] - pub const fn dma(&self) -> bool { - let val = (self.0 >> 6usize) & 0x01; - val != 0 - } - #[doc = "If 1, IO_BANK1 can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] - #[inline(always)] - pub fn set_dma(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 6usize)) | (((val as u32) & 0x01) << 6usize); - } - #[doc = "If 1, IO_BANK1 can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] - #[inline(always)] - pub const fn dbg(&self) -> bool { - let val = (self.0 >> 7usize) & 0x01; - val != 0 - } - #[doc = "If 1, IO_BANK1 can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] - #[inline(always)] - pub fn set_dbg(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 7usize)) | (((val as u32) & 0x01) << 7usize); - } -} -impl Default for IoBank1 { - #[inline(always)] - fn default() -> IoBank1 { - IoBank1(0) - } -} -#[doc = "Once a LOCK bit is written to 1, ACCESSCTRL silently ignores writes from that master. LOCK is writable only by a Secure, Privileged processor or debugger. LOCK bits are only writable when their value is zero. Once set, they can never be cleared, except by a full reset of ACCESSCTRL Setting the LOCK bit does not affect whether an access raises a bus error. Unprivileged writes, or writes from the DMA, will continue to raise bus errors. All other accesses will continue not to."] -#[repr(transparent)] -#[derive(Copy, Clone, Eq, PartialEq)] -pub struct Lock(pub u32); -impl Lock { - #[inline(always)] - pub const fn core0(&self) -> bool { - let val = (self.0 >> 0usize) & 0x01; - val != 0 - } - #[inline(always)] - pub fn set_core0(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize); - } - #[inline(always)] - pub const fn core1(&self) -> bool { - let val = (self.0 >> 1usize) & 0x01; - val != 0 - } - #[inline(always)] - pub fn set_core1(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize); - } - #[inline(always)] - pub const fn dma(&self) -> bool { - let val = (self.0 >> 2usize) & 0x01; - val != 0 - } - #[inline(always)] - pub fn set_dma(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 2usize)) | (((val as u32) & 0x01) << 2usize); - } - #[inline(always)] - pub const fn debug(&self) -> bool { - let val = (self.0 >> 3usize) & 0x01; - val != 0 - } - #[inline(always)] - pub fn set_debug(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 3usize)) | (((val as u32) & 0x01) << 3usize); - } -} -impl Default for Lock { - #[inline(always)] - fn default() -> Lock { - Lock(0) - } -} -#[doc = "Control whether debugger, DMA, core 0 and core 1 can access OTP, and at what security/privilege levels they can do so. Defaults to Secure access from any master. This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set."] -#[repr(transparent)] -#[derive(Copy, Clone, Eq, PartialEq)] -pub struct Otp(pub u32); -impl Otp { - #[doc = "If 1, and NSP is also set, OTP can be accessed from a Non-secure, Unprivileged context. This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set."] - #[inline(always)] - pub const fn nsu(&self) -> bool { - let val = (self.0 >> 0usize) & 0x01; - val != 0 - } - #[doc = "If 1, and NSP is also set, OTP can be accessed from a Non-secure, Unprivileged context. This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set."] - #[inline(always)] - pub fn set_nsu(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize); - } - #[doc = "If 1, OTP can be accessed from a Non-secure, Privileged context."] - #[inline(always)] - pub const fn nsp(&self) -> bool { - let val = (self.0 >> 1usize) & 0x01; - val != 0 - } - #[doc = "If 1, OTP can be accessed from a Non-secure, Privileged context."] - #[inline(always)] - pub fn set_nsp(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize); - } - #[doc = "If 1, and SP is also set, OTP can be accessed from a Secure, Unprivileged context."] - #[inline(always)] - pub const fn su(&self) -> bool { - let val = (self.0 >> 2usize) & 0x01; - val != 0 - } - #[doc = "If 1, and SP is also set, OTP can be accessed from a Secure, Unprivileged context."] - #[inline(always)] - pub fn set_su(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 2usize)) | (((val as u32) & 0x01) << 2usize); - } - #[doc = "If 1, OTP can be accessed from a Secure, Privileged context."] - #[inline(always)] - pub const fn sp(&self) -> bool { - let val = (self.0 >> 3usize) & 0x01; - val != 0 - } - #[doc = "If 1, OTP can be accessed from a Secure, Privileged context."] - #[inline(always)] - pub fn set_sp(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 3usize)) | (((val as u32) & 0x01) << 3usize); - } - #[doc = "If 1, OTP can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] - #[inline(always)] - pub const fn core0(&self) -> bool { - let val = (self.0 >> 4usize) & 0x01; - val != 0 - } - #[doc = "If 1, OTP can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] - #[inline(always)] - pub fn set_core0(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 4usize)) | (((val as u32) & 0x01) << 4usize); - } - #[doc = "If 1, OTP can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] - #[inline(always)] - pub const fn core1(&self) -> bool { - let val = (self.0 >> 5usize) & 0x01; - val != 0 - } - #[doc = "If 1, OTP can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] - #[inline(always)] - pub fn set_core1(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 5usize)) | (((val as u32) & 0x01) << 5usize); - } - #[doc = "If 1, OTP can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] - #[inline(always)] - pub const fn dma(&self) -> bool { - let val = (self.0 >> 6usize) & 0x01; - val != 0 - } - #[doc = "If 1, OTP can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] - #[inline(always)] - pub fn set_dma(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 6usize)) | (((val as u32) & 0x01) << 6usize); - } - #[doc = "If 1, OTP can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] - #[inline(always)] - pub const fn dbg(&self) -> bool { - let val = (self.0 >> 7usize) & 0x01; - val != 0 - } - #[doc = "If 1, OTP can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] - #[inline(always)] - pub fn set_dbg(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 7usize)) | (((val as u32) & 0x01) << 7usize); - } -} -impl Default for Otp { - #[inline(always)] - fn default() -> Otp { - Otp(0) - } -} -#[doc = "Control whether debugger, DMA, core 0 and core 1 can access PADS_BANK0, and at what security/privilege levels they can do so. Defaults to Secure access from any master. This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set."] -#[repr(transparent)] -#[derive(Copy, Clone, Eq, PartialEq)] -pub struct PadsBank0(pub u32); -impl PadsBank0 { - #[doc = "If 1, and NSP is also set, PADS_BANK0 can be accessed from a Non-secure, Unprivileged context. This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set."] - #[inline(always)] - pub const fn nsu(&self) -> bool { - let val = (self.0 >> 0usize) & 0x01; - val != 0 - } - #[doc = "If 1, and NSP is also set, PADS_BANK0 can be accessed from a Non-secure, Unprivileged context. This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set."] - #[inline(always)] - pub fn set_nsu(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize); - } - #[doc = "If 1, PADS_BANK0 can be accessed from a Non-secure, Privileged context."] - #[inline(always)] - pub const fn nsp(&self) -> bool { - let val = (self.0 >> 1usize) & 0x01; - val != 0 - } - #[doc = "If 1, PADS_BANK0 can be accessed from a Non-secure, Privileged context."] - #[inline(always)] - pub fn set_nsp(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize); - } - #[doc = "If 1, and SP is also set, PADS_BANK0 can be accessed from a Secure, Unprivileged context."] - #[inline(always)] - pub const fn su(&self) -> bool { - let val = (self.0 >> 2usize) & 0x01; - val != 0 - } - #[doc = "If 1, and SP is also set, PADS_BANK0 can be accessed from a Secure, Unprivileged context."] - #[inline(always)] - pub fn set_su(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 2usize)) | (((val as u32) & 0x01) << 2usize); - } - #[doc = "If 1, PADS_BANK0 can be accessed from a Secure, Privileged context."] - #[inline(always)] - pub const fn sp(&self) -> bool { - let val = (self.0 >> 3usize) & 0x01; - val != 0 - } - #[doc = "If 1, PADS_BANK0 can be accessed from a Secure, Privileged context."] - #[inline(always)] - pub fn set_sp(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 3usize)) | (((val as u32) & 0x01) << 3usize); - } - #[doc = "If 1, PADS_BANK0 can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] - #[inline(always)] - pub const fn core0(&self) -> bool { - let val = (self.0 >> 4usize) & 0x01; - val != 0 - } - #[doc = "If 1, PADS_BANK0 can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] - #[inline(always)] - pub fn set_core0(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 4usize)) | (((val as u32) & 0x01) << 4usize); - } - #[doc = "If 1, PADS_BANK0 can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] - #[inline(always)] - pub const fn core1(&self) -> bool { - let val = (self.0 >> 5usize) & 0x01; - val != 0 - } - #[doc = "If 1, PADS_BANK0 can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] - #[inline(always)] - pub fn set_core1(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 5usize)) | (((val as u32) & 0x01) << 5usize); - } - #[doc = "If 1, PADS_BANK0 can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] - #[inline(always)] - pub const fn dma(&self) -> bool { - let val = (self.0 >> 6usize) & 0x01; - val != 0 - } - #[doc = "If 1, PADS_BANK0 can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] - #[inline(always)] - pub fn set_dma(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 6usize)) | (((val as u32) & 0x01) << 6usize); - } - #[doc = "If 1, PADS_BANK0 can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] - #[inline(always)] - pub const fn dbg(&self) -> bool { - let val = (self.0 >> 7usize) & 0x01; - val != 0 - } - #[doc = "If 1, PADS_BANK0 can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] - #[inline(always)] - pub fn set_dbg(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 7usize)) | (((val as u32) & 0x01) << 7usize); - } -} -impl Default for PadsBank0 { - #[inline(always)] - fn default() -> PadsBank0 { - PadsBank0(0) - } -} -#[doc = "Control whether debugger, DMA, core 0 and core 1 can access PADS_QSPI, and at what security/privilege levels they can do so. Defaults to Secure access from any master. This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set."] -#[repr(transparent)] -#[derive(Copy, Clone, Eq, PartialEq)] -pub struct PadsQspi(pub u32); -impl PadsQspi { - #[doc = "If 1, and NSP is also set, PADS_QSPI can be accessed from a Non-secure, Unprivileged context. This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set."] - #[inline(always)] - pub const fn nsu(&self) -> bool { - let val = (self.0 >> 0usize) & 0x01; - val != 0 - } - #[doc = "If 1, and NSP is also set, PADS_QSPI can be accessed from a Non-secure, Unprivileged context. This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set."] - #[inline(always)] - pub fn set_nsu(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize); - } - #[doc = "If 1, PADS_QSPI can be accessed from a Non-secure, Privileged context."] - #[inline(always)] - pub const fn nsp(&self) -> bool { - let val = (self.0 >> 1usize) & 0x01; - val != 0 - } - #[doc = "If 1, PADS_QSPI can be accessed from a Non-secure, Privileged context."] - #[inline(always)] - pub fn set_nsp(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize); - } - #[doc = "If 1, and SP is also set, PADS_QSPI can be accessed from a Secure, Unprivileged context."] - #[inline(always)] - pub const fn su(&self) -> bool { - let val = (self.0 >> 2usize) & 0x01; - val != 0 - } - #[doc = "If 1, and SP is also set, PADS_QSPI can be accessed from a Secure, Unprivileged context."] - #[inline(always)] - pub fn set_su(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 2usize)) | (((val as u32) & 0x01) << 2usize); - } - #[doc = "If 1, PADS_QSPI can be accessed from a Secure, Privileged context."] - #[inline(always)] - pub const fn sp(&self) -> bool { - let val = (self.0 >> 3usize) & 0x01; - val != 0 - } - #[doc = "If 1, PADS_QSPI can be accessed from a Secure, Privileged context."] - #[inline(always)] - pub fn set_sp(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 3usize)) | (((val as u32) & 0x01) << 3usize); - } - #[doc = "If 1, PADS_QSPI can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] - #[inline(always)] - pub const fn core0(&self) -> bool { - let val = (self.0 >> 4usize) & 0x01; - val != 0 - } - #[doc = "If 1, PADS_QSPI can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] - #[inline(always)] - pub fn set_core0(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 4usize)) | (((val as u32) & 0x01) << 4usize); - } - #[doc = "If 1, PADS_QSPI can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] - #[inline(always)] - pub const fn core1(&self) -> bool { - let val = (self.0 >> 5usize) & 0x01; - val != 0 - } - #[doc = "If 1, PADS_QSPI can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] - #[inline(always)] - pub fn set_core1(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 5usize)) | (((val as u32) & 0x01) << 5usize); - } - #[doc = "If 1, PADS_QSPI can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] - #[inline(always)] - pub const fn dma(&self) -> bool { - let val = (self.0 >> 6usize) & 0x01; - val != 0 - } - #[doc = "If 1, PADS_QSPI can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] - #[inline(always)] - pub fn set_dma(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 6usize)) | (((val as u32) & 0x01) << 6usize); - } - #[doc = "If 1, PADS_QSPI can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] - #[inline(always)] - pub const fn dbg(&self) -> bool { - let val = (self.0 >> 7usize) & 0x01; - val != 0 - } - #[doc = "If 1, PADS_QSPI can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] - #[inline(always)] - pub fn set_dbg(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 7usize)) | (((val as u32) & 0x01) << 7usize); - } -} -impl Default for PadsQspi { - #[inline(always)] - fn default() -> PadsQspi { - PadsQspi(0) - } -} -#[doc = "Control whether debugger, DMA, core 0 and core 1 can access PIO0, and at what security/privilege levels they can do so. Defaults to Secure access from any master. This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set."] -#[repr(transparent)] -#[derive(Copy, Clone, Eq, PartialEq)] -pub struct Pio0(pub u32); -impl Pio0 { - #[doc = "If 1, and NSP is also set, PIO0 can be accessed from a Non-secure, Unprivileged context. This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set."] - #[inline(always)] - pub const fn nsu(&self) -> bool { - let val = (self.0 >> 0usize) & 0x01; - val != 0 - } - #[doc = "If 1, and NSP is also set, PIO0 can be accessed from a Non-secure, Unprivileged context. This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set."] - #[inline(always)] - pub fn set_nsu(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize); - } - #[doc = "If 1, PIO0 can be accessed from a Non-secure, Privileged context."] - #[inline(always)] - pub const fn nsp(&self) -> bool { - let val = (self.0 >> 1usize) & 0x01; - val != 0 - } - #[doc = "If 1, PIO0 can be accessed from a Non-secure, Privileged context."] - #[inline(always)] - pub fn set_nsp(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize); - } - #[doc = "If 1, and SP is also set, PIO0 can be accessed from a Secure, Unprivileged context."] - #[inline(always)] - pub const fn su(&self) -> bool { - let val = (self.0 >> 2usize) & 0x01; - val != 0 - } - #[doc = "If 1, and SP is also set, PIO0 can be accessed from a Secure, Unprivileged context."] - #[inline(always)] - pub fn set_su(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 2usize)) | (((val as u32) & 0x01) << 2usize); - } - #[doc = "If 1, PIO0 can be accessed from a Secure, Privileged context."] - #[inline(always)] - pub const fn sp(&self) -> bool { - let val = (self.0 >> 3usize) & 0x01; - val != 0 - } - #[doc = "If 1, PIO0 can be accessed from a Secure, Privileged context."] - #[inline(always)] - pub fn set_sp(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 3usize)) | (((val as u32) & 0x01) << 3usize); - } - #[doc = "If 1, PIO0 can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] - #[inline(always)] - pub const fn core0(&self) -> bool { - let val = (self.0 >> 4usize) & 0x01; - val != 0 - } - #[doc = "If 1, PIO0 can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] - #[inline(always)] - pub fn set_core0(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 4usize)) | (((val as u32) & 0x01) << 4usize); - } - #[doc = "If 1, PIO0 can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] - #[inline(always)] - pub const fn core1(&self) -> bool { - let val = (self.0 >> 5usize) & 0x01; - val != 0 - } - #[doc = "If 1, PIO0 can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] - #[inline(always)] - pub fn set_core1(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 5usize)) | (((val as u32) & 0x01) << 5usize); - } - #[doc = "If 1, PIO0 can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] - #[inline(always)] - pub const fn dma(&self) -> bool { - let val = (self.0 >> 6usize) & 0x01; - val != 0 - } - #[doc = "If 1, PIO0 can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] - #[inline(always)] - pub fn set_dma(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 6usize)) | (((val as u32) & 0x01) << 6usize); - } - #[doc = "If 1, PIO0 can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] - #[inline(always)] - pub const fn dbg(&self) -> bool { - let val = (self.0 >> 7usize) & 0x01; - val != 0 - } - #[doc = "If 1, PIO0 can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] - #[inline(always)] - pub fn set_dbg(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 7usize)) | (((val as u32) & 0x01) << 7usize); - } -} -impl Default for Pio0 { - #[inline(always)] - fn default() -> Pio0 { - Pio0(0) - } -} -#[doc = "Control whether debugger, DMA, core 0 and core 1 can access PIO1, and at what security/privilege levels they can do so. Defaults to Secure access from any master. This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set."] -#[repr(transparent)] -#[derive(Copy, Clone, Eq, PartialEq)] -pub struct Pio1(pub u32); -impl Pio1 { - #[doc = "If 1, and NSP is also set, PIO1 can be accessed from a Non-secure, Unprivileged context. This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set."] - #[inline(always)] - pub const fn nsu(&self) -> bool { - let val = (self.0 >> 0usize) & 0x01; - val != 0 - } - #[doc = "If 1, and NSP is also set, PIO1 can be accessed from a Non-secure, Unprivileged context. This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set."] - #[inline(always)] - pub fn set_nsu(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize); - } - #[doc = "If 1, PIO1 can be accessed from a Non-secure, Privileged context."] - #[inline(always)] - pub const fn nsp(&self) -> bool { - let val = (self.0 >> 1usize) & 0x01; - val != 0 - } - #[doc = "If 1, PIO1 can be accessed from a Non-secure, Privileged context."] - #[inline(always)] - pub fn set_nsp(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize); - } - #[doc = "If 1, and SP is also set, PIO1 can be accessed from a Secure, Unprivileged context."] - #[inline(always)] - pub const fn su(&self) -> bool { - let val = (self.0 >> 2usize) & 0x01; - val != 0 - } - #[doc = "If 1, and SP is also set, PIO1 can be accessed from a Secure, Unprivileged context."] - #[inline(always)] - pub fn set_su(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 2usize)) | (((val as u32) & 0x01) << 2usize); - } - #[doc = "If 1, PIO1 can be accessed from a Secure, Privileged context."] - #[inline(always)] - pub const fn sp(&self) -> bool { - let val = (self.0 >> 3usize) & 0x01; - val != 0 - } - #[doc = "If 1, PIO1 can be accessed from a Secure, Privileged context."] - #[inline(always)] - pub fn set_sp(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 3usize)) | (((val as u32) & 0x01) << 3usize); - } - #[doc = "If 1, PIO1 can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] - #[inline(always)] - pub const fn core0(&self) -> bool { - let val = (self.0 >> 4usize) & 0x01; - val != 0 - } - #[doc = "If 1, PIO1 can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] - #[inline(always)] - pub fn set_core0(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 4usize)) | (((val as u32) & 0x01) << 4usize); - } - #[doc = "If 1, PIO1 can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] - #[inline(always)] - pub const fn core1(&self) -> bool { - let val = (self.0 >> 5usize) & 0x01; - val != 0 - } - #[doc = "If 1, PIO1 can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] - #[inline(always)] - pub fn set_core1(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 5usize)) | (((val as u32) & 0x01) << 5usize); - } - #[doc = "If 1, PIO1 can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] - #[inline(always)] - pub const fn dma(&self) -> bool { - let val = (self.0 >> 6usize) & 0x01; - val != 0 - } - #[doc = "If 1, PIO1 can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] - #[inline(always)] - pub fn set_dma(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 6usize)) | (((val as u32) & 0x01) << 6usize); - } - #[doc = "If 1, PIO1 can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] - #[inline(always)] - pub const fn dbg(&self) -> bool { - let val = (self.0 >> 7usize) & 0x01; - val != 0 - } - #[doc = "If 1, PIO1 can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] - #[inline(always)] - pub fn set_dbg(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 7usize)) | (((val as u32) & 0x01) << 7usize); - } -} -impl Default for Pio1 { - #[inline(always)] - fn default() -> Pio1 { - Pio1(0) - } -} -#[doc = "Control whether debugger, DMA, core 0 and core 1 can access PIO2, and at what security/privilege levels they can do so. Defaults to Secure access from any master. This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set."] -#[repr(transparent)] -#[derive(Copy, Clone, Eq, PartialEq)] -pub struct Pio2(pub u32); -impl Pio2 { - #[doc = "If 1, and NSP is also set, PIO2 can be accessed from a Non-secure, Unprivileged context. This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set."] - #[inline(always)] - pub const fn nsu(&self) -> bool { - let val = (self.0 >> 0usize) & 0x01; - val != 0 - } - #[doc = "If 1, and NSP is also set, PIO2 can be accessed from a Non-secure, Unprivileged context. This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set."] - #[inline(always)] - pub fn set_nsu(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize); - } - #[doc = "If 1, PIO2 can be accessed from a Non-secure, Privileged context."] - #[inline(always)] - pub const fn nsp(&self) -> bool { - let val = (self.0 >> 1usize) & 0x01; - val != 0 - } - #[doc = "If 1, PIO2 can be accessed from a Non-secure, Privileged context."] - #[inline(always)] - pub fn set_nsp(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize); - } - #[doc = "If 1, and SP is also set, PIO2 can be accessed from a Secure, Unprivileged context."] - #[inline(always)] - pub const fn su(&self) -> bool { - let val = (self.0 >> 2usize) & 0x01; - val != 0 - } - #[doc = "If 1, and SP is also set, PIO2 can be accessed from a Secure, Unprivileged context."] - #[inline(always)] - pub fn set_su(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 2usize)) | (((val as u32) & 0x01) << 2usize); - } - #[doc = "If 1, PIO2 can be accessed from a Secure, Privileged context."] - #[inline(always)] - pub const fn sp(&self) -> bool { - let val = (self.0 >> 3usize) & 0x01; - val != 0 - } - #[doc = "If 1, PIO2 can be accessed from a Secure, Privileged context."] - #[inline(always)] - pub fn set_sp(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 3usize)) | (((val as u32) & 0x01) << 3usize); - } - #[doc = "If 1, PIO2 can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] - #[inline(always)] - pub const fn core0(&self) -> bool { - let val = (self.0 >> 4usize) & 0x01; - val != 0 - } - #[doc = "If 1, PIO2 can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] - #[inline(always)] - pub fn set_core0(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 4usize)) | (((val as u32) & 0x01) << 4usize); - } - #[doc = "If 1, PIO2 can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] - #[inline(always)] - pub const fn core1(&self) -> bool { - let val = (self.0 >> 5usize) & 0x01; - val != 0 - } - #[doc = "If 1, PIO2 can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] - #[inline(always)] - pub fn set_core1(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 5usize)) | (((val as u32) & 0x01) << 5usize); - } - #[doc = "If 1, PIO2 can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] - #[inline(always)] - pub const fn dma(&self) -> bool { - let val = (self.0 >> 6usize) & 0x01; - val != 0 - } - #[doc = "If 1, PIO2 can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] - #[inline(always)] - pub fn set_dma(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 6usize)) | (((val as u32) & 0x01) << 6usize); - } - #[doc = "If 1, PIO2 can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] - #[inline(always)] - pub const fn dbg(&self) -> bool { - let val = (self.0 >> 7usize) & 0x01; - val != 0 - } - #[doc = "If 1, PIO2 can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] - #[inline(always)] - pub fn set_dbg(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 7usize)) | (((val as u32) & 0x01) << 7usize); - } -} -impl Default for Pio2 { - #[inline(always)] - fn default() -> Pio2 { - Pio2(0) - } -} -#[doc = "Control whether debugger, DMA, core 0 and core 1 can access PLL_SYS, and at what security/privilege levels they can do so. Defaults to Secure, Privileged processor or debug access only. This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set."] -#[repr(transparent)] -#[derive(Copy, Clone, Eq, PartialEq)] -pub struct PllSys(pub u32); -impl PllSys { - #[doc = "If 1, and NSP is also set, PLL_SYS can be accessed from a Non-secure, Unprivileged context. This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set."] - #[inline(always)] - pub const fn nsu(&self) -> bool { - let val = (self.0 >> 0usize) & 0x01; - val != 0 - } - #[doc = "If 1, and NSP is also set, PLL_SYS can be accessed from a Non-secure, Unprivileged context. This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set."] - #[inline(always)] - pub fn set_nsu(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize); - } - #[doc = "If 1, PLL_SYS can be accessed from a Non-secure, Privileged context."] - #[inline(always)] - pub const fn nsp(&self) -> bool { - let val = (self.0 >> 1usize) & 0x01; - val != 0 - } - #[doc = "If 1, PLL_SYS can be accessed from a Non-secure, Privileged context."] - #[inline(always)] - pub fn set_nsp(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize); - } - #[doc = "If 1, and SP is also set, PLL_SYS can be accessed from a Secure, Unprivileged context."] - #[inline(always)] - pub const fn su(&self) -> bool { - let val = (self.0 >> 2usize) & 0x01; - val != 0 - } - #[doc = "If 1, and SP is also set, PLL_SYS can be accessed from a Secure, Unprivileged context."] - #[inline(always)] - pub fn set_su(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 2usize)) | (((val as u32) & 0x01) << 2usize); - } - #[doc = "If 1, PLL_SYS can be accessed from a Secure, Privileged context."] - #[inline(always)] - pub const fn sp(&self) -> bool { - let val = (self.0 >> 3usize) & 0x01; - val != 0 - } - #[doc = "If 1, PLL_SYS can be accessed from a Secure, Privileged context."] - #[inline(always)] - pub fn set_sp(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 3usize)) | (((val as u32) & 0x01) << 3usize); - } - #[doc = "If 1, PLL_SYS can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] - #[inline(always)] - pub const fn core0(&self) -> bool { - let val = (self.0 >> 4usize) & 0x01; - val != 0 - } - #[doc = "If 1, PLL_SYS can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] - #[inline(always)] - pub fn set_core0(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 4usize)) | (((val as u32) & 0x01) << 4usize); - } - #[doc = "If 1, PLL_SYS can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] - #[inline(always)] - pub const fn core1(&self) -> bool { - let val = (self.0 >> 5usize) & 0x01; - val != 0 - } - #[doc = "If 1, PLL_SYS can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] - #[inline(always)] - pub fn set_core1(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 5usize)) | (((val as u32) & 0x01) << 5usize); - } - #[doc = "If 1, PLL_SYS can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] - #[inline(always)] - pub const fn dma(&self) -> bool { - let val = (self.0 >> 6usize) & 0x01; - val != 0 - } - #[doc = "If 1, PLL_SYS can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] - #[inline(always)] - pub fn set_dma(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 6usize)) | (((val as u32) & 0x01) << 6usize); - } - #[doc = "If 1, PLL_SYS can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] - #[inline(always)] - pub const fn dbg(&self) -> bool { - let val = (self.0 >> 7usize) & 0x01; - val != 0 - } - #[doc = "If 1, PLL_SYS can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] - #[inline(always)] - pub fn set_dbg(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 7usize)) | (((val as u32) & 0x01) << 7usize); - } -} -impl Default for PllSys { - #[inline(always)] - fn default() -> PllSys { - PllSys(0) - } -} -#[doc = "Control whether debugger, DMA, core 0 and core 1 can access PLL_USB, and at what security/privilege levels they can do so. Defaults to Secure, Privileged processor or debug access only. This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set."] -#[repr(transparent)] -#[derive(Copy, Clone, Eq, PartialEq)] -pub struct PllUsb(pub u32); -impl PllUsb { - #[doc = "If 1, and NSP is also set, PLL_USB can be accessed from a Non-secure, Unprivileged context. This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set."] - #[inline(always)] - pub const fn nsu(&self) -> bool { - let val = (self.0 >> 0usize) & 0x01; - val != 0 - } - #[doc = "If 1, and NSP is also set, PLL_USB can be accessed from a Non-secure, Unprivileged context. This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set."] - #[inline(always)] - pub fn set_nsu(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize); - } - #[doc = "If 1, PLL_USB can be accessed from a Non-secure, Privileged context."] - #[inline(always)] - pub const fn nsp(&self) -> bool { - let val = (self.0 >> 1usize) & 0x01; - val != 0 - } - #[doc = "If 1, PLL_USB can be accessed from a Non-secure, Privileged context."] - #[inline(always)] - pub fn set_nsp(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize); - } - #[doc = "If 1, and SP is also set, PLL_USB can be accessed from a Secure, Unprivileged context."] - #[inline(always)] - pub const fn su(&self) -> bool { - let val = (self.0 >> 2usize) & 0x01; - val != 0 - } - #[doc = "If 1, and SP is also set, PLL_USB can be accessed from a Secure, Unprivileged context."] - #[inline(always)] - pub fn set_su(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 2usize)) | (((val as u32) & 0x01) << 2usize); - } - #[doc = "If 1, PLL_USB can be accessed from a Secure, Privileged context."] - #[inline(always)] - pub const fn sp(&self) -> bool { - let val = (self.0 >> 3usize) & 0x01; - val != 0 - } - #[doc = "If 1, PLL_USB can be accessed from a Secure, Privileged context."] - #[inline(always)] - pub fn set_sp(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 3usize)) | (((val as u32) & 0x01) << 3usize); - } - #[doc = "If 1, PLL_USB can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] - #[inline(always)] - pub const fn core0(&self) -> bool { - let val = (self.0 >> 4usize) & 0x01; - val != 0 - } - #[doc = "If 1, PLL_USB can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] - #[inline(always)] - pub fn set_core0(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 4usize)) | (((val as u32) & 0x01) << 4usize); - } - #[doc = "If 1, PLL_USB can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] - #[inline(always)] - pub const fn core1(&self) -> bool { - let val = (self.0 >> 5usize) & 0x01; - val != 0 - } - #[doc = "If 1, PLL_USB can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] - #[inline(always)] - pub fn set_core1(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 5usize)) | (((val as u32) & 0x01) << 5usize); - } - #[doc = "If 1, PLL_USB can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] - #[inline(always)] - pub const fn dma(&self) -> bool { - let val = (self.0 >> 6usize) & 0x01; - val != 0 - } - #[doc = "If 1, PLL_USB can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] - #[inline(always)] - pub fn set_dma(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 6usize)) | (((val as u32) & 0x01) << 6usize); - } - #[doc = "If 1, PLL_USB can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] - #[inline(always)] - pub const fn dbg(&self) -> bool { - let val = (self.0 >> 7usize) & 0x01; - val != 0 - } - #[doc = "If 1, PLL_USB can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] - #[inline(always)] - pub fn set_dbg(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 7usize)) | (((val as u32) & 0x01) << 7usize); - } -} -impl Default for PllUsb { - #[inline(always)] - fn default() -> PllUsb { - PllUsb(0) - } -} -#[doc = "Control whether debugger, DMA, core 0 and core 1 can access POWMAN, and at what security/privilege levels they can do so. Defaults to Secure, Privileged processor or debug access only. This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set."] -#[repr(transparent)] -#[derive(Copy, Clone, Eq, PartialEq)] -pub struct Powman(pub u32); -impl Powman { - #[doc = "If 1, and NSP is also set, POWMAN can be accessed from a Non-secure, Unprivileged context. This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set."] - #[inline(always)] - pub const fn nsu(&self) -> bool { - let val = (self.0 >> 0usize) & 0x01; - val != 0 - } - #[doc = "If 1, and NSP is also set, POWMAN can be accessed from a Non-secure, Unprivileged context. This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set."] - #[inline(always)] - pub fn set_nsu(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize); - } - #[doc = "If 1, POWMAN can be accessed from a Non-secure, Privileged context."] - #[inline(always)] - pub const fn nsp(&self) -> bool { - let val = (self.0 >> 1usize) & 0x01; - val != 0 - } - #[doc = "If 1, POWMAN can be accessed from a Non-secure, Privileged context."] - #[inline(always)] - pub fn set_nsp(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize); - } - #[doc = "If 1, and SP is also set, POWMAN can be accessed from a Secure, Unprivileged context."] - #[inline(always)] - pub const fn su(&self) -> bool { - let val = (self.0 >> 2usize) & 0x01; - val != 0 - } - #[doc = "If 1, and SP is also set, POWMAN can be accessed from a Secure, Unprivileged context."] - #[inline(always)] - pub fn set_su(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 2usize)) | (((val as u32) & 0x01) << 2usize); - } - #[doc = "If 1, POWMAN can be accessed from a Secure, Privileged context."] - #[inline(always)] - pub const fn sp(&self) -> bool { - let val = (self.0 >> 3usize) & 0x01; - val != 0 - } - #[doc = "If 1, POWMAN can be accessed from a Secure, Privileged context."] - #[inline(always)] - pub fn set_sp(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 3usize)) | (((val as u32) & 0x01) << 3usize); - } - #[doc = "If 1, POWMAN can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] - #[inline(always)] - pub const fn core0(&self) -> bool { - let val = (self.0 >> 4usize) & 0x01; - val != 0 - } - #[doc = "If 1, POWMAN can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] - #[inline(always)] - pub fn set_core0(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 4usize)) | (((val as u32) & 0x01) << 4usize); - } - #[doc = "If 1, POWMAN can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] - #[inline(always)] - pub const fn core1(&self) -> bool { - let val = (self.0 >> 5usize) & 0x01; - val != 0 - } - #[doc = "If 1, POWMAN can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] - #[inline(always)] - pub fn set_core1(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 5usize)) | (((val as u32) & 0x01) << 5usize); - } - #[doc = "If 1, POWMAN can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] - #[inline(always)] - pub const fn dma(&self) -> bool { - let val = (self.0 >> 6usize) & 0x01; - val != 0 - } - #[doc = "If 1, POWMAN can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] - #[inline(always)] - pub fn set_dma(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 6usize)) | (((val as u32) & 0x01) << 6usize); - } - #[doc = "If 1, POWMAN can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] - #[inline(always)] - pub const fn dbg(&self) -> bool { - let val = (self.0 >> 7usize) & 0x01; - val != 0 - } - #[doc = "If 1, POWMAN can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] - #[inline(always)] - pub fn set_dbg(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 7usize)) | (((val as u32) & 0x01) << 7usize); - } -} -impl Default for Powman { - #[inline(always)] - fn default() -> Powman { - Powman(0) - } -} -#[doc = "Control whether debugger, DMA, core 0 and core 1 can access PWM, and at what security/privilege levels they can do so. Defaults to Secure access from any master. This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set."] -#[repr(transparent)] -#[derive(Copy, Clone, Eq, PartialEq)] -pub struct Pwm(pub u32); -impl Pwm { - #[doc = "If 1, and NSP is also set, PWM can be accessed from a Non-secure, Unprivileged context. This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set."] - #[inline(always)] - pub const fn nsu(&self) -> bool { - let val = (self.0 >> 0usize) & 0x01; - val != 0 - } - #[doc = "If 1, and NSP is also set, PWM can be accessed from a Non-secure, Unprivileged context. This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set."] - #[inline(always)] - pub fn set_nsu(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize); - } - #[doc = "If 1, PWM can be accessed from a Non-secure, Privileged context."] - #[inline(always)] - pub const fn nsp(&self) -> bool { - let val = (self.0 >> 1usize) & 0x01; - val != 0 - } - #[doc = "If 1, PWM can be accessed from a Non-secure, Privileged context."] - #[inline(always)] - pub fn set_nsp(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize); - } - #[doc = "If 1, and SP is also set, PWM can be accessed from a Secure, Unprivileged context."] - #[inline(always)] - pub const fn su(&self) -> bool { - let val = (self.0 >> 2usize) & 0x01; - val != 0 - } - #[doc = "If 1, and SP is also set, PWM can be accessed from a Secure, Unprivileged context."] - #[inline(always)] - pub fn set_su(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 2usize)) | (((val as u32) & 0x01) << 2usize); - } - #[doc = "If 1, PWM can be accessed from a Secure, Privileged context."] - #[inline(always)] - pub const fn sp(&self) -> bool { - let val = (self.0 >> 3usize) & 0x01; - val != 0 - } - #[doc = "If 1, PWM can be accessed from a Secure, Privileged context."] - #[inline(always)] - pub fn set_sp(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 3usize)) | (((val as u32) & 0x01) << 3usize); - } - #[doc = "If 1, PWM can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] - #[inline(always)] - pub const fn core0(&self) -> bool { - let val = (self.0 >> 4usize) & 0x01; - val != 0 - } - #[doc = "If 1, PWM can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] - #[inline(always)] - pub fn set_core0(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 4usize)) | (((val as u32) & 0x01) << 4usize); - } - #[doc = "If 1, PWM can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] - #[inline(always)] - pub const fn core1(&self) -> bool { - let val = (self.0 >> 5usize) & 0x01; - val != 0 - } - #[doc = "If 1, PWM can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] - #[inline(always)] - pub fn set_core1(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 5usize)) | (((val as u32) & 0x01) << 5usize); - } - #[doc = "If 1, PWM can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] - #[inline(always)] - pub const fn dma(&self) -> bool { - let val = (self.0 >> 6usize) & 0x01; - val != 0 - } - #[doc = "If 1, PWM can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] - #[inline(always)] - pub fn set_dma(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 6usize)) | (((val as u32) & 0x01) << 6usize); - } - #[doc = "If 1, PWM can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] - #[inline(always)] - pub const fn dbg(&self) -> bool { - let val = (self.0 >> 7usize) & 0x01; - val != 0 - } - #[doc = "If 1, PWM can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] - #[inline(always)] - pub fn set_dbg(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 7usize)) | (((val as u32) & 0x01) << 7usize); - } -} -impl Default for Pwm { - #[inline(always)] - fn default() -> Pwm { - Pwm(0) - } -} -#[doc = "Control whether debugger, DMA, core 0 and core 1 can access RESETS, and at what security/privilege levels they can do so. Defaults to Secure access from any master. This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set."] -#[repr(transparent)] -#[derive(Copy, Clone, Eq, PartialEq)] -pub struct Resets(pub u32); -impl Resets { - #[doc = "If 1, and NSP is also set, RESETS can be accessed from a Non-secure, Unprivileged context. This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set."] - #[inline(always)] - pub const fn nsu(&self) -> bool { - let val = (self.0 >> 0usize) & 0x01; - val != 0 - } - #[doc = "If 1, and NSP is also set, RESETS can be accessed from a Non-secure, Unprivileged context. This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set."] - #[inline(always)] - pub fn set_nsu(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize); - } - #[doc = "If 1, RESETS can be accessed from a Non-secure, Privileged context."] - #[inline(always)] - pub const fn nsp(&self) -> bool { - let val = (self.0 >> 1usize) & 0x01; - val != 0 - } - #[doc = "If 1, RESETS can be accessed from a Non-secure, Privileged context."] - #[inline(always)] - pub fn set_nsp(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize); - } - #[doc = "If 1, and SP is also set, RESETS can be accessed from a Secure, Unprivileged context."] - #[inline(always)] - pub const fn su(&self) -> bool { - let val = (self.0 >> 2usize) & 0x01; - val != 0 - } - #[doc = "If 1, and SP is also set, RESETS can be accessed from a Secure, Unprivileged context."] - #[inline(always)] - pub fn set_su(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 2usize)) | (((val as u32) & 0x01) << 2usize); - } - #[doc = "If 1, RESETS can be accessed from a Secure, Privileged context."] - #[inline(always)] - pub const fn sp(&self) -> bool { - let val = (self.0 >> 3usize) & 0x01; - val != 0 - } - #[doc = "If 1, RESETS can be accessed from a Secure, Privileged context."] - #[inline(always)] - pub fn set_sp(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 3usize)) | (((val as u32) & 0x01) << 3usize); - } - #[doc = "If 1, RESETS can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] - #[inline(always)] - pub const fn core0(&self) -> bool { - let val = (self.0 >> 4usize) & 0x01; - val != 0 - } - #[doc = "If 1, RESETS can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] - #[inline(always)] - pub fn set_core0(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 4usize)) | (((val as u32) & 0x01) << 4usize); - } - #[doc = "If 1, RESETS can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] - #[inline(always)] - pub const fn core1(&self) -> bool { - let val = (self.0 >> 5usize) & 0x01; - val != 0 - } - #[doc = "If 1, RESETS can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] - #[inline(always)] - pub fn set_core1(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 5usize)) | (((val as u32) & 0x01) << 5usize); - } - #[doc = "If 1, RESETS can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] - #[inline(always)] - pub const fn dma(&self) -> bool { - let val = (self.0 >> 6usize) & 0x01; - val != 0 - } - #[doc = "If 1, RESETS can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] - #[inline(always)] - pub fn set_dma(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 6usize)) | (((val as u32) & 0x01) << 6usize); - } - #[doc = "If 1, RESETS can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] - #[inline(always)] - pub const fn dbg(&self) -> bool { - let val = (self.0 >> 7usize) & 0x01; - val != 0 - } - #[doc = "If 1, RESETS can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] - #[inline(always)] - pub fn set_dbg(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 7usize)) | (((val as u32) & 0x01) << 7usize); - } -} -impl Default for Resets { - #[inline(always)] - fn default() -> Resets { - Resets(0) - } -} -#[doc = "Control whether debugger, DMA, core 0 and core 1 can access ROM, and at what security/privilege levels they can do so. Defaults to fully open access. This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set."] -#[repr(transparent)] -#[derive(Copy, Clone, Eq, PartialEq)] -pub struct Rom(pub u32); -impl Rom { - #[doc = "If 1, and NSP is also set, ROM can be accessed from a Non-secure, Unprivileged context. This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set."] - #[inline(always)] - pub const fn nsu(&self) -> bool { - let val = (self.0 >> 0usize) & 0x01; - val != 0 - } - #[doc = "If 1, and NSP is also set, ROM can be accessed from a Non-secure, Unprivileged context. This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set."] - #[inline(always)] - pub fn set_nsu(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize); - } - #[doc = "If 1, ROM can be accessed from a Non-secure, Privileged context."] - #[inline(always)] - pub const fn nsp(&self) -> bool { - let val = (self.0 >> 1usize) & 0x01; - val != 0 - } - #[doc = "If 1, ROM can be accessed from a Non-secure, Privileged context."] - #[inline(always)] - pub fn set_nsp(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize); - } - #[doc = "If 1, and SP is also set, ROM can be accessed from a Secure, Unprivileged context."] - #[inline(always)] - pub const fn su(&self) -> bool { - let val = (self.0 >> 2usize) & 0x01; - val != 0 - } - #[doc = "If 1, and SP is also set, ROM can be accessed from a Secure, Unprivileged context."] - #[inline(always)] - pub fn set_su(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 2usize)) | (((val as u32) & 0x01) << 2usize); - } - #[doc = "If 1, ROM can be accessed from a Secure, Privileged context."] - #[inline(always)] - pub const fn sp(&self) -> bool { - let val = (self.0 >> 3usize) & 0x01; - val != 0 - } - #[doc = "If 1, ROM can be accessed from a Secure, Privileged context."] - #[inline(always)] - pub fn set_sp(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 3usize)) | (((val as u32) & 0x01) << 3usize); - } - #[doc = "If 1, ROM can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] - #[inline(always)] - pub const fn core0(&self) -> bool { - let val = (self.0 >> 4usize) & 0x01; - val != 0 - } - #[doc = "If 1, ROM can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] - #[inline(always)] - pub fn set_core0(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 4usize)) | (((val as u32) & 0x01) << 4usize); - } - #[doc = "If 1, ROM can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] - #[inline(always)] - pub const fn core1(&self) -> bool { - let val = (self.0 >> 5usize) & 0x01; - val != 0 - } - #[doc = "If 1, ROM can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] - #[inline(always)] - pub fn set_core1(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 5usize)) | (((val as u32) & 0x01) << 5usize); - } - #[doc = "If 1, ROM can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] - #[inline(always)] - pub const fn dma(&self) -> bool { - let val = (self.0 >> 6usize) & 0x01; - val != 0 - } - #[doc = "If 1, ROM can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] - #[inline(always)] - pub fn set_dma(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 6usize)) | (((val as u32) & 0x01) << 6usize); - } - #[doc = "If 1, ROM can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] - #[inline(always)] - pub const fn dbg(&self) -> bool { - let val = (self.0 >> 7usize) & 0x01; - val != 0 - } - #[doc = "If 1, ROM can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] - #[inline(always)] - pub fn set_dbg(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 7usize)) | (((val as u32) & 0x01) << 7usize); - } -} -impl Default for Rom { - #[inline(always)] - fn default() -> Rom { - Rom(0) - } -} -#[doc = "Control whether debugger, DMA, core 0 and core 1 can access ROSC, and at what security/privilege levels they can do so. Defaults to Secure, Privileged processor or debug access only. This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set."] -#[repr(transparent)] -#[derive(Copy, Clone, Eq, PartialEq)] -pub struct Rosc(pub u32); -impl Rosc { - #[doc = "If 1, and NSP is also set, ROSC can be accessed from a Non-secure, Unprivileged context. This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set."] - #[inline(always)] - pub const fn nsu(&self) -> bool { - let val = (self.0 >> 0usize) & 0x01; - val != 0 - } - #[doc = "If 1, and NSP is also set, ROSC can be accessed from a Non-secure, Unprivileged context. This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set."] - #[inline(always)] - pub fn set_nsu(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize); - } - #[doc = "If 1, ROSC can be accessed from a Non-secure, Privileged context."] - #[inline(always)] - pub const fn nsp(&self) -> bool { - let val = (self.0 >> 1usize) & 0x01; - val != 0 - } - #[doc = "If 1, ROSC can be accessed from a Non-secure, Privileged context."] - #[inline(always)] - pub fn set_nsp(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize); - } - #[doc = "If 1, and SP is also set, ROSC can be accessed from a Secure, Unprivileged context."] - #[inline(always)] - pub const fn su(&self) -> bool { - let val = (self.0 >> 2usize) & 0x01; - val != 0 - } - #[doc = "If 1, and SP is also set, ROSC can be accessed from a Secure, Unprivileged context."] - #[inline(always)] - pub fn set_su(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 2usize)) | (((val as u32) & 0x01) << 2usize); - } - #[doc = "If 1, ROSC can be accessed from a Secure, Privileged context."] - #[inline(always)] - pub const fn sp(&self) -> bool { - let val = (self.0 >> 3usize) & 0x01; - val != 0 - } - #[doc = "If 1, ROSC can be accessed from a Secure, Privileged context."] - #[inline(always)] - pub fn set_sp(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 3usize)) | (((val as u32) & 0x01) << 3usize); - } - #[doc = "If 1, ROSC can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] - #[inline(always)] - pub const fn core0(&self) -> bool { - let val = (self.0 >> 4usize) & 0x01; - val != 0 - } - #[doc = "If 1, ROSC can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] - #[inline(always)] - pub fn set_core0(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 4usize)) | (((val as u32) & 0x01) << 4usize); - } - #[doc = "If 1, ROSC can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] - #[inline(always)] - pub const fn core1(&self) -> bool { - let val = (self.0 >> 5usize) & 0x01; - val != 0 - } - #[doc = "If 1, ROSC can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] - #[inline(always)] - pub fn set_core1(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 5usize)) | (((val as u32) & 0x01) << 5usize); - } - #[doc = "If 1, ROSC can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] - #[inline(always)] - pub const fn dma(&self) -> bool { - let val = (self.0 >> 6usize) & 0x01; - val != 0 - } - #[doc = "If 1, ROSC can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] - #[inline(always)] - pub fn set_dma(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 6usize)) | (((val as u32) & 0x01) << 6usize); - } - #[doc = "If 1, ROSC can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] - #[inline(always)] - pub const fn dbg(&self) -> bool { - let val = (self.0 >> 7usize) & 0x01; - val != 0 - } - #[doc = "If 1, ROSC can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] - #[inline(always)] - pub fn set_dbg(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 7usize)) | (((val as u32) & 0x01) << 7usize); - } -} -impl Default for Rosc { - #[inline(always)] - fn default() -> Rosc { - Rosc(0) - } -} -#[doc = "Control whether debugger, DMA, core 0 and core 1 can access RSM, and at what security/privilege levels they can do so. Defaults to Secure, Privileged processor or debug access only. This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set."] -#[repr(transparent)] -#[derive(Copy, Clone, Eq, PartialEq)] -pub struct Rsm(pub u32); -impl Rsm { - #[doc = "If 1, and NSP is also set, RSM can be accessed from a Non-secure, Unprivileged context. This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set."] - #[inline(always)] - pub const fn nsu(&self) -> bool { - let val = (self.0 >> 0usize) & 0x01; - val != 0 - } - #[doc = "If 1, and NSP is also set, RSM can be accessed from a Non-secure, Unprivileged context. This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set."] - #[inline(always)] - pub fn set_nsu(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize); - } - #[doc = "If 1, RSM can be accessed from a Non-secure, Privileged context."] - #[inline(always)] - pub const fn nsp(&self) -> bool { - let val = (self.0 >> 1usize) & 0x01; - val != 0 - } - #[doc = "If 1, RSM can be accessed from a Non-secure, Privileged context."] - #[inline(always)] - pub fn set_nsp(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize); - } - #[doc = "If 1, and SP is also set, RSM can be accessed from a Secure, Unprivileged context."] - #[inline(always)] - pub const fn su(&self) -> bool { - let val = (self.0 >> 2usize) & 0x01; - val != 0 - } - #[doc = "If 1, and SP is also set, RSM can be accessed from a Secure, Unprivileged context."] - #[inline(always)] - pub fn set_su(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 2usize)) | (((val as u32) & 0x01) << 2usize); - } - #[doc = "If 1, RSM can be accessed from a Secure, Privileged context."] - #[inline(always)] - pub const fn sp(&self) -> bool { - let val = (self.0 >> 3usize) & 0x01; - val != 0 - } - #[doc = "If 1, RSM can be accessed from a Secure, Privileged context."] - #[inline(always)] - pub fn set_sp(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 3usize)) | (((val as u32) & 0x01) << 3usize); - } - #[doc = "If 1, RSM can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] - #[inline(always)] - pub const fn core0(&self) -> bool { - let val = (self.0 >> 4usize) & 0x01; - val != 0 - } - #[doc = "If 1, RSM can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] - #[inline(always)] - pub fn set_core0(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 4usize)) | (((val as u32) & 0x01) << 4usize); - } - #[doc = "If 1, RSM can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] - #[inline(always)] - pub const fn core1(&self) -> bool { - let val = (self.0 >> 5usize) & 0x01; - val != 0 - } - #[doc = "If 1, RSM can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] - #[inline(always)] - pub fn set_core1(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 5usize)) | (((val as u32) & 0x01) << 5usize); - } - #[doc = "If 1, RSM can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] - #[inline(always)] - pub const fn dma(&self) -> bool { - let val = (self.0 >> 6usize) & 0x01; - val != 0 - } - #[doc = "If 1, RSM can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] - #[inline(always)] - pub fn set_dma(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 6usize)) | (((val as u32) & 0x01) << 6usize); - } - #[doc = "If 1, RSM can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] - #[inline(always)] - pub const fn dbg(&self) -> bool { - let val = (self.0 >> 7usize) & 0x01; - val != 0 - } - #[doc = "If 1, RSM can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] - #[inline(always)] - pub fn set_dbg(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 7usize)) | (((val as u32) & 0x01) << 7usize); - } -} -impl Default for Rsm { - #[inline(always)] - fn default() -> Rsm { - Rsm(0) - } -} -#[doc = "Control whether debugger, DMA, core 0 and core 1 can access SHA256, and at what security/privilege levels they can do so. Defaults to Secure, Privileged access only. This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set."] -#[repr(transparent)] -#[derive(Copy, Clone, Eq, PartialEq)] -pub struct Sha256(pub u32); -impl Sha256 { - #[doc = "If 1, and NSP is also set, SHA256 can be accessed from a Non-secure, Unprivileged context. This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set."] - #[inline(always)] - pub const fn nsu(&self) -> bool { - let val = (self.0 >> 0usize) & 0x01; - val != 0 - } - #[doc = "If 1, and NSP is also set, SHA256 can be accessed from a Non-secure, Unprivileged context. This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set."] - #[inline(always)] - pub fn set_nsu(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize); - } - #[doc = "If 1, SHA256 can be accessed from a Non-secure, Privileged context."] - #[inline(always)] - pub const fn nsp(&self) -> bool { - let val = (self.0 >> 1usize) & 0x01; - val != 0 - } - #[doc = "If 1, SHA256 can be accessed from a Non-secure, Privileged context."] - #[inline(always)] - pub fn set_nsp(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize); - } - #[doc = "If 1, and SP is also set, SHA256 can be accessed from a Secure, Unprivileged context."] - #[inline(always)] - pub const fn su(&self) -> bool { - let val = (self.0 >> 2usize) & 0x01; - val != 0 - } - #[doc = "If 1, and SP is also set, SHA256 can be accessed from a Secure, Unprivileged context."] - #[inline(always)] - pub fn set_su(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 2usize)) | (((val as u32) & 0x01) << 2usize); - } - #[doc = "If 1, SHA256 can be accessed from a Secure, Privileged context."] - #[inline(always)] - pub const fn sp(&self) -> bool { - let val = (self.0 >> 3usize) & 0x01; - val != 0 - } - #[doc = "If 1, SHA256 can be accessed from a Secure, Privileged context."] - #[inline(always)] - pub fn set_sp(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 3usize)) | (((val as u32) & 0x01) << 3usize); - } - #[doc = "If 1, SHA256 can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] - #[inline(always)] - pub const fn core0(&self) -> bool { - let val = (self.0 >> 4usize) & 0x01; - val != 0 - } - #[doc = "If 1, SHA256 can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] - #[inline(always)] - pub fn set_core0(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 4usize)) | (((val as u32) & 0x01) << 4usize); - } - #[doc = "If 1, SHA256 can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] - #[inline(always)] - pub const fn core1(&self) -> bool { - let val = (self.0 >> 5usize) & 0x01; - val != 0 - } - #[doc = "If 1, SHA256 can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] - #[inline(always)] - pub fn set_core1(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 5usize)) | (((val as u32) & 0x01) << 5usize); - } - #[doc = "If 1, SHA256 can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] - #[inline(always)] - pub const fn dma(&self) -> bool { - let val = (self.0 >> 6usize) & 0x01; - val != 0 - } - #[doc = "If 1, SHA256 can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] - #[inline(always)] - pub fn set_dma(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 6usize)) | (((val as u32) & 0x01) << 6usize); - } - #[doc = "If 1, SHA256 can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] - #[inline(always)] - pub const fn dbg(&self) -> bool { - let val = (self.0 >> 7usize) & 0x01; - val != 0 - } - #[doc = "If 1, SHA256 can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] - #[inline(always)] - pub fn set_dbg(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 7usize)) | (((val as u32) & 0x01) << 7usize); - } -} -impl Default for Sha256 { - #[inline(always)] - fn default() -> Sha256 { - Sha256(0) - } -} -#[doc = "Control whether debugger, DMA, core 0 and core 1 can access SPI0, and at what security/privilege levels they can do so. Defaults to Secure access from any master. This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set."] -#[repr(transparent)] -#[derive(Copy, Clone, Eq, PartialEq)] -pub struct Spi0(pub u32); -impl Spi0 { - #[doc = "If 1, and NSP is also set, SPI0 can be accessed from a Non-secure, Unprivileged context. This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set."] - #[inline(always)] - pub const fn nsu(&self) -> bool { - let val = (self.0 >> 0usize) & 0x01; - val != 0 - } - #[doc = "If 1, and NSP is also set, SPI0 can be accessed from a Non-secure, Unprivileged context. This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set."] - #[inline(always)] - pub fn set_nsu(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize); - } - #[doc = "If 1, SPI0 can be accessed from a Non-secure, Privileged context."] - #[inline(always)] - pub const fn nsp(&self) -> bool { - let val = (self.0 >> 1usize) & 0x01; - val != 0 - } - #[doc = "If 1, SPI0 can be accessed from a Non-secure, Privileged context."] - #[inline(always)] - pub fn set_nsp(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize); - } - #[doc = "If 1, and SP is also set, SPI0 can be accessed from a Secure, Unprivileged context."] - #[inline(always)] - pub const fn su(&self) -> bool { - let val = (self.0 >> 2usize) & 0x01; - val != 0 - } - #[doc = "If 1, and SP is also set, SPI0 can be accessed from a Secure, Unprivileged context."] - #[inline(always)] - pub fn set_su(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 2usize)) | (((val as u32) & 0x01) << 2usize); - } - #[doc = "If 1, SPI0 can be accessed from a Secure, Privileged context."] - #[inline(always)] - pub const fn sp(&self) -> bool { - let val = (self.0 >> 3usize) & 0x01; - val != 0 - } - #[doc = "If 1, SPI0 can be accessed from a Secure, Privileged context."] - #[inline(always)] - pub fn set_sp(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 3usize)) | (((val as u32) & 0x01) << 3usize); - } - #[doc = "If 1, SPI0 can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] - #[inline(always)] - pub const fn core0(&self) -> bool { - let val = (self.0 >> 4usize) & 0x01; - val != 0 - } - #[doc = "If 1, SPI0 can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] - #[inline(always)] - pub fn set_core0(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 4usize)) | (((val as u32) & 0x01) << 4usize); - } - #[doc = "If 1, SPI0 can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] - #[inline(always)] - pub const fn core1(&self) -> bool { - let val = (self.0 >> 5usize) & 0x01; - val != 0 - } - #[doc = "If 1, SPI0 can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] - #[inline(always)] - pub fn set_core1(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 5usize)) | (((val as u32) & 0x01) << 5usize); - } - #[doc = "If 1, SPI0 can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] - #[inline(always)] - pub const fn dma(&self) -> bool { - let val = (self.0 >> 6usize) & 0x01; - val != 0 - } - #[doc = "If 1, SPI0 can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] - #[inline(always)] - pub fn set_dma(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 6usize)) | (((val as u32) & 0x01) << 6usize); - } - #[doc = "If 1, SPI0 can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] - #[inline(always)] - pub const fn dbg(&self) -> bool { - let val = (self.0 >> 7usize) & 0x01; - val != 0 - } - #[doc = "If 1, SPI0 can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] - #[inline(always)] - pub fn set_dbg(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 7usize)) | (((val as u32) & 0x01) << 7usize); - } -} -impl Default for Spi0 { - #[inline(always)] - fn default() -> Spi0 { - Spi0(0) - } -} -#[doc = "Control whether debugger, DMA, core 0 and core 1 can access SPI1, and at what security/privilege levels they can do so. Defaults to Secure access from any master. This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set."] -#[repr(transparent)] -#[derive(Copy, Clone, Eq, PartialEq)] -pub struct Spi1(pub u32); -impl Spi1 { - #[doc = "If 1, and NSP is also set, SPI1 can be accessed from a Non-secure, Unprivileged context. This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set."] - #[inline(always)] - pub const fn nsu(&self) -> bool { - let val = (self.0 >> 0usize) & 0x01; - val != 0 - } - #[doc = "If 1, and NSP is also set, SPI1 can be accessed from a Non-secure, Unprivileged context. This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set."] - #[inline(always)] - pub fn set_nsu(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize); - } - #[doc = "If 1, SPI1 can be accessed from a Non-secure, Privileged context."] - #[inline(always)] - pub const fn nsp(&self) -> bool { - let val = (self.0 >> 1usize) & 0x01; - val != 0 - } - #[doc = "If 1, SPI1 can be accessed from a Non-secure, Privileged context."] - #[inline(always)] - pub fn set_nsp(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize); - } - #[doc = "If 1, and SP is also set, SPI1 can be accessed from a Secure, Unprivileged context."] - #[inline(always)] - pub const fn su(&self) -> bool { - let val = (self.0 >> 2usize) & 0x01; - val != 0 - } - #[doc = "If 1, and SP is also set, SPI1 can be accessed from a Secure, Unprivileged context."] - #[inline(always)] - pub fn set_su(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 2usize)) | (((val as u32) & 0x01) << 2usize); - } - #[doc = "If 1, SPI1 can be accessed from a Secure, Privileged context."] - #[inline(always)] - pub const fn sp(&self) -> bool { - let val = (self.0 >> 3usize) & 0x01; - val != 0 - } - #[doc = "If 1, SPI1 can be accessed from a Secure, Privileged context."] - #[inline(always)] - pub fn set_sp(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 3usize)) | (((val as u32) & 0x01) << 3usize); - } - #[doc = "If 1, SPI1 can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] - #[inline(always)] - pub const fn core0(&self) -> bool { - let val = (self.0 >> 4usize) & 0x01; - val != 0 - } - #[doc = "If 1, SPI1 can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] - #[inline(always)] - pub fn set_core0(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 4usize)) | (((val as u32) & 0x01) << 4usize); - } - #[doc = "If 1, SPI1 can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] - #[inline(always)] - pub const fn core1(&self) -> bool { - let val = (self.0 >> 5usize) & 0x01; - val != 0 - } - #[doc = "If 1, SPI1 can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] - #[inline(always)] - pub fn set_core1(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 5usize)) | (((val as u32) & 0x01) << 5usize); - } - #[doc = "If 1, SPI1 can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] - #[inline(always)] - pub const fn dma(&self) -> bool { - let val = (self.0 >> 6usize) & 0x01; - val != 0 - } - #[doc = "If 1, SPI1 can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] - #[inline(always)] - pub fn set_dma(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 6usize)) | (((val as u32) & 0x01) << 6usize); - } - #[doc = "If 1, SPI1 can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] - #[inline(always)] - pub const fn dbg(&self) -> bool { - let val = (self.0 >> 7usize) & 0x01; - val != 0 - } - #[doc = "If 1, SPI1 can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] - #[inline(always)] - pub fn set_dbg(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 7usize)) | (((val as u32) & 0x01) << 7usize); - } -} -impl Default for Spi1 { - #[inline(always)] - fn default() -> Spi1 { - Spi1(0) - } -} -#[doc = "Control whether debugger, DMA, core 0 and core 1 can access SRAM0, and at what security/privilege levels they can do so. Defaults to fully open access. This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set."] -#[repr(transparent)] -#[derive(Copy, Clone, Eq, PartialEq)] -pub struct Sram0(pub u32); -impl Sram0 { - #[doc = "If 1, and NSP is also set, SRAM0 can be accessed from a Non-secure, Unprivileged context. This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set."] - #[inline(always)] - pub const fn nsu(&self) -> bool { - let val = (self.0 >> 0usize) & 0x01; - val != 0 - } - #[doc = "If 1, and NSP is also set, SRAM0 can be accessed from a Non-secure, Unprivileged context. This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set."] - #[inline(always)] - pub fn set_nsu(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize); - } - #[doc = "If 1, SRAM0 can be accessed from a Non-secure, Privileged context."] - #[inline(always)] - pub const fn nsp(&self) -> bool { - let val = (self.0 >> 1usize) & 0x01; - val != 0 - } - #[doc = "If 1, SRAM0 can be accessed from a Non-secure, Privileged context."] - #[inline(always)] - pub fn set_nsp(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize); - } - #[doc = "If 1, and SP is also set, SRAM0 can be accessed from a Secure, Unprivileged context."] - #[inline(always)] - pub const fn su(&self) -> bool { - let val = (self.0 >> 2usize) & 0x01; - val != 0 - } - #[doc = "If 1, and SP is also set, SRAM0 can be accessed from a Secure, Unprivileged context."] - #[inline(always)] - pub fn set_su(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 2usize)) | (((val as u32) & 0x01) << 2usize); - } - #[doc = "If 1, SRAM0 can be accessed from a Secure, Privileged context."] - #[inline(always)] - pub const fn sp(&self) -> bool { - let val = (self.0 >> 3usize) & 0x01; - val != 0 - } - #[doc = "If 1, SRAM0 can be accessed from a Secure, Privileged context."] - #[inline(always)] - pub fn set_sp(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 3usize)) | (((val as u32) & 0x01) << 3usize); - } - #[doc = "If 1, SRAM0 can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] - #[inline(always)] - pub const fn core0(&self) -> bool { - let val = (self.0 >> 4usize) & 0x01; - val != 0 - } - #[doc = "If 1, SRAM0 can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] - #[inline(always)] - pub fn set_core0(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 4usize)) | (((val as u32) & 0x01) << 4usize); - } - #[doc = "If 1, SRAM0 can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] - #[inline(always)] - pub const fn core1(&self) -> bool { - let val = (self.0 >> 5usize) & 0x01; - val != 0 - } - #[doc = "If 1, SRAM0 can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] - #[inline(always)] - pub fn set_core1(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 5usize)) | (((val as u32) & 0x01) << 5usize); - } - #[doc = "If 1, SRAM0 can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] - #[inline(always)] - pub const fn dma(&self) -> bool { - let val = (self.0 >> 6usize) & 0x01; - val != 0 - } - #[doc = "If 1, SRAM0 can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] - #[inline(always)] - pub fn set_dma(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 6usize)) | (((val as u32) & 0x01) << 6usize); - } - #[doc = "If 1, SRAM0 can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] - #[inline(always)] - pub const fn dbg(&self) -> bool { - let val = (self.0 >> 7usize) & 0x01; - val != 0 - } - #[doc = "If 1, SRAM0 can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] - #[inline(always)] - pub fn set_dbg(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 7usize)) | (((val as u32) & 0x01) << 7usize); - } -} -impl Default for Sram0 { - #[inline(always)] - fn default() -> Sram0 { - Sram0(0) - } -} -#[doc = "Control whether debugger, DMA, core 0 and core 1 can access SRAM1, and at what security/privilege levels they can do so. Defaults to fully open access. This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set."] -#[repr(transparent)] -#[derive(Copy, Clone, Eq, PartialEq)] -pub struct Sram1(pub u32); -impl Sram1 { - #[doc = "If 1, and NSP is also set, SRAM1 can be accessed from a Non-secure, Unprivileged context. This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set."] - #[inline(always)] - pub const fn nsu(&self) -> bool { - let val = (self.0 >> 0usize) & 0x01; - val != 0 - } - #[doc = "If 1, and NSP is also set, SRAM1 can be accessed from a Non-secure, Unprivileged context. This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set."] - #[inline(always)] - pub fn set_nsu(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize); - } - #[doc = "If 1, SRAM1 can be accessed from a Non-secure, Privileged context."] - #[inline(always)] - pub const fn nsp(&self) -> bool { - let val = (self.0 >> 1usize) & 0x01; - val != 0 - } - #[doc = "If 1, SRAM1 can be accessed from a Non-secure, Privileged context."] - #[inline(always)] - pub fn set_nsp(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize); - } - #[doc = "If 1, and SP is also set, SRAM1 can be accessed from a Secure, Unprivileged context."] - #[inline(always)] - pub const fn su(&self) -> bool { - let val = (self.0 >> 2usize) & 0x01; - val != 0 - } - #[doc = "If 1, and SP is also set, SRAM1 can be accessed from a Secure, Unprivileged context."] - #[inline(always)] - pub fn set_su(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 2usize)) | (((val as u32) & 0x01) << 2usize); - } - #[doc = "If 1, SRAM1 can be accessed from a Secure, Privileged context."] - #[inline(always)] - pub const fn sp(&self) -> bool { - let val = (self.0 >> 3usize) & 0x01; - val != 0 - } - #[doc = "If 1, SRAM1 can be accessed from a Secure, Privileged context."] - #[inline(always)] - pub fn set_sp(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 3usize)) | (((val as u32) & 0x01) << 3usize); - } - #[doc = "If 1, SRAM1 can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] - #[inline(always)] - pub const fn core0(&self) -> bool { - let val = (self.0 >> 4usize) & 0x01; - val != 0 - } - #[doc = "If 1, SRAM1 can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] - #[inline(always)] - pub fn set_core0(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 4usize)) | (((val as u32) & 0x01) << 4usize); - } - #[doc = "If 1, SRAM1 can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] - #[inline(always)] - pub const fn core1(&self) -> bool { - let val = (self.0 >> 5usize) & 0x01; - val != 0 - } - #[doc = "If 1, SRAM1 can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] - #[inline(always)] - pub fn set_core1(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 5usize)) | (((val as u32) & 0x01) << 5usize); - } - #[doc = "If 1, SRAM1 can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] - #[inline(always)] - pub const fn dma(&self) -> bool { - let val = (self.0 >> 6usize) & 0x01; - val != 0 - } - #[doc = "If 1, SRAM1 can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] - #[inline(always)] - pub fn set_dma(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 6usize)) | (((val as u32) & 0x01) << 6usize); - } - #[doc = "If 1, SRAM1 can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] - #[inline(always)] - pub const fn dbg(&self) -> bool { - let val = (self.0 >> 7usize) & 0x01; - val != 0 - } - #[doc = "If 1, SRAM1 can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] - #[inline(always)] - pub fn set_dbg(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 7usize)) | (((val as u32) & 0x01) << 7usize); - } -} -impl Default for Sram1 { - #[inline(always)] - fn default() -> Sram1 { - Sram1(0) - } -} -#[doc = "Control whether debugger, DMA, core 0 and core 1 can access SRAM2, and at what security/privilege levels they can do so. Defaults to fully open access. This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set."] -#[repr(transparent)] -#[derive(Copy, Clone, Eq, PartialEq)] -pub struct Sram2(pub u32); -impl Sram2 { - #[doc = "If 1, and NSP is also set, SRAM2 can be accessed from a Non-secure, Unprivileged context. This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set."] - #[inline(always)] - pub const fn nsu(&self) -> bool { - let val = (self.0 >> 0usize) & 0x01; - val != 0 - } - #[doc = "If 1, and NSP is also set, SRAM2 can be accessed from a Non-secure, Unprivileged context. This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set."] - #[inline(always)] - pub fn set_nsu(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize); - } - #[doc = "If 1, SRAM2 can be accessed from a Non-secure, Privileged context."] - #[inline(always)] - pub const fn nsp(&self) -> bool { - let val = (self.0 >> 1usize) & 0x01; - val != 0 - } - #[doc = "If 1, SRAM2 can be accessed from a Non-secure, Privileged context."] - #[inline(always)] - pub fn set_nsp(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize); - } - #[doc = "If 1, and SP is also set, SRAM2 can be accessed from a Secure, Unprivileged context."] - #[inline(always)] - pub const fn su(&self) -> bool { - let val = (self.0 >> 2usize) & 0x01; - val != 0 - } - #[doc = "If 1, and SP is also set, SRAM2 can be accessed from a Secure, Unprivileged context."] - #[inline(always)] - pub fn set_su(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 2usize)) | (((val as u32) & 0x01) << 2usize); - } - #[doc = "If 1, SRAM2 can be accessed from a Secure, Privileged context."] - #[inline(always)] - pub const fn sp(&self) -> bool { - let val = (self.0 >> 3usize) & 0x01; - val != 0 - } - #[doc = "If 1, SRAM2 can be accessed from a Secure, Privileged context."] - #[inline(always)] - pub fn set_sp(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 3usize)) | (((val as u32) & 0x01) << 3usize); - } - #[doc = "If 1, SRAM2 can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] - #[inline(always)] - pub const fn core0(&self) -> bool { - let val = (self.0 >> 4usize) & 0x01; - val != 0 - } - #[doc = "If 1, SRAM2 can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] - #[inline(always)] - pub fn set_core0(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 4usize)) | (((val as u32) & 0x01) << 4usize); - } - #[doc = "If 1, SRAM2 can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] - #[inline(always)] - pub const fn core1(&self) -> bool { - let val = (self.0 >> 5usize) & 0x01; - val != 0 - } - #[doc = "If 1, SRAM2 can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] - #[inline(always)] - pub fn set_core1(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 5usize)) | (((val as u32) & 0x01) << 5usize); - } - #[doc = "If 1, SRAM2 can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] - #[inline(always)] - pub const fn dma(&self) -> bool { - let val = (self.0 >> 6usize) & 0x01; - val != 0 - } - #[doc = "If 1, SRAM2 can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] - #[inline(always)] - pub fn set_dma(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 6usize)) | (((val as u32) & 0x01) << 6usize); - } - #[doc = "If 1, SRAM2 can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] - #[inline(always)] - pub const fn dbg(&self) -> bool { - let val = (self.0 >> 7usize) & 0x01; - val != 0 - } - #[doc = "If 1, SRAM2 can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] - #[inline(always)] - pub fn set_dbg(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 7usize)) | (((val as u32) & 0x01) << 7usize); - } -} -impl Default for Sram2 { - #[inline(always)] - fn default() -> Sram2 { - Sram2(0) - } -} -#[doc = "Control whether debugger, DMA, core 0 and core 1 can access SRAM3, and at what security/privilege levels they can do so. Defaults to fully open access. This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set."] -#[repr(transparent)] -#[derive(Copy, Clone, Eq, PartialEq)] -pub struct Sram3(pub u32); -impl Sram3 { - #[doc = "If 1, and NSP is also set, SRAM3 can be accessed from a Non-secure, Unprivileged context. This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set."] - #[inline(always)] - pub const fn nsu(&self) -> bool { - let val = (self.0 >> 0usize) & 0x01; - val != 0 - } - #[doc = "If 1, and NSP is also set, SRAM3 can be accessed from a Non-secure, Unprivileged context. This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set."] - #[inline(always)] - pub fn set_nsu(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize); - } - #[doc = "If 1, SRAM3 can be accessed from a Non-secure, Privileged context."] - #[inline(always)] - pub const fn nsp(&self) -> bool { - let val = (self.0 >> 1usize) & 0x01; - val != 0 - } - #[doc = "If 1, SRAM3 can be accessed from a Non-secure, Privileged context."] - #[inline(always)] - pub fn set_nsp(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize); - } - #[doc = "If 1, and SP is also set, SRAM3 can be accessed from a Secure, Unprivileged context."] - #[inline(always)] - pub const fn su(&self) -> bool { - let val = (self.0 >> 2usize) & 0x01; - val != 0 - } - #[doc = "If 1, and SP is also set, SRAM3 can be accessed from a Secure, Unprivileged context."] - #[inline(always)] - pub fn set_su(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 2usize)) | (((val as u32) & 0x01) << 2usize); - } - #[doc = "If 1, SRAM3 can be accessed from a Secure, Privileged context."] - #[inline(always)] - pub const fn sp(&self) -> bool { - let val = (self.0 >> 3usize) & 0x01; - val != 0 - } - #[doc = "If 1, SRAM3 can be accessed from a Secure, Privileged context."] - #[inline(always)] - pub fn set_sp(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 3usize)) | (((val as u32) & 0x01) << 3usize); - } - #[doc = "If 1, SRAM3 can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] - #[inline(always)] - pub const fn core0(&self) -> bool { - let val = (self.0 >> 4usize) & 0x01; - val != 0 - } - #[doc = "If 1, SRAM3 can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] - #[inline(always)] - pub fn set_core0(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 4usize)) | (((val as u32) & 0x01) << 4usize); - } - #[doc = "If 1, SRAM3 can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] - #[inline(always)] - pub const fn core1(&self) -> bool { - let val = (self.0 >> 5usize) & 0x01; - val != 0 - } - #[doc = "If 1, SRAM3 can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] - #[inline(always)] - pub fn set_core1(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 5usize)) | (((val as u32) & 0x01) << 5usize); - } - #[doc = "If 1, SRAM3 can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] - #[inline(always)] - pub const fn dma(&self) -> bool { - let val = (self.0 >> 6usize) & 0x01; - val != 0 - } - #[doc = "If 1, SRAM3 can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] - #[inline(always)] - pub fn set_dma(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 6usize)) | (((val as u32) & 0x01) << 6usize); - } - #[doc = "If 1, SRAM3 can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] - #[inline(always)] - pub const fn dbg(&self) -> bool { - let val = (self.0 >> 7usize) & 0x01; - val != 0 - } - #[doc = "If 1, SRAM3 can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] - #[inline(always)] - pub fn set_dbg(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 7usize)) | (((val as u32) & 0x01) << 7usize); - } -} -impl Default for Sram3 { - #[inline(always)] - fn default() -> Sram3 { - Sram3(0) - } -} -#[doc = "Control whether debugger, DMA, core 0 and core 1 can access SRAM4, and at what security/privilege levels they can do so. Defaults to fully open access. This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set."] -#[repr(transparent)] -#[derive(Copy, Clone, Eq, PartialEq)] -pub struct Sram4(pub u32); -impl Sram4 { - #[doc = "If 1, and NSP is also set, SRAM4 can be accessed from a Non-secure, Unprivileged context. This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set."] - #[inline(always)] - pub const fn nsu(&self) -> bool { - let val = (self.0 >> 0usize) & 0x01; - val != 0 - } - #[doc = "If 1, and NSP is also set, SRAM4 can be accessed from a Non-secure, Unprivileged context. This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set."] - #[inline(always)] - pub fn set_nsu(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize); - } - #[doc = "If 1, SRAM4 can be accessed from a Non-secure, Privileged context."] - #[inline(always)] - pub const fn nsp(&self) -> bool { - let val = (self.0 >> 1usize) & 0x01; - val != 0 - } - #[doc = "If 1, SRAM4 can be accessed from a Non-secure, Privileged context."] - #[inline(always)] - pub fn set_nsp(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize); - } - #[doc = "If 1, and SP is also set, SRAM4 can be accessed from a Secure, Unprivileged context."] - #[inline(always)] - pub const fn su(&self) -> bool { - let val = (self.0 >> 2usize) & 0x01; - val != 0 - } - #[doc = "If 1, and SP is also set, SRAM4 can be accessed from a Secure, Unprivileged context."] - #[inline(always)] - pub fn set_su(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 2usize)) | (((val as u32) & 0x01) << 2usize); - } - #[doc = "If 1, SRAM4 can be accessed from a Secure, Privileged context."] - #[inline(always)] - pub const fn sp(&self) -> bool { - let val = (self.0 >> 3usize) & 0x01; - val != 0 - } - #[doc = "If 1, SRAM4 can be accessed from a Secure, Privileged context."] - #[inline(always)] - pub fn set_sp(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 3usize)) | (((val as u32) & 0x01) << 3usize); - } - #[doc = "If 1, SRAM4 can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] - #[inline(always)] - pub const fn core0(&self) -> bool { - let val = (self.0 >> 4usize) & 0x01; - val != 0 - } - #[doc = "If 1, SRAM4 can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] - #[inline(always)] - pub fn set_core0(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 4usize)) | (((val as u32) & 0x01) << 4usize); - } - #[doc = "If 1, SRAM4 can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] - #[inline(always)] - pub const fn core1(&self) -> bool { - let val = (self.0 >> 5usize) & 0x01; - val != 0 - } - #[doc = "If 1, SRAM4 can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] - #[inline(always)] - pub fn set_core1(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 5usize)) | (((val as u32) & 0x01) << 5usize); - } - #[doc = "If 1, SRAM4 can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] - #[inline(always)] - pub const fn dma(&self) -> bool { - let val = (self.0 >> 6usize) & 0x01; - val != 0 - } - #[doc = "If 1, SRAM4 can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] - #[inline(always)] - pub fn set_dma(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 6usize)) | (((val as u32) & 0x01) << 6usize); - } - #[doc = "If 1, SRAM4 can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] - #[inline(always)] - pub const fn dbg(&self) -> bool { - let val = (self.0 >> 7usize) & 0x01; - val != 0 - } - #[doc = "If 1, SRAM4 can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] - #[inline(always)] - pub fn set_dbg(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 7usize)) | (((val as u32) & 0x01) << 7usize); - } -} -impl Default for Sram4 { - #[inline(always)] - fn default() -> Sram4 { - Sram4(0) - } -} -#[doc = "Control whether debugger, DMA, core 0 and core 1 can access SRAM5, and at what security/privilege levels they can do so. Defaults to fully open access. This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set."] -#[repr(transparent)] -#[derive(Copy, Clone, Eq, PartialEq)] -pub struct Sram5(pub u32); -impl Sram5 { - #[doc = "If 1, and NSP is also set, SRAM5 can be accessed from a Non-secure, Unprivileged context. This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set."] - #[inline(always)] - pub const fn nsu(&self) -> bool { - let val = (self.0 >> 0usize) & 0x01; - val != 0 - } - #[doc = "If 1, and NSP is also set, SRAM5 can be accessed from a Non-secure, Unprivileged context. This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set."] - #[inline(always)] - pub fn set_nsu(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize); - } - #[doc = "If 1, SRAM5 can be accessed from a Non-secure, Privileged context."] - #[inline(always)] - pub const fn nsp(&self) -> bool { - let val = (self.0 >> 1usize) & 0x01; - val != 0 - } - #[doc = "If 1, SRAM5 can be accessed from a Non-secure, Privileged context."] - #[inline(always)] - pub fn set_nsp(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize); - } - #[doc = "If 1, and SP is also set, SRAM5 can be accessed from a Secure, Unprivileged context."] - #[inline(always)] - pub const fn su(&self) -> bool { - let val = (self.0 >> 2usize) & 0x01; - val != 0 - } - #[doc = "If 1, and SP is also set, SRAM5 can be accessed from a Secure, Unprivileged context."] - #[inline(always)] - pub fn set_su(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 2usize)) | (((val as u32) & 0x01) << 2usize); - } - #[doc = "If 1, SRAM5 can be accessed from a Secure, Privileged context."] - #[inline(always)] - pub const fn sp(&self) -> bool { - let val = (self.0 >> 3usize) & 0x01; - val != 0 - } - #[doc = "If 1, SRAM5 can be accessed from a Secure, Privileged context."] - #[inline(always)] - pub fn set_sp(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 3usize)) | (((val as u32) & 0x01) << 3usize); - } - #[doc = "If 1, SRAM5 can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] - #[inline(always)] - pub const fn core0(&self) -> bool { - let val = (self.0 >> 4usize) & 0x01; - val != 0 - } - #[doc = "If 1, SRAM5 can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] - #[inline(always)] - pub fn set_core0(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 4usize)) | (((val as u32) & 0x01) << 4usize); - } - #[doc = "If 1, SRAM5 can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] - #[inline(always)] - pub const fn core1(&self) -> bool { - let val = (self.0 >> 5usize) & 0x01; - val != 0 - } - #[doc = "If 1, SRAM5 can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] - #[inline(always)] - pub fn set_core1(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 5usize)) | (((val as u32) & 0x01) << 5usize); - } - #[doc = "If 1, SRAM5 can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] - #[inline(always)] - pub const fn dma(&self) -> bool { - let val = (self.0 >> 6usize) & 0x01; - val != 0 - } - #[doc = "If 1, SRAM5 can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] - #[inline(always)] - pub fn set_dma(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 6usize)) | (((val as u32) & 0x01) << 6usize); - } - #[doc = "If 1, SRAM5 can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] - #[inline(always)] - pub const fn dbg(&self) -> bool { - let val = (self.0 >> 7usize) & 0x01; - val != 0 - } - #[doc = "If 1, SRAM5 can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] - #[inline(always)] - pub fn set_dbg(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 7usize)) | (((val as u32) & 0x01) << 7usize); - } -} -impl Default for Sram5 { - #[inline(always)] - fn default() -> Sram5 { - Sram5(0) - } -} -#[doc = "Control whether debugger, DMA, core 0 and core 1 can access SRAM6, and at what security/privilege levels they can do so. Defaults to fully open access. This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set."] -#[repr(transparent)] -#[derive(Copy, Clone, Eq, PartialEq)] -pub struct Sram6(pub u32); -impl Sram6 { - #[doc = "If 1, and NSP is also set, SRAM6 can be accessed from a Non-secure, Unprivileged context. This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set."] - #[inline(always)] - pub const fn nsu(&self) -> bool { - let val = (self.0 >> 0usize) & 0x01; - val != 0 - } - #[doc = "If 1, and NSP is also set, SRAM6 can be accessed from a Non-secure, Unprivileged context. This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set."] - #[inline(always)] - pub fn set_nsu(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize); - } - #[doc = "If 1, SRAM6 can be accessed from a Non-secure, Privileged context."] - #[inline(always)] - pub const fn nsp(&self) -> bool { - let val = (self.0 >> 1usize) & 0x01; - val != 0 - } - #[doc = "If 1, SRAM6 can be accessed from a Non-secure, Privileged context."] - #[inline(always)] - pub fn set_nsp(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize); - } - #[doc = "If 1, and SP is also set, SRAM6 can be accessed from a Secure, Unprivileged context."] - #[inline(always)] - pub const fn su(&self) -> bool { - let val = (self.0 >> 2usize) & 0x01; - val != 0 - } - #[doc = "If 1, and SP is also set, SRAM6 can be accessed from a Secure, Unprivileged context."] - #[inline(always)] - pub fn set_su(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 2usize)) | (((val as u32) & 0x01) << 2usize); - } - #[doc = "If 1, SRAM6 can be accessed from a Secure, Privileged context."] - #[inline(always)] - pub const fn sp(&self) -> bool { - let val = (self.0 >> 3usize) & 0x01; - val != 0 - } - #[doc = "If 1, SRAM6 can be accessed from a Secure, Privileged context."] - #[inline(always)] - pub fn set_sp(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 3usize)) | (((val as u32) & 0x01) << 3usize); - } - #[doc = "If 1, SRAM6 can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] - #[inline(always)] - pub const fn core0(&self) -> bool { - let val = (self.0 >> 4usize) & 0x01; - val != 0 - } - #[doc = "If 1, SRAM6 can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] - #[inline(always)] - pub fn set_core0(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 4usize)) | (((val as u32) & 0x01) << 4usize); - } - #[doc = "If 1, SRAM6 can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] - #[inline(always)] - pub const fn core1(&self) -> bool { - let val = (self.0 >> 5usize) & 0x01; - val != 0 - } - #[doc = "If 1, SRAM6 can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] - #[inline(always)] - pub fn set_core1(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 5usize)) | (((val as u32) & 0x01) << 5usize); - } - #[doc = "If 1, SRAM6 can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] - #[inline(always)] - pub const fn dma(&self) -> bool { - let val = (self.0 >> 6usize) & 0x01; - val != 0 - } - #[doc = "If 1, SRAM6 can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] - #[inline(always)] - pub fn set_dma(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 6usize)) | (((val as u32) & 0x01) << 6usize); - } - #[doc = "If 1, SRAM6 can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] - #[inline(always)] - pub const fn dbg(&self) -> bool { - let val = (self.0 >> 7usize) & 0x01; - val != 0 - } - #[doc = "If 1, SRAM6 can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] - #[inline(always)] - pub fn set_dbg(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 7usize)) | (((val as u32) & 0x01) << 7usize); - } -} -impl Default for Sram6 { - #[inline(always)] - fn default() -> Sram6 { - Sram6(0) - } -} -#[doc = "Control whether debugger, DMA, core 0 and core 1 can access SRAM7, and at what security/privilege levels they can do so. Defaults to fully open access. This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set."] -#[repr(transparent)] -#[derive(Copy, Clone, Eq, PartialEq)] -pub struct Sram7(pub u32); -impl Sram7 { - #[doc = "If 1, and NSP is also set, SRAM7 can be accessed from a Non-secure, Unprivileged context. This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set."] - #[inline(always)] - pub const fn nsu(&self) -> bool { - let val = (self.0 >> 0usize) & 0x01; - val != 0 - } - #[doc = "If 1, and NSP is also set, SRAM7 can be accessed from a Non-secure, Unprivileged context. This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set."] - #[inline(always)] - pub fn set_nsu(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize); - } - #[doc = "If 1, SRAM7 can be accessed from a Non-secure, Privileged context."] - #[inline(always)] - pub const fn nsp(&self) -> bool { - let val = (self.0 >> 1usize) & 0x01; - val != 0 - } - #[doc = "If 1, SRAM7 can be accessed from a Non-secure, Privileged context."] - #[inline(always)] - pub fn set_nsp(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize); - } - #[doc = "If 1, and SP is also set, SRAM7 can be accessed from a Secure, Unprivileged context."] - #[inline(always)] - pub const fn su(&self) -> bool { - let val = (self.0 >> 2usize) & 0x01; - val != 0 - } - #[doc = "If 1, and SP is also set, SRAM7 can be accessed from a Secure, Unprivileged context."] - #[inline(always)] - pub fn set_su(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 2usize)) | (((val as u32) & 0x01) << 2usize); - } - #[doc = "If 1, SRAM7 can be accessed from a Secure, Privileged context."] - #[inline(always)] - pub const fn sp(&self) -> bool { - let val = (self.0 >> 3usize) & 0x01; - val != 0 - } - #[doc = "If 1, SRAM7 can be accessed from a Secure, Privileged context."] - #[inline(always)] - pub fn set_sp(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 3usize)) | (((val as u32) & 0x01) << 3usize); - } - #[doc = "If 1, SRAM7 can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] - #[inline(always)] - pub const fn core0(&self) -> bool { - let val = (self.0 >> 4usize) & 0x01; - val != 0 - } - #[doc = "If 1, SRAM7 can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] - #[inline(always)] - pub fn set_core0(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 4usize)) | (((val as u32) & 0x01) << 4usize); - } - #[doc = "If 1, SRAM7 can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] - #[inline(always)] - pub const fn core1(&self) -> bool { - let val = (self.0 >> 5usize) & 0x01; - val != 0 - } - #[doc = "If 1, SRAM7 can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] - #[inline(always)] - pub fn set_core1(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 5usize)) | (((val as u32) & 0x01) << 5usize); - } - #[doc = "If 1, SRAM7 can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] - #[inline(always)] - pub const fn dma(&self) -> bool { - let val = (self.0 >> 6usize) & 0x01; - val != 0 - } - #[doc = "If 1, SRAM7 can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] - #[inline(always)] - pub fn set_dma(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 6usize)) | (((val as u32) & 0x01) << 6usize); - } - #[doc = "If 1, SRAM7 can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] - #[inline(always)] - pub const fn dbg(&self) -> bool { - let val = (self.0 >> 7usize) & 0x01; - val != 0 - } - #[doc = "If 1, SRAM7 can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] - #[inline(always)] - pub fn set_dbg(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 7usize)) | (((val as u32) & 0x01) << 7usize); - } -} -impl Default for Sram7 { - #[inline(always)] - fn default() -> Sram7 { - Sram7(0) - } -} -#[doc = "Control whether debugger, DMA, core 0 and core 1 can access SRAM8, and at what security/privilege levels they can do so. Defaults to fully open access. This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set."] -#[repr(transparent)] -#[derive(Copy, Clone, Eq, PartialEq)] -pub struct Sram8(pub u32); -impl Sram8 { - #[doc = "If 1, and NSP is also set, SRAM8 can be accessed from a Non-secure, Unprivileged context. This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set."] - #[inline(always)] - pub const fn nsu(&self) -> bool { - let val = (self.0 >> 0usize) & 0x01; - val != 0 - } - #[doc = "If 1, and NSP is also set, SRAM8 can be accessed from a Non-secure, Unprivileged context. This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set."] - #[inline(always)] - pub fn set_nsu(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize); - } - #[doc = "If 1, SRAM8 can be accessed from a Non-secure, Privileged context."] - #[inline(always)] - pub const fn nsp(&self) -> bool { - let val = (self.0 >> 1usize) & 0x01; - val != 0 - } - #[doc = "If 1, SRAM8 can be accessed from a Non-secure, Privileged context."] - #[inline(always)] - pub fn set_nsp(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize); - } - #[doc = "If 1, and SP is also set, SRAM8 can be accessed from a Secure, Unprivileged context."] - #[inline(always)] - pub const fn su(&self) -> bool { - let val = (self.0 >> 2usize) & 0x01; - val != 0 - } - #[doc = "If 1, and SP is also set, SRAM8 can be accessed from a Secure, Unprivileged context."] - #[inline(always)] - pub fn set_su(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 2usize)) | (((val as u32) & 0x01) << 2usize); - } - #[doc = "If 1, SRAM8 can be accessed from a Secure, Privileged context."] - #[inline(always)] - pub const fn sp(&self) -> bool { - let val = (self.0 >> 3usize) & 0x01; - val != 0 - } - #[doc = "If 1, SRAM8 can be accessed from a Secure, Privileged context."] - #[inline(always)] - pub fn set_sp(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 3usize)) | (((val as u32) & 0x01) << 3usize); - } - #[doc = "If 1, SRAM8 can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] - #[inline(always)] - pub const fn core0(&self) -> bool { - let val = (self.0 >> 4usize) & 0x01; - val != 0 - } - #[doc = "If 1, SRAM8 can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] - #[inline(always)] - pub fn set_core0(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 4usize)) | (((val as u32) & 0x01) << 4usize); - } - #[doc = "If 1, SRAM8 can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] - #[inline(always)] - pub const fn core1(&self) -> bool { - let val = (self.0 >> 5usize) & 0x01; - val != 0 - } - #[doc = "If 1, SRAM8 can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] - #[inline(always)] - pub fn set_core1(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 5usize)) | (((val as u32) & 0x01) << 5usize); - } - #[doc = "If 1, SRAM8 can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] - #[inline(always)] - pub const fn dma(&self) -> bool { - let val = (self.0 >> 6usize) & 0x01; - val != 0 - } - #[doc = "If 1, SRAM8 can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] - #[inline(always)] - pub fn set_dma(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 6usize)) | (((val as u32) & 0x01) << 6usize); - } - #[doc = "If 1, SRAM8 can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] - #[inline(always)] - pub const fn dbg(&self) -> bool { - let val = (self.0 >> 7usize) & 0x01; - val != 0 - } - #[doc = "If 1, SRAM8 can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] - #[inline(always)] - pub fn set_dbg(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 7usize)) | (((val as u32) & 0x01) << 7usize); - } -} -impl Default for Sram8 { - #[inline(always)] - fn default() -> Sram8 { - Sram8(0) - } -} -#[doc = "Control whether debugger, DMA, core 0 and core 1 can access SRAM9, and at what security/privilege levels they can do so. Defaults to fully open access. This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set."] -#[repr(transparent)] -#[derive(Copy, Clone, Eq, PartialEq)] -pub struct Sram9(pub u32); -impl Sram9 { - #[doc = "If 1, and NSP is also set, SRAM9 can be accessed from a Non-secure, Unprivileged context. This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set."] - #[inline(always)] - pub const fn nsu(&self) -> bool { - let val = (self.0 >> 0usize) & 0x01; - val != 0 - } - #[doc = "If 1, and NSP is also set, SRAM9 can be accessed from a Non-secure, Unprivileged context. This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set."] - #[inline(always)] - pub fn set_nsu(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize); - } - #[doc = "If 1, SRAM9 can be accessed from a Non-secure, Privileged context."] - #[inline(always)] - pub const fn nsp(&self) -> bool { - let val = (self.0 >> 1usize) & 0x01; - val != 0 - } - #[doc = "If 1, SRAM9 can be accessed from a Non-secure, Privileged context."] - #[inline(always)] - pub fn set_nsp(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize); - } - #[doc = "If 1, and SP is also set, SRAM9 can be accessed from a Secure, Unprivileged context."] - #[inline(always)] - pub const fn su(&self) -> bool { - let val = (self.0 >> 2usize) & 0x01; - val != 0 - } - #[doc = "If 1, and SP is also set, SRAM9 can be accessed from a Secure, Unprivileged context."] - #[inline(always)] - pub fn set_su(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 2usize)) | (((val as u32) & 0x01) << 2usize); - } - #[doc = "If 1, SRAM9 can be accessed from a Secure, Privileged context."] - #[inline(always)] - pub const fn sp(&self) -> bool { - let val = (self.0 >> 3usize) & 0x01; - val != 0 - } - #[doc = "If 1, SRAM9 can be accessed from a Secure, Privileged context."] - #[inline(always)] - pub fn set_sp(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 3usize)) | (((val as u32) & 0x01) << 3usize); - } - #[doc = "If 1, SRAM9 can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] - #[inline(always)] - pub const fn core0(&self) -> bool { - let val = (self.0 >> 4usize) & 0x01; - val != 0 - } - #[doc = "If 1, SRAM9 can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] - #[inline(always)] - pub fn set_core0(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 4usize)) | (((val as u32) & 0x01) << 4usize); - } - #[doc = "If 1, SRAM9 can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] - #[inline(always)] - pub const fn core1(&self) -> bool { - let val = (self.0 >> 5usize) & 0x01; - val != 0 - } - #[doc = "If 1, SRAM9 can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] - #[inline(always)] - pub fn set_core1(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 5usize)) | (((val as u32) & 0x01) << 5usize); - } - #[doc = "If 1, SRAM9 can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] - #[inline(always)] - pub const fn dma(&self) -> bool { - let val = (self.0 >> 6usize) & 0x01; - val != 0 - } - #[doc = "If 1, SRAM9 can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] - #[inline(always)] - pub fn set_dma(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 6usize)) | (((val as u32) & 0x01) << 6usize); - } - #[doc = "If 1, SRAM9 can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] - #[inline(always)] - pub const fn dbg(&self) -> bool { - let val = (self.0 >> 7usize) & 0x01; - val != 0 - } - #[doc = "If 1, SRAM9 can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] - #[inline(always)] - pub fn set_dbg(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 7usize)) | (((val as u32) & 0x01) << 7usize); - } -} -impl Default for Sram9 { - #[inline(always)] - fn default() -> Sram9 { - Sram9(0) - } -} -#[doc = "Control whether debugger, DMA, core 0 and core 1 can access SYSCFG, and at what security/privilege levels they can do so. Defaults to Secure, Privileged processor or debug access only. This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set."] -#[repr(transparent)] -#[derive(Copy, Clone, Eq, PartialEq)] -pub struct Syscfg(pub u32); -impl Syscfg { - #[doc = "If 1, and NSP is also set, SYSCFG can be accessed from a Non-secure, Unprivileged context. This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set."] - #[inline(always)] - pub const fn nsu(&self) -> bool { - let val = (self.0 >> 0usize) & 0x01; - val != 0 - } - #[doc = "If 1, and NSP is also set, SYSCFG can be accessed from a Non-secure, Unprivileged context. This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set."] - #[inline(always)] - pub fn set_nsu(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize); - } - #[doc = "If 1, SYSCFG can be accessed from a Non-secure, Privileged context."] - #[inline(always)] - pub const fn nsp(&self) -> bool { - let val = (self.0 >> 1usize) & 0x01; - val != 0 - } - #[doc = "If 1, SYSCFG can be accessed from a Non-secure, Privileged context."] - #[inline(always)] - pub fn set_nsp(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize); - } - #[doc = "If 1, and SP is also set, SYSCFG can be accessed from a Secure, Unprivileged context."] - #[inline(always)] - pub const fn su(&self) -> bool { - let val = (self.0 >> 2usize) & 0x01; - val != 0 - } - #[doc = "If 1, and SP is also set, SYSCFG can be accessed from a Secure, Unprivileged context."] - #[inline(always)] - pub fn set_su(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 2usize)) | (((val as u32) & 0x01) << 2usize); - } - #[doc = "If 1, SYSCFG can be accessed from a Secure, Privileged context."] - #[inline(always)] - pub const fn sp(&self) -> bool { - let val = (self.0 >> 3usize) & 0x01; - val != 0 - } - #[doc = "If 1, SYSCFG can be accessed from a Secure, Privileged context."] - #[inline(always)] - pub fn set_sp(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 3usize)) | (((val as u32) & 0x01) << 3usize); - } - #[doc = "If 1, SYSCFG can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] - #[inline(always)] - pub const fn core0(&self) -> bool { - let val = (self.0 >> 4usize) & 0x01; - val != 0 - } - #[doc = "If 1, SYSCFG can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] - #[inline(always)] - pub fn set_core0(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 4usize)) | (((val as u32) & 0x01) << 4usize); - } - #[doc = "If 1, SYSCFG can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] - #[inline(always)] - pub const fn core1(&self) -> bool { - let val = (self.0 >> 5usize) & 0x01; - val != 0 - } - #[doc = "If 1, SYSCFG can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] - #[inline(always)] - pub fn set_core1(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 5usize)) | (((val as u32) & 0x01) << 5usize); - } - #[doc = "If 1, SYSCFG can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] - #[inline(always)] - pub const fn dma(&self) -> bool { - let val = (self.0 >> 6usize) & 0x01; - val != 0 - } - #[doc = "If 1, SYSCFG can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] - #[inline(always)] - pub fn set_dma(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 6usize)) | (((val as u32) & 0x01) << 6usize); - } - #[doc = "If 1, SYSCFG can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] - #[inline(always)] - pub const fn dbg(&self) -> bool { - let val = (self.0 >> 7usize) & 0x01; - val != 0 - } - #[doc = "If 1, SYSCFG can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] - #[inline(always)] - pub fn set_dbg(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 7usize)) | (((val as u32) & 0x01) << 7usize); - } -} -impl Default for Syscfg { - #[inline(always)] - fn default() -> Syscfg { - Syscfg(0) - } -} -#[doc = "Control whether debugger, DMA, core 0 and core 1 can access SYSINFO, and at what security/privilege levels they can do so. Defaults to fully open access. This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set."] -#[repr(transparent)] -#[derive(Copy, Clone, Eq, PartialEq)] -pub struct Sysinfo(pub u32); -impl Sysinfo { - #[doc = "If 1, and NSP is also set, SYSINFO can be accessed from a Non-secure, Unprivileged context. This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set."] - #[inline(always)] - pub const fn nsu(&self) -> bool { - let val = (self.0 >> 0usize) & 0x01; - val != 0 - } - #[doc = "If 1, and NSP is also set, SYSINFO can be accessed from a Non-secure, Unprivileged context. This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set."] - #[inline(always)] - pub fn set_nsu(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize); - } - #[doc = "If 1, SYSINFO can be accessed from a Non-secure, Privileged context."] - #[inline(always)] - pub const fn nsp(&self) -> bool { - let val = (self.0 >> 1usize) & 0x01; - val != 0 - } - #[doc = "If 1, SYSINFO can be accessed from a Non-secure, Privileged context."] - #[inline(always)] - pub fn set_nsp(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize); - } - #[doc = "If 1, and SP is also set, SYSINFO can be accessed from a Secure, Unprivileged context."] - #[inline(always)] - pub const fn su(&self) -> bool { - let val = (self.0 >> 2usize) & 0x01; - val != 0 - } - #[doc = "If 1, and SP is also set, SYSINFO can be accessed from a Secure, Unprivileged context."] - #[inline(always)] - pub fn set_su(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 2usize)) | (((val as u32) & 0x01) << 2usize); - } - #[doc = "If 1, SYSINFO can be accessed from a Secure, Privileged context."] - #[inline(always)] - pub const fn sp(&self) -> bool { - let val = (self.0 >> 3usize) & 0x01; - val != 0 - } - #[doc = "If 1, SYSINFO can be accessed from a Secure, Privileged context."] - #[inline(always)] - pub fn set_sp(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 3usize)) | (((val as u32) & 0x01) << 3usize); - } - #[doc = "If 1, SYSINFO can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] - #[inline(always)] - pub const fn core0(&self) -> bool { - let val = (self.0 >> 4usize) & 0x01; - val != 0 - } - #[doc = "If 1, SYSINFO can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] - #[inline(always)] - pub fn set_core0(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 4usize)) | (((val as u32) & 0x01) << 4usize); - } - #[doc = "If 1, SYSINFO can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] - #[inline(always)] - pub const fn core1(&self) -> bool { - let val = (self.0 >> 5usize) & 0x01; - val != 0 - } - #[doc = "If 1, SYSINFO can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] - #[inline(always)] - pub fn set_core1(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 5usize)) | (((val as u32) & 0x01) << 5usize); - } - #[doc = "If 1, SYSINFO can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] - #[inline(always)] - pub const fn dma(&self) -> bool { - let val = (self.0 >> 6usize) & 0x01; - val != 0 - } - #[doc = "If 1, SYSINFO can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] - #[inline(always)] - pub fn set_dma(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 6usize)) | (((val as u32) & 0x01) << 6usize); - } - #[doc = "If 1, SYSINFO can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] - #[inline(always)] - pub const fn dbg(&self) -> bool { - let val = (self.0 >> 7usize) & 0x01; - val != 0 - } - #[doc = "If 1, SYSINFO can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] - #[inline(always)] - pub fn set_dbg(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 7usize)) | (((val as u32) & 0x01) << 7usize); - } -} -impl Default for Sysinfo { - #[inline(always)] - fn default() -> Sysinfo { - Sysinfo(0) - } -} -#[doc = "Control whether debugger, DMA, core 0 and core 1 can access TBMAN, and at what security/privilege levels they can do so. Defaults to Secure access from any master. This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set."] -#[repr(transparent)] -#[derive(Copy, Clone, Eq, PartialEq)] -pub struct Tbman(pub u32); -impl Tbman { - #[doc = "If 1, and NSP is also set, TBMAN can be accessed from a Non-secure, Unprivileged context. This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set."] - #[inline(always)] - pub const fn nsu(&self) -> bool { - let val = (self.0 >> 0usize) & 0x01; - val != 0 - } - #[doc = "If 1, and NSP is also set, TBMAN can be accessed from a Non-secure, Unprivileged context. This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set."] - #[inline(always)] - pub fn set_nsu(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize); - } - #[doc = "If 1, TBMAN can be accessed from a Non-secure, Privileged context."] - #[inline(always)] - pub const fn nsp(&self) -> bool { - let val = (self.0 >> 1usize) & 0x01; - val != 0 - } - #[doc = "If 1, TBMAN can be accessed from a Non-secure, Privileged context."] - #[inline(always)] - pub fn set_nsp(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize); - } - #[doc = "If 1, and SP is also set, TBMAN can be accessed from a Secure, Unprivileged context."] - #[inline(always)] - pub const fn su(&self) -> bool { - let val = (self.0 >> 2usize) & 0x01; - val != 0 - } - #[doc = "If 1, and SP is also set, TBMAN can be accessed from a Secure, Unprivileged context."] - #[inline(always)] - pub fn set_su(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 2usize)) | (((val as u32) & 0x01) << 2usize); - } - #[doc = "If 1, TBMAN can be accessed from a Secure, Privileged context."] - #[inline(always)] - pub const fn sp(&self) -> bool { - let val = (self.0 >> 3usize) & 0x01; - val != 0 - } - #[doc = "If 1, TBMAN can be accessed from a Secure, Privileged context."] - #[inline(always)] - pub fn set_sp(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 3usize)) | (((val as u32) & 0x01) << 3usize); - } - #[doc = "If 1, TBMAN can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] - #[inline(always)] - pub const fn core0(&self) -> bool { - let val = (self.0 >> 4usize) & 0x01; - val != 0 - } - #[doc = "If 1, TBMAN can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] - #[inline(always)] - pub fn set_core0(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 4usize)) | (((val as u32) & 0x01) << 4usize); - } - #[doc = "If 1, TBMAN can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] - #[inline(always)] - pub const fn core1(&self) -> bool { - let val = (self.0 >> 5usize) & 0x01; - val != 0 - } - #[doc = "If 1, TBMAN can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] - #[inline(always)] - pub fn set_core1(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 5usize)) | (((val as u32) & 0x01) << 5usize); - } - #[doc = "If 1, TBMAN can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] - #[inline(always)] - pub const fn dma(&self) -> bool { - let val = (self.0 >> 6usize) & 0x01; - val != 0 - } - #[doc = "If 1, TBMAN can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] - #[inline(always)] - pub fn set_dma(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 6usize)) | (((val as u32) & 0x01) << 6usize); - } - #[doc = "If 1, TBMAN can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] - #[inline(always)] - pub const fn dbg(&self) -> bool { - let val = (self.0 >> 7usize) & 0x01; - val != 0 - } - #[doc = "If 1, TBMAN can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] - #[inline(always)] - pub fn set_dbg(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 7usize)) | (((val as u32) & 0x01) << 7usize); - } -} -impl Default for Tbman { - #[inline(always)] - fn default() -> Tbman { - Tbman(0) - } -} -#[doc = "Control whether debugger, DMA, core 0 and core 1 can access TICKS, and at what security/privilege levels they can do so. Defaults to Secure, Privileged processor or debug access only. This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set."] -#[repr(transparent)] -#[derive(Copy, Clone, Eq, PartialEq)] -pub struct Ticks(pub u32); -impl Ticks { - #[doc = "If 1, and NSP is also set, TICKS can be accessed from a Non-secure, Unprivileged context. This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set."] - #[inline(always)] - pub const fn nsu(&self) -> bool { - let val = (self.0 >> 0usize) & 0x01; - val != 0 - } - #[doc = "If 1, and NSP is also set, TICKS can be accessed from a Non-secure, Unprivileged context. This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set."] - #[inline(always)] - pub fn set_nsu(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize); - } - #[doc = "If 1, TICKS can be accessed from a Non-secure, Privileged context."] - #[inline(always)] - pub const fn nsp(&self) -> bool { - let val = (self.0 >> 1usize) & 0x01; - val != 0 - } - #[doc = "If 1, TICKS can be accessed from a Non-secure, Privileged context."] - #[inline(always)] - pub fn set_nsp(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize); - } - #[doc = "If 1, and SP is also set, TICKS can be accessed from a Secure, Unprivileged context."] - #[inline(always)] - pub const fn su(&self) -> bool { - let val = (self.0 >> 2usize) & 0x01; - val != 0 - } - #[doc = "If 1, and SP is also set, TICKS can be accessed from a Secure, Unprivileged context."] - #[inline(always)] - pub fn set_su(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 2usize)) | (((val as u32) & 0x01) << 2usize); - } - #[doc = "If 1, TICKS can be accessed from a Secure, Privileged context."] - #[inline(always)] - pub const fn sp(&self) -> bool { - let val = (self.0 >> 3usize) & 0x01; - val != 0 - } - #[doc = "If 1, TICKS can be accessed from a Secure, Privileged context."] - #[inline(always)] - pub fn set_sp(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 3usize)) | (((val as u32) & 0x01) << 3usize); - } - #[doc = "If 1, TICKS can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] - #[inline(always)] - pub const fn core0(&self) -> bool { - let val = (self.0 >> 4usize) & 0x01; - val != 0 - } - #[doc = "If 1, TICKS can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] - #[inline(always)] - pub fn set_core0(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 4usize)) | (((val as u32) & 0x01) << 4usize); - } - #[doc = "If 1, TICKS can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] - #[inline(always)] - pub const fn core1(&self) -> bool { - let val = (self.0 >> 5usize) & 0x01; - val != 0 - } - #[doc = "If 1, TICKS can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] - #[inline(always)] - pub fn set_core1(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 5usize)) | (((val as u32) & 0x01) << 5usize); - } - #[doc = "If 1, TICKS can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] - #[inline(always)] - pub const fn dma(&self) -> bool { - let val = (self.0 >> 6usize) & 0x01; - val != 0 - } - #[doc = "If 1, TICKS can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] - #[inline(always)] - pub fn set_dma(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 6usize)) | (((val as u32) & 0x01) << 6usize); - } - #[doc = "If 1, TICKS can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] - #[inline(always)] - pub const fn dbg(&self) -> bool { - let val = (self.0 >> 7usize) & 0x01; - val != 0 - } - #[doc = "If 1, TICKS can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] - #[inline(always)] - pub fn set_dbg(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 7usize)) | (((val as u32) & 0x01) << 7usize); - } -} -impl Default for Ticks { - #[inline(always)] - fn default() -> Ticks { - Ticks(0) - } -} -#[doc = "Control whether debugger, DMA, core 0 and core 1 can access TIMER0, and at what security/privilege levels they can do so. Defaults to Secure access from any master. This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set."] -#[repr(transparent)] -#[derive(Copy, Clone, Eq, PartialEq)] -pub struct Timer0(pub u32); -impl Timer0 { - #[doc = "If 1, and NSP is also set, TIMER0 can be accessed from a Non-secure, Unprivileged context. This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set."] - #[inline(always)] - pub const fn nsu(&self) -> bool { - let val = (self.0 >> 0usize) & 0x01; - val != 0 - } - #[doc = "If 1, and NSP is also set, TIMER0 can be accessed from a Non-secure, Unprivileged context. This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set."] - #[inline(always)] - pub fn set_nsu(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize); - } - #[doc = "If 1, TIMER0 can be accessed from a Non-secure, Privileged context."] - #[inline(always)] - pub const fn nsp(&self) -> bool { - let val = (self.0 >> 1usize) & 0x01; - val != 0 - } - #[doc = "If 1, TIMER0 can be accessed from a Non-secure, Privileged context."] - #[inline(always)] - pub fn set_nsp(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize); - } - #[doc = "If 1, and SP is also set, TIMER0 can be accessed from a Secure, Unprivileged context."] - #[inline(always)] - pub const fn su(&self) -> bool { - let val = (self.0 >> 2usize) & 0x01; - val != 0 - } - #[doc = "If 1, and SP is also set, TIMER0 can be accessed from a Secure, Unprivileged context."] - #[inline(always)] - pub fn set_su(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 2usize)) | (((val as u32) & 0x01) << 2usize); - } - #[doc = "If 1, TIMER0 can be accessed from a Secure, Privileged context."] - #[inline(always)] - pub const fn sp(&self) -> bool { - let val = (self.0 >> 3usize) & 0x01; - val != 0 - } - #[doc = "If 1, TIMER0 can be accessed from a Secure, Privileged context."] - #[inline(always)] - pub fn set_sp(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 3usize)) | (((val as u32) & 0x01) << 3usize); - } - #[doc = "If 1, TIMER0 can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] - #[inline(always)] - pub const fn core0(&self) -> bool { - let val = (self.0 >> 4usize) & 0x01; - val != 0 - } - #[doc = "If 1, TIMER0 can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] - #[inline(always)] - pub fn set_core0(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 4usize)) | (((val as u32) & 0x01) << 4usize); - } - #[doc = "If 1, TIMER0 can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] - #[inline(always)] - pub const fn core1(&self) -> bool { - let val = (self.0 >> 5usize) & 0x01; - val != 0 - } - #[doc = "If 1, TIMER0 can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] - #[inline(always)] - pub fn set_core1(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 5usize)) | (((val as u32) & 0x01) << 5usize); - } - #[doc = "If 1, TIMER0 can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] - #[inline(always)] - pub const fn dma(&self) -> bool { - let val = (self.0 >> 6usize) & 0x01; - val != 0 - } - #[doc = "If 1, TIMER0 can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] - #[inline(always)] - pub fn set_dma(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 6usize)) | (((val as u32) & 0x01) << 6usize); - } - #[doc = "If 1, TIMER0 can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] - #[inline(always)] - pub const fn dbg(&self) -> bool { - let val = (self.0 >> 7usize) & 0x01; - val != 0 - } - #[doc = "If 1, TIMER0 can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] - #[inline(always)] - pub fn set_dbg(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 7usize)) | (((val as u32) & 0x01) << 7usize); - } -} -impl Default for Timer0 { - #[inline(always)] - fn default() -> Timer0 { - Timer0(0) - } -} -#[doc = "Control whether debugger, DMA, core 0 and core 1 can access TIMER1, and at what security/privilege levels they can do so. Defaults to Secure access from any master. This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set."] -#[repr(transparent)] -#[derive(Copy, Clone, Eq, PartialEq)] -pub struct Timer1(pub u32); -impl Timer1 { - #[doc = "If 1, and NSP is also set, TIMER1 can be accessed from a Non-secure, Unprivileged context. This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set."] - #[inline(always)] - pub const fn nsu(&self) -> bool { - let val = (self.0 >> 0usize) & 0x01; - val != 0 - } - #[doc = "If 1, and NSP is also set, TIMER1 can be accessed from a Non-secure, Unprivileged context. This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set."] - #[inline(always)] - pub fn set_nsu(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize); - } - #[doc = "If 1, TIMER1 can be accessed from a Non-secure, Privileged context."] - #[inline(always)] - pub const fn nsp(&self) -> bool { - let val = (self.0 >> 1usize) & 0x01; - val != 0 - } - #[doc = "If 1, TIMER1 can be accessed from a Non-secure, Privileged context."] - #[inline(always)] - pub fn set_nsp(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize); - } - #[doc = "If 1, and SP is also set, TIMER1 can be accessed from a Secure, Unprivileged context."] - #[inline(always)] - pub const fn su(&self) -> bool { - let val = (self.0 >> 2usize) & 0x01; - val != 0 - } - #[doc = "If 1, and SP is also set, TIMER1 can be accessed from a Secure, Unprivileged context."] - #[inline(always)] - pub fn set_su(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 2usize)) | (((val as u32) & 0x01) << 2usize); - } - #[doc = "If 1, TIMER1 can be accessed from a Secure, Privileged context."] - #[inline(always)] - pub const fn sp(&self) -> bool { - let val = (self.0 >> 3usize) & 0x01; - val != 0 - } - #[doc = "If 1, TIMER1 can be accessed from a Secure, Privileged context."] - #[inline(always)] - pub fn set_sp(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 3usize)) | (((val as u32) & 0x01) << 3usize); - } - #[doc = "If 1, TIMER1 can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] - #[inline(always)] - pub const fn core0(&self) -> bool { - let val = (self.0 >> 4usize) & 0x01; - val != 0 - } - #[doc = "If 1, TIMER1 can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] - #[inline(always)] - pub fn set_core0(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 4usize)) | (((val as u32) & 0x01) << 4usize); - } - #[doc = "If 1, TIMER1 can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] - #[inline(always)] - pub const fn core1(&self) -> bool { - let val = (self.0 >> 5usize) & 0x01; - val != 0 - } - #[doc = "If 1, TIMER1 can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] - #[inline(always)] - pub fn set_core1(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 5usize)) | (((val as u32) & 0x01) << 5usize); - } - #[doc = "If 1, TIMER1 can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] - #[inline(always)] - pub const fn dma(&self) -> bool { - let val = (self.0 >> 6usize) & 0x01; - val != 0 - } - #[doc = "If 1, TIMER1 can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] - #[inline(always)] - pub fn set_dma(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 6usize)) | (((val as u32) & 0x01) << 6usize); - } - #[doc = "If 1, TIMER1 can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] - #[inline(always)] - pub const fn dbg(&self) -> bool { - let val = (self.0 >> 7usize) & 0x01; - val != 0 - } - #[doc = "If 1, TIMER1 can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] - #[inline(always)] - pub fn set_dbg(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 7usize)) | (((val as u32) & 0x01) << 7usize); - } -} -impl Default for Timer1 { - #[inline(always)] - fn default() -> Timer1 { - Timer1(0) - } -} -#[doc = "Control whether debugger, DMA, core 0 and core 1 can access TRNG, and at what security/privilege levels they can do so. Defaults to Secure, Privileged processor or debug access only. This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set."] -#[repr(transparent)] -#[derive(Copy, Clone, Eq, PartialEq)] -pub struct Trng(pub u32); -impl Trng { - #[doc = "If 1, and NSP is also set, TRNG can be accessed from a Non-secure, Unprivileged context. This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set."] - #[inline(always)] - pub const fn nsu(&self) -> bool { - let val = (self.0 >> 0usize) & 0x01; - val != 0 - } - #[doc = "If 1, and NSP is also set, TRNG can be accessed from a Non-secure, Unprivileged context. This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set."] - #[inline(always)] - pub fn set_nsu(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize); - } - #[doc = "If 1, TRNG can be accessed from a Non-secure, Privileged context."] - #[inline(always)] - pub const fn nsp(&self) -> bool { - let val = (self.0 >> 1usize) & 0x01; - val != 0 - } - #[doc = "If 1, TRNG can be accessed from a Non-secure, Privileged context."] - #[inline(always)] - pub fn set_nsp(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize); - } - #[doc = "If 1, and SP is also set, TRNG can be accessed from a Secure, Unprivileged context."] - #[inline(always)] - pub const fn su(&self) -> bool { - let val = (self.0 >> 2usize) & 0x01; - val != 0 - } - #[doc = "If 1, and SP is also set, TRNG can be accessed from a Secure, Unprivileged context."] - #[inline(always)] - pub fn set_su(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 2usize)) | (((val as u32) & 0x01) << 2usize); - } - #[doc = "If 1, TRNG can be accessed from a Secure, Privileged context."] - #[inline(always)] - pub const fn sp(&self) -> bool { - let val = (self.0 >> 3usize) & 0x01; - val != 0 - } - #[doc = "If 1, TRNG can be accessed from a Secure, Privileged context."] - #[inline(always)] - pub fn set_sp(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 3usize)) | (((val as u32) & 0x01) << 3usize); - } - #[doc = "If 1, TRNG can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] - #[inline(always)] - pub const fn core0(&self) -> bool { - let val = (self.0 >> 4usize) & 0x01; - val != 0 - } - #[doc = "If 1, TRNG can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] - #[inline(always)] - pub fn set_core0(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 4usize)) | (((val as u32) & 0x01) << 4usize); - } - #[doc = "If 1, TRNG can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] - #[inline(always)] - pub const fn core1(&self) -> bool { - let val = (self.0 >> 5usize) & 0x01; - val != 0 - } - #[doc = "If 1, TRNG can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] - #[inline(always)] - pub fn set_core1(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 5usize)) | (((val as u32) & 0x01) << 5usize); - } - #[doc = "If 1, TRNG can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] - #[inline(always)] - pub const fn dma(&self) -> bool { - let val = (self.0 >> 6usize) & 0x01; - val != 0 - } - #[doc = "If 1, TRNG can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] - #[inline(always)] - pub fn set_dma(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 6usize)) | (((val as u32) & 0x01) << 6usize); - } - #[doc = "If 1, TRNG can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] - #[inline(always)] - pub const fn dbg(&self) -> bool { - let val = (self.0 >> 7usize) & 0x01; - val != 0 - } - #[doc = "If 1, TRNG can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] - #[inline(always)] - pub fn set_dbg(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 7usize)) | (((val as u32) & 0x01) << 7usize); - } -} -impl Default for Trng { - #[inline(always)] - fn default() -> Trng { - Trng(0) - } -} -#[doc = "Control whether debugger, DMA, core 0 and core 1 can access UART0, and at what security/privilege levels they can do so. Defaults to Secure access from any master. This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set."] -#[repr(transparent)] -#[derive(Copy, Clone, Eq, PartialEq)] -pub struct Uart0(pub u32); -impl Uart0 { - #[doc = "If 1, and NSP is also set, UART0 can be accessed from a Non-secure, Unprivileged context. This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set."] - #[inline(always)] - pub const fn nsu(&self) -> bool { - let val = (self.0 >> 0usize) & 0x01; - val != 0 - } - #[doc = "If 1, and NSP is also set, UART0 can be accessed from a Non-secure, Unprivileged context. This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set."] - #[inline(always)] - pub fn set_nsu(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize); - } - #[doc = "If 1, UART0 can be accessed from a Non-secure, Privileged context."] - #[inline(always)] - pub const fn nsp(&self) -> bool { - let val = (self.0 >> 1usize) & 0x01; - val != 0 - } - #[doc = "If 1, UART0 can be accessed from a Non-secure, Privileged context."] - #[inline(always)] - pub fn set_nsp(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize); - } - #[doc = "If 1, and SP is also set, UART0 can be accessed from a Secure, Unprivileged context."] - #[inline(always)] - pub const fn su(&self) -> bool { - let val = (self.0 >> 2usize) & 0x01; - val != 0 - } - #[doc = "If 1, and SP is also set, UART0 can be accessed from a Secure, Unprivileged context."] - #[inline(always)] - pub fn set_su(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 2usize)) | (((val as u32) & 0x01) << 2usize); - } - #[doc = "If 1, UART0 can be accessed from a Secure, Privileged context."] - #[inline(always)] - pub const fn sp(&self) -> bool { - let val = (self.0 >> 3usize) & 0x01; - val != 0 - } - #[doc = "If 1, UART0 can be accessed from a Secure, Privileged context."] - #[inline(always)] - pub fn set_sp(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 3usize)) | (((val as u32) & 0x01) << 3usize); - } - #[doc = "If 1, UART0 can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] - #[inline(always)] - pub const fn core0(&self) -> bool { - let val = (self.0 >> 4usize) & 0x01; - val != 0 - } - #[doc = "If 1, UART0 can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] - #[inline(always)] - pub fn set_core0(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 4usize)) | (((val as u32) & 0x01) << 4usize); - } - #[doc = "If 1, UART0 can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] - #[inline(always)] - pub const fn core1(&self) -> bool { - let val = (self.0 >> 5usize) & 0x01; - val != 0 - } - #[doc = "If 1, UART0 can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] - #[inline(always)] - pub fn set_core1(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 5usize)) | (((val as u32) & 0x01) << 5usize); - } - #[doc = "If 1, UART0 can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] - #[inline(always)] - pub const fn dma(&self) -> bool { - let val = (self.0 >> 6usize) & 0x01; - val != 0 - } - #[doc = "If 1, UART0 can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] - #[inline(always)] - pub fn set_dma(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 6usize)) | (((val as u32) & 0x01) << 6usize); - } - #[doc = "If 1, UART0 can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] - #[inline(always)] - pub const fn dbg(&self) -> bool { - let val = (self.0 >> 7usize) & 0x01; - val != 0 - } - #[doc = "If 1, UART0 can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] - #[inline(always)] - pub fn set_dbg(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 7usize)) | (((val as u32) & 0x01) << 7usize); - } -} -impl Default for Uart0 { - #[inline(always)] - fn default() -> Uart0 { - Uart0(0) - } -} -#[doc = "Control whether debugger, DMA, core 0 and core 1 can access UART1, and at what security/privilege levels they can do so. Defaults to Secure access from any master. This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set."] -#[repr(transparent)] -#[derive(Copy, Clone, Eq, PartialEq)] -pub struct Uart1(pub u32); -impl Uart1 { - #[doc = "If 1, and NSP is also set, UART1 can be accessed from a Non-secure, Unprivileged context. This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set."] - #[inline(always)] - pub const fn nsu(&self) -> bool { - let val = (self.0 >> 0usize) & 0x01; - val != 0 - } - #[doc = "If 1, and NSP is also set, UART1 can be accessed from a Non-secure, Unprivileged context. This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set."] - #[inline(always)] - pub fn set_nsu(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize); - } - #[doc = "If 1, UART1 can be accessed from a Non-secure, Privileged context."] - #[inline(always)] - pub const fn nsp(&self) -> bool { - let val = (self.0 >> 1usize) & 0x01; - val != 0 - } - #[doc = "If 1, UART1 can be accessed from a Non-secure, Privileged context."] - #[inline(always)] - pub fn set_nsp(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize); - } - #[doc = "If 1, and SP is also set, UART1 can be accessed from a Secure, Unprivileged context."] - #[inline(always)] - pub const fn su(&self) -> bool { - let val = (self.0 >> 2usize) & 0x01; - val != 0 - } - #[doc = "If 1, and SP is also set, UART1 can be accessed from a Secure, Unprivileged context."] - #[inline(always)] - pub fn set_su(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 2usize)) | (((val as u32) & 0x01) << 2usize); - } - #[doc = "If 1, UART1 can be accessed from a Secure, Privileged context."] - #[inline(always)] - pub const fn sp(&self) -> bool { - let val = (self.0 >> 3usize) & 0x01; - val != 0 - } - #[doc = "If 1, UART1 can be accessed from a Secure, Privileged context."] - #[inline(always)] - pub fn set_sp(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 3usize)) | (((val as u32) & 0x01) << 3usize); - } - #[doc = "If 1, UART1 can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] - #[inline(always)] - pub const fn core0(&self) -> bool { - let val = (self.0 >> 4usize) & 0x01; - val != 0 - } - #[doc = "If 1, UART1 can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] - #[inline(always)] - pub fn set_core0(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 4usize)) | (((val as u32) & 0x01) << 4usize); - } - #[doc = "If 1, UART1 can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] - #[inline(always)] - pub const fn core1(&self) -> bool { - let val = (self.0 >> 5usize) & 0x01; - val != 0 - } - #[doc = "If 1, UART1 can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] - #[inline(always)] - pub fn set_core1(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 5usize)) | (((val as u32) & 0x01) << 5usize); - } - #[doc = "If 1, UART1 can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] - #[inline(always)] - pub const fn dma(&self) -> bool { - let val = (self.0 >> 6usize) & 0x01; - val != 0 - } - #[doc = "If 1, UART1 can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] - #[inline(always)] - pub fn set_dma(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 6usize)) | (((val as u32) & 0x01) << 6usize); - } - #[doc = "If 1, UART1 can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] - #[inline(always)] - pub const fn dbg(&self) -> bool { - let val = (self.0 >> 7usize) & 0x01; - val != 0 - } - #[doc = "If 1, UART1 can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] - #[inline(always)] - pub fn set_dbg(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 7usize)) | (((val as u32) & 0x01) << 7usize); - } -} -impl Default for Uart1 { - #[inline(always)] - fn default() -> Uart1 { - Uart1(0) - } -} -#[doc = "Control whether debugger, DMA, core 0 and core 1 can access USBCTRL, and at what security/privilege levels they can do so. Defaults to Secure access from any master. This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set."] -#[repr(transparent)] -#[derive(Copy, Clone, Eq, PartialEq)] -pub struct Usbctrl(pub u32); -impl Usbctrl { - #[doc = "If 1, and NSP is also set, USBCTRL can be accessed from a Non-secure, Unprivileged context. This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set."] - #[inline(always)] - pub const fn nsu(&self) -> bool { - let val = (self.0 >> 0usize) & 0x01; - val != 0 - } - #[doc = "If 1, and NSP is also set, USBCTRL can be accessed from a Non-secure, Unprivileged context. This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set."] - #[inline(always)] - pub fn set_nsu(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize); - } - #[doc = "If 1, USBCTRL can be accessed from a Non-secure, Privileged context."] - #[inline(always)] - pub const fn nsp(&self) -> bool { - let val = (self.0 >> 1usize) & 0x01; - val != 0 - } - #[doc = "If 1, USBCTRL can be accessed from a Non-secure, Privileged context."] - #[inline(always)] - pub fn set_nsp(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize); - } - #[doc = "If 1, and SP is also set, USBCTRL can be accessed from a Secure, Unprivileged context."] - #[inline(always)] - pub const fn su(&self) -> bool { - let val = (self.0 >> 2usize) & 0x01; - val != 0 - } - #[doc = "If 1, and SP is also set, USBCTRL can be accessed from a Secure, Unprivileged context."] - #[inline(always)] - pub fn set_su(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 2usize)) | (((val as u32) & 0x01) << 2usize); - } - #[doc = "If 1, USBCTRL can be accessed from a Secure, Privileged context."] - #[inline(always)] - pub const fn sp(&self) -> bool { - let val = (self.0 >> 3usize) & 0x01; - val != 0 - } - #[doc = "If 1, USBCTRL can be accessed from a Secure, Privileged context."] - #[inline(always)] - pub fn set_sp(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 3usize)) | (((val as u32) & 0x01) << 3usize); - } - #[doc = "If 1, USBCTRL can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] - #[inline(always)] - pub const fn core0(&self) -> bool { - let val = (self.0 >> 4usize) & 0x01; - val != 0 - } - #[doc = "If 1, USBCTRL can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] - #[inline(always)] - pub fn set_core0(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 4usize)) | (((val as u32) & 0x01) << 4usize); - } - #[doc = "If 1, USBCTRL can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] - #[inline(always)] - pub const fn core1(&self) -> bool { - let val = (self.0 >> 5usize) & 0x01; - val != 0 - } - #[doc = "If 1, USBCTRL can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] - #[inline(always)] - pub fn set_core1(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 5usize)) | (((val as u32) & 0x01) << 5usize); - } - #[doc = "If 1, USBCTRL can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] - #[inline(always)] - pub const fn dma(&self) -> bool { - let val = (self.0 >> 6usize) & 0x01; - val != 0 - } - #[doc = "If 1, USBCTRL can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] - #[inline(always)] - pub fn set_dma(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 6usize)) | (((val as u32) & 0x01) << 6usize); - } - #[doc = "If 1, USBCTRL can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] - #[inline(always)] - pub const fn dbg(&self) -> bool { - let val = (self.0 >> 7usize) & 0x01; - val != 0 - } - #[doc = "If 1, USBCTRL can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] - #[inline(always)] - pub fn set_dbg(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 7usize)) | (((val as u32) & 0x01) << 7usize); - } -} -impl Default for Usbctrl { - #[inline(always)] - fn default() -> Usbctrl { - Usbctrl(0) - } -} -#[doc = "Control whether debugger, DMA, core 0 and core 1 can access WATCHDOG, and at what security/privilege levels they can do so. Defaults to Secure, Privileged processor or debug access only. This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set."] -#[repr(transparent)] -#[derive(Copy, Clone, Eq, PartialEq)] -pub struct Watchdog(pub u32); -impl Watchdog { - #[doc = "If 1, and NSP is also set, WATCHDOG can be accessed from a Non-secure, Unprivileged context. This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set."] - #[inline(always)] - pub const fn nsu(&self) -> bool { - let val = (self.0 >> 0usize) & 0x01; - val != 0 - } - #[doc = "If 1, and NSP is also set, WATCHDOG can be accessed from a Non-secure, Unprivileged context. This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set."] - #[inline(always)] - pub fn set_nsu(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize); - } - #[doc = "If 1, WATCHDOG can be accessed from a Non-secure, Privileged context."] - #[inline(always)] - pub const fn nsp(&self) -> bool { - let val = (self.0 >> 1usize) & 0x01; - val != 0 - } - #[doc = "If 1, WATCHDOG can be accessed from a Non-secure, Privileged context."] - #[inline(always)] - pub fn set_nsp(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize); - } - #[doc = "If 1, and SP is also set, WATCHDOG can be accessed from a Secure, Unprivileged context."] - #[inline(always)] - pub const fn su(&self) -> bool { - let val = (self.0 >> 2usize) & 0x01; - val != 0 - } - #[doc = "If 1, and SP is also set, WATCHDOG can be accessed from a Secure, Unprivileged context."] - #[inline(always)] - pub fn set_su(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 2usize)) | (((val as u32) & 0x01) << 2usize); - } - #[doc = "If 1, WATCHDOG can be accessed from a Secure, Privileged context."] - #[inline(always)] - pub const fn sp(&self) -> bool { - let val = (self.0 >> 3usize) & 0x01; - val != 0 - } - #[doc = "If 1, WATCHDOG can be accessed from a Secure, Privileged context."] - #[inline(always)] - pub fn set_sp(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 3usize)) | (((val as u32) & 0x01) << 3usize); - } - #[doc = "If 1, WATCHDOG can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] - #[inline(always)] - pub const fn core0(&self) -> bool { - let val = (self.0 >> 4usize) & 0x01; - val != 0 - } - #[doc = "If 1, WATCHDOG can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] - #[inline(always)] - pub fn set_core0(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 4usize)) | (((val as u32) & 0x01) << 4usize); - } - #[doc = "If 1, WATCHDOG can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] - #[inline(always)] - pub const fn core1(&self) -> bool { - let val = (self.0 >> 5usize) & 0x01; - val != 0 - } - #[doc = "If 1, WATCHDOG can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] - #[inline(always)] - pub fn set_core1(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 5usize)) | (((val as u32) & 0x01) << 5usize); - } - #[doc = "If 1, WATCHDOG can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] - #[inline(always)] - pub const fn dma(&self) -> bool { - let val = (self.0 >> 6usize) & 0x01; - val != 0 - } - #[doc = "If 1, WATCHDOG can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] - #[inline(always)] - pub fn set_dma(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 6usize)) | (((val as u32) & 0x01) << 6usize); - } - #[doc = "If 1, WATCHDOG can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] - #[inline(always)] - pub const fn dbg(&self) -> bool { - let val = (self.0 >> 7usize) & 0x01; - val != 0 - } - #[doc = "If 1, WATCHDOG can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] - #[inline(always)] - pub fn set_dbg(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 7usize)) | (((val as u32) & 0x01) << 7usize); - } -} -impl Default for Watchdog { - #[inline(always)] - fn default() -> Watchdog { - Watchdog(0) - } -} -#[doc = "Control whether debugger, DMA, core 0 and core 1 can access XIP_AUX, and at what security/privilege levels they can do so. Defaults to Secure, Privileged access only. This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set."] -#[repr(transparent)] -#[derive(Copy, Clone, Eq, PartialEq)] -pub struct XipAux(pub u32); -impl XipAux { - #[doc = "If 1, and NSP is also set, XIP_AUX can be accessed from a Non-secure, Unprivileged context. This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set."] - #[inline(always)] - pub const fn nsu(&self) -> bool { - let val = (self.0 >> 0usize) & 0x01; - val != 0 - } - #[doc = "If 1, and NSP is also set, XIP_AUX can be accessed from a Non-secure, Unprivileged context. This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set."] - #[inline(always)] - pub fn set_nsu(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize); - } - #[doc = "If 1, XIP_AUX can be accessed from a Non-secure, Privileged context."] - #[inline(always)] - pub const fn nsp(&self) -> bool { - let val = (self.0 >> 1usize) & 0x01; - val != 0 - } - #[doc = "If 1, XIP_AUX can be accessed from a Non-secure, Privileged context."] - #[inline(always)] - pub fn set_nsp(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize); - } - #[doc = "If 1, and SP is also set, XIP_AUX can be accessed from a Secure, Unprivileged context."] - #[inline(always)] - pub const fn su(&self) -> bool { - let val = (self.0 >> 2usize) & 0x01; - val != 0 - } - #[doc = "If 1, and SP is also set, XIP_AUX can be accessed from a Secure, Unprivileged context."] - #[inline(always)] - pub fn set_su(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 2usize)) | (((val as u32) & 0x01) << 2usize); - } - #[doc = "If 1, XIP_AUX can be accessed from a Secure, Privileged context."] - #[inline(always)] - pub const fn sp(&self) -> bool { - let val = (self.0 >> 3usize) & 0x01; - val != 0 - } - #[doc = "If 1, XIP_AUX can be accessed from a Secure, Privileged context."] - #[inline(always)] - pub fn set_sp(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 3usize)) | (((val as u32) & 0x01) << 3usize); - } - #[doc = "If 1, XIP_AUX can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] - #[inline(always)] - pub const fn core0(&self) -> bool { - let val = (self.0 >> 4usize) & 0x01; - val != 0 - } - #[doc = "If 1, XIP_AUX can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] - #[inline(always)] - pub fn set_core0(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 4usize)) | (((val as u32) & 0x01) << 4usize); - } - #[doc = "If 1, XIP_AUX can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] - #[inline(always)] - pub const fn core1(&self) -> bool { - let val = (self.0 >> 5usize) & 0x01; - val != 0 - } - #[doc = "If 1, XIP_AUX can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] - #[inline(always)] - pub fn set_core1(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 5usize)) | (((val as u32) & 0x01) << 5usize); - } - #[doc = "If 1, XIP_AUX can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] - #[inline(always)] - pub const fn dma(&self) -> bool { - let val = (self.0 >> 6usize) & 0x01; - val != 0 - } - #[doc = "If 1, XIP_AUX can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] - #[inline(always)] - pub fn set_dma(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 6usize)) | (((val as u32) & 0x01) << 6usize); - } - #[doc = "If 1, XIP_AUX can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] - #[inline(always)] - pub const fn dbg(&self) -> bool { - let val = (self.0 >> 7usize) & 0x01; - val != 0 - } - #[doc = "If 1, XIP_AUX can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] - #[inline(always)] - pub fn set_dbg(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 7usize)) | (((val as u32) & 0x01) << 7usize); - } -} -impl Default for XipAux { - #[inline(always)] - fn default() -> XipAux { - XipAux(0) - } -} -#[doc = "Control whether debugger, DMA, core 0 and core 1 can access XIP_CTRL, and at what security/privilege levels they can do so. Defaults to Secure, Privileged processor or debug access only. This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set."] -#[repr(transparent)] -#[derive(Copy, Clone, Eq, PartialEq)] -pub struct XipCtrl(pub u32); -impl XipCtrl { - #[doc = "If 1, and NSP is also set, XIP_CTRL can be accessed from a Non-secure, Unprivileged context. This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set."] - #[inline(always)] - pub const fn nsu(&self) -> bool { - let val = (self.0 >> 0usize) & 0x01; - val != 0 - } - #[doc = "If 1, and NSP is also set, XIP_CTRL can be accessed from a Non-secure, Unprivileged context. This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set."] - #[inline(always)] - pub fn set_nsu(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize); - } - #[doc = "If 1, XIP_CTRL can be accessed from a Non-secure, Privileged context."] - #[inline(always)] - pub const fn nsp(&self) -> bool { - let val = (self.0 >> 1usize) & 0x01; - val != 0 - } - #[doc = "If 1, XIP_CTRL can be accessed from a Non-secure, Privileged context."] - #[inline(always)] - pub fn set_nsp(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize); - } - #[doc = "If 1, and SP is also set, XIP_CTRL can be accessed from a Secure, Unprivileged context."] - #[inline(always)] - pub const fn su(&self) -> bool { - let val = (self.0 >> 2usize) & 0x01; - val != 0 - } - #[doc = "If 1, and SP is also set, XIP_CTRL can be accessed from a Secure, Unprivileged context."] - #[inline(always)] - pub fn set_su(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 2usize)) | (((val as u32) & 0x01) << 2usize); - } - #[doc = "If 1, XIP_CTRL can be accessed from a Secure, Privileged context."] - #[inline(always)] - pub const fn sp(&self) -> bool { - let val = (self.0 >> 3usize) & 0x01; - val != 0 - } - #[doc = "If 1, XIP_CTRL can be accessed from a Secure, Privileged context."] - #[inline(always)] - pub fn set_sp(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 3usize)) | (((val as u32) & 0x01) << 3usize); - } - #[doc = "If 1, XIP_CTRL can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] - #[inline(always)] - pub const fn core0(&self) -> bool { - let val = (self.0 >> 4usize) & 0x01; - val != 0 - } - #[doc = "If 1, XIP_CTRL can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] - #[inline(always)] - pub fn set_core0(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 4usize)) | (((val as u32) & 0x01) << 4usize); - } - #[doc = "If 1, XIP_CTRL can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] - #[inline(always)] - pub const fn core1(&self) -> bool { - let val = (self.0 >> 5usize) & 0x01; - val != 0 - } - #[doc = "If 1, XIP_CTRL can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] - #[inline(always)] - pub fn set_core1(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 5usize)) | (((val as u32) & 0x01) << 5usize); - } - #[doc = "If 1, XIP_CTRL can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] - #[inline(always)] - pub const fn dma(&self) -> bool { - let val = (self.0 >> 6usize) & 0x01; - val != 0 - } - #[doc = "If 1, XIP_CTRL can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] - #[inline(always)] - pub fn set_dma(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 6usize)) | (((val as u32) & 0x01) << 6usize); - } - #[doc = "If 1, XIP_CTRL can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] - #[inline(always)] - pub const fn dbg(&self) -> bool { - let val = (self.0 >> 7usize) & 0x01; - val != 0 - } - #[doc = "If 1, XIP_CTRL can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] - #[inline(always)] - pub fn set_dbg(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 7usize)) | (((val as u32) & 0x01) << 7usize); - } -} -impl Default for XipCtrl { - #[inline(always)] - fn default() -> XipCtrl { - XipCtrl(0) - } -} -#[doc = "Control whether debugger, DMA, core 0 and core 1 can access XIP_MAIN, and at what security/privilege levels they can do so. Defaults to fully open access. This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set."] -#[repr(transparent)] -#[derive(Copy, Clone, Eq, PartialEq)] -pub struct XipMain(pub u32); -impl XipMain { - #[doc = "If 1, and NSP is also set, XIP_MAIN can be accessed from a Non-secure, Unprivileged context. This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set."] - #[inline(always)] - pub const fn nsu(&self) -> bool { - let val = (self.0 >> 0usize) & 0x01; - val != 0 - } - #[doc = "If 1, and NSP is also set, XIP_MAIN can be accessed from a Non-secure, Unprivileged context. This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set."] - #[inline(always)] - pub fn set_nsu(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize); - } - #[doc = "If 1, XIP_MAIN can be accessed from a Non-secure, Privileged context."] - #[inline(always)] - pub const fn nsp(&self) -> bool { - let val = (self.0 >> 1usize) & 0x01; - val != 0 - } - #[doc = "If 1, XIP_MAIN can be accessed from a Non-secure, Privileged context."] - #[inline(always)] - pub fn set_nsp(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize); - } - #[doc = "If 1, and SP is also set, XIP_MAIN can be accessed from a Secure, Unprivileged context."] - #[inline(always)] - pub const fn su(&self) -> bool { - let val = (self.0 >> 2usize) & 0x01; - val != 0 - } - #[doc = "If 1, and SP is also set, XIP_MAIN can be accessed from a Secure, Unprivileged context."] - #[inline(always)] - pub fn set_su(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 2usize)) | (((val as u32) & 0x01) << 2usize); - } - #[doc = "If 1, XIP_MAIN can be accessed from a Secure, Privileged context."] - #[inline(always)] - pub const fn sp(&self) -> bool { - let val = (self.0 >> 3usize) & 0x01; - val != 0 - } - #[doc = "If 1, XIP_MAIN can be accessed from a Secure, Privileged context."] - #[inline(always)] - pub fn set_sp(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 3usize)) | (((val as u32) & 0x01) << 3usize); - } - #[doc = "If 1, XIP_MAIN can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] - #[inline(always)] - pub const fn core0(&self) -> bool { - let val = (self.0 >> 4usize) & 0x01; - val != 0 - } - #[doc = "If 1, XIP_MAIN can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] - #[inline(always)] - pub fn set_core0(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 4usize)) | (((val as u32) & 0x01) << 4usize); - } - #[doc = "If 1, XIP_MAIN can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] - #[inline(always)] - pub const fn core1(&self) -> bool { - let val = (self.0 >> 5usize) & 0x01; - val != 0 - } - #[doc = "If 1, XIP_MAIN can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] - #[inline(always)] - pub fn set_core1(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 5usize)) | (((val as u32) & 0x01) << 5usize); - } - #[doc = "If 1, XIP_MAIN can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] - #[inline(always)] - pub const fn dma(&self) -> bool { - let val = (self.0 >> 6usize) & 0x01; - val != 0 - } - #[doc = "If 1, XIP_MAIN can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] - #[inline(always)] - pub fn set_dma(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 6usize)) | (((val as u32) & 0x01) << 6usize); - } - #[doc = "If 1, XIP_MAIN can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] - #[inline(always)] - pub const fn dbg(&self) -> bool { - let val = (self.0 >> 7usize) & 0x01; - val != 0 - } - #[doc = "If 1, XIP_MAIN can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] - #[inline(always)] - pub fn set_dbg(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 7usize)) | (((val as u32) & 0x01) << 7usize); - } -} -impl Default for XipMain { - #[inline(always)] - fn default() -> XipMain { - XipMain(0) - } -} -#[doc = "Control whether debugger, DMA, core 0 and core 1 can access XIP_QMI, and at what security/privilege levels they can do so. Defaults to Secure, Privileged processor or debug access only. This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set."] -#[repr(transparent)] -#[derive(Copy, Clone, Eq, PartialEq)] -pub struct XipQmi(pub u32); -impl XipQmi { - #[doc = "If 1, and NSP is also set, XIP_QMI can be accessed from a Non-secure, Unprivileged context. This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set."] - #[inline(always)] - pub const fn nsu(&self) -> bool { - let val = (self.0 >> 0usize) & 0x01; - val != 0 - } - #[doc = "If 1, and NSP is also set, XIP_QMI can be accessed from a Non-secure, Unprivileged context. This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set."] - #[inline(always)] - pub fn set_nsu(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize); - } - #[doc = "If 1, XIP_QMI can be accessed from a Non-secure, Privileged context."] - #[inline(always)] - pub const fn nsp(&self) -> bool { - let val = (self.0 >> 1usize) & 0x01; - val != 0 - } - #[doc = "If 1, XIP_QMI can be accessed from a Non-secure, Privileged context."] - #[inline(always)] - pub fn set_nsp(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize); - } - #[doc = "If 1, and SP is also set, XIP_QMI can be accessed from a Secure, Unprivileged context."] - #[inline(always)] - pub const fn su(&self) -> bool { - let val = (self.0 >> 2usize) & 0x01; - val != 0 - } - #[doc = "If 1, and SP is also set, XIP_QMI can be accessed from a Secure, Unprivileged context."] - #[inline(always)] - pub fn set_su(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 2usize)) | (((val as u32) & 0x01) << 2usize); - } - #[doc = "If 1, XIP_QMI can be accessed from a Secure, Privileged context."] - #[inline(always)] - pub const fn sp(&self) -> bool { - let val = (self.0 >> 3usize) & 0x01; - val != 0 - } - #[doc = "If 1, XIP_QMI can be accessed from a Secure, Privileged context."] - #[inline(always)] - pub fn set_sp(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 3usize)) | (((val as u32) & 0x01) << 3usize); - } - #[doc = "If 1, XIP_QMI can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] - #[inline(always)] - pub const fn core0(&self) -> bool { - let val = (self.0 >> 4usize) & 0x01; - val != 0 - } - #[doc = "If 1, XIP_QMI can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] - #[inline(always)] - pub fn set_core0(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 4usize)) | (((val as u32) & 0x01) << 4usize); - } - #[doc = "If 1, XIP_QMI can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] - #[inline(always)] - pub const fn core1(&self) -> bool { - let val = (self.0 >> 5usize) & 0x01; - val != 0 - } - #[doc = "If 1, XIP_QMI can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] - #[inline(always)] - pub fn set_core1(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 5usize)) | (((val as u32) & 0x01) << 5usize); - } - #[doc = "If 1, XIP_QMI can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] - #[inline(always)] - pub const fn dma(&self) -> bool { - let val = (self.0 >> 6usize) & 0x01; - val != 0 - } - #[doc = "If 1, XIP_QMI can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] - #[inline(always)] - pub fn set_dma(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 6usize)) | (((val as u32) & 0x01) << 6usize); - } - #[doc = "If 1, XIP_QMI can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] - #[inline(always)] - pub const fn dbg(&self) -> bool { - let val = (self.0 >> 7usize) & 0x01; - val != 0 - } - #[doc = "If 1, XIP_QMI can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] - #[inline(always)] - pub fn set_dbg(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 7usize)) | (((val as u32) & 0x01) << 7usize); - } -} -impl Default for XipQmi { - #[inline(always)] - fn default() -> XipQmi { - XipQmi(0) - } -} -#[doc = "Control whether debugger, DMA, core 0 and core 1 can access XOSC, and at what security/privilege levels they can do so. Defaults to Secure, Privileged processor or debug access only. This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set."] -#[repr(transparent)] -#[derive(Copy, Clone, Eq, PartialEq)] -pub struct Xosc(pub u32); -impl Xosc { - #[doc = "If 1, and NSP is also set, XOSC can be accessed from a Non-secure, Unprivileged context. This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set."] - #[inline(always)] - pub const fn nsu(&self) -> bool { - let val = (self.0 >> 0usize) & 0x01; - val != 0 - } - #[doc = "If 1, and NSP is also set, XOSC can be accessed from a Non-secure, Unprivileged context. This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set."] - #[inline(always)] - pub fn set_nsu(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize); - } - #[doc = "If 1, XOSC can be accessed from a Non-secure, Privileged context."] - #[inline(always)] - pub const fn nsp(&self) -> bool { - let val = (self.0 >> 1usize) & 0x01; - val != 0 - } - #[doc = "If 1, XOSC can be accessed from a Non-secure, Privileged context."] - #[inline(always)] - pub fn set_nsp(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize); - } - #[doc = "If 1, and SP is also set, XOSC can be accessed from a Secure, Unprivileged context."] - #[inline(always)] - pub const fn su(&self) -> bool { - let val = (self.0 >> 2usize) & 0x01; - val != 0 - } - #[doc = "If 1, and SP is also set, XOSC can be accessed from a Secure, Unprivileged context."] - #[inline(always)] - pub fn set_su(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 2usize)) | (((val as u32) & 0x01) << 2usize); - } - #[doc = "If 1, XOSC can be accessed from a Secure, Privileged context."] - #[inline(always)] - pub const fn sp(&self) -> bool { - let val = (self.0 >> 3usize) & 0x01; - val != 0 - } - #[doc = "If 1, XOSC can be accessed from a Secure, Privileged context."] - #[inline(always)] - pub fn set_sp(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 3usize)) | (((val as u32) & 0x01) << 3usize); - } - #[doc = "If 1, XOSC can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] - #[inline(always)] - pub const fn core0(&self) -> bool { - let val = (self.0 >> 4usize) & 0x01; - val != 0 - } - #[doc = "If 1, XOSC can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] - #[inline(always)] - pub fn set_core0(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 4usize)) | (((val as u32) & 0x01) << 4usize); - } - #[doc = "If 1, XOSC can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] - #[inline(always)] - pub const fn core1(&self) -> bool { - let val = (self.0 >> 5usize) & 0x01; - val != 0 - } - #[doc = "If 1, XOSC can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] - #[inline(always)] - pub fn set_core1(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 5usize)) | (((val as u32) & 0x01) << 5usize); - } - #[doc = "If 1, XOSC can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] - #[inline(always)] - pub const fn dma(&self) -> bool { - let val = (self.0 >> 6usize) & 0x01; - val != 0 - } - #[doc = "If 1, XOSC can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] - #[inline(always)] - pub fn set_dma(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 6usize)) | (((val as u32) & 0x01) << 6usize); - } - #[doc = "If 1, XOSC can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] - #[inline(always)] - pub const fn dbg(&self) -> bool { - let val = (self.0 >> 7usize) & 0x01; - val != 0 - } - #[doc = "If 1, XOSC can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] - #[inline(always)] - pub fn set_dbg(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 7usize)) | (((val as u32) & 0x01) << 7usize); - } -} -impl Default for Xosc { - #[inline(always)] - fn default() -> Xosc { - Xosc(0) + fn default() -> Lock { + Lock(0) } } diff --git a/src/rp235x/adc.rs b/src/rp235x/adc.rs index 1027f21b..88b82c78 100644 --- a/src/rp235x/adc.rs +++ b/src/rp235x/adc.rs @@ -17,47 +17,47 @@ impl Adc { #[doc = "ADC Control and Status"] #[inline(always)] pub const fn cs(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(0usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x0usize) as _) } } #[doc = "Result of most recent ADC conversion"] #[inline(always)] pub const fn result(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(4usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x04usize) as _) } } #[doc = "FIFO control and status"] #[inline(always)] pub const fn fcs(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(8usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x08usize) as _) } } #[doc = "Conversion result FIFO"] #[inline(always)] pub const fn fifo(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(12usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x0cusize) as _) } } #[doc = "Clock divider. If non-zero, CS_START_MANY will start conversions at regular intervals rather than back-to-back. The divider is reset when either of these fields are written. Total period is 1 + INT + FRAC / 256"] #[inline(always)] pub const fn div(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(16usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x10usize) as _) } } #[doc = "Raw Interrupts"] #[inline(always)] pub const fn intr(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(20usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x14usize) as _) } } #[doc = "Interrupt Enable"] #[inline(always)] pub const fn inte(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(24usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x18usize) as _) } } #[doc = "Interrupt Force"] #[inline(always)] pub const fn intf(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(28usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x1cusize) as _) } } #[doc = "Interrupt status after masking & forcing"] #[inline(always)] pub const fn ints(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(32usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x20usize) as _) } } } pub mod regs; diff --git a/src/rp235x/adc/regs.rs b/src/rp235x/adc/regs.rs index 2cc7a939..a48baf48 100644 --- a/src/rp235x/adc/regs.rs +++ b/src/rp235x/adc/regs.rs @@ -293,7 +293,7 @@ impl Default for Fifo { Fifo(0) } } -#[doc = "Interrupt status after masking & forcing"] +#[doc = "Interrupt Force"] #[repr(transparent)] #[derive(Copy, Clone, Eq, PartialEq)] pub struct Int(pub u32); diff --git a/src/rp235x/bootram.rs b/src/rp235x/bootram.rs index 814cd79e..52d88e2a 100644 --- a/src/rp235x/bootram.rs +++ b/src/rp235x/bootram.rs @@ -17,57 +17,23 @@ impl Bootram { #[doc = "This registers always ORs writes into its current contents. Once a bit is set, it can only be cleared by a reset."] #[inline(always)] pub const fn write_once0(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(2048usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x0800usize) as _) } } #[doc = "This registers always ORs writes into its current contents. Once a bit is set, it can only be cleared by a reset."] #[inline(always)] pub const fn write_once1(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(2052usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x0804usize) as _) } } #[doc = "Bootlock status register. 1=unclaimed, 0=claimed. These locks function identically to the SIO spinlocks, but are reserved for bootrom use."] #[inline(always)] pub const fn bootlock_stat(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(2056usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x0808usize) as _) } } #[doc = "Read to claim and check. Write to unclaim. The value returned on successful claim is 1 << n, and on failed claim is zero."] #[inline(always)] - pub const fn bootlock0(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(2060usize) as _) } - } - #[doc = "Read to claim and check. Write to unclaim. The value returned on successful claim is 1 << n, and on failed claim is zero."] - #[inline(always)] - pub const fn bootlock1(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(2064usize) as _) } - } - #[doc = "Read to claim and check. Write to unclaim. The value returned on successful claim is 1 << n, and on failed claim is zero."] - #[inline(always)] - pub const fn bootlock2(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(2068usize) as _) } - } - #[doc = "Read to claim and check. Write to unclaim. The value returned on successful claim is 1 << n, and on failed claim is zero."] - #[inline(always)] - pub const fn bootlock3(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(2072usize) as _) } - } - #[doc = "Read to claim and check. Write to unclaim. The value returned on successful claim is 1 << n, and on failed claim is zero."] - #[inline(always)] - pub const fn bootlock4(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(2076usize) as _) } - } - #[doc = "Read to claim and check. Write to unclaim. The value returned on successful claim is 1 << n, and on failed claim is zero."] - #[inline(always)] - pub const fn bootlock5(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(2080usize) as _) } - } - #[doc = "Read to claim and check. Write to unclaim. The value returned on successful claim is 1 << n, and on failed claim is zero."] - #[inline(always)] - pub const fn bootlock6(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(2084usize) as _) } - } - #[doc = "Read to claim and check. Write to unclaim. The value returned on successful claim is 1 << n, and on failed claim is zero."] - #[inline(always)] - pub const fn bootlock7(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(2088usize) as _) } + pub const fn bootlock(self, n: usize) -> crate::common::Reg { + assert!(n < 8usize); + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x080cusize + n * 4usize) as _) } } } pub mod regs; diff --git a/src/rp235x/busctrl.rs b/src/rp235x/busctrl.rs index 851d4575..522ad2c1 100644 --- a/src/rp235x/busctrl.rs +++ b/src/rp235x/busctrl.rs @@ -17,31 +17,31 @@ impl Busctrl { #[doc = "Set the priority of each master for bus arbitration."] #[inline(always)] pub const fn bus_priority(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(0usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x0usize) as _) } } #[doc = "Bus priority acknowledge"] #[inline(always)] pub const fn bus_priority_ack( self, ) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(4usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x04usize) as _) } } #[doc = "Enable the performance counters. If 0, the performance counters do not increment. This can be used to precisely start/stop event sampling around the profiled section of code. The performance counters are initially disabled, to save energy."] #[inline(always)] pub const fn perfctr_en(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(8usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x08usize) as _) } } #[doc = "Bus fabric performance counter 0"] #[inline(always)] pub const fn perfctr(self, n: usize) -> crate::common::Reg { assert!(n < 4usize); - unsafe { crate::common::Reg::from_ptr(self.ptr.add(12usize + n * 8usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x0cusize + n * 8usize) as _) } } #[doc = "Bus fabric performance event select for PERFCTR0"] #[inline(always)] pub const fn perfsel(self, n: usize) -> crate::common::Reg { assert!(n < 4usize); - unsafe { crate::common::Reg::from_ptr(self.ptr.add(16usize + n * 8usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x10usize + n * 8usize) as _) } } } pub mod regs; diff --git a/src/rp235x/busctrl/regs.rs b/src/rp235x/busctrl/regs.rs index 1d041af4..8025066b 100644 --- a/src/rp235x/busctrl/regs.rs +++ b/src/rp235x/busctrl/regs.rs @@ -77,18 +77,18 @@ impl Default for BusPriorityAck { BusPriorityAck(0) } } -#[doc = "Bus fabric performance counter 2"] +#[doc = "Bus fabric performance counter 3"] #[repr(transparent)] #[derive(Copy, Clone, Eq, PartialEq)] pub struct Perfctr(pub u32); impl Perfctr { - #[doc = "Busfabric saturating performance counter 2 Count some event signal from the busfabric arbiters, if PERFCTR_EN is set. Write any value to clear. Select an event to count using PERFSEL2"] + #[doc = "Busfabric saturating performance counter 3 Count some event signal from the busfabric arbiters, if PERFCTR_EN is set. Write any value to clear. Select an event to count using PERFSEL3"] #[inline(always)] pub const fn perfctr(&self) -> u32 { let val = (self.0 >> 0usize) & 0x00ff_ffff; val as u32 } - #[doc = "Busfabric saturating performance counter 2 Count some event signal from the busfabric arbiters, if PERFCTR_EN is set. Write any value to clear. Select an event to count using PERFSEL2"] + #[doc = "Busfabric saturating performance counter 3 Count some event signal from the busfabric arbiters, if PERFCTR_EN is set. Write any value to clear. Select an event to count using PERFSEL3"] #[inline(always)] pub fn set_perfctr(&mut self, val: u32) { self.0 = (self.0 & !(0x00ff_ffff << 0usize)) | (((val as u32) & 0x00ff_ffff) << 0usize); diff --git a/src/rp235x/busctrl/vals.rs b/src/rp235x/busctrl/vals.rs index ea550a97..3d6a14d6 100644 --- a/src/rp235x/busctrl/vals.rs +++ b/src/rp235x/busctrl/vals.rs @@ -1,7 +1,7 @@ #[repr(u8)] #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] pub enum Perfsel { - SIOB_PROC1_STALL_UPSTREAM = 0, + SIOB_PROC1_STALL_UPSTREAM = 0x0, SIOB_PROC1_STALL_DOWNSTREAM = 0x01, SIOB_PROC1_ACCESS_CONTESTED = 0x02, SIOB_PROC1_ACCESS = 0x03, diff --git a/src/rp235x/clocks.rs b/src/rp235x/clocks.rs index 7a6b4841..5e8ffa7f 100644 --- a/src/rp235x/clocks.rs +++ b/src/rp235x/clocks.rs @@ -20,7 +20,7 @@ impl Clocks { n: usize, ) -> crate::common::Reg { assert!(n < 4usize); - unsafe { crate::common::Reg::from_ptr(self.ptr.add(0usize + n * 12usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x0usize + n * 12usize) as _) } } #[inline(always)] pub const fn clk_gpout_div( @@ -28,7 +28,7 @@ impl Clocks { n: usize, ) -> crate::common::Reg { assert!(n < 4usize); - unsafe { crate::common::Reg::from_ptr(self.ptr.add(4usize + n * 12usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x04usize + n * 12usize) as _) } } #[doc = "Indicates which src is currently selected (one-hot)"] #[inline(always)] @@ -37,223 +37,223 @@ impl Clocks { n: usize, ) -> crate::common::Reg { assert!(n < 4usize); - unsafe { crate::common::Reg::from_ptr(self.ptr.add(8usize + n * 12usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x08usize + n * 12usize) as _) } } #[doc = "Clock control, can be changed on-the-fly (except for auxsrc)"] #[inline(always)] pub const fn clk_ref_ctrl(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(48usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x30usize) as _) } } #[inline(always)] pub const fn clk_ref_div(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(52usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x34usize) as _) } } #[doc = "Indicates which src is currently selected (one-hot)"] #[inline(always)] pub const fn clk_ref_selected( self, ) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(56usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x38usize) as _) } } #[doc = "Clock control, can be changed on-the-fly (except for auxsrc)"] #[inline(always)] pub const fn clk_sys_ctrl(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(60usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x3cusize) as _) } } #[inline(always)] pub const fn clk_sys_div(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(64usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x40usize) as _) } } #[doc = "Indicates which src is currently selected (one-hot)"] #[inline(always)] pub const fn clk_sys_selected( self, ) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(68usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x44usize) as _) } } #[doc = "Clock control, can be changed on-the-fly (except for auxsrc)"] #[inline(always)] pub const fn clk_peri_ctrl(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(72usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x48usize) as _) } } #[inline(always)] pub const fn clk_peri_div(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(76usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x4cusize) as _) } } #[doc = "Indicates which src is currently selected (one-hot)"] #[inline(always)] pub const fn clk_peri_selected( self, ) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(80usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x50usize) as _) } } #[doc = "Clock control, can be changed on-the-fly (except for auxsrc)"] #[inline(always)] pub const fn clk_hstx_ctrl(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(84usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x54usize) as _) } } #[inline(always)] pub const fn clk_hstx_div(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(88usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x58usize) as _) } } #[doc = "Indicates which src is currently selected (one-hot)"] #[inline(always)] pub const fn clk_hstx_selected( self, ) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(92usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x5cusize) as _) } } #[doc = "Clock control, can be changed on-the-fly (except for auxsrc)"] #[inline(always)] pub const fn clk_usb_ctrl(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(96usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x60usize) as _) } } #[inline(always)] pub const fn clk_usb_div(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(100usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x64usize) as _) } } #[doc = "Indicates which src is currently selected (one-hot)"] #[inline(always)] pub const fn clk_usb_selected( self, ) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(104usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x68usize) as _) } } #[doc = "Clock control, can be changed on-the-fly (except for auxsrc)"] #[inline(always)] pub const fn clk_adc_ctrl(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(108usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x6cusize) as _) } } #[inline(always)] pub const fn clk_adc_div(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(112usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x70usize) as _) } } #[doc = "Indicates which src is currently selected (one-hot)"] #[inline(always)] pub const fn clk_adc_selected( self, ) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(116usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x74usize) as _) } } #[inline(always)] pub const fn dftclk_xosc_ctrl( self, ) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(120usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x78usize) as _) } } #[inline(always)] pub const fn dftclk_rosc_ctrl( self, ) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(124usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x7cusize) as _) } } #[inline(always)] pub const fn dftclk_lposc_ctrl( self, ) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(128usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x80usize) as _) } } #[inline(always)] pub const fn clk_sys_resus_ctrl( self, ) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(132usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x84usize) as _) } } #[inline(always)] pub const fn clk_sys_resus_status( self, ) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(136usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x88usize) as _) } } #[doc = "Reference clock frequency in kHz"] #[inline(always)] pub const fn fc0_ref_khz(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(140usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x8cusize) as _) } } #[doc = "Minimum pass frequency in kHz. This is optional. Set to 0 if you are not using the pass/fail flags"] #[inline(always)] pub const fn fc0_min_khz(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(144usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x90usize) as _) } } #[doc = "Maximum pass frequency in kHz. This is optional. Set to 0x1ffffff if you are not using the pass/fail flags"] #[inline(always)] pub const fn fc0_max_khz(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(148usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x94usize) as _) } } #[doc = "Delays the start of frequency counting to allow the mux to settle Delay is measured in multiples of the reference clock period"] #[inline(always)] pub const fn fc0_delay(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(152usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x98usize) as _) } } #[doc = "The test interval is 0.98us * 2**interval, but let's call it 1us * 2**interval The default gives a test interval of 250us"] #[inline(always)] pub const fn fc0_interval(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(156usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x9cusize) as _) } } #[doc = "Clock sent to frequency counter, set to 0 when not required Writing to this register initiates the frequency count"] #[inline(always)] pub const fn fc0_src(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(160usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0xa0usize) as _) } } #[doc = "Frequency counter status"] #[inline(always)] pub const fn fc0_status(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(164usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0xa4usize) as _) } } #[doc = "Result of frequency measurement, only valid when status_done=1"] #[inline(always)] pub const fn fc0_result(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(168usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0xa8usize) as _) } } #[doc = "enable clock in wake mode"] #[inline(always)] pub const fn wake_en0(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(172usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0xacusize) as _) } } #[doc = "enable clock in wake mode"] #[inline(always)] pub const fn wake_en1(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(176usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0xb0usize) as _) } } #[doc = "enable clock in sleep mode"] #[inline(always)] pub const fn sleep_en0(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(180usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0xb4usize) as _) } } #[doc = "enable clock in sleep mode"] #[inline(always)] pub const fn sleep_en1(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(184usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0xb8usize) as _) } } #[doc = "indicates the state of the clock enable"] #[inline(always)] pub const fn enabled0(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(188usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0xbcusize) as _) } } #[doc = "indicates the state of the clock enable"] #[inline(always)] pub const fn enabled1(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(192usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0xc0usize) as _) } } #[doc = "Raw Interrupts"] #[inline(always)] pub const fn intr(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(196usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0xc4usize) as _) } } #[doc = "Interrupt Enable"] #[inline(always)] pub const fn inte(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(200usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0xc8usize) as _) } } #[doc = "Interrupt Force"] #[inline(always)] pub const fn intf(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(204usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0xccusize) as _) } } #[doc = "Interrupt status after masking & forcing"] #[inline(always)] pub const fn ints(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(208usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0xd0usize) as _) } } } pub mod regs; diff --git a/src/rp235x/clocks/regs.rs b/src/rp235x/clocks/regs.rs index 83df4a8d..eea6122d 100644 --- a/src/rp235x/clocks/regs.rs +++ b/src/rp235x/clocks/regs.rs @@ -1835,7 +1835,7 @@ impl Default for Fc0status { Fc0status(0) } } -#[doc = "Interrupt Force"] +#[doc = "Interrupt status after masking & forcing"] #[repr(transparent)] #[derive(Copy, Clone, Eq, PartialEq)] pub struct Int(pub u32); diff --git a/src/rp235x/clocks/vals.rs b/src/rp235x/clocks/vals.rs index de6752eb..27fd16c8 100644 --- a/src/rp235x/clocks/vals.rs +++ b/src/rp235x/clocks/vals.rs @@ -1,7 +1,7 @@ #[repr(u8)] #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] pub enum ClkAdcCtrlAuxsrc { - CLKSRC_PLL_USB = 0, + CLKSRC_PLL_USB = 0x0, CLKSRC_PLL_SYS = 0x01, ROSC_CLKSRC_PH = 0x02, XOSC_CLKSRC = 0x03, @@ -35,7 +35,7 @@ impl From for u8 { #[repr(u8)] #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] pub enum ClkGpoutCtrlAuxsrc { - CLKSRC_PLL_SYS = 0, + CLKSRC_PLL_SYS = 0x0, CLKSRC_GPIN0 = 0x01, CLKSRC_GPIN1 = 0x02, CLKSRC_PLL_USB = 0x03, @@ -77,7 +77,7 @@ impl From for u8 { #[repr(u8)] #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] pub enum ClkHstxCtrlAuxsrc { - CLK_SYS = 0, + CLK_SYS = 0x0, CLKSRC_PLL_SYS = 0x01, CLKSRC_PLL_USB = 0x02, CLKSRC_GPIN0 = 0x03, @@ -111,7 +111,7 @@ impl From for u8 { #[repr(u8)] #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] pub enum ClkPeriCtrlAuxsrc { - CLK_SYS = 0, + CLK_SYS = 0x0, CLKSRC_PLL_SYS = 0x01, CLKSRC_PLL_USB = 0x02, ROSC_CLKSRC_PH = 0x03, @@ -145,7 +145,7 @@ impl From for u8 { #[repr(u8)] #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] pub enum ClkRefCtrlAuxsrc { - CLKSRC_PLL_USB = 0, + CLKSRC_PLL_USB = 0x0, CLKSRC_GPIN0 = 0x01, CLKSRC_GPIN1 = 0x02, CLKSRC_PLL_USB_PRIMARY_REF_OPCG = 0x03, @@ -175,7 +175,7 @@ impl From for u8 { #[repr(u8)] #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] pub enum ClkRefCtrlSrc { - ROSC_CLKSRC_PH = 0, + ROSC_CLKSRC_PH = 0x0, CLKSRC_CLK_REF_AUX = 0x01, XOSC_CLKSRC = 0x02, LPOSC_CLKSRC = 0x03, @@ -205,7 +205,7 @@ impl From for u8 { #[repr(u8)] #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] pub enum ClkSysCtrlAuxsrc { - CLKSRC_PLL_SYS = 0, + CLKSRC_PLL_SYS = 0x0, CLKSRC_PLL_USB = 0x01, ROSC_CLKSRC = 0x02, XOSC_CLKSRC = 0x03, @@ -239,7 +239,7 @@ impl From for u8 { #[repr(u8)] #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] pub enum ClkSysCtrlSrc { - CLK_REF = 0, + CLK_REF = 0x0, CLKSRC_CLK_SYS_AUX = 0x01, } impl ClkSysCtrlSrc { @@ -267,7 +267,7 @@ impl From for u8 { #[repr(u8)] #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] pub enum ClkUsbCtrlAuxsrc { - CLKSRC_PLL_USB = 0, + CLKSRC_PLL_USB = 0x0, CLKSRC_PLL_SYS = 0x01, ROSC_CLKSRC_PH = 0x02, XOSC_CLKSRC = 0x03, @@ -301,7 +301,7 @@ impl From for u8 { #[repr(u8)] #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] pub enum DftclkLposcCtrlSrc { - NULL = 0, + NULL = 0x0, CLKSRC_PLL_USB_PRIMARY_LPOSC = 0x01, CLKSRC_GPIN1 = 0x02, _RESERVED_3 = 0x03, @@ -331,7 +331,7 @@ impl From for u8 { #[repr(u8)] #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] pub enum DftclkRoscCtrlSrc { - NULL = 0, + NULL = 0x0, CLKSRC_PLL_SYS_PRIMARY_ROSC = 0x01, CLKSRC_GPIN1 = 0x02, _RESERVED_3 = 0x03, @@ -361,7 +361,7 @@ impl From for u8 { #[repr(u8)] #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] pub enum DftclkXoscCtrlSrc { - NULL = 0, + NULL = 0x0, CLKSRC_PLL_USB_PRIMARY = 0x01, CLKSRC_GPIN0 = 0x02, _RESERVED_3 = 0x03, @@ -391,7 +391,7 @@ impl From for u8 { #[repr(u8)] #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] pub enum Fc0src { - NULL = 0, + NULL = 0x0, PLL_SYS_CLKSRC_PRIMARY = 0x01, PLL_USB_CLKSRC_PRIMARY = 0x02, ROSC_CLKSRC = 0x03, diff --git a/src/rp235x/coresight_trace.rs b/src/rp235x/coresight_trace.rs index fa01ad9c..597bab57 100644 --- a/src/rp235x/coresight_trace.rs +++ b/src/rp235x/coresight_trace.rs @@ -17,12 +17,12 @@ impl CoresightTrace { #[doc = "Control and status register"] #[inline(always)] pub const fn ctrl_status(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(0usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x0usize) as _) } } #[doc = "FIFO for trace data captured from the TPIU"] #[inline(always)] pub const fn trace_capture_fifo(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(4usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x04usize) as _) } } } pub mod regs; diff --git a/src/rp235x/dma.rs b/src/rp235x/dma.rs index e29ae21b..d9e05262 100644 --- a/src/rp235x/dma.rs +++ b/src/rp235x/dma.rs @@ -13,95 +13,95 @@ impl Channel { pub const fn as_ptr(&self) -> *mut () { self.ptr as _ } - #[doc = "DMA Channel 14 Read Address pointer"] + #[doc = "DMA Channel 12 Read Address pointer"] #[inline(always)] pub const fn read_addr(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(0usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x0usize) as _) } } - #[doc = "DMA Channel 14 Write Address pointer"] + #[doc = "DMA Channel 12 Write Address pointer"] #[inline(always)] pub const fn write_addr(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(4usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x04usize) as _) } } - #[doc = "DMA Channel 14 Transfer Count"] + #[doc = "DMA Channel 12 Transfer Count"] #[inline(always)] - pub const fn trans_count(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(8usize) as _) } + pub const fn trans_count(self) -> crate::common::Reg { + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x08usize) as _) } } - #[doc = "DMA Channel 14 Control and Status"] + #[doc = "DMA Channel 12 Control and Status"] #[inline(always)] pub const fn ctrl_trig(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(12usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x0cusize) as _) } } - #[doc = "Alias for channel 14 CTRL register"] + #[doc = "Alias for channel 12 CTRL register"] #[inline(always)] pub const fn al1_ctrl(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(16usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x10usize) as _) } } - #[doc = "Alias for channel 14 READ_ADDR register"] + #[doc = "Alias for channel 12 READ_ADDR register"] #[inline(always)] pub const fn al1_read_addr(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(20usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x14usize) as _) } } - #[doc = "Alias for channel 14 WRITE_ADDR register"] + #[doc = "Alias for channel 12 WRITE_ADDR register"] #[inline(always)] pub const fn al1_write_addr(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(24usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x18usize) as _) } } - #[doc = "Alias for channel 14 TRANS_COUNT register This is a trigger register (0xc). Writing a nonzero value will reload the channel counter and start the channel."] + #[doc = "Alias for channel 12 TRANS_COUNT register This is a trigger register (0xc). Writing a nonzero value will reload the channel counter and start the channel."] #[inline(always)] pub const fn al1_trans_count_trig(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(28usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x1cusize) as _) } } - #[doc = "Alias for channel 14 CTRL register"] + #[doc = "Alias for channel 12 CTRL register"] #[inline(always)] pub const fn al2_ctrl(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(32usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x20usize) as _) } } - #[doc = "Alias for channel 14 TRANS_COUNT register"] + #[doc = "Alias for channel 12 TRANS_COUNT register"] #[inline(always)] pub const fn al2_trans_count(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(36usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x24usize) as _) } } - #[doc = "Alias for channel 14 READ_ADDR register"] + #[doc = "Alias for channel 12 READ_ADDR register"] #[inline(always)] pub const fn al2_read_addr(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(40usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x28usize) as _) } } - #[doc = "Alias for channel 14 WRITE_ADDR register This is a trigger register (0xc). Writing a nonzero value will reload the channel counter and start the channel."] + #[doc = "Alias for channel 12 WRITE_ADDR register This is a trigger register (0xc). Writing a nonzero value will reload the channel counter and start the channel."] #[inline(always)] pub const fn al2_write_addr_trig(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(44usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x2cusize) as _) } } - #[doc = "Alias for channel 14 CTRL register"] + #[doc = "Alias for channel 12 CTRL register"] #[inline(always)] pub const fn al3_ctrl(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(48usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x30usize) as _) } } - #[doc = "Alias for channel 14 WRITE_ADDR register"] + #[doc = "Alias for channel 12 WRITE_ADDR register"] #[inline(always)] pub const fn al3_write_addr(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(52usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x34usize) as _) } } - #[doc = "Alias for channel 14 TRANS_COUNT register"] + #[doc = "Alias for channel 12 TRANS_COUNT register"] #[inline(always)] pub const fn al3_trans_count(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(56usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x38usize) as _) } } - #[doc = "Alias for channel 14 READ_ADDR register This is a trigger register (0xc). Writing a nonzero value will reload the channel counter and start the channel."] + #[doc = "Alias for channel 12 READ_ADDR register This is a trigger register (0xc). Writing a nonzero value will reload the channel counter and start the channel."] #[inline(always)] pub const fn al3_read_addr_trig(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(60usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x3cusize) as _) } } #[doc = "Read: get channel DREQ counter (i.e. how many accesses the DMA expects it can perform on the peripheral without overflow/underflow. Write any value: clears the counter, and cause channel to re-initiate DREQ handshake."] #[inline(always)] pub const fn dbg_ctdreq(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(2048usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x0800usize) as _) } } #[doc = "Read to get channel TRANS_COUNT reload value, i.e. the length of the next transfer"] #[inline(always)] pub const fn dbg_tcr(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(2052usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x0804usize) as _) } } } #[doc = "DMA with separate read and write masters"] @@ -123,315 +123,109 @@ impl Dma { #[inline(always)] pub const fn ch(self, n: usize) -> Channel { assert!(n < 16usize); - unsafe { Channel::from_ptr(self.ptr.add(0usize + n * 64usize) as _) } + unsafe { Channel::from_ptr(self.ptr.add(0x0usize + n * 64usize) as _) } } #[doc = "Interrupt Status (raw)"] #[inline(always)] - pub const fn intr(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(1024usize) as _) } + pub const fn intr(self, n: usize) -> crate::common::Reg { + assert!(n < 4usize); + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x0400usize + n * 16usize) as _) } } #[doc = "Interrupt Enables for IRQ 0"] #[inline(always)] - pub const fn inte0(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(1028usize) as _) } + pub const fn inte(self, n: usize) -> crate::common::Reg { + assert!(n < 4usize); + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x0404usize + n * 16usize) as _) } } #[doc = "Force Interrupts"] #[inline(always)] - pub const fn intf0(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(1032usize) as _) } + pub const fn intf(self, n: usize) -> crate::common::Reg { + assert!(n < 4usize); + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x0408usize + n * 16usize) as _) } } #[doc = "Interrupt Status for IRQ 0"] #[inline(always)] - pub const fn ints0(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(1036usize) as _) } - } - #[doc = "Interrupt Status (raw)"] - #[inline(always)] - pub const fn intr1(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(1040usize) as _) } - } - #[doc = "Interrupt Enables for IRQ 1"] - #[inline(always)] - pub const fn inte1(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(1044usize) as _) } - } - #[doc = "Force Interrupts"] - #[inline(always)] - pub const fn intf1(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(1048usize) as _) } - } - #[doc = "Interrupt Status for IRQ 1"] - #[inline(always)] - pub const fn ints1(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(1052usize) as _) } - } - #[doc = "Interrupt Status (raw)"] - #[inline(always)] - pub const fn intr2(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(1056usize) as _) } - } - #[doc = "Interrupt Enables for IRQ 2"] - #[inline(always)] - pub const fn inte2(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(1060usize) as _) } - } - #[doc = "Force Interrupts"] - #[inline(always)] - pub const fn intf2(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(1064usize) as _) } - } - #[doc = "Interrupt Status for IRQ 2"] - #[inline(always)] - pub const fn ints2(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(1068usize) as _) } - } - #[doc = "Interrupt Status (raw)"] - #[inline(always)] - pub const fn intr3(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(1072usize) as _) } - } - #[doc = "Interrupt Enables for IRQ 3"] - #[inline(always)] - pub const fn inte3(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(1076usize) as _) } - } - #[doc = "Force Interrupts"] - #[inline(always)] - pub const fn intf3(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(1080usize) as _) } - } - #[doc = "Interrupt Status for IRQ 3"] - #[inline(always)] - pub const fn ints3(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(1084usize) as _) } + pub const fn ints(self, n: usize) -> crate::common::Reg { + assert!(n < 4usize); + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x040cusize + n * 16usize) as _) } } #[doc = "Pacing (X/Y) fractional timer The pacing timer produces TREQ assertions at a rate set by ((X/Y) * sys_clk). This equation is evaluated every sys_clk cycles and therefore can only generate TREQs at a rate of 1 per sys_clk (i.e. permanent TREQ) or less."] #[inline(always)] pub const fn timer(self, n: usize) -> crate::common::Reg { assert!(n < 4usize); - unsafe { crate::common::Reg::from_ptr(self.ptr.add(1088usize + n * 4usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x0440usize + n * 4usize) as _) } } #[doc = "Trigger one or more channels simultaneously"] #[inline(always)] pub const fn multi_chan_trigger( self, ) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(1104usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x0450usize) as _) } } #[doc = "Sniffer Control"] #[inline(always)] pub const fn sniff_ctrl(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(1108usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x0454usize) as _) } } #[doc = "Data accumulator for sniff hardware"] #[inline(always)] pub const fn sniff_data(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(1112usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x0458usize) as _) } } #[doc = "Debug RAF, WAF, TDF levels"] #[inline(always)] pub const fn fifo_levels(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(1120usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x0460usize) as _) } } #[doc = "Abort an in-progress transfer sequence on one or more channels"] #[inline(always)] pub const fn chan_abort(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(1124usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x0464usize) as _) } } #[doc = "The number of channels this DMA instance is equipped with. This DMA supports up to 16 hardware channels, but can be configured with as few as one, to minimise silicon area."] #[inline(always)] pub const fn n_channels(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(1128usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x0468usize) as _) } } #[doc = "Security configuration for channel 0. Control whether this channel performs Secure/Non-secure and Privileged/Unprivileged bus accesses. If this channel generates bus accesses of some security level, an access of at least that level (in the order S+P > S+U > NS+P > NS+U) is required to program, trigger, abort, check the status of, interrupt on or acknowledge the interrupt of this channel. This register automatically locks down (becomes read-only) once software starts to configure the channel. This register is world-readable, but is writable only from a Secure, Privileged context."] #[inline(always)] - pub const fn seccfg_ch0(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(1152usize) as _) } - } - #[doc = "Security configuration for channel 1. Control whether this channel performs Secure/Non-secure and Privileged/Unprivileged bus accesses. If this channel generates bus accesses of some security level, an access of at least that level (in the order S+P > S+U > NS+P > NS+U) is required to program, trigger, abort, check the status of, interrupt on or acknowledge the interrupt of this channel. This register automatically locks down (becomes read-only) once software starts to configure the channel. This register is world-readable, but is writable only from a Secure, Privileged context."] - #[inline(always)] - pub const fn seccfg_ch1(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(1156usize) as _) } - } - #[doc = "Security configuration for channel 2. Control whether this channel performs Secure/Non-secure and Privileged/Unprivileged bus accesses. If this channel generates bus accesses of some security level, an access of at least that level (in the order S+P > S+U > NS+P > NS+U) is required to program, trigger, abort, check the status of, interrupt on or acknowledge the interrupt of this channel. This register automatically locks down (becomes read-only) once software starts to configure the channel. This register is world-readable, but is writable only from a Secure, Privileged context."] - #[inline(always)] - pub const fn seccfg_ch2(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(1160usize) as _) } - } - #[doc = "Security configuration for channel 3. Control whether this channel performs Secure/Non-secure and Privileged/Unprivileged bus accesses. If this channel generates bus accesses of some security level, an access of at least that level (in the order S+P > S+U > NS+P > NS+U) is required to program, trigger, abort, check the status of, interrupt on or acknowledge the interrupt of this channel. This register automatically locks down (becomes read-only) once software starts to configure the channel. This register is world-readable, but is writable only from a Secure, Privileged context."] - #[inline(always)] - pub const fn seccfg_ch3(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(1164usize) as _) } - } - #[doc = "Security configuration for channel 4. Control whether this channel performs Secure/Non-secure and Privileged/Unprivileged bus accesses. If this channel generates bus accesses of some security level, an access of at least that level (in the order S+P > S+U > NS+P > NS+U) is required to program, trigger, abort, check the status of, interrupt on or acknowledge the interrupt of this channel. This register automatically locks down (becomes read-only) once software starts to configure the channel. This register is world-readable, but is writable only from a Secure, Privileged context."] - #[inline(always)] - pub const fn seccfg_ch4(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(1168usize) as _) } - } - #[doc = "Security configuration for channel 5. Control whether this channel performs Secure/Non-secure and Privileged/Unprivileged bus accesses. If this channel generates bus accesses of some security level, an access of at least that level (in the order S+P > S+U > NS+P > NS+U) is required to program, trigger, abort, check the status of, interrupt on or acknowledge the interrupt of this channel. This register automatically locks down (becomes read-only) once software starts to configure the channel. This register is world-readable, but is writable only from a Secure, Privileged context."] - #[inline(always)] - pub const fn seccfg_ch5(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(1172usize) as _) } - } - #[doc = "Security configuration for channel 6. Control whether this channel performs Secure/Non-secure and Privileged/Unprivileged bus accesses. If this channel generates bus accesses of some security level, an access of at least that level (in the order S+P > S+U > NS+P > NS+U) is required to program, trigger, abort, check the status of, interrupt on or acknowledge the interrupt of this channel. This register automatically locks down (becomes read-only) once software starts to configure the channel. This register is world-readable, but is writable only from a Secure, Privileged context."] - #[inline(always)] - pub const fn seccfg_ch6(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(1176usize) as _) } - } - #[doc = "Security configuration for channel 7. Control whether this channel performs Secure/Non-secure and Privileged/Unprivileged bus accesses. If this channel generates bus accesses of some security level, an access of at least that level (in the order S+P > S+U > NS+P > NS+U) is required to program, trigger, abort, check the status of, interrupt on or acknowledge the interrupt of this channel. This register automatically locks down (becomes read-only) once software starts to configure the channel. This register is world-readable, but is writable only from a Secure, Privileged context."] - #[inline(always)] - pub const fn seccfg_ch7(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(1180usize) as _) } - } - #[doc = "Security configuration for channel 8. Control whether this channel performs Secure/Non-secure and Privileged/Unprivileged bus accesses. If this channel generates bus accesses of some security level, an access of at least that level (in the order S+P > S+U > NS+P > NS+U) is required to program, trigger, abort, check the status of, interrupt on or acknowledge the interrupt of this channel. This register automatically locks down (becomes read-only) once software starts to configure the channel. This register is world-readable, but is writable only from a Secure, Privileged context."] - #[inline(always)] - pub const fn seccfg_ch8(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(1184usize) as _) } - } - #[doc = "Security configuration for channel 9. Control whether this channel performs Secure/Non-secure and Privileged/Unprivileged bus accesses. If this channel generates bus accesses of some security level, an access of at least that level (in the order S+P > S+U > NS+P > NS+U) is required to program, trigger, abort, check the status of, interrupt on or acknowledge the interrupt of this channel. This register automatically locks down (becomes read-only) once software starts to configure the channel. This register is world-readable, but is writable only from a Secure, Privileged context."] - #[inline(always)] - pub const fn seccfg_ch9(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(1188usize) as _) } - } - #[doc = "Security configuration for channel 10. Control whether this channel performs Secure/Non-secure and Privileged/Unprivileged bus accesses. If this channel generates bus accesses of some security level, an access of at least that level (in the order S+P > S+U > NS+P > NS+U) is required to program, trigger, abort, check the status of, interrupt on or acknowledge the interrupt of this channel. This register automatically locks down (becomes read-only) once software starts to configure the channel. This register is world-readable, but is writable only from a Secure, Privileged context."] - #[inline(always)] - pub const fn seccfg_ch10(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(1192usize) as _) } - } - #[doc = "Security configuration for channel 11. Control whether this channel performs Secure/Non-secure and Privileged/Unprivileged bus accesses. If this channel generates bus accesses of some security level, an access of at least that level (in the order S+P > S+U > NS+P > NS+U) is required to program, trigger, abort, check the status of, interrupt on or acknowledge the interrupt of this channel. This register automatically locks down (becomes read-only) once software starts to configure the channel. This register is world-readable, but is writable only from a Secure, Privileged context."] - #[inline(always)] - pub const fn seccfg_ch11(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(1196usize) as _) } - } - #[doc = "Security configuration for channel 12. Control whether this channel performs Secure/Non-secure and Privileged/Unprivileged bus accesses. If this channel generates bus accesses of some security level, an access of at least that level (in the order S+P > S+U > NS+P > NS+U) is required to program, trigger, abort, check the status of, interrupt on or acknowledge the interrupt of this channel. This register automatically locks down (becomes read-only) once software starts to configure the channel. This register is world-readable, but is writable only from a Secure, Privileged context."] - #[inline(always)] - pub const fn seccfg_ch12(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(1200usize) as _) } - } - #[doc = "Security configuration for channel 13. Control whether this channel performs Secure/Non-secure and Privileged/Unprivileged bus accesses. If this channel generates bus accesses of some security level, an access of at least that level (in the order S+P > S+U > NS+P > NS+U) is required to program, trigger, abort, check the status of, interrupt on or acknowledge the interrupt of this channel. This register automatically locks down (becomes read-only) once software starts to configure the channel. This register is world-readable, but is writable only from a Secure, Privileged context."] - #[inline(always)] - pub const fn seccfg_ch13(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(1204usize) as _) } - } - #[doc = "Security configuration for channel 14. Control whether this channel performs Secure/Non-secure and Privileged/Unprivileged bus accesses. If this channel generates bus accesses of some security level, an access of at least that level (in the order S+P > S+U > NS+P > NS+U) is required to program, trigger, abort, check the status of, interrupt on or acknowledge the interrupt of this channel. This register automatically locks down (becomes read-only) once software starts to configure the channel. This register is world-readable, but is writable only from a Secure, Privileged context."] - #[inline(always)] - pub const fn seccfg_ch14(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(1208usize) as _) } - } - #[doc = "Security configuration for channel 15. Control whether this channel performs Secure/Non-secure and Privileged/Unprivileged bus accesses. If this channel generates bus accesses of some security level, an access of at least that level (in the order S+P > S+U > NS+P > NS+U) is required to program, trigger, abort, check the status of, interrupt on or acknowledge the interrupt of this channel. This register automatically locks down (becomes read-only) once software starts to configure the channel. This register is world-readable, but is writable only from a Secure, Privileged context."] - #[inline(always)] - pub const fn seccfg_ch15(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(1212usize) as _) } + pub const fn seccfg_ch( + self, + n: usize, + ) -> crate::common::Reg { + assert!(n < 16usize); + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x0480usize + n * 4usize) as _) } } #[doc = "Security configuration for IRQ 0. Control whether the IRQ permits configuration by Non-secure/Unprivileged contexts, and whether it can observe Secure/Privileged channel interrupt flags."] #[inline(always)] - pub const fn seccfg_irq0(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(1216usize) as _) } - } - #[doc = "Security configuration for IRQ 1. Control whether the IRQ permits configuration by Non-secure/Unprivileged contexts, and whether it can observe Secure/Privileged channel interrupt flags."] - #[inline(always)] - pub const fn seccfg_irq1(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(1220usize) as _) } - } - #[doc = "Security configuration for IRQ 2. Control whether the IRQ permits configuration by Non-secure/Unprivileged contexts, and whether it can observe Secure/Privileged channel interrupt flags."] - #[inline(always)] - pub const fn seccfg_irq2(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(1224usize) as _) } - } - #[doc = "Security configuration for IRQ 3. Control whether the IRQ permits configuration by Non-secure/Unprivileged contexts, and whether it can observe Secure/Privileged channel interrupt flags."] - #[inline(always)] - pub const fn seccfg_irq3(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(1228usize) as _) } + pub const fn seccfg_irq( + self, + n: usize, + ) -> crate::common::Reg { + assert!(n < 4usize); + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x04c0usize + n * 4usize) as _) } } #[doc = "Miscellaneous security configuration"] #[inline(always)] pub const fn seccfg_misc(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(1232usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x04d0usize) as _) } } #[doc = "Control register for DMA MPU. Accessible only from a Privileged context."] #[inline(always)] pub const fn mpu_ctrl(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(1280usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x0500usize) as _) } } #[doc = "Base address register for MPU region 0. Writable only from a Secure, Privileged context."] #[inline(always)] - pub const fn mpu_bar0(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(1284usize) as _) } + pub const fn mpu_bar(self, n: usize) -> crate::common::Reg { + assert!(n < 8usize); + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x0504usize + n * 8usize) as _) } } #[doc = "Limit address register for MPU region 0. Writable only from a Secure, Privileged context, with the exception of the P bit."] #[inline(always)] - pub const fn mpu_lar0(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(1288usize) as _) } - } - #[doc = "Base address register for MPU region 1. Writable only from a Secure, Privileged context."] - #[inline(always)] - pub const fn mpu_bar1(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(1292usize) as _) } - } - #[doc = "Limit address register for MPU region 1. Writable only from a Secure, Privileged context, with the exception of the P bit."] - #[inline(always)] - pub const fn mpu_lar1(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(1296usize) as _) } - } - #[doc = "Base address register for MPU region 2. Writable only from a Secure, Privileged context."] - #[inline(always)] - pub const fn mpu_bar2(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(1300usize) as _) } - } - #[doc = "Limit address register for MPU region 2. Writable only from a Secure, Privileged context, with the exception of the P bit."] - #[inline(always)] - pub const fn mpu_lar2(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(1304usize) as _) } - } - #[doc = "Base address register for MPU region 3. Writable only from a Secure, Privileged context."] - #[inline(always)] - pub const fn mpu_bar3(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(1308usize) as _) } - } - #[doc = "Limit address register for MPU region 3. Writable only from a Secure, Privileged context, with the exception of the P bit."] - #[inline(always)] - pub const fn mpu_lar3(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(1312usize) as _) } - } - #[doc = "Base address register for MPU region 4. Writable only from a Secure, Privileged context."] - #[inline(always)] - pub const fn mpu_bar4(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(1316usize) as _) } - } - #[doc = "Limit address register for MPU region 4. Writable only from a Secure, Privileged context, with the exception of the P bit."] - #[inline(always)] - pub const fn mpu_lar4(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(1320usize) as _) } - } - #[doc = "Base address register for MPU region 5. Writable only from a Secure, Privileged context."] - #[inline(always)] - pub const fn mpu_bar5(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(1324usize) as _) } - } - #[doc = "Limit address register for MPU region 5. Writable only from a Secure, Privileged context, with the exception of the P bit."] - #[inline(always)] - pub const fn mpu_lar5(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(1328usize) as _) } - } - #[doc = "Base address register for MPU region 6. Writable only from a Secure, Privileged context."] - #[inline(always)] - pub const fn mpu_bar6(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(1332usize) as _) } - } - #[doc = "Limit address register for MPU region 6. Writable only from a Secure, Privileged context, with the exception of the P bit."] - #[inline(always)] - pub const fn mpu_lar6(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(1336usize) as _) } - } - #[doc = "Base address register for MPU region 7. Writable only from a Secure, Privileged context."] - #[inline(always)] - pub const fn mpu_bar7(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(1340usize) as _) } - } - #[doc = "Limit address register for MPU region 7. Writable only from a Secure, Privileged context, with the exception of the P bit."] - #[inline(always)] - pub const fn mpu_lar7(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(1344usize) as _) } + pub const fn mpu_lar(self, n: usize) -> crate::common::Reg { + assert!(n < 8usize); + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x0508usize + n * 8usize) as _) } } } pub mod regs; diff --git a/src/rp235x/dma/regs.rs b/src/rp235x/dma/regs.rs index 819d534f..f2599a12 100644 --- a/src/rp235x/dma/regs.rs +++ b/src/rp235x/dma/regs.rs @@ -1,8 +1,8 @@ -#[doc = "DMA Channel 0 Transfer Count"] +#[doc = "DMA Channel 3 Transfer Count"] #[repr(transparent)] #[derive(Copy, Clone, Eq, PartialEq)] -pub struct Ch0transCount(pub u32); -impl Ch0transCount { +pub struct ChTransCount(pub u32); +impl ChTransCount { #[doc = "28-bit transfer count (256 million transfers maximum). Program the number of bus transfers a channel will perform before halting. Note that, if transfers are larger than one byte in size, this is not equal to the number of bytes transferred (see CTRL_DATA_SIZE). When the channel is active, reading this register shows the number of transfers remaining, updating automatically each time a write transfer completes. Writing this register sets the RELOAD value for the transfer counter. Each time this channel is triggered, the RELOAD value is copied into the live transfer counter. The channel can be started multiple times, and will perform the same number of transfers each time, as programmed by most recent write. The RELOAD value can be observed at CHx_DBG_TCR. If TRANS_COUNT is used as a trigger, the written value is used immediately as the length of the new transfer sequence, as well as being written to RELOAD."] #[inline(always)] pub const fn count(&self) -> u32 { @@ -16,2747 +16,460 @@ impl Ch0transCount { } #[doc = "When MODE is 0x0, the transfer count decrements with each transfer until 0, and then the channel triggers the next channel indicated by CTRL_CHAIN_TO. When MODE is 0x1, the transfer count decrements with each transfer until 0, and then the channel re-triggers itself, in addition to the trigger indicated by CTRL_CHAIN_TO. This is useful for e.g. an endless ring-buffer DMA with periodic interrupts. When MODE is 0xf, the transfer count does not decrement. The DMA channel performs an endless sequence of transfers, never triggering other channels or raising interrupts, until an ABORT is raised. All other values are reserved."] #[inline(always)] - pub const fn mode(&self) -> super::vals::Ch0transCountMode { + pub const fn mode(&self) -> super::vals::TransCountMode { let val = (self.0 >> 28usize) & 0x0f; - super::vals::Ch0transCountMode::from_bits(val as u8) + super::vals::TransCountMode::from_bits(val as u8) } #[doc = "When MODE is 0x0, the transfer count decrements with each transfer until 0, and then the channel triggers the next channel indicated by CTRL_CHAIN_TO. When MODE is 0x1, the transfer count decrements with each transfer until 0, and then the channel re-triggers itself, in addition to the trigger indicated by CTRL_CHAIN_TO. This is useful for e.g. an endless ring-buffer DMA with periodic interrupts. When MODE is 0xf, the transfer count does not decrement. The DMA channel performs an endless sequence of transfers, never triggering other channels or raising interrupts, until an ABORT is raised. All other values are reserved."] #[inline(always)] - pub fn set_mode(&mut self, val: super::vals::Ch0transCountMode) { + pub fn set_mode(&mut self, val: super::vals::TransCountMode) { self.0 = (self.0 & !(0x0f << 28usize)) | (((val.to_bits() as u32) & 0x0f) << 28usize); } } -impl Default for Ch0transCount { +impl Default for ChTransCount { #[inline(always)] - fn default() -> Ch0transCount { - Ch0transCount(0) + fn default() -> ChTransCount { + ChTransCount(0) } } -#[doc = "DMA Channel 10 Transfer Count"] +#[doc = "Abort an in-progress transfer sequence on one or more channels"] #[repr(transparent)] #[derive(Copy, Clone, Eq, PartialEq)] -pub struct Ch10transCount(pub u32); -impl Ch10transCount { - #[doc = "28-bit transfer count (256 million transfers maximum). Program the number of bus transfers a channel will perform before halting. Note that, if transfers are larger than one byte in size, this is not equal to the number of bytes transferred (see CTRL_DATA_SIZE). When the channel is active, reading this register shows the number of transfers remaining, updating automatically each time a write transfer completes. Writing this register sets the RELOAD value for the transfer counter. Each time this channel is triggered, the RELOAD value is copied into the live transfer counter. The channel can be started multiple times, and will perform the same number of transfers each time, as programmed by most recent write. The RELOAD value can be observed at CHx_DBG_TCR. If TRANS_COUNT is used as a trigger, the written value is used immediately as the length of the new transfer sequence, as well as being written to RELOAD."] - #[inline(always)] - pub const fn count(&self) -> u32 { - let val = (self.0 >> 0usize) & 0x0fff_ffff; - val as u32 - } - #[doc = "28-bit transfer count (256 million transfers maximum). Program the number of bus transfers a channel will perform before halting. Note that, if transfers are larger than one byte in size, this is not equal to the number of bytes transferred (see CTRL_DATA_SIZE). When the channel is active, reading this register shows the number of transfers remaining, updating automatically each time a write transfer completes. Writing this register sets the RELOAD value for the transfer counter. Each time this channel is triggered, the RELOAD value is copied into the live transfer counter. The channel can be started multiple times, and will perform the same number of transfers each time, as programmed by most recent write. The RELOAD value can be observed at CHx_DBG_TCR. If TRANS_COUNT is used as a trigger, the written value is used immediately as the length of the new transfer sequence, as well as being written to RELOAD."] - #[inline(always)] - pub fn set_count(&mut self, val: u32) { - self.0 = (self.0 & !(0x0fff_ffff << 0usize)) | (((val as u32) & 0x0fff_ffff) << 0usize); - } - #[doc = "When MODE is 0x0, the transfer count decrements with each transfer until 0, and then the channel triggers the next channel indicated by CTRL_CHAIN_TO. When MODE is 0x1, the transfer count decrements with each transfer until 0, and then the channel re-triggers itself, in addition to the trigger indicated by CTRL_CHAIN_TO. This is useful for e.g. an endless ring-buffer DMA with periodic interrupts. When MODE is 0xf, the transfer count does not decrement. The DMA channel performs an endless sequence of transfers, never triggering other channels or raising interrupts, until an ABORT is raised. All other values are reserved."] +pub struct ChanAbort(pub u32); +impl ChanAbort { + #[doc = "Each bit corresponds to a channel. Writing a 1 aborts whatever transfer sequence is in progress on that channel. The bit will remain high until any in-flight transfers have been flushed through the address and data FIFOs. After writing, this register must be polled until it returns all-zero. Until this point, it is unsafe to restart the channel."] #[inline(always)] - pub const fn mode(&self) -> super::vals::Ch10transCountMode { - let val = (self.0 >> 28usize) & 0x0f; - super::vals::Ch10transCountMode::from_bits(val as u8) + pub const fn chan_abort(&self) -> u16 { + let val = (self.0 >> 0usize) & 0xffff; + val as u16 } - #[doc = "When MODE is 0x0, the transfer count decrements with each transfer until 0, and then the channel triggers the next channel indicated by CTRL_CHAIN_TO. When MODE is 0x1, the transfer count decrements with each transfer until 0, and then the channel re-triggers itself, in addition to the trigger indicated by CTRL_CHAIN_TO. This is useful for e.g. an endless ring-buffer DMA with periodic interrupts. When MODE is 0xf, the transfer count does not decrement. The DMA channel performs an endless sequence of transfers, never triggering other channels or raising interrupts, until an ABORT is raised. All other values are reserved."] + #[doc = "Each bit corresponds to a channel. Writing a 1 aborts whatever transfer sequence is in progress on that channel. The bit will remain high until any in-flight transfers have been flushed through the address and data FIFOs. After writing, this register must be polled until it returns all-zero. Until this point, it is unsafe to restart the channel."] #[inline(always)] - pub fn set_mode(&mut self, val: super::vals::Ch10transCountMode) { - self.0 = (self.0 & !(0x0f << 28usize)) | (((val.to_bits() as u32) & 0x0f) << 28usize); + pub fn set_chan_abort(&mut self, val: u16) { + self.0 = (self.0 & !(0xffff << 0usize)) | (((val as u32) & 0xffff) << 0usize); } } -impl Default for Ch10transCount { +impl Default for ChanAbort { #[inline(always)] - fn default() -> Ch10transCount { - Ch10transCount(0) + fn default() -> ChanAbort { + ChanAbort(0) } } -#[doc = "DMA Channel 11 Transfer Count"] +#[doc = "DMA Channel 0 Control and Status"] #[repr(transparent)] #[derive(Copy, Clone, Eq, PartialEq)] -pub struct Ch11transCount(pub u32); -impl Ch11transCount { - #[doc = "28-bit transfer count (256 million transfers maximum). Program the number of bus transfers a channel will perform before halting. Note that, if transfers are larger than one byte in size, this is not equal to the number of bytes transferred (see CTRL_DATA_SIZE). When the channel is active, reading this register shows the number of transfers remaining, updating automatically each time a write transfer completes. Writing this register sets the RELOAD value for the transfer counter. Each time this channel is triggered, the RELOAD value is copied into the live transfer counter. The channel can be started multiple times, and will perform the same number of transfers each time, as programmed by most recent write. The RELOAD value can be observed at CHx_DBG_TCR. If TRANS_COUNT is used as a trigger, the written value is used immediately as the length of the new transfer sequence, as well as being written to RELOAD."] - #[inline(always)] - pub const fn count(&self) -> u32 { - let val = (self.0 >> 0usize) & 0x0fff_ffff; - val as u32 - } - #[doc = "28-bit transfer count (256 million transfers maximum). Program the number of bus transfers a channel will perform before halting. Note that, if transfers are larger than one byte in size, this is not equal to the number of bytes transferred (see CTRL_DATA_SIZE). When the channel is active, reading this register shows the number of transfers remaining, updating automatically each time a write transfer completes. Writing this register sets the RELOAD value for the transfer counter. Each time this channel is triggered, the RELOAD value is copied into the live transfer counter. The channel can be started multiple times, and will perform the same number of transfers each time, as programmed by most recent write. The RELOAD value can be observed at CHx_DBG_TCR. If TRANS_COUNT is used as a trigger, the written value is used immediately as the length of the new transfer sequence, as well as being written to RELOAD."] - #[inline(always)] - pub fn set_count(&mut self, val: u32) { - self.0 = (self.0 & !(0x0fff_ffff << 0usize)) | (((val as u32) & 0x0fff_ffff) << 0usize); - } - #[doc = "When MODE is 0x0, the transfer count decrements with each transfer until 0, and then the channel triggers the next channel indicated by CTRL_CHAIN_TO. When MODE is 0x1, the transfer count decrements with each transfer until 0, and then the channel re-triggers itself, in addition to the trigger indicated by CTRL_CHAIN_TO. This is useful for e.g. an endless ring-buffer DMA with periodic interrupts. When MODE is 0xf, the transfer count does not decrement. The DMA channel performs an endless sequence of transfers, never triggering other channels or raising interrupts, until an ABORT is raised. All other values are reserved."] - #[inline(always)] - pub const fn mode(&self) -> super::vals::Ch11transCountMode { - let val = (self.0 >> 28usize) & 0x0f; - super::vals::Ch11transCountMode::from_bits(val as u8) - } - #[doc = "When MODE is 0x0, the transfer count decrements with each transfer until 0, and then the channel triggers the next channel indicated by CTRL_CHAIN_TO. When MODE is 0x1, the transfer count decrements with each transfer until 0, and then the channel re-triggers itself, in addition to the trigger indicated by CTRL_CHAIN_TO. This is useful for e.g. an endless ring-buffer DMA with periodic interrupts. When MODE is 0xf, the transfer count does not decrement. The DMA channel performs an endless sequence of transfers, never triggering other channels or raising interrupts, until an ABORT is raised. All other values are reserved."] +pub struct CtrlTrig(pub u32); +impl CtrlTrig { + #[doc = "DMA Channel Enable. When 1, the channel will respond to triggering events, which will cause it to become BUSY and start transferring data. When 0, the channel will ignore triggers, stop issuing transfers, and pause the current transfer sequence (i.e. BUSY will remain high if already high)"] #[inline(always)] - pub fn set_mode(&mut self, val: super::vals::Ch11transCountMode) { - self.0 = (self.0 & !(0x0f << 28usize)) | (((val.to_bits() as u32) & 0x0f) << 28usize); + pub const fn en(&self) -> bool { + let val = (self.0 >> 0usize) & 0x01; + val != 0 } -} -impl Default for Ch11transCount { + #[doc = "DMA Channel Enable. When 1, the channel will respond to triggering events, which will cause it to become BUSY and start transferring data. When 0, the channel will ignore triggers, stop issuing transfers, and pause the current transfer sequence (i.e. BUSY will remain high if already high)"] #[inline(always)] - fn default() -> Ch11transCount { - Ch11transCount(0) + pub fn set_en(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize); } -} -#[doc = "DMA Channel 12 Transfer Count"] -#[repr(transparent)] -#[derive(Copy, Clone, Eq, PartialEq)] -pub struct Ch12transCount(pub u32); -impl Ch12transCount { - #[doc = "28-bit transfer count (256 million transfers maximum). Program the number of bus transfers a channel will perform before halting. Note that, if transfers are larger than one byte in size, this is not equal to the number of bytes transferred (see CTRL_DATA_SIZE). When the channel is active, reading this register shows the number of transfers remaining, updating automatically each time a write transfer completes. Writing this register sets the RELOAD value for the transfer counter. Each time this channel is triggered, the RELOAD value is copied into the live transfer counter. The channel can be started multiple times, and will perform the same number of transfers each time, as programmed by most recent write. The RELOAD value can be observed at CHx_DBG_TCR. If TRANS_COUNT is used as a trigger, the written value is used immediately as the length of the new transfer sequence, as well as being written to RELOAD."] + #[doc = "HIGH_PRIORITY gives a channel preferential treatment in issue scheduling: in each scheduling round, all high priority channels are considered first, and then only a single low priority channel, before returning to the high priority channels. This only affects the order in which the DMA schedules channels. The DMA's bus priority is not changed. If the DMA is not saturated then a low priority channel will see no loss of throughput."] #[inline(always)] - pub const fn count(&self) -> u32 { - let val = (self.0 >> 0usize) & 0x0fff_ffff; - val as u32 + pub const fn high_priority(&self) -> bool { + let val = (self.0 >> 1usize) & 0x01; + val != 0 } - #[doc = "28-bit transfer count (256 million transfers maximum). Program the number of bus transfers a channel will perform before halting. Note that, if transfers are larger than one byte in size, this is not equal to the number of bytes transferred (see CTRL_DATA_SIZE). When the channel is active, reading this register shows the number of transfers remaining, updating automatically each time a write transfer completes. Writing this register sets the RELOAD value for the transfer counter. Each time this channel is triggered, the RELOAD value is copied into the live transfer counter. The channel can be started multiple times, and will perform the same number of transfers each time, as programmed by most recent write. The RELOAD value can be observed at CHx_DBG_TCR. If TRANS_COUNT is used as a trigger, the written value is used immediately as the length of the new transfer sequence, as well as being written to RELOAD."] + #[doc = "HIGH_PRIORITY gives a channel preferential treatment in issue scheduling: in each scheduling round, all high priority channels are considered first, and then only a single low priority channel, before returning to the high priority channels. This only affects the order in which the DMA schedules channels. The DMA's bus priority is not changed. If the DMA is not saturated then a low priority channel will see no loss of throughput."] #[inline(always)] - pub fn set_count(&mut self, val: u32) { - self.0 = (self.0 & !(0x0fff_ffff << 0usize)) | (((val as u32) & 0x0fff_ffff) << 0usize); + pub fn set_high_priority(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize); } - #[doc = "When MODE is 0x0, the transfer count decrements with each transfer until 0, and then the channel triggers the next channel indicated by CTRL_CHAIN_TO. When MODE is 0x1, the transfer count decrements with each transfer until 0, and then the channel re-triggers itself, in addition to the trigger indicated by CTRL_CHAIN_TO. This is useful for e.g. an endless ring-buffer DMA with periodic interrupts. When MODE is 0xf, the transfer count does not decrement. The DMA channel performs an endless sequence of transfers, never triggering other channels or raising interrupts, until an ABORT is raised. All other values are reserved."] + #[doc = "Set the size of each bus transfer (byte/halfword/word). READ_ADDR and WRITE_ADDR advance by this amount (1/2/4 bytes) with each transfer."] #[inline(always)] - pub const fn mode(&self) -> super::vals::Ch12transCountMode { - let val = (self.0 >> 28usize) & 0x0f; - super::vals::Ch12transCountMode::from_bits(val as u8) + pub const fn data_size(&self) -> super::vals::DataSize { + let val = (self.0 >> 2usize) & 0x03; + super::vals::DataSize::from_bits(val as u8) } - #[doc = "When MODE is 0x0, the transfer count decrements with each transfer until 0, and then the channel triggers the next channel indicated by CTRL_CHAIN_TO. When MODE is 0x1, the transfer count decrements with each transfer until 0, and then the channel re-triggers itself, in addition to the trigger indicated by CTRL_CHAIN_TO. This is useful for e.g. an endless ring-buffer DMA with periodic interrupts. When MODE is 0xf, the transfer count does not decrement. The DMA channel performs an endless sequence of transfers, never triggering other channels or raising interrupts, until an ABORT is raised. All other values are reserved."] + #[doc = "Set the size of each bus transfer (byte/halfword/word). READ_ADDR and WRITE_ADDR advance by this amount (1/2/4 bytes) with each transfer."] #[inline(always)] - pub fn set_mode(&mut self, val: super::vals::Ch12transCountMode) { - self.0 = (self.0 & !(0x0f << 28usize)) | (((val.to_bits() as u32) & 0x0f) << 28usize); + pub fn set_data_size(&mut self, val: super::vals::DataSize) { + self.0 = (self.0 & !(0x03 << 2usize)) | (((val.to_bits() as u32) & 0x03) << 2usize); } -} -impl Default for Ch12transCount { + #[doc = "If 1, the read address increments with each transfer. If 0, each read is directed to the same, initial address. Generally this should be disabled for peripheral-to-memory transfers."] #[inline(always)] - fn default() -> Ch12transCount { - Ch12transCount(0) + pub const fn incr_read(&self) -> bool { + let val = (self.0 >> 4usize) & 0x01; + val != 0 } -} -#[doc = "DMA Channel 13 Transfer Count"] -#[repr(transparent)] -#[derive(Copy, Clone, Eq, PartialEq)] -pub struct Ch13transCount(pub u32); -impl Ch13transCount { - #[doc = "28-bit transfer count (256 million transfers maximum). Program the number of bus transfers a channel will perform before halting. Note that, if transfers are larger than one byte in size, this is not equal to the number of bytes transferred (see CTRL_DATA_SIZE). When the channel is active, reading this register shows the number of transfers remaining, updating automatically each time a write transfer completes. Writing this register sets the RELOAD value for the transfer counter. Each time this channel is triggered, the RELOAD value is copied into the live transfer counter. The channel can be started multiple times, and will perform the same number of transfers each time, as programmed by most recent write. The RELOAD value can be observed at CHx_DBG_TCR. If TRANS_COUNT is used as a trigger, the written value is used immediately as the length of the new transfer sequence, as well as being written to RELOAD."] + #[doc = "If 1, the read address increments with each transfer. If 0, each read is directed to the same, initial address. Generally this should be disabled for peripheral-to-memory transfers."] #[inline(always)] - pub const fn count(&self) -> u32 { - let val = (self.0 >> 0usize) & 0x0fff_ffff; - val as u32 + pub fn set_incr_read(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 4usize)) | (((val as u32) & 0x01) << 4usize); } - #[doc = "28-bit transfer count (256 million transfers maximum). Program the number of bus transfers a channel will perform before halting. Note that, if transfers are larger than one byte in size, this is not equal to the number of bytes transferred (see CTRL_DATA_SIZE). When the channel is active, reading this register shows the number of transfers remaining, updating automatically each time a write transfer completes. Writing this register sets the RELOAD value for the transfer counter. Each time this channel is triggered, the RELOAD value is copied into the live transfer counter. The channel can be started multiple times, and will perform the same number of transfers each time, as programmed by most recent write. The RELOAD value can be observed at CHx_DBG_TCR. If TRANS_COUNT is used as a trigger, the written value is used immediately as the length of the new transfer sequence, as well as being written to RELOAD."] + #[doc = "If 1, and INCR_READ is 1, the read address is decremented rather than incremented with each transfer. If 1, and INCR_READ is 0, this otherwise-unused combination causes the read address to be incremented by twice the transfer size, i.e. skipping over alternate addresses."] #[inline(always)] - pub fn set_count(&mut self, val: u32) { - self.0 = (self.0 & !(0x0fff_ffff << 0usize)) | (((val as u32) & 0x0fff_ffff) << 0usize); + pub const fn incr_read_rev(&self) -> bool { + let val = (self.0 >> 5usize) & 0x01; + val != 0 } - #[doc = "When MODE is 0x0, the transfer count decrements with each transfer until 0, and then the channel triggers the next channel indicated by CTRL_CHAIN_TO. When MODE is 0x1, the transfer count decrements with each transfer until 0, and then the channel re-triggers itself, in addition to the trigger indicated by CTRL_CHAIN_TO. This is useful for e.g. an endless ring-buffer DMA with periodic interrupts. When MODE is 0xf, the transfer count does not decrement. The DMA channel performs an endless sequence of transfers, never triggering other channels or raising interrupts, until an ABORT is raised. All other values are reserved."] + #[doc = "If 1, and INCR_READ is 1, the read address is decremented rather than incremented with each transfer. If 1, and INCR_READ is 0, this otherwise-unused combination causes the read address to be incremented by twice the transfer size, i.e. skipping over alternate addresses."] #[inline(always)] - pub const fn mode(&self) -> super::vals::Ch13transCountMode { - let val = (self.0 >> 28usize) & 0x0f; - super::vals::Ch13transCountMode::from_bits(val as u8) + pub fn set_incr_read_rev(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 5usize)) | (((val as u32) & 0x01) << 5usize); } - #[doc = "When MODE is 0x0, the transfer count decrements with each transfer until 0, and then the channel triggers the next channel indicated by CTRL_CHAIN_TO. When MODE is 0x1, the transfer count decrements with each transfer until 0, and then the channel re-triggers itself, in addition to the trigger indicated by CTRL_CHAIN_TO. This is useful for e.g. an endless ring-buffer DMA with periodic interrupts. When MODE is 0xf, the transfer count does not decrement. The DMA channel performs an endless sequence of transfers, never triggering other channels or raising interrupts, until an ABORT is raised. All other values are reserved."] + #[doc = "If 1, the write address increments with each transfer. If 0, each write is directed to the same, initial address. Generally this should be disabled for memory-to-peripheral transfers."] #[inline(always)] - pub fn set_mode(&mut self, val: super::vals::Ch13transCountMode) { - self.0 = (self.0 & !(0x0f << 28usize)) | (((val.to_bits() as u32) & 0x0f) << 28usize); + pub const fn incr_write(&self) -> bool { + let val = (self.0 >> 6usize) & 0x01; + val != 0 } -} -impl Default for Ch13transCount { + #[doc = "If 1, the write address increments with each transfer. If 0, each write is directed to the same, initial address. Generally this should be disabled for memory-to-peripheral transfers."] #[inline(always)] - fn default() -> Ch13transCount { - Ch13transCount(0) + pub fn set_incr_write(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 6usize)) | (((val as u32) & 0x01) << 6usize); } -} -#[doc = "DMA Channel 14 Transfer Count"] -#[repr(transparent)] -#[derive(Copy, Clone, Eq, PartialEq)] -pub struct Ch14transCount(pub u32); -impl Ch14transCount { - #[doc = "28-bit transfer count (256 million transfers maximum). Program the number of bus transfers a channel will perform before halting. Note that, if transfers are larger than one byte in size, this is not equal to the number of bytes transferred (see CTRL_DATA_SIZE). When the channel is active, reading this register shows the number of transfers remaining, updating automatically each time a write transfer completes. Writing this register sets the RELOAD value for the transfer counter. Each time this channel is triggered, the RELOAD value is copied into the live transfer counter. The channel can be started multiple times, and will perform the same number of transfers each time, as programmed by most recent write. The RELOAD value can be observed at CHx_DBG_TCR. If TRANS_COUNT is used as a trigger, the written value is used immediately as the length of the new transfer sequence, as well as being written to RELOAD."] + #[doc = "If 1, and INCR_WRITE is 1, the write address is decremented rather than incremented with each transfer. If 1, and INCR_WRITE is 0, this otherwise-unused combination causes the write address to be incremented by twice the transfer size, i.e. skipping over alternate addresses."] #[inline(always)] - pub const fn count(&self) -> u32 { - let val = (self.0 >> 0usize) & 0x0fff_ffff; - val as u32 + pub const fn incr_write_rev(&self) -> bool { + let val = (self.0 >> 7usize) & 0x01; + val != 0 } - #[doc = "28-bit transfer count (256 million transfers maximum). Program the number of bus transfers a channel will perform before halting. Note that, if transfers are larger than one byte in size, this is not equal to the number of bytes transferred (see CTRL_DATA_SIZE). When the channel is active, reading this register shows the number of transfers remaining, updating automatically each time a write transfer completes. Writing this register sets the RELOAD value for the transfer counter. Each time this channel is triggered, the RELOAD value is copied into the live transfer counter. The channel can be started multiple times, and will perform the same number of transfers each time, as programmed by most recent write. The RELOAD value can be observed at CHx_DBG_TCR. If TRANS_COUNT is used as a trigger, the written value is used immediately as the length of the new transfer sequence, as well as being written to RELOAD."] + #[doc = "If 1, and INCR_WRITE is 1, the write address is decremented rather than incremented with each transfer. If 1, and INCR_WRITE is 0, this otherwise-unused combination causes the write address to be incremented by twice the transfer size, i.e. skipping over alternate addresses."] #[inline(always)] - pub fn set_count(&mut self, val: u32) { - self.0 = (self.0 & !(0x0fff_ffff << 0usize)) | (((val as u32) & 0x0fff_ffff) << 0usize); + pub fn set_incr_write_rev(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 7usize)) | (((val as u32) & 0x01) << 7usize); } - #[doc = "When MODE is 0x0, the transfer count decrements with each transfer until 0, and then the channel triggers the next channel indicated by CTRL_CHAIN_TO. When MODE is 0x1, the transfer count decrements with each transfer until 0, and then the channel re-triggers itself, in addition to the trigger indicated by CTRL_CHAIN_TO. This is useful for e.g. an endless ring-buffer DMA with periodic interrupts. When MODE is 0xf, the transfer count does not decrement. The DMA channel performs an endless sequence of transfers, never triggering other channels or raising interrupts, until an ABORT is raised. All other values are reserved."] + #[doc = "Size of address wrap region. If 0, don't wrap. For values n > 0, only the lower n bits of the address will change. This wraps the address on a (1 << n) byte boundary, facilitating access to naturally-aligned ring buffers. Ring sizes between 2 and 32768 bytes are possible. This can apply to either read or write addresses, based on value of RING_SEL."] #[inline(always)] - pub const fn mode(&self) -> super::vals::Ch14transCountMode { - let val = (self.0 >> 28usize) & 0x0f; - super::vals::Ch14transCountMode::from_bits(val as u8) + pub const fn ring_size(&self) -> u8 { + let val = (self.0 >> 8usize) & 0x0f; + val as u8 } - #[doc = "When MODE is 0x0, the transfer count decrements with each transfer until 0, and then the channel triggers the next channel indicated by CTRL_CHAIN_TO. When MODE is 0x1, the transfer count decrements with each transfer until 0, and then the channel re-triggers itself, in addition to the trigger indicated by CTRL_CHAIN_TO. This is useful for e.g. an endless ring-buffer DMA with periodic interrupts. When MODE is 0xf, the transfer count does not decrement. The DMA channel performs an endless sequence of transfers, never triggering other channels or raising interrupts, until an ABORT is raised. All other values are reserved."] + #[doc = "Size of address wrap region. If 0, don't wrap. For values n > 0, only the lower n bits of the address will change. This wraps the address on a (1 << n) byte boundary, facilitating access to naturally-aligned ring buffers. Ring sizes between 2 and 32768 bytes are possible. This can apply to either read or write addresses, based on value of RING_SEL."] #[inline(always)] - pub fn set_mode(&mut self, val: super::vals::Ch14transCountMode) { - self.0 = (self.0 & !(0x0f << 28usize)) | (((val.to_bits() as u32) & 0x0f) << 28usize); + pub fn set_ring_size(&mut self, val: u8) { + self.0 = (self.0 & !(0x0f << 8usize)) | (((val as u32) & 0x0f) << 8usize); } -} -impl Default for Ch14transCount { + #[doc = "Select whether RING_SIZE applies to read or write addresses. If 0, read addresses are wrapped on a (1 << RING_SIZE) boundary. If 1, write addresses are wrapped."] #[inline(always)] - fn default() -> Ch14transCount { - Ch14transCount(0) + pub const fn ring_sel(&self) -> bool { + let val = (self.0 >> 12usize) & 0x01; + val != 0 } -} -#[doc = "DMA Channel 15 Transfer Count"] -#[repr(transparent)] -#[derive(Copy, Clone, Eq, PartialEq)] -pub struct Ch15transCount(pub u32); -impl Ch15transCount { - #[doc = "28-bit transfer count (256 million transfers maximum). Program the number of bus transfers a channel will perform before halting. Note that, if transfers are larger than one byte in size, this is not equal to the number of bytes transferred (see CTRL_DATA_SIZE). When the channel is active, reading this register shows the number of transfers remaining, updating automatically each time a write transfer completes. Writing this register sets the RELOAD value for the transfer counter. Each time this channel is triggered, the RELOAD value is copied into the live transfer counter. The channel can be started multiple times, and will perform the same number of transfers each time, as programmed by most recent write. The RELOAD value can be observed at CHx_DBG_TCR. If TRANS_COUNT is used as a trigger, the written value is used immediately as the length of the new transfer sequence, as well as being written to RELOAD."] + #[doc = "Select whether RING_SIZE applies to read or write addresses. If 0, read addresses are wrapped on a (1 << RING_SIZE) boundary. If 1, write addresses are wrapped."] #[inline(always)] - pub const fn count(&self) -> u32 { - let val = (self.0 >> 0usize) & 0x0fff_ffff; - val as u32 + pub fn set_ring_sel(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 12usize)) | (((val as u32) & 0x01) << 12usize); } - #[doc = "28-bit transfer count (256 million transfers maximum). Program the number of bus transfers a channel will perform before halting. Note that, if transfers are larger than one byte in size, this is not equal to the number of bytes transferred (see CTRL_DATA_SIZE). When the channel is active, reading this register shows the number of transfers remaining, updating automatically each time a write transfer completes. Writing this register sets the RELOAD value for the transfer counter. Each time this channel is triggered, the RELOAD value is copied into the live transfer counter. The channel can be started multiple times, and will perform the same number of transfers each time, as programmed by most recent write. The RELOAD value can be observed at CHx_DBG_TCR. If TRANS_COUNT is used as a trigger, the written value is used immediately as the length of the new transfer sequence, as well as being written to RELOAD."] + #[doc = "When this channel completes, it will trigger the channel indicated by CHAIN_TO. Disable by setting CHAIN_TO = _(this channel)_. Note this field resets to 0, so channels 1 and above will chain to channel 0 by default. Set this field to avoid this behaviour."] #[inline(always)] - pub fn set_count(&mut self, val: u32) { - self.0 = (self.0 & !(0x0fff_ffff << 0usize)) | (((val as u32) & 0x0fff_ffff) << 0usize); + pub const fn chain_to(&self) -> u8 { + let val = (self.0 >> 13usize) & 0x0f; + val as u8 } - #[doc = "When MODE is 0x0, the transfer count decrements with each transfer until 0, and then the channel triggers the next channel indicated by CTRL_CHAIN_TO. When MODE is 0x1, the transfer count decrements with each transfer until 0, and then the channel re-triggers itself, in addition to the trigger indicated by CTRL_CHAIN_TO. This is useful for e.g. an endless ring-buffer DMA with periodic interrupts. When MODE is 0xf, the transfer count does not decrement. The DMA channel performs an endless sequence of transfers, never triggering other channels or raising interrupts, until an ABORT is raised. All other values are reserved."] + #[doc = "When this channel completes, it will trigger the channel indicated by CHAIN_TO. Disable by setting CHAIN_TO = _(this channel)_. Note this field resets to 0, so channels 1 and above will chain to channel 0 by default. Set this field to avoid this behaviour."] #[inline(always)] - pub const fn mode(&self) -> super::vals::Ch15transCountMode { - let val = (self.0 >> 28usize) & 0x0f; - super::vals::Ch15transCountMode::from_bits(val as u8) + pub fn set_chain_to(&mut self, val: u8) { + self.0 = (self.0 & !(0x0f << 13usize)) | (((val as u32) & 0x0f) << 13usize); } - #[doc = "When MODE is 0x0, the transfer count decrements with each transfer until 0, and then the channel triggers the next channel indicated by CTRL_CHAIN_TO. When MODE is 0x1, the transfer count decrements with each transfer until 0, and then the channel re-triggers itself, in addition to the trigger indicated by CTRL_CHAIN_TO. This is useful for e.g. an endless ring-buffer DMA with periodic interrupts. When MODE is 0xf, the transfer count does not decrement. The DMA channel performs an endless sequence of transfers, never triggering other channels or raising interrupts, until an ABORT is raised. All other values are reserved."] + #[doc = "Select a Transfer Request signal. The channel uses the transfer request signal to pace its data transfer rate. Sources for TREQ signals are internal (TIMERS) or external (DREQ, a Data Request from the system). 0x0 to 0x3a -> select DREQ n as TREQ"] #[inline(always)] - pub fn set_mode(&mut self, val: super::vals::Ch15transCountMode) { - self.0 = (self.0 & !(0x0f << 28usize)) | (((val.to_bits() as u32) & 0x0f) << 28usize); + pub const fn treq_sel(&self) -> super::vals::TreqSel { + let val = (self.0 >> 17usize) & 0x3f; + super::vals::TreqSel::from_bits(val as u8) } -} -impl Default for Ch15transCount { + #[doc = "Select a Transfer Request signal. The channel uses the transfer request signal to pace its data transfer rate. Sources for TREQ signals are internal (TIMERS) or external (DREQ, a Data Request from the system). 0x0 to 0x3a -> select DREQ n as TREQ"] #[inline(always)] - fn default() -> Ch15transCount { - Ch15transCount(0) + pub fn set_treq_sel(&mut self, val: super::vals::TreqSel) { + self.0 = (self.0 & !(0x3f << 17usize)) | (((val.to_bits() as u32) & 0x3f) << 17usize); } -} -#[doc = "DMA Channel 1 Transfer Count"] -#[repr(transparent)] -#[derive(Copy, Clone, Eq, PartialEq)] -pub struct Ch1transCount(pub u32); -impl Ch1transCount { - #[doc = "28-bit transfer count (256 million transfers maximum). Program the number of bus transfers a channel will perform before halting. Note that, if transfers are larger than one byte in size, this is not equal to the number of bytes transferred (see CTRL_DATA_SIZE). When the channel is active, reading this register shows the number of transfers remaining, updating automatically each time a write transfer completes. Writing this register sets the RELOAD value for the transfer counter. Each time this channel is triggered, the RELOAD value is copied into the live transfer counter. The channel can be started multiple times, and will perform the same number of transfers each time, as programmed by most recent write. The RELOAD value can be observed at CHx_DBG_TCR. If TRANS_COUNT is used as a trigger, the written value is used immediately as the length of the new transfer sequence, as well as being written to RELOAD."] + #[doc = "In QUIET mode, the channel does not generate IRQs at the end of every transfer block. Instead, an IRQ is raised when NULL is written to a trigger register, indicating the end of a control block chain. This reduces the number of interrupts to be serviced by the CPU when transferring a DMA chain of many small control blocks."] #[inline(always)] - pub const fn count(&self) -> u32 { - let val = (self.0 >> 0usize) & 0x0fff_ffff; - val as u32 + pub const fn irq_quiet(&self) -> bool { + let val = (self.0 >> 23usize) & 0x01; + val != 0 } - #[doc = "28-bit transfer count (256 million transfers maximum). Program the number of bus transfers a channel will perform before halting. Note that, if transfers are larger than one byte in size, this is not equal to the number of bytes transferred (see CTRL_DATA_SIZE). When the channel is active, reading this register shows the number of transfers remaining, updating automatically each time a write transfer completes. Writing this register sets the RELOAD value for the transfer counter. Each time this channel is triggered, the RELOAD value is copied into the live transfer counter. The channel can be started multiple times, and will perform the same number of transfers each time, as programmed by most recent write. The RELOAD value can be observed at CHx_DBG_TCR. If TRANS_COUNT is used as a trigger, the written value is used immediately as the length of the new transfer sequence, as well as being written to RELOAD."] + #[doc = "In QUIET mode, the channel does not generate IRQs at the end of every transfer block. Instead, an IRQ is raised when NULL is written to a trigger register, indicating the end of a control block chain. This reduces the number of interrupts to be serviced by the CPU when transferring a DMA chain of many small control blocks."] #[inline(always)] - pub fn set_count(&mut self, val: u32) { - self.0 = (self.0 & !(0x0fff_ffff << 0usize)) | (((val as u32) & 0x0fff_ffff) << 0usize); + pub fn set_irq_quiet(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 23usize)) | (((val as u32) & 0x01) << 23usize); } - #[doc = "When MODE is 0x0, the transfer count decrements with each transfer until 0, and then the channel triggers the next channel indicated by CTRL_CHAIN_TO. When MODE is 0x1, the transfer count decrements with each transfer until 0, and then the channel re-triggers itself, in addition to the trigger indicated by CTRL_CHAIN_TO. This is useful for e.g. an endless ring-buffer DMA with periodic interrupts. When MODE is 0xf, the transfer count does not decrement. The DMA channel performs an endless sequence of transfers, never triggering other channels or raising interrupts, until an ABORT is raised. All other values are reserved."] + #[doc = "Apply byte-swap transformation to DMA data. For byte data, this has no effect. For halfword data, the two bytes of each halfword are swapped. For word data, the four bytes of each word are swapped to reverse order."] #[inline(always)] - pub const fn mode(&self) -> super::vals::Ch1transCountMode { - let val = (self.0 >> 28usize) & 0x0f; - super::vals::Ch1transCountMode::from_bits(val as u8) + pub const fn bswap(&self) -> bool { + let val = (self.0 >> 24usize) & 0x01; + val != 0 } - #[doc = "When MODE is 0x0, the transfer count decrements with each transfer until 0, and then the channel triggers the next channel indicated by CTRL_CHAIN_TO. When MODE is 0x1, the transfer count decrements with each transfer until 0, and then the channel re-triggers itself, in addition to the trigger indicated by CTRL_CHAIN_TO. This is useful for e.g. an endless ring-buffer DMA with periodic interrupts. When MODE is 0xf, the transfer count does not decrement. The DMA channel performs an endless sequence of transfers, never triggering other channels or raising interrupts, until an ABORT is raised. All other values are reserved."] + #[doc = "Apply byte-swap transformation to DMA data. For byte data, this has no effect. For halfword data, the two bytes of each halfword are swapped. For word data, the four bytes of each word are swapped to reverse order."] #[inline(always)] - pub fn set_mode(&mut self, val: super::vals::Ch1transCountMode) { - self.0 = (self.0 & !(0x0f << 28usize)) | (((val.to_bits() as u32) & 0x0f) << 28usize); + pub fn set_bswap(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 24usize)) | (((val as u32) & 0x01) << 24usize); } -} -impl Default for Ch1transCount { + #[doc = "If 1, this channel's data transfers are visible to the sniff hardware, and each transfer will advance the state of the checksum. This only applies if the sniff hardware is enabled, and has this channel selected. This allows checksum to be enabled or disabled on a per-control- block basis."] #[inline(always)] - fn default() -> Ch1transCount { - Ch1transCount(0) + pub const fn sniff_en(&self) -> bool { + let val = (self.0 >> 25usize) & 0x01; + val != 0 } -} -#[doc = "DMA Channel 2 Transfer Count"] -#[repr(transparent)] -#[derive(Copy, Clone, Eq, PartialEq)] -pub struct Ch2transCount(pub u32); -impl Ch2transCount { - #[doc = "28-bit transfer count (256 million transfers maximum). Program the number of bus transfers a channel will perform before halting. Note that, if transfers are larger than one byte in size, this is not equal to the number of bytes transferred (see CTRL_DATA_SIZE). When the channel is active, reading this register shows the number of transfers remaining, updating automatically each time a write transfer completes. Writing this register sets the RELOAD value for the transfer counter. Each time this channel is triggered, the RELOAD value is copied into the live transfer counter. The channel can be started multiple times, and will perform the same number of transfers each time, as programmed by most recent write. The RELOAD value can be observed at CHx_DBG_TCR. If TRANS_COUNT is used as a trigger, the written value is used immediately as the length of the new transfer sequence, as well as being written to RELOAD."] + #[doc = "If 1, this channel's data transfers are visible to the sniff hardware, and each transfer will advance the state of the checksum. This only applies if the sniff hardware is enabled, and has this channel selected. This allows checksum to be enabled or disabled on a per-control- block basis."] #[inline(always)] - pub const fn count(&self) -> u32 { - let val = (self.0 >> 0usize) & 0x0fff_ffff; - val as u32 + pub fn set_sniff_en(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 25usize)) | (((val as u32) & 0x01) << 25usize); } - #[doc = "28-bit transfer count (256 million transfers maximum). Program the number of bus transfers a channel will perform before halting. Note that, if transfers are larger than one byte in size, this is not equal to the number of bytes transferred (see CTRL_DATA_SIZE). When the channel is active, reading this register shows the number of transfers remaining, updating automatically each time a write transfer completes. Writing this register sets the RELOAD value for the transfer counter. Each time this channel is triggered, the RELOAD value is copied into the live transfer counter. The channel can be started multiple times, and will perform the same number of transfers each time, as programmed by most recent write. The RELOAD value can be observed at CHx_DBG_TCR. If TRANS_COUNT is used as a trigger, the written value is used immediately as the length of the new transfer sequence, as well as being written to RELOAD."] + #[doc = "This flag goes high when the channel starts a new transfer sequence, and low when the last transfer of that sequence completes. Clearing EN while BUSY is high pauses the channel, and BUSY will stay high while paused. To terminate a sequence early (and clear the BUSY flag), see CHAN_ABORT."] #[inline(always)] - pub fn set_count(&mut self, val: u32) { - self.0 = (self.0 & !(0x0fff_ffff << 0usize)) | (((val as u32) & 0x0fff_ffff) << 0usize); + pub const fn busy(&self) -> bool { + let val = (self.0 >> 26usize) & 0x01; + val != 0 } - #[doc = "When MODE is 0x0, the transfer count decrements with each transfer until 0, and then the channel triggers the next channel indicated by CTRL_CHAIN_TO. When MODE is 0x1, the transfer count decrements with each transfer until 0, and then the channel re-triggers itself, in addition to the trigger indicated by CTRL_CHAIN_TO. This is useful for e.g. an endless ring-buffer DMA with periodic interrupts. When MODE is 0xf, the transfer count does not decrement. The DMA channel performs an endless sequence of transfers, never triggering other channels or raising interrupts, until an ABORT is raised. All other values are reserved."] + #[doc = "This flag goes high when the channel starts a new transfer sequence, and low when the last transfer of that sequence completes. Clearing EN while BUSY is high pauses the channel, and BUSY will stay high while paused. To terminate a sequence early (and clear the BUSY flag), see CHAN_ABORT."] #[inline(always)] - pub const fn mode(&self) -> super::vals::Ch2transCountMode { - let val = (self.0 >> 28usize) & 0x0f; - super::vals::Ch2transCountMode::from_bits(val as u8) + pub fn set_busy(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 26usize)) | (((val as u32) & 0x01) << 26usize); } - #[doc = "When MODE is 0x0, the transfer count decrements with each transfer until 0, and then the channel triggers the next channel indicated by CTRL_CHAIN_TO. When MODE is 0x1, the transfer count decrements with each transfer until 0, and then the channel re-triggers itself, in addition to the trigger indicated by CTRL_CHAIN_TO. This is useful for e.g. an endless ring-buffer DMA with periodic interrupts. When MODE is 0xf, the transfer count does not decrement. The DMA channel performs an endless sequence of transfers, never triggering other channels or raising interrupts, until an ABORT is raised. All other values are reserved."] + #[doc = "If 1, the channel received a write bus error. Write one to clear. WRITE_ADDR shows the approximate address where the bus error was encountered (will not be earlier, or more than 5 transfers later)"] #[inline(always)] - pub fn set_mode(&mut self, val: super::vals::Ch2transCountMode) { - self.0 = (self.0 & !(0x0f << 28usize)) | (((val.to_bits() as u32) & 0x0f) << 28usize); + pub const fn write_error(&self) -> bool { + let val = (self.0 >> 29usize) & 0x01; + val != 0 } -} -impl Default for Ch2transCount { + #[doc = "If 1, the channel received a write bus error. Write one to clear. WRITE_ADDR shows the approximate address where the bus error was encountered (will not be earlier, or more than 5 transfers later)"] #[inline(always)] - fn default() -> Ch2transCount { - Ch2transCount(0) + pub fn set_write_error(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 29usize)) | (((val as u32) & 0x01) << 29usize); } -} -#[doc = "DMA Channel 3 Transfer Count"] -#[repr(transparent)] -#[derive(Copy, Clone, Eq, PartialEq)] -pub struct Ch3transCount(pub u32); -impl Ch3transCount { - #[doc = "28-bit transfer count (256 million transfers maximum). Program the number of bus transfers a channel will perform before halting. Note that, if transfers are larger than one byte in size, this is not equal to the number of bytes transferred (see CTRL_DATA_SIZE). When the channel is active, reading this register shows the number of transfers remaining, updating automatically each time a write transfer completes. Writing this register sets the RELOAD value for the transfer counter. Each time this channel is triggered, the RELOAD value is copied into the live transfer counter. The channel can be started multiple times, and will perform the same number of transfers each time, as programmed by most recent write. The RELOAD value can be observed at CHx_DBG_TCR. If TRANS_COUNT is used as a trigger, the written value is used immediately as the length of the new transfer sequence, as well as being written to RELOAD."] - #[inline(always)] - pub const fn count(&self) -> u32 { - let val = (self.0 >> 0usize) & 0x0fff_ffff; - val as u32 - } - #[doc = "28-bit transfer count (256 million transfers maximum). Program the number of bus transfers a channel will perform before halting. Note that, if transfers are larger than one byte in size, this is not equal to the number of bytes transferred (see CTRL_DATA_SIZE). When the channel is active, reading this register shows the number of transfers remaining, updating automatically each time a write transfer completes. Writing this register sets the RELOAD value for the transfer counter. Each time this channel is triggered, the RELOAD value is copied into the live transfer counter. The channel can be started multiple times, and will perform the same number of transfers each time, as programmed by most recent write. The RELOAD value can be observed at CHx_DBG_TCR. If TRANS_COUNT is used as a trigger, the written value is used immediately as the length of the new transfer sequence, as well as being written to RELOAD."] - #[inline(always)] - pub fn set_count(&mut self, val: u32) { - self.0 = (self.0 & !(0x0fff_ffff << 0usize)) | (((val as u32) & 0x0fff_ffff) << 0usize); - } - #[doc = "When MODE is 0x0, the transfer count decrements with each transfer until 0, and then the channel triggers the next channel indicated by CTRL_CHAIN_TO. When MODE is 0x1, the transfer count decrements with each transfer until 0, and then the channel re-triggers itself, in addition to the trigger indicated by CTRL_CHAIN_TO. This is useful for e.g. an endless ring-buffer DMA with periodic interrupts. When MODE is 0xf, the transfer count does not decrement. The DMA channel performs an endless sequence of transfers, never triggering other channels or raising interrupts, until an ABORT is raised. All other values are reserved."] - #[inline(always)] - pub const fn mode(&self) -> super::vals::Ch3transCountMode { - let val = (self.0 >> 28usize) & 0x0f; - super::vals::Ch3transCountMode::from_bits(val as u8) - } - #[doc = "When MODE is 0x0, the transfer count decrements with each transfer until 0, and then the channel triggers the next channel indicated by CTRL_CHAIN_TO. When MODE is 0x1, the transfer count decrements with each transfer until 0, and then the channel re-triggers itself, in addition to the trigger indicated by CTRL_CHAIN_TO. This is useful for e.g. an endless ring-buffer DMA with periodic interrupts. When MODE is 0xf, the transfer count does not decrement. The DMA channel performs an endless sequence of transfers, never triggering other channels or raising interrupts, until an ABORT is raised. All other values are reserved."] - #[inline(always)] - pub fn set_mode(&mut self, val: super::vals::Ch3transCountMode) { - self.0 = (self.0 & !(0x0f << 28usize)) | (((val.to_bits() as u32) & 0x0f) << 28usize); - } -} -impl Default for Ch3transCount { - #[inline(always)] - fn default() -> Ch3transCount { - Ch3transCount(0) - } -} -#[doc = "DMA Channel 4 Transfer Count"] -#[repr(transparent)] -#[derive(Copy, Clone, Eq, PartialEq)] -pub struct Ch4transCount(pub u32); -impl Ch4transCount { - #[doc = "28-bit transfer count (256 million transfers maximum). Program the number of bus transfers a channel will perform before halting. Note that, if transfers are larger than one byte in size, this is not equal to the number of bytes transferred (see CTRL_DATA_SIZE). When the channel is active, reading this register shows the number of transfers remaining, updating automatically each time a write transfer completes. Writing this register sets the RELOAD value for the transfer counter. Each time this channel is triggered, the RELOAD value is copied into the live transfer counter. The channel can be started multiple times, and will perform the same number of transfers each time, as programmed by most recent write. The RELOAD value can be observed at CHx_DBG_TCR. If TRANS_COUNT is used as a trigger, the written value is used immediately as the length of the new transfer sequence, as well as being written to RELOAD."] - #[inline(always)] - pub const fn count(&self) -> u32 { - let val = (self.0 >> 0usize) & 0x0fff_ffff; - val as u32 - } - #[doc = "28-bit transfer count (256 million transfers maximum). Program the number of bus transfers a channel will perform before halting. Note that, if transfers are larger than one byte in size, this is not equal to the number of bytes transferred (see CTRL_DATA_SIZE). When the channel is active, reading this register shows the number of transfers remaining, updating automatically each time a write transfer completes. Writing this register sets the RELOAD value for the transfer counter. Each time this channel is triggered, the RELOAD value is copied into the live transfer counter. The channel can be started multiple times, and will perform the same number of transfers each time, as programmed by most recent write. The RELOAD value can be observed at CHx_DBG_TCR. If TRANS_COUNT is used as a trigger, the written value is used immediately as the length of the new transfer sequence, as well as being written to RELOAD."] - #[inline(always)] - pub fn set_count(&mut self, val: u32) { - self.0 = (self.0 & !(0x0fff_ffff << 0usize)) | (((val as u32) & 0x0fff_ffff) << 0usize); - } - #[doc = "When MODE is 0x0, the transfer count decrements with each transfer until 0, and then the channel triggers the next channel indicated by CTRL_CHAIN_TO. When MODE is 0x1, the transfer count decrements with each transfer until 0, and then the channel re-triggers itself, in addition to the trigger indicated by CTRL_CHAIN_TO. This is useful for e.g. an endless ring-buffer DMA with periodic interrupts. When MODE is 0xf, the transfer count does not decrement. The DMA channel performs an endless sequence of transfers, never triggering other channels or raising interrupts, until an ABORT is raised. All other values are reserved."] - #[inline(always)] - pub const fn mode(&self) -> super::vals::Ch4transCountMode { - let val = (self.0 >> 28usize) & 0x0f; - super::vals::Ch4transCountMode::from_bits(val as u8) - } - #[doc = "When MODE is 0x0, the transfer count decrements with each transfer until 0, and then the channel triggers the next channel indicated by CTRL_CHAIN_TO. When MODE is 0x1, the transfer count decrements with each transfer until 0, and then the channel re-triggers itself, in addition to the trigger indicated by CTRL_CHAIN_TO. This is useful for e.g. an endless ring-buffer DMA with periodic interrupts. When MODE is 0xf, the transfer count does not decrement. The DMA channel performs an endless sequence of transfers, never triggering other channels or raising interrupts, until an ABORT is raised. All other values are reserved."] - #[inline(always)] - pub fn set_mode(&mut self, val: super::vals::Ch4transCountMode) { - self.0 = (self.0 & !(0x0f << 28usize)) | (((val.to_bits() as u32) & 0x0f) << 28usize); - } -} -impl Default for Ch4transCount { - #[inline(always)] - fn default() -> Ch4transCount { - Ch4transCount(0) - } -} -#[doc = "DMA Channel 5 Transfer Count"] -#[repr(transparent)] -#[derive(Copy, Clone, Eq, PartialEq)] -pub struct Ch5transCount(pub u32); -impl Ch5transCount { - #[doc = "28-bit transfer count (256 million transfers maximum). Program the number of bus transfers a channel will perform before halting. Note that, if transfers are larger than one byte in size, this is not equal to the number of bytes transferred (see CTRL_DATA_SIZE). When the channel is active, reading this register shows the number of transfers remaining, updating automatically each time a write transfer completes. Writing this register sets the RELOAD value for the transfer counter. Each time this channel is triggered, the RELOAD value is copied into the live transfer counter. The channel can be started multiple times, and will perform the same number of transfers each time, as programmed by most recent write. The RELOAD value can be observed at CHx_DBG_TCR. If TRANS_COUNT is used as a trigger, the written value is used immediately as the length of the new transfer sequence, as well as being written to RELOAD."] - #[inline(always)] - pub const fn count(&self) -> u32 { - let val = (self.0 >> 0usize) & 0x0fff_ffff; - val as u32 - } - #[doc = "28-bit transfer count (256 million transfers maximum). Program the number of bus transfers a channel will perform before halting. Note that, if transfers are larger than one byte in size, this is not equal to the number of bytes transferred (see CTRL_DATA_SIZE). When the channel is active, reading this register shows the number of transfers remaining, updating automatically each time a write transfer completes. Writing this register sets the RELOAD value for the transfer counter. Each time this channel is triggered, the RELOAD value is copied into the live transfer counter. The channel can be started multiple times, and will perform the same number of transfers each time, as programmed by most recent write. The RELOAD value can be observed at CHx_DBG_TCR. If TRANS_COUNT is used as a trigger, the written value is used immediately as the length of the new transfer sequence, as well as being written to RELOAD."] - #[inline(always)] - pub fn set_count(&mut self, val: u32) { - self.0 = (self.0 & !(0x0fff_ffff << 0usize)) | (((val as u32) & 0x0fff_ffff) << 0usize); - } - #[doc = "When MODE is 0x0, the transfer count decrements with each transfer until 0, and then the channel triggers the next channel indicated by CTRL_CHAIN_TO. When MODE is 0x1, the transfer count decrements with each transfer until 0, and then the channel re-triggers itself, in addition to the trigger indicated by CTRL_CHAIN_TO. This is useful for e.g. an endless ring-buffer DMA with periodic interrupts. When MODE is 0xf, the transfer count does not decrement. The DMA channel performs an endless sequence of transfers, never triggering other channels or raising interrupts, until an ABORT is raised. All other values are reserved."] - #[inline(always)] - pub const fn mode(&self) -> super::vals::Ch5transCountMode { - let val = (self.0 >> 28usize) & 0x0f; - super::vals::Ch5transCountMode::from_bits(val as u8) - } - #[doc = "When MODE is 0x0, the transfer count decrements with each transfer until 0, and then the channel triggers the next channel indicated by CTRL_CHAIN_TO. When MODE is 0x1, the transfer count decrements with each transfer until 0, and then the channel re-triggers itself, in addition to the trigger indicated by CTRL_CHAIN_TO. This is useful for e.g. an endless ring-buffer DMA with periodic interrupts. When MODE is 0xf, the transfer count does not decrement. The DMA channel performs an endless sequence of transfers, never triggering other channels or raising interrupts, until an ABORT is raised. All other values are reserved."] - #[inline(always)] - pub fn set_mode(&mut self, val: super::vals::Ch5transCountMode) { - self.0 = (self.0 & !(0x0f << 28usize)) | (((val.to_bits() as u32) & 0x0f) << 28usize); - } -} -impl Default for Ch5transCount { - #[inline(always)] - fn default() -> Ch5transCount { - Ch5transCount(0) - } -} -#[doc = "DMA Channel 6 Transfer Count"] -#[repr(transparent)] -#[derive(Copy, Clone, Eq, PartialEq)] -pub struct Ch6transCount(pub u32); -impl Ch6transCount { - #[doc = "28-bit transfer count (256 million transfers maximum). Program the number of bus transfers a channel will perform before halting. Note that, if transfers are larger than one byte in size, this is not equal to the number of bytes transferred (see CTRL_DATA_SIZE). When the channel is active, reading this register shows the number of transfers remaining, updating automatically each time a write transfer completes. Writing this register sets the RELOAD value for the transfer counter. Each time this channel is triggered, the RELOAD value is copied into the live transfer counter. The channel can be started multiple times, and will perform the same number of transfers each time, as programmed by most recent write. The RELOAD value can be observed at CHx_DBG_TCR. If TRANS_COUNT is used as a trigger, the written value is used immediately as the length of the new transfer sequence, as well as being written to RELOAD."] - #[inline(always)] - pub const fn count(&self) -> u32 { - let val = (self.0 >> 0usize) & 0x0fff_ffff; - val as u32 - } - #[doc = "28-bit transfer count (256 million transfers maximum). Program the number of bus transfers a channel will perform before halting. Note that, if transfers are larger than one byte in size, this is not equal to the number of bytes transferred (see CTRL_DATA_SIZE). When the channel is active, reading this register shows the number of transfers remaining, updating automatically each time a write transfer completes. Writing this register sets the RELOAD value for the transfer counter. Each time this channel is triggered, the RELOAD value is copied into the live transfer counter. The channel can be started multiple times, and will perform the same number of transfers each time, as programmed by most recent write. The RELOAD value can be observed at CHx_DBG_TCR. If TRANS_COUNT is used as a trigger, the written value is used immediately as the length of the new transfer sequence, as well as being written to RELOAD."] - #[inline(always)] - pub fn set_count(&mut self, val: u32) { - self.0 = (self.0 & !(0x0fff_ffff << 0usize)) | (((val as u32) & 0x0fff_ffff) << 0usize); - } - #[doc = "When MODE is 0x0, the transfer count decrements with each transfer until 0, and then the channel triggers the next channel indicated by CTRL_CHAIN_TO. When MODE is 0x1, the transfer count decrements with each transfer until 0, and then the channel re-triggers itself, in addition to the trigger indicated by CTRL_CHAIN_TO. This is useful for e.g. an endless ring-buffer DMA with periodic interrupts. When MODE is 0xf, the transfer count does not decrement. The DMA channel performs an endless sequence of transfers, never triggering other channels or raising interrupts, until an ABORT is raised. All other values are reserved."] - #[inline(always)] - pub const fn mode(&self) -> super::vals::Ch6transCountMode { - let val = (self.0 >> 28usize) & 0x0f; - super::vals::Ch6transCountMode::from_bits(val as u8) - } - #[doc = "When MODE is 0x0, the transfer count decrements with each transfer until 0, and then the channel triggers the next channel indicated by CTRL_CHAIN_TO. When MODE is 0x1, the transfer count decrements with each transfer until 0, and then the channel re-triggers itself, in addition to the trigger indicated by CTRL_CHAIN_TO. This is useful for e.g. an endless ring-buffer DMA with periodic interrupts. When MODE is 0xf, the transfer count does not decrement. The DMA channel performs an endless sequence of transfers, never triggering other channels or raising interrupts, until an ABORT is raised. All other values are reserved."] - #[inline(always)] - pub fn set_mode(&mut self, val: super::vals::Ch6transCountMode) { - self.0 = (self.0 & !(0x0f << 28usize)) | (((val.to_bits() as u32) & 0x0f) << 28usize); - } -} -impl Default for Ch6transCount { - #[inline(always)] - fn default() -> Ch6transCount { - Ch6transCount(0) - } -} -#[doc = "DMA Channel 7 Transfer Count"] -#[repr(transparent)] -#[derive(Copy, Clone, Eq, PartialEq)] -pub struct Ch7transCount(pub u32); -impl Ch7transCount { - #[doc = "28-bit transfer count (256 million transfers maximum). Program the number of bus transfers a channel will perform before halting. Note that, if transfers are larger than one byte in size, this is not equal to the number of bytes transferred (see CTRL_DATA_SIZE). When the channel is active, reading this register shows the number of transfers remaining, updating automatically each time a write transfer completes. Writing this register sets the RELOAD value for the transfer counter. Each time this channel is triggered, the RELOAD value is copied into the live transfer counter. The channel can be started multiple times, and will perform the same number of transfers each time, as programmed by most recent write. The RELOAD value can be observed at CHx_DBG_TCR. If TRANS_COUNT is used as a trigger, the written value is used immediately as the length of the new transfer sequence, as well as being written to RELOAD."] - #[inline(always)] - pub const fn count(&self) -> u32 { - let val = (self.0 >> 0usize) & 0x0fff_ffff; - val as u32 - } - #[doc = "28-bit transfer count (256 million transfers maximum). Program the number of bus transfers a channel will perform before halting. Note that, if transfers are larger than one byte in size, this is not equal to the number of bytes transferred (see CTRL_DATA_SIZE). When the channel is active, reading this register shows the number of transfers remaining, updating automatically each time a write transfer completes. Writing this register sets the RELOAD value for the transfer counter. Each time this channel is triggered, the RELOAD value is copied into the live transfer counter. The channel can be started multiple times, and will perform the same number of transfers each time, as programmed by most recent write. The RELOAD value can be observed at CHx_DBG_TCR. If TRANS_COUNT is used as a trigger, the written value is used immediately as the length of the new transfer sequence, as well as being written to RELOAD."] - #[inline(always)] - pub fn set_count(&mut self, val: u32) { - self.0 = (self.0 & !(0x0fff_ffff << 0usize)) | (((val as u32) & 0x0fff_ffff) << 0usize); - } - #[doc = "When MODE is 0x0, the transfer count decrements with each transfer until 0, and then the channel triggers the next channel indicated by CTRL_CHAIN_TO. When MODE is 0x1, the transfer count decrements with each transfer until 0, and then the channel re-triggers itself, in addition to the trigger indicated by CTRL_CHAIN_TO. This is useful for e.g. an endless ring-buffer DMA with periodic interrupts. When MODE is 0xf, the transfer count does not decrement. The DMA channel performs an endless sequence of transfers, never triggering other channels or raising interrupts, until an ABORT is raised. All other values are reserved."] - #[inline(always)] - pub const fn mode(&self) -> super::vals::Ch7transCountMode { - let val = (self.0 >> 28usize) & 0x0f; - super::vals::Ch7transCountMode::from_bits(val as u8) - } - #[doc = "When MODE is 0x0, the transfer count decrements with each transfer until 0, and then the channel triggers the next channel indicated by CTRL_CHAIN_TO. When MODE is 0x1, the transfer count decrements with each transfer until 0, and then the channel re-triggers itself, in addition to the trigger indicated by CTRL_CHAIN_TO. This is useful for e.g. an endless ring-buffer DMA with periodic interrupts. When MODE is 0xf, the transfer count does not decrement. The DMA channel performs an endless sequence of transfers, never triggering other channels or raising interrupts, until an ABORT is raised. All other values are reserved."] - #[inline(always)] - pub fn set_mode(&mut self, val: super::vals::Ch7transCountMode) { - self.0 = (self.0 & !(0x0f << 28usize)) | (((val.to_bits() as u32) & 0x0f) << 28usize); - } -} -impl Default for Ch7transCount { - #[inline(always)] - fn default() -> Ch7transCount { - Ch7transCount(0) - } -} -#[doc = "DMA Channel 8 Transfer Count"] -#[repr(transparent)] -#[derive(Copy, Clone, Eq, PartialEq)] -pub struct Ch8transCount(pub u32); -impl Ch8transCount { - #[doc = "28-bit transfer count (256 million transfers maximum). Program the number of bus transfers a channel will perform before halting. Note that, if transfers are larger than one byte in size, this is not equal to the number of bytes transferred (see CTRL_DATA_SIZE). When the channel is active, reading this register shows the number of transfers remaining, updating automatically each time a write transfer completes. Writing this register sets the RELOAD value for the transfer counter. Each time this channel is triggered, the RELOAD value is copied into the live transfer counter. The channel can be started multiple times, and will perform the same number of transfers each time, as programmed by most recent write. The RELOAD value can be observed at CHx_DBG_TCR. If TRANS_COUNT is used as a trigger, the written value is used immediately as the length of the new transfer sequence, as well as being written to RELOAD."] - #[inline(always)] - pub const fn count(&self) -> u32 { - let val = (self.0 >> 0usize) & 0x0fff_ffff; - val as u32 - } - #[doc = "28-bit transfer count (256 million transfers maximum). Program the number of bus transfers a channel will perform before halting. Note that, if transfers are larger than one byte in size, this is not equal to the number of bytes transferred (see CTRL_DATA_SIZE). When the channel is active, reading this register shows the number of transfers remaining, updating automatically each time a write transfer completes. Writing this register sets the RELOAD value for the transfer counter. Each time this channel is triggered, the RELOAD value is copied into the live transfer counter. The channel can be started multiple times, and will perform the same number of transfers each time, as programmed by most recent write. The RELOAD value can be observed at CHx_DBG_TCR. If TRANS_COUNT is used as a trigger, the written value is used immediately as the length of the new transfer sequence, as well as being written to RELOAD."] - #[inline(always)] - pub fn set_count(&mut self, val: u32) { - self.0 = (self.0 & !(0x0fff_ffff << 0usize)) | (((val as u32) & 0x0fff_ffff) << 0usize); - } - #[doc = "When MODE is 0x0, the transfer count decrements with each transfer until 0, and then the channel triggers the next channel indicated by CTRL_CHAIN_TO. When MODE is 0x1, the transfer count decrements with each transfer until 0, and then the channel re-triggers itself, in addition to the trigger indicated by CTRL_CHAIN_TO. This is useful for e.g. an endless ring-buffer DMA with periodic interrupts. When MODE is 0xf, the transfer count does not decrement. The DMA channel performs an endless sequence of transfers, never triggering other channels or raising interrupts, until an ABORT is raised. All other values are reserved."] - #[inline(always)] - pub const fn mode(&self) -> super::vals::Ch8transCountMode { - let val = (self.0 >> 28usize) & 0x0f; - super::vals::Ch8transCountMode::from_bits(val as u8) - } - #[doc = "When MODE is 0x0, the transfer count decrements with each transfer until 0, and then the channel triggers the next channel indicated by CTRL_CHAIN_TO. When MODE is 0x1, the transfer count decrements with each transfer until 0, and then the channel re-triggers itself, in addition to the trigger indicated by CTRL_CHAIN_TO. This is useful for e.g. an endless ring-buffer DMA with periodic interrupts. When MODE is 0xf, the transfer count does not decrement. The DMA channel performs an endless sequence of transfers, never triggering other channels or raising interrupts, until an ABORT is raised. All other values are reserved."] - #[inline(always)] - pub fn set_mode(&mut self, val: super::vals::Ch8transCountMode) { - self.0 = (self.0 & !(0x0f << 28usize)) | (((val.to_bits() as u32) & 0x0f) << 28usize); - } -} -impl Default for Ch8transCount { - #[inline(always)] - fn default() -> Ch8transCount { - Ch8transCount(0) - } -} -#[doc = "DMA Channel 9 Transfer Count"] -#[repr(transparent)] -#[derive(Copy, Clone, Eq, PartialEq)] -pub struct Ch9transCount(pub u32); -impl Ch9transCount { - #[doc = "28-bit transfer count (256 million transfers maximum). Program the number of bus transfers a channel will perform before halting. Note that, if transfers are larger than one byte in size, this is not equal to the number of bytes transferred (see CTRL_DATA_SIZE). When the channel is active, reading this register shows the number of transfers remaining, updating automatically each time a write transfer completes. Writing this register sets the RELOAD value for the transfer counter. Each time this channel is triggered, the RELOAD value is copied into the live transfer counter. The channel can be started multiple times, and will perform the same number of transfers each time, as programmed by most recent write. The RELOAD value can be observed at CHx_DBG_TCR. If TRANS_COUNT is used as a trigger, the written value is used immediately as the length of the new transfer sequence, as well as being written to RELOAD."] - #[inline(always)] - pub const fn count(&self) -> u32 { - let val = (self.0 >> 0usize) & 0x0fff_ffff; - val as u32 - } - #[doc = "28-bit transfer count (256 million transfers maximum). Program the number of bus transfers a channel will perform before halting. Note that, if transfers are larger than one byte in size, this is not equal to the number of bytes transferred (see CTRL_DATA_SIZE). When the channel is active, reading this register shows the number of transfers remaining, updating automatically each time a write transfer completes. Writing this register sets the RELOAD value for the transfer counter. Each time this channel is triggered, the RELOAD value is copied into the live transfer counter. The channel can be started multiple times, and will perform the same number of transfers each time, as programmed by most recent write. The RELOAD value can be observed at CHx_DBG_TCR. If TRANS_COUNT is used as a trigger, the written value is used immediately as the length of the new transfer sequence, as well as being written to RELOAD."] - #[inline(always)] - pub fn set_count(&mut self, val: u32) { - self.0 = (self.0 & !(0x0fff_ffff << 0usize)) | (((val as u32) & 0x0fff_ffff) << 0usize); - } - #[doc = "When MODE is 0x0, the transfer count decrements with each transfer until 0, and then the channel triggers the next channel indicated by CTRL_CHAIN_TO. When MODE is 0x1, the transfer count decrements with each transfer until 0, and then the channel re-triggers itself, in addition to the trigger indicated by CTRL_CHAIN_TO. This is useful for e.g. an endless ring-buffer DMA with periodic interrupts. When MODE is 0xf, the transfer count does not decrement. The DMA channel performs an endless sequence of transfers, never triggering other channels or raising interrupts, until an ABORT is raised. All other values are reserved."] - #[inline(always)] - pub const fn mode(&self) -> super::vals::Ch9transCountMode { - let val = (self.0 >> 28usize) & 0x0f; - super::vals::Ch9transCountMode::from_bits(val as u8) - } - #[doc = "When MODE is 0x0, the transfer count decrements with each transfer until 0, and then the channel triggers the next channel indicated by CTRL_CHAIN_TO. When MODE is 0x1, the transfer count decrements with each transfer until 0, and then the channel re-triggers itself, in addition to the trigger indicated by CTRL_CHAIN_TO. This is useful for e.g. an endless ring-buffer DMA with periodic interrupts. When MODE is 0xf, the transfer count does not decrement. The DMA channel performs an endless sequence of transfers, never triggering other channels or raising interrupts, until an ABORT is raised. All other values are reserved."] - #[inline(always)] - pub fn set_mode(&mut self, val: super::vals::Ch9transCountMode) { - self.0 = (self.0 & !(0x0f << 28usize)) | (((val.to_bits() as u32) & 0x0f) << 28usize); - } -} -impl Default for Ch9transCount { - #[inline(always)] - fn default() -> Ch9transCount { - Ch9transCount(0) - } -} -#[doc = "Abort an in-progress transfer sequence on one or more channels"] -#[repr(transparent)] -#[derive(Copy, Clone, Eq, PartialEq)] -pub struct ChanAbort(pub u32); -impl ChanAbort { - #[doc = "Each bit corresponds to a channel. Writing a 1 aborts whatever transfer sequence is in progress on that channel. The bit will remain high until any in-flight transfers have been flushed through the address and data FIFOs. After writing, this register must be polled until it returns all-zero. Until this point, it is unsafe to restart the channel."] - #[inline(always)] - pub const fn chan_abort(&self) -> u16 { - let val = (self.0 >> 0usize) & 0xffff; - val as u16 - } - #[doc = "Each bit corresponds to a channel. Writing a 1 aborts whatever transfer sequence is in progress on that channel. The bit will remain high until any in-flight transfers have been flushed through the address and data FIFOs. After writing, this register must be polled until it returns all-zero. Until this point, it is unsafe to restart the channel."] - #[inline(always)] - pub fn set_chan_abort(&mut self, val: u16) { - self.0 = (self.0 & !(0xffff << 0usize)) | (((val as u32) & 0xffff) << 0usize); - } -} -impl Default for ChanAbort { - #[inline(always)] - fn default() -> ChanAbort { - ChanAbort(0) - } -} -#[doc = "DMA Channel 6 Control and Status"] -#[repr(transparent)] -#[derive(Copy, Clone, Eq, PartialEq)] -pub struct CtrlTrig(pub u32); -impl CtrlTrig { - #[doc = "DMA Channel Enable. When 1, the channel will respond to triggering events, which will cause it to become BUSY and start transferring data. When 0, the channel will ignore triggers, stop issuing transfers, and pause the current transfer sequence (i.e. BUSY will remain high if already high)"] - #[inline(always)] - pub const fn en(&self) -> bool { - let val = (self.0 >> 0usize) & 0x01; - val != 0 - } - #[doc = "DMA Channel Enable. When 1, the channel will respond to triggering events, which will cause it to become BUSY and start transferring data. When 0, the channel will ignore triggers, stop issuing transfers, and pause the current transfer sequence (i.e. BUSY will remain high if already high)"] - #[inline(always)] - pub fn set_en(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize); - } - #[doc = "HIGH_PRIORITY gives a channel preferential treatment in issue scheduling: in each scheduling round, all high priority channels are considered first, and then only a single low priority channel, before returning to the high priority channels. This only affects the order in which the DMA schedules channels. The DMA's bus priority is not changed. If the DMA is not saturated then a low priority channel will see no loss of throughput."] - #[inline(always)] - pub const fn high_priority(&self) -> bool { - let val = (self.0 >> 1usize) & 0x01; - val != 0 - } - #[doc = "HIGH_PRIORITY gives a channel preferential treatment in issue scheduling: in each scheduling round, all high priority channels are considered first, and then only a single low priority channel, before returning to the high priority channels. This only affects the order in which the DMA schedules channels. The DMA's bus priority is not changed. If the DMA is not saturated then a low priority channel will see no loss of throughput."] - #[inline(always)] - pub fn set_high_priority(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize); - } - #[doc = "Set the size of each bus transfer (byte/halfword/word). READ_ADDR and WRITE_ADDR advance by this amount (1/2/4 bytes) with each transfer."] - #[inline(always)] - pub const fn data_size(&self) -> super::vals::DataSize { - let val = (self.0 >> 2usize) & 0x03; - super::vals::DataSize::from_bits(val as u8) - } - #[doc = "Set the size of each bus transfer (byte/halfword/word). READ_ADDR and WRITE_ADDR advance by this amount (1/2/4 bytes) with each transfer."] - #[inline(always)] - pub fn set_data_size(&mut self, val: super::vals::DataSize) { - self.0 = (self.0 & !(0x03 << 2usize)) | (((val.to_bits() as u32) & 0x03) << 2usize); - } - #[doc = "If 1, the read address increments with each transfer. If 0, each read is directed to the same, initial address. Generally this should be disabled for peripheral-to-memory transfers."] - #[inline(always)] - pub const fn incr_read(&self) -> bool { - let val = (self.0 >> 4usize) & 0x01; - val != 0 - } - #[doc = "If 1, the read address increments with each transfer. If 0, each read is directed to the same, initial address. Generally this should be disabled for peripheral-to-memory transfers."] - #[inline(always)] - pub fn set_incr_read(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 4usize)) | (((val as u32) & 0x01) << 4usize); - } - #[doc = "If 1, and INCR_READ is 1, the read address is decremented rather than incremented with each transfer. If 1, and INCR_READ is 0, this otherwise-unused combination causes the read address to be incremented by twice the transfer size, i.e. skipping over alternate addresses."] - #[inline(always)] - pub const fn incr_read_rev(&self) -> bool { - let val = (self.0 >> 5usize) & 0x01; - val != 0 - } - #[doc = "If 1, and INCR_READ is 1, the read address is decremented rather than incremented with each transfer. If 1, and INCR_READ is 0, this otherwise-unused combination causes the read address to be incremented by twice the transfer size, i.e. skipping over alternate addresses."] - #[inline(always)] - pub fn set_incr_read_rev(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 5usize)) | (((val as u32) & 0x01) << 5usize); - } - #[doc = "If 1, the write address increments with each transfer. If 0, each write is directed to the same, initial address. Generally this should be disabled for memory-to-peripheral transfers."] - #[inline(always)] - pub const fn incr_write(&self) -> bool { - let val = (self.0 >> 6usize) & 0x01; - val != 0 - } - #[doc = "If 1, the write address increments with each transfer. If 0, each write is directed to the same, initial address. Generally this should be disabled for memory-to-peripheral transfers."] - #[inline(always)] - pub fn set_incr_write(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 6usize)) | (((val as u32) & 0x01) << 6usize); - } - #[doc = "If 1, and INCR_WRITE is 1, the write address is decremented rather than incremented with each transfer. If 1, and INCR_WRITE is 0, this otherwise-unused combination causes the write address to be incremented by twice the transfer size, i.e. skipping over alternate addresses."] - #[inline(always)] - pub const fn incr_write_rev(&self) -> bool { - let val = (self.0 >> 7usize) & 0x01; - val != 0 - } - #[doc = "If 1, and INCR_WRITE is 1, the write address is decremented rather than incremented with each transfer. If 1, and INCR_WRITE is 0, this otherwise-unused combination causes the write address to be incremented by twice the transfer size, i.e. skipping over alternate addresses."] - #[inline(always)] - pub fn set_incr_write_rev(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 7usize)) | (((val as u32) & 0x01) << 7usize); - } - #[doc = "Size of address wrap region. If 0, don't wrap. For values n > 0, only the lower n bits of the address will change. This wraps the address on a (1 << n) byte boundary, facilitating access to naturally-aligned ring buffers. Ring sizes between 2 and 32768 bytes are possible. This can apply to either read or write addresses, based on value of RING_SEL."] - #[inline(always)] - pub const fn ring_size(&self) -> u8 { - let val = (self.0 >> 8usize) & 0x0f; - val as u8 - } - #[doc = "Size of address wrap region. If 0, don't wrap. For values n > 0, only the lower n bits of the address will change. This wraps the address on a (1 << n) byte boundary, facilitating access to naturally-aligned ring buffers. Ring sizes between 2 and 32768 bytes are possible. This can apply to either read or write addresses, based on value of RING_SEL."] - #[inline(always)] - pub fn set_ring_size(&mut self, val: u8) { - self.0 = (self.0 & !(0x0f << 8usize)) | (((val as u32) & 0x0f) << 8usize); - } - #[doc = "Select whether RING_SIZE applies to read or write addresses. If 0, read addresses are wrapped on a (1 << RING_SIZE) boundary. If 1, write addresses are wrapped."] - #[inline(always)] - pub const fn ring_sel(&self) -> bool { - let val = (self.0 >> 12usize) & 0x01; - val != 0 - } - #[doc = "Select whether RING_SIZE applies to read or write addresses. If 0, read addresses are wrapped on a (1 << RING_SIZE) boundary. If 1, write addresses are wrapped."] - #[inline(always)] - pub fn set_ring_sel(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 12usize)) | (((val as u32) & 0x01) << 12usize); - } - #[doc = "When this channel completes, it will trigger the channel indicated by CHAIN_TO. Disable by setting CHAIN_TO = _(this channel)_. Note this field resets to 0, so channels 1 and above will chain to channel 0 by default. Set this field to avoid this behaviour."] - #[inline(always)] - pub const fn chain_to(&self) -> u8 { - let val = (self.0 >> 13usize) & 0x0f; - val as u8 - } - #[doc = "When this channel completes, it will trigger the channel indicated by CHAIN_TO. Disable by setting CHAIN_TO = _(this channel)_. Note this field resets to 0, so channels 1 and above will chain to channel 0 by default. Set this field to avoid this behaviour."] - #[inline(always)] - pub fn set_chain_to(&mut self, val: u8) { - self.0 = (self.0 & !(0x0f << 13usize)) | (((val as u32) & 0x0f) << 13usize); - } - #[doc = "Select a Transfer Request signal. The channel uses the transfer request signal to pace its data transfer rate. Sources for TREQ signals are internal (TIMERS) or external (DREQ, a Data Request from the system). 0x0 to 0x3a -> select DREQ n as TREQ"] - #[inline(always)] - pub const fn treq_sel(&self) -> super::vals::TreqSel { - let val = (self.0 >> 17usize) & 0x3f; - super::vals::TreqSel::from_bits(val as u8) - } - #[doc = "Select a Transfer Request signal. The channel uses the transfer request signal to pace its data transfer rate. Sources for TREQ signals are internal (TIMERS) or external (DREQ, a Data Request from the system). 0x0 to 0x3a -> select DREQ n as TREQ"] - #[inline(always)] - pub fn set_treq_sel(&mut self, val: super::vals::TreqSel) { - self.0 = (self.0 & !(0x3f << 17usize)) | (((val.to_bits() as u32) & 0x3f) << 17usize); - } - #[doc = "In QUIET mode, the channel does not generate IRQs at the end of every transfer block. Instead, an IRQ is raised when NULL is written to a trigger register, indicating the end of a control block chain. This reduces the number of interrupts to be serviced by the CPU when transferring a DMA chain of many small control blocks."] - #[inline(always)] - pub const fn irq_quiet(&self) -> bool { - let val = (self.0 >> 23usize) & 0x01; - val != 0 - } - #[doc = "In QUIET mode, the channel does not generate IRQs at the end of every transfer block. Instead, an IRQ is raised when NULL is written to a trigger register, indicating the end of a control block chain. This reduces the number of interrupts to be serviced by the CPU when transferring a DMA chain of many small control blocks."] - #[inline(always)] - pub fn set_irq_quiet(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 23usize)) | (((val as u32) & 0x01) << 23usize); - } - #[doc = "Apply byte-swap transformation to DMA data. For byte data, this has no effect. For halfword data, the two bytes of each halfword are swapped. For word data, the four bytes of each word are swapped to reverse order."] - #[inline(always)] - pub const fn bswap(&self) -> bool { - let val = (self.0 >> 24usize) & 0x01; - val != 0 - } - #[doc = "Apply byte-swap transformation to DMA data. For byte data, this has no effect. For halfword data, the two bytes of each halfword are swapped. For word data, the four bytes of each word are swapped to reverse order."] - #[inline(always)] - pub fn set_bswap(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 24usize)) | (((val as u32) & 0x01) << 24usize); - } - #[doc = "If 1, this channel's data transfers are visible to the sniff hardware, and each transfer will advance the state of the checksum. This only applies if the sniff hardware is enabled, and has this channel selected. This allows checksum to be enabled or disabled on a per-control- block basis."] - #[inline(always)] - pub const fn sniff_en(&self) -> bool { - let val = (self.0 >> 25usize) & 0x01; - val != 0 - } - #[doc = "If 1, this channel's data transfers are visible to the sniff hardware, and each transfer will advance the state of the checksum. This only applies if the sniff hardware is enabled, and has this channel selected. This allows checksum to be enabled or disabled on a per-control- block basis."] - #[inline(always)] - pub fn set_sniff_en(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 25usize)) | (((val as u32) & 0x01) << 25usize); - } - #[doc = "This flag goes high when the channel starts a new transfer sequence, and low when the last transfer of that sequence completes. Clearing EN while BUSY is high pauses the channel, and BUSY will stay high while paused. To terminate a sequence early (and clear the BUSY flag), see CHAN_ABORT."] - #[inline(always)] - pub const fn busy(&self) -> bool { - let val = (self.0 >> 26usize) & 0x01; - val != 0 - } - #[doc = "This flag goes high when the channel starts a new transfer sequence, and low when the last transfer of that sequence completes. Clearing EN while BUSY is high pauses the channel, and BUSY will stay high while paused. To terminate a sequence early (and clear the BUSY flag), see CHAN_ABORT."] - #[inline(always)] - pub fn set_busy(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 26usize)) | (((val as u32) & 0x01) << 26usize); - } - #[doc = "If 1, the channel received a write bus error. Write one to clear. WRITE_ADDR shows the approximate address where the bus error was encountered (will not be earlier, or more than 5 transfers later)"] - #[inline(always)] - pub const fn write_error(&self) -> bool { - let val = (self.0 >> 29usize) & 0x01; - val != 0 - } - #[doc = "If 1, the channel received a write bus error. Write one to clear. WRITE_ADDR shows the approximate address where the bus error was encountered (will not be earlier, or more than 5 transfers later)"] - #[inline(always)] - pub fn set_write_error(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 29usize)) | (((val as u32) & 0x01) << 29usize); - } - #[doc = "If 1, the channel received a read bus error. Write one to clear. READ_ADDR shows the approximate address where the bus error was encountered (will not be earlier, or more than 3 transfers later)"] - #[inline(always)] - pub const fn read_error(&self) -> bool { - let val = (self.0 >> 30usize) & 0x01; - val != 0 - } - #[doc = "If 1, the channel received a read bus error. Write one to clear. READ_ADDR shows the approximate address where the bus error was encountered (will not be earlier, or more than 3 transfers later)"] - #[inline(always)] - pub fn set_read_error(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 30usize)) | (((val as u32) & 0x01) << 30usize); - } - #[doc = "Logical OR of the READ_ERROR and WRITE_ERROR flags. The channel halts when it encounters any bus error, and always raises its channel IRQ flag."] - #[inline(always)] - pub const fn ahb_error(&self) -> bool { - let val = (self.0 >> 31usize) & 0x01; - val != 0 - } - #[doc = "Logical OR of the READ_ERROR and WRITE_ERROR flags. The channel halts when it encounters any bus error, and always raises its channel IRQ flag."] - #[inline(always)] - pub fn set_ahb_error(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 31usize)) | (((val as u32) & 0x01) << 31usize); - } -} -impl Default for CtrlTrig { - #[inline(always)] - fn default() -> CtrlTrig { - CtrlTrig(0) - } -} -#[doc = "Read: get channel DREQ counter (i.e. how many accesses the DMA expects it can perform on the peripheral without overflow/underflow. Write any value: clears the counter, and cause channel to re-initiate DREQ handshake."] -#[repr(transparent)] -#[derive(Copy, Clone, Eq, PartialEq)] -pub struct DbgCtdreq(pub u32); -impl DbgCtdreq { - #[inline(always)] - pub const fn dbg_ctdreq(&self) -> u8 { - let val = (self.0 >> 0usize) & 0x3f; - val as u8 - } - #[inline(always)] - pub fn set_dbg_ctdreq(&mut self, val: u8) { - self.0 = (self.0 & !(0x3f << 0usize)) | (((val as u32) & 0x3f) << 0usize); - } -} -impl Default for DbgCtdreq { - #[inline(always)] - fn default() -> DbgCtdreq { - DbgCtdreq(0) - } -} -#[doc = "Debug RAF, WAF, TDF levels"] -#[repr(transparent)] -#[derive(Copy, Clone, Eq, PartialEq)] -pub struct FifoLevels(pub u32); -impl FifoLevels { - #[doc = "Current Transfer-Data-FIFO fill level"] - #[inline(always)] - pub const fn tdf_lvl(&self) -> u8 { - let val = (self.0 >> 0usize) & 0xff; - val as u8 - } - #[doc = "Current Transfer-Data-FIFO fill level"] - #[inline(always)] - pub fn set_tdf_lvl(&mut self, val: u8) { - self.0 = (self.0 & !(0xff << 0usize)) | (((val as u32) & 0xff) << 0usize); - } - #[doc = "Current Write-Address-FIFO fill level"] - #[inline(always)] - pub const fn waf_lvl(&self) -> u8 { - let val = (self.0 >> 8usize) & 0xff; - val as u8 - } - #[doc = "Current Write-Address-FIFO fill level"] - #[inline(always)] - pub fn set_waf_lvl(&mut self, val: u8) { - self.0 = (self.0 & !(0xff << 8usize)) | (((val as u32) & 0xff) << 8usize); - } - #[doc = "Current Read-Address-FIFO fill level"] - #[inline(always)] - pub const fn raf_lvl(&self) -> u8 { - let val = (self.0 >> 16usize) & 0xff; - val as u8 - } - #[doc = "Current Read-Address-FIFO fill level"] - #[inline(always)] - pub fn set_raf_lvl(&mut self, val: u8) { - self.0 = (self.0 & !(0xff << 16usize)) | (((val as u32) & 0xff) << 16usize); - } -} -impl Default for FifoLevels { - #[inline(always)] - fn default() -> FifoLevels { - FifoLevels(0) - } -} -#[doc = "Interrupt Enables for IRQ 0"] -#[repr(transparent)] -#[derive(Copy, Clone, Eq, PartialEq)] -pub struct Inte0(pub u32); -impl Inte0 { - #[doc = "Set bit n to pass interrupts from channel n to DMA IRQ 0. Note this bit has no effect if the channel security/privilege level, defined by SECCFG_CHx, is greater than the IRQ security/privilege defined by SECCFG_IRQ0."] - #[inline(always)] - pub const fn inte0(&self) -> u16 { - let val = (self.0 >> 0usize) & 0xffff; - val as u16 - } - #[doc = "Set bit n to pass interrupts from channel n to DMA IRQ 0. Note this bit has no effect if the channel security/privilege level, defined by SECCFG_CHx, is greater than the IRQ security/privilege defined by SECCFG_IRQ0."] - #[inline(always)] - pub fn set_inte0(&mut self, val: u16) { - self.0 = (self.0 & !(0xffff << 0usize)) | (((val as u32) & 0xffff) << 0usize); - } -} -impl Default for Inte0 { - #[inline(always)] - fn default() -> Inte0 { - Inte0(0) - } -} -#[doc = "Interrupt Enables for IRQ 1"] -#[repr(transparent)] -#[derive(Copy, Clone, Eq, PartialEq)] -pub struct Inte1(pub u32); -impl Inte1 { - #[doc = "Set bit n to pass interrupts from channel n to DMA IRQ 1. Note this bit has no effect if the channel security/privilege level, defined by SECCFG_CHx, is greater than the IRQ security/privilege defined by SECCFG_IRQ1."] - #[inline(always)] - pub const fn inte1(&self) -> u16 { - let val = (self.0 >> 0usize) & 0xffff; - val as u16 - } - #[doc = "Set bit n to pass interrupts from channel n to DMA IRQ 1. Note this bit has no effect if the channel security/privilege level, defined by SECCFG_CHx, is greater than the IRQ security/privilege defined by SECCFG_IRQ1."] - #[inline(always)] - pub fn set_inte1(&mut self, val: u16) { - self.0 = (self.0 & !(0xffff << 0usize)) | (((val as u32) & 0xffff) << 0usize); - } -} -impl Default for Inte1 { - #[inline(always)] - fn default() -> Inte1 { - Inte1(0) - } -} -#[doc = "Interrupt Enables for IRQ 2"] -#[repr(transparent)] -#[derive(Copy, Clone, Eq, PartialEq)] -pub struct Inte2(pub u32); -impl Inte2 { - #[doc = "Set bit n to pass interrupts from channel n to DMA IRQ 2. Note this bit has no effect if the channel security/privilege level, defined by SECCFG_CHx, is greater than the IRQ security/privilege defined by SECCFG_IRQ2."] - #[inline(always)] - pub const fn inte2(&self) -> u16 { - let val = (self.0 >> 0usize) & 0xffff; - val as u16 - } - #[doc = "Set bit n to pass interrupts from channel n to DMA IRQ 2. Note this bit has no effect if the channel security/privilege level, defined by SECCFG_CHx, is greater than the IRQ security/privilege defined by SECCFG_IRQ2."] - #[inline(always)] - pub fn set_inte2(&mut self, val: u16) { - self.0 = (self.0 & !(0xffff << 0usize)) | (((val as u32) & 0xffff) << 0usize); - } -} -impl Default for Inte2 { - #[inline(always)] - fn default() -> Inte2 { - Inte2(0) - } -} -#[doc = "Interrupt Enables for IRQ 3"] -#[repr(transparent)] -#[derive(Copy, Clone, Eq, PartialEq)] -pub struct Inte3(pub u32); -impl Inte3 { - #[doc = "Set bit n to pass interrupts from channel n to DMA IRQ 3. Note this bit has no effect if the channel security/privilege level, defined by SECCFG_CHx, is greater than the IRQ security/privilege defined by SECCFG_IRQ3."] - #[inline(always)] - pub const fn inte3(&self) -> u16 { - let val = (self.0 >> 0usize) & 0xffff; - val as u16 - } - #[doc = "Set bit n to pass interrupts from channel n to DMA IRQ 3. Note this bit has no effect if the channel security/privilege level, defined by SECCFG_CHx, is greater than the IRQ security/privilege defined by SECCFG_IRQ3."] - #[inline(always)] - pub fn set_inte3(&mut self, val: u16) { - self.0 = (self.0 & !(0xffff << 0usize)) | (((val as u32) & 0xffff) << 0usize); - } -} -impl Default for Inte3 { - #[inline(always)] - fn default() -> Inte3 { - Inte3(0) - } -} -#[doc = "Force Interrupts"] -#[repr(transparent)] -#[derive(Copy, Clone, Eq, PartialEq)] -pub struct Intf0(pub u32); -impl Intf0 { - #[doc = "Write 1s to force the corresponding bits in INTS0. The interrupt remains asserted until INTF0 is cleared."] - #[inline(always)] - pub const fn intf0(&self) -> u16 { - let val = (self.0 >> 0usize) & 0xffff; - val as u16 - } - #[doc = "Write 1s to force the corresponding bits in INTS0. The interrupt remains asserted until INTF0 is cleared."] - #[inline(always)] - pub fn set_intf0(&mut self, val: u16) { - self.0 = (self.0 & !(0xffff << 0usize)) | (((val as u32) & 0xffff) << 0usize); - } -} -impl Default for Intf0 { - #[inline(always)] - fn default() -> Intf0 { - Intf0(0) - } -} -#[doc = "Force Interrupts"] -#[repr(transparent)] -#[derive(Copy, Clone, Eq, PartialEq)] -pub struct Intf1(pub u32); -impl Intf1 { - #[doc = "Write 1s to force the corresponding bits in INTS1. The interrupt remains asserted until INTF1 is cleared."] - #[inline(always)] - pub const fn intf1(&self) -> u16 { - let val = (self.0 >> 0usize) & 0xffff; - val as u16 - } - #[doc = "Write 1s to force the corresponding bits in INTS1. The interrupt remains asserted until INTF1 is cleared."] - #[inline(always)] - pub fn set_intf1(&mut self, val: u16) { - self.0 = (self.0 & !(0xffff << 0usize)) | (((val as u32) & 0xffff) << 0usize); - } -} -impl Default for Intf1 { - #[inline(always)] - fn default() -> Intf1 { - Intf1(0) - } -} -#[doc = "Force Interrupts"] -#[repr(transparent)] -#[derive(Copy, Clone, Eq, PartialEq)] -pub struct Intf2(pub u32); -impl Intf2 { - #[doc = "Write 1s to force the corresponding bits in INTS2. The interrupt remains asserted until INTF2 is cleared."] - #[inline(always)] - pub const fn intf2(&self) -> u16 { - let val = (self.0 >> 0usize) & 0xffff; - val as u16 - } - #[doc = "Write 1s to force the corresponding bits in INTS2. The interrupt remains asserted until INTF2 is cleared."] - #[inline(always)] - pub fn set_intf2(&mut self, val: u16) { - self.0 = (self.0 & !(0xffff << 0usize)) | (((val as u32) & 0xffff) << 0usize); - } -} -impl Default for Intf2 { - #[inline(always)] - fn default() -> Intf2 { - Intf2(0) - } -} -#[doc = "Force Interrupts"] -#[repr(transparent)] -#[derive(Copy, Clone, Eq, PartialEq)] -pub struct Intf3(pub u32); -impl Intf3 { - #[doc = "Write 1s to force the corresponding bits in INTS3. The interrupt remains asserted until INTF3 is cleared."] - #[inline(always)] - pub const fn intf3(&self) -> u16 { - let val = (self.0 >> 0usize) & 0xffff; - val as u16 - } - #[doc = "Write 1s to force the corresponding bits in INTS3. The interrupt remains asserted until INTF3 is cleared."] - #[inline(always)] - pub fn set_intf3(&mut self, val: u16) { - self.0 = (self.0 & !(0xffff << 0usize)) | (((val as u32) & 0xffff) << 0usize); - } -} -impl Default for Intf3 { - #[inline(always)] - fn default() -> Intf3 { - Intf3(0) - } -} -#[doc = "Interrupt Status (raw)"] -#[repr(transparent)] -#[derive(Copy, Clone, Eq, PartialEq)] -pub struct Intr(pub u32); -impl Intr { - #[doc = "Raw interrupt status for DMA Channels 0..15. Bit n corresponds to channel n. Ignores any masking or forcing. Channel interrupts can be cleared by writing a bit mask to INTR or INTS0/1/2/3. Channel interrupts can be routed to either of four system-level IRQs based on INTE0, INTE1, INTE2 and INTE3. The multiple system-level interrupts might be used to allow NVIC IRQ preemption for more time-critical channels, to spread IRQ load across different cores, or to target IRQs to different security domains. It is also valid to ignore the multiple IRQs, and just use INTE0/INTS0/IRQ 0. If this register is accessed at a security/privilege level less than that of a given channel (as defined by that channel's SECCFG_CHx register), then that channel's interrupt status will read as 0, ignore writes."] - #[inline(always)] - pub const fn intr(&self) -> u16 { - let val = (self.0 >> 0usize) & 0xffff; - val as u16 - } - #[doc = "Raw interrupt status for DMA Channels 0..15. Bit n corresponds to channel n. Ignores any masking or forcing. Channel interrupts can be cleared by writing a bit mask to INTR or INTS0/1/2/3. Channel interrupts can be routed to either of four system-level IRQs based on INTE0, INTE1, INTE2 and INTE3. The multiple system-level interrupts might be used to allow NVIC IRQ preemption for more time-critical channels, to spread IRQ load across different cores, or to target IRQs to different security domains. It is also valid to ignore the multiple IRQs, and just use INTE0/INTS0/IRQ 0. If this register is accessed at a security/privilege level less than that of a given channel (as defined by that channel's SECCFG_CHx register), then that channel's interrupt status will read as 0, ignore writes."] - #[inline(always)] - pub fn set_intr(&mut self, val: u16) { - self.0 = (self.0 & !(0xffff << 0usize)) | (((val as u32) & 0xffff) << 0usize); - } -} -impl Default for Intr { - #[inline(always)] - fn default() -> Intr { - Intr(0) - } -} -#[doc = "Interrupt Status (raw)"] -#[repr(transparent)] -#[derive(Copy, Clone, Eq, PartialEq)] -pub struct Intr1(pub u32); -impl Intr1 { - #[doc = "Raw interrupt status for DMA Channels 0..15. Bit n corresponds to channel n. Ignores any masking or forcing. Channel interrupts can be cleared by writing a bit mask to INTR or INTS0/1/2/3. Channel interrupts can be routed to either of four system-level IRQs based on INTE0, INTE1, INTE2 and INTE3. The multiple system-level interrupts might be used to allow NVIC IRQ preemption for more time-critical channels, to spread IRQ load across different cores, or to target IRQs to different security domains. It is also valid to ignore the multiple IRQs, and just use INTE0/INTS0/IRQ 0. If this register is accessed at a security/privilege level less than that of a given channel (as defined by that channel's SECCFG_CHx register), then that channel's interrupt status will read as 0, ignore writes."] - #[inline(always)] - pub const fn intr1(&self) -> u16 { - let val = (self.0 >> 0usize) & 0xffff; - val as u16 - } - #[doc = "Raw interrupt status for DMA Channels 0..15. Bit n corresponds to channel n. Ignores any masking or forcing. Channel interrupts can be cleared by writing a bit mask to INTR or INTS0/1/2/3. Channel interrupts can be routed to either of four system-level IRQs based on INTE0, INTE1, INTE2 and INTE3. The multiple system-level interrupts might be used to allow NVIC IRQ preemption for more time-critical channels, to spread IRQ load across different cores, or to target IRQs to different security domains. It is also valid to ignore the multiple IRQs, and just use INTE0/INTS0/IRQ 0. If this register is accessed at a security/privilege level less than that of a given channel (as defined by that channel's SECCFG_CHx register), then that channel's interrupt status will read as 0, ignore writes."] - #[inline(always)] - pub fn set_intr1(&mut self, val: u16) { - self.0 = (self.0 & !(0xffff << 0usize)) | (((val as u32) & 0xffff) << 0usize); - } -} -impl Default for Intr1 { - #[inline(always)] - fn default() -> Intr1 { - Intr1(0) - } -} -#[doc = "Interrupt Status (raw)"] -#[repr(transparent)] -#[derive(Copy, Clone, Eq, PartialEq)] -pub struct Intr2(pub u32); -impl Intr2 { - #[doc = "Raw interrupt status for DMA Channels 0..15. Bit n corresponds to channel n. Ignores any masking or forcing. Channel interrupts can be cleared by writing a bit mask to INTR or INTS0/1/2/3. Channel interrupts can be routed to either of four system-level IRQs based on INTE0, INTE1, INTE2 and INTE3. The multiple system-level interrupts might be used to allow NVIC IRQ preemption for more time-critical channels, to spread IRQ load across different cores, or to target IRQs to different security domains. It is also valid to ignore the multiple IRQs, and just use INTE0/INTS0/IRQ 0. If this register is accessed at a security/privilege level less than that of a given channel (as defined by that channel's SECCFG_CHx register), then that channel's interrupt status will read as 0, ignore writes."] - #[inline(always)] - pub const fn intr2(&self) -> u16 { - let val = (self.0 >> 0usize) & 0xffff; - val as u16 - } - #[doc = "Raw interrupt status for DMA Channels 0..15. Bit n corresponds to channel n. Ignores any masking or forcing. Channel interrupts can be cleared by writing a bit mask to INTR or INTS0/1/2/3. Channel interrupts can be routed to either of four system-level IRQs based on INTE0, INTE1, INTE2 and INTE3. The multiple system-level interrupts might be used to allow NVIC IRQ preemption for more time-critical channels, to spread IRQ load across different cores, or to target IRQs to different security domains. It is also valid to ignore the multiple IRQs, and just use INTE0/INTS0/IRQ 0. If this register is accessed at a security/privilege level less than that of a given channel (as defined by that channel's SECCFG_CHx register), then that channel's interrupt status will read as 0, ignore writes."] - #[inline(always)] - pub fn set_intr2(&mut self, val: u16) { - self.0 = (self.0 & !(0xffff << 0usize)) | (((val as u32) & 0xffff) << 0usize); - } -} -impl Default for Intr2 { - #[inline(always)] - fn default() -> Intr2 { - Intr2(0) - } -} -#[doc = "Interrupt Status (raw)"] -#[repr(transparent)] -#[derive(Copy, Clone, Eq, PartialEq)] -pub struct Intr3(pub u32); -impl Intr3 { - #[doc = "Raw interrupt status for DMA Channels 0..15. Bit n corresponds to channel n. Ignores any masking or forcing. Channel interrupts can be cleared by writing a bit mask to INTR or INTS0/1/2/3. Channel interrupts can be routed to either of four system-level IRQs based on INTE0, INTE1, INTE2 and INTE3. The multiple system-level interrupts might be used to allow NVIC IRQ preemption for more time-critical channels, to spread IRQ load across different cores, or to target IRQs to different security domains. It is also valid to ignore the multiple IRQs, and just use INTE0/INTS0/IRQ 0. If this register is accessed at a security/privilege level less than that of a given channel (as defined by that channel's SECCFG_CHx register), then that channel's interrupt status will read as 0, ignore writes."] - #[inline(always)] - pub const fn intr3(&self) -> u16 { - let val = (self.0 >> 0usize) & 0xffff; - val as u16 - } - #[doc = "Raw interrupt status for DMA Channels 0..15. Bit n corresponds to channel n. Ignores any masking or forcing. Channel interrupts can be cleared by writing a bit mask to INTR or INTS0/1/2/3. Channel interrupts can be routed to either of four system-level IRQs based on INTE0, INTE1, INTE2 and INTE3. The multiple system-level interrupts might be used to allow NVIC IRQ preemption for more time-critical channels, to spread IRQ load across different cores, or to target IRQs to different security domains. It is also valid to ignore the multiple IRQs, and just use INTE0/INTS0/IRQ 0. If this register is accessed at a security/privilege level less than that of a given channel (as defined by that channel's SECCFG_CHx register), then that channel's interrupt status will read as 0, ignore writes."] - #[inline(always)] - pub fn set_intr3(&mut self, val: u16) { - self.0 = (self.0 & !(0xffff << 0usize)) | (((val as u32) & 0xffff) << 0usize); - } -} -impl Default for Intr3 { - #[inline(always)] - fn default() -> Intr3 { - Intr3(0) - } -} -#[doc = "Interrupt Status for IRQ 0"] -#[repr(transparent)] -#[derive(Copy, Clone, Eq, PartialEq)] -pub struct Ints0(pub u32); -impl Ints0 { - #[doc = "Indicates active channel interrupt requests which are currently causing IRQ 0 to be asserted. Channel interrupts can be cleared by writing a bit mask here. Channels with a security/privilege (SECCFG_CHx) greater SECCFG_IRQ0) read as 0 in this register, and ignore writes."] - #[inline(always)] - pub const fn ints0(&self) -> u16 { - let val = (self.0 >> 0usize) & 0xffff; - val as u16 - } - #[doc = "Indicates active channel interrupt requests which are currently causing IRQ 0 to be asserted. Channel interrupts can be cleared by writing a bit mask here. Channels with a security/privilege (SECCFG_CHx) greater SECCFG_IRQ0) read as 0 in this register, and ignore writes."] - #[inline(always)] - pub fn set_ints0(&mut self, val: u16) { - self.0 = (self.0 & !(0xffff << 0usize)) | (((val as u32) & 0xffff) << 0usize); - } -} -impl Default for Ints0 { - #[inline(always)] - fn default() -> Ints0 { - Ints0(0) - } -} -#[doc = "Interrupt Status for IRQ 1"] -#[repr(transparent)] -#[derive(Copy, Clone, Eq, PartialEq)] -pub struct Ints1(pub u32); -impl Ints1 { - #[doc = "Indicates active channel interrupt requests which are currently causing IRQ 1 to be asserted. Channel interrupts can be cleared by writing a bit mask here. Channels with a security/privilege (SECCFG_CHx) greater SECCFG_IRQ1) read as 0 in this register, and ignore writes."] - #[inline(always)] - pub const fn ints1(&self) -> u16 { - let val = (self.0 >> 0usize) & 0xffff; - val as u16 - } - #[doc = "Indicates active channel interrupt requests which are currently causing IRQ 1 to be asserted. Channel interrupts can be cleared by writing a bit mask here. Channels with a security/privilege (SECCFG_CHx) greater SECCFG_IRQ1) read as 0 in this register, and ignore writes."] - #[inline(always)] - pub fn set_ints1(&mut self, val: u16) { - self.0 = (self.0 & !(0xffff << 0usize)) | (((val as u32) & 0xffff) << 0usize); - } -} -impl Default for Ints1 { - #[inline(always)] - fn default() -> Ints1 { - Ints1(0) - } -} -#[doc = "Interrupt Status for IRQ 2"] -#[repr(transparent)] -#[derive(Copy, Clone, Eq, PartialEq)] -pub struct Ints2(pub u32); -impl Ints2 { - #[doc = "Indicates active channel interrupt requests which are currently causing IRQ 2 to be asserted. Channel interrupts can be cleared by writing a bit mask here. Channels with a security/privilege (SECCFG_CHx) greater SECCFG_IRQ2) read as 0 in this register, and ignore writes."] - #[inline(always)] - pub const fn ints2(&self) -> u16 { - let val = (self.0 >> 0usize) & 0xffff; - val as u16 - } - #[doc = "Indicates active channel interrupt requests which are currently causing IRQ 2 to be asserted. Channel interrupts can be cleared by writing a bit mask here. Channels with a security/privilege (SECCFG_CHx) greater SECCFG_IRQ2) read as 0 in this register, and ignore writes."] - #[inline(always)] - pub fn set_ints2(&mut self, val: u16) { - self.0 = (self.0 & !(0xffff << 0usize)) | (((val as u32) & 0xffff) << 0usize); - } -} -impl Default for Ints2 { - #[inline(always)] - fn default() -> Ints2 { - Ints2(0) - } -} -#[doc = "Interrupt Status for IRQ 3"] -#[repr(transparent)] -#[derive(Copy, Clone, Eq, PartialEq)] -pub struct Ints3(pub u32); -impl Ints3 { - #[doc = "Indicates active channel interrupt requests which are currently causing IRQ 3 to be asserted. Channel interrupts can be cleared by writing a bit mask here. Channels with a security/privilege (SECCFG_CHx) greater SECCFG_IRQ3) read as 0 in this register, and ignore writes."] - #[inline(always)] - pub const fn ints3(&self) -> u16 { - let val = (self.0 >> 0usize) & 0xffff; - val as u16 - } - #[doc = "Indicates active channel interrupt requests which are currently causing IRQ 3 to be asserted. Channel interrupts can be cleared by writing a bit mask here. Channels with a security/privilege (SECCFG_CHx) greater SECCFG_IRQ3) read as 0 in this register, and ignore writes."] - #[inline(always)] - pub fn set_ints3(&mut self, val: u16) { - self.0 = (self.0 & !(0xffff << 0usize)) | (((val as u32) & 0xffff) << 0usize); - } -} -impl Default for Ints3 { - #[inline(always)] - fn default() -> Ints3 { - Ints3(0) - } -} -#[doc = "Base address register for MPU region 0. Writable only from a Secure, Privileged context."] -#[repr(transparent)] -#[derive(Copy, Clone, Eq, PartialEq)] -pub struct MpuBar0(pub u32); -impl MpuBar0 { - #[doc = "This MPU region matches addresses where addr\\[31:5\\] (the 27 most significant bits) are greater than or equal to BAR_ADDR, and less than or equal to LAR_ADDR. Readable from any Privileged context, if and only if this region's S bit is clear, and MPU_CTRL_NS_HIDE_ADDR is clear. Otherwise readable only from a Secure, Privileged context."] - #[inline(always)] - pub const fn addr(&self) -> u32 { - let val = (self.0 >> 5usize) & 0x07ff_ffff; - val as u32 - } - #[doc = "This MPU region matches addresses where addr\\[31:5\\] (the 27 most significant bits) are greater than or equal to BAR_ADDR, and less than or equal to LAR_ADDR. Readable from any Privileged context, if and only if this region's S bit is clear, and MPU_CTRL_NS_HIDE_ADDR is clear. Otherwise readable only from a Secure, Privileged context."] - #[inline(always)] - pub fn set_addr(&mut self, val: u32) { - self.0 = (self.0 & !(0x07ff_ffff << 5usize)) | (((val as u32) & 0x07ff_ffff) << 5usize); - } -} -impl Default for MpuBar0 { - #[inline(always)] - fn default() -> MpuBar0 { - MpuBar0(0) - } -} -#[doc = "Base address register for MPU region 1. Writable only from a Secure, Privileged context."] -#[repr(transparent)] -#[derive(Copy, Clone, Eq, PartialEq)] -pub struct MpuBar1(pub u32); -impl MpuBar1 { - #[doc = "This MPU region matches addresses where addr\\[31:5\\] (the 27 most significant bits) are greater than or equal to BAR_ADDR, and less than or equal to LAR_ADDR. Readable from any Privileged context, if and only if this region's S bit is clear, and MPU_CTRL_NS_HIDE_ADDR is clear. Otherwise readable only from a Secure, Privileged context."] - #[inline(always)] - pub const fn addr(&self) -> u32 { - let val = (self.0 >> 5usize) & 0x07ff_ffff; - val as u32 - } - #[doc = "This MPU region matches addresses where addr\\[31:5\\] (the 27 most significant bits) are greater than or equal to BAR_ADDR, and less than or equal to LAR_ADDR. Readable from any Privileged context, if and only if this region's S bit is clear, and MPU_CTRL_NS_HIDE_ADDR is clear. Otherwise readable only from a Secure, Privileged context."] - #[inline(always)] - pub fn set_addr(&mut self, val: u32) { - self.0 = (self.0 & !(0x07ff_ffff << 5usize)) | (((val as u32) & 0x07ff_ffff) << 5usize); - } -} -impl Default for MpuBar1 { - #[inline(always)] - fn default() -> MpuBar1 { - MpuBar1(0) - } -} -#[doc = "Base address register for MPU region 2. Writable only from a Secure, Privileged context."] -#[repr(transparent)] -#[derive(Copy, Clone, Eq, PartialEq)] -pub struct MpuBar2(pub u32); -impl MpuBar2 { - #[doc = "This MPU region matches addresses where addr\\[31:5\\] (the 27 most significant bits) are greater than or equal to BAR_ADDR, and less than or equal to LAR_ADDR. Readable from any Privileged context, if and only if this region's S bit is clear, and MPU_CTRL_NS_HIDE_ADDR is clear. Otherwise readable only from a Secure, Privileged context."] - #[inline(always)] - pub const fn addr(&self) -> u32 { - let val = (self.0 >> 5usize) & 0x07ff_ffff; - val as u32 - } - #[doc = "This MPU region matches addresses where addr\\[31:5\\] (the 27 most significant bits) are greater than or equal to BAR_ADDR, and less than or equal to LAR_ADDR. Readable from any Privileged context, if and only if this region's S bit is clear, and MPU_CTRL_NS_HIDE_ADDR is clear. Otherwise readable only from a Secure, Privileged context."] - #[inline(always)] - pub fn set_addr(&mut self, val: u32) { - self.0 = (self.0 & !(0x07ff_ffff << 5usize)) | (((val as u32) & 0x07ff_ffff) << 5usize); - } -} -impl Default for MpuBar2 { - #[inline(always)] - fn default() -> MpuBar2 { - MpuBar2(0) - } -} -#[doc = "Base address register for MPU region 3. Writable only from a Secure, Privileged context."] -#[repr(transparent)] -#[derive(Copy, Clone, Eq, PartialEq)] -pub struct MpuBar3(pub u32); -impl MpuBar3 { - #[doc = "This MPU region matches addresses where addr\\[31:5\\] (the 27 most significant bits) are greater than or equal to BAR_ADDR, and less than or equal to LAR_ADDR. Readable from any Privileged context, if and only if this region's S bit is clear, and MPU_CTRL_NS_HIDE_ADDR is clear. Otherwise readable only from a Secure, Privileged context."] - #[inline(always)] - pub const fn addr(&self) -> u32 { - let val = (self.0 >> 5usize) & 0x07ff_ffff; - val as u32 - } - #[doc = "This MPU region matches addresses where addr\\[31:5\\] (the 27 most significant bits) are greater than or equal to BAR_ADDR, and less than or equal to LAR_ADDR. Readable from any Privileged context, if and only if this region's S bit is clear, and MPU_CTRL_NS_HIDE_ADDR is clear. Otherwise readable only from a Secure, Privileged context."] - #[inline(always)] - pub fn set_addr(&mut self, val: u32) { - self.0 = (self.0 & !(0x07ff_ffff << 5usize)) | (((val as u32) & 0x07ff_ffff) << 5usize); - } -} -impl Default for MpuBar3 { - #[inline(always)] - fn default() -> MpuBar3 { - MpuBar3(0) - } -} -#[doc = "Base address register for MPU region 4. Writable only from a Secure, Privileged context."] -#[repr(transparent)] -#[derive(Copy, Clone, Eq, PartialEq)] -pub struct MpuBar4(pub u32); -impl MpuBar4 { - #[doc = "This MPU region matches addresses where addr\\[31:5\\] (the 27 most significant bits) are greater than or equal to BAR_ADDR, and less than or equal to LAR_ADDR. Readable from any Privileged context, if and only if this region's S bit is clear, and MPU_CTRL_NS_HIDE_ADDR is clear. Otherwise readable only from a Secure, Privileged context."] - #[inline(always)] - pub const fn addr(&self) -> u32 { - let val = (self.0 >> 5usize) & 0x07ff_ffff; - val as u32 - } - #[doc = "This MPU region matches addresses where addr\\[31:5\\] (the 27 most significant bits) are greater than or equal to BAR_ADDR, and less than or equal to LAR_ADDR. Readable from any Privileged context, if and only if this region's S bit is clear, and MPU_CTRL_NS_HIDE_ADDR is clear. Otherwise readable only from a Secure, Privileged context."] - #[inline(always)] - pub fn set_addr(&mut self, val: u32) { - self.0 = (self.0 & !(0x07ff_ffff << 5usize)) | (((val as u32) & 0x07ff_ffff) << 5usize); - } -} -impl Default for MpuBar4 { - #[inline(always)] - fn default() -> MpuBar4 { - MpuBar4(0) - } -} -#[doc = "Base address register for MPU region 5. Writable only from a Secure, Privileged context."] -#[repr(transparent)] -#[derive(Copy, Clone, Eq, PartialEq)] -pub struct MpuBar5(pub u32); -impl MpuBar5 { - #[doc = "This MPU region matches addresses where addr\\[31:5\\] (the 27 most significant bits) are greater than or equal to BAR_ADDR, and less than or equal to LAR_ADDR. Readable from any Privileged context, if and only if this region's S bit is clear, and MPU_CTRL_NS_HIDE_ADDR is clear. Otherwise readable only from a Secure, Privileged context."] - #[inline(always)] - pub const fn addr(&self) -> u32 { - let val = (self.0 >> 5usize) & 0x07ff_ffff; - val as u32 - } - #[doc = "This MPU region matches addresses where addr\\[31:5\\] (the 27 most significant bits) are greater than or equal to BAR_ADDR, and less than or equal to LAR_ADDR. Readable from any Privileged context, if and only if this region's S bit is clear, and MPU_CTRL_NS_HIDE_ADDR is clear. Otherwise readable only from a Secure, Privileged context."] - #[inline(always)] - pub fn set_addr(&mut self, val: u32) { - self.0 = (self.0 & !(0x07ff_ffff << 5usize)) | (((val as u32) & 0x07ff_ffff) << 5usize); - } -} -impl Default for MpuBar5 { - #[inline(always)] - fn default() -> MpuBar5 { - MpuBar5(0) - } -} -#[doc = "Base address register for MPU region 6. Writable only from a Secure, Privileged context."] -#[repr(transparent)] -#[derive(Copy, Clone, Eq, PartialEq)] -pub struct MpuBar6(pub u32); -impl MpuBar6 { - #[doc = "This MPU region matches addresses where addr\\[31:5\\] (the 27 most significant bits) are greater than or equal to BAR_ADDR, and less than or equal to LAR_ADDR. Readable from any Privileged context, if and only if this region's S bit is clear, and MPU_CTRL_NS_HIDE_ADDR is clear. Otherwise readable only from a Secure, Privileged context."] - #[inline(always)] - pub const fn addr(&self) -> u32 { - let val = (self.0 >> 5usize) & 0x07ff_ffff; - val as u32 - } - #[doc = "This MPU region matches addresses where addr\\[31:5\\] (the 27 most significant bits) are greater than or equal to BAR_ADDR, and less than or equal to LAR_ADDR. Readable from any Privileged context, if and only if this region's S bit is clear, and MPU_CTRL_NS_HIDE_ADDR is clear. Otherwise readable only from a Secure, Privileged context."] - #[inline(always)] - pub fn set_addr(&mut self, val: u32) { - self.0 = (self.0 & !(0x07ff_ffff << 5usize)) | (((val as u32) & 0x07ff_ffff) << 5usize); - } -} -impl Default for MpuBar6 { - #[inline(always)] - fn default() -> MpuBar6 { - MpuBar6(0) - } -} -#[doc = "Base address register for MPU region 7. Writable only from a Secure, Privileged context."] -#[repr(transparent)] -#[derive(Copy, Clone, Eq, PartialEq)] -pub struct MpuBar7(pub u32); -impl MpuBar7 { - #[doc = "This MPU region matches addresses where addr\\[31:5\\] (the 27 most significant bits) are greater than or equal to BAR_ADDR, and less than or equal to LAR_ADDR. Readable from any Privileged context, if and only if this region's S bit is clear, and MPU_CTRL_NS_HIDE_ADDR is clear. Otherwise readable only from a Secure, Privileged context."] - #[inline(always)] - pub const fn addr(&self) -> u32 { - let val = (self.0 >> 5usize) & 0x07ff_ffff; - val as u32 - } - #[doc = "This MPU region matches addresses where addr\\[31:5\\] (the 27 most significant bits) are greater than or equal to BAR_ADDR, and less than or equal to LAR_ADDR. Readable from any Privileged context, if and only if this region's S bit is clear, and MPU_CTRL_NS_HIDE_ADDR is clear. Otherwise readable only from a Secure, Privileged context."] - #[inline(always)] - pub fn set_addr(&mut self, val: u32) { - self.0 = (self.0 & !(0x07ff_ffff << 5usize)) | (((val as u32) & 0x07ff_ffff) << 5usize); - } -} -impl Default for MpuBar7 { - #[inline(always)] - fn default() -> MpuBar7 { - MpuBar7(0) - } -} -#[doc = "Control register for DMA MPU. Accessible only from a Privileged context."] -#[repr(transparent)] -#[derive(Copy, Clone, Eq, PartialEq)] -pub struct MpuCtrl(pub u32); -impl MpuCtrl { - #[doc = "Determine whether an address not covered by an active MPU region is Privileged (1) or Unprivileged (0)"] - #[inline(always)] - pub const fn p(&self) -> bool { - let val = (self.0 >> 1usize) & 0x01; - val != 0 - } - #[doc = "Determine whether an address not covered by an active MPU region is Privileged (1) or Unprivileged (0)"] - #[inline(always)] - pub fn set_p(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize); - } - #[doc = "Determine whether an address not covered by an active MPU region is Secure (1) or Non-secure (0)"] - #[inline(always)] - pub const fn s(&self) -> bool { - let val = (self.0 >> 2usize) & 0x01; - val != 0 - } - #[doc = "Determine whether an address not covered by an active MPU region is Secure (1) or Non-secure (0)"] - #[inline(always)] - pub fn set_s(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 2usize)) | (((val as u32) & 0x01) << 2usize); - } - #[doc = "By default, when a region's S bit is clear, Non-secure-Privileged reads can see the region's base address and limit address. Set this bit to make the addresses appear as 0 to Non-secure reads, even when the region is Non-secure, to avoid leaking information about the processor SAU map."] - #[inline(always)] - pub const fn ns_hide_addr(&self) -> bool { - let val = (self.0 >> 3usize) & 0x01; - val != 0 - } - #[doc = "By default, when a region's S bit is clear, Non-secure-Privileged reads can see the region's base address and limit address. Set this bit to make the addresses appear as 0 to Non-secure reads, even when the region is Non-secure, to avoid leaking information about the processor SAU map."] - #[inline(always)] - pub fn set_ns_hide_addr(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 3usize)) | (((val as u32) & 0x01) << 3usize); - } -} -impl Default for MpuCtrl { - #[inline(always)] - fn default() -> MpuCtrl { - MpuCtrl(0) - } -} -#[doc = "Limit address register for MPU region 0. Writable only from a Secure, Privileged context, with the exception of the P bit."] -#[repr(transparent)] -#[derive(Copy, Clone, Eq, PartialEq)] -pub struct MpuLar0(pub u32); -impl MpuLar0 { - #[doc = "Region enable. If 1, any address within range specified by the base address (BAR_ADDR) and limit address (LAR_ADDR) has the attributes specified by S and P."] - #[inline(always)] - pub const fn en(&self) -> bool { - let val = (self.0 >> 0usize) & 0x01; - val != 0 - } - #[doc = "Region enable. If 1, any address within range specified by the base address (BAR_ADDR) and limit address (LAR_ADDR) has the attributes specified by S and P."] - #[inline(always)] - pub fn set_en(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize); - } - #[doc = "Determines the Privileged/Unprivileged (=1/0) status of addresses matching this region, if this region is enabled. Writable from any Privileged context, if and only if the S bit is clear. Otherwise, writable only from a Secure, Privileged context."] - #[inline(always)] - pub const fn p(&self) -> bool { - let val = (self.0 >> 1usize) & 0x01; - val != 0 - } - #[doc = "Determines the Privileged/Unprivileged (=1/0) status of addresses matching this region, if this region is enabled. Writable from any Privileged context, if and only if the S bit is clear. Otherwise, writable only from a Secure, Privileged context."] - #[inline(always)] - pub fn set_p(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize); - } - #[doc = "Determines the Secure/Non-secure (=1/0) status of addresses matching this region, if this region is enabled."] - #[inline(always)] - pub const fn s(&self) -> bool { - let val = (self.0 >> 2usize) & 0x01; - val != 0 - } - #[doc = "Determines the Secure/Non-secure (=1/0) status of addresses matching this region, if this region is enabled."] - #[inline(always)] - pub fn set_s(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 2usize)) | (((val as u32) & 0x01) << 2usize); - } - #[doc = "Limit address bits 31:5. Readable from any Privileged context, if and only if this region's S bit is clear, and MPU_CTRL_NS_HIDE_ADDR is clear. Otherwise readable only from a Secure, Privileged context."] - #[inline(always)] - pub const fn addr(&self) -> u32 { - let val = (self.0 >> 5usize) & 0x07ff_ffff; - val as u32 - } - #[doc = "Limit address bits 31:5. Readable from any Privileged context, if and only if this region's S bit is clear, and MPU_CTRL_NS_HIDE_ADDR is clear. Otherwise readable only from a Secure, Privileged context."] - #[inline(always)] - pub fn set_addr(&mut self, val: u32) { - self.0 = (self.0 & !(0x07ff_ffff << 5usize)) | (((val as u32) & 0x07ff_ffff) << 5usize); - } -} -impl Default for MpuLar0 { - #[inline(always)] - fn default() -> MpuLar0 { - MpuLar0(0) - } -} -#[doc = "Limit address register for MPU region 1. Writable only from a Secure, Privileged context, with the exception of the P bit."] -#[repr(transparent)] -#[derive(Copy, Clone, Eq, PartialEq)] -pub struct MpuLar1(pub u32); -impl MpuLar1 { - #[doc = "Region enable. If 1, any address within range specified by the base address (BAR_ADDR) and limit address (LAR_ADDR) has the attributes specified by S and P."] - #[inline(always)] - pub const fn en(&self) -> bool { - let val = (self.0 >> 0usize) & 0x01; - val != 0 - } - #[doc = "Region enable. If 1, any address within range specified by the base address (BAR_ADDR) and limit address (LAR_ADDR) has the attributes specified by S and P."] - #[inline(always)] - pub fn set_en(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize); - } - #[doc = "Determines the Privileged/Unprivileged (=1/0) status of addresses matching this region, if this region is enabled. Writable from any Privileged context, if and only if the S bit is clear. Otherwise, writable only from a Secure, Privileged context."] - #[inline(always)] - pub const fn p(&self) -> bool { - let val = (self.0 >> 1usize) & 0x01; - val != 0 - } - #[doc = "Determines the Privileged/Unprivileged (=1/0) status of addresses matching this region, if this region is enabled. Writable from any Privileged context, if and only if the S bit is clear. Otherwise, writable only from a Secure, Privileged context."] - #[inline(always)] - pub fn set_p(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize); - } - #[doc = "Determines the Secure/Non-secure (=1/0) status of addresses matching this region, if this region is enabled."] - #[inline(always)] - pub const fn s(&self) -> bool { - let val = (self.0 >> 2usize) & 0x01; - val != 0 - } - #[doc = "Determines the Secure/Non-secure (=1/0) status of addresses matching this region, if this region is enabled."] - #[inline(always)] - pub fn set_s(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 2usize)) | (((val as u32) & 0x01) << 2usize); - } - #[doc = "Limit address bits 31:5. Readable from any Privileged context, if and only if this region's S bit is clear, and MPU_CTRL_NS_HIDE_ADDR is clear. Otherwise readable only from a Secure, Privileged context."] - #[inline(always)] - pub const fn addr(&self) -> u32 { - let val = (self.0 >> 5usize) & 0x07ff_ffff; - val as u32 - } - #[doc = "Limit address bits 31:5. Readable from any Privileged context, if and only if this region's S bit is clear, and MPU_CTRL_NS_HIDE_ADDR is clear. Otherwise readable only from a Secure, Privileged context."] - #[inline(always)] - pub fn set_addr(&mut self, val: u32) { - self.0 = (self.0 & !(0x07ff_ffff << 5usize)) | (((val as u32) & 0x07ff_ffff) << 5usize); - } -} -impl Default for MpuLar1 { - #[inline(always)] - fn default() -> MpuLar1 { - MpuLar1(0) - } -} -#[doc = "Limit address register for MPU region 2. Writable only from a Secure, Privileged context, with the exception of the P bit."] -#[repr(transparent)] -#[derive(Copy, Clone, Eq, PartialEq)] -pub struct MpuLar2(pub u32); -impl MpuLar2 { - #[doc = "Region enable. If 1, any address within range specified by the base address (BAR_ADDR) and limit address (LAR_ADDR) has the attributes specified by S and P."] - #[inline(always)] - pub const fn en(&self) -> bool { - let val = (self.0 >> 0usize) & 0x01; - val != 0 - } - #[doc = "Region enable. If 1, any address within range specified by the base address (BAR_ADDR) and limit address (LAR_ADDR) has the attributes specified by S and P."] - #[inline(always)] - pub fn set_en(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize); - } - #[doc = "Determines the Privileged/Unprivileged (=1/0) status of addresses matching this region, if this region is enabled. Writable from any Privileged context, if and only if the S bit is clear. Otherwise, writable only from a Secure, Privileged context."] - #[inline(always)] - pub const fn p(&self) -> bool { - let val = (self.0 >> 1usize) & 0x01; - val != 0 - } - #[doc = "Determines the Privileged/Unprivileged (=1/0) status of addresses matching this region, if this region is enabled. Writable from any Privileged context, if and only if the S bit is clear. Otherwise, writable only from a Secure, Privileged context."] - #[inline(always)] - pub fn set_p(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize); - } - #[doc = "Determines the Secure/Non-secure (=1/0) status of addresses matching this region, if this region is enabled."] - #[inline(always)] - pub const fn s(&self) -> bool { - let val = (self.0 >> 2usize) & 0x01; - val != 0 - } - #[doc = "Determines the Secure/Non-secure (=1/0) status of addresses matching this region, if this region is enabled."] - #[inline(always)] - pub fn set_s(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 2usize)) | (((val as u32) & 0x01) << 2usize); - } - #[doc = "Limit address bits 31:5. Readable from any Privileged context, if and only if this region's S bit is clear, and MPU_CTRL_NS_HIDE_ADDR is clear. Otherwise readable only from a Secure, Privileged context."] - #[inline(always)] - pub const fn addr(&self) -> u32 { - let val = (self.0 >> 5usize) & 0x07ff_ffff; - val as u32 - } - #[doc = "Limit address bits 31:5. Readable from any Privileged context, if and only if this region's S bit is clear, and MPU_CTRL_NS_HIDE_ADDR is clear. Otherwise readable only from a Secure, Privileged context."] - #[inline(always)] - pub fn set_addr(&mut self, val: u32) { - self.0 = (self.0 & !(0x07ff_ffff << 5usize)) | (((val as u32) & 0x07ff_ffff) << 5usize); - } -} -impl Default for MpuLar2 { - #[inline(always)] - fn default() -> MpuLar2 { - MpuLar2(0) - } -} -#[doc = "Limit address register for MPU region 3. Writable only from a Secure, Privileged context, with the exception of the P bit."] -#[repr(transparent)] -#[derive(Copy, Clone, Eq, PartialEq)] -pub struct MpuLar3(pub u32); -impl MpuLar3 { - #[doc = "Region enable. If 1, any address within range specified by the base address (BAR_ADDR) and limit address (LAR_ADDR) has the attributes specified by S and P."] - #[inline(always)] - pub const fn en(&self) -> bool { - let val = (self.0 >> 0usize) & 0x01; - val != 0 - } - #[doc = "Region enable. If 1, any address within range specified by the base address (BAR_ADDR) and limit address (LAR_ADDR) has the attributes specified by S and P."] - #[inline(always)] - pub fn set_en(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize); - } - #[doc = "Determines the Privileged/Unprivileged (=1/0) status of addresses matching this region, if this region is enabled. Writable from any Privileged context, if and only if the S bit is clear. Otherwise, writable only from a Secure, Privileged context."] - #[inline(always)] - pub const fn p(&self) -> bool { - let val = (self.0 >> 1usize) & 0x01; - val != 0 - } - #[doc = "Determines the Privileged/Unprivileged (=1/0) status of addresses matching this region, if this region is enabled. Writable from any Privileged context, if and only if the S bit is clear. Otherwise, writable only from a Secure, Privileged context."] - #[inline(always)] - pub fn set_p(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize); - } - #[doc = "Determines the Secure/Non-secure (=1/0) status of addresses matching this region, if this region is enabled."] - #[inline(always)] - pub const fn s(&self) -> bool { - let val = (self.0 >> 2usize) & 0x01; - val != 0 - } - #[doc = "Determines the Secure/Non-secure (=1/0) status of addresses matching this region, if this region is enabled."] - #[inline(always)] - pub fn set_s(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 2usize)) | (((val as u32) & 0x01) << 2usize); - } - #[doc = "Limit address bits 31:5. Readable from any Privileged context, if and only if this region's S bit is clear, and MPU_CTRL_NS_HIDE_ADDR is clear. Otherwise readable only from a Secure, Privileged context."] - #[inline(always)] - pub const fn addr(&self) -> u32 { - let val = (self.0 >> 5usize) & 0x07ff_ffff; - val as u32 - } - #[doc = "Limit address bits 31:5. Readable from any Privileged context, if and only if this region's S bit is clear, and MPU_CTRL_NS_HIDE_ADDR is clear. Otherwise readable only from a Secure, Privileged context."] - #[inline(always)] - pub fn set_addr(&mut self, val: u32) { - self.0 = (self.0 & !(0x07ff_ffff << 5usize)) | (((val as u32) & 0x07ff_ffff) << 5usize); - } -} -impl Default for MpuLar3 { - #[inline(always)] - fn default() -> MpuLar3 { - MpuLar3(0) - } -} -#[doc = "Limit address register for MPU region 4. Writable only from a Secure, Privileged context, with the exception of the P bit."] -#[repr(transparent)] -#[derive(Copy, Clone, Eq, PartialEq)] -pub struct MpuLar4(pub u32); -impl MpuLar4 { - #[doc = "Region enable. If 1, any address within range specified by the base address (BAR_ADDR) and limit address (LAR_ADDR) has the attributes specified by S and P."] - #[inline(always)] - pub const fn en(&self) -> bool { - let val = (self.0 >> 0usize) & 0x01; - val != 0 - } - #[doc = "Region enable. If 1, any address within range specified by the base address (BAR_ADDR) and limit address (LAR_ADDR) has the attributes specified by S and P."] - #[inline(always)] - pub fn set_en(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize); - } - #[doc = "Determines the Privileged/Unprivileged (=1/0) status of addresses matching this region, if this region is enabled. Writable from any Privileged context, if and only if the S bit is clear. Otherwise, writable only from a Secure, Privileged context."] - #[inline(always)] - pub const fn p(&self) -> bool { - let val = (self.0 >> 1usize) & 0x01; - val != 0 - } - #[doc = "Determines the Privileged/Unprivileged (=1/0) status of addresses matching this region, if this region is enabled. Writable from any Privileged context, if and only if the S bit is clear. Otherwise, writable only from a Secure, Privileged context."] - #[inline(always)] - pub fn set_p(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize); - } - #[doc = "Determines the Secure/Non-secure (=1/0) status of addresses matching this region, if this region is enabled."] - #[inline(always)] - pub const fn s(&self) -> bool { - let val = (self.0 >> 2usize) & 0x01; - val != 0 - } - #[doc = "Determines the Secure/Non-secure (=1/0) status of addresses matching this region, if this region is enabled."] - #[inline(always)] - pub fn set_s(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 2usize)) | (((val as u32) & 0x01) << 2usize); - } - #[doc = "Limit address bits 31:5. Readable from any Privileged context, if and only if this region's S bit is clear, and MPU_CTRL_NS_HIDE_ADDR is clear. Otherwise readable only from a Secure, Privileged context."] - #[inline(always)] - pub const fn addr(&self) -> u32 { - let val = (self.0 >> 5usize) & 0x07ff_ffff; - val as u32 - } - #[doc = "Limit address bits 31:5. Readable from any Privileged context, if and only if this region's S bit is clear, and MPU_CTRL_NS_HIDE_ADDR is clear. Otherwise readable only from a Secure, Privileged context."] - #[inline(always)] - pub fn set_addr(&mut self, val: u32) { - self.0 = (self.0 & !(0x07ff_ffff << 5usize)) | (((val as u32) & 0x07ff_ffff) << 5usize); - } -} -impl Default for MpuLar4 { - #[inline(always)] - fn default() -> MpuLar4 { - MpuLar4(0) - } -} -#[doc = "Limit address register for MPU region 5. Writable only from a Secure, Privileged context, with the exception of the P bit."] -#[repr(transparent)] -#[derive(Copy, Clone, Eq, PartialEq)] -pub struct MpuLar5(pub u32); -impl MpuLar5 { - #[doc = "Region enable. If 1, any address within range specified by the base address (BAR_ADDR) and limit address (LAR_ADDR) has the attributes specified by S and P."] - #[inline(always)] - pub const fn en(&self) -> bool { - let val = (self.0 >> 0usize) & 0x01; - val != 0 - } - #[doc = "Region enable. If 1, any address within range specified by the base address (BAR_ADDR) and limit address (LAR_ADDR) has the attributes specified by S and P."] - #[inline(always)] - pub fn set_en(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize); - } - #[doc = "Determines the Privileged/Unprivileged (=1/0) status of addresses matching this region, if this region is enabled. Writable from any Privileged context, if and only if the S bit is clear. Otherwise, writable only from a Secure, Privileged context."] - #[inline(always)] - pub const fn p(&self) -> bool { - let val = (self.0 >> 1usize) & 0x01; - val != 0 - } - #[doc = "Determines the Privileged/Unprivileged (=1/0) status of addresses matching this region, if this region is enabled. Writable from any Privileged context, if and only if the S bit is clear. Otherwise, writable only from a Secure, Privileged context."] - #[inline(always)] - pub fn set_p(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize); - } - #[doc = "Determines the Secure/Non-secure (=1/0) status of addresses matching this region, if this region is enabled."] - #[inline(always)] - pub const fn s(&self) -> bool { - let val = (self.0 >> 2usize) & 0x01; - val != 0 - } - #[doc = "Determines the Secure/Non-secure (=1/0) status of addresses matching this region, if this region is enabled."] - #[inline(always)] - pub fn set_s(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 2usize)) | (((val as u32) & 0x01) << 2usize); - } - #[doc = "Limit address bits 31:5. Readable from any Privileged context, if and only if this region's S bit is clear, and MPU_CTRL_NS_HIDE_ADDR is clear. Otherwise readable only from a Secure, Privileged context."] - #[inline(always)] - pub const fn addr(&self) -> u32 { - let val = (self.0 >> 5usize) & 0x07ff_ffff; - val as u32 - } - #[doc = "Limit address bits 31:5. Readable from any Privileged context, if and only if this region's S bit is clear, and MPU_CTRL_NS_HIDE_ADDR is clear. Otherwise readable only from a Secure, Privileged context."] - #[inline(always)] - pub fn set_addr(&mut self, val: u32) { - self.0 = (self.0 & !(0x07ff_ffff << 5usize)) | (((val as u32) & 0x07ff_ffff) << 5usize); - } -} -impl Default for MpuLar5 { - #[inline(always)] - fn default() -> MpuLar5 { - MpuLar5(0) - } -} -#[doc = "Limit address register for MPU region 6. Writable only from a Secure, Privileged context, with the exception of the P bit."] -#[repr(transparent)] -#[derive(Copy, Clone, Eq, PartialEq)] -pub struct MpuLar6(pub u32); -impl MpuLar6 { - #[doc = "Region enable. If 1, any address within range specified by the base address (BAR_ADDR) and limit address (LAR_ADDR) has the attributes specified by S and P."] - #[inline(always)] - pub const fn en(&self) -> bool { - let val = (self.0 >> 0usize) & 0x01; - val != 0 - } - #[doc = "Region enable. If 1, any address within range specified by the base address (BAR_ADDR) and limit address (LAR_ADDR) has the attributes specified by S and P."] - #[inline(always)] - pub fn set_en(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize); - } - #[doc = "Determines the Privileged/Unprivileged (=1/0) status of addresses matching this region, if this region is enabled. Writable from any Privileged context, if and only if the S bit is clear. Otherwise, writable only from a Secure, Privileged context."] - #[inline(always)] - pub const fn p(&self) -> bool { - let val = (self.0 >> 1usize) & 0x01; - val != 0 - } - #[doc = "Determines the Privileged/Unprivileged (=1/0) status of addresses matching this region, if this region is enabled. Writable from any Privileged context, if and only if the S bit is clear. Otherwise, writable only from a Secure, Privileged context."] - #[inline(always)] - pub fn set_p(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize); - } - #[doc = "Determines the Secure/Non-secure (=1/0) status of addresses matching this region, if this region is enabled."] - #[inline(always)] - pub const fn s(&self) -> bool { - let val = (self.0 >> 2usize) & 0x01; - val != 0 - } - #[doc = "Determines the Secure/Non-secure (=1/0) status of addresses matching this region, if this region is enabled."] - #[inline(always)] - pub fn set_s(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 2usize)) | (((val as u32) & 0x01) << 2usize); - } - #[doc = "Limit address bits 31:5. Readable from any Privileged context, if and only if this region's S bit is clear, and MPU_CTRL_NS_HIDE_ADDR is clear. Otherwise readable only from a Secure, Privileged context."] - #[inline(always)] - pub const fn addr(&self) -> u32 { - let val = (self.0 >> 5usize) & 0x07ff_ffff; - val as u32 - } - #[doc = "Limit address bits 31:5. Readable from any Privileged context, if and only if this region's S bit is clear, and MPU_CTRL_NS_HIDE_ADDR is clear. Otherwise readable only from a Secure, Privileged context."] - #[inline(always)] - pub fn set_addr(&mut self, val: u32) { - self.0 = (self.0 & !(0x07ff_ffff << 5usize)) | (((val as u32) & 0x07ff_ffff) << 5usize); - } -} -impl Default for MpuLar6 { - #[inline(always)] - fn default() -> MpuLar6 { - MpuLar6(0) - } -} -#[doc = "Limit address register for MPU region 7. Writable only from a Secure, Privileged context, with the exception of the P bit."] -#[repr(transparent)] -#[derive(Copy, Clone, Eq, PartialEq)] -pub struct MpuLar7(pub u32); -impl MpuLar7 { - #[doc = "Region enable. If 1, any address within range specified by the base address (BAR_ADDR) and limit address (LAR_ADDR) has the attributes specified by S and P."] - #[inline(always)] - pub const fn en(&self) -> bool { - let val = (self.0 >> 0usize) & 0x01; - val != 0 - } - #[doc = "Region enable. If 1, any address within range specified by the base address (BAR_ADDR) and limit address (LAR_ADDR) has the attributes specified by S and P."] - #[inline(always)] - pub fn set_en(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize); - } - #[doc = "Determines the Privileged/Unprivileged (=1/0) status of addresses matching this region, if this region is enabled. Writable from any Privileged context, if and only if the S bit is clear. Otherwise, writable only from a Secure, Privileged context."] - #[inline(always)] - pub const fn p(&self) -> bool { - let val = (self.0 >> 1usize) & 0x01; - val != 0 - } - #[doc = "Determines the Privileged/Unprivileged (=1/0) status of addresses matching this region, if this region is enabled. Writable from any Privileged context, if and only if the S bit is clear. Otherwise, writable only from a Secure, Privileged context."] - #[inline(always)] - pub fn set_p(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize); - } - #[doc = "Determines the Secure/Non-secure (=1/0) status of addresses matching this region, if this region is enabled."] - #[inline(always)] - pub const fn s(&self) -> bool { - let val = (self.0 >> 2usize) & 0x01; - val != 0 - } - #[doc = "Determines the Secure/Non-secure (=1/0) status of addresses matching this region, if this region is enabled."] - #[inline(always)] - pub fn set_s(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 2usize)) | (((val as u32) & 0x01) << 2usize); - } - #[doc = "Limit address bits 31:5. Readable from any Privileged context, if and only if this region's S bit is clear, and MPU_CTRL_NS_HIDE_ADDR is clear. Otherwise readable only from a Secure, Privileged context."] - #[inline(always)] - pub const fn addr(&self) -> u32 { - let val = (self.0 >> 5usize) & 0x07ff_ffff; - val as u32 - } - #[doc = "Limit address bits 31:5. Readable from any Privileged context, if and only if this region's S bit is clear, and MPU_CTRL_NS_HIDE_ADDR is clear. Otherwise readable only from a Secure, Privileged context."] - #[inline(always)] - pub fn set_addr(&mut self, val: u32) { - self.0 = (self.0 & !(0x07ff_ffff << 5usize)) | (((val as u32) & 0x07ff_ffff) << 5usize); - } -} -impl Default for MpuLar7 { - #[inline(always)] - fn default() -> MpuLar7 { - MpuLar7(0) - } -} -#[doc = "Trigger one or more channels simultaneously"] -#[repr(transparent)] -#[derive(Copy, Clone, Eq, PartialEq)] -pub struct MultiChanTrigger(pub u32); -impl MultiChanTrigger { - #[doc = "Each bit in this register corresponds to a DMA channel. Writing a 1 to the relevant bit is the same as writing to that channel's trigger register; the channel will start if it is currently enabled and not already busy."] - #[inline(always)] - pub const fn multi_chan_trigger(&self) -> u16 { - let val = (self.0 >> 0usize) & 0xffff; - val as u16 - } - #[doc = "Each bit in this register corresponds to a DMA channel. Writing a 1 to the relevant bit is the same as writing to that channel's trigger register; the channel will start if it is currently enabled and not already busy."] - #[inline(always)] - pub fn set_multi_chan_trigger(&mut self, val: u16) { - self.0 = (self.0 & !(0xffff << 0usize)) | (((val as u32) & 0xffff) << 0usize); - } -} -impl Default for MultiChanTrigger { - #[inline(always)] - fn default() -> MultiChanTrigger { - MultiChanTrigger(0) - } -} -#[doc = "The number of channels this DMA instance is equipped with. This DMA supports up to 16 hardware channels, but can be configured with as few as one, to minimise silicon area."] -#[repr(transparent)] -#[derive(Copy, Clone, Eq, PartialEq)] -pub struct Nchannels(pub u32); -impl Nchannels { - #[inline(always)] - pub const fn n_channels(&self) -> u8 { - let val = (self.0 >> 0usize) & 0x1f; - val as u8 - } - #[inline(always)] - pub fn set_n_channels(&mut self, val: u8) { - self.0 = (self.0 & !(0x1f << 0usize)) | (((val as u32) & 0x1f) << 0usize); - } -} -impl Default for Nchannels { - #[inline(always)] - fn default() -> Nchannels { - Nchannels(0) - } -} -#[doc = "Security configuration for channel 0. Control whether this channel performs Secure/Non-secure and Privileged/Unprivileged bus accesses. If this channel generates bus accesses of some security level, an access of at least that level (in the order S+P > S+U > NS+P > NS+U) is required to program, trigger, abort, check the status of, interrupt on or acknowledge the interrupt of this channel. This register automatically locks down (becomes read-only) once software starts to configure the channel. This register is world-readable, but is writable only from a Secure, Privileged context."] -#[repr(transparent)] -#[derive(Copy, Clone, Eq, PartialEq)] -pub struct SeccfgCh0(pub u32); -impl SeccfgCh0 { - #[doc = "Privileged channel. If 1, this channel performs Privileged bus accesses. If 0, it performs Unprivileged bus accesses. If 1, this channel is controllable only from a Privileged context of the same Secure/Non-secure level, or any context of a higher Secure/Non-secure level."] - #[inline(always)] - pub const fn p(&self) -> bool { - let val = (self.0 >> 0usize) & 0x01; - val != 0 - } - #[doc = "Privileged channel. If 1, this channel performs Privileged bus accesses. If 0, it performs Unprivileged bus accesses. If 1, this channel is controllable only from a Privileged context of the same Secure/Non-secure level, or any context of a higher Secure/Non-secure level."] - #[inline(always)] - pub fn set_p(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize); - } - #[doc = "Secure channel. If 1, this channel performs Secure bus accesses. If 0, it performs Non-secure bus accesses. If 1, this channel is controllable only from a Secure context."] - #[inline(always)] - pub const fn s(&self) -> bool { - let val = (self.0 >> 1usize) & 0x01; - val != 0 - } - #[doc = "Secure channel. If 1, this channel performs Secure bus accesses. If 0, it performs Non-secure bus accesses. If 1, this channel is controllable only from a Secure context."] - #[inline(always)] - pub fn set_s(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize); - } - #[doc = "LOCK is 0 at reset, and is set to 1 automatically upon a successful write to this channel's control registers. That is, a write to CTRL, READ_ADDR, WRITE_ADDR, TRANS_COUNT and their aliases. Once its LOCK bit is set, this register becomes read-only. A failed write, for example due to the write's privilege being lower than that specified in the channel's SECCFG register, will not set the LOCK bit."] - #[inline(always)] - pub const fn lock(&self) -> bool { - let val = (self.0 >> 2usize) & 0x01; - val != 0 - } - #[doc = "LOCK is 0 at reset, and is set to 1 automatically upon a successful write to this channel's control registers. That is, a write to CTRL, READ_ADDR, WRITE_ADDR, TRANS_COUNT and their aliases. Once its LOCK bit is set, this register becomes read-only. A failed write, for example due to the write's privilege being lower than that specified in the channel's SECCFG register, will not set the LOCK bit."] - #[inline(always)] - pub fn set_lock(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 2usize)) | (((val as u32) & 0x01) << 2usize); - } -} -impl Default for SeccfgCh0 { - #[inline(always)] - fn default() -> SeccfgCh0 { - SeccfgCh0(0) - } -} -#[doc = "Security configuration for channel 1. Control whether this channel performs Secure/Non-secure and Privileged/Unprivileged bus accesses. If this channel generates bus accesses of some security level, an access of at least that level (in the order S+P > S+U > NS+P > NS+U) is required to program, trigger, abort, check the status of, interrupt on or acknowledge the interrupt of this channel. This register automatically locks down (becomes read-only) once software starts to configure the channel. This register is world-readable, but is writable only from a Secure, Privileged context."] -#[repr(transparent)] -#[derive(Copy, Clone, Eq, PartialEq)] -pub struct SeccfgCh1(pub u32); -impl SeccfgCh1 { - #[doc = "Privileged channel. If 1, this channel performs Privileged bus accesses. If 0, it performs Unprivileged bus accesses. If 1, this channel is controllable only from a Privileged context of the same Secure/Non-secure level, or any context of a higher Secure/Non-secure level."] - #[inline(always)] - pub const fn p(&self) -> bool { - let val = (self.0 >> 0usize) & 0x01; - val != 0 - } - #[doc = "Privileged channel. If 1, this channel performs Privileged bus accesses. If 0, it performs Unprivileged bus accesses. If 1, this channel is controllable only from a Privileged context of the same Secure/Non-secure level, or any context of a higher Secure/Non-secure level."] - #[inline(always)] - pub fn set_p(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize); - } - #[doc = "Secure channel. If 1, this channel performs Secure bus accesses. If 0, it performs Non-secure bus accesses. If 1, this channel is controllable only from a Secure context."] - #[inline(always)] - pub const fn s(&self) -> bool { - let val = (self.0 >> 1usize) & 0x01; - val != 0 - } - #[doc = "Secure channel. If 1, this channel performs Secure bus accesses. If 0, it performs Non-secure bus accesses. If 1, this channel is controllable only from a Secure context."] - #[inline(always)] - pub fn set_s(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize); - } - #[doc = "LOCK is 0 at reset, and is set to 1 automatically upon a successful write to this channel's control registers. That is, a write to CTRL, READ_ADDR, WRITE_ADDR, TRANS_COUNT and their aliases. Once its LOCK bit is set, this register becomes read-only. A failed write, for example due to the write's privilege being lower than that specified in the channel's SECCFG register, will not set the LOCK bit."] - #[inline(always)] - pub const fn lock(&self) -> bool { - let val = (self.0 >> 2usize) & 0x01; - val != 0 - } - #[doc = "LOCK is 0 at reset, and is set to 1 automatically upon a successful write to this channel's control registers. That is, a write to CTRL, READ_ADDR, WRITE_ADDR, TRANS_COUNT and their aliases. Once its LOCK bit is set, this register becomes read-only. A failed write, for example due to the write's privilege being lower than that specified in the channel's SECCFG register, will not set the LOCK bit."] - #[inline(always)] - pub fn set_lock(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 2usize)) | (((val as u32) & 0x01) << 2usize); - } -} -impl Default for SeccfgCh1 { - #[inline(always)] - fn default() -> SeccfgCh1 { - SeccfgCh1(0) - } -} -#[doc = "Security configuration for channel 10. Control whether this channel performs Secure/Non-secure and Privileged/Unprivileged bus accesses. If this channel generates bus accesses of some security level, an access of at least that level (in the order S+P > S+U > NS+P > NS+U) is required to program, trigger, abort, check the status of, interrupt on or acknowledge the interrupt of this channel. This register automatically locks down (becomes read-only) once software starts to configure the channel. This register is world-readable, but is writable only from a Secure, Privileged context."] -#[repr(transparent)] -#[derive(Copy, Clone, Eq, PartialEq)] -pub struct SeccfgCh10(pub u32); -impl SeccfgCh10 { - #[doc = "Privileged channel. If 1, this channel performs Privileged bus accesses. If 0, it performs Unprivileged bus accesses. If 1, this channel is controllable only from a Privileged context of the same Secure/Non-secure level, or any context of a higher Secure/Non-secure level."] - #[inline(always)] - pub const fn p(&self) -> bool { - let val = (self.0 >> 0usize) & 0x01; - val != 0 - } - #[doc = "Privileged channel. If 1, this channel performs Privileged bus accesses. If 0, it performs Unprivileged bus accesses. If 1, this channel is controllable only from a Privileged context of the same Secure/Non-secure level, or any context of a higher Secure/Non-secure level."] - #[inline(always)] - pub fn set_p(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize); - } - #[doc = "Secure channel. If 1, this channel performs Secure bus accesses. If 0, it performs Non-secure bus accesses. If 1, this channel is controllable only from a Secure context."] - #[inline(always)] - pub const fn s(&self) -> bool { - let val = (self.0 >> 1usize) & 0x01; - val != 0 - } - #[doc = "Secure channel. If 1, this channel performs Secure bus accesses. If 0, it performs Non-secure bus accesses. If 1, this channel is controllable only from a Secure context."] - #[inline(always)] - pub fn set_s(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize); - } - #[doc = "LOCK is 0 at reset, and is set to 1 automatically upon a successful write to this channel's control registers. That is, a write to CTRL, READ_ADDR, WRITE_ADDR, TRANS_COUNT and their aliases. Once its LOCK bit is set, this register becomes read-only. A failed write, for example due to the write's privilege being lower than that specified in the channel's SECCFG register, will not set the LOCK bit."] - #[inline(always)] - pub const fn lock(&self) -> bool { - let val = (self.0 >> 2usize) & 0x01; - val != 0 - } - #[doc = "LOCK is 0 at reset, and is set to 1 automatically upon a successful write to this channel's control registers. That is, a write to CTRL, READ_ADDR, WRITE_ADDR, TRANS_COUNT and their aliases. Once its LOCK bit is set, this register becomes read-only. A failed write, for example due to the write's privilege being lower than that specified in the channel's SECCFG register, will not set the LOCK bit."] - #[inline(always)] - pub fn set_lock(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 2usize)) | (((val as u32) & 0x01) << 2usize); - } -} -impl Default for SeccfgCh10 { - #[inline(always)] - fn default() -> SeccfgCh10 { - SeccfgCh10(0) - } -} -#[doc = "Security configuration for channel 11. Control whether this channel performs Secure/Non-secure and Privileged/Unprivileged bus accesses. If this channel generates bus accesses of some security level, an access of at least that level (in the order S+P > S+U > NS+P > NS+U) is required to program, trigger, abort, check the status of, interrupt on or acknowledge the interrupt of this channel. This register automatically locks down (becomes read-only) once software starts to configure the channel. This register is world-readable, but is writable only from a Secure, Privileged context."] -#[repr(transparent)] -#[derive(Copy, Clone, Eq, PartialEq)] -pub struct SeccfgCh11(pub u32); -impl SeccfgCh11 { - #[doc = "Privileged channel. If 1, this channel performs Privileged bus accesses. If 0, it performs Unprivileged bus accesses. If 1, this channel is controllable only from a Privileged context of the same Secure/Non-secure level, or any context of a higher Secure/Non-secure level."] - #[inline(always)] - pub const fn p(&self) -> bool { - let val = (self.0 >> 0usize) & 0x01; - val != 0 - } - #[doc = "Privileged channel. If 1, this channel performs Privileged bus accesses. If 0, it performs Unprivileged bus accesses. If 1, this channel is controllable only from a Privileged context of the same Secure/Non-secure level, or any context of a higher Secure/Non-secure level."] - #[inline(always)] - pub fn set_p(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize); - } - #[doc = "Secure channel. If 1, this channel performs Secure bus accesses. If 0, it performs Non-secure bus accesses. If 1, this channel is controllable only from a Secure context."] - #[inline(always)] - pub const fn s(&self) -> bool { - let val = (self.0 >> 1usize) & 0x01; - val != 0 - } - #[doc = "Secure channel. If 1, this channel performs Secure bus accesses. If 0, it performs Non-secure bus accesses. If 1, this channel is controllable only from a Secure context."] - #[inline(always)] - pub fn set_s(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize); - } - #[doc = "LOCK is 0 at reset, and is set to 1 automatically upon a successful write to this channel's control registers. That is, a write to CTRL, READ_ADDR, WRITE_ADDR, TRANS_COUNT and their aliases. Once its LOCK bit is set, this register becomes read-only. A failed write, for example due to the write's privilege being lower than that specified in the channel's SECCFG register, will not set the LOCK bit."] - #[inline(always)] - pub const fn lock(&self) -> bool { - let val = (self.0 >> 2usize) & 0x01; - val != 0 - } - #[doc = "LOCK is 0 at reset, and is set to 1 automatically upon a successful write to this channel's control registers. That is, a write to CTRL, READ_ADDR, WRITE_ADDR, TRANS_COUNT and their aliases. Once its LOCK bit is set, this register becomes read-only. A failed write, for example due to the write's privilege being lower than that specified in the channel's SECCFG register, will not set the LOCK bit."] - #[inline(always)] - pub fn set_lock(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 2usize)) | (((val as u32) & 0x01) << 2usize); - } -} -impl Default for SeccfgCh11 { - #[inline(always)] - fn default() -> SeccfgCh11 { - SeccfgCh11(0) - } -} -#[doc = "Security configuration for channel 12. Control whether this channel performs Secure/Non-secure and Privileged/Unprivileged bus accesses. If this channel generates bus accesses of some security level, an access of at least that level (in the order S+P > S+U > NS+P > NS+U) is required to program, trigger, abort, check the status of, interrupt on or acknowledge the interrupt of this channel. This register automatically locks down (becomes read-only) once software starts to configure the channel. This register is world-readable, but is writable only from a Secure, Privileged context."] -#[repr(transparent)] -#[derive(Copy, Clone, Eq, PartialEq)] -pub struct SeccfgCh12(pub u32); -impl SeccfgCh12 { - #[doc = "Privileged channel. If 1, this channel performs Privileged bus accesses. If 0, it performs Unprivileged bus accesses. If 1, this channel is controllable only from a Privileged context of the same Secure/Non-secure level, or any context of a higher Secure/Non-secure level."] - #[inline(always)] - pub const fn p(&self) -> bool { - let val = (self.0 >> 0usize) & 0x01; - val != 0 - } - #[doc = "Privileged channel. If 1, this channel performs Privileged bus accesses. If 0, it performs Unprivileged bus accesses. If 1, this channel is controllable only from a Privileged context of the same Secure/Non-secure level, or any context of a higher Secure/Non-secure level."] - #[inline(always)] - pub fn set_p(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize); - } - #[doc = "Secure channel. If 1, this channel performs Secure bus accesses. If 0, it performs Non-secure bus accesses. If 1, this channel is controllable only from a Secure context."] - #[inline(always)] - pub const fn s(&self) -> bool { - let val = (self.0 >> 1usize) & 0x01; - val != 0 - } - #[doc = "Secure channel. If 1, this channel performs Secure bus accesses. If 0, it performs Non-secure bus accesses. If 1, this channel is controllable only from a Secure context."] - #[inline(always)] - pub fn set_s(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize); - } - #[doc = "LOCK is 0 at reset, and is set to 1 automatically upon a successful write to this channel's control registers. That is, a write to CTRL, READ_ADDR, WRITE_ADDR, TRANS_COUNT and their aliases. Once its LOCK bit is set, this register becomes read-only. A failed write, for example due to the write's privilege being lower than that specified in the channel's SECCFG register, will not set the LOCK bit."] - #[inline(always)] - pub const fn lock(&self) -> bool { - let val = (self.0 >> 2usize) & 0x01; - val != 0 - } - #[doc = "LOCK is 0 at reset, and is set to 1 automatically upon a successful write to this channel's control registers. That is, a write to CTRL, READ_ADDR, WRITE_ADDR, TRANS_COUNT and their aliases. Once its LOCK bit is set, this register becomes read-only. A failed write, for example due to the write's privilege being lower than that specified in the channel's SECCFG register, will not set the LOCK bit."] - #[inline(always)] - pub fn set_lock(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 2usize)) | (((val as u32) & 0x01) << 2usize); - } -} -impl Default for SeccfgCh12 { - #[inline(always)] - fn default() -> SeccfgCh12 { - SeccfgCh12(0) - } -} -#[doc = "Security configuration for channel 13. Control whether this channel performs Secure/Non-secure and Privileged/Unprivileged bus accesses. If this channel generates bus accesses of some security level, an access of at least that level (in the order S+P > S+U > NS+P > NS+U) is required to program, trigger, abort, check the status of, interrupt on or acknowledge the interrupt of this channel. This register automatically locks down (becomes read-only) once software starts to configure the channel. This register is world-readable, but is writable only from a Secure, Privileged context."] -#[repr(transparent)] -#[derive(Copy, Clone, Eq, PartialEq)] -pub struct SeccfgCh13(pub u32); -impl SeccfgCh13 { - #[doc = "Privileged channel. If 1, this channel performs Privileged bus accesses. If 0, it performs Unprivileged bus accesses. If 1, this channel is controllable only from a Privileged context of the same Secure/Non-secure level, or any context of a higher Secure/Non-secure level."] - #[inline(always)] - pub const fn p(&self) -> bool { - let val = (self.0 >> 0usize) & 0x01; - val != 0 - } - #[doc = "Privileged channel. If 1, this channel performs Privileged bus accesses. If 0, it performs Unprivileged bus accesses. If 1, this channel is controllable only from a Privileged context of the same Secure/Non-secure level, or any context of a higher Secure/Non-secure level."] - #[inline(always)] - pub fn set_p(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize); - } - #[doc = "Secure channel. If 1, this channel performs Secure bus accesses. If 0, it performs Non-secure bus accesses. If 1, this channel is controllable only from a Secure context."] - #[inline(always)] - pub const fn s(&self) -> bool { - let val = (self.0 >> 1usize) & 0x01; - val != 0 - } - #[doc = "Secure channel. If 1, this channel performs Secure bus accesses. If 0, it performs Non-secure bus accesses. If 1, this channel is controllable only from a Secure context."] - #[inline(always)] - pub fn set_s(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize); - } - #[doc = "LOCK is 0 at reset, and is set to 1 automatically upon a successful write to this channel's control registers. That is, a write to CTRL, READ_ADDR, WRITE_ADDR, TRANS_COUNT and their aliases. Once its LOCK bit is set, this register becomes read-only. A failed write, for example due to the write's privilege being lower than that specified in the channel's SECCFG register, will not set the LOCK bit."] - #[inline(always)] - pub const fn lock(&self) -> bool { - let val = (self.0 >> 2usize) & 0x01; - val != 0 - } - #[doc = "LOCK is 0 at reset, and is set to 1 automatically upon a successful write to this channel's control registers. That is, a write to CTRL, READ_ADDR, WRITE_ADDR, TRANS_COUNT and their aliases. Once its LOCK bit is set, this register becomes read-only. A failed write, for example due to the write's privilege being lower than that specified in the channel's SECCFG register, will not set the LOCK bit."] - #[inline(always)] - pub fn set_lock(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 2usize)) | (((val as u32) & 0x01) << 2usize); - } -} -impl Default for SeccfgCh13 { - #[inline(always)] - fn default() -> SeccfgCh13 { - SeccfgCh13(0) - } -} -#[doc = "Security configuration for channel 14. Control whether this channel performs Secure/Non-secure and Privileged/Unprivileged bus accesses. If this channel generates bus accesses of some security level, an access of at least that level (in the order S+P > S+U > NS+P > NS+U) is required to program, trigger, abort, check the status of, interrupt on or acknowledge the interrupt of this channel. This register automatically locks down (becomes read-only) once software starts to configure the channel. This register is world-readable, but is writable only from a Secure, Privileged context."] -#[repr(transparent)] -#[derive(Copy, Clone, Eq, PartialEq)] -pub struct SeccfgCh14(pub u32); -impl SeccfgCh14 { - #[doc = "Privileged channel. If 1, this channel performs Privileged bus accesses. If 0, it performs Unprivileged bus accesses. If 1, this channel is controllable only from a Privileged context of the same Secure/Non-secure level, or any context of a higher Secure/Non-secure level."] - #[inline(always)] - pub const fn p(&self) -> bool { - let val = (self.0 >> 0usize) & 0x01; - val != 0 - } - #[doc = "Privileged channel. If 1, this channel performs Privileged bus accesses. If 0, it performs Unprivileged bus accesses. If 1, this channel is controllable only from a Privileged context of the same Secure/Non-secure level, or any context of a higher Secure/Non-secure level."] - #[inline(always)] - pub fn set_p(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize); - } - #[doc = "Secure channel. If 1, this channel performs Secure bus accesses. If 0, it performs Non-secure bus accesses. If 1, this channel is controllable only from a Secure context."] - #[inline(always)] - pub const fn s(&self) -> bool { - let val = (self.0 >> 1usize) & 0x01; - val != 0 - } - #[doc = "Secure channel. If 1, this channel performs Secure bus accesses. If 0, it performs Non-secure bus accesses. If 1, this channel is controllable only from a Secure context."] - #[inline(always)] - pub fn set_s(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize); - } - #[doc = "LOCK is 0 at reset, and is set to 1 automatically upon a successful write to this channel's control registers. That is, a write to CTRL, READ_ADDR, WRITE_ADDR, TRANS_COUNT and their aliases. Once its LOCK bit is set, this register becomes read-only. A failed write, for example due to the write's privilege being lower than that specified in the channel's SECCFG register, will not set the LOCK bit."] - #[inline(always)] - pub const fn lock(&self) -> bool { - let val = (self.0 >> 2usize) & 0x01; - val != 0 - } - #[doc = "LOCK is 0 at reset, and is set to 1 automatically upon a successful write to this channel's control registers. That is, a write to CTRL, READ_ADDR, WRITE_ADDR, TRANS_COUNT and their aliases. Once its LOCK bit is set, this register becomes read-only. A failed write, for example due to the write's privilege being lower than that specified in the channel's SECCFG register, will not set the LOCK bit."] - #[inline(always)] - pub fn set_lock(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 2usize)) | (((val as u32) & 0x01) << 2usize); - } -} -impl Default for SeccfgCh14 { - #[inline(always)] - fn default() -> SeccfgCh14 { - SeccfgCh14(0) - } -} -#[doc = "Security configuration for channel 15. Control whether this channel performs Secure/Non-secure and Privileged/Unprivileged bus accesses. If this channel generates bus accesses of some security level, an access of at least that level (in the order S+P > S+U > NS+P > NS+U) is required to program, trigger, abort, check the status of, interrupt on or acknowledge the interrupt of this channel. This register automatically locks down (becomes read-only) once software starts to configure the channel. This register is world-readable, but is writable only from a Secure, Privileged context."] -#[repr(transparent)] -#[derive(Copy, Clone, Eq, PartialEq)] -pub struct SeccfgCh15(pub u32); -impl SeccfgCh15 { - #[doc = "Privileged channel. If 1, this channel performs Privileged bus accesses. If 0, it performs Unprivileged bus accesses. If 1, this channel is controllable only from a Privileged context of the same Secure/Non-secure level, or any context of a higher Secure/Non-secure level."] - #[inline(always)] - pub const fn p(&self) -> bool { - let val = (self.0 >> 0usize) & 0x01; - val != 0 - } - #[doc = "Privileged channel. If 1, this channel performs Privileged bus accesses. If 0, it performs Unprivileged bus accesses. If 1, this channel is controllable only from a Privileged context of the same Secure/Non-secure level, or any context of a higher Secure/Non-secure level."] - #[inline(always)] - pub fn set_p(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize); - } - #[doc = "Secure channel. If 1, this channel performs Secure bus accesses. If 0, it performs Non-secure bus accesses. If 1, this channel is controllable only from a Secure context."] - #[inline(always)] - pub const fn s(&self) -> bool { - let val = (self.0 >> 1usize) & 0x01; - val != 0 - } - #[doc = "Secure channel. If 1, this channel performs Secure bus accesses. If 0, it performs Non-secure bus accesses. If 1, this channel is controllable only from a Secure context."] - #[inline(always)] - pub fn set_s(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize); - } - #[doc = "LOCK is 0 at reset, and is set to 1 automatically upon a successful write to this channel's control registers. That is, a write to CTRL, READ_ADDR, WRITE_ADDR, TRANS_COUNT and their aliases. Once its LOCK bit is set, this register becomes read-only. A failed write, for example due to the write's privilege being lower than that specified in the channel's SECCFG register, will not set the LOCK bit."] - #[inline(always)] - pub const fn lock(&self) -> bool { - let val = (self.0 >> 2usize) & 0x01; - val != 0 - } - #[doc = "LOCK is 0 at reset, and is set to 1 automatically upon a successful write to this channel's control registers. That is, a write to CTRL, READ_ADDR, WRITE_ADDR, TRANS_COUNT and their aliases. Once its LOCK bit is set, this register becomes read-only. A failed write, for example due to the write's privilege being lower than that specified in the channel's SECCFG register, will not set the LOCK bit."] - #[inline(always)] - pub fn set_lock(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 2usize)) | (((val as u32) & 0x01) << 2usize); - } -} -impl Default for SeccfgCh15 { - #[inline(always)] - fn default() -> SeccfgCh15 { - SeccfgCh15(0) - } -} -#[doc = "Security configuration for channel 2. Control whether this channel performs Secure/Non-secure and Privileged/Unprivileged bus accesses. If this channel generates bus accesses of some security level, an access of at least that level (in the order S+P > S+U > NS+P > NS+U) is required to program, trigger, abort, check the status of, interrupt on or acknowledge the interrupt of this channel. This register automatically locks down (becomes read-only) once software starts to configure the channel. This register is world-readable, but is writable only from a Secure, Privileged context."] -#[repr(transparent)] -#[derive(Copy, Clone, Eq, PartialEq)] -pub struct SeccfgCh2(pub u32); -impl SeccfgCh2 { - #[doc = "Privileged channel. If 1, this channel performs Privileged bus accesses. If 0, it performs Unprivileged bus accesses. If 1, this channel is controllable only from a Privileged context of the same Secure/Non-secure level, or any context of a higher Secure/Non-secure level."] - #[inline(always)] - pub const fn p(&self) -> bool { - let val = (self.0 >> 0usize) & 0x01; - val != 0 - } - #[doc = "Privileged channel. If 1, this channel performs Privileged bus accesses. If 0, it performs Unprivileged bus accesses. If 1, this channel is controllable only from a Privileged context of the same Secure/Non-secure level, or any context of a higher Secure/Non-secure level."] - #[inline(always)] - pub fn set_p(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize); - } - #[doc = "Secure channel. If 1, this channel performs Secure bus accesses. If 0, it performs Non-secure bus accesses. If 1, this channel is controllable only from a Secure context."] - #[inline(always)] - pub const fn s(&self) -> bool { - let val = (self.0 >> 1usize) & 0x01; - val != 0 - } - #[doc = "Secure channel. If 1, this channel performs Secure bus accesses. If 0, it performs Non-secure bus accesses. If 1, this channel is controllable only from a Secure context."] - #[inline(always)] - pub fn set_s(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize); - } - #[doc = "LOCK is 0 at reset, and is set to 1 automatically upon a successful write to this channel's control registers. That is, a write to CTRL, READ_ADDR, WRITE_ADDR, TRANS_COUNT and their aliases. Once its LOCK bit is set, this register becomes read-only. A failed write, for example due to the write's privilege being lower than that specified in the channel's SECCFG register, will not set the LOCK bit."] - #[inline(always)] - pub const fn lock(&self) -> bool { - let val = (self.0 >> 2usize) & 0x01; - val != 0 - } - #[doc = "LOCK is 0 at reset, and is set to 1 automatically upon a successful write to this channel's control registers. That is, a write to CTRL, READ_ADDR, WRITE_ADDR, TRANS_COUNT and their aliases. Once its LOCK bit is set, this register becomes read-only. A failed write, for example due to the write's privilege being lower than that specified in the channel's SECCFG register, will not set the LOCK bit."] - #[inline(always)] - pub fn set_lock(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 2usize)) | (((val as u32) & 0x01) << 2usize); - } -} -impl Default for SeccfgCh2 { - #[inline(always)] - fn default() -> SeccfgCh2 { - SeccfgCh2(0) - } -} -#[doc = "Security configuration for channel 3. Control whether this channel performs Secure/Non-secure and Privileged/Unprivileged bus accesses. If this channel generates bus accesses of some security level, an access of at least that level (in the order S+P > S+U > NS+P > NS+U) is required to program, trigger, abort, check the status of, interrupt on or acknowledge the interrupt of this channel. This register automatically locks down (becomes read-only) once software starts to configure the channel. This register is world-readable, but is writable only from a Secure, Privileged context."] -#[repr(transparent)] -#[derive(Copy, Clone, Eq, PartialEq)] -pub struct SeccfgCh3(pub u32); -impl SeccfgCh3 { - #[doc = "Privileged channel. If 1, this channel performs Privileged bus accesses. If 0, it performs Unprivileged bus accesses. If 1, this channel is controllable only from a Privileged context of the same Secure/Non-secure level, or any context of a higher Secure/Non-secure level."] - #[inline(always)] - pub const fn p(&self) -> bool { - let val = (self.0 >> 0usize) & 0x01; - val != 0 - } - #[doc = "Privileged channel. If 1, this channel performs Privileged bus accesses. If 0, it performs Unprivileged bus accesses. If 1, this channel is controllable only from a Privileged context of the same Secure/Non-secure level, or any context of a higher Secure/Non-secure level."] - #[inline(always)] - pub fn set_p(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize); - } - #[doc = "Secure channel. If 1, this channel performs Secure bus accesses. If 0, it performs Non-secure bus accesses. If 1, this channel is controllable only from a Secure context."] - #[inline(always)] - pub const fn s(&self) -> bool { - let val = (self.0 >> 1usize) & 0x01; - val != 0 - } - #[doc = "Secure channel. If 1, this channel performs Secure bus accesses. If 0, it performs Non-secure bus accesses. If 1, this channel is controllable only from a Secure context."] - #[inline(always)] - pub fn set_s(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize); - } - #[doc = "LOCK is 0 at reset, and is set to 1 automatically upon a successful write to this channel's control registers. That is, a write to CTRL, READ_ADDR, WRITE_ADDR, TRANS_COUNT and their aliases. Once its LOCK bit is set, this register becomes read-only. A failed write, for example due to the write's privilege being lower than that specified in the channel's SECCFG register, will not set the LOCK bit."] - #[inline(always)] - pub const fn lock(&self) -> bool { - let val = (self.0 >> 2usize) & 0x01; - val != 0 - } - #[doc = "LOCK is 0 at reset, and is set to 1 automatically upon a successful write to this channel's control registers. That is, a write to CTRL, READ_ADDR, WRITE_ADDR, TRANS_COUNT and their aliases. Once its LOCK bit is set, this register becomes read-only. A failed write, for example due to the write's privilege being lower than that specified in the channel's SECCFG register, will not set the LOCK bit."] - #[inline(always)] - pub fn set_lock(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 2usize)) | (((val as u32) & 0x01) << 2usize); - } -} -impl Default for SeccfgCh3 { - #[inline(always)] - fn default() -> SeccfgCh3 { - SeccfgCh3(0) - } -} -#[doc = "Security configuration for channel 4. Control whether this channel performs Secure/Non-secure and Privileged/Unprivileged bus accesses. If this channel generates bus accesses of some security level, an access of at least that level (in the order S+P > S+U > NS+P > NS+U) is required to program, trigger, abort, check the status of, interrupt on or acknowledge the interrupt of this channel. This register automatically locks down (becomes read-only) once software starts to configure the channel. This register is world-readable, but is writable only from a Secure, Privileged context."] -#[repr(transparent)] -#[derive(Copy, Clone, Eq, PartialEq)] -pub struct SeccfgCh4(pub u32); -impl SeccfgCh4 { - #[doc = "Privileged channel. If 1, this channel performs Privileged bus accesses. If 0, it performs Unprivileged bus accesses. If 1, this channel is controllable only from a Privileged context of the same Secure/Non-secure level, or any context of a higher Secure/Non-secure level."] - #[inline(always)] - pub const fn p(&self) -> bool { - let val = (self.0 >> 0usize) & 0x01; - val != 0 - } - #[doc = "Privileged channel. If 1, this channel performs Privileged bus accesses. If 0, it performs Unprivileged bus accesses. If 1, this channel is controllable only from a Privileged context of the same Secure/Non-secure level, or any context of a higher Secure/Non-secure level."] - #[inline(always)] - pub fn set_p(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize); - } - #[doc = "Secure channel. If 1, this channel performs Secure bus accesses. If 0, it performs Non-secure bus accesses. If 1, this channel is controllable only from a Secure context."] - #[inline(always)] - pub const fn s(&self) -> bool { - let val = (self.0 >> 1usize) & 0x01; - val != 0 - } - #[doc = "Secure channel. If 1, this channel performs Secure bus accesses. If 0, it performs Non-secure bus accesses. If 1, this channel is controllable only from a Secure context."] - #[inline(always)] - pub fn set_s(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize); - } - #[doc = "LOCK is 0 at reset, and is set to 1 automatically upon a successful write to this channel's control registers. That is, a write to CTRL, READ_ADDR, WRITE_ADDR, TRANS_COUNT and their aliases. Once its LOCK bit is set, this register becomes read-only. A failed write, for example due to the write's privilege being lower than that specified in the channel's SECCFG register, will not set the LOCK bit."] - #[inline(always)] - pub const fn lock(&self) -> bool { - let val = (self.0 >> 2usize) & 0x01; - val != 0 - } - #[doc = "LOCK is 0 at reset, and is set to 1 automatically upon a successful write to this channel's control registers. That is, a write to CTRL, READ_ADDR, WRITE_ADDR, TRANS_COUNT and their aliases. Once its LOCK bit is set, this register becomes read-only. A failed write, for example due to the write's privilege being lower than that specified in the channel's SECCFG register, will not set the LOCK bit."] - #[inline(always)] - pub fn set_lock(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 2usize)) | (((val as u32) & 0x01) << 2usize); - } -} -impl Default for SeccfgCh4 { - #[inline(always)] - fn default() -> SeccfgCh4 { - SeccfgCh4(0) - } -} -#[doc = "Security configuration for channel 5. Control whether this channel performs Secure/Non-secure and Privileged/Unprivileged bus accesses. If this channel generates bus accesses of some security level, an access of at least that level (in the order S+P > S+U > NS+P > NS+U) is required to program, trigger, abort, check the status of, interrupt on or acknowledge the interrupt of this channel. This register automatically locks down (becomes read-only) once software starts to configure the channel. This register is world-readable, but is writable only from a Secure, Privileged context."] -#[repr(transparent)] -#[derive(Copy, Clone, Eq, PartialEq)] -pub struct SeccfgCh5(pub u32); -impl SeccfgCh5 { - #[doc = "Privileged channel. If 1, this channel performs Privileged bus accesses. If 0, it performs Unprivileged bus accesses. If 1, this channel is controllable only from a Privileged context of the same Secure/Non-secure level, or any context of a higher Secure/Non-secure level."] - #[inline(always)] - pub const fn p(&self) -> bool { - let val = (self.0 >> 0usize) & 0x01; - val != 0 - } - #[doc = "Privileged channel. If 1, this channel performs Privileged bus accesses. If 0, it performs Unprivileged bus accesses. If 1, this channel is controllable only from a Privileged context of the same Secure/Non-secure level, or any context of a higher Secure/Non-secure level."] - #[inline(always)] - pub fn set_p(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize); - } - #[doc = "Secure channel. If 1, this channel performs Secure bus accesses. If 0, it performs Non-secure bus accesses. If 1, this channel is controllable only from a Secure context."] - #[inline(always)] - pub const fn s(&self) -> bool { - let val = (self.0 >> 1usize) & 0x01; - val != 0 - } - #[doc = "Secure channel. If 1, this channel performs Secure bus accesses. If 0, it performs Non-secure bus accesses. If 1, this channel is controllable only from a Secure context."] - #[inline(always)] - pub fn set_s(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize); - } - #[doc = "LOCK is 0 at reset, and is set to 1 automatically upon a successful write to this channel's control registers. That is, a write to CTRL, READ_ADDR, WRITE_ADDR, TRANS_COUNT and their aliases. Once its LOCK bit is set, this register becomes read-only. A failed write, for example due to the write's privilege being lower than that specified in the channel's SECCFG register, will not set the LOCK bit."] - #[inline(always)] - pub const fn lock(&self) -> bool { - let val = (self.0 >> 2usize) & 0x01; - val != 0 - } - #[doc = "LOCK is 0 at reset, and is set to 1 automatically upon a successful write to this channel's control registers. That is, a write to CTRL, READ_ADDR, WRITE_ADDR, TRANS_COUNT and their aliases. Once its LOCK bit is set, this register becomes read-only. A failed write, for example due to the write's privilege being lower than that specified in the channel's SECCFG register, will not set the LOCK bit."] - #[inline(always)] - pub fn set_lock(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 2usize)) | (((val as u32) & 0x01) << 2usize); - } -} -impl Default for SeccfgCh5 { - #[inline(always)] - fn default() -> SeccfgCh5 { - SeccfgCh5(0) - } -} -#[doc = "Security configuration for channel 6. Control whether this channel performs Secure/Non-secure and Privileged/Unprivileged bus accesses. If this channel generates bus accesses of some security level, an access of at least that level (in the order S+P > S+U > NS+P > NS+U) is required to program, trigger, abort, check the status of, interrupt on or acknowledge the interrupt of this channel. This register automatically locks down (becomes read-only) once software starts to configure the channel. This register is world-readable, but is writable only from a Secure, Privileged context."] -#[repr(transparent)] -#[derive(Copy, Clone, Eq, PartialEq)] -pub struct SeccfgCh6(pub u32); -impl SeccfgCh6 { - #[doc = "Privileged channel. If 1, this channel performs Privileged bus accesses. If 0, it performs Unprivileged bus accesses. If 1, this channel is controllable only from a Privileged context of the same Secure/Non-secure level, or any context of a higher Secure/Non-secure level."] - #[inline(always)] - pub const fn p(&self) -> bool { - let val = (self.0 >> 0usize) & 0x01; - val != 0 - } - #[doc = "Privileged channel. If 1, this channel performs Privileged bus accesses. If 0, it performs Unprivileged bus accesses. If 1, this channel is controllable only from a Privileged context of the same Secure/Non-secure level, or any context of a higher Secure/Non-secure level."] - #[inline(always)] - pub fn set_p(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize); - } - #[doc = "Secure channel. If 1, this channel performs Secure bus accesses. If 0, it performs Non-secure bus accesses. If 1, this channel is controllable only from a Secure context."] - #[inline(always)] - pub const fn s(&self) -> bool { - let val = (self.0 >> 1usize) & 0x01; - val != 0 - } - #[doc = "Secure channel. If 1, this channel performs Secure bus accesses. If 0, it performs Non-secure bus accesses. If 1, this channel is controllable only from a Secure context."] - #[inline(always)] - pub fn set_s(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize); - } - #[doc = "LOCK is 0 at reset, and is set to 1 automatically upon a successful write to this channel's control registers. That is, a write to CTRL, READ_ADDR, WRITE_ADDR, TRANS_COUNT and their aliases. Once its LOCK bit is set, this register becomes read-only. A failed write, for example due to the write's privilege being lower than that specified in the channel's SECCFG register, will not set the LOCK bit."] - #[inline(always)] - pub const fn lock(&self) -> bool { - let val = (self.0 >> 2usize) & 0x01; - val != 0 - } - #[doc = "LOCK is 0 at reset, and is set to 1 automatically upon a successful write to this channel's control registers. That is, a write to CTRL, READ_ADDR, WRITE_ADDR, TRANS_COUNT and their aliases. Once its LOCK bit is set, this register becomes read-only. A failed write, for example due to the write's privilege being lower than that specified in the channel's SECCFG register, will not set the LOCK bit."] - #[inline(always)] - pub fn set_lock(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 2usize)) | (((val as u32) & 0x01) << 2usize); - } -} -impl Default for SeccfgCh6 { - #[inline(always)] - fn default() -> SeccfgCh6 { - SeccfgCh6(0) - } -} -#[doc = "Security configuration for channel 7. Control whether this channel performs Secure/Non-secure and Privileged/Unprivileged bus accesses. If this channel generates bus accesses of some security level, an access of at least that level (in the order S+P > S+U > NS+P > NS+U) is required to program, trigger, abort, check the status of, interrupt on or acknowledge the interrupt of this channel. This register automatically locks down (becomes read-only) once software starts to configure the channel. This register is world-readable, but is writable only from a Secure, Privileged context."] -#[repr(transparent)] -#[derive(Copy, Clone, Eq, PartialEq)] -pub struct SeccfgCh7(pub u32); -impl SeccfgCh7 { - #[doc = "Privileged channel. If 1, this channel performs Privileged bus accesses. If 0, it performs Unprivileged bus accesses. If 1, this channel is controllable only from a Privileged context of the same Secure/Non-secure level, or any context of a higher Secure/Non-secure level."] + #[doc = "If 1, the channel received a read bus error. Write one to clear. READ_ADDR shows the approximate address where the bus error was encountered (will not be earlier, or more than 3 transfers later)"] #[inline(always)] - pub const fn p(&self) -> bool { - let val = (self.0 >> 0usize) & 0x01; + pub const fn read_error(&self) -> bool { + let val = (self.0 >> 30usize) & 0x01; val != 0 } - #[doc = "Privileged channel. If 1, this channel performs Privileged bus accesses. If 0, it performs Unprivileged bus accesses. If 1, this channel is controllable only from a Privileged context of the same Secure/Non-secure level, or any context of a higher Secure/Non-secure level."] + #[doc = "If 1, the channel received a read bus error. Write one to clear. READ_ADDR shows the approximate address where the bus error was encountered (will not be earlier, or more than 3 transfers later)"] #[inline(always)] - pub fn set_p(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize); + pub fn set_read_error(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 30usize)) | (((val as u32) & 0x01) << 30usize); } - #[doc = "Secure channel. If 1, this channel performs Secure bus accesses. If 0, it performs Non-secure bus accesses. If 1, this channel is controllable only from a Secure context."] + #[doc = "Logical OR of the READ_ERROR and WRITE_ERROR flags. The channel halts when it encounters any bus error, and always raises its channel IRQ flag."] #[inline(always)] - pub const fn s(&self) -> bool { - let val = (self.0 >> 1usize) & 0x01; + pub const fn ahb_error(&self) -> bool { + let val = (self.0 >> 31usize) & 0x01; val != 0 } - #[doc = "Secure channel. If 1, this channel performs Secure bus accesses. If 0, it performs Non-secure bus accesses. If 1, this channel is controllable only from a Secure context."] + #[doc = "Logical OR of the READ_ERROR and WRITE_ERROR flags. The channel halts when it encounters any bus error, and always raises its channel IRQ flag."] #[inline(always)] - pub fn set_s(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize); + pub fn set_ahb_error(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 31usize)) | (((val as u32) & 0x01) << 31usize); } - #[doc = "LOCK is 0 at reset, and is set to 1 automatically upon a successful write to this channel's control registers. That is, a write to CTRL, READ_ADDR, WRITE_ADDR, TRANS_COUNT and their aliases. Once its LOCK bit is set, this register becomes read-only. A failed write, for example due to the write's privilege being lower than that specified in the channel's SECCFG register, will not set the LOCK bit."] +} +impl Default for CtrlTrig { #[inline(always)] - pub const fn lock(&self) -> bool { - let val = (self.0 >> 2usize) & 0x01; - val != 0 + fn default() -> CtrlTrig { + CtrlTrig(0) } - #[doc = "LOCK is 0 at reset, and is set to 1 automatically upon a successful write to this channel's control registers. That is, a write to CTRL, READ_ADDR, WRITE_ADDR, TRANS_COUNT and their aliases. Once its LOCK bit is set, this register becomes read-only. A failed write, for example due to the write's privilege being lower than that specified in the channel's SECCFG register, will not set the LOCK bit."] +} +#[doc = "Read: get channel DREQ counter (i.e. how many accesses the DMA expects it can perform on the peripheral without overflow/underflow. Write any value: clears the counter, and cause channel to re-initiate DREQ handshake."] +#[repr(transparent)] +#[derive(Copy, Clone, Eq, PartialEq)] +pub struct DbgCtdreq(pub u32); +impl DbgCtdreq { #[inline(always)] - pub fn set_lock(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 2usize)) | (((val as u32) & 0x01) << 2usize); + pub const fn dbg_ctdreq(&self) -> u8 { + let val = (self.0 >> 0usize) & 0x3f; + val as u8 + } + #[inline(always)] + pub fn set_dbg_ctdreq(&mut self, val: u8) { + self.0 = (self.0 & !(0x3f << 0usize)) | (((val as u32) & 0x3f) << 0usize); } } -impl Default for SeccfgCh7 { +impl Default for DbgCtdreq { #[inline(always)] - fn default() -> SeccfgCh7 { - SeccfgCh7(0) + fn default() -> DbgCtdreq { + DbgCtdreq(0) } } -#[doc = "Security configuration for channel 8. Control whether this channel performs Secure/Non-secure and Privileged/Unprivileged bus accesses. If this channel generates bus accesses of some security level, an access of at least that level (in the order S+P > S+U > NS+P > NS+U) is required to program, trigger, abort, check the status of, interrupt on or acknowledge the interrupt of this channel. This register automatically locks down (becomes read-only) once software starts to configure the channel. This register is world-readable, but is writable only from a Secure, Privileged context."] +#[doc = "Debug RAF, WAF, TDF levels"] #[repr(transparent)] #[derive(Copy, Clone, Eq, PartialEq)] -pub struct SeccfgCh8(pub u32); -impl SeccfgCh8 { - #[doc = "Privileged channel. If 1, this channel performs Privileged bus accesses. If 0, it performs Unprivileged bus accesses. If 1, this channel is controllable only from a Privileged context of the same Secure/Non-secure level, or any context of a higher Secure/Non-secure level."] +pub struct FifoLevels(pub u32); +impl FifoLevels { + #[doc = "Current Transfer-Data-FIFO fill level"] #[inline(always)] - pub const fn p(&self) -> bool { - let val = (self.0 >> 0usize) & 0x01; - val != 0 + pub const fn tdf_lvl(&self) -> u8 { + let val = (self.0 >> 0usize) & 0xff; + val as u8 } - #[doc = "Privileged channel. If 1, this channel performs Privileged bus accesses. If 0, it performs Unprivileged bus accesses. If 1, this channel is controllable only from a Privileged context of the same Secure/Non-secure level, or any context of a higher Secure/Non-secure level."] + #[doc = "Current Transfer-Data-FIFO fill level"] #[inline(always)] - pub fn set_p(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize); + pub fn set_tdf_lvl(&mut self, val: u8) { + self.0 = (self.0 & !(0xff << 0usize)) | (((val as u32) & 0xff) << 0usize); } - #[doc = "Secure channel. If 1, this channel performs Secure bus accesses. If 0, it performs Non-secure bus accesses. If 1, this channel is controllable only from a Secure context."] + #[doc = "Current Write-Address-FIFO fill level"] #[inline(always)] - pub const fn s(&self) -> bool { - let val = (self.0 >> 1usize) & 0x01; - val != 0 + pub const fn waf_lvl(&self) -> u8 { + let val = (self.0 >> 8usize) & 0xff; + val as u8 } - #[doc = "Secure channel. If 1, this channel performs Secure bus accesses. If 0, it performs Non-secure bus accesses. If 1, this channel is controllable only from a Secure context."] + #[doc = "Current Write-Address-FIFO fill level"] #[inline(always)] - pub fn set_s(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize); + pub fn set_waf_lvl(&mut self, val: u8) { + self.0 = (self.0 & !(0xff << 8usize)) | (((val as u32) & 0xff) << 8usize); } - #[doc = "LOCK is 0 at reset, and is set to 1 automatically upon a successful write to this channel's control registers. That is, a write to CTRL, READ_ADDR, WRITE_ADDR, TRANS_COUNT and their aliases. Once its LOCK bit is set, this register becomes read-only. A failed write, for example due to the write's privilege being lower than that specified in the channel's SECCFG register, will not set the LOCK bit."] + #[doc = "Current Read-Address-FIFO fill level"] #[inline(always)] - pub const fn lock(&self) -> bool { - let val = (self.0 >> 2usize) & 0x01; - val != 0 + pub const fn raf_lvl(&self) -> u8 { + let val = (self.0 >> 16usize) & 0xff; + val as u8 } - #[doc = "LOCK is 0 at reset, and is set to 1 automatically upon a successful write to this channel's control registers. That is, a write to CTRL, READ_ADDR, WRITE_ADDR, TRANS_COUNT and their aliases. Once its LOCK bit is set, this register becomes read-only. A failed write, for example due to the write's privilege being lower than that specified in the channel's SECCFG register, will not set the LOCK bit."] + #[doc = "Current Read-Address-FIFO fill level"] #[inline(always)] - pub fn set_lock(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 2usize)) | (((val as u32) & 0x01) << 2usize); + pub fn set_raf_lvl(&mut self, val: u8) { + self.0 = (self.0 & !(0xff << 16usize)) | (((val as u32) & 0xff) << 16usize); } } -impl Default for SeccfgCh8 { +impl Default for FifoLevels { #[inline(always)] - fn default() -> SeccfgCh8 { - SeccfgCh8(0) + fn default() -> FifoLevels { + FifoLevels(0) } } -#[doc = "Security configuration for channel 9. Control whether this channel performs Secure/Non-secure and Privileged/Unprivileged bus accesses. If this channel generates bus accesses of some security level, an access of at least that level (in the order S+P > S+U > NS+P > NS+U) is required to program, trigger, abort, check the status of, interrupt on or acknowledge the interrupt of this channel. This register automatically locks down (becomes read-only) once software starts to configure the channel. This register is world-readable, but is writable only from a Secure, Privileged context."] +#[doc = "Control register for DMA MPU. Accessible only from a Privileged context."] #[repr(transparent)] #[derive(Copy, Clone, Eq, PartialEq)] -pub struct SeccfgCh9(pub u32); -impl SeccfgCh9 { - #[doc = "Privileged channel. If 1, this channel performs Privileged bus accesses. If 0, it performs Unprivileged bus accesses. If 1, this channel is controllable only from a Privileged context of the same Secure/Non-secure level, or any context of a higher Secure/Non-secure level."] +pub struct MpuCtrl(pub u32); +impl MpuCtrl { + #[doc = "Determine whether an address not covered by an active MPU region is Privileged (1) or Unprivileged (0)"] #[inline(always)] pub const fn p(&self) -> bool { - let val = (self.0 >> 0usize) & 0x01; + let val = (self.0 >> 1usize) & 0x01; val != 0 } - #[doc = "Privileged channel. If 1, this channel performs Privileged bus accesses. If 0, it performs Unprivileged bus accesses. If 1, this channel is controllable only from a Privileged context of the same Secure/Non-secure level, or any context of a higher Secure/Non-secure level."] + #[doc = "Determine whether an address not covered by an active MPU region is Privileged (1) or Unprivileged (0)"] #[inline(always)] pub fn set_p(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize); + self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize); } - #[doc = "Secure channel. If 1, this channel performs Secure bus accesses. If 0, it performs Non-secure bus accesses. If 1, this channel is controllable only from a Secure context."] + #[doc = "Determine whether an address not covered by an active MPU region is Secure (1) or Non-secure (0)"] #[inline(always)] pub const fn s(&self) -> bool { - let val = (self.0 >> 1usize) & 0x01; + let val = (self.0 >> 2usize) & 0x01; val != 0 } - #[doc = "Secure channel. If 1, this channel performs Secure bus accesses. If 0, it performs Non-secure bus accesses. If 1, this channel is controllable only from a Secure context."] + #[doc = "Determine whether an address not covered by an active MPU region is Secure (1) or Non-secure (0)"] #[inline(always)] pub fn set_s(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize); + self.0 = (self.0 & !(0x01 << 2usize)) | (((val as u32) & 0x01) << 2usize); } - #[doc = "LOCK is 0 at reset, and is set to 1 automatically upon a successful write to this channel's control registers. That is, a write to CTRL, READ_ADDR, WRITE_ADDR, TRANS_COUNT and their aliases. Once its LOCK bit is set, this register becomes read-only. A failed write, for example due to the write's privilege being lower than that specified in the channel's SECCFG register, will not set the LOCK bit."] + #[doc = "By default, when a region's S bit is clear, Non-secure-Privileged reads can see the region's base address and limit address. Set this bit to make the addresses appear as 0 to Non-secure reads, even when the region is Non-secure, to avoid leaking information about the processor SAU map."] #[inline(always)] - pub const fn lock(&self) -> bool { - let val = (self.0 >> 2usize) & 0x01; + pub const fn ns_hide_addr(&self) -> bool { + let val = (self.0 >> 3usize) & 0x01; val != 0 } - #[doc = "LOCK is 0 at reset, and is set to 1 automatically upon a successful write to this channel's control registers. That is, a write to CTRL, READ_ADDR, WRITE_ADDR, TRANS_COUNT and their aliases. Once its LOCK bit is set, this register becomes read-only. A failed write, for example due to the write's privilege being lower than that specified in the channel's SECCFG register, will not set the LOCK bit."] + #[doc = "By default, when a region's S bit is clear, Non-secure-Privileged reads can see the region's base address and limit address. Set this bit to make the addresses appear as 0 to Non-secure reads, even when the region is Non-secure, to avoid leaking information about the processor SAU map."] #[inline(always)] - pub fn set_lock(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 2usize)) | (((val as u32) & 0x01) << 2usize); + pub fn set_ns_hide_addr(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 3usize)) | (((val as u32) & 0x01) << 3usize); } } -impl Default for SeccfgCh9 { +impl Default for MpuCtrl { #[inline(always)] - fn default() -> SeccfgCh9 { - SeccfgCh9(0) + fn default() -> MpuCtrl { + MpuCtrl(0) } } -#[doc = "Security configuration for IRQ 0. Control whether the IRQ permits configuration by Non-secure/Unprivileged contexts, and whether it can observe Secure/Privileged channel interrupt flags."] +#[doc = "Trigger one or more channels simultaneously"] #[repr(transparent)] #[derive(Copy, Clone, Eq, PartialEq)] -pub struct SeccfgIrq0(pub u32); -impl SeccfgIrq0 { - #[doc = "Privileged IRQ. If 1, this IRQ's control registers can only be accessed from a Privileged context. If 0, this IRQ's control registers can be accessed from an Unprivileged context, but Privileged channels (as per SECCFG_CHx) are masked from the IRQ status, and this IRQ's registers can not be used to acknowledge the channel interrupts of Privileged channels."] - #[inline(always)] - pub const fn p(&self) -> bool { - let val = (self.0 >> 0usize) & 0x01; - val != 0 - } - #[doc = "Privileged IRQ. If 1, this IRQ's control registers can only be accessed from a Privileged context. If 0, this IRQ's control registers can be accessed from an Unprivileged context, but Privileged channels (as per SECCFG_CHx) are masked from the IRQ status, and this IRQ's registers can not be used to acknowledge the channel interrupts of Privileged channels."] - #[inline(always)] - pub fn set_p(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize); - } - #[doc = "Secure IRQ. If 1, this IRQ's control registers can only be accessed from a Secure context. If 0, this IRQ's control registers can be accessed from a Non-secure context, but Secure channels (as per SECCFG_CHx) are masked from the IRQ status, and this IRQ's registers can not be used to acknowledge the channel interrupts of Secure channels."] +pub struct MultiChanTrigger(pub u32); +impl MultiChanTrigger { + #[doc = "Each bit in this register corresponds to a DMA channel. Writing a 1 to the relevant bit is the same as writing to that channel's trigger register; the channel will start if it is currently enabled and not already busy."] #[inline(always)] - pub const fn s(&self) -> bool { - let val = (self.0 >> 1usize) & 0x01; - val != 0 + pub const fn multi_chan_trigger(&self) -> u16 { + let val = (self.0 >> 0usize) & 0xffff; + val as u16 } - #[doc = "Secure IRQ. If 1, this IRQ's control registers can only be accessed from a Secure context. If 0, this IRQ's control registers can be accessed from a Non-secure context, but Secure channels (as per SECCFG_CHx) are masked from the IRQ status, and this IRQ's registers can not be used to acknowledge the channel interrupts of Secure channels."] + #[doc = "Each bit in this register corresponds to a DMA channel. Writing a 1 to the relevant bit is the same as writing to that channel's trigger register; the channel will start if it is currently enabled and not already busy."] #[inline(always)] - pub fn set_s(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize); + pub fn set_multi_chan_trigger(&mut self, val: u16) { + self.0 = (self.0 & !(0xffff << 0usize)) | (((val as u32) & 0xffff) << 0usize); } } -impl Default for SeccfgIrq0 { +impl Default for MultiChanTrigger { #[inline(always)] - fn default() -> SeccfgIrq0 { - SeccfgIrq0(0) + fn default() -> MultiChanTrigger { + MultiChanTrigger(0) } } -#[doc = "Security configuration for IRQ 1. Control whether the IRQ permits configuration by Non-secure/Unprivileged contexts, and whether it can observe Secure/Privileged channel interrupt flags."] +#[doc = "The number of channels this DMA instance is equipped with. This DMA supports up to 16 hardware channels, but can be configured with as few as one, to minimise silicon area."] #[repr(transparent)] #[derive(Copy, Clone, Eq, PartialEq)] -pub struct SeccfgIrq1(pub u32); -impl SeccfgIrq1 { - #[doc = "Privileged IRQ. If 1, this IRQ's control registers can only be accessed from a Privileged context. If 0, this IRQ's control registers can be accessed from an Unprivileged context, but Privileged channels (as per SECCFG_CHx) are masked from the IRQ status, and this IRQ's registers can not be used to acknowledge the channel interrupts of Privileged channels."] - #[inline(always)] - pub const fn p(&self) -> bool { - let val = (self.0 >> 0usize) & 0x01; - val != 0 - } - #[doc = "Privileged IRQ. If 1, this IRQ's control registers can only be accessed from a Privileged context. If 0, this IRQ's control registers can be accessed from an Unprivileged context, but Privileged channels (as per SECCFG_CHx) are masked from the IRQ status, and this IRQ's registers can not be used to acknowledge the channel interrupts of Privileged channels."] - #[inline(always)] - pub fn set_p(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize); - } - #[doc = "Secure IRQ. If 1, this IRQ's control registers can only be accessed from a Secure context. If 0, this IRQ's control registers can be accessed from a Non-secure context, but Secure channels (as per SECCFG_CHx) are masked from the IRQ status, and this IRQ's registers can not be used to acknowledge the channel interrupts of Secure channels."] +pub struct Nchannels(pub u32); +impl Nchannels { #[inline(always)] - pub const fn s(&self) -> bool { - let val = (self.0 >> 1usize) & 0x01; - val != 0 + pub const fn n_channels(&self) -> u8 { + let val = (self.0 >> 0usize) & 0x1f; + val as u8 } - #[doc = "Secure IRQ. If 1, this IRQ's control registers can only be accessed from a Secure context. If 0, this IRQ's control registers can be accessed from a Non-secure context, but Secure channels (as per SECCFG_CHx) are masked from the IRQ status, and this IRQ's registers can not be used to acknowledge the channel interrupts of Secure channels."] #[inline(always)] - pub fn set_s(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize); + pub fn set_n_channels(&mut self, val: u8) { + self.0 = (self.0 & !(0x1f << 0usize)) | (((val as u32) & 0x1f) << 0usize); } } -impl Default for SeccfgIrq1 { +impl Default for Nchannels { #[inline(always)] - fn default() -> SeccfgIrq1 { - SeccfgIrq1(0) + fn default() -> Nchannels { + Nchannels(0) } } -#[doc = "Security configuration for IRQ 2. Control whether the IRQ permits configuration by Non-secure/Unprivileged contexts, and whether it can observe Secure/Privileged channel interrupt flags."] +#[doc = "Security configuration for channel 6. Control whether this channel performs Secure/Non-secure and Privileged/Unprivileged bus accesses. If this channel generates bus accesses of some security level, an access of at least that level (in the order S+P > S+U > NS+P > NS+U) is required to program, trigger, abort, check the status of, interrupt on or acknowledge the interrupt of this channel. This register automatically locks down (becomes read-only) once software starts to configure the channel. This register is world-readable, but is writable only from a Secure, Privileged context."] #[repr(transparent)] #[derive(Copy, Clone, Eq, PartialEq)] -pub struct SeccfgIrq2(pub u32); -impl SeccfgIrq2 { - #[doc = "Privileged IRQ. If 1, this IRQ's control registers can only be accessed from a Privileged context. If 0, this IRQ's control registers can be accessed from an Unprivileged context, but Privileged channels (as per SECCFG_CHx) are masked from the IRQ status, and this IRQ's registers can not be used to acknowledge the channel interrupts of Privileged channels."] +pub struct SeccfgCh(pub u32); +impl SeccfgCh { + #[doc = "Privileged channel. If 1, this channel performs Privileged bus accesses. If 0, it performs Unprivileged bus accesses. If 1, this channel is controllable only from a Privileged context of the same Secure/Non-secure level, or any context of a higher Secure/Non-secure level."] #[inline(always)] pub const fn p(&self) -> bool { let val = (self.0 >> 0usize) & 0x01; val != 0 } - #[doc = "Privileged IRQ. If 1, this IRQ's control registers can only be accessed from a Privileged context. If 0, this IRQ's control registers can be accessed from an Unprivileged context, but Privileged channels (as per SECCFG_CHx) are masked from the IRQ status, and this IRQ's registers can not be used to acknowledge the channel interrupts of Privileged channels."] + #[doc = "Privileged channel. If 1, this channel performs Privileged bus accesses. If 0, it performs Unprivileged bus accesses. If 1, this channel is controllable only from a Privileged context of the same Secure/Non-secure level, or any context of a higher Secure/Non-secure level."] #[inline(always)] pub fn set_p(&mut self, val: bool) { self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize); } - #[doc = "Secure IRQ. If 1, this IRQ's control registers can only be accessed from a Secure context. If 0, this IRQ's control registers can be accessed from a Non-secure context, but Secure channels (as per SECCFG_CHx) are masked from the IRQ status, and this IRQ's registers can not be used to acknowledge the channel interrupts of Secure channels."] + #[doc = "Secure channel. If 1, this channel performs Secure bus accesses. If 0, it performs Non-secure bus accesses. If 1, this channel is controllable only from a Secure context."] #[inline(always)] pub const fn s(&self) -> bool { let val = (self.0 >> 1usize) & 0x01; val != 0 } - #[doc = "Secure IRQ. If 1, this IRQ's control registers can only be accessed from a Secure context. If 0, this IRQ's control registers can be accessed from a Non-secure context, but Secure channels (as per SECCFG_CHx) are masked from the IRQ status, and this IRQ's registers can not be used to acknowledge the channel interrupts of Secure channels."] + #[doc = "Secure channel. If 1, this channel performs Secure bus accesses. If 0, it performs Non-secure bus accesses. If 1, this channel is controllable only from a Secure context."] #[inline(always)] pub fn set_s(&mut self, val: bool) { self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize); } + #[doc = "LOCK is 0 at reset, and is set to 1 automatically upon a successful write to this channel's control registers. That is, a write to CTRL, READ_ADDR, WRITE_ADDR, TRANS_COUNT and their aliases. Once its LOCK bit is set, this register becomes read-only. A failed write, for example due to the write's privilege being lower than that specified in the channel's SECCFG register, will not set the LOCK bit."] + #[inline(always)] + pub const fn lock(&self) -> bool { + let val = (self.0 >> 2usize) & 0x01; + val != 0 + } + #[doc = "LOCK is 0 at reset, and is set to 1 automatically upon a successful write to this channel's control registers. That is, a write to CTRL, READ_ADDR, WRITE_ADDR, TRANS_COUNT and their aliases. Once its LOCK bit is set, this register becomes read-only. A failed write, for example due to the write's privilege being lower than that specified in the channel's SECCFG register, will not set the LOCK bit."] + #[inline(always)] + pub fn set_lock(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 2usize)) | (((val as u32) & 0x01) << 2usize); + } } -impl Default for SeccfgIrq2 { +impl Default for SeccfgCh { #[inline(always)] - fn default() -> SeccfgIrq2 { - SeccfgIrq2(0) + fn default() -> SeccfgCh { + SeccfgCh(0) } } #[doc = "Security configuration for IRQ 3. Control whether the IRQ permits configuration by Non-secure/Unprivileged contexts, and whether it can observe Secure/Privileged channel interrupt flags."] #[repr(transparent)] #[derive(Copy, Clone, Eq, PartialEq)] -pub struct SeccfgIrq3(pub u32); -impl SeccfgIrq3 { +pub struct SeccfgIrq(pub u32); +impl SeccfgIrq { #[doc = "Privileged IRQ. If 1, this IRQ's control registers can only be accessed from a Privileged context. If 0, this IRQ's control registers can be accessed from an Unprivileged context, but Privileged channels (as per SECCFG_CHx) are masked from the IRQ status, and this IRQ's registers can not be used to acknowledge the channel interrupts of Privileged channels."] #[inline(always)] pub const fn p(&self) -> bool { @@ -2780,10 +493,10 @@ impl SeccfgIrq3 { self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize); } } -impl Default for SeccfgIrq3 { +impl Default for SeccfgIrq { #[inline(always)] - fn default() -> SeccfgIrq3 { - SeccfgIrq3(0) + fn default() -> SeccfgIrq { + SeccfgIrq(0) } } #[doc = "Miscellaneous security configuration"] @@ -2815,91 +528,33 @@ impl SeccfgMisc { } #[doc = "If 1, the TIMER0 register is only accessible from a Privileged (or more Secure) context, and timer DREQ 0 is only visible to Privileged (or more Secure) channels."] #[inline(always)] - pub const fn timer0_p(&self) -> bool { - let val = (self.0 >> 2usize) & 0x01; + pub const fn timer_p(&self, n: usize) -> bool { + assert!(n < 4usize); + let offs = 2usize + n * 2usize; + let val = (self.0 >> offs) & 0x01; val != 0 } #[doc = "If 1, the TIMER0 register is only accessible from a Privileged (or more Secure) context, and timer DREQ 0 is only visible to Privileged (or more Secure) channels."] #[inline(always)] - pub fn set_timer0_p(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 2usize)) | (((val as u32) & 0x01) << 2usize); + pub fn set_timer_p(&mut self, n: usize, val: bool) { + assert!(n < 4usize); + let offs = 2usize + n * 2usize; + self.0 = (self.0 & !(0x01 << offs)) | (((val as u32) & 0x01) << offs); } #[doc = "If 1, the TIMER0 register is only accessible from a Secure context, and timer DREQ 0 is only visible to Secure channels."] #[inline(always)] - pub const fn timer0_s(&self) -> bool { - let val = (self.0 >> 3usize) & 0x01; + pub const fn timer_s(&self, n: usize) -> bool { + assert!(n < 4usize); + let offs = 3usize + n * 2usize; + let val = (self.0 >> offs) & 0x01; val != 0 } #[doc = "If 1, the TIMER0 register is only accessible from a Secure context, and timer DREQ 0 is only visible to Secure channels."] #[inline(always)] - pub fn set_timer0_s(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 3usize)) | (((val as u32) & 0x01) << 3usize); - } - #[doc = "If 1, the TIMER1 register is only accessible from a Privileged (or more Secure) context, and timer DREQ 1 is only visible to Privileged (or more Secure) channels."] - #[inline(always)] - pub const fn timer1_p(&self) -> bool { - let val = (self.0 >> 4usize) & 0x01; - val != 0 - } - #[doc = "If 1, the TIMER1 register is only accessible from a Privileged (or more Secure) context, and timer DREQ 1 is only visible to Privileged (or more Secure) channels."] - #[inline(always)] - pub fn set_timer1_p(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 4usize)) | (((val as u32) & 0x01) << 4usize); - } - #[doc = "If 1, the TIMER1 register is only accessible from a Secure context, and timer DREQ 1 is only visible to Secure channels."] - #[inline(always)] - pub const fn timer1_s(&self) -> bool { - let val = (self.0 >> 5usize) & 0x01; - val != 0 - } - #[doc = "If 1, the TIMER1 register is only accessible from a Secure context, and timer DREQ 1 is only visible to Secure channels."] - #[inline(always)] - pub fn set_timer1_s(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 5usize)) | (((val as u32) & 0x01) << 5usize); - } - #[doc = "If 1, the TIMER2 register is only accessible from a Privileged (or more Secure) context, and timer DREQ 2 is only visible to Privileged (or more Secure) channels."] - #[inline(always)] - pub const fn timer2_p(&self) -> bool { - let val = (self.0 >> 6usize) & 0x01; - val != 0 - } - #[doc = "If 1, the TIMER2 register is only accessible from a Privileged (or more Secure) context, and timer DREQ 2 is only visible to Privileged (or more Secure) channels."] - #[inline(always)] - pub fn set_timer2_p(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 6usize)) | (((val as u32) & 0x01) << 6usize); - } - #[doc = "If 1, the TIMER2 register is only accessible from a Secure context, and timer DREQ 2 is only visible to Secure channels."] - #[inline(always)] - pub const fn timer2_s(&self) -> bool { - let val = (self.0 >> 7usize) & 0x01; - val != 0 - } - #[doc = "If 1, the TIMER2 register is only accessible from a Secure context, and timer DREQ 2 is only visible to Secure channels."] - #[inline(always)] - pub fn set_timer2_s(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 7usize)) | (((val as u32) & 0x01) << 7usize); - } - #[doc = "If 1, the TIMER3 register is only accessible from a Privileged (or more Secure) context, and timer DREQ 3 is only visible to Privileged (or more Secure) channels."] - #[inline(always)] - pub const fn timer3_p(&self) -> bool { - let val = (self.0 >> 8usize) & 0x01; - val != 0 - } - #[doc = "If 1, the TIMER3 register is only accessible from a Privileged (or more Secure) context, and timer DREQ 3 is only visible to Privileged (or more Secure) channels."] - #[inline(always)] - pub fn set_timer3_p(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 8usize)) | (((val as u32) & 0x01) << 8usize); - } - #[doc = "If 1, the TIMER3 register is only accessible from a Secure context, and timer DREQ 3 is only visible to Secure channels."] - #[inline(always)] - pub const fn timer3_s(&self) -> bool { - let val = (self.0 >> 9usize) & 0x01; - val != 0 - } - #[doc = "If 1, the TIMER3 register is only accessible from a Secure context, and timer DREQ 3 is only visible to Secure channels."] - #[inline(always)] - pub fn set_timer3_s(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 9usize)) | (((val as u32) & 0x01) << 9usize); + pub fn set_timer_s(&mut self, n: usize, val: bool) { + assert!(n < 4usize); + let offs = 3usize + n * 2usize; + self.0 = (self.0 & !(0x01 << offs)) | (((val as u32) & 0x01) << offs); } } impl Default for SeccfgMisc { diff --git a/src/rp235x/dma/vals.rs b/src/rp235x/dma/vals.rs index f655aa23..418a2b3f 100644 --- a/src/rp235x/dma/vals.rs +++ b/src/rp235x/dma/vals.rs @@ -2,7 +2,7 @@ #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] pub enum Calc { #[doc = "Calculate a CRC-32 (IEEE802.3 polynomial)"] - CRC32 = 0, + CRC32 = 0x0, #[doc = "Calculate a CRC-32 (IEEE802.3 polynomial) with bit reversed data"] CRC32R = 0x01, #[doc = "Calculate a CRC-16-CCITT"] @@ -48,638 +48,38 @@ impl From for u8 { } #[repr(u8)] #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] -pub enum Ch0transCountMode { - NORMAL = 0, - TRIGGER_SELF = 0x01, - _RESERVED_2 = 0x02, - _RESERVED_3 = 0x03, - _RESERVED_4 = 0x04, - _RESERVED_5 = 0x05, - _RESERVED_6 = 0x06, - _RESERVED_7 = 0x07, - _RESERVED_8 = 0x08, - _RESERVED_9 = 0x09, - _RESERVED_a = 0x0a, - _RESERVED_b = 0x0b, - _RESERVED_c = 0x0c, - _RESERVED_d = 0x0d, - _RESERVED_e = 0x0e, - ENDLESS = 0x0f, -} -impl Ch0transCountMode { - #[inline(always)] - pub const fn from_bits(val: u8) -> Ch0transCountMode { - unsafe { core::mem::transmute(val & 0x0f) } - } - #[inline(always)] - pub const fn to_bits(self) -> u8 { - unsafe { core::mem::transmute(self) } - } -} -impl From for Ch0transCountMode { - #[inline(always)] - fn from(val: u8) -> Ch0transCountMode { - Ch0transCountMode::from_bits(val) - } -} -impl From for u8 { - #[inline(always)] - fn from(val: Ch0transCountMode) -> u8 { - Ch0transCountMode::to_bits(val) - } -} -#[repr(u8)] -#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] -pub enum Ch10transCountMode { - NORMAL = 0, - TRIGGER_SELF = 0x01, - _RESERVED_2 = 0x02, - _RESERVED_3 = 0x03, - _RESERVED_4 = 0x04, - _RESERVED_5 = 0x05, - _RESERVED_6 = 0x06, - _RESERVED_7 = 0x07, - _RESERVED_8 = 0x08, - _RESERVED_9 = 0x09, - _RESERVED_a = 0x0a, - _RESERVED_b = 0x0b, - _RESERVED_c = 0x0c, - _RESERVED_d = 0x0d, - _RESERVED_e = 0x0e, - ENDLESS = 0x0f, -} -impl Ch10transCountMode { - #[inline(always)] - pub const fn from_bits(val: u8) -> Ch10transCountMode { - unsafe { core::mem::transmute(val & 0x0f) } - } - #[inline(always)] - pub const fn to_bits(self) -> u8 { - unsafe { core::mem::transmute(self) } - } -} -impl From for Ch10transCountMode { - #[inline(always)] - fn from(val: u8) -> Ch10transCountMode { - Ch10transCountMode::from_bits(val) - } -} -impl From for u8 { - #[inline(always)] - fn from(val: Ch10transCountMode) -> u8 { - Ch10transCountMode::to_bits(val) - } -} -#[repr(u8)] -#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] -pub enum Ch11transCountMode { - NORMAL = 0, - TRIGGER_SELF = 0x01, - _RESERVED_2 = 0x02, - _RESERVED_3 = 0x03, - _RESERVED_4 = 0x04, - _RESERVED_5 = 0x05, - _RESERVED_6 = 0x06, - _RESERVED_7 = 0x07, - _RESERVED_8 = 0x08, - _RESERVED_9 = 0x09, - _RESERVED_a = 0x0a, - _RESERVED_b = 0x0b, - _RESERVED_c = 0x0c, - _RESERVED_d = 0x0d, - _RESERVED_e = 0x0e, - ENDLESS = 0x0f, -} -impl Ch11transCountMode { - #[inline(always)] - pub const fn from_bits(val: u8) -> Ch11transCountMode { - unsafe { core::mem::transmute(val & 0x0f) } - } - #[inline(always)] - pub const fn to_bits(self) -> u8 { - unsafe { core::mem::transmute(self) } - } -} -impl From for Ch11transCountMode { - #[inline(always)] - fn from(val: u8) -> Ch11transCountMode { - Ch11transCountMode::from_bits(val) - } -} -impl From for u8 { - #[inline(always)] - fn from(val: Ch11transCountMode) -> u8 { - Ch11transCountMode::to_bits(val) - } -} -#[repr(u8)] -#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] -pub enum Ch12transCountMode { - NORMAL = 0, - TRIGGER_SELF = 0x01, - _RESERVED_2 = 0x02, - _RESERVED_3 = 0x03, - _RESERVED_4 = 0x04, - _RESERVED_5 = 0x05, - _RESERVED_6 = 0x06, - _RESERVED_7 = 0x07, - _RESERVED_8 = 0x08, - _RESERVED_9 = 0x09, - _RESERVED_a = 0x0a, - _RESERVED_b = 0x0b, - _RESERVED_c = 0x0c, - _RESERVED_d = 0x0d, - _RESERVED_e = 0x0e, - ENDLESS = 0x0f, -} -impl Ch12transCountMode { - #[inline(always)] - pub const fn from_bits(val: u8) -> Ch12transCountMode { - unsafe { core::mem::transmute(val & 0x0f) } - } - #[inline(always)] - pub const fn to_bits(self) -> u8 { - unsafe { core::mem::transmute(self) } - } -} -impl From for Ch12transCountMode { - #[inline(always)] - fn from(val: u8) -> Ch12transCountMode { - Ch12transCountMode::from_bits(val) - } -} -impl From for u8 { - #[inline(always)] - fn from(val: Ch12transCountMode) -> u8 { - Ch12transCountMode::to_bits(val) - } -} -#[repr(u8)] -#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] -pub enum Ch13transCountMode { - NORMAL = 0, - TRIGGER_SELF = 0x01, - _RESERVED_2 = 0x02, - _RESERVED_3 = 0x03, - _RESERVED_4 = 0x04, - _RESERVED_5 = 0x05, - _RESERVED_6 = 0x06, - _RESERVED_7 = 0x07, - _RESERVED_8 = 0x08, - _RESERVED_9 = 0x09, - _RESERVED_a = 0x0a, - _RESERVED_b = 0x0b, - _RESERVED_c = 0x0c, - _RESERVED_d = 0x0d, - _RESERVED_e = 0x0e, - ENDLESS = 0x0f, -} -impl Ch13transCountMode { - #[inline(always)] - pub const fn from_bits(val: u8) -> Ch13transCountMode { - unsafe { core::mem::transmute(val & 0x0f) } - } - #[inline(always)] - pub const fn to_bits(self) -> u8 { - unsafe { core::mem::transmute(self) } - } -} -impl From for Ch13transCountMode { - #[inline(always)] - fn from(val: u8) -> Ch13transCountMode { - Ch13transCountMode::from_bits(val) - } -} -impl From for u8 { - #[inline(always)] - fn from(val: Ch13transCountMode) -> u8 { - Ch13transCountMode::to_bits(val) - } -} -#[repr(u8)] -#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] -pub enum Ch14transCountMode { - NORMAL = 0, - TRIGGER_SELF = 0x01, - _RESERVED_2 = 0x02, - _RESERVED_3 = 0x03, - _RESERVED_4 = 0x04, - _RESERVED_5 = 0x05, - _RESERVED_6 = 0x06, - _RESERVED_7 = 0x07, - _RESERVED_8 = 0x08, - _RESERVED_9 = 0x09, - _RESERVED_a = 0x0a, - _RESERVED_b = 0x0b, - _RESERVED_c = 0x0c, - _RESERVED_d = 0x0d, - _RESERVED_e = 0x0e, - ENDLESS = 0x0f, -} -impl Ch14transCountMode { - #[inline(always)] - pub const fn from_bits(val: u8) -> Ch14transCountMode { - unsafe { core::mem::transmute(val & 0x0f) } - } - #[inline(always)] - pub const fn to_bits(self) -> u8 { - unsafe { core::mem::transmute(self) } - } -} -impl From for Ch14transCountMode { - #[inline(always)] - fn from(val: u8) -> Ch14transCountMode { - Ch14transCountMode::from_bits(val) - } -} -impl From for u8 { - #[inline(always)] - fn from(val: Ch14transCountMode) -> u8 { - Ch14transCountMode::to_bits(val) - } -} -#[repr(u8)] -#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] -pub enum Ch15transCountMode { - NORMAL = 0, - TRIGGER_SELF = 0x01, - _RESERVED_2 = 0x02, - _RESERVED_3 = 0x03, - _RESERVED_4 = 0x04, - _RESERVED_5 = 0x05, - _RESERVED_6 = 0x06, - _RESERVED_7 = 0x07, - _RESERVED_8 = 0x08, - _RESERVED_9 = 0x09, - _RESERVED_a = 0x0a, - _RESERVED_b = 0x0b, - _RESERVED_c = 0x0c, - _RESERVED_d = 0x0d, - _RESERVED_e = 0x0e, - ENDLESS = 0x0f, -} -impl Ch15transCountMode { - #[inline(always)] - pub const fn from_bits(val: u8) -> Ch15transCountMode { - unsafe { core::mem::transmute(val & 0x0f) } - } - #[inline(always)] - pub const fn to_bits(self) -> u8 { - unsafe { core::mem::transmute(self) } - } -} -impl From for Ch15transCountMode { - #[inline(always)] - fn from(val: u8) -> Ch15transCountMode { - Ch15transCountMode::from_bits(val) - } -} -impl From for u8 { - #[inline(always)] - fn from(val: Ch15transCountMode) -> u8 { - Ch15transCountMode::to_bits(val) - } -} -#[repr(u8)] -#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] -pub enum Ch1transCountMode { - NORMAL = 0, - TRIGGER_SELF = 0x01, - _RESERVED_2 = 0x02, - _RESERVED_3 = 0x03, - _RESERVED_4 = 0x04, - _RESERVED_5 = 0x05, - _RESERVED_6 = 0x06, - _RESERVED_7 = 0x07, - _RESERVED_8 = 0x08, - _RESERVED_9 = 0x09, - _RESERVED_a = 0x0a, - _RESERVED_b = 0x0b, - _RESERVED_c = 0x0c, - _RESERVED_d = 0x0d, - _RESERVED_e = 0x0e, - ENDLESS = 0x0f, -} -impl Ch1transCountMode { - #[inline(always)] - pub const fn from_bits(val: u8) -> Ch1transCountMode { - unsafe { core::mem::transmute(val & 0x0f) } - } - #[inline(always)] - pub const fn to_bits(self) -> u8 { - unsafe { core::mem::transmute(self) } - } -} -impl From for Ch1transCountMode { - #[inline(always)] - fn from(val: u8) -> Ch1transCountMode { - Ch1transCountMode::from_bits(val) - } -} -impl From for u8 { - #[inline(always)] - fn from(val: Ch1transCountMode) -> u8 { - Ch1transCountMode::to_bits(val) - } -} -#[repr(u8)] -#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] -pub enum Ch2transCountMode { - NORMAL = 0, - TRIGGER_SELF = 0x01, - _RESERVED_2 = 0x02, - _RESERVED_3 = 0x03, - _RESERVED_4 = 0x04, - _RESERVED_5 = 0x05, - _RESERVED_6 = 0x06, - _RESERVED_7 = 0x07, - _RESERVED_8 = 0x08, - _RESERVED_9 = 0x09, - _RESERVED_a = 0x0a, - _RESERVED_b = 0x0b, - _RESERVED_c = 0x0c, - _RESERVED_d = 0x0d, - _RESERVED_e = 0x0e, - ENDLESS = 0x0f, -} -impl Ch2transCountMode { - #[inline(always)] - pub const fn from_bits(val: u8) -> Ch2transCountMode { - unsafe { core::mem::transmute(val & 0x0f) } - } - #[inline(always)] - pub const fn to_bits(self) -> u8 { - unsafe { core::mem::transmute(self) } - } -} -impl From for Ch2transCountMode { - #[inline(always)] - fn from(val: u8) -> Ch2transCountMode { - Ch2transCountMode::from_bits(val) - } -} -impl From for u8 { - #[inline(always)] - fn from(val: Ch2transCountMode) -> u8 { - Ch2transCountMode::to_bits(val) - } -} -#[repr(u8)] -#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] -pub enum Ch3transCountMode { - NORMAL = 0, - TRIGGER_SELF = 0x01, - _RESERVED_2 = 0x02, - _RESERVED_3 = 0x03, - _RESERVED_4 = 0x04, - _RESERVED_5 = 0x05, - _RESERVED_6 = 0x06, - _RESERVED_7 = 0x07, - _RESERVED_8 = 0x08, - _RESERVED_9 = 0x09, - _RESERVED_a = 0x0a, - _RESERVED_b = 0x0b, - _RESERVED_c = 0x0c, - _RESERVED_d = 0x0d, - _RESERVED_e = 0x0e, - ENDLESS = 0x0f, -} -impl Ch3transCountMode { - #[inline(always)] - pub const fn from_bits(val: u8) -> Ch3transCountMode { - unsafe { core::mem::transmute(val & 0x0f) } - } - #[inline(always)] - pub const fn to_bits(self) -> u8 { - unsafe { core::mem::transmute(self) } - } -} -impl From for Ch3transCountMode { - #[inline(always)] - fn from(val: u8) -> Ch3transCountMode { - Ch3transCountMode::from_bits(val) - } -} -impl From for u8 { - #[inline(always)] - fn from(val: Ch3transCountMode) -> u8 { - Ch3transCountMode::to_bits(val) - } -} -#[repr(u8)] -#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] -pub enum Ch4transCountMode { - NORMAL = 0, - TRIGGER_SELF = 0x01, - _RESERVED_2 = 0x02, - _RESERVED_3 = 0x03, - _RESERVED_4 = 0x04, - _RESERVED_5 = 0x05, - _RESERVED_6 = 0x06, - _RESERVED_7 = 0x07, - _RESERVED_8 = 0x08, - _RESERVED_9 = 0x09, - _RESERVED_a = 0x0a, - _RESERVED_b = 0x0b, - _RESERVED_c = 0x0c, - _RESERVED_d = 0x0d, - _RESERVED_e = 0x0e, - ENDLESS = 0x0f, -} -impl Ch4transCountMode { - #[inline(always)] - pub const fn from_bits(val: u8) -> Ch4transCountMode { - unsafe { core::mem::transmute(val & 0x0f) } - } - #[inline(always)] - pub const fn to_bits(self) -> u8 { - unsafe { core::mem::transmute(self) } - } -} -impl From for Ch4transCountMode { - #[inline(always)] - fn from(val: u8) -> Ch4transCountMode { - Ch4transCountMode::from_bits(val) - } -} -impl From for u8 { - #[inline(always)] - fn from(val: Ch4transCountMode) -> u8 { - Ch4transCountMode::to_bits(val) - } -} -#[repr(u8)] -#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] -pub enum Ch5transCountMode { - NORMAL = 0, - TRIGGER_SELF = 0x01, - _RESERVED_2 = 0x02, - _RESERVED_3 = 0x03, - _RESERVED_4 = 0x04, - _RESERVED_5 = 0x05, - _RESERVED_6 = 0x06, - _RESERVED_7 = 0x07, - _RESERVED_8 = 0x08, - _RESERVED_9 = 0x09, - _RESERVED_a = 0x0a, - _RESERVED_b = 0x0b, - _RESERVED_c = 0x0c, - _RESERVED_d = 0x0d, - _RESERVED_e = 0x0e, - ENDLESS = 0x0f, -} -impl Ch5transCountMode { - #[inline(always)] - pub const fn from_bits(val: u8) -> Ch5transCountMode { - unsafe { core::mem::transmute(val & 0x0f) } - } - #[inline(always)] - pub const fn to_bits(self) -> u8 { - unsafe { core::mem::transmute(self) } - } -} -impl From for Ch5transCountMode { - #[inline(always)] - fn from(val: u8) -> Ch5transCountMode { - Ch5transCountMode::from_bits(val) - } -} -impl From for u8 { - #[inline(always)] - fn from(val: Ch5transCountMode) -> u8 { - Ch5transCountMode::to_bits(val) - } -} -#[repr(u8)] -#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] -pub enum Ch6transCountMode { - NORMAL = 0, - TRIGGER_SELF = 0x01, - _RESERVED_2 = 0x02, - _RESERVED_3 = 0x03, - _RESERVED_4 = 0x04, - _RESERVED_5 = 0x05, - _RESERVED_6 = 0x06, - _RESERVED_7 = 0x07, - _RESERVED_8 = 0x08, - _RESERVED_9 = 0x09, - _RESERVED_a = 0x0a, - _RESERVED_b = 0x0b, - _RESERVED_c = 0x0c, - _RESERVED_d = 0x0d, - _RESERVED_e = 0x0e, - ENDLESS = 0x0f, -} -impl Ch6transCountMode { - #[inline(always)] - pub const fn from_bits(val: u8) -> Ch6transCountMode { - unsafe { core::mem::transmute(val & 0x0f) } - } - #[inline(always)] - pub const fn to_bits(self) -> u8 { - unsafe { core::mem::transmute(self) } - } -} -impl From for Ch6transCountMode { - #[inline(always)] - fn from(val: u8) -> Ch6transCountMode { - Ch6transCountMode::from_bits(val) - } -} -impl From for u8 { - #[inline(always)] - fn from(val: Ch6transCountMode) -> u8 { - Ch6transCountMode::to_bits(val) - } -} -#[repr(u8)] -#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] -pub enum Ch7transCountMode { - NORMAL = 0, - TRIGGER_SELF = 0x01, - _RESERVED_2 = 0x02, - _RESERVED_3 = 0x03, - _RESERVED_4 = 0x04, - _RESERVED_5 = 0x05, - _RESERVED_6 = 0x06, - _RESERVED_7 = 0x07, - _RESERVED_8 = 0x08, - _RESERVED_9 = 0x09, - _RESERVED_a = 0x0a, - _RESERVED_b = 0x0b, - _RESERVED_c = 0x0c, - _RESERVED_d = 0x0d, - _RESERVED_e = 0x0e, - ENDLESS = 0x0f, -} -impl Ch7transCountMode { - #[inline(always)] - pub const fn from_bits(val: u8) -> Ch7transCountMode { - unsafe { core::mem::transmute(val & 0x0f) } - } - #[inline(always)] - pub const fn to_bits(self) -> u8 { - unsafe { core::mem::transmute(self) } - } -} -impl From for Ch7transCountMode { - #[inline(always)] - fn from(val: u8) -> Ch7transCountMode { - Ch7transCountMode::from_bits(val) - } -} -impl From for u8 { - #[inline(always)] - fn from(val: Ch7transCountMode) -> u8 { - Ch7transCountMode::to_bits(val) - } -} -#[repr(u8)] -#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] -pub enum Ch8transCountMode { - NORMAL = 0, - TRIGGER_SELF = 0x01, - _RESERVED_2 = 0x02, +pub enum DataSize { + SIZE_BYTE = 0x0, + SIZE_HALFWORD = 0x01, + SIZE_WORD = 0x02, _RESERVED_3 = 0x03, - _RESERVED_4 = 0x04, - _RESERVED_5 = 0x05, - _RESERVED_6 = 0x06, - _RESERVED_7 = 0x07, - _RESERVED_8 = 0x08, - _RESERVED_9 = 0x09, - _RESERVED_a = 0x0a, - _RESERVED_b = 0x0b, - _RESERVED_c = 0x0c, - _RESERVED_d = 0x0d, - _RESERVED_e = 0x0e, - ENDLESS = 0x0f, } -impl Ch8transCountMode { +impl DataSize { #[inline(always)] - pub const fn from_bits(val: u8) -> Ch8transCountMode { - unsafe { core::mem::transmute(val & 0x0f) } + pub const fn from_bits(val: u8) -> DataSize { + unsafe { core::mem::transmute(val & 0x03) } } #[inline(always)] pub const fn to_bits(self) -> u8 { unsafe { core::mem::transmute(self) } } } -impl From for Ch8transCountMode { +impl From for DataSize { #[inline(always)] - fn from(val: u8) -> Ch8transCountMode { - Ch8transCountMode::from_bits(val) + fn from(val: u8) -> DataSize { + DataSize::from_bits(val) } } -impl From for u8 { +impl From for u8 { #[inline(always)] - fn from(val: Ch8transCountMode) -> u8 { - Ch8transCountMode::to_bits(val) + fn from(val: DataSize) -> u8 { + DataSize::to_bits(val) } } #[repr(u8)] #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] -pub enum Ch9transCountMode { - NORMAL = 0, +pub enum TransCountMode { + NORMAL = 0x0, TRIGGER_SELF = 0x01, _RESERVED_2 = 0x02, _RESERVED_3 = 0x03, @@ -696,9 +96,9 @@ pub enum Ch9transCountMode { _RESERVED_e = 0x0e, ENDLESS = 0x0f, } -impl Ch9transCountMode { +impl TransCountMode { #[inline(always)] - pub const fn from_bits(val: u8) -> Ch9transCountMode { + pub const fn from_bits(val: u8) -> TransCountMode { unsafe { core::mem::transmute(val & 0x0f) } } #[inline(always)] @@ -706,53 +106,23 @@ impl Ch9transCountMode { unsafe { core::mem::transmute(self) } } } -impl From for Ch9transCountMode { - #[inline(always)] - fn from(val: u8) -> Ch9transCountMode { - Ch9transCountMode::from_bits(val) - } -} -impl From for u8 { +impl From for TransCountMode { #[inline(always)] - fn from(val: Ch9transCountMode) -> u8 { - Ch9transCountMode::to_bits(val) + fn from(val: u8) -> TransCountMode { + TransCountMode::from_bits(val) } } -#[repr(u8)] -#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] -pub enum DataSize { - SIZE_BYTE = 0, - SIZE_HALFWORD = 0x01, - SIZE_WORD = 0x02, - _RESERVED_3 = 0x03, -} -impl DataSize { +impl From for u8 { #[inline(always)] - pub const fn from_bits(val: u8) -> DataSize { - unsafe { core::mem::transmute(val & 0x03) } - } - #[inline(always)] - pub const fn to_bits(self) -> u8 { - unsafe { core::mem::transmute(self) } - } -} -impl From for DataSize { - #[inline(always)] - fn from(val: u8) -> DataSize { - DataSize::from_bits(val) - } -} -impl From for u8 { - #[inline(always)] - fn from(val: DataSize) -> u8 { - DataSize::to_bits(val) + fn from(val: TransCountMode) -> u8 { + TransCountMode::to_bits(val) } } #[repr(u8)] #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] pub enum TreqSel { #[doc = "Select PIO0's TX FIFO 0 as TREQ"] - PIO0_TX0 = 0, + PIO0_TX0 = 0x0, #[doc = "Select PIO0's TX FIFO 1 as TREQ"] PIO0_TX1 = 0x01, #[doc = "Select PIO0's TX FIFO 2 as TREQ"] diff --git a/src/rp235x/eppb.rs b/src/rp235x/eppb.rs index cfca571c..748878c8 100644 --- a/src/rp235x/eppb.rs +++ b/src/rp235x/eppb.rs @@ -17,17 +17,17 @@ impl Eppb { #[doc = "NMI mask for IRQs 0 through 31. This register is core-local, and is reset by a processor warm reset."] #[inline(always)] pub const fn nmi_mask0(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(0usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x0usize) as _) } } #[doc = "NMI mask for IRQs 0 though 51. This register is core-local, and is reset by a processor warm reset."] #[inline(always)] pub const fn nmi_mask1(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(4usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x04usize) as _) } } #[doc = "Nonstandard sleep control register"] #[inline(always)] pub const fn sleepctrl(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(8usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x08usize) as _) } } } pub mod regs; diff --git a/src/rp235x/glitch_detector.rs b/src/rp235x/glitch_detector.rs index 7508e406..daf1663b 100644 --- a/src/rp235x/glitch_detector.rs +++ b/src/rp235x/glitch_detector.rs @@ -17,30 +17,30 @@ impl GlitchDetector { #[doc = "Forcibly arm the glitch detectors, if they are not already armed by OTP. When armed, any individual detector trigger will cause a restart of the switched core power domain's power-on reset state machine. Glitch detector triggers are recorded accumulatively in TRIG_STATUS. If the system is reset by a glitch detector trigger, this is recorded in POWMAN_CHIP_RESET. This register is Secure read/write only."] #[inline(always)] pub const fn arm(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(0usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x0usize) as _) } } #[inline(always)] pub const fn disarm(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(4usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x04usize) as _) } } #[doc = "Adjust the sensitivity of glitch detectors to values other than their OTP-provided defaults. This register is Secure read/write only."] #[inline(always)] pub const fn sensitivity(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(8usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x08usize) as _) } } #[inline(always)] pub const fn lock(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(12usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x0cusize) as _) } } #[doc = "Set when a detector output triggers. Write-1-clear. (May immediately return high if the detector remains in a failed state. Detectors can only be cleared by a full reset of the switched core power domain.) This register is Secure read/write only."] #[inline(always)] pub const fn trig_status(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(16usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x10usize) as _) } } #[doc = "Simulate the firing of one or more detectors. Writing ones to this register will set the matching bits in STATUS_TRIG. If the glitch detectors are currently armed, writing ones will also immediately reset the switched core power domain, and set the reset reason latches in POWMAN_CHIP_RESET to indicate a glitch detector resets. This register is Secure read/write only."] #[inline(always)] pub const fn trig_force(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(20usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x14usize) as _) } } } pub mod regs; diff --git a/src/rp235x/glitch_detector/vals.rs b/src/rp235x/glitch_detector/vals.rs index 244acffc..0602db4d 100644 --- a/src/rp235x/glitch_detector/vals.rs +++ b/src/rp235x/glitch_detector/vals.rs @@ -3,7 +3,7 @@ pub struct Arm(pub u16); impl Arm { #[doc = "Force the glitch detectors to be armed. (Any value other than ARM_NO counts as YES)"] - pub const YES: Self = Self(0); + pub const YES: Self = Self(0x0); #[doc = "Do not force the glitch detectors to be armed"] pub const NO: Self = Self(0x5bad); } @@ -32,7 +32,7 @@ impl From for u16 { pub struct Default(pub u8); impl Default { #[doc = "Use the default sensitivity configured in OTP for all detectors. (Any value other than DEFAULT_NO counts as YES)"] - pub const YES: Self = Self(0); + pub const YES: Self = Self(0x0); #[doc = "Do not use the default sensitivity configured in OTP. Instead use the value from this register."] pub const NO: Self = Self(0xde); } @@ -61,7 +61,7 @@ impl From for u8 { pub struct Disarm(pub u16); impl Disarm { #[doc = "Do not disarm the glitch detectors. (Any value other than DISARM_YES counts as NO)"] - pub const NO: Self = Self(0); + pub const NO: Self = Self(0x0); #[doc = "Disarm the glitch detectors"] pub const YES: Self = Self(0xdcaf); } diff --git a/src/rp235x/hstx_ctrl.rs b/src/rp235x/hstx_ctrl.rs index f24d2caf..f47cf415 100644 --- a/src/rp235x/hstx_ctrl.rs +++ b/src/rp235x/hstx_ctrl.rs @@ -16,57 +16,23 @@ impl HstxCtrl { } #[inline(always)] pub const fn csr(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(0usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x0usize) as _) } } #[doc = "Data control register for output bit 0"] #[inline(always)] - pub const fn bit0(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(4usize) as _) } - } - #[doc = "Data control register for output bit 1"] - #[inline(always)] - pub const fn bit1(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(8usize) as _) } - } - #[doc = "Data control register for output bit 2"] - #[inline(always)] - pub const fn bit2(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(12usize) as _) } - } - #[doc = "Data control register for output bit 3"] - #[inline(always)] - pub const fn bit3(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(16usize) as _) } - } - #[doc = "Data control register for output bit 4"] - #[inline(always)] - pub const fn bit4(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(20usize) as _) } - } - #[doc = "Data control register for output bit 5"] - #[inline(always)] - pub const fn bit5(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(24usize) as _) } - } - #[doc = "Data control register for output bit 6"] - #[inline(always)] - pub const fn bit6(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(28usize) as _) } - } - #[doc = "Data control register for output bit 7"] - #[inline(always)] - pub const fn bit7(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(32usize) as _) } + pub const fn bit_(self, n: usize) -> crate::common::Reg { + assert!(n < 8usize); + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x04usize + n * 4usize) as _) } } #[doc = "Configure the optional shifter inside the command expander"] #[inline(always)] pub const fn expand_shift(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(36usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x24usize) as _) } } #[doc = "Configure the optional TMDS encoder inside the command expander"] #[inline(always)] pub const fn expand_tmds(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(40usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x28usize) as _) } } } pub mod regs; diff --git a/src/rp235x/hstx_ctrl/regs.rs b/src/rp235x/hstx_ctrl/regs.rs index 19e4a0bb..499c2440 100644 --- a/src/rp235x/hstx_ctrl/regs.rs +++ b/src/rp235x/hstx_ctrl/regs.rs @@ -1,400 +1,8 @@ -#[doc = "Data control register for output bit 0"] -#[repr(transparent)] -#[derive(Copy, Clone, Eq, PartialEq)] -pub struct Bit0(pub u32); -impl Bit0 { - #[doc = "Shift register data bit select for the first half of the HSTX clock cycle"] - #[inline(always)] - pub const fn sel_p(&self) -> u8 { - let val = (self.0 >> 0usize) & 0x1f; - val as u8 - } - #[doc = "Shift register data bit select for the first half of the HSTX clock cycle"] - #[inline(always)] - pub fn set_sel_p(&mut self, val: u8) { - self.0 = (self.0 & !(0x1f << 0usize)) | (((val as u32) & 0x1f) << 0usize); - } - #[doc = "Shift register data bit select for the second half of the HSTX clock cycle"] - #[inline(always)] - pub const fn sel_n(&self) -> u8 { - let val = (self.0 >> 8usize) & 0x1f; - val as u8 - } - #[doc = "Shift register data bit select for the second half of the HSTX clock cycle"] - #[inline(always)] - pub fn set_sel_n(&mut self, val: u8) { - self.0 = (self.0 & !(0x1f << 8usize)) | (((val as u32) & 0x1f) << 8usize); - } - #[doc = "Invert this data output (logical NOT)"] - #[inline(always)] - pub const fn inv(&self) -> bool { - let val = (self.0 >> 16usize) & 0x01; - val != 0 - } - #[doc = "Invert this data output (logical NOT)"] - #[inline(always)] - pub fn set_inv(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 16usize)) | (((val as u32) & 0x01) << 16usize); - } - #[doc = "Connect this output to the generated clock, rather than the data shift register. SEL_P and SEL_N are ignored if this bit is set, but INV can still be set to generate an antiphase clock."] - #[inline(always)] - pub const fn clk(&self) -> bool { - let val = (self.0 >> 17usize) & 0x01; - val != 0 - } - #[doc = "Connect this output to the generated clock, rather than the data shift register. SEL_P and SEL_N are ignored if this bit is set, but INV can still be set to generate an antiphase clock."] - #[inline(always)] - pub fn set_clk(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 17usize)) | (((val as u32) & 0x01) << 17usize); - } -} -impl Default for Bit0 { - #[inline(always)] - fn default() -> Bit0 { - Bit0(0) - } -} -#[doc = "Data control register for output bit 1"] -#[repr(transparent)] -#[derive(Copy, Clone, Eq, PartialEq)] -pub struct Bit1(pub u32); -impl Bit1 { - #[doc = "Shift register data bit select for the first half of the HSTX clock cycle"] - #[inline(always)] - pub const fn sel_p(&self) -> u8 { - let val = (self.0 >> 0usize) & 0x1f; - val as u8 - } - #[doc = "Shift register data bit select for the first half of the HSTX clock cycle"] - #[inline(always)] - pub fn set_sel_p(&mut self, val: u8) { - self.0 = (self.0 & !(0x1f << 0usize)) | (((val as u32) & 0x1f) << 0usize); - } - #[doc = "Shift register data bit select for the second half of the HSTX clock cycle"] - #[inline(always)] - pub const fn sel_n(&self) -> u8 { - let val = (self.0 >> 8usize) & 0x1f; - val as u8 - } - #[doc = "Shift register data bit select for the second half of the HSTX clock cycle"] - #[inline(always)] - pub fn set_sel_n(&mut self, val: u8) { - self.0 = (self.0 & !(0x1f << 8usize)) | (((val as u32) & 0x1f) << 8usize); - } - #[doc = "Invert this data output (logical NOT)"] - #[inline(always)] - pub const fn inv(&self) -> bool { - let val = (self.0 >> 16usize) & 0x01; - val != 0 - } - #[doc = "Invert this data output (logical NOT)"] - #[inline(always)] - pub fn set_inv(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 16usize)) | (((val as u32) & 0x01) << 16usize); - } - #[doc = "Connect this output to the generated clock, rather than the data shift register. SEL_P and SEL_N are ignored if this bit is set, but INV can still be set to generate an antiphase clock."] - #[inline(always)] - pub const fn clk(&self) -> bool { - let val = (self.0 >> 17usize) & 0x01; - val != 0 - } - #[doc = "Connect this output to the generated clock, rather than the data shift register. SEL_P and SEL_N are ignored if this bit is set, but INV can still be set to generate an antiphase clock."] - #[inline(always)] - pub fn set_clk(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 17usize)) | (((val as u32) & 0x01) << 17usize); - } -} -impl Default for Bit1 { - #[inline(always)] - fn default() -> Bit1 { - Bit1(0) - } -} -#[doc = "Data control register for output bit 2"] -#[repr(transparent)] -#[derive(Copy, Clone, Eq, PartialEq)] -pub struct Bit2(pub u32); -impl Bit2 { - #[doc = "Shift register data bit select for the first half of the HSTX clock cycle"] - #[inline(always)] - pub const fn sel_p(&self) -> u8 { - let val = (self.0 >> 0usize) & 0x1f; - val as u8 - } - #[doc = "Shift register data bit select for the first half of the HSTX clock cycle"] - #[inline(always)] - pub fn set_sel_p(&mut self, val: u8) { - self.0 = (self.0 & !(0x1f << 0usize)) | (((val as u32) & 0x1f) << 0usize); - } - #[doc = "Shift register data bit select for the second half of the HSTX clock cycle"] - #[inline(always)] - pub const fn sel_n(&self) -> u8 { - let val = (self.0 >> 8usize) & 0x1f; - val as u8 - } - #[doc = "Shift register data bit select for the second half of the HSTX clock cycle"] - #[inline(always)] - pub fn set_sel_n(&mut self, val: u8) { - self.0 = (self.0 & !(0x1f << 8usize)) | (((val as u32) & 0x1f) << 8usize); - } - #[doc = "Invert this data output (logical NOT)"] - #[inline(always)] - pub const fn inv(&self) -> bool { - let val = (self.0 >> 16usize) & 0x01; - val != 0 - } - #[doc = "Invert this data output (logical NOT)"] - #[inline(always)] - pub fn set_inv(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 16usize)) | (((val as u32) & 0x01) << 16usize); - } - #[doc = "Connect this output to the generated clock, rather than the data shift register. SEL_P and SEL_N are ignored if this bit is set, but INV can still be set to generate an antiphase clock."] - #[inline(always)] - pub const fn clk(&self) -> bool { - let val = (self.0 >> 17usize) & 0x01; - val != 0 - } - #[doc = "Connect this output to the generated clock, rather than the data shift register. SEL_P and SEL_N are ignored if this bit is set, but INV can still be set to generate an antiphase clock."] - #[inline(always)] - pub fn set_clk(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 17usize)) | (((val as u32) & 0x01) << 17usize); - } -} -impl Default for Bit2 { - #[inline(always)] - fn default() -> Bit2 { - Bit2(0) - } -} -#[doc = "Data control register for output bit 3"] -#[repr(transparent)] -#[derive(Copy, Clone, Eq, PartialEq)] -pub struct Bit3(pub u32); -impl Bit3 { - #[doc = "Shift register data bit select for the first half of the HSTX clock cycle"] - #[inline(always)] - pub const fn sel_p(&self) -> u8 { - let val = (self.0 >> 0usize) & 0x1f; - val as u8 - } - #[doc = "Shift register data bit select for the first half of the HSTX clock cycle"] - #[inline(always)] - pub fn set_sel_p(&mut self, val: u8) { - self.0 = (self.0 & !(0x1f << 0usize)) | (((val as u32) & 0x1f) << 0usize); - } - #[doc = "Shift register data bit select for the second half of the HSTX clock cycle"] - #[inline(always)] - pub const fn sel_n(&self) -> u8 { - let val = (self.0 >> 8usize) & 0x1f; - val as u8 - } - #[doc = "Shift register data bit select for the second half of the HSTX clock cycle"] - #[inline(always)] - pub fn set_sel_n(&mut self, val: u8) { - self.0 = (self.0 & !(0x1f << 8usize)) | (((val as u32) & 0x1f) << 8usize); - } - #[doc = "Invert this data output (logical NOT)"] - #[inline(always)] - pub const fn inv(&self) -> bool { - let val = (self.0 >> 16usize) & 0x01; - val != 0 - } - #[doc = "Invert this data output (logical NOT)"] - #[inline(always)] - pub fn set_inv(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 16usize)) | (((val as u32) & 0x01) << 16usize); - } - #[doc = "Connect this output to the generated clock, rather than the data shift register. SEL_P and SEL_N are ignored if this bit is set, but INV can still be set to generate an antiphase clock."] - #[inline(always)] - pub const fn clk(&self) -> bool { - let val = (self.0 >> 17usize) & 0x01; - val != 0 - } - #[doc = "Connect this output to the generated clock, rather than the data shift register. SEL_P and SEL_N are ignored if this bit is set, but INV can still be set to generate an antiphase clock."] - #[inline(always)] - pub fn set_clk(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 17usize)) | (((val as u32) & 0x01) << 17usize); - } -} -impl Default for Bit3 { - #[inline(always)] - fn default() -> Bit3 { - Bit3(0) - } -} -#[doc = "Data control register for output bit 4"] -#[repr(transparent)] -#[derive(Copy, Clone, Eq, PartialEq)] -pub struct Bit4(pub u32); -impl Bit4 { - #[doc = "Shift register data bit select for the first half of the HSTX clock cycle"] - #[inline(always)] - pub const fn sel_p(&self) -> u8 { - let val = (self.0 >> 0usize) & 0x1f; - val as u8 - } - #[doc = "Shift register data bit select for the first half of the HSTX clock cycle"] - #[inline(always)] - pub fn set_sel_p(&mut self, val: u8) { - self.0 = (self.0 & !(0x1f << 0usize)) | (((val as u32) & 0x1f) << 0usize); - } - #[doc = "Shift register data bit select for the second half of the HSTX clock cycle"] - #[inline(always)] - pub const fn sel_n(&self) -> u8 { - let val = (self.0 >> 8usize) & 0x1f; - val as u8 - } - #[doc = "Shift register data bit select for the second half of the HSTX clock cycle"] - #[inline(always)] - pub fn set_sel_n(&mut self, val: u8) { - self.0 = (self.0 & !(0x1f << 8usize)) | (((val as u32) & 0x1f) << 8usize); - } - #[doc = "Invert this data output (logical NOT)"] - #[inline(always)] - pub const fn inv(&self) -> bool { - let val = (self.0 >> 16usize) & 0x01; - val != 0 - } - #[doc = "Invert this data output (logical NOT)"] - #[inline(always)] - pub fn set_inv(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 16usize)) | (((val as u32) & 0x01) << 16usize); - } - #[doc = "Connect this output to the generated clock, rather than the data shift register. SEL_P and SEL_N are ignored if this bit is set, but INV can still be set to generate an antiphase clock."] - #[inline(always)] - pub const fn clk(&self) -> bool { - let val = (self.0 >> 17usize) & 0x01; - val != 0 - } - #[doc = "Connect this output to the generated clock, rather than the data shift register. SEL_P and SEL_N are ignored if this bit is set, but INV can still be set to generate an antiphase clock."] - #[inline(always)] - pub fn set_clk(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 17usize)) | (((val as u32) & 0x01) << 17usize); - } -} -impl Default for Bit4 { - #[inline(always)] - fn default() -> Bit4 { - Bit4(0) - } -} -#[doc = "Data control register for output bit 5"] -#[repr(transparent)] -#[derive(Copy, Clone, Eq, PartialEq)] -pub struct Bit5(pub u32); -impl Bit5 { - #[doc = "Shift register data bit select for the first half of the HSTX clock cycle"] - #[inline(always)] - pub const fn sel_p(&self) -> u8 { - let val = (self.0 >> 0usize) & 0x1f; - val as u8 - } - #[doc = "Shift register data bit select for the first half of the HSTX clock cycle"] - #[inline(always)] - pub fn set_sel_p(&mut self, val: u8) { - self.0 = (self.0 & !(0x1f << 0usize)) | (((val as u32) & 0x1f) << 0usize); - } - #[doc = "Shift register data bit select for the second half of the HSTX clock cycle"] - #[inline(always)] - pub const fn sel_n(&self) -> u8 { - let val = (self.0 >> 8usize) & 0x1f; - val as u8 - } - #[doc = "Shift register data bit select for the second half of the HSTX clock cycle"] - #[inline(always)] - pub fn set_sel_n(&mut self, val: u8) { - self.0 = (self.0 & !(0x1f << 8usize)) | (((val as u32) & 0x1f) << 8usize); - } - #[doc = "Invert this data output (logical NOT)"] - #[inline(always)] - pub const fn inv(&self) -> bool { - let val = (self.0 >> 16usize) & 0x01; - val != 0 - } - #[doc = "Invert this data output (logical NOT)"] - #[inline(always)] - pub fn set_inv(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 16usize)) | (((val as u32) & 0x01) << 16usize); - } - #[doc = "Connect this output to the generated clock, rather than the data shift register. SEL_P and SEL_N are ignored if this bit is set, but INV can still be set to generate an antiphase clock."] - #[inline(always)] - pub const fn clk(&self) -> bool { - let val = (self.0 >> 17usize) & 0x01; - val != 0 - } - #[doc = "Connect this output to the generated clock, rather than the data shift register. SEL_P and SEL_N are ignored if this bit is set, but INV can still be set to generate an antiphase clock."] - #[inline(always)] - pub fn set_clk(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 17usize)) | (((val as u32) & 0x01) << 17usize); - } -} -impl Default for Bit5 { - #[inline(always)] - fn default() -> Bit5 { - Bit5(0) - } -} -#[doc = "Data control register for output bit 6"] -#[repr(transparent)] -#[derive(Copy, Clone, Eq, PartialEq)] -pub struct Bit6(pub u32); -impl Bit6 { - #[doc = "Shift register data bit select for the first half of the HSTX clock cycle"] - #[inline(always)] - pub const fn sel_p(&self) -> u8 { - let val = (self.0 >> 0usize) & 0x1f; - val as u8 - } - #[doc = "Shift register data bit select for the first half of the HSTX clock cycle"] - #[inline(always)] - pub fn set_sel_p(&mut self, val: u8) { - self.0 = (self.0 & !(0x1f << 0usize)) | (((val as u32) & 0x1f) << 0usize); - } - #[doc = "Shift register data bit select for the second half of the HSTX clock cycle"] - #[inline(always)] - pub const fn sel_n(&self) -> u8 { - let val = (self.0 >> 8usize) & 0x1f; - val as u8 - } - #[doc = "Shift register data bit select for the second half of the HSTX clock cycle"] - #[inline(always)] - pub fn set_sel_n(&mut self, val: u8) { - self.0 = (self.0 & !(0x1f << 8usize)) | (((val as u32) & 0x1f) << 8usize); - } - #[doc = "Invert this data output (logical NOT)"] - #[inline(always)] - pub const fn inv(&self) -> bool { - let val = (self.0 >> 16usize) & 0x01; - val != 0 - } - #[doc = "Invert this data output (logical NOT)"] - #[inline(always)] - pub fn set_inv(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 16usize)) | (((val as u32) & 0x01) << 16usize); - } - #[doc = "Connect this output to the generated clock, rather than the data shift register. SEL_P and SEL_N are ignored if this bit is set, but INV can still be set to generate an antiphase clock."] - #[inline(always)] - pub const fn clk(&self) -> bool { - let val = (self.0 >> 17usize) & 0x01; - val != 0 - } - #[doc = "Connect this output to the generated clock, rather than the data shift register. SEL_P and SEL_N are ignored if this bit is set, but INV can still be set to generate an antiphase clock."] - #[inline(always)] - pub fn set_clk(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 17usize)) | (((val as u32) & 0x01) << 17usize); - } -} -impl Default for Bit6 { - #[inline(always)] - fn default() -> Bit6 { - Bit6(0) - } -} #[doc = "Data control register for output bit 7"] #[repr(transparent)] #[derive(Copy, Clone, Eq, PartialEq)] -pub struct Bit7(pub u32); -impl Bit7 { +pub struct Bit(pub u32); +impl Bit { #[doc = "Shift register data bit select for the first half of the HSTX clock cycle"] #[inline(always)] pub const fn sel_p(&self) -> u8 { @@ -440,10 +48,10 @@ impl Bit7 { self.0 = (self.0 & !(0x01 << 17usize)) | (((val as u32) & 0x01) << 17usize); } } -impl Default for Bit7 { +impl Default for Bit { #[inline(always)] - fn default() -> Bit7 { - Bit7(0) + fn default() -> Bit { + Bit(0) } } #[repr(transparent)] diff --git a/src/rp235x/hstx_fifo.rs b/src/rp235x/hstx_fifo.rs index c7108751..eca99dfa 100644 --- a/src/rp235x/hstx_fifo.rs +++ b/src/rp235x/hstx_fifo.rs @@ -17,12 +17,12 @@ impl HstxFifo { #[doc = "FIFO status"] #[inline(always)] pub const fn stat(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(0usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x0usize) as _) } } #[doc = "Write access to FIFO"] #[inline(always)] pub const fn fifo(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(4usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x04usize) as _) } } } pub mod regs; diff --git a/src/rp235x/i2c.rs b/src/rp235x/i2c.rs index c752f5d1..1580aa4b 100644 --- a/src/rp235x/i2c.rs +++ b/src/rp235x/i2c.rs @@ -17,236 +17,236 @@ impl I2c { #[doc = "I2C Control Register. This register can be written only when the DW_apb_i2c is disabled, which corresponds to the IC_ENABLE\\[0\\] register being set to 0. Writes at other times have no effect. Read/Write Access: - bit 10 is read only. - bit 11 is read only - bit 16 is read only - bit 17 is read only - bits 18 and 19 are read only."] #[inline(always)] pub const fn ic_con(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(0usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x0usize) as _) } } #[doc = "I2C Target Address Register This register is 12 bits wide, and bits 31:12 are reserved. This register can be written to only when IC_ENABLE\\[0\\] is set to 0. Note: If the software or application is aware that the DW_apb_i2c is not using the TAR address for the pending commands in the Tx FIFO, then it is possible to update the TAR address even while the Tx FIFO has entries (IC_STATUS\\[2\\]= 0). - It is not necessary to perform any write to this register if DW_apb_i2c is enabled as an I2C slave only."] #[inline(always)] pub const fn ic_tar(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(4usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x04usize) as _) } } #[doc = "I2C Slave Address Register"] #[inline(always)] pub const fn ic_sar(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(8usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x08usize) as _) } } #[doc = "I2C Rx/Tx Data Buffer and Command Register; this is the register the CPU writes to when filling the TX FIFO and the CPU reads from when retrieving bytes from RX FIFO. The size of the register changes as follows: Write: - 11 bits when IC_EMPTYFIFO_HOLD_MASTER_EN=1 - 9 bits when IC_EMPTYFIFO_HOLD_MASTER_EN=0 Read: - 12 bits when IC_FIRST_DATA_BYTE_STATUS = 1 - 8 bits when IC_FIRST_DATA_BYTE_STATUS = 0 Note: In order for the DW_apb_i2c to continue acknowledging reads, a read command should be written for every byte that is to be received; otherwise the DW_apb_i2c will stop acknowledging."] #[inline(always)] pub const fn ic_data_cmd(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(16usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x10usize) as _) } } #[doc = "Standard Speed I2C Clock SCL High Count Register"] #[inline(always)] pub const fn ic_ss_scl_hcnt(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(20usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x14usize) as _) } } #[doc = "Standard Speed I2C Clock SCL Low Count Register"] #[inline(always)] pub const fn ic_ss_scl_lcnt(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(24usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x18usize) as _) } } #[doc = "Fast Mode or Fast Mode Plus I2C Clock SCL High Count Register"] #[inline(always)] pub const fn ic_fs_scl_hcnt(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(28usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x1cusize) as _) } } #[doc = "Fast Mode or Fast Mode Plus I2C Clock SCL Low Count Register"] #[inline(always)] pub const fn ic_fs_scl_lcnt(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(32usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x20usize) as _) } } #[doc = "I2C Interrupt Status Register Each bit in this register has a corresponding mask bit in the IC_INTR_MASK register. These bits are cleared by reading the matching interrupt clear register. The unmasked raw versions of these bits are available in the IC_RAW_INTR_STAT register."] #[inline(always)] pub const fn ic_intr_stat(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(44usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x2cusize) as _) } } #[doc = "I2C Interrupt Mask Register. These bits mask their corresponding interrupt status bits. This register is active low; a value of 0 masks the interrupt, whereas a value of 1 unmasks the interrupt."] #[inline(always)] pub const fn ic_intr_mask(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(48usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x30usize) as _) } } #[doc = "I2C Raw Interrupt Status Register Unlike the IC_INTR_STAT register, these bits are not masked so they always show the true status of the DW_apb_i2c."] #[inline(always)] pub const fn ic_raw_intr_stat( self, ) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(52usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x34usize) as _) } } #[doc = "I2C Receive FIFO Threshold Register"] #[inline(always)] pub const fn ic_rx_tl(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(56usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x38usize) as _) } } #[doc = "I2C Transmit FIFO Threshold Register"] #[inline(always)] pub const fn ic_tx_tl(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(60usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x3cusize) as _) } } #[doc = "Clear Combined and Individual Interrupt Register"] #[inline(always)] pub const fn ic_clr_intr(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(64usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x40usize) as _) } } #[doc = "Clear RX_UNDER Interrupt Register"] #[inline(always)] pub const fn ic_clr_rx_under( self, ) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(68usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x44usize) as _) } } #[doc = "Clear RX_OVER Interrupt Register"] #[inline(always)] pub const fn ic_clr_rx_over(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(72usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x48usize) as _) } } #[doc = "Clear TX_OVER Interrupt Register"] #[inline(always)] pub const fn ic_clr_tx_over(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(76usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x4cusize) as _) } } #[doc = "Clear RD_REQ Interrupt Register"] #[inline(always)] pub const fn ic_clr_rd_req(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(80usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x50usize) as _) } } #[doc = "Clear TX_ABRT Interrupt Register"] #[inline(always)] pub const fn ic_clr_tx_abrt(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(84usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x54usize) as _) } } #[doc = "Clear RX_DONE Interrupt Register"] #[inline(always)] pub const fn ic_clr_rx_done(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(88usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x58usize) as _) } } #[doc = "Clear ACTIVITY Interrupt Register"] #[inline(always)] pub const fn ic_clr_activity( self, ) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(92usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x5cusize) as _) } } #[doc = "Clear STOP_DET Interrupt Register"] #[inline(always)] pub const fn ic_clr_stop_det( self, ) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(96usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x60usize) as _) } } #[doc = "Clear START_DET Interrupt Register"] #[inline(always)] pub const fn ic_clr_start_det( self, ) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(100usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x64usize) as _) } } #[doc = "Clear GEN_CALL Interrupt Register"] #[inline(always)] pub const fn ic_clr_gen_call( self, ) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(104usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x68usize) as _) } } #[doc = "I2C Enable Register"] #[inline(always)] pub const fn ic_enable(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(108usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x6cusize) as _) } } #[doc = "I2C Status Register This is a read-only register used to indicate the current transfer status and FIFO status. The status register may be read at any time. None of the bits in this register request an interrupt. When the I2C is disabled by writing 0 in bit 0 of the IC_ENABLE register: - Bits 1 and 2 are set to 1 - Bits 3 and 10 are set to 0 When the master or slave state machines goes to idle and ic_en=0: - Bits 5 and 6 are set to 0"] #[inline(always)] pub const fn ic_status(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(112usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x70usize) as _) } } #[doc = "I2C Transmit FIFO Level Register This register contains the number of valid data entries in the transmit FIFO buffer. It is cleared whenever: - The I2C is disabled - There is a transmit abort - that is, TX_ABRT bit is set in the IC_RAW_INTR_STAT register - The slave bulk transmit mode is aborted The register increments whenever data is placed into the transmit FIFO and decrements when data is taken from the transmit FIFO."] #[inline(always)] pub const fn ic_txflr(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(116usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x74usize) as _) } } #[doc = "I2C Receive FIFO Level Register This register contains the number of valid data entries in the receive FIFO buffer. It is cleared whenever: - The I2C is disabled - Whenever there is a transmit abort caused by any of the events tracked in IC_TX_ABRT_SOURCE The register increments whenever data is placed into the receive FIFO and decrements when data is taken from the receive FIFO."] #[inline(always)] pub const fn ic_rxflr(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(120usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x78usize) as _) } } #[doc = "I2C SDA Hold Time Length Register The bits \\[15:0\\] of this register are used to control the hold time of SDA during transmit in both slave and master mode (after SCL goes from HIGH to LOW). The bits \\[23:16\\] of this register are used to extend the SDA transition (if any) whenever SCL is HIGH in the receiver in either master or slave mode. Writes to this register succeed only when IC_ENABLE\\[0\\]=0. The values in this register are in units of ic_clk period. The value programmed in IC_SDA_TX_HOLD must be greater than the minimum hold time in each mode (one cycle in master mode, seven cycles in slave mode) for the value to be implemented. The programmed SDA hold time during transmit (IC_SDA_TX_HOLD) cannot exceed at any time the duration of the low part of scl. Therefore the programmed value cannot be larger than N_SCL_LOW-2, where N_SCL_LOW is the duration of the low part of the scl period measured in ic_clk cycles."] #[inline(always)] pub const fn ic_sda_hold(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(124usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x7cusize) as _) } } #[doc = "I2C Transmit Abort Source Register This register has 32 bits that indicate the source of the TX_ABRT bit. Except for Bit 9, this register is cleared whenever the IC_CLR_TX_ABRT register or the IC_CLR_INTR register is read. To clear Bit 9, the source of the ABRT_SBYTE_NORSTRT must be fixed first; RESTART must be enabled (IC_CON\\[5\\]=1), the SPECIAL bit must be cleared (IC_TAR\\[11\\]), or the GC_OR_START bit must be cleared (IC_TAR\\[10\\]). Once the source of the ABRT_SBYTE_NORSTRT is fixed, then this bit can be cleared in the same manner as other bits in this register. If the source of the ABRT_SBYTE_NORSTRT is not fixed before attempting to clear this bit, Bit 9 clears for one cycle and is then re-asserted."] #[inline(always)] pub const fn ic_tx_abrt_source( self, ) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(128usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x80usize) as _) } } #[doc = "Generate Slave Data NACK Register The register is used to generate a NACK for the data part of a transfer when DW_apb_i2c is acting as a slave-receiver. This register only exists when the IC_SLV_DATA_NACK_ONLY parameter is set to 1. When this parameter disabled, this register does not exist and writing to the register's address has no effect. A write can occur on this register if both of the following conditions are met: - DW_apb_i2c is disabled (IC_ENABLE\\[0\\] = 0) - Slave part is inactive (IC_STATUS\\[6\\] = 0) Note: The IC_STATUS\\[6\\] is a register read-back location for the internal slv_activity signal; the user should poll this before writing the ic_slv_data_nack_only bit."] #[inline(always)] pub const fn ic_slv_data_nack_only( self, ) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(132usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x84usize) as _) } } #[doc = "DMA Control Register The register is used to enable the DMA Controller interface operation. There is a separate bit for transmit and receive. This can be programmed regardless of the state of IC_ENABLE."] #[inline(always)] pub const fn ic_dma_cr(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(136usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x88usize) as _) } } #[doc = "DMA Transmit Data Level Register"] #[inline(always)] pub const fn ic_dma_tdlr(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(140usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x8cusize) as _) } } #[doc = "I2C Receive Data Level Register"] #[inline(always)] pub const fn ic_dma_rdlr(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(144usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x90usize) as _) } } #[doc = "I2C SDA Setup Register This register controls the amount of time delay (in terms of number of ic_clk clock periods) introduced in the rising edge of SCL - relative to SDA changing - when DW_apb_i2c services a read request in a slave-transmitter operation. The relevant I2C requirement is tSU:DAT (note 4) as detailed in the I2C Bus Specification. This register must be programmed with a value equal to or greater than 2. Writes to this register succeed only when IC_ENABLE\\[0\\] = 0. Note: The length of setup time is calculated using \\[(IC_SDA_SETUP - 1) * (ic_clk_period)\\], so if the user requires 10 ic_clk periods of setup time, they should program a value of 11. The IC_SDA_SETUP register is only used by the DW_apb_i2c when operating as a slave transmitter."] #[inline(always)] pub const fn ic_sda_setup(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(148usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x94usize) as _) } } #[doc = "I2C ACK General Call Register The register controls whether DW_apb_i2c responds with a ACK or NACK when it receives an I2C General Call address. This register is applicable only when the DW_apb_i2c is in slave mode."] #[inline(always)] pub const fn ic_ack_general_call( self, ) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(152usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x98usize) as _) } } #[doc = "I2C Enable Status Register The register is used to report the DW_apb_i2c hardware status when the IC_ENABLE\\[0\\] register is set from 1 to 0; that is, when DW_apb_i2c is disabled. If IC_ENABLE\\[0\\] has been set to 1, bits 2:1 are forced to 0, and bit 0 is forced to 1. If IC_ENABLE\\[0\\] has been set to 0, bits 2:1 is only be valid as soon as bit 0 is read as '0'. Note: When IC_ENABLE\\[0\\] has been set to 0, a delay occurs for bit 0 to be read as 0 because disabling the DW_apb_i2c depends on I2C bus activities."] #[inline(always)] pub const fn ic_enable_status( self, ) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(156usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x9cusize) as _) } } #[doc = "I2C SS, FS or FM+ spike suppression limit This register is used to store the duration, measured in ic_clk cycles, of the longest spike that is filtered out by the spike suppression logic when the component is operating in SS, FS or FM+ modes. The relevant I2C requirement is tSP (table 4) as detailed in the I2C Bus Specification. This register must be programmed with a minimum value of 1."] #[inline(always)] pub const fn ic_fs_spklen(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(160usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0xa0usize) as _) } } #[doc = "Clear RESTART_DET Interrupt Register"] #[inline(always)] pub const fn ic_clr_restart_det( self, ) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(168usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0xa8usize) as _) } } #[doc = "Component Parameter Register 1 Note This register is not implemented and therefore reads as 0. If it was implemented it would be a constant read-only register that contains encoded information about the component's parameter settings. Fields shown below are the settings for those parameters"] #[inline(always)] pub const fn ic_comp_param_1( self, ) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(244usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0xf4usize) as _) } } #[doc = "I2C Component Version Register"] #[inline(always)] pub const fn ic_comp_version(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(248usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0xf8usize) as _) } } #[doc = "I2C Component Type Register"] #[inline(always)] pub const fn ic_comp_type(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(252usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0xfcusize) as _) } } } pub mod regs; diff --git a/src/rp235x/i2c/vals.rs b/src/rp235x/i2c/vals.rs index 41e0860e..3755ac03 100644 --- a/src/rp235x/i2c/vals.rs +++ b/src/rp235x/i2c/vals.rs @@ -1,7 +1,7 @@ #[repr(u8)] #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] pub enum Speed { - _RESERVED_0 = 0, + _RESERVED_0 = 0x0, #[doc = "Standard Speed mode of operation"] STANDARD = 0x01, #[doc = "Fast or Fast Plus mode of operation"] diff --git a/src/rp235x/io.rs b/src/rp235x/io.rs index ad3be7d7..03f0023c 100644 --- a/src/rp235x/io.rs +++ b/src/rp235x/io.rs @@ -15,11 +15,11 @@ impl Gpio { } #[inline(always)] pub const fn status(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(0usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x0usize) as _) } } #[inline(always)] pub const fn ctrl(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(4usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x04usize) as _) } } } #[derive(Copy, Clone, Eq, PartialEq)] @@ -37,23 +37,23 @@ impl Int { pub const fn as_ptr(&self) -> *mut () { self.ptr as _ } - #[doc = "Interrupt Enable for proc1"] + #[doc = "Interrupt Enable for proc0"] #[inline(always)] pub const fn inte(self, n: usize) -> crate::common::Reg { assert!(n < 6usize); - unsafe { crate::common::Reg::from_ptr(self.ptr.add(0usize + n * 4usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x0usize + n * 4usize) as _) } } - #[doc = "Interrupt Force for proc1"] + #[doc = "Interrupt Force for proc0"] #[inline(always)] pub const fn intf(self, n: usize) -> crate::common::Reg { assert!(n < 6usize); - unsafe { crate::common::Reg::from_ptr(self.ptr.add(24usize + n * 4usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x18usize + n * 4usize) as _) } } - #[doc = "Interrupt status after masking & forcing for proc1"] + #[doc = "Interrupt status after masking & forcing for proc0"] #[inline(always)] pub const fn ints(self, n: usize) -> crate::common::Reg { assert!(n < 6usize); - unsafe { crate::common::Reg::from_ptr(self.ptr.add(48usize + n * 4usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x30usize + n * 4usize) as _) } } } #[derive(Copy, Clone, Eq, PartialEq)] @@ -74,94 +74,70 @@ impl Io { #[inline(always)] pub const fn gpio(self, n: usize) -> Gpio { assert!(n < 48usize); - unsafe { Gpio::from_ptr(self.ptr.add(0usize + n * 8usize) as _) } + unsafe { Gpio::from_ptr(self.ptr.add(0x0usize + n * 8usize) as _) } } #[inline(always)] - pub const fn irqsummary_proc0_secure0( + pub const fn irqsummary_proc0_secure( self, - ) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(512usize) as _) } - } - #[inline(always)] - pub const fn irqsummary_proc0_secure1( - self, - ) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(516usize) as _) } - } - #[inline(always)] - pub const fn irqsummary_proc0_nonsecure0( - self, - ) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(520usize) as _) } - } - #[inline(always)] - pub const fn irqsummary_proc0_nonsecure1( - self, - ) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(524usize) as _) } - } - #[inline(always)] - pub const fn irqsummary_proc1_secure0( - self, - ) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(528usize) as _) } - } - #[inline(always)] - pub const fn irqsummary_proc1_secure1( - self, - ) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(532usize) as _) } - } - #[inline(always)] - pub const fn irqsummary_proc1_nonsecure0( - self, - ) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(536usize) as _) } + n: usize, + ) -> crate::common::Reg { + assert!(n < 2usize); + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x0200usize + n * 4usize) as _) } } #[inline(always)] - pub const fn irqsummary_proc1_nonsecure1( + pub const fn irqsummary_proc0_nonsecure( self, - ) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(540usize) as _) } + n: usize, + ) -> crate::common::Reg { + assert!(n < 2usize); + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x0208usize + n * 4usize) as _) } } #[inline(always)] - pub const fn irqsummary_dormant_wake_secure0( + pub const fn irqsummary_proc1_secure( self, - ) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(544usize) as _) } + n: usize, + ) -> crate::common::Reg { + assert!(n < 2usize); + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x0210usize + n * 4usize) as _) } } #[inline(always)] - pub const fn irqsummary_dormant_wake_secure1( + pub const fn irqsummary_proc1_nonsecure( self, - ) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(548usize) as _) } + n: usize, + ) -> crate::common::Reg { + assert!(n < 2usize); + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x0218usize + n * 4usize) as _) } } #[inline(always)] - pub const fn irqsummary_dormant_wake_nonsecure0( + pub const fn irqsummary_dormant_wake_secure( self, - ) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(552usize) as _) } + n: usize, + ) -> crate::common::Reg { + assert!(n < 2usize); + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x0220usize + n * 4usize) as _) } } #[inline(always)] - pub const fn irqsummary_dormant_wake_nonsecure1( + pub const fn irqsummary_dormant_wake_nonsecure( self, - ) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(556usize) as _) } + n: usize, + ) -> crate::common::Reg { + assert!(n < 2usize); + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x0228usize + n * 4usize) as _) } } #[doc = "Raw Interrupts"] #[inline(always)] pub const fn intr(self, n: usize) -> crate::common::Reg { assert!(n < 6usize); - unsafe { crate::common::Reg::from_ptr(self.ptr.add(560usize + n * 4usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x0230usize + n * 4usize) as _) } } #[inline(always)] pub const fn int_proc(self, n: usize) -> Int { assert!(n < 2usize); - unsafe { Int::from_ptr(self.ptr.add(584usize + n * 72usize) as _) } + unsafe { Int::from_ptr(self.ptr.add(0x0248usize + n * 72usize) as _) } } #[inline(always)] pub const fn int_dormant_wake(self) -> Int { - unsafe { Int::from_ptr(self.ptr.add(728usize) as _) } + unsafe { Int::from_ptr(self.ptr.add(0x02d8usize) as _) } } } pub mod regs; diff --git a/src/rp235x/io/regs.rs b/src/rp235x/io/regs.rs index 6bc23c48..30464b55 100644 --- a/src/rp235x/io/regs.rs +++ b/src/rp235x/io/regs.rs @@ -111,7 +111,7 @@ impl Default for GpioStatus { GpioStatus(0) } } -#[doc = "Interrupt Force for proc0"] +#[doc = "Interrupt status after masking & forcing for proc0"] #[repr(transparent)] #[derive(Copy, Clone, Eq, PartialEq)] pub struct Int(pub u32); @@ -175,2727 +175,3 @@ impl Default for Int { Int(0) } } -#[repr(transparent)] -#[derive(Copy, Clone, Eq, PartialEq)] -pub struct IrqsummaryDormantWakeNonsecure0(pub u32); -impl IrqsummaryDormantWakeNonsecure0 { - #[inline(always)] - pub const fn gpio0(&self) -> bool { - let val = (self.0 >> 0usize) & 0x01; - val != 0 - } - #[inline(always)] - pub fn set_gpio0(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize); - } - #[inline(always)] - pub const fn gpio1(&self) -> bool { - let val = (self.0 >> 1usize) & 0x01; - val != 0 - } - #[inline(always)] - pub fn set_gpio1(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize); - } - #[inline(always)] - pub const fn gpio2(&self) -> bool { - let val = (self.0 >> 2usize) & 0x01; - val != 0 - } - #[inline(always)] - pub fn set_gpio2(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 2usize)) | (((val as u32) & 0x01) << 2usize); - } - #[inline(always)] - pub const fn gpio3(&self) -> bool { - let val = (self.0 >> 3usize) & 0x01; - val != 0 - } - #[inline(always)] - pub fn set_gpio3(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 3usize)) | (((val as u32) & 0x01) << 3usize); - } - #[inline(always)] - pub const fn gpio4(&self) -> bool { - let val = (self.0 >> 4usize) & 0x01; - val != 0 - } - #[inline(always)] - pub fn set_gpio4(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 4usize)) | (((val as u32) & 0x01) << 4usize); - } - #[inline(always)] - pub const fn gpio5(&self) -> bool { - let val = (self.0 >> 5usize) & 0x01; - val != 0 - } - #[inline(always)] - pub fn set_gpio5(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 5usize)) | (((val as u32) & 0x01) << 5usize); - } - #[inline(always)] - pub const fn gpio6(&self) -> bool { - let val = (self.0 >> 6usize) & 0x01; - val != 0 - } - #[inline(always)] - pub fn set_gpio6(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 6usize)) | (((val as u32) & 0x01) << 6usize); - } - #[inline(always)] - pub const fn gpio7(&self) -> bool { - let val = (self.0 >> 7usize) & 0x01; - val != 0 - } - #[inline(always)] - pub fn set_gpio7(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 7usize)) | (((val as u32) & 0x01) << 7usize); - } - #[inline(always)] - pub const fn gpio8(&self) -> bool { - let val = (self.0 >> 8usize) & 0x01; - val != 0 - } - #[inline(always)] - pub fn set_gpio8(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 8usize)) | (((val as u32) & 0x01) << 8usize); - } - #[inline(always)] - pub const fn gpio9(&self) -> bool { - let val = (self.0 >> 9usize) & 0x01; - val != 0 - } - #[inline(always)] - pub fn set_gpio9(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 9usize)) | (((val as u32) & 0x01) << 9usize); - } - #[inline(always)] - pub const fn gpio10(&self) -> bool { - let val = (self.0 >> 10usize) & 0x01; - val != 0 - } - #[inline(always)] - pub fn set_gpio10(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 10usize)) | (((val as u32) & 0x01) << 10usize); - } - #[inline(always)] - pub const fn gpio11(&self) -> bool { - let val = (self.0 >> 11usize) & 0x01; - val != 0 - } - #[inline(always)] - pub fn set_gpio11(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 11usize)) | (((val as u32) & 0x01) << 11usize); - } - #[inline(always)] - pub const fn gpio12(&self) -> bool { - let val = (self.0 >> 12usize) & 0x01; - val != 0 - } - #[inline(always)] - pub fn set_gpio12(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 12usize)) | (((val as u32) & 0x01) << 12usize); - } - #[inline(always)] - pub const fn gpio13(&self) -> bool { - let val = (self.0 >> 13usize) & 0x01; - val != 0 - } - #[inline(always)] - pub fn set_gpio13(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 13usize)) | (((val as u32) & 0x01) << 13usize); - } - #[inline(always)] - pub const fn gpio14(&self) -> bool { - let val = (self.0 >> 14usize) & 0x01; - val != 0 - } - #[inline(always)] - pub fn set_gpio14(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 14usize)) | (((val as u32) & 0x01) << 14usize); - } - #[inline(always)] - pub const fn gpio15(&self) -> bool { - let val = (self.0 >> 15usize) & 0x01; - val != 0 - } - #[inline(always)] - pub fn set_gpio15(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 15usize)) | (((val as u32) & 0x01) << 15usize); - } - #[inline(always)] - pub const fn gpio16(&self) -> bool { - let val = (self.0 >> 16usize) & 0x01; - val != 0 - } - #[inline(always)] - pub fn set_gpio16(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 16usize)) | (((val as u32) & 0x01) << 16usize); - } - #[inline(always)] - pub const fn gpio17(&self) -> bool { - let val = (self.0 >> 17usize) & 0x01; - val != 0 - } - #[inline(always)] - pub fn set_gpio17(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 17usize)) | (((val as u32) & 0x01) << 17usize); - } - #[inline(always)] - pub const fn gpio18(&self) -> bool { - let val = (self.0 >> 18usize) & 0x01; - val != 0 - } - #[inline(always)] - pub fn set_gpio18(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 18usize)) | (((val as u32) & 0x01) << 18usize); - } - #[inline(always)] - pub const fn gpio19(&self) -> bool { - let val = (self.0 >> 19usize) & 0x01; - val != 0 - } - #[inline(always)] - pub fn set_gpio19(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 19usize)) | (((val as u32) & 0x01) << 19usize); - } - #[inline(always)] - pub const fn gpio20(&self) -> bool { - let val = (self.0 >> 20usize) & 0x01; - val != 0 - } - #[inline(always)] - pub fn set_gpio20(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 20usize)) | (((val as u32) & 0x01) << 20usize); - } - #[inline(always)] - pub const fn gpio21(&self) -> bool { - let val = (self.0 >> 21usize) & 0x01; - val != 0 - } - #[inline(always)] - pub fn set_gpio21(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 21usize)) | (((val as u32) & 0x01) << 21usize); - } - #[inline(always)] - pub const fn gpio22(&self) -> bool { - let val = (self.0 >> 22usize) & 0x01; - val != 0 - } - #[inline(always)] - pub fn set_gpio22(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 22usize)) | (((val as u32) & 0x01) << 22usize); - } - #[inline(always)] - pub const fn gpio23(&self) -> bool { - let val = (self.0 >> 23usize) & 0x01; - val != 0 - } - #[inline(always)] - pub fn set_gpio23(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 23usize)) | (((val as u32) & 0x01) << 23usize); - } - #[inline(always)] - pub const fn gpio24(&self) -> bool { - let val = (self.0 >> 24usize) & 0x01; - val != 0 - } - #[inline(always)] - pub fn set_gpio24(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 24usize)) | (((val as u32) & 0x01) << 24usize); - } - #[inline(always)] - pub const fn gpio25(&self) -> bool { - let val = (self.0 >> 25usize) & 0x01; - val != 0 - } - #[inline(always)] - pub fn set_gpio25(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 25usize)) | (((val as u32) & 0x01) << 25usize); - } - #[inline(always)] - pub const fn gpio26(&self) -> bool { - let val = (self.0 >> 26usize) & 0x01; - val != 0 - } - #[inline(always)] - pub fn set_gpio26(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 26usize)) | (((val as u32) & 0x01) << 26usize); - } - #[inline(always)] - pub const fn gpio27(&self) -> bool { - let val = (self.0 >> 27usize) & 0x01; - val != 0 - } - #[inline(always)] - pub fn set_gpio27(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 27usize)) | (((val as u32) & 0x01) << 27usize); - } - #[inline(always)] - pub const fn gpio28(&self) -> bool { - let val = (self.0 >> 28usize) & 0x01; - val != 0 - } - #[inline(always)] - pub fn set_gpio28(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 28usize)) | (((val as u32) & 0x01) << 28usize); - } - #[inline(always)] - pub const fn gpio29(&self) -> bool { - let val = (self.0 >> 29usize) & 0x01; - val != 0 - } - #[inline(always)] - pub fn set_gpio29(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 29usize)) | (((val as u32) & 0x01) << 29usize); - } - #[inline(always)] - pub const fn gpio30(&self) -> bool { - let val = (self.0 >> 30usize) & 0x01; - val != 0 - } - #[inline(always)] - pub fn set_gpio30(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 30usize)) | (((val as u32) & 0x01) << 30usize); - } - #[inline(always)] - pub const fn gpio31(&self) -> bool { - let val = (self.0 >> 31usize) & 0x01; - val != 0 - } - #[inline(always)] - pub fn set_gpio31(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 31usize)) | (((val as u32) & 0x01) << 31usize); - } -} -impl Default for IrqsummaryDormantWakeNonsecure0 { - #[inline(always)] - fn default() -> IrqsummaryDormantWakeNonsecure0 { - IrqsummaryDormantWakeNonsecure0(0) - } -} -#[repr(transparent)] -#[derive(Copy, Clone, Eq, PartialEq)] -pub struct IrqsummaryDormantWakeNonsecure1(pub u32); -impl IrqsummaryDormantWakeNonsecure1 { - #[inline(always)] - pub const fn gpio32(&self) -> bool { - let val = (self.0 >> 0usize) & 0x01; - val != 0 - } - #[inline(always)] - pub fn set_gpio32(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize); - } - #[inline(always)] - pub const fn gpio33(&self) -> bool { - let val = (self.0 >> 1usize) & 0x01; - val != 0 - } - #[inline(always)] - pub fn set_gpio33(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize); - } - #[inline(always)] - pub const fn gpio34(&self) -> bool { - let val = (self.0 >> 2usize) & 0x01; - val != 0 - } - #[inline(always)] - pub fn set_gpio34(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 2usize)) | (((val as u32) & 0x01) << 2usize); - } - #[inline(always)] - pub const fn gpio35(&self) -> bool { - let val = (self.0 >> 3usize) & 0x01; - val != 0 - } - #[inline(always)] - pub fn set_gpio35(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 3usize)) | (((val as u32) & 0x01) << 3usize); - } - #[inline(always)] - pub const fn gpio36(&self) -> bool { - let val = (self.0 >> 4usize) & 0x01; - val != 0 - } - #[inline(always)] - pub fn set_gpio36(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 4usize)) | (((val as u32) & 0x01) << 4usize); - } - #[inline(always)] - pub const fn gpio37(&self) -> bool { - let val = (self.0 >> 5usize) & 0x01; - val != 0 - } - #[inline(always)] - pub fn set_gpio37(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 5usize)) | (((val as u32) & 0x01) << 5usize); - } - #[inline(always)] - pub const fn gpio38(&self) -> bool { - let val = (self.0 >> 6usize) & 0x01; - val != 0 - } - #[inline(always)] - pub fn set_gpio38(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 6usize)) | (((val as u32) & 0x01) << 6usize); - } - #[inline(always)] - pub const fn gpio39(&self) -> bool { - let val = (self.0 >> 7usize) & 0x01; - val != 0 - } - #[inline(always)] - pub fn set_gpio39(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 7usize)) | (((val as u32) & 0x01) << 7usize); - } - #[inline(always)] - pub const fn gpio40(&self) -> bool { - let val = (self.0 >> 8usize) & 0x01; - val != 0 - } - #[inline(always)] - pub fn set_gpio40(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 8usize)) | (((val as u32) & 0x01) << 8usize); - } - #[inline(always)] - pub const fn gpio41(&self) -> bool { - let val = (self.0 >> 9usize) & 0x01; - val != 0 - } - #[inline(always)] - pub fn set_gpio41(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 9usize)) | (((val as u32) & 0x01) << 9usize); - } - #[inline(always)] - pub const fn gpio42(&self) -> bool { - let val = (self.0 >> 10usize) & 0x01; - val != 0 - } - #[inline(always)] - pub fn set_gpio42(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 10usize)) | (((val as u32) & 0x01) << 10usize); - } - #[inline(always)] - pub const fn gpio43(&self) -> bool { - let val = (self.0 >> 11usize) & 0x01; - val != 0 - } - #[inline(always)] - pub fn set_gpio43(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 11usize)) | (((val as u32) & 0x01) << 11usize); - } - #[inline(always)] - pub const fn gpio44(&self) -> bool { - let val = (self.0 >> 12usize) & 0x01; - val != 0 - } - #[inline(always)] - pub fn set_gpio44(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 12usize)) | (((val as u32) & 0x01) << 12usize); - } - #[inline(always)] - pub const fn gpio45(&self) -> bool { - let val = (self.0 >> 13usize) & 0x01; - val != 0 - } - #[inline(always)] - pub fn set_gpio45(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 13usize)) | (((val as u32) & 0x01) << 13usize); - } - #[inline(always)] - pub const fn gpio46(&self) -> bool { - let val = (self.0 >> 14usize) & 0x01; - val != 0 - } - #[inline(always)] - pub fn set_gpio46(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 14usize)) | (((val as u32) & 0x01) << 14usize); - } - #[inline(always)] - pub const fn gpio47(&self) -> bool { - let val = (self.0 >> 15usize) & 0x01; - val != 0 - } - #[inline(always)] - pub fn set_gpio47(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 15usize)) | (((val as u32) & 0x01) << 15usize); - } -} -impl Default for IrqsummaryDormantWakeNonsecure1 { - #[inline(always)] - fn default() -> IrqsummaryDormantWakeNonsecure1 { - IrqsummaryDormantWakeNonsecure1(0) - } -} -#[repr(transparent)] -#[derive(Copy, Clone, Eq, PartialEq)] -pub struct IrqsummaryDormantWakeSecure0(pub u32); -impl IrqsummaryDormantWakeSecure0 { - #[inline(always)] - pub const fn gpio0(&self) -> bool { - let val = (self.0 >> 0usize) & 0x01; - val != 0 - } - #[inline(always)] - pub fn set_gpio0(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize); - } - #[inline(always)] - pub const fn gpio1(&self) -> bool { - let val = (self.0 >> 1usize) & 0x01; - val != 0 - } - #[inline(always)] - pub fn set_gpio1(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize); - } - #[inline(always)] - pub const fn gpio2(&self) -> bool { - let val = (self.0 >> 2usize) & 0x01; - val != 0 - } - #[inline(always)] - pub fn set_gpio2(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 2usize)) | (((val as u32) & 0x01) << 2usize); - } - #[inline(always)] - pub const fn gpio3(&self) -> bool { - let val = (self.0 >> 3usize) & 0x01; - val != 0 - } - #[inline(always)] - pub fn set_gpio3(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 3usize)) | (((val as u32) & 0x01) << 3usize); - } - #[inline(always)] - pub const fn gpio4(&self) -> bool { - let val = (self.0 >> 4usize) & 0x01; - val != 0 - } - #[inline(always)] - pub fn set_gpio4(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 4usize)) | (((val as u32) & 0x01) << 4usize); - } - #[inline(always)] - pub const fn gpio5(&self) -> bool { - let val = (self.0 >> 5usize) & 0x01; - val != 0 - } - #[inline(always)] - pub fn set_gpio5(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 5usize)) | (((val as u32) & 0x01) << 5usize); - } - #[inline(always)] - pub const fn gpio6(&self) -> bool { - let val = (self.0 >> 6usize) & 0x01; - val != 0 - } - #[inline(always)] - pub fn set_gpio6(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 6usize)) | (((val as u32) & 0x01) << 6usize); - } - #[inline(always)] - pub const fn gpio7(&self) -> bool { - let val = (self.0 >> 7usize) & 0x01; - val != 0 - } - #[inline(always)] - pub fn set_gpio7(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 7usize)) | (((val as u32) & 0x01) << 7usize); - } - #[inline(always)] - pub const fn gpio8(&self) -> bool { - let val = (self.0 >> 8usize) & 0x01; - val != 0 - } - #[inline(always)] - pub fn set_gpio8(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 8usize)) | (((val as u32) & 0x01) << 8usize); - } - #[inline(always)] - pub const fn gpio9(&self) -> bool { - let val = (self.0 >> 9usize) & 0x01; - val != 0 - } - #[inline(always)] - pub fn set_gpio9(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 9usize)) | (((val as u32) & 0x01) << 9usize); - } - #[inline(always)] - pub const fn gpio10(&self) -> bool { - let val = (self.0 >> 10usize) & 0x01; - val != 0 - } - #[inline(always)] - pub fn set_gpio10(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 10usize)) | (((val as u32) & 0x01) << 10usize); - } - #[inline(always)] - pub const fn gpio11(&self) -> bool { - let val = (self.0 >> 11usize) & 0x01; - val != 0 - } - #[inline(always)] - pub fn set_gpio11(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 11usize)) | (((val as u32) & 0x01) << 11usize); - } - #[inline(always)] - pub const fn gpio12(&self) -> bool { - let val = (self.0 >> 12usize) & 0x01; - val != 0 - } - #[inline(always)] - pub fn set_gpio12(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 12usize)) | (((val as u32) & 0x01) << 12usize); - } - #[inline(always)] - pub const fn gpio13(&self) -> bool { - let val = (self.0 >> 13usize) & 0x01; - val != 0 - } - #[inline(always)] - pub fn set_gpio13(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 13usize)) | (((val as u32) & 0x01) << 13usize); - } - #[inline(always)] - pub const fn gpio14(&self) -> bool { - let val = (self.0 >> 14usize) & 0x01; - val != 0 - } - #[inline(always)] - pub fn set_gpio14(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 14usize)) | (((val as u32) & 0x01) << 14usize); - } - #[inline(always)] - pub const fn gpio15(&self) -> bool { - let val = (self.0 >> 15usize) & 0x01; - val != 0 - } - #[inline(always)] - pub fn set_gpio15(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 15usize)) | (((val as u32) & 0x01) << 15usize); - } - #[inline(always)] - pub const fn gpio16(&self) -> bool { - let val = (self.0 >> 16usize) & 0x01; - val != 0 - } - #[inline(always)] - pub fn set_gpio16(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 16usize)) | (((val as u32) & 0x01) << 16usize); - } - #[inline(always)] - pub const fn gpio17(&self) -> bool { - let val = (self.0 >> 17usize) & 0x01; - val != 0 - } - #[inline(always)] - pub fn set_gpio17(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 17usize)) | (((val as u32) & 0x01) << 17usize); - } - #[inline(always)] - pub const fn gpio18(&self) -> bool { - let val = (self.0 >> 18usize) & 0x01; - val != 0 - } - #[inline(always)] - pub fn set_gpio18(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 18usize)) | (((val as u32) & 0x01) << 18usize); - } - #[inline(always)] - pub const fn gpio19(&self) -> bool { - let val = (self.0 >> 19usize) & 0x01; - val != 0 - } - #[inline(always)] - pub fn set_gpio19(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 19usize)) | (((val as u32) & 0x01) << 19usize); - } - #[inline(always)] - pub const fn gpio20(&self) -> bool { - let val = (self.0 >> 20usize) & 0x01; - val != 0 - } - #[inline(always)] - pub fn set_gpio20(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 20usize)) | (((val as u32) & 0x01) << 20usize); - } - #[inline(always)] - pub const fn gpio21(&self) -> bool { - let val = (self.0 >> 21usize) & 0x01; - val != 0 - } - #[inline(always)] - pub fn set_gpio21(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 21usize)) | (((val as u32) & 0x01) << 21usize); - } - #[inline(always)] - pub const fn gpio22(&self) -> bool { - let val = (self.0 >> 22usize) & 0x01; - val != 0 - } - #[inline(always)] - pub fn set_gpio22(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 22usize)) | (((val as u32) & 0x01) << 22usize); - } - #[inline(always)] - pub const fn gpio23(&self) -> bool { - let val = (self.0 >> 23usize) & 0x01; - val != 0 - } - #[inline(always)] - pub fn set_gpio23(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 23usize)) | (((val as u32) & 0x01) << 23usize); - } - #[inline(always)] - pub const fn gpio24(&self) -> bool { - let val = (self.0 >> 24usize) & 0x01; - val != 0 - } - #[inline(always)] - pub fn set_gpio24(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 24usize)) | (((val as u32) & 0x01) << 24usize); - } - #[inline(always)] - pub const fn gpio25(&self) -> bool { - let val = (self.0 >> 25usize) & 0x01; - val != 0 - } - #[inline(always)] - pub fn set_gpio25(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 25usize)) | (((val as u32) & 0x01) << 25usize); - } - #[inline(always)] - pub const fn gpio26(&self) -> bool { - let val = (self.0 >> 26usize) & 0x01; - val != 0 - } - #[inline(always)] - pub fn set_gpio26(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 26usize)) | (((val as u32) & 0x01) << 26usize); - } - #[inline(always)] - pub const fn gpio27(&self) -> bool { - let val = (self.0 >> 27usize) & 0x01; - val != 0 - } - #[inline(always)] - pub fn set_gpio27(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 27usize)) | (((val as u32) & 0x01) << 27usize); - } - #[inline(always)] - pub const fn gpio28(&self) -> bool { - let val = (self.0 >> 28usize) & 0x01; - val != 0 - } - #[inline(always)] - pub fn set_gpio28(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 28usize)) | (((val as u32) & 0x01) << 28usize); - } - #[inline(always)] - pub const fn gpio29(&self) -> bool { - let val = (self.0 >> 29usize) & 0x01; - val != 0 - } - #[inline(always)] - pub fn set_gpio29(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 29usize)) | (((val as u32) & 0x01) << 29usize); - } - #[inline(always)] - pub const fn gpio30(&self) -> bool { - let val = (self.0 >> 30usize) & 0x01; - val != 0 - } - #[inline(always)] - pub fn set_gpio30(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 30usize)) | (((val as u32) & 0x01) << 30usize); - } - #[inline(always)] - pub const fn gpio31(&self) -> bool { - let val = (self.0 >> 31usize) & 0x01; - val != 0 - } - #[inline(always)] - pub fn set_gpio31(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 31usize)) | (((val as u32) & 0x01) << 31usize); - } -} -impl Default for IrqsummaryDormantWakeSecure0 { - #[inline(always)] - fn default() -> IrqsummaryDormantWakeSecure0 { - IrqsummaryDormantWakeSecure0(0) - } -} -#[repr(transparent)] -#[derive(Copy, Clone, Eq, PartialEq)] -pub struct IrqsummaryDormantWakeSecure1(pub u32); -impl IrqsummaryDormantWakeSecure1 { - #[inline(always)] - pub const fn gpio32(&self) -> bool { - let val = (self.0 >> 0usize) & 0x01; - val != 0 - } - #[inline(always)] - pub fn set_gpio32(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize); - } - #[inline(always)] - pub const fn gpio33(&self) -> bool { - let val = (self.0 >> 1usize) & 0x01; - val != 0 - } - #[inline(always)] - pub fn set_gpio33(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize); - } - #[inline(always)] - pub const fn gpio34(&self) -> bool { - let val = (self.0 >> 2usize) & 0x01; - val != 0 - } - #[inline(always)] - pub fn set_gpio34(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 2usize)) | (((val as u32) & 0x01) << 2usize); - } - #[inline(always)] - pub const fn gpio35(&self) -> bool { - let val = (self.0 >> 3usize) & 0x01; - val != 0 - } - #[inline(always)] - pub fn set_gpio35(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 3usize)) | (((val as u32) & 0x01) << 3usize); - } - #[inline(always)] - pub const fn gpio36(&self) -> bool { - let val = (self.0 >> 4usize) & 0x01; - val != 0 - } - #[inline(always)] - pub fn set_gpio36(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 4usize)) | (((val as u32) & 0x01) << 4usize); - } - #[inline(always)] - pub const fn gpio37(&self) -> bool { - let val = (self.0 >> 5usize) & 0x01; - val != 0 - } - #[inline(always)] - pub fn set_gpio37(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 5usize)) | (((val as u32) & 0x01) << 5usize); - } - #[inline(always)] - pub const fn gpio38(&self) -> bool { - let val = (self.0 >> 6usize) & 0x01; - val != 0 - } - #[inline(always)] - pub fn set_gpio38(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 6usize)) | (((val as u32) & 0x01) << 6usize); - } - #[inline(always)] - pub const fn gpio39(&self) -> bool { - let val = (self.0 >> 7usize) & 0x01; - val != 0 - } - #[inline(always)] - pub fn set_gpio39(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 7usize)) | (((val as u32) & 0x01) << 7usize); - } - #[inline(always)] - pub const fn gpio40(&self) -> bool { - let val = (self.0 >> 8usize) & 0x01; - val != 0 - } - #[inline(always)] - pub fn set_gpio40(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 8usize)) | (((val as u32) & 0x01) << 8usize); - } - #[inline(always)] - pub const fn gpio41(&self) -> bool { - let val = (self.0 >> 9usize) & 0x01; - val != 0 - } - #[inline(always)] - pub fn set_gpio41(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 9usize)) | (((val as u32) & 0x01) << 9usize); - } - #[inline(always)] - pub const fn gpio42(&self) -> bool { - let val = (self.0 >> 10usize) & 0x01; - val != 0 - } - #[inline(always)] - pub fn set_gpio42(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 10usize)) | (((val as u32) & 0x01) << 10usize); - } - #[inline(always)] - pub const fn gpio43(&self) -> bool { - let val = (self.0 >> 11usize) & 0x01; - val != 0 - } - #[inline(always)] - pub fn set_gpio43(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 11usize)) | (((val as u32) & 0x01) << 11usize); - } - #[inline(always)] - pub const fn gpio44(&self) -> bool { - let val = (self.0 >> 12usize) & 0x01; - val != 0 - } - #[inline(always)] - pub fn set_gpio44(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 12usize)) | (((val as u32) & 0x01) << 12usize); - } - #[inline(always)] - pub const fn gpio45(&self) -> bool { - let val = (self.0 >> 13usize) & 0x01; - val != 0 - } - #[inline(always)] - pub fn set_gpio45(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 13usize)) | (((val as u32) & 0x01) << 13usize); - } - #[inline(always)] - pub const fn gpio46(&self) -> bool { - let val = (self.0 >> 14usize) & 0x01; - val != 0 - } - #[inline(always)] - pub fn set_gpio46(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 14usize)) | (((val as u32) & 0x01) << 14usize); - } - #[inline(always)] - pub const fn gpio47(&self) -> bool { - let val = (self.0 >> 15usize) & 0x01; - val != 0 - } - #[inline(always)] - pub fn set_gpio47(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 15usize)) | (((val as u32) & 0x01) << 15usize); - } -} -impl Default for IrqsummaryDormantWakeSecure1 { - #[inline(always)] - fn default() -> IrqsummaryDormantWakeSecure1 { - IrqsummaryDormantWakeSecure1(0) - } -} -#[repr(transparent)] -#[derive(Copy, Clone, Eq, PartialEq)] -pub struct IrqsummaryProc0nonsecure0(pub u32); -impl IrqsummaryProc0nonsecure0 { - #[inline(always)] - pub const fn gpio0(&self) -> bool { - let val = (self.0 >> 0usize) & 0x01; - val != 0 - } - #[inline(always)] - pub fn set_gpio0(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize); - } - #[inline(always)] - pub const fn gpio1(&self) -> bool { - let val = (self.0 >> 1usize) & 0x01; - val != 0 - } - #[inline(always)] - pub fn set_gpio1(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize); - } - #[inline(always)] - pub const fn gpio2(&self) -> bool { - let val = (self.0 >> 2usize) & 0x01; - val != 0 - } - #[inline(always)] - pub fn set_gpio2(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 2usize)) | (((val as u32) & 0x01) << 2usize); - } - #[inline(always)] - pub const fn gpio3(&self) -> bool { - let val = (self.0 >> 3usize) & 0x01; - val != 0 - } - #[inline(always)] - pub fn set_gpio3(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 3usize)) | (((val as u32) & 0x01) << 3usize); - } - #[inline(always)] - pub const fn gpio4(&self) -> bool { - let val = (self.0 >> 4usize) & 0x01; - val != 0 - } - #[inline(always)] - pub fn set_gpio4(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 4usize)) | (((val as u32) & 0x01) << 4usize); - } - #[inline(always)] - pub const fn gpio5(&self) -> bool { - let val = (self.0 >> 5usize) & 0x01; - val != 0 - } - #[inline(always)] - pub fn set_gpio5(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 5usize)) | (((val as u32) & 0x01) << 5usize); - } - #[inline(always)] - pub const fn gpio6(&self) -> bool { - let val = (self.0 >> 6usize) & 0x01; - val != 0 - } - #[inline(always)] - pub fn set_gpio6(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 6usize)) | (((val as u32) & 0x01) << 6usize); - } - #[inline(always)] - pub const fn gpio7(&self) -> bool { - let val = (self.0 >> 7usize) & 0x01; - val != 0 - } - #[inline(always)] - pub fn set_gpio7(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 7usize)) | (((val as u32) & 0x01) << 7usize); - } - #[inline(always)] - pub const fn gpio8(&self) -> bool { - let val = (self.0 >> 8usize) & 0x01; - val != 0 - } - #[inline(always)] - pub fn set_gpio8(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 8usize)) | (((val as u32) & 0x01) << 8usize); - } - #[inline(always)] - pub const fn gpio9(&self) -> bool { - let val = (self.0 >> 9usize) & 0x01; - val != 0 - } - #[inline(always)] - pub fn set_gpio9(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 9usize)) | (((val as u32) & 0x01) << 9usize); - } - #[inline(always)] - pub const fn gpio10(&self) -> bool { - let val = (self.0 >> 10usize) & 0x01; - val != 0 - } - #[inline(always)] - pub fn set_gpio10(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 10usize)) | (((val as u32) & 0x01) << 10usize); - } - #[inline(always)] - pub const fn gpio11(&self) -> bool { - let val = (self.0 >> 11usize) & 0x01; - val != 0 - } - #[inline(always)] - pub fn set_gpio11(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 11usize)) | (((val as u32) & 0x01) << 11usize); - } - #[inline(always)] - pub const fn gpio12(&self) -> bool { - let val = (self.0 >> 12usize) & 0x01; - val != 0 - } - #[inline(always)] - pub fn set_gpio12(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 12usize)) | (((val as u32) & 0x01) << 12usize); - } - #[inline(always)] - pub const fn gpio13(&self) -> bool { - let val = (self.0 >> 13usize) & 0x01; - val != 0 - } - #[inline(always)] - pub fn set_gpio13(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 13usize)) | (((val as u32) & 0x01) << 13usize); - } - #[inline(always)] - pub const fn gpio14(&self) -> bool { - let val = (self.0 >> 14usize) & 0x01; - val != 0 - } - #[inline(always)] - pub fn set_gpio14(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 14usize)) | (((val as u32) & 0x01) << 14usize); - } - #[inline(always)] - pub const fn gpio15(&self) -> bool { - let val = (self.0 >> 15usize) & 0x01; - val != 0 - } - #[inline(always)] - pub fn set_gpio15(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 15usize)) | (((val as u32) & 0x01) << 15usize); - } - #[inline(always)] - pub const fn gpio16(&self) -> bool { - let val = (self.0 >> 16usize) & 0x01; - val != 0 - } - #[inline(always)] - pub fn set_gpio16(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 16usize)) | (((val as u32) & 0x01) << 16usize); - } - #[inline(always)] - pub const fn gpio17(&self) -> bool { - let val = (self.0 >> 17usize) & 0x01; - val != 0 - } - #[inline(always)] - pub fn set_gpio17(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 17usize)) | (((val as u32) & 0x01) << 17usize); - } - #[inline(always)] - pub const fn gpio18(&self) -> bool { - let val = (self.0 >> 18usize) & 0x01; - val != 0 - } - #[inline(always)] - pub fn set_gpio18(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 18usize)) | (((val as u32) & 0x01) << 18usize); - } - #[inline(always)] - pub const fn gpio19(&self) -> bool { - let val = (self.0 >> 19usize) & 0x01; - val != 0 - } - #[inline(always)] - pub fn set_gpio19(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 19usize)) | (((val as u32) & 0x01) << 19usize); - } - #[inline(always)] - pub const fn gpio20(&self) -> bool { - let val = (self.0 >> 20usize) & 0x01; - val != 0 - } - #[inline(always)] - pub fn set_gpio20(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 20usize)) | (((val as u32) & 0x01) << 20usize); - } - #[inline(always)] - pub const fn gpio21(&self) -> bool { - let val = (self.0 >> 21usize) & 0x01; - val != 0 - } - #[inline(always)] - pub fn set_gpio21(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 21usize)) | (((val as u32) & 0x01) << 21usize); - } - #[inline(always)] - pub const fn gpio22(&self) -> bool { - let val = (self.0 >> 22usize) & 0x01; - val != 0 - } - #[inline(always)] - pub fn set_gpio22(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 22usize)) | (((val as u32) & 0x01) << 22usize); - } - #[inline(always)] - pub const fn gpio23(&self) -> bool { - let val = (self.0 >> 23usize) & 0x01; - val != 0 - } - #[inline(always)] - pub fn set_gpio23(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 23usize)) | (((val as u32) & 0x01) << 23usize); - } - #[inline(always)] - pub const fn gpio24(&self) -> bool { - let val = (self.0 >> 24usize) & 0x01; - val != 0 - } - #[inline(always)] - pub fn set_gpio24(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 24usize)) | (((val as u32) & 0x01) << 24usize); - } - #[inline(always)] - pub const fn gpio25(&self) -> bool { - let val = (self.0 >> 25usize) & 0x01; - val != 0 - } - #[inline(always)] - pub fn set_gpio25(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 25usize)) | (((val as u32) & 0x01) << 25usize); - } - #[inline(always)] - pub const fn gpio26(&self) -> bool { - let val = (self.0 >> 26usize) & 0x01; - val != 0 - } - #[inline(always)] - pub fn set_gpio26(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 26usize)) | (((val as u32) & 0x01) << 26usize); - } - #[inline(always)] - pub const fn gpio27(&self) -> bool { - let val = (self.0 >> 27usize) & 0x01; - val != 0 - } - #[inline(always)] - pub fn set_gpio27(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 27usize)) | (((val as u32) & 0x01) << 27usize); - } - #[inline(always)] - pub const fn gpio28(&self) -> bool { - let val = (self.0 >> 28usize) & 0x01; - val != 0 - } - #[inline(always)] - pub fn set_gpio28(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 28usize)) | (((val as u32) & 0x01) << 28usize); - } - #[inline(always)] - pub const fn gpio29(&self) -> bool { - let val = (self.0 >> 29usize) & 0x01; - val != 0 - } - #[inline(always)] - pub fn set_gpio29(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 29usize)) | (((val as u32) & 0x01) << 29usize); - } - #[inline(always)] - pub const fn gpio30(&self) -> bool { - let val = (self.0 >> 30usize) & 0x01; - val != 0 - } - #[inline(always)] - pub fn set_gpio30(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 30usize)) | (((val as u32) & 0x01) << 30usize); - } - #[inline(always)] - pub const fn gpio31(&self) -> bool { - let val = (self.0 >> 31usize) & 0x01; - val != 0 - } - #[inline(always)] - pub fn set_gpio31(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 31usize)) | (((val as u32) & 0x01) << 31usize); - } -} -impl Default for IrqsummaryProc0nonsecure0 { - #[inline(always)] - fn default() -> IrqsummaryProc0nonsecure0 { - IrqsummaryProc0nonsecure0(0) - } -} -#[repr(transparent)] -#[derive(Copy, Clone, Eq, PartialEq)] -pub struct IrqsummaryProc0nonsecure1(pub u32); -impl IrqsummaryProc0nonsecure1 { - #[inline(always)] - pub const fn gpio32(&self) -> bool { - let val = (self.0 >> 0usize) & 0x01; - val != 0 - } - #[inline(always)] - pub fn set_gpio32(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize); - } - #[inline(always)] - pub const fn gpio33(&self) -> bool { - let val = (self.0 >> 1usize) & 0x01; - val != 0 - } - #[inline(always)] - pub fn set_gpio33(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize); - } - #[inline(always)] - pub const fn gpio34(&self) -> bool { - let val = (self.0 >> 2usize) & 0x01; - val != 0 - } - #[inline(always)] - pub fn set_gpio34(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 2usize)) | (((val as u32) & 0x01) << 2usize); - } - #[inline(always)] - pub const fn gpio35(&self) -> bool { - let val = (self.0 >> 3usize) & 0x01; - val != 0 - } - #[inline(always)] - pub fn set_gpio35(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 3usize)) | (((val as u32) & 0x01) << 3usize); - } - #[inline(always)] - pub const fn gpio36(&self) -> bool { - let val = (self.0 >> 4usize) & 0x01; - val != 0 - } - #[inline(always)] - pub fn set_gpio36(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 4usize)) | (((val as u32) & 0x01) << 4usize); - } - #[inline(always)] - pub const fn gpio37(&self) -> bool { - let val = (self.0 >> 5usize) & 0x01; - val != 0 - } - #[inline(always)] - pub fn set_gpio37(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 5usize)) | (((val as u32) & 0x01) << 5usize); - } - #[inline(always)] - pub const fn gpio38(&self) -> bool { - let val = (self.0 >> 6usize) & 0x01; - val != 0 - } - #[inline(always)] - pub fn set_gpio38(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 6usize)) | (((val as u32) & 0x01) << 6usize); - } - #[inline(always)] - pub const fn gpio39(&self) -> bool { - let val = (self.0 >> 7usize) & 0x01; - val != 0 - } - #[inline(always)] - pub fn set_gpio39(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 7usize)) | (((val as u32) & 0x01) << 7usize); - } - #[inline(always)] - pub const fn gpio40(&self) -> bool { - let val = (self.0 >> 8usize) & 0x01; - val != 0 - } - #[inline(always)] - pub fn set_gpio40(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 8usize)) | (((val as u32) & 0x01) << 8usize); - } - #[inline(always)] - pub const fn gpio41(&self) -> bool { - let val = (self.0 >> 9usize) & 0x01; - val != 0 - } - #[inline(always)] - pub fn set_gpio41(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 9usize)) | (((val as u32) & 0x01) << 9usize); - } - #[inline(always)] - pub const fn gpio42(&self) -> bool { - let val = (self.0 >> 10usize) & 0x01; - val != 0 - } - #[inline(always)] - pub fn set_gpio42(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 10usize)) | (((val as u32) & 0x01) << 10usize); - } - #[inline(always)] - pub const fn gpio43(&self) -> bool { - let val = (self.0 >> 11usize) & 0x01; - val != 0 - } - #[inline(always)] - pub fn set_gpio43(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 11usize)) | (((val as u32) & 0x01) << 11usize); - } - #[inline(always)] - pub const fn gpio44(&self) -> bool { - let val = (self.0 >> 12usize) & 0x01; - val != 0 - } - #[inline(always)] - pub fn set_gpio44(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 12usize)) | (((val as u32) & 0x01) << 12usize); - } - #[inline(always)] - pub const fn gpio45(&self) -> bool { - let val = (self.0 >> 13usize) & 0x01; - val != 0 - } - #[inline(always)] - pub fn set_gpio45(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 13usize)) | (((val as u32) & 0x01) << 13usize); - } - #[inline(always)] - pub const fn gpio46(&self) -> bool { - let val = (self.0 >> 14usize) & 0x01; - val != 0 - } - #[inline(always)] - pub fn set_gpio46(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 14usize)) | (((val as u32) & 0x01) << 14usize); - } - #[inline(always)] - pub const fn gpio47(&self) -> bool { - let val = (self.0 >> 15usize) & 0x01; - val != 0 - } - #[inline(always)] - pub fn set_gpio47(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 15usize)) | (((val as u32) & 0x01) << 15usize); - } -} -impl Default for IrqsummaryProc0nonsecure1 { - #[inline(always)] - fn default() -> IrqsummaryProc0nonsecure1 { - IrqsummaryProc0nonsecure1(0) - } -} -#[repr(transparent)] -#[derive(Copy, Clone, Eq, PartialEq)] -pub struct IrqsummaryProc0secure0(pub u32); -impl IrqsummaryProc0secure0 { - #[inline(always)] - pub const fn gpio0(&self) -> bool { - let val = (self.0 >> 0usize) & 0x01; - val != 0 - } - #[inline(always)] - pub fn set_gpio0(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize); - } - #[inline(always)] - pub const fn gpio1(&self) -> bool { - let val = (self.0 >> 1usize) & 0x01; - val != 0 - } - #[inline(always)] - pub fn set_gpio1(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize); - } - #[inline(always)] - pub const fn gpio2(&self) -> bool { - let val = (self.0 >> 2usize) & 0x01; - val != 0 - } - #[inline(always)] - pub fn set_gpio2(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 2usize)) | (((val as u32) & 0x01) << 2usize); - } - #[inline(always)] - pub const fn gpio3(&self) -> bool { - let val = (self.0 >> 3usize) & 0x01; - val != 0 - } - #[inline(always)] - pub fn set_gpio3(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 3usize)) | (((val as u32) & 0x01) << 3usize); - } - #[inline(always)] - pub const fn gpio4(&self) -> bool { - let val = (self.0 >> 4usize) & 0x01; - val != 0 - } - #[inline(always)] - pub fn set_gpio4(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 4usize)) | (((val as u32) & 0x01) << 4usize); - } - #[inline(always)] - pub const fn gpio5(&self) -> bool { - let val = (self.0 >> 5usize) & 0x01; - val != 0 - } - #[inline(always)] - pub fn set_gpio5(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 5usize)) | (((val as u32) & 0x01) << 5usize); - } - #[inline(always)] - pub const fn gpio6(&self) -> bool { - let val = (self.0 >> 6usize) & 0x01; - val != 0 - } - #[inline(always)] - pub fn set_gpio6(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 6usize)) | (((val as u32) & 0x01) << 6usize); - } - #[inline(always)] - pub const fn gpio7(&self) -> bool { - let val = (self.0 >> 7usize) & 0x01; - val != 0 - } - #[inline(always)] - pub fn set_gpio7(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 7usize)) | (((val as u32) & 0x01) << 7usize); - } - #[inline(always)] - pub const fn gpio8(&self) -> bool { - let val = (self.0 >> 8usize) & 0x01; - val != 0 - } - #[inline(always)] - pub fn set_gpio8(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 8usize)) | (((val as u32) & 0x01) << 8usize); - } - #[inline(always)] - pub const fn gpio9(&self) -> bool { - let val = (self.0 >> 9usize) & 0x01; - val != 0 - } - #[inline(always)] - pub fn set_gpio9(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 9usize)) | (((val as u32) & 0x01) << 9usize); - } - #[inline(always)] - pub const fn gpio10(&self) -> bool { - let val = (self.0 >> 10usize) & 0x01; - val != 0 - } - #[inline(always)] - pub fn set_gpio10(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 10usize)) | (((val as u32) & 0x01) << 10usize); - } - #[inline(always)] - pub const fn gpio11(&self) -> bool { - let val = (self.0 >> 11usize) & 0x01; - val != 0 - } - #[inline(always)] - pub fn set_gpio11(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 11usize)) | (((val as u32) & 0x01) << 11usize); - } - #[inline(always)] - pub const fn gpio12(&self) -> bool { - let val = (self.0 >> 12usize) & 0x01; - val != 0 - } - #[inline(always)] - pub fn set_gpio12(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 12usize)) | (((val as u32) & 0x01) << 12usize); - } - #[inline(always)] - pub const fn gpio13(&self) -> bool { - let val = (self.0 >> 13usize) & 0x01; - val != 0 - } - #[inline(always)] - pub fn set_gpio13(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 13usize)) | (((val as u32) & 0x01) << 13usize); - } - #[inline(always)] - pub const fn gpio14(&self) -> bool { - let val = (self.0 >> 14usize) & 0x01; - val != 0 - } - #[inline(always)] - pub fn set_gpio14(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 14usize)) | (((val as u32) & 0x01) << 14usize); - } - #[inline(always)] - pub const fn gpio15(&self) -> bool { - let val = (self.0 >> 15usize) & 0x01; - val != 0 - } - #[inline(always)] - pub fn set_gpio15(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 15usize)) | (((val as u32) & 0x01) << 15usize); - } - #[inline(always)] - pub const fn gpio16(&self) -> bool { - let val = (self.0 >> 16usize) & 0x01; - val != 0 - } - #[inline(always)] - pub fn set_gpio16(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 16usize)) | (((val as u32) & 0x01) << 16usize); - } - #[inline(always)] - pub const fn gpio17(&self) -> bool { - let val = (self.0 >> 17usize) & 0x01; - val != 0 - } - #[inline(always)] - pub fn set_gpio17(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 17usize)) | (((val as u32) & 0x01) << 17usize); - } - #[inline(always)] - pub const fn gpio18(&self) -> bool { - let val = (self.0 >> 18usize) & 0x01; - val != 0 - } - #[inline(always)] - pub fn set_gpio18(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 18usize)) | (((val as u32) & 0x01) << 18usize); - } - #[inline(always)] - pub const fn gpio19(&self) -> bool { - let val = (self.0 >> 19usize) & 0x01; - val != 0 - } - #[inline(always)] - pub fn set_gpio19(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 19usize)) | (((val as u32) & 0x01) << 19usize); - } - #[inline(always)] - pub const fn gpio20(&self) -> bool { - let val = (self.0 >> 20usize) & 0x01; - val != 0 - } - #[inline(always)] - pub fn set_gpio20(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 20usize)) | (((val as u32) & 0x01) << 20usize); - } - #[inline(always)] - pub const fn gpio21(&self) -> bool { - let val = (self.0 >> 21usize) & 0x01; - val != 0 - } - #[inline(always)] - pub fn set_gpio21(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 21usize)) | (((val as u32) & 0x01) << 21usize); - } - #[inline(always)] - pub const fn gpio22(&self) -> bool { - let val = (self.0 >> 22usize) & 0x01; - val != 0 - } - #[inline(always)] - pub fn set_gpio22(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 22usize)) | (((val as u32) & 0x01) << 22usize); - } - #[inline(always)] - pub const fn gpio23(&self) -> bool { - let val = (self.0 >> 23usize) & 0x01; - val != 0 - } - #[inline(always)] - pub fn set_gpio23(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 23usize)) | (((val as u32) & 0x01) << 23usize); - } - #[inline(always)] - pub const fn gpio24(&self) -> bool { - let val = (self.0 >> 24usize) & 0x01; - val != 0 - } - #[inline(always)] - pub fn set_gpio24(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 24usize)) | (((val as u32) & 0x01) << 24usize); - } - #[inline(always)] - pub const fn gpio25(&self) -> bool { - let val = (self.0 >> 25usize) & 0x01; - val != 0 - } - #[inline(always)] - pub fn set_gpio25(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 25usize)) | (((val as u32) & 0x01) << 25usize); - } - #[inline(always)] - pub const fn gpio26(&self) -> bool { - let val = (self.0 >> 26usize) & 0x01; - val != 0 - } - #[inline(always)] - pub fn set_gpio26(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 26usize)) | (((val as u32) & 0x01) << 26usize); - } - #[inline(always)] - pub const fn gpio27(&self) -> bool { - let val = (self.0 >> 27usize) & 0x01; - val != 0 - } - #[inline(always)] - pub fn set_gpio27(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 27usize)) | (((val as u32) & 0x01) << 27usize); - } - #[inline(always)] - pub const fn gpio28(&self) -> bool { - let val = (self.0 >> 28usize) & 0x01; - val != 0 - } - #[inline(always)] - pub fn set_gpio28(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 28usize)) | (((val as u32) & 0x01) << 28usize); - } - #[inline(always)] - pub const fn gpio29(&self) -> bool { - let val = (self.0 >> 29usize) & 0x01; - val != 0 - } - #[inline(always)] - pub fn set_gpio29(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 29usize)) | (((val as u32) & 0x01) << 29usize); - } - #[inline(always)] - pub const fn gpio30(&self) -> bool { - let val = (self.0 >> 30usize) & 0x01; - val != 0 - } - #[inline(always)] - pub fn set_gpio30(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 30usize)) | (((val as u32) & 0x01) << 30usize); - } - #[inline(always)] - pub const fn gpio31(&self) -> bool { - let val = (self.0 >> 31usize) & 0x01; - val != 0 - } - #[inline(always)] - pub fn set_gpio31(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 31usize)) | (((val as u32) & 0x01) << 31usize); - } -} -impl Default for IrqsummaryProc0secure0 { - #[inline(always)] - fn default() -> IrqsummaryProc0secure0 { - IrqsummaryProc0secure0(0) - } -} -#[repr(transparent)] -#[derive(Copy, Clone, Eq, PartialEq)] -pub struct IrqsummaryProc0secure1(pub u32); -impl IrqsummaryProc0secure1 { - #[inline(always)] - pub const fn gpio32(&self) -> bool { - let val = (self.0 >> 0usize) & 0x01; - val != 0 - } - #[inline(always)] - pub fn set_gpio32(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize); - } - #[inline(always)] - pub const fn gpio33(&self) -> bool { - let val = (self.0 >> 1usize) & 0x01; - val != 0 - } - #[inline(always)] - pub fn set_gpio33(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize); - } - #[inline(always)] - pub const fn gpio34(&self) -> bool { - let val = (self.0 >> 2usize) & 0x01; - val != 0 - } - #[inline(always)] - pub fn set_gpio34(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 2usize)) | (((val as u32) & 0x01) << 2usize); - } - #[inline(always)] - pub const fn gpio35(&self) -> bool { - let val = (self.0 >> 3usize) & 0x01; - val != 0 - } - #[inline(always)] - pub fn set_gpio35(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 3usize)) | (((val as u32) & 0x01) << 3usize); - } - #[inline(always)] - pub const fn gpio36(&self) -> bool { - let val = (self.0 >> 4usize) & 0x01; - val != 0 - } - #[inline(always)] - pub fn set_gpio36(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 4usize)) | (((val as u32) & 0x01) << 4usize); - } - #[inline(always)] - pub const fn gpio37(&self) -> bool { - let val = (self.0 >> 5usize) & 0x01; - val != 0 - } - #[inline(always)] - pub fn set_gpio37(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 5usize)) | (((val as u32) & 0x01) << 5usize); - } - #[inline(always)] - pub const fn gpio38(&self) -> bool { - let val = (self.0 >> 6usize) & 0x01; - val != 0 - } - #[inline(always)] - pub fn set_gpio38(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 6usize)) | (((val as u32) & 0x01) << 6usize); - } - #[inline(always)] - pub const fn gpio39(&self) -> bool { - let val = (self.0 >> 7usize) & 0x01; - val != 0 - } - #[inline(always)] - pub fn set_gpio39(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 7usize)) | (((val as u32) & 0x01) << 7usize); - } - #[inline(always)] - pub const fn gpio40(&self) -> bool { - let val = (self.0 >> 8usize) & 0x01; - val != 0 - } - #[inline(always)] - pub fn set_gpio40(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 8usize)) | (((val as u32) & 0x01) << 8usize); - } - #[inline(always)] - pub const fn gpio41(&self) -> bool { - let val = (self.0 >> 9usize) & 0x01; - val != 0 - } - #[inline(always)] - pub fn set_gpio41(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 9usize)) | (((val as u32) & 0x01) << 9usize); - } - #[inline(always)] - pub const fn gpio42(&self) -> bool { - let val = (self.0 >> 10usize) & 0x01; - val != 0 - } - #[inline(always)] - pub fn set_gpio42(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 10usize)) | (((val as u32) & 0x01) << 10usize); - } - #[inline(always)] - pub const fn gpio43(&self) -> bool { - let val = (self.0 >> 11usize) & 0x01; - val != 0 - } - #[inline(always)] - pub fn set_gpio43(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 11usize)) | (((val as u32) & 0x01) << 11usize); - } - #[inline(always)] - pub const fn gpio44(&self) -> bool { - let val = (self.0 >> 12usize) & 0x01; - val != 0 - } - #[inline(always)] - pub fn set_gpio44(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 12usize)) | (((val as u32) & 0x01) << 12usize); - } - #[inline(always)] - pub const fn gpio45(&self) -> bool { - let val = (self.0 >> 13usize) & 0x01; - val != 0 - } - #[inline(always)] - pub fn set_gpio45(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 13usize)) | (((val as u32) & 0x01) << 13usize); - } - #[inline(always)] - pub const fn gpio46(&self) -> bool { - let val = (self.0 >> 14usize) & 0x01; - val != 0 - } - #[inline(always)] - pub fn set_gpio46(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 14usize)) | (((val as u32) & 0x01) << 14usize); - } - #[inline(always)] - pub const fn gpio47(&self) -> bool { - let val = (self.0 >> 15usize) & 0x01; - val != 0 - } - #[inline(always)] - pub fn set_gpio47(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 15usize)) | (((val as u32) & 0x01) << 15usize); - } -} -impl Default for IrqsummaryProc0secure1 { - #[inline(always)] - fn default() -> IrqsummaryProc0secure1 { - IrqsummaryProc0secure1(0) - } -} -#[repr(transparent)] -#[derive(Copy, Clone, Eq, PartialEq)] -pub struct IrqsummaryProc1nonsecure0(pub u32); -impl IrqsummaryProc1nonsecure0 { - #[inline(always)] - pub const fn gpio0(&self) -> bool { - let val = (self.0 >> 0usize) & 0x01; - val != 0 - } - #[inline(always)] - pub fn set_gpio0(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize); - } - #[inline(always)] - pub const fn gpio1(&self) -> bool { - let val = (self.0 >> 1usize) & 0x01; - val != 0 - } - #[inline(always)] - pub fn set_gpio1(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize); - } - #[inline(always)] - pub const fn gpio2(&self) -> bool { - let val = (self.0 >> 2usize) & 0x01; - val != 0 - } - #[inline(always)] - pub fn set_gpio2(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 2usize)) | (((val as u32) & 0x01) << 2usize); - } - #[inline(always)] - pub const fn gpio3(&self) -> bool { - let val = (self.0 >> 3usize) & 0x01; - val != 0 - } - #[inline(always)] - pub fn set_gpio3(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 3usize)) | (((val as u32) & 0x01) << 3usize); - } - #[inline(always)] - pub const fn gpio4(&self) -> bool { - let val = (self.0 >> 4usize) & 0x01; - val != 0 - } - #[inline(always)] - pub fn set_gpio4(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 4usize)) | (((val as u32) & 0x01) << 4usize); - } - #[inline(always)] - pub const fn gpio5(&self) -> bool { - let val = (self.0 >> 5usize) & 0x01; - val != 0 - } - #[inline(always)] - pub fn set_gpio5(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 5usize)) | (((val as u32) & 0x01) << 5usize); - } - #[inline(always)] - pub const fn gpio6(&self) -> bool { - let val = (self.0 >> 6usize) & 0x01; - val != 0 - } - #[inline(always)] - pub fn set_gpio6(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 6usize)) | (((val as u32) & 0x01) << 6usize); - } - #[inline(always)] - pub const fn gpio7(&self) -> bool { - let val = (self.0 >> 7usize) & 0x01; - val != 0 - } - #[inline(always)] - pub fn set_gpio7(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 7usize)) | (((val as u32) & 0x01) << 7usize); - } - #[inline(always)] - pub const fn gpio8(&self) -> bool { - let val = (self.0 >> 8usize) & 0x01; - val != 0 - } - #[inline(always)] - pub fn set_gpio8(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 8usize)) | (((val as u32) & 0x01) << 8usize); - } - #[inline(always)] - pub const fn gpio9(&self) -> bool { - let val = (self.0 >> 9usize) & 0x01; - val != 0 - } - #[inline(always)] - pub fn set_gpio9(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 9usize)) | (((val as u32) & 0x01) << 9usize); - } - #[inline(always)] - pub const fn gpio10(&self) -> bool { - let val = (self.0 >> 10usize) & 0x01; - val != 0 - } - #[inline(always)] - pub fn set_gpio10(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 10usize)) | (((val as u32) & 0x01) << 10usize); - } - #[inline(always)] - pub const fn gpio11(&self) -> bool { - let val = (self.0 >> 11usize) & 0x01; - val != 0 - } - #[inline(always)] - pub fn set_gpio11(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 11usize)) | (((val as u32) & 0x01) << 11usize); - } - #[inline(always)] - pub const fn gpio12(&self) -> bool { - let val = (self.0 >> 12usize) & 0x01; - val != 0 - } - #[inline(always)] - pub fn set_gpio12(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 12usize)) | (((val as u32) & 0x01) << 12usize); - } - #[inline(always)] - pub const fn gpio13(&self) -> bool { - let val = (self.0 >> 13usize) & 0x01; - val != 0 - } - #[inline(always)] - pub fn set_gpio13(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 13usize)) | (((val as u32) & 0x01) << 13usize); - } - #[inline(always)] - pub const fn gpio14(&self) -> bool { - let val = (self.0 >> 14usize) & 0x01; - val != 0 - } - #[inline(always)] - pub fn set_gpio14(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 14usize)) | (((val as u32) & 0x01) << 14usize); - } - #[inline(always)] - pub const fn gpio15(&self) -> bool { - let val = (self.0 >> 15usize) & 0x01; - val != 0 - } - #[inline(always)] - pub fn set_gpio15(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 15usize)) | (((val as u32) & 0x01) << 15usize); - } - #[inline(always)] - pub const fn gpio16(&self) -> bool { - let val = (self.0 >> 16usize) & 0x01; - val != 0 - } - #[inline(always)] - pub fn set_gpio16(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 16usize)) | (((val as u32) & 0x01) << 16usize); - } - #[inline(always)] - pub const fn gpio17(&self) -> bool { - let val = (self.0 >> 17usize) & 0x01; - val != 0 - } - #[inline(always)] - pub fn set_gpio17(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 17usize)) | (((val as u32) & 0x01) << 17usize); - } - #[inline(always)] - pub const fn gpio18(&self) -> bool { - let val = (self.0 >> 18usize) & 0x01; - val != 0 - } - #[inline(always)] - pub fn set_gpio18(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 18usize)) | (((val as u32) & 0x01) << 18usize); - } - #[inline(always)] - pub const fn gpio19(&self) -> bool { - let val = (self.0 >> 19usize) & 0x01; - val != 0 - } - #[inline(always)] - pub fn set_gpio19(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 19usize)) | (((val as u32) & 0x01) << 19usize); - } - #[inline(always)] - pub const fn gpio20(&self) -> bool { - let val = (self.0 >> 20usize) & 0x01; - val != 0 - } - #[inline(always)] - pub fn set_gpio20(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 20usize)) | (((val as u32) & 0x01) << 20usize); - } - #[inline(always)] - pub const fn gpio21(&self) -> bool { - let val = (self.0 >> 21usize) & 0x01; - val != 0 - } - #[inline(always)] - pub fn set_gpio21(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 21usize)) | (((val as u32) & 0x01) << 21usize); - } - #[inline(always)] - pub const fn gpio22(&self) -> bool { - let val = (self.0 >> 22usize) & 0x01; - val != 0 - } - #[inline(always)] - pub fn set_gpio22(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 22usize)) | (((val as u32) & 0x01) << 22usize); - } - #[inline(always)] - pub const fn gpio23(&self) -> bool { - let val = (self.0 >> 23usize) & 0x01; - val != 0 - } - #[inline(always)] - pub fn set_gpio23(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 23usize)) | (((val as u32) & 0x01) << 23usize); - } - #[inline(always)] - pub const fn gpio24(&self) -> bool { - let val = (self.0 >> 24usize) & 0x01; - val != 0 - } - #[inline(always)] - pub fn set_gpio24(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 24usize)) | (((val as u32) & 0x01) << 24usize); - } - #[inline(always)] - pub const fn gpio25(&self) -> bool { - let val = (self.0 >> 25usize) & 0x01; - val != 0 - } - #[inline(always)] - pub fn set_gpio25(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 25usize)) | (((val as u32) & 0x01) << 25usize); - } - #[inline(always)] - pub const fn gpio26(&self) -> bool { - let val = (self.0 >> 26usize) & 0x01; - val != 0 - } - #[inline(always)] - pub fn set_gpio26(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 26usize)) | (((val as u32) & 0x01) << 26usize); - } - #[inline(always)] - pub const fn gpio27(&self) -> bool { - let val = (self.0 >> 27usize) & 0x01; - val != 0 - } - #[inline(always)] - pub fn set_gpio27(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 27usize)) | (((val as u32) & 0x01) << 27usize); - } - #[inline(always)] - pub const fn gpio28(&self) -> bool { - let val = (self.0 >> 28usize) & 0x01; - val != 0 - } - #[inline(always)] - pub fn set_gpio28(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 28usize)) | (((val as u32) & 0x01) << 28usize); - } - #[inline(always)] - pub const fn gpio29(&self) -> bool { - let val = (self.0 >> 29usize) & 0x01; - val != 0 - } - #[inline(always)] - pub fn set_gpio29(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 29usize)) | (((val as u32) & 0x01) << 29usize); - } - #[inline(always)] - pub const fn gpio30(&self) -> bool { - let val = (self.0 >> 30usize) & 0x01; - val != 0 - } - #[inline(always)] - pub fn set_gpio30(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 30usize)) | (((val as u32) & 0x01) << 30usize); - } - #[inline(always)] - pub const fn gpio31(&self) -> bool { - let val = (self.0 >> 31usize) & 0x01; - val != 0 - } - #[inline(always)] - pub fn set_gpio31(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 31usize)) | (((val as u32) & 0x01) << 31usize); - } -} -impl Default for IrqsummaryProc1nonsecure0 { - #[inline(always)] - fn default() -> IrqsummaryProc1nonsecure0 { - IrqsummaryProc1nonsecure0(0) - } -} -#[repr(transparent)] -#[derive(Copy, Clone, Eq, PartialEq)] -pub struct IrqsummaryProc1nonsecure1(pub u32); -impl IrqsummaryProc1nonsecure1 { - #[inline(always)] - pub const fn gpio32(&self) -> bool { - let val = (self.0 >> 0usize) & 0x01; - val != 0 - } - #[inline(always)] - pub fn set_gpio32(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize); - } - #[inline(always)] - pub const fn gpio33(&self) -> bool { - let val = (self.0 >> 1usize) & 0x01; - val != 0 - } - #[inline(always)] - pub fn set_gpio33(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize); - } - #[inline(always)] - pub const fn gpio34(&self) -> bool { - let val = (self.0 >> 2usize) & 0x01; - val != 0 - } - #[inline(always)] - pub fn set_gpio34(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 2usize)) | (((val as u32) & 0x01) << 2usize); - } - #[inline(always)] - pub const fn gpio35(&self) -> bool { - let val = (self.0 >> 3usize) & 0x01; - val != 0 - } - #[inline(always)] - pub fn set_gpio35(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 3usize)) | (((val as u32) & 0x01) << 3usize); - } - #[inline(always)] - pub const fn gpio36(&self) -> bool { - let val = (self.0 >> 4usize) & 0x01; - val != 0 - } - #[inline(always)] - pub fn set_gpio36(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 4usize)) | (((val as u32) & 0x01) << 4usize); - } - #[inline(always)] - pub const fn gpio37(&self) -> bool { - let val = (self.0 >> 5usize) & 0x01; - val != 0 - } - #[inline(always)] - pub fn set_gpio37(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 5usize)) | (((val as u32) & 0x01) << 5usize); - } - #[inline(always)] - pub const fn gpio38(&self) -> bool { - let val = (self.0 >> 6usize) & 0x01; - val != 0 - } - #[inline(always)] - pub fn set_gpio38(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 6usize)) | (((val as u32) & 0x01) << 6usize); - } - #[inline(always)] - pub const fn gpio39(&self) -> bool { - let val = (self.0 >> 7usize) & 0x01; - val != 0 - } - #[inline(always)] - pub fn set_gpio39(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 7usize)) | (((val as u32) & 0x01) << 7usize); - } - #[inline(always)] - pub const fn gpio40(&self) -> bool { - let val = (self.0 >> 8usize) & 0x01; - val != 0 - } - #[inline(always)] - pub fn set_gpio40(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 8usize)) | (((val as u32) & 0x01) << 8usize); - } - #[inline(always)] - pub const fn gpio41(&self) -> bool { - let val = (self.0 >> 9usize) & 0x01; - val != 0 - } - #[inline(always)] - pub fn set_gpio41(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 9usize)) | (((val as u32) & 0x01) << 9usize); - } - #[inline(always)] - pub const fn gpio42(&self) -> bool { - let val = (self.0 >> 10usize) & 0x01; - val != 0 - } - #[inline(always)] - pub fn set_gpio42(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 10usize)) | (((val as u32) & 0x01) << 10usize); - } - #[inline(always)] - pub const fn gpio43(&self) -> bool { - let val = (self.0 >> 11usize) & 0x01; - val != 0 - } - #[inline(always)] - pub fn set_gpio43(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 11usize)) | (((val as u32) & 0x01) << 11usize); - } - #[inline(always)] - pub const fn gpio44(&self) -> bool { - let val = (self.0 >> 12usize) & 0x01; - val != 0 - } - #[inline(always)] - pub fn set_gpio44(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 12usize)) | (((val as u32) & 0x01) << 12usize); - } - #[inline(always)] - pub const fn gpio45(&self) -> bool { - let val = (self.0 >> 13usize) & 0x01; - val != 0 - } - #[inline(always)] - pub fn set_gpio45(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 13usize)) | (((val as u32) & 0x01) << 13usize); - } - #[inline(always)] - pub const fn gpio46(&self) -> bool { - let val = (self.0 >> 14usize) & 0x01; - val != 0 - } - #[inline(always)] - pub fn set_gpio46(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 14usize)) | (((val as u32) & 0x01) << 14usize); - } - #[inline(always)] - pub const fn gpio47(&self) -> bool { - let val = (self.0 >> 15usize) & 0x01; - val != 0 - } - #[inline(always)] - pub fn set_gpio47(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 15usize)) | (((val as u32) & 0x01) << 15usize); - } -} -impl Default for IrqsummaryProc1nonsecure1 { - #[inline(always)] - fn default() -> IrqsummaryProc1nonsecure1 { - IrqsummaryProc1nonsecure1(0) - } -} -#[repr(transparent)] -#[derive(Copy, Clone, Eq, PartialEq)] -pub struct IrqsummaryProc1secure0(pub u32); -impl IrqsummaryProc1secure0 { - #[inline(always)] - pub const fn gpio0(&self) -> bool { - let val = (self.0 >> 0usize) & 0x01; - val != 0 - } - #[inline(always)] - pub fn set_gpio0(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize); - } - #[inline(always)] - pub const fn gpio1(&self) -> bool { - let val = (self.0 >> 1usize) & 0x01; - val != 0 - } - #[inline(always)] - pub fn set_gpio1(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize); - } - #[inline(always)] - pub const fn gpio2(&self) -> bool { - let val = (self.0 >> 2usize) & 0x01; - val != 0 - } - #[inline(always)] - pub fn set_gpio2(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 2usize)) | (((val as u32) & 0x01) << 2usize); - } - #[inline(always)] - pub const fn gpio3(&self) -> bool { - let val = (self.0 >> 3usize) & 0x01; - val != 0 - } - #[inline(always)] - pub fn set_gpio3(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 3usize)) | (((val as u32) & 0x01) << 3usize); - } - #[inline(always)] - pub const fn gpio4(&self) -> bool { - let val = (self.0 >> 4usize) & 0x01; - val != 0 - } - #[inline(always)] - pub fn set_gpio4(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 4usize)) | (((val as u32) & 0x01) << 4usize); - } - #[inline(always)] - pub const fn gpio5(&self) -> bool { - let val = (self.0 >> 5usize) & 0x01; - val != 0 - } - #[inline(always)] - pub fn set_gpio5(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 5usize)) | (((val as u32) & 0x01) << 5usize); - } - #[inline(always)] - pub const fn gpio6(&self) -> bool { - let val = (self.0 >> 6usize) & 0x01; - val != 0 - } - #[inline(always)] - pub fn set_gpio6(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 6usize)) | (((val as u32) & 0x01) << 6usize); - } - #[inline(always)] - pub const fn gpio7(&self) -> bool { - let val = (self.0 >> 7usize) & 0x01; - val != 0 - } - #[inline(always)] - pub fn set_gpio7(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 7usize)) | (((val as u32) & 0x01) << 7usize); - } - #[inline(always)] - pub const fn gpio8(&self) -> bool { - let val = (self.0 >> 8usize) & 0x01; - val != 0 - } - #[inline(always)] - pub fn set_gpio8(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 8usize)) | (((val as u32) & 0x01) << 8usize); - } - #[inline(always)] - pub const fn gpio9(&self) -> bool { - let val = (self.0 >> 9usize) & 0x01; - val != 0 - } - #[inline(always)] - pub fn set_gpio9(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 9usize)) | (((val as u32) & 0x01) << 9usize); - } - #[inline(always)] - pub const fn gpio10(&self) -> bool { - let val = (self.0 >> 10usize) & 0x01; - val != 0 - } - #[inline(always)] - pub fn set_gpio10(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 10usize)) | (((val as u32) & 0x01) << 10usize); - } - #[inline(always)] - pub const fn gpio11(&self) -> bool { - let val = (self.0 >> 11usize) & 0x01; - val != 0 - } - #[inline(always)] - pub fn set_gpio11(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 11usize)) | (((val as u32) & 0x01) << 11usize); - } - #[inline(always)] - pub const fn gpio12(&self) -> bool { - let val = (self.0 >> 12usize) & 0x01; - val != 0 - } - #[inline(always)] - pub fn set_gpio12(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 12usize)) | (((val as u32) & 0x01) << 12usize); - } - #[inline(always)] - pub const fn gpio13(&self) -> bool { - let val = (self.0 >> 13usize) & 0x01; - val != 0 - } - #[inline(always)] - pub fn set_gpio13(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 13usize)) | (((val as u32) & 0x01) << 13usize); - } - #[inline(always)] - pub const fn gpio14(&self) -> bool { - let val = (self.0 >> 14usize) & 0x01; - val != 0 - } - #[inline(always)] - pub fn set_gpio14(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 14usize)) | (((val as u32) & 0x01) << 14usize); - } - #[inline(always)] - pub const fn gpio15(&self) -> bool { - let val = (self.0 >> 15usize) & 0x01; - val != 0 - } - #[inline(always)] - pub fn set_gpio15(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 15usize)) | (((val as u32) & 0x01) << 15usize); - } - #[inline(always)] - pub const fn gpio16(&self) -> bool { - let val = (self.0 >> 16usize) & 0x01; - val != 0 - } - #[inline(always)] - pub fn set_gpio16(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 16usize)) | (((val as u32) & 0x01) << 16usize); - } - #[inline(always)] - pub const fn gpio17(&self) -> bool { - let val = (self.0 >> 17usize) & 0x01; - val != 0 - } - #[inline(always)] - pub fn set_gpio17(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 17usize)) | (((val as u32) & 0x01) << 17usize); - } - #[inline(always)] - pub const fn gpio18(&self) -> bool { - let val = (self.0 >> 18usize) & 0x01; - val != 0 - } - #[inline(always)] - pub fn set_gpio18(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 18usize)) | (((val as u32) & 0x01) << 18usize); - } - #[inline(always)] - pub const fn gpio19(&self) -> bool { - let val = (self.0 >> 19usize) & 0x01; - val != 0 - } - #[inline(always)] - pub fn set_gpio19(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 19usize)) | (((val as u32) & 0x01) << 19usize); - } - #[inline(always)] - pub const fn gpio20(&self) -> bool { - let val = (self.0 >> 20usize) & 0x01; - val != 0 - } - #[inline(always)] - pub fn set_gpio20(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 20usize)) | (((val as u32) & 0x01) << 20usize); - } - #[inline(always)] - pub const fn gpio21(&self) -> bool { - let val = (self.0 >> 21usize) & 0x01; - val != 0 - } - #[inline(always)] - pub fn set_gpio21(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 21usize)) | (((val as u32) & 0x01) << 21usize); - } - #[inline(always)] - pub const fn gpio22(&self) -> bool { - let val = (self.0 >> 22usize) & 0x01; - val != 0 - } - #[inline(always)] - pub fn set_gpio22(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 22usize)) | (((val as u32) & 0x01) << 22usize); - } - #[inline(always)] - pub const fn gpio23(&self) -> bool { - let val = (self.0 >> 23usize) & 0x01; - val != 0 - } - #[inline(always)] - pub fn set_gpio23(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 23usize)) | (((val as u32) & 0x01) << 23usize); - } - #[inline(always)] - pub const fn gpio24(&self) -> bool { - let val = (self.0 >> 24usize) & 0x01; - val != 0 - } - #[inline(always)] - pub fn set_gpio24(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 24usize)) | (((val as u32) & 0x01) << 24usize); - } - #[inline(always)] - pub const fn gpio25(&self) -> bool { - let val = (self.0 >> 25usize) & 0x01; - val != 0 - } - #[inline(always)] - pub fn set_gpio25(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 25usize)) | (((val as u32) & 0x01) << 25usize); - } - #[inline(always)] - pub const fn gpio26(&self) -> bool { - let val = (self.0 >> 26usize) & 0x01; - val != 0 - } - #[inline(always)] - pub fn set_gpio26(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 26usize)) | (((val as u32) & 0x01) << 26usize); - } - #[inline(always)] - pub const fn gpio27(&self) -> bool { - let val = (self.0 >> 27usize) & 0x01; - val != 0 - } - #[inline(always)] - pub fn set_gpio27(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 27usize)) | (((val as u32) & 0x01) << 27usize); - } - #[inline(always)] - pub const fn gpio28(&self) -> bool { - let val = (self.0 >> 28usize) & 0x01; - val != 0 - } - #[inline(always)] - pub fn set_gpio28(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 28usize)) | (((val as u32) & 0x01) << 28usize); - } - #[inline(always)] - pub const fn gpio29(&self) -> bool { - let val = (self.0 >> 29usize) & 0x01; - val != 0 - } - #[inline(always)] - pub fn set_gpio29(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 29usize)) | (((val as u32) & 0x01) << 29usize); - } - #[inline(always)] - pub const fn gpio30(&self) -> bool { - let val = (self.0 >> 30usize) & 0x01; - val != 0 - } - #[inline(always)] - pub fn set_gpio30(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 30usize)) | (((val as u32) & 0x01) << 30usize); - } - #[inline(always)] - pub const fn gpio31(&self) -> bool { - let val = (self.0 >> 31usize) & 0x01; - val != 0 - } - #[inline(always)] - pub fn set_gpio31(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 31usize)) | (((val as u32) & 0x01) << 31usize); - } -} -impl Default for IrqsummaryProc1secure0 { - #[inline(always)] - fn default() -> IrqsummaryProc1secure0 { - IrqsummaryProc1secure0(0) - } -} -#[repr(transparent)] -#[derive(Copy, Clone, Eq, PartialEq)] -pub struct IrqsummaryProc1secure1(pub u32); -impl IrqsummaryProc1secure1 { - #[inline(always)] - pub const fn gpio32(&self) -> bool { - let val = (self.0 >> 0usize) & 0x01; - val != 0 - } - #[inline(always)] - pub fn set_gpio32(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize); - } - #[inline(always)] - pub const fn gpio33(&self) -> bool { - let val = (self.0 >> 1usize) & 0x01; - val != 0 - } - #[inline(always)] - pub fn set_gpio33(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize); - } - #[inline(always)] - pub const fn gpio34(&self) -> bool { - let val = (self.0 >> 2usize) & 0x01; - val != 0 - } - #[inline(always)] - pub fn set_gpio34(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 2usize)) | (((val as u32) & 0x01) << 2usize); - } - #[inline(always)] - pub const fn gpio35(&self) -> bool { - let val = (self.0 >> 3usize) & 0x01; - val != 0 - } - #[inline(always)] - pub fn set_gpio35(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 3usize)) | (((val as u32) & 0x01) << 3usize); - } - #[inline(always)] - pub const fn gpio36(&self) -> bool { - let val = (self.0 >> 4usize) & 0x01; - val != 0 - } - #[inline(always)] - pub fn set_gpio36(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 4usize)) | (((val as u32) & 0x01) << 4usize); - } - #[inline(always)] - pub const fn gpio37(&self) -> bool { - let val = (self.0 >> 5usize) & 0x01; - val != 0 - } - #[inline(always)] - pub fn set_gpio37(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 5usize)) | (((val as u32) & 0x01) << 5usize); - } - #[inline(always)] - pub const fn gpio38(&self) -> bool { - let val = (self.0 >> 6usize) & 0x01; - val != 0 - } - #[inline(always)] - pub fn set_gpio38(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 6usize)) | (((val as u32) & 0x01) << 6usize); - } - #[inline(always)] - pub const fn gpio39(&self) -> bool { - let val = (self.0 >> 7usize) & 0x01; - val != 0 - } - #[inline(always)] - pub fn set_gpio39(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 7usize)) | (((val as u32) & 0x01) << 7usize); - } - #[inline(always)] - pub const fn gpio40(&self) -> bool { - let val = (self.0 >> 8usize) & 0x01; - val != 0 - } - #[inline(always)] - pub fn set_gpio40(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 8usize)) | (((val as u32) & 0x01) << 8usize); - } - #[inline(always)] - pub const fn gpio41(&self) -> bool { - let val = (self.0 >> 9usize) & 0x01; - val != 0 - } - #[inline(always)] - pub fn set_gpio41(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 9usize)) | (((val as u32) & 0x01) << 9usize); - } - #[inline(always)] - pub const fn gpio42(&self) -> bool { - let val = (self.0 >> 10usize) & 0x01; - val != 0 - } - #[inline(always)] - pub fn set_gpio42(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 10usize)) | (((val as u32) & 0x01) << 10usize); - } - #[inline(always)] - pub const fn gpio43(&self) -> bool { - let val = (self.0 >> 11usize) & 0x01; - val != 0 - } - #[inline(always)] - pub fn set_gpio43(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 11usize)) | (((val as u32) & 0x01) << 11usize); - } - #[inline(always)] - pub const fn gpio44(&self) -> bool { - let val = (self.0 >> 12usize) & 0x01; - val != 0 - } - #[inline(always)] - pub fn set_gpio44(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 12usize)) | (((val as u32) & 0x01) << 12usize); - } - #[inline(always)] - pub const fn gpio45(&self) -> bool { - let val = (self.0 >> 13usize) & 0x01; - val != 0 - } - #[inline(always)] - pub fn set_gpio45(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 13usize)) | (((val as u32) & 0x01) << 13usize); - } - #[inline(always)] - pub const fn gpio46(&self) -> bool { - let val = (self.0 >> 14usize) & 0x01; - val != 0 - } - #[inline(always)] - pub fn set_gpio46(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 14usize)) | (((val as u32) & 0x01) << 14usize); - } - #[inline(always)] - pub const fn gpio47(&self) -> bool { - let val = (self.0 >> 15usize) & 0x01; - val != 0 - } - #[inline(always)] - pub fn set_gpio47(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 15usize)) | (((val as u32) & 0x01) << 15usize); - } -} -impl Default for IrqsummaryProc1secure1 { - #[inline(always)] - fn default() -> IrqsummaryProc1secure1 { - IrqsummaryProc1secure1(0) - } -} diff --git a/src/rp235x/io/vals.rs b/src/rp235x/io/vals.rs index 49b2970e..1d2f50c6 100644 --- a/src/rp235x/io/vals.rs +++ b/src/rp235x/io/vals.rs @@ -1,7 +1,7 @@ #[repr(u8)] #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] pub enum Gpio0ctrlFuncsel { - JTAG_TCK = 0, + JTAG_TCK = 0x0, SPI0_RX = 0x01, UART0_TX = 0x02, I2C0_SDA = 0x03, @@ -59,7 +59,7 @@ impl From for u8 { #[repr(u8)] #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] pub enum Gpio10ctrlFuncsel { - _RESERVED_0 = 0, + _RESERVED_0 = 0x0, SPI1_SCLK = 0x01, UART1_CTS = 0x02, I2C1_SDA = 0x03, @@ -117,7 +117,7 @@ impl From for u8 { #[repr(u8)] #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] pub enum Gpio11ctrlFuncsel { - _RESERVED_0 = 0, + _RESERVED_0 = 0x0, SPI1_TX = 0x01, UART1_RTS = 0x02, I2C1_SCL = 0x03, @@ -175,7 +175,7 @@ impl From for u8 { #[repr(u8)] #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] pub enum Gpio12ctrlFuncsel { - HSTX_0 = 0, + HSTX_0 = 0x0, SPI1_RX = 0x01, UART0_TX = 0x02, I2C0_SDA = 0x03, @@ -233,7 +233,7 @@ impl From for u8 { #[repr(u8)] #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] pub enum Gpio13ctrlFuncsel { - HSTX_1 = 0, + HSTX_1 = 0x0, SPI1_SS_N = 0x01, UART0_RX = 0x02, I2C0_SCL = 0x03, @@ -291,7 +291,7 @@ impl From for u8 { #[repr(u8)] #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] pub enum Gpio14ctrlFuncsel { - HSTX_2 = 0, + HSTX_2 = 0x0, SPI1_SCLK = 0x01, UART0_CTS = 0x02, I2C1_SDA = 0x03, @@ -349,7 +349,7 @@ impl From for u8 { #[repr(u8)] #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] pub enum Gpio15ctrlFuncsel { - HSTX_3 = 0, + HSTX_3 = 0x0, SPI1_TX = 0x01, UART0_RTS = 0x02, I2C1_SCL = 0x03, @@ -407,7 +407,7 @@ impl From for u8 { #[repr(u8)] #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] pub enum Gpio16ctrlFuncsel { - HSTX_4 = 0, + HSTX_4 = 0x0, SPI0_RX = 0x01, UART0_TX = 0x02, I2C0_SDA = 0x03, @@ -465,7 +465,7 @@ impl From for u8 { #[repr(u8)] #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] pub enum Gpio17ctrlFuncsel { - HSTX_5 = 0, + HSTX_5 = 0x0, SPI0_SS_N = 0x01, UART0_RX = 0x02, I2C0_SCL = 0x03, @@ -523,7 +523,7 @@ impl From for u8 { #[repr(u8)] #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] pub enum Gpio18ctrlFuncsel { - HSTX_6 = 0, + HSTX_6 = 0x0, SPI0_SCLK = 0x01, UART0_CTS = 0x02, I2C1_SDA = 0x03, @@ -581,7 +581,7 @@ impl From for u8 { #[repr(u8)] #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] pub enum Gpio19ctrlFuncsel { - HSTX_7 = 0, + HSTX_7 = 0x0, SPI0_TX = 0x01, UART0_RTS = 0x02, I2C1_SCL = 0x03, @@ -639,7 +639,7 @@ impl From for u8 { #[repr(u8)] #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] pub enum Gpio1ctrlFuncsel { - JTAG_TMS = 0, + JTAG_TMS = 0x0, SPI0_SS_N = 0x01, UART0_RX = 0x02, I2C0_SCL = 0x03, @@ -697,7 +697,7 @@ impl From for u8 { #[repr(u8)] #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] pub enum Gpio20ctrlFuncsel { - _RESERVED_0 = 0, + _RESERVED_0 = 0x0, SPI0_RX = 0x01, UART1_TX = 0x02, I2C0_SDA = 0x03, @@ -755,7 +755,7 @@ impl From for u8 { #[repr(u8)] #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] pub enum Gpio21ctrlFuncsel { - _RESERVED_0 = 0, + _RESERVED_0 = 0x0, SPI0_SS_N = 0x01, UART1_RX = 0x02, I2C0_SCL = 0x03, @@ -813,7 +813,7 @@ impl From for u8 { #[repr(u8)] #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] pub enum Gpio22ctrlFuncsel { - _RESERVED_0 = 0, + _RESERVED_0 = 0x0, SPI0_SCLK = 0x01, UART1_CTS = 0x02, I2C1_SDA = 0x03, @@ -871,7 +871,7 @@ impl From for u8 { #[repr(u8)] #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] pub enum Gpio23ctrlFuncsel { - _RESERVED_0 = 0, + _RESERVED_0 = 0x0, SPI0_TX = 0x01, UART1_RTS = 0x02, I2C1_SCL = 0x03, @@ -929,7 +929,7 @@ impl From for u8 { #[repr(u8)] #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] pub enum Gpio24ctrlFuncsel { - _RESERVED_0 = 0, + _RESERVED_0 = 0x0, SPI1_RX = 0x01, UART1_TX = 0x02, I2C0_SDA = 0x03, @@ -987,7 +987,7 @@ impl From for u8 { #[repr(u8)] #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] pub enum Gpio25ctrlFuncsel { - _RESERVED_0 = 0, + _RESERVED_0 = 0x0, SPI1_SS_N = 0x01, UART1_RX = 0x02, I2C0_SCL = 0x03, @@ -1045,7 +1045,7 @@ impl From for u8 { #[repr(u8)] #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] pub enum Gpio26ctrlFuncsel { - _RESERVED_0 = 0, + _RESERVED_0 = 0x0, SPI1_SCLK = 0x01, UART1_CTS = 0x02, I2C1_SDA = 0x03, @@ -1103,7 +1103,7 @@ impl From for u8 { #[repr(u8)] #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] pub enum Gpio27ctrlFuncsel { - _RESERVED_0 = 0, + _RESERVED_0 = 0x0, SPI1_TX = 0x01, UART1_RTS = 0x02, I2C1_SCL = 0x03, @@ -1161,7 +1161,7 @@ impl From for u8 { #[repr(u8)] #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] pub enum Gpio28ctrlFuncsel { - _RESERVED_0 = 0, + _RESERVED_0 = 0x0, SPI1_RX = 0x01, UART0_TX = 0x02, I2C0_SDA = 0x03, @@ -1219,7 +1219,7 @@ impl From for u8 { #[repr(u8)] #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] pub enum Gpio29ctrlFuncsel { - _RESERVED_0 = 0, + _RESERVED_0 = 0x0, SPI1_SS_N = 0x01, UART0_RX = 0x02, I2C0_SCL = 0x03, @@ -1277,7 +1277,7 @@ impl From for u8 { #[repr(u8)] #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] pub enum Gpio2ctrlFuncsel { - JTAG_TDI = 0, + JTAG_TDI = 0x0, SPI0_SCLK = 0x01, UART0_CTS = 0x02, I2C1_SDA = 0x03, @@ -1335,7 +1335,7 @@ impl From for u8 { #[repr(u8)] #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] pub enum Gpio30ctrlFuncsel { - _RESERVED_0 = 0, + _RESERVED_0 = 0x0, SPI1_SCLK = 0x01, UART0_CTS = 0x02, I2C1_SDA = 0x03, @@ -1393,7 +1393,7 @@ impl From for u8 { #[repr(u8)] #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] pub enum Gpio31ctrlFuncsel { - _RESERVED_0 = 0, + _RESERVED_0 = 0x0, SPI1_TX = 0x01, UART0_RTS = 0x02, I2C1_SCL = 0x03, @@ -1451,7 +1451,7 @@ impl From for u8 { #[repr(u8)] #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] pub enum Gpio32ctrlFuncsel { - _RESERVED_0 = 0, + _RESERVED_0 = 0x0, SPI0_RX = 0x01, UART0_TX = 0x02, I2C0_SDA = 0x03, @@ -1509,7 +1509,7 @@ impl From for u8 { #[repr(u8)] #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] pub enum Gpio33ctrlFuncsel { - _RESERVED_0 = 0, + _RESERVED_0 = 0x0, SPI0_SS_N = 0x01, UART0_RX = 0x02, I2C0_SCL = 0x03, @@ -1567,7 +1567,7 @@ impl From for u8 { #[repr(u8)] #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] pub enum Gpio34ctrlFuncsel { - _RESERVED_0 = 0, + _RESERVED_0 = 0x0, SPI0_SCLK = 0x01, UART0_CTS = 0x02, I2C1_SDA = 0x03, @@ -1625,7 +1625,7 @@ impl From for u8 { #[repr(u8)] #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] pub enum Gpio35ctrlFuncsel { - _RESERVED_0 = 0, + _RESERVED_0 = 0x0, SPI0_TX = 0x01, UART0_RTS = 0x02, I2C1_SCL = 0x03, @@ -1683,7 +1683,7 @@ impl From for u8 { #[repr(u8)] #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] pub enum Gpio36ctrlFuncsel { - _RESERVED_0 = 0, + _RESERVED_0 = 0x0, SPI0_RX = 0x01, UART1_TX = 0x02, I2C0_SDA = 0x03, @@ -1741,7 +1741,7 @@ impl From for u8 { #[repr(u8)] #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] pub enum Gpio37ctrlFuncsel { - _RESERVED_0 = 0, + _RESERVED_0 = 0x0, SPI0_SS_N = 0x01, UART1_RX = 0x02, I2C0_SCL = 0x03, @@ -1799,7 +1799,7 @@ impl From for u8 { #[repr(u8)] #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] pub enum Gpio38ctrlFuncsel { - _RESERVED_0 = 0, + _RESERVED_0 = 0x0, SPI0_SCLK = 0x01, UART1_CTS = 0x02, I2C1_SDA = 0x03, @@ -1857,7 +1857,7 @@ impl From for u8 { #[repr(u8)] #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] pub enum Gpio39ctrlFuncsel { - _RESERVED_0 = 0, + _RESERVED_0 = 0x0, SPI0_TX = 0x01, UART1_RTS = 0x02, I2C1_SCL = 0x03, @@ -1915,7 +1915,7 @@ impl From for u8 { #[repr(u8)] #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] pub enum Gpio3ctrlFuncsel { - JTAG_TDO = 0, + JTAG_TDO = 0x0, SPI0_TX = 0x01, UART0_RTS = 0x02, I2C1_SCL = 0x03, @@ -1973,7 +1973,7 @@ impl From for u8 { #[repr(u8)] #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] pub enum Gpio40ctrlFuncsel { - _RESERVED_0 = 0, + _RESERVED_0 = 0x0, SPI1_RX = 0x01, UART1_TX = 0x02, I2C0_SDA = 0x03, @@ -2031,7 +2031,7 @@ impl From for u8 { #[repr(u8)] #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] pub enum Gpio41ctrlFuncsel { - _RESERVED_0 = 0, + _RESERVED_0 = 0x0, SPI1_SS_N = 0x01, UART1_RX = 0x02, I2C0_SCL = 0x03, @@ -2089,7 +2089,7 @@ impl From for u8 { #[repr(u8)] #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] pub enum Gpio42ctrlFuncsel { - _RESERVED_0 = 0, + _RESERVED_0 = 0x0, SPI1_SCLK = 0x01, UART1_CTS = 0x02, I2C1_SDA = 0x03, @@ -2147,7 +2147,7 @@ impl From for u8 { #[repr(u8)] #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] pub enum Gpio43ctrlFuncsel { - _RESERVED_0 = 0, + _RESERVED_0 = 0x0, SPI1_TX = 0x01, UART1_RTS = 0x02, I2C1_SCL = 0x03, @@ -2205,7 +2205,7 @@ impl From for u8 { #[repr(u8)] #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] pub enum Gpio44ctrlFuncsel { - _RESERVED_0 = 0, + _RESERVED_0 = 0x0, SPI1_RX = 0x01, UART0_TX = 0x02, I2C0_SDA = 0x03, @@ -2263,7 +2263,7 @@ impl From for u8 { #[repr(u8)] #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] pub enum Gpio45ctrlFuncsel { - _RESERVED_0 = 0, + _RESERVED_0 = 0x0, SPI1_SS_N = 0x01, UART0_RX = 0x02, I2C0_SCL = 0x03, @@ -2321,7 +2321,7 @@ impl From for u8 { #[repr(u8)] #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] pub enum Gpio46ctrlFuncsel { - _RESERVED_0 = 0, + _RESERVED_0 = 0x0, SPI1_SCLK = 0x01, UART0_CTS = 0x02, I2C1_SDA = 0x03, @@ -2379,7 +2379,7 @@ impl From for u8 { #[repr(u8)] #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] pub enum Gpio47ctrlFuncsel { - _RESERVED_0 = 0, + _RESERVED_0 = 0x0, SPI1_TX = 0x01, UART0_RTS = 0x02, I2C1_SCL = 0x03, @@ -2437,7 +2437,7 @@ impl From for u8 { #[repr(u8)] #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] pub enum Gpio4ctrlFuncsel { - _RESERVED_0 = 0, + _RESERVED_0 = 0x0, SPI0_RX = 0x01, UART1_TX = 0x02, I2C0_SDA = 0x03, @@ -2495,7 +2495,7 @@ impl From for u8 { #[repr(u8)] #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] pub enum Gpio5ctrlFuncsel { - _RESERVED_0 = 0, + _RESERVED_0 = 0x0, SPI0_SS_N = 0x01, UART1_RX = 0x02, I2C0_SCL = 0x03, @@ -2553,7 +2553,7 @@ impl From for u8 { #[repr(u8)] #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] pub enum Gpio6ctrlFuncsel { - _RESERVED_0 = 0, + _RESERVED_0 = 0x0, SPI0_SCLK = 0x01, UART1_CTS = 0x02, I2C1_SDA = 0x03, @@ -2611,7 +2611,7 @@ impl From for u8 { #[repr(u8)] #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] pub enum Gpio7ctrlFuncsel { - _RESERVED_0 = 0, + _RESERVED_0 = 0x0, SPI0_TX = 0x01, UART1_RTS = 0x02, I2C1_SCL = 0x03, @@ -2669,7 +2669,7 @@ impl From for u8 { #[repr(u8)] #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] pub enum Gpio8ctrlFuncsel { - _RESERVED_0 = 0, + _RESERVED_0 = 0x0, SPI1_RX = 0x01, UART1_TX = 0x02, I2C0_SDA = 0x03, @@ -2727,7 +2727,7 @@ impl From for u8 { #[repr(u8)] #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] pub enum Gpio9ctrlFuncsel { - _RESERVED_0 = 0, + _RESERVED_0 = 0x0, SPI1_SS_N = 0x01, UART1_RX = 0x02, I2C0_SCL = 0x03, @@ -2786,7 +2786,7 @@ impl From for u8 { #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] pub enum Inover { #[doc = "don't invert the peri input"] - NORMAL = 0, + NORMAL = 0x0, #[doc = "invert the peri input"] INVERT = 0x01, #[doc = "drive peri input low"] @@ -2820,7 +2820,7 @@ impl From for u8 { #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] pub enum Irqover { #[doc = "don't invert the interrupt"] - NORMAL = 0, + NORMAL = 0x0, #[doc = "invert the interrupt"] INVERT = 0x01, #[doc = "drive interrupt low"] @@ -2854,7 +2854,7 @@ impl From for u8 { #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] pub enum Oeover { #[doc = "drive output enable from peripheral signal selected by funcsel"] - NORMAL = 0, + NORMAL = 0x0, #[doc = "drive output enable from inverse of peripheral signal selected by funcsel"] INVERT = 0x01, #[doc = "disable output"] @@ -2888,7 +2888,7 @@ impl From for u8 { #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] pub enum Outover { #[doc = "drive output from peripheral signal selected by funcsel"] - NORMAL = 0, + NORMAL = 0x0, #[doc = "drive output from inverse of peripheral signal selected by funcsel"] INVERT = 0x01, #[doc = "drive output low"] diff --git a/src/rp235x/mod.rs b/src/rp235x/mod.rs index 7ea79d50..d537ae1f 100644 --- a/src/rp235x/mod.rs +++ b/src/rp235x/mod.rs @@ -207,3206 +207,6 @@ pub const NVIC_PRIO_BITS: u8 = 4; pub use cortex_m_rt::interrupt; #[cfg(feature = "rt")] pub use Interrupt as interrupt; -#[repr(transparent)] -#[derive(Copy, Clone, Eq, PartialEq)] -pub struct BootFlags0R1(pub u32); -impl BootFlags0R1 { - #[inline(always)] - pub const fn val(&self) -> u32 { - let val = (self.0 >> 0usize) & 0x00ff_ffff; - val as u32 - } - #[inline(always)] - pub fn set_val(&mut self, val: u32) { - self.0 = (self.0 & !(0x00ff_ffff << 0usize)) | (((val as u32) & 0x00ff_ffff) << 0usize); - } -} -impl Default for BootFlags0R1 { - #[inline(always)] - fn default() -> BootFlags0R1 { - BootFlags0R1(0) - } -} -#[repr(transparent)] -#[derive(Copy, Clone, Eq, PartialEq)] -pub struct BootFlags0R2(pub u32); -impl BootFlags0R2 { - #[inline(always)] - pub const fn val(&self) -> u32 { - let val = (self.0 >> 0usize) & 0x00ff_ffff; - val as u32 - } - #[inline(always)] - pub fn set_val(&mut self, val: u32) { - self.0 = (self.0 & !(0x00ff_ffff << 0usize)) | (((val as u32) & 0x00ff_ffff) << 0usize); - } -} -impl Default for BootFlags0R2 { - #[inline(always)] - fn default() -> BootFlags0R2 { - BootFlags0R2(0) - } -} -#[repr(transparent)] -#[derive(Copy, Clone, Eq, PartialEq)] -pub struct BootFlags1R1(pub u32); -impl BootFlags1R1 { - #[inline(always)] - pub const fn val(&self) -> u32 { - let val = (self.0 >> 0usize) & 0x00ff_ffff; - val as u32 - } - #[inline(always)] - pub fn set_val(&mut self, val: u32) { - self.0 = (self.0 & !(0x00ff_ffff << 0usize)) | (((val as u32) & 0x00ff_ffff) << 0usize); - } -} -impl Default for BootFlags1R1 { - #[inline(always)] - fn default() -> BootFlags1R1 { - BootFlags1R1(0) - } -} -#[repr(transparent)] -#[derive(Copy, Clone, Eq, PartialEq)] -pub struct BootFlags1R2(pub u32); -impl BootFlags1R2 { - #[inline(always)] - pub const fn val(&self) -> u32 { - let val = (self.0 >> 0usize) & 0x00ff_ffff; - val as u32 - } - #[inline(always)] - pub fn set_val(&mut self, val: u32) { - self.0 = (self.0 & !(0x00ff_ffff << 0usize)) | (((val as u32) & 0x00ff_ffff) << 0usize); - } -} -impl Default for BootFlags1R2 { - #[inline(always)] - fn default() -> BootFlags1R2 { - BootFlags1R2(0) - } -} -#[repr(transparent)] -#[derive(Copy, Clone, Eq, PartialEq)] -pub struct Bootkey00(pub u32); -impl Bootkey00 { - #[inline(always)] - pub const fn val(&self) -> u32 { - let val = (self.0 >> 0usize) & 0x00ff_ffff; - val as u32 - } - #[inline(always)] - pub fn set_val(&mut self, val: u32) { - self.0 = (self.0 & !(0x00ff_ffff << 0usize)) | (((val as u32) & 0x00ff_ffff) << 0usize); - } -} -impl Default for Bootkey00 { - #[inline(always)] - fn default() -> Bootkey00 { - Bootkey00(0) - } -} -#[repr(transparent)] -#[derive(Copy, Clone, Eq, PartialEq)] -pub struct Bootkey01(pub u32); -impl Bootkey01 { - #[inline(always)] - pub const fn val(&self) -> u32 { - let val = (self.0 >> 0usize) & 0x00ff_ffff; - val as u32 - } - #[inline(always)] - pub fn set_val(&mut self, val: u32) { - self.0 = (self.0 & !(0x00ff_ffff << 0usize)) | (((val as u32) & 0x00ff_ffff) << 0usize); - } -} -impl Default for Bootkey01 { - #[inline(always)] - fn default() -> Bootkey01 { - Bootkey01(0) - } -} -#[repr(transparent)] -#[derive(Copy, Clone, Eq, PartialEq)] -pub struct Bootkey010(pub u32); -impl Bootkey010 { - #[inline(always)] - pub const fn val(&self) -> u32 { - let val = (self.0 >> 0usize) & 0x00ff_ffff; - val as u32 - } - #[inline(always)] - pub fn set_val(&mut self, val: u32) { - self.0 = (self.0 & !(0x00ff_ffff << 0usize)) | (((val as u32) & 0x00ff_ffff) << 0usize); - } -} -impl Default for Bootkey010 { - #[inline(always)] - fn default() -> Bootkey010 { - Bootkey010(0) - } -} -#[repr(transparent)] -#[derive(Copy, Clone, Eq, PartialEq)] -pub struct Bootkey011(pub u32); -impl Bootkey011 { - #[inline(always)] - pub const fn val(&self) -> u32 { - let val = (self.0 >> 0usize) & 0x00ff_ffff; - val as u32 - } - #[inline(always)] - pub fn set_val(&mut self, val: u32) { - self.0 = (self.0 & !(0x00ff_ffff << 0usize)) | (((val as u32) & 0x00ff_ffff) << 0usize); - } -} -impl Default for Bootkey011 { - #[inline(always)] - fn default() -> Bootkey011 { - Bootkey011(0) - } -} -#[repr(transparent)] -#[derive(Copy, Clone, Eq, PartialEq)] -pub struct Bootkey012(pub u32); -impl Bootkey012 { - #[inline(always)] - pub const fn val(&self) -> u32 { - let val = (self.0 >> 0usize) & 0x00ff_ffff; - val as u32 - } - #[inline(always)] - pub fn set_val(&mut self, val: u32) { - self.0 = (self.0 & !(0x00ff_ffff << 0usize)) | (((val as u32) & 0x00ff_ffff) << 0usize); - } -} -impl Default for Bootkey012 { - #[inline(always)] - fn default() -> Bootkey012 { - Bootkey012(0) - } -} -#[repr(transparent)] -#[derive(Copy, Clone, Eq, PartialEq)] -pub struct Bootkey013(pub u32); -impl Bootkey013 { - #[inline(always)] - pub const fn val(&self) -> u32 { - let val = (self.0 >> 0usize) & 0x00ff_ffff; - val as u32 - } - #[inline(always)] - pub fn set_val(&mut self, val: u32) { - self.0 = (self.0 & !(0x00ff_ffff << 0usize)) | (((val as u32) & 0x00ff_ffff) << 0usize); - } -} -impl Default for Bootkey013 { - #[inline(always)] - fn default() -> Bootkey013 { - Bootkey013(0) - } -} -#[repr(transparent)] -#[derive(Copy, Clone, Eq, PartialEq)] -pub struct Bootkey014(pub u32); -impl Bootkey014 { - #[inline(always)] - pub const fn val(&self) -> u32 { - let val = (self.0 >> 0usize) & 0x00ff_ffff; - val as u32 - } - #[inline(always)] - pub fn set_val(&mut self, val: u32) { - self.0 = (self.0 & !(0x00ff_ffff << 0usize)) | (((val as u32) & 0x00ff_ffff) << 0usize); - } -} -impl Default for Bootkey014 { - #[inline(always)] - fn default() -> Bootkey014 { - Bootkey014(0) - } -} -#[repr(transparent)] -#[derive(Copy, Clone, Eq, PartialEq)] -pub struct Bootkey015(pub u32); -impl Bootkey015 { - #[inline(always)] - pub const fn val(&self) -> u32 { - let val = (self.0 >> 0usize) & 0x00ff_ffff; - val as u32 - } - #[inline(always)] - pub fn set_val(&mut self, val: u32) { - self.0 = (self.0 & !(0x00ff_ffff << 0usize)) | (((val as u32) & 0x00ff_ffff) << 0usize); - } -} -impl Default for Bootkey015 { - #[inline(always)] - fn default() -> Bootkey015 { - Bootkey015(0) - } -} -#[repr(transparent)] -#[derive(Copy, Clone, Eq, PartialEq)] -pub struct Bootkey02(pub u32); -impl Bootkey02 { - #[inline(always)] - pub const fn val(&self) -> u32 { - let val = (self.0 >> 0usize) & 0x00ff_ffff; - val as u32 - } - #[inline(always)] - pub fn set_val(&mut self, val: u32) { - self.0 = (self.0 & !(0x00ff_ffff << 0usize)) | (((val as u32) & 0x00ff_ffff) << 0usize); - } -} -impl Default for Bootkey02 { - #[inline(always)] - fn default() -> Bootkey02 { - Bootkey02(0) - } -} -#[repr(transparent)] -#[derive(Copy, Clone, Eq, PartialEq)] -pub struct Bootkey03(pub u32); -impl Bootkey03 { - #[inline(always)] - pub const fn val(&self) -> u32 { - let val = (self.0 >> 0usize) & 0x00ff_ffff; - val as u32 - } - #[inline(always)] - pub fn set_val(&mut self, val: u32) { - self.0 = (self.0 & !(0x00ff_ffff << 0usize)) | (((val as u32) & 0x00ff_ffff) << 0usize); - } -} -impl Default for Bootkey03 { - #[inline(always)] - fn default() -> Bootkey03 { - Bootkey03(0) - } -} -#[repr(transparent)] -#[derive(Copy, Clone, Eq, PartialEq)] -pub struct Bootkey04(pub u32); -impl Bootkey04 { - #[inline(always)] - pub const fn val(&self) -> u32 { - let val = (self.0 >> 0usize) & 0x00ff_ffff; - val as u32 - } - #[inline(always)] - pub fn set_val(&mut self, val: u32) { - self.0 = (self.0 & !(0x00ff_ffff << 0usize)) | (((val as u32) & 0x00ff_ffff) << 0usize); - } -} -impl Default for Bootkey04 { - #[inline(always)] - fn default() -> Bootkey04 { - Bootkey04(0) - } -} -#[repr(transparent)] -#[derive(Copy, Clone, Eq, PartialEq)] -pub struct Bootkey05(pub u32); -impl Bootkey05 { - #[inline(always)] - pub const fn val(&self) -> u32 { - let val = (self.0 >> 0usize) & 0x00ff_ffff; - val as u32 - } - #[inline(always)] - pub fn set_val(&mut self, val: u32) { - self.0 = (self.0 & !(0x00ff_ffff << 0usize)) | (((val as u32) & 0x00ff_ffff) << 0usize); - } -} -impl Default for Bootkey05 { - #[inline(always)] - fn default() -> Bootkey05 { - Bootkey05(0) - } -} -#[repr(transparent)] -#[derive(Copy, Clone, Eq, PartialEq)] -pub struct Bootkey06(pub u32); -impl Bootkey06 { - #[inline(always)] - pub const fn val(&self) -> u32 { - let val = (self.0 >> 0usize) & 0x00ff_ffff; - val as u32 - } - #[inline(always)] - pub fn set_val(&mut self, val: u32) { - self.0 = (self.0 & !(0x00ff_ffff << 0usize)) | (((val as u32) & 0x00ff_ffff) << 0usize); - } -} -impl Default for Bootkey06 { - #[inline(always)] - fn default() -> Bootkey06 { - Bootkey06(0) - } -} -#[repr(transparent)] -#[derive(Copy, Clone, Eq, PartialEq)] -pub struct Bootkey07(pub u32); -impl Bootkey07 { - #[inline(always)] - pub const fn val(&self) -> u32 { - let val = (self.0 >> 0usize) & 0x00ff_ffff; - val as u32 - } - #[inline(always)] - pub fn set_val(&mut self, val: u32) { - self.0 = (self.0 & !(0x00ff_ffff << 0usize)) | (((val as u32) & 0x00ff_ffff) << 0usize); - } -} -impl Default for Bootkey07 { - #[inline(always)] - fn default() -> Bootkey07 { - Bootkey07(0) - } -} -#[repr(transparent)] -#[derive(Copy, Clone, Eq, PartialEq)] -pub struct Bootkey08(pub u32); -impl Bootkey08 { - #[inline(always)] - pub const fn val(&self) -> u32 { - let val = (self.0 >> 0usize) & 0x00ff_ffff; - val as u32 - } - #[inline(always)] - pub fn set_val(&mut self, val: u32) { - self.0 = (self.0 & !(0x00ff_ffff << 0usize)) | (((val as u32) & 0x00ff_ffff) << 0usize); - } -} -impl Default for Bootkey08 { - #[inline(always)] - fn default() -> Bootkey08 { - Bootkey08(0) - } -} -#[repr(transparent)] -#[derive(Copy, Clone, Eq, PartialEq)] -pub struct Bootkey09(pub u32); -impl Bootkey09 { - #[inline(always)] - pub const fn val(&self) -> u32 { - let val = (self.0 >> 0usize) & 0x00ff_ffff; - val as u32 - } - #[inline(always)] - pub fn set_val(&mut self, val: u32) { - self.0 = (self.0 & !(0x00ff_ffff << 0usize)) | (((val as u32) & 0x00ff_ffff) << 0usize); - } -} -impl Default for Bootkey09 { - #[inline(always)] - fn default() -> Bootkey09 { - Bootkey09(0) - } -} -#[repr(transparent)] -#[derive(Copy, Clone, Eq, PartialEq)] -pub struct Bootkey10(pub u32); -impl Bootkey10 { - #[inline(always)] - pub const fn val(&self) -> u32 { - let val = (self.0 >> 0usize) & 0x00ff_ffff; - val as u32 - } - #[inline(always)] - pub fn set_val(&mut self, val: u32) { - self.0 = (self.0 & !(0x00ff_ffff << 0usize)) | (((val as u32) & 0x00ff_ffff) << 0usize); - } -} -impl Default for Bootkey10 { - #[inline(always)] - fn default() -> Bootkey10 { - Bootkey10(0) - } -} -#[repr(transparent)] -#[derive(Copy, Clone, Eq, PartialEq)] -pub struct Bootkey11(pub u32); -impl Bootkey11 { - #[inline(always)] - pub const fn val(&self) -> u32 { - let val = (self.0 >> 0usize) & 0x00ff_ffff; - val as u32 - } - #[inline(always)] - pub fn set_val(&mut self, val: u32) { - self.0 = (self.0 & !(0x00ff_ffff << 0usize)) | (((val as u32) & 0x00ff_ffff) << 0usize); - } -} -impl Default for Bootkey11 { - #[inline(always)] - fn default() -> Bootkey11 { - Bootkey11(0) - } -} -#[repr(transparent)] -#[derive(Copy, Clone, Eq, PartialEq)] -pub struct Bootkey110(pub u32); -impl Bootkey110 { - #[inline(always)] - pub const fn val(&self) -> u32 { - let val = (self.0 >> 0usize) & 0x00ff_ffff; - val as u32 - } - #[inline(always)] - pub fn set_val(&mut self, val: u32) { - self.0 = (self.0 & !(0x00ff_ffff << 0usize)) | (((val as u32) & 0x00ff_ffff) << 0usize); - } -} -impl Default for Bootkey110 { - #[inline(always)] - fn default() -> Bootkey110 { - Bootkey110(0) - } -} -#[repr(transparent)] -#[derive(Copy, Clone, Eq, PartialEq)] -pub struct Bootkey111(pub u32); -impl Bootkey111 { - #[inline(always)] - pub const fn val(&self) -> u32 { - let val = (self.0 >> 0usize) & 0x00ff_ffff; - val as u32 - } - #[inline(always)] - pub fn set_val(&mut self, val: u32) { - self.0 = (self.0 & !(0x00ff_ffff << 0usize)) | (((val as u32) & 0x00ff_ffff) << 0usize); - } -} -impl Default for Bootkey111 { - #[inline(always)] - fn default() -> Bootkey111 { - Bootkey111(0) - } -} -#[repr(transparent)] -#[derive(Copy, Clone, Eq, PartialEq)] -pub struct Bootkey112(pub u32); -impl Bootkey112 { - #[inline(always)] - pub const fn val(&self) -> u32 { - let val = (self.0 >> 0usize) & 0x00ff_ffff; - val as u32 - } - #[inline(always)] - pub fn set_val(&mut self, val: u32) { - self.0 = (self.0 & !(0x00ff_ffff << 0usize)) | (((val as u32) & 0x00ff_ffff) << 0usize); - } -} -impl Default for Bootkey112 { - #[inline(always)] - fn default() -> Bootkey112 { - Bootkey112(0) - } -} -#[repr(transparent)] -#[derive(Copy, Clone, Eq, PartialEq)] -pub struct Bootkey113(pub u32); -impl Bootkey113 { - #[inline(always)] - pub const fn val(&self) -> u32 { - let val = (self.0 >> 0usize) & 0x00ff_ffff; - val as u32 - } - #[inline(always)] - pub fn set_val(&mut self, val: u32) { - self.0 = (self.0 & !(0x00ff_ffff << 0usize)) | (((val as u32) & 0x00ff_ffff) << 0usize); - } -} -impl Default for Bootkey113 { - #[inline(always)] - fn default() -> Bootkey113 { - Bootkey113(0) - } -} -#[repr(transparent)] -#[derive(Copy, Clone, Eq, PartialEq)] -pub struct Bootkey114(pub u32); -impl Bootkey114 { - #[inline(always)] - pub const fn val(&self) -> u32 { - let val = (self.0 >> 0usize) & 0x00ff_ffff; - val as u32 - } - #[inline(always)] - pub fn set_val(&mut self, val: u32) { - self.0 = (self.0 & !(0x00ff_ffff << 0usize)) | (((val as u32) & 0x00ff_ffff) << 0usize); - } -} -impl Default for Bootkey114 { - #[inline(always)] - fn default() -> Bootkey114 { - Bootkey114(0) - } -} -#[repr(transparent)] -#[derive(Copy, Clone, Eq, PartialEq)] -pub struct Bootkey115(pub u32); -impl Bootkey115 { - #[inline(always)] - pub const fn val(&self) -> u32 { - let val = (self.0 >> 0usize) & 0x00ff_ffff; - val as u32 - } - #[inline(always)] - pub fn set_val(&mut self, val: u32) { - self.0 = (self.0 & !(0x00ff_ffff << 0usize)) | (((val as u32) & 0x00ff_ffff) << 0usize); - } -} -impl Default for Bootkey115 { - #[inline(always)] - fn default() -> Bootkey115 { - Bootkey115(0) - } -} -#[repr(transparent)] -#[derive(Copy, Clone, Eq, PartialEq)] -pub struct Bootkey12(pub u32); -impl Bootkey12 { - #[inline(always)] - pub const fn val(&self) -> u32 { - let val = (self.0 >> 0usize) & 0x00ff_ffff; - val as u32 - } - #[inline(always)] - pub fn set_val(&mut self, val: u32) { - self.0 = (self.0 & !(0x00ff_ffff << 0usize)) | (((val as u32) & 0x00ff_ffff) << 0usize); - } -} -impl Default for Bootkey12 { - #[inline(always)] - fn default() -> Bootkey12 { - Bootkey12(0) - } -} -#[repr(transparent)] -#[derive(Copy, Clone, Eq, PartialEq)] -pub struct Bootkey13(pub u32); -impl Bootkey13 { - #[inline(always)] - pub const fn val(&self) -> u32 { - let val = (self.0 >> 0usize) & 0x00ff_ffff; - val as u32 - } - #[inline(always)] - pub fn set_val(&mut self, val: u32) { - self.0 = (self.0 & !(0x00ff_ffff << 0usize)) | (((val as u32) & 0x00ff_ffff) << 0usize); - } -} -impl Default for Bootkey13 { - #[inline(always)] - fn default() -> Bootkey13 { - Bootkey13(0) - } -} -#[repr(transparent)] -#[derive(Copy, Clone, Eq, PartialEq)] -pub struct Bootkey14(pub u32); -impl Bootkey14 { - #[inline(always)] - pub const fn val(&self) -> u32 { - let val = (self.0 >> 0usize) & 0x00ff_ffff; - val as u32 - } - #[inline(always)] - pub fn set_val(&mut self, val: u32) { - self.0 = (self.0 & !(0x00ff_ffff << 0usize)) | (((val as u32) & 0x00ff_ffff) << 0usize); - } -} -impl Default for Bootkey14 { - #[inline(always)] - fn default() -> Bootkey14 { - Bootkey14(0) - } -} -#[repr(transparent)] -#[derive(Copy, Clone, Eq, PartialEq)] -pub struct Bootkey15(pub u32); -impl Bootkey15 { - #[inline(always)] - pub const fn val(&self) -> u32 { - let val = (self.0 >> 0usize) & 0x00ff_ffff; - val as u32 - } - #[inline(always)] - pub fn set_val(&mut self, val: u32) { - self.0 = (self.0 & !(0x00ff_ffff << 0usize)) | (((val as u32) & 0x00ff_ffff) << 0usize); - } -} -impl Default for Bootkey15 { - #[inline(always)] - fn default() -> Bootkey15 { - Bootkey15(0) - } -} -#[repr(transparent)] -#[derive(Copy, Clone, Eq, PartialEq)] -pub struct Bootkey16(pub u32); -impl Bootkey16 { - #[inline(always)] - pub const fn val(&self) -> u32 { - let val = (self.0 >> 0usize) & 0x00ff_ffff; - val as u32 - } - #[inline(always)] - pub fn set_val(&mut self, val: u32) { - self.0 = (self.0 & !(0x00ff_ffff << 0usize)) | (((val as u32) & 0x00ff_ffff) << 0usize); - } -} -impl Default for Bootkey16 { - #[inline(always)] - fn default() -> Bootkey16 { - Bootkey16(0) - } -} -#[repr(transparent)] -#[derive(Copy, Clone, Eq, PartialEq)] -pub struct Bootkey17(pub u32); -impl Bootkey17 { - #[inline(always)] - pub const fn val(&self) -> u32 { - let val = (self.0 >> 0usize) & 0x00ff_ffff; - val as u32 - } - #[inline(always)] - pub fn set_val(&mut self, val: u32) { - self.0 = (self.0 & !(0x00ff_ffff << 0usize)) | (((val as u32) & 0x00ff_ffff) << 0usize); - } -} -impl Default for Bootkey17 { - #[inline(always)] - fn default() -> Bootkey17 { - Bootkey17(0) - } -} -#[repr(transparent)] -#[derive(Copy, Clone, Eq, PartialEq)] -pub struct Bootkey18(pub u32); -impl Bootkey18 { - #[inline(always)] - pub const fn val(&self) -> u32 { - let val = (self.0 >> 0usize) & 0x00ff_ffff; - val as u32 - } - #[inline(always)] - pub fn set_val(&mut self, val: u32) { - self.0 = (self.0 & !(0x00ff_ffff << 0usize)) | (((val as u32) & 0x00ff_ffff) << 0usize); - } -} -impl Default for Bootkey18 { - #[inline(always)] - fn default() -> Bootkey18 { - Bootkey18(0) - } -} -#[repr(transparent)] -#[derive(Copy, Clone, Eq, PartialEq)] -pub struct Bootkey19(pub u32); -impl Bootkey19 { - #[inline(always)] - pub const fn val(&self) -> u32 { - let val = (self.0 >> 0usize) & 0x00ff_ffff; - val as u32 - } - #[inline(always)] - pub fn set_val(&mut self, val: u32) { - self.0 = (self.0 & !(0x00ff_ffff << 0usize)) | (((val as u32) & 0x00ff_ffff) << 0usize); - } -} -impl Default for Bootkey19 { - #[inline(always)] - fn default() -> Bootkey19 { - Bootkey19(0) - } -} -#[repr(transparent)] -#[derive(Copy, Clone, Eq, PartialEq)] -pub struct Bootkey20(pub u32); -impl Bootkey20 { - #[inline(always)] - pub const fn val(&self) -> u32 { - let val = (self.0 >> 0usize) & 0x00ff_ffff; - val as u32 - } - #[inline(always)] - pub fn set_val(&mut self, val: u32) { - self.0 = (self.0 & !(0x00ff_ffff << 0usize)) | (((val as u32) & 0x00ff_ffff) << 0usize); - } -} -impl Default for Bootkey20 { - #[inline(always)] - fn default() -> Bootkey20 { - Bootkey20(0) - } -} -#[repr(transparent)] -#[derive(Copy, Clone, Eq, PartialEq)] -pub struct Bootkey21(pub u32); -impl Bootkey21 { - #[inline(always)] - pub const fn val(&self) -> u32 { - let val = (self.0 >> 0usize) & 0x00ff_ffff; - val as u32 - } - #[inline(always)] - pub fn set_val(&mut self, val: u32) { - self.0 = (self.0 & !(0x00ff_ffff << 0usize)) | (((val as u32) & 0x00ff_ffff) << 0usize); - } -} -impl Default for Bootkey21 { - #[inline(always)] - fn default() -> Bootkey21 { - Bootkey21(0) - } -} -#[repr(transparent)] -#[derive(Copy, Clone, Eq, PartialEq)] -pub struct Bootkey210(pub u32); -impl Bootkey210 { - #[inline(always)] - pub const fn val(&self) -> u32 { - let val = (self.0 >> 0usize) & 0x00ff_ffff; - val as u32 - } - #[inline(always)] - pub fn set_val(&mut self, val: u32) { - self.0 = (self.0 & !(0x00ff_ffff << 0usize)) | (((val as u32) & 0x00ff_ffff) << 0usize); - } -} -impl Default for Bootkey210 { - #[inline(always)] - fn default() -> Bootkey210 { - Bootkey210(0) - } -} -#[repr(transparent)] -#[derive(Copy, Clone, Eq, PartialEq)] -pub struct Bootkey211(pub u32); -impl Bootkey211 { - #[inline(always)] - pub const fn val(&self) -> u32 { - let val = (self.0 >> 0usize) & 0x00ff_ffff; - val as u32 - } - #[inline(always)] - pub fn set_val(&mut self, val: u32) { - self.0 = (self.0 & !(0x00ff_ffff << 0usize)) | (((val as u32) & 0x00ff_ffff) << 0usize); - } -} -impl Default for Bootkey211 { - #[inline(always)] - fn default() -> Bootkey211 { - Bootkey211(0) - } -} -#[repr(transparent)] -#[derive(Copy, Clone, Eq, PartialEq)] -pub struct Bootkey212(pub u32); -impl Bootkey212 { - #[inline(always)] - pub const fn val(&self) -> u32 { - let val = (self.0 >> 0usize) & 0x00ff_ffff; - val as u32 - } - #[inline(always)] - pub fn set_val(&mut self, val: u32) { - self.0 = (self.0 & !(0x00ff_ffff << 0usize)) | (((val as u32) & 0x00ff_ffff) << 0usize); - } -} -impl Default for Bootkey212 { - #[inline(always)] - fn default() -> Bootkey212 { - Bootkey212(0) - } -} -#[repr(transparent)] -#[derive(Copy, Clone, Eq, PartialEq)] -pub struct Bootkey213(pub u32); -impl Bootkey213 { - #[inline(always)] - pub const fn val(&self) -> u32 { - let val = (self.0 >> 0usize) & 0x00ff_ffff; - val as u32 - } - #[inline(always)] - pub fn set_val(&mut self, val: u32) { - self.0 = (self.0 & !(0x00ff_ffff << 0usize)) | (((val as u32) & 0x00ff_ffff) << 0usize); - } -} -impl Default for Bootkey213 { - #[inline(always)] - fn default() -> Bootkey213 { - Bootkey213(0) - } -} -#[repr(transparent)] -#[derive(Copy, Clone, Eq, PartialEq)] -pub struct Bootkey214(pub u32); -impl Bootkey214 { - #[inline(always)] - pub const fn val(&self) -> u32 { - let val = (self.0 >> 0usize) & 0x00ff_ffff; - val as u32 - } - #[inline(always)] - pub fn set_val(&mut self, val: u32) { - self.0 = (self.0 & !(0x00ff_ffff << 0usize)) | (((val as u32) & 0x00ff_ffff) << 0usize); - } -} -impl Default for Bootkey214 { - #[inline(always)] - fn default() -> Bootkey214 { - Bootkey214(0) - } -} -#[repr(transparent)] -#[derive(Copy, Clone, Eq, PartialEq)] -pub struct Bootkey215(pub u32); -impl Bootkey215 { - #[inline(always)] - pub const fn val(&self) -> u32 { - let val = (self.0 >> 0usize) & 0x00ff_ffff; - val as u32 - } - #[inline(always)] - pub fn set_val(&mut self, val: u32) { - self.0 = (self.0 & !(0x00ff_ffff << 0usize)) | (((val as u32) & 0x00ff_ffff) << 0usize); - } -} -impl Default for Bootkey215 { - #[inline(always)] - fn default() -> Bootkey215 { - Bootkey215(0) - } -} -#[repr(transparent)] -#[derive(Copy, Clone, Eq, PartialEq)] -pub struct Bootkey22(pub u32); -impl Bootkey22 { - #[inline(always)] - pub const fn val(&self) -> u32 { - let val = (self.0 >> 0usize) & 0x00ff_ffff; - val as u32 - } - #[inline(always)] - pub fn set_val(&mut self, val: u32) { - self.0 = (self.0 & !(0x00ff_ffff << 0usize)) | (((val as u32) & 0x00ff_ffff) << 0usize); - } -} -impl Default for Bootkey22 { - #[inline(always)] - fn default() -> Bootkey22 { - Bootkey22(0) - } -} -#[repr(transparent)] -#[derive(Copy, Clone, Eq, PartialEq)] -pub struct Bootkey23(pub u32); -impl Bootkey23 { - #[inline(always)] - pub const fn val(&self) -> u32 { - let val = (self.0 >> 0usize) & 0x00ff_ffff; - val as u32 - } - #[inline(always)] - pub fn set_val(&mut self, val: u32) { - self.0 = (self.0 & !(0x00ff_ffff << 0usize)) | (((val as u32) & 0x00ff_ffff) << 0usize); - } -} -impl Default for Bootkey23 { - #[inline(always)] - fn default() -> Bootkey23 { - Bootkey23(0) - } -} -#[repr(transparent)] -#[derive(Copy, Clone, Eq, PartialEq)] -pub struct Bootkey24(pub u32); -impl Bootkey24 { - #[inline(always)] - pub const fn val(&self) -> u32 { - let val = (self.0 >> 0usize) & 0x00ff_ffff; - val as u32 - } - #[inline(always)] - pub fn set_val(&mut self, val: u32) { - self.0 = (self.0 & !(0x00ff_ffff << 0usize)) | (((val as u32) & 0x00ff_ffff) << 0usize); - } -} -impl Default for Bootkey24 { - #[inline(always)] - fn default() -> Bootkey24 { - Bootkey24(0) - } -} -#[repr(transparent)] -#[derive(Copy, Clone, Eq, PartialEq)] -pub struct Bootkey25(pub u32); -impl Bootkey25 { - #[inline(always)] - pub const fn val(&self) -> u32 { - let val = (self.0 >> 0usize) & 0x00ff_ffff; - val as u32 - } - #[inline(always)] - pub fn set_val(&mut self, val: u32) { - self.0 = (self.0 & !(0x00ff_ffff << 0usize)) | (((val as u32) & 0x00ff_ffff) << 0usize); - } -} -impl Default for Bootkey25 { - #[inline(always)] - fn default() -> Bootkey25 { - Bootkey25(0) - } -} -#[repr(transparent)] -#[derive(Copy, Clone, Eq, PartialEq)] -pub struct Bootkey26(pub u32); -impl Bootkey26 { - #[inline(always)] - pub const fn val(&self) -> u32 { - let val = (self.0 >> 0usize) & 0x00ff_ffff; - val as u32 - } - #[inline(always)] - pub fn set_val(&mut self, val: u32) { - self.0 = (self.0 & !(0x00ff_ffff << 0usize)) | (((val as u32) & 0x00ff_ffff) << 0usize); - } -} -impl Default for Bootkey26 { - #[inline(always)] - fn default() -> Bootkey26 { - Bootkey26(0) - } -} -#[repr(transparent)] -#[derive(Copy, Clone, Eq, PartialEq)] -pub struct Bootkey27(pub u32); -impl Bootkey27 { - #[inline(always)] - pub const fn val(&self) -> u32 { - let val = (self.0 >> 0usize) & 0x00ff_ffff; - val as u32 - } - #[inline(always)] - pub fn set_val(&mut self, val: u32) { - self.0 = (self.0 & !(0x00ff_ffff << 0usize)) | (((val as u32) & 0x00ff_ffff) << 0usize); - } -} -impl Default for Bootkey27 { - #[inline(always)] - fn default() -> Bootkey27 { - Bootkey27(0) - } -} -#[repr(transparent)] -#[derive(Copy, Clone, Eq, PartialEq)] -pub struct Bootkey28(pub u32); -impl Bootkey28 { - #[inline(always)] - pub const fn val(&self) -> u32 { - let val = (self.0 >> 0usize) & 0x00ff_ffff; - val as u32 - } - #[inline(always)] - pub fn set_val(&mut self, val: u32) { - self.0 = (self.0 & !(0x00ff_ffff << 0usize)) | (((val as u32) & 0x00ff_ffff) << 0usize); - } -} -impl Default for Bootkey28 { - #[inline(always)] - fn default() -> Bootkey28 { - Bootkey28(0) - } -} -#[repr(transparent)] -#[derive(Copy, Clone, Eq, PartialEq)] -pub struct Bootkey29(pub u32); -impl Bootkey29 { - #[inline(always)] - pub const fn val(&self) -> u32 { - let val = (self.0 >> 0usize) & 0x00ff_ffff; - val as u32 - } - #[inline(always)] - pub fn set_val(&mut self, val: u32) { - self.0 = (self.0 & !(0x00ff_ffff << 0usize)) | (((val as u32) & 0x00ff_ffff) << 0usize); - } -} -impl Default for Bootkey29 { - #[inline(always)] - fn default() -> Bootkey29 { - Bootkey29(0) - } -} -#[repr(transparent)] -#[derive(Copy, Clone, Eq, PartialEq)] -pub struct Bootkey30(pub u32); -impl Bootkey30 { - #[inline(always)] - pub const fn val(&self) -> u32 { - let val = (self.0 >> 0usize) & 0x00ff_ffff; - val as u32 - } - #[inline(always)] - pub fn set_val(&mut self, val: u32) { - self.0 = (self.0 & !(0x00ff_ffff << 0usize)) | (((val as u32) & 0x00ff_ffff) << 0usize); - } -} -impl Default for Bootkey30 { - #[inline(always)] - fn default() -> Bootkey30 { - Bootkey30(0) - } -} -#[repr(transparent)] -#[derive(Copy, Clone, Eq, PartialEq)] -pub struct Bootkey31(pub u32); -impl Bootkey31 { - #[inline(always)] - pub const fn val(&self) -> u32 { - let val = (self.0 >> 0usize) & 0x00ff_ffff; - val as u32 - } - #[inline(always)] - pub fn set_val(&mut self, val: u32) { - self.0 = (self.0 & !(0x00ff_ffff << 0usize)) | (((val as u32) & 0x00ff_ffff) << 0usize); - } -} -impl Default for Bootkey31 { - #[inline(always)] - fn default() -> Bootkey31 { - Bootkey31(0) - } -} -#[repr(transparent)] -#[derive(Copy, Clone, Eq, PartialEq)] -pub struct Bootkey310(pub u32); -impl Bootkey310 { - #[inline(always)] - pub const fn val(&self) -> u32 { - let val = (self.0 >> 0usize) & 0x00ff_ffff; - val as u32 - } - #[inline(always)] - pub fn set_val(&mut self, val: u32) { - self.0 = (self.0 & !(0x00ff_ffff << 0usize)) | (((val as u32) & 0x00ff_ffff) << 0usize); - } -} -impl Default for Bootkey310 { - #[inline(always)] - fn default() -> Bootkey310 { - Bootkey310(0) - } -} -#[repr(transparent)] -#[derive(Copy, Clone, Eq, PartialEq)] -pub struct Bootkey311(pub u32); -impl Bootkey311 { - #[inline(always)] - pub const fn val(&self) -> u32 { - let val = (self.0 >> 0usize) & 0x00ff_ffff; - val as u32 - } - #[inline(always)] - pub fn set_val(&mut self, val: u32) { - self.0 = (self.0 & !(0x00ff_ffff << 0usize)) | (((val as u32) & 0x00ff_ffff) << 0usize); - } -} -impl Default for Bootkey311 { - #[inline(always)] - fn default() -> Bootkey311 { - Bootkey311(0) - } -} -#[repr(transparent)] -#[derive(Copy, Clone, Eq, PartialEq)] -pub struct Bootkey312(pub u32); -impl Bootkey312 { - #[inline(always)] - pub const fn val(&self) -> u32 { - let val = (self.0 >> 0usize) & 0x00ff_ffff; - val as u32 - } - #[inline(always)] - pub fn set_val(&mut self, val: u32) { - self.0 = (self.0 & !(0x00ff_ffff << 0usize)) | (((val as u32) & 0x00ff_ffff) << 0usize); - } -} -impl Default for Bootkey312 { - #[inline(always)] - fn default() -> Bootkey312 { - Bootkey312(0) - } -} -#[repr(transparent)] -#[derive(Copy, Clone, Eq, PartialEq)] -pub struct Bootkey313(pub u32); -impl Bootkey313 { - #[inline(always)] - pub const fn val(&self) -> u32 { - let val = (self.0 >> 0usize) & 0x00ff_ffff; - val as u32 - } - #[inline(always)] - pub fn set_val(&mut self, val: u32) { - self.0 = (self.0 & !(0x00ff_ffff << 0usize)) | (((val as u32) & 0x00ff_ffff) << 0usize); - } -} -impl Default for Bootkey313 { - #[inline(always)] - fn default() -> Bootkey313 { - Bootkey313(0) - } -} -#[repr(transparent)] -#[derive(Copy, Clone, Eq, PartialEq)] -pub struct Bootkey314(pub u32); -impl Bootkey314 { - #[inline(always)] - pub const fn val(&self) -> u32 { - let val = (self.0 >> 0usize) & 0x00ff_ffff; - val as u32 - } - #[inline(always)] - pub fn set_val(&mut self, val: u32) { - self.0 = (self.0 & !(0x00ff_ffff << 0usize)) | (((val as u32) & 0x00ff_ffff) << 0usize); - } -} -impl Default for Bootkey314 { - #[inline(always)] - fn default() -> Bootkey314 { - Bootkey314(0) - } -} -#[repr(transparent)] -#[derive(Copy, Clone, Eq, PartialEq)] -pub struct Bootkey315(pub u32); -impl Bootkey315 { - #[inline(always)] - pub const fn val(&self) -> u32 { - let val = (self.0 >> 0usize) & 0x00ff_ffff; - val as u32 - } - #[inline(always)] - pub fn set_val(&mut self, val: u32) { - self.0 = (self.0 & !(0x00ff_ffff << 0usize)) | (((val as u32) & 0x00ff_ffff) << 0usize); - } -} -impl Default for Bootkey315 { - #[inline(always)] - fn default() -> Bootkey315 { - Bootkey315(0) - } -} -#[repr(transparent)] -#[derive(Copy, Clone, Eq, PartialEq)] -pub struct Bootkey32(pub u32); -impl Bootkey32 { - #[inline(always)] - pub const fn val(&self) -> u32 { - let val = (self.0 >> 0usize) & 0x00ff_ffff; - val as u32 - } - #[inline(always)] - pub fn set_val(&mut self, val: u32) { - self.0 = (self.0 & !(0x00ff_ffff << 0usize)) | (((val as u32) & 0x00ff_ffff) << 0usize); - } -} -impl Default for Bootkey32 { - #[inline(always)] - fn default() -> Bootkey32 { - Bootkey32(0) - } -} -#[repr(transparent)] -#[derive(Copy, Clone, Eq, PartialEq)] -pub struct Bootkey33(pub u32); -impl Bootkey33 { - #[inline(always)] - pub const fn val(&self) -> u32 { - let val = (self.0 >> 0usize) & 0x00ff_ffff; - val as u32 - } - #[inline(always)] - pub fn set_val(&mut self, val: u32) { - self.0 = (self.0 & !(0x00ff_ffff << 0usize)) | (((val as u32) & 0x00ff_ffff) << 0usize); - } -} -impl Default for Bootkey33 { - #[inline(always)] - fn default() -> Bootkey33 { - Bootkey33(0) - } -} -#[repr(transparent)] -#[derive(Copy, Clone, Eq, PartialEq)] -pub struct Bootkey34(pub u32); -impl Bootkey34 { - #[inline(always)] - pub const fn val(&self) -> u32 { - let val = (self.0 >> 0usize) & 0x00ff_ffff; - val as u32 - } - #[inline(always)] - pub fn set_val(&mut self, val: u32) { - self.0 = (self.0 & !(0x00ff_ffff << 0usize)) | (((val as u32) & 0x00ff_ffff) << 0usize); - } -} -impl Default for Bootkey34 { - #[inline(always)] - fn default() -> Bootkey34 { - Bootkey34(0) - } -} -#[repr(transparent)] -#[derive(Copy, Clone, Eq, PartialEq)] -pub struct Bootkey35(pub u32); -impl Bootkey35 { - #[inline(always)] - pub const fn val(&self) -> u32 { - let val = (self.0 >> 0usize) & 0x00ff_ffff; - val as u32 - } - #[inline(always)] - pub fn set_val(&mut self, val: u32) { - self.0 = (self.0 & !(0x00ff_ffff << 0usize)) | (((val as u32) & 0x00ff_ffff) << 0usize); - } -} -impl Default for Bootkey35 { - #[inline(always)] - fn default() -> Bootkey35 { - Bootkey35(0) - } -} -#[repr(transparent)] -#[derive(Copy, Clone, Eq, PartialEq)] -pub struct Bootkey36(pub u32); -impl Bootkey36 { - #[inline(always)] - pub const fn val(&self) -> u32 { - let val = (self.0 >> 0usize) & 0x00ff_ffff; - val as u32 - } - #[inline(always)] - pub fn set_val(&mut self, val: u32) { - self.0 = (self.0 & !(0x00ff_ffff << 0usize)) | (((val as u32) & 0x00ff_ffff) << 0usize); - } -} -impl Default for Bootkey36 { - #[inline(always)] - fn default() -> Bootkey36 { - Bootkey36(0) - } -} -#[repr(transparent)] -#[derive(Copy, Clone, Eq, PartialEq)] -pub struct Bootkey37(pub u32); -impl Bootkey37 { - #[inline(always)] - pub const fn val(&self) -> u32 { - let val = (self.0 >> 0usize) & 0x00ff_ffff; - val as u32 - } - #[inline(always)] - pub fn set_val(&mut self, val: u32) { - self.0 = (self.0 & !(0x00ff_ffff << 0usize)) | (((val as u32) & 0x00ff_ffff) << 0usize); - } -} -impl Default for Bootkey37 { - #[inline(always)] - fn default() -> Bootkey37 { - Bootkey37(0) - } -} -#[repr(transparent)] -#[derive(Copy, Clone, Eq, PartialEq)] -pub struct Bootkey38(pub u32); -impl Bootkey38 { - #[inline(always)] - pub const fn val(&self) -> u32 { - let val = (self.0 >> 0usize) & 0x00ff_ffff; - val as u32 - } - #[inline(always)] - pub fn set_val(&mut self, val: u32) { - self.0 = (self.0 & !(0x00ff_ffff << 0usize)) | (((val as u32) & 0x00ff_ffff) << 0usize); - } -} -impl Default for Bootkey38 { - #[inline(always)] - fn default() -> Bootkey38 { - Bootkey38(0) - } -} -#[repr(transparent)] -#[derive(Copy, Clone, Eq, PartialEq)] -pub struct Bootkey39(pub u32); -impl Bootkey39 { - #[inline(always)] - pub const fn val(&self) -> u32 { - let val = (self.0 >> 0usize) & 0x00ff_ffff; - val as u32 - } - #[inline(always)] - pub fn set_val(&mut self, val: u32) { - self.0 = (self.0 & !(0x00ff_ffff << 0usize)) | (((val as u32) & 0x00ff_ffff) << 0usize); - } -} -impl Default for Bootkey39 { - #[inline(always)] - fn default() -> Bootkey39 { - Bootkey39(0) - } -} -#[repr(transparent)] -#[derive(Copy, Clone, Eq, PartialEq)] -pub struct Chipid0(pub u32); -impl Chipid0 { - #[inline(always)] - pub const fn val(&self) -> u32 { - let val = (self.0 >> 0usize) & 0x00ff_ffff; - val as u32 - } - #[inline(always)] - pub fn set_val(&mut self, val: u32) { - self.0 = (self.0 & !(0x00ff_ffff << 0usize)) | (((val as u32) & 0x00ff_ffff) << 0usize); - } -} -impl Default for Chipid0 { - #[inline(always)] - fn default() -> Chipid0 { - Chipid0(0) - } -} -#[repr(transparent)] -#[derive(Copy, Clone, Eq, PartialEq)] -pub struct Chipid1(pub u32); -impl Chipid1 { - #[inline(always)] - pub const fn val(&self) -> u32 { - let val = (self.0 >> 0usize) & 0x00ff_ffff; - val as u32 - } - #[inline(always)] - pub fn set_val(&mut self, val: u32) { - self.0 = (self.0 & !(0x00ff_ffff << 0usize)) | (((val as u32) & 0x00ff_ffff) << 0usize); - } -} -impl Default for Chipid1 { - #[inline(always)] - fn default() -> Chipid1 { - Chipid1(0) - } -} -#[repr(transparent)] -#[derive(Copy, Clone, Eq, PartialEq)] -pub struct Chipid2(pub u32); -impl Chipid2 { - #[inline(always)] - pub const fn val(&self) -> u32 { - let val = (self.0 >> 0usize) & 0x00ff_ffff; - val as u32 - } - #[inline(always)] - pub fn set_val(&mut self, val: u32) { - self.0 = (self.0 & !(0x00ff_ffff << 0usize)) | (((val as u32) & 0x00ff_ffff) << 0usize); - } -} -impl Default for Chipid2 { - #[inline(always)] - fn default() -> Chipid2 { - Chipid2(0) - } -} -#[repr(transparent)] -#[derive(Copy, Clone, Eq, PartialEq)] -pub struct Chipid3(pub u32); -impl Chipid3 { - #[inline(always)] - pub const fn val(&self) -> u32 { - let val = (self.0 >> 0usize) & 0x00ff_ffff; - val as u32 - } - #[inline(always)] - pub fn set_val(&mut self, val: u32) { - self.0 = (self.0 & !(0x00ff_ffff << 0usize)) | (((val as u32) & 0x00ff_ffff) << 0usize); - } -} -impl Default for Chipid3 { - #[inline(always)] - fn default() -> Chipid3 { - Chipid3(0) - } -} -#[repr(transparent)] -#[derive(Copy, Clone, Eq, PartialEq)] -pub struct Crit0R1(pub u32); -impl Crit0R1 { - #[inline(always)] - pub const fn val(&self) -> u32 { - let val = (self.0 >> 0usize) & 0x00ff_ffff; - val as u32 - } - #[inline(always)] - pub fn set_val(&mut self, val: u32) { - self.0 = (self.0 & !(0x00ff_ffff << 0usize)) | (((val as u32) & 0x00ff_ffff) << 0usize); - } -} -impl Default for Crit0R1 { - #[inline(always)] - fn default() -> Crit0R1 { - Crit0R1(0) - } -} -#[repr(transparent)] -#[derive(Copy, Clone, Eq, PartialEq)] -pub struct Crit0R2(pub u32); -impl Crit0R2 { - #[inline(always)] - pub const fn val(&self) -> u32 { - let val = (self.0 >> 0usize) & 0x00ff_ffff; - val as u32 - } - #[inline(always)] - pub fn set_val(&mut self, val: u32) { - self.0 = (self.0 & !(0x00ff_ffff << 0usize)) | (((val as u32) & 0x00ff_ffff) << 0usize); - } -} -impl Default for Crit0R2 { - #[inline(always)] - fn default() -> Crit0R2 { - Crit0R2(0) - } -} -#[repr(transparent)] -#[derive(Copy, Clone, Eq, PartialEq)] -pub struct Crit0R3(pub u32); -impl Crit0R3 { - #[inline(always)] - pub const fn val(&self) -> u32 { - let val = (self.0 >> 0usize) & 0x00ff_ffff; - val as u32 - } - #[inline(always)] - pub fn set_val(&mut self, val: u32) { - self.0 = (self.0 & !(0x00ff_ffff << 0usize)) | (((val as u32) & 0x00ff_ffff) << 0usize); - } -} -impl Default for Crit0R3 { - #[inline(always)] - fn default() -> Crit0R3 { - Crit0R3(0) - } -} -#[repr(transparent)] -#[derive(Copy, Clone, Eq, PartialEq)] -pub struct Crit0R4(pub u32); -impl Crit0R4 { - #[inline(always)] - pub const fn val(&self) -> u32 { - let val = (self.0 >> 0usize) & 0x00ff_ffff; - val as u32 - } - #[inline(always)] - pub fn set_val(&mut self, val: u32) { - self.0 = (self.0 & !(0x00ff_ffff << 0usize)) | (((val as u32) & 0x00ff_ffff) << 0usize); - } -} -impl Default for Crit0R4 { - #[inline(always)] - fn default() -> Crit0R4 { - Crit0R4(0) - } -} -#[repr(transparent)] -#[derive(Copy, Clone, Eq, PartialEq)] -pub struct Crit0R5(pub u32); -impl Crit0R5 { - #[inline(always)] - pub const fn val(&self) -> u32 { - let val = (self.0 >> 0usize) & 0x00ff_ffff; - val as u32 - } - #[inline(always)] - pub fn set_val(&mut self, val: u32) { - self.0 = (self.0 & !(0x00ff_ffff << 0usize)) | (((val as u32) & 0x00ff_ffff) << 0usize); - } -} -impl Default for Crit0R5 { - #[inline(always)] - fn default() -> Crit0R5 { - Crit0R5(0) - } -} -#[repr(transparent)] -#[derive(Copy, Clone, Eq, PartialEq)] -pub struct Crit0R6(pub u32); -impl Crit0R6 { - #[inline(always)] - pub const fn val(&self) -> u32 { - let val = (self.0 >> 0usize) & 0x00ff_ffff; - val as u32 - } - #[inline(always)] - pub fn set_val(&mut self, val: u32) { - self.0 = (self.0 & !(0x00ff_ffff << 0usize)) | (((val as u32) & 0x00ff_ffff) << 0usize); - } -} -impl Default for Crit0R6 { - #[inline(always)] - fn default() -> Crit0R6 { - Crit0R6(0) - } -} -#[repr(transparent)] -#[derive(Copy, Clone, Eq, PartialEq)] -pub struct Crit0R7(pub u32); -impl Crit0R7 { - #[inline(always)] - pub const fn val(&self) -> u32 { - let val = (self.0 >> 0usize) & 0x00ff_ffff; - val as u32 - } - #[inline(always)] - pub fn set_val(&mut self, val: u32) { - self.0 = (self.0 & !(0x00ff_ffff << 0usize)) | (((val as u32) & 0x00ff_ffff) << 0usize); - } -} -impl Default for Crit0R7 { - #[inline(always)] - fn default() -> Crit0R7 { - Crit0R7(0) - } -} -#[repr(transparent)] -#[derive(Copy, Clone, Eq, PartialEq)] -pub struct Crit1R1(pub u32); -impl Crit1R1 { - #[inline(always)] - pub const fn val(&self) -> u32 { - let val = (self.0 >> 0usize) & 0x00ff_ffff; - val as u32 - } - #[inline(always)] - pub fn set_val(&mut self, val: u32) { - self.0 = (self.0 & !(0x00ff_ffff << 0usize)) | (((val as u32) & 0x00ff_ffff) << 0usize); - } -} -impl Default for Crit1R1 { - #[inline(always)] - fn default() -> Crit1R1 { - Crit1R1(0) - } -} -#[repr(transparent)] -#[derive(Copy, Clone, Eq, PartialEq)] -pub struct Crit1R2(pub u32); -impl Crit1R2 { - #[inline(always)] - pub const fn val(&self) -> u32 { - let val = (self.0 >> 0usize) & 0x00ff_ffff; - val as u32 - } - #[inline(always)] - pub fn set_val(&mut self, val: u32) { - self.0 = (self.0 & !(0x00ff_ffff << 0usize)) | (((val as u32) & 0x00ff_ffff) << 0usize); - } -} -impl Default for Crit1R2 { - #[inline(always)] - fn default() -> Crit1R2 { - Crit1R2(0) - } -} -#[repr(transparent)] -#[derive(Copy, Clone, Eq, PartialEq)] -pub struct Crit1R3(pub u32); -impl Crit1R3 { - #[inline(always)] - pub const fn val(&self) -> u32 { - let val = (self.0 >> 0usize) & 0x00ff_ffff; - val as u32 - } - #[inline(always)] - pub fn set_val(&mut self, val: u32) { - self.0 = (self.0 & !(0x00ff_ffff << 0usize)) | (((val as u32) & 0x00ff_ffff) << 0usize); - } -} -impl Default for Crit1R3 { - #[inline(always)] - fn default() -> Crit1R3 { - Crit1R3(0) - } -} -#[repr(transparent)] -#[derive(Copy, Clone, Eq, PartialEq)] -pub struct Crit1R4(pub u32); -impl Crit1R4 { - #[inline(always)] - pub const fn val(&self) -> u32 { - let val = (self.0 >> 0usize) & 0x00ff_ffff; - val as u32 - } - #[inline(always)] - pub fn set_val(&mut self, val: u32) { - self.0 = (self.0 & !(0x00ff_ffff << 0usize)) | (((val as u32) & 0x00ff_ffff) << 0usize); - } -} -impl Default for Crit1R4 { - #[inline(always)] - fn default() -> Crit1R4 { - Crit1R4(0) - } -} -#[repr(transparent)] -#[derive(Copy, Clone, Eq, PartialEq)] -pub struct Crit1R5(pub u32); -impl Crit1R5 { - #[inline(always)] - pub const fn val(&self) -> u32 { - let val = (self.0 >> 0usize) & 0x00ff_ffff; - val as u32 - } - #[inline(always)] - pub fn set_val(&mut self, val: u32) { - self.0 = (self.0 & !(0x00ff_ffff << 0usize)) | (((val as u32) & 0x00ff_ffff) << 0usize); - } -} -impl Default for Crit1R5 { - #[inline(always)] - fn default() -> Crit1R5 { - Crit1R5(0) - } -} -#[repr(transparent)] -#[derive(Copy, Clone, Eq, PartialEq)] -pub struct Crit1R6(pub u32); -impl Crit1R6 { - #[inline(always)] - pub const fn val(&self) -> u32 { - let val = (self.0 >> 0usize) & 0x00ff_ffff; - val as u32 - } - #[inline(always)] - pub fn set_val(&mut self, val: u32) { - self.0 = (self.0 & !(0x00ff_ffff << 0usize)) | (((val as u32) & 0x00ff_ffff) << 0usize); - } -} -impl Default for Crit1R6 { - #[inline(always)] - fn default() -> Crit1R6 { - Crit1R6(0) - } -} -#[repr(transparent)] -#[derive(Copy, Clone, Eq, PartialEq)] -pub struct Crit1R7(pub u32); -impl Crit1R7 { - #[inline(always)] - pub const fn val(&self) -> u32 { - let val = (self.0 >> 0usize) & 0x00ff_ffff; - val as u32 - } - #[inline(always)] - pub fn set_val(&mut self, val: u32) { - self.0 = (self.0 & !(0x00ff_ffff << 0usize)) | (((val as u32) & 0x00ff_ffff) << 0usize); - } -} -impl Default for Crit1R7 { - #[inline(always)] - fn default() -> Crit1R7 { - Crit1R7(0) - } -} -#[repr(transparent)] -#[derive(Copy, Clone, Eq, PartialEq)] -pub struct DefaultBootVersion0(pub u32); -impl DefaultBootVersion0 { - #[inline(always)] - pub const fn val(&self) -> u32 { - let val = (self.0 >> 0usize) & 0x00ff_ffff; - val as u32 - } - #[inline(always)] - pub fn set_val(&mut self, val: u32) { - self.0 = (self.0 & !(0x00ff_ffff << 0usize)) | (((val as u32) & 0x00ff_ffff) << 0usize); - } -} -impl Default for DefaultBootVersion0 { - #[inline(always)] - fn default() -> DefaultBootVersion0 { - DefaultBootVersion0(0) - } -} -#[repr(transparent)] -#[derive(Copy, Clone, Eq, PartialEq)] -pub struct DefaultBootVersion0R1(pub u32); -impl DefaultBootVersion0R1 { - #[inline(always)] - pub const fn val(&self) -> u32 { - let val = (self.0 >> 0usize) & 0x00ff_ffff; - val as u32 - } - #[inline(always)] - pub fn set_val(&mut self, val: u32) { - self.0 = (self.0 & !(0x00ff_ffff << 0usize)) | (((val as u32) & 0x00ff_ffff) << 0usize); - } -} -impl Default for DefaultBootVersion0R1 { - #[inline(always)] - fn default() -> DefaultBootVersion0R1 { - DefaultBootVersion0R1(0) - } -} -#[repr(transparent)] -#[derive(Copy, Clone, Eq, PartialEq)] -pub struct DefaultBootVersion0R2(pub u32); -impl DefaultBootVersion0R2 { - #[inline(always)] - pub const fn val(&self) -> u32 { - let val = (self.0 >> 0usize) & 0x00ff_ffff; - val as u32 - } - #[inline(always)] - pub fn set_val(&mut self, val: u32) { - self.0 = (self.0 & !(0x00ff_ffff << 0usize)) | (((val as u32) & 0x00ff_ffff) << 0usize); - } -} -impl Default for DefaultBootVersion0R2 { - #[inline(always)] - fn default() -> DefaultBootVersion0R2 { - DefaultBootVersion0R2(0) - } -} -#[repr(transparent)] -#[derive(Copy, Clone, Eq, PartialEq)] -pub struct DefaultBootVersion1(pub u32); -impl DefaultBootVersion1 { - #[inline(always)] - pub const fn val(&self) -> u32 { - let val = (self.0 >> 0usize) & 0x00ff_ffff; - val as u32 - } - #[inline(always)] - pub fn set_val(&mut self, val: u32) { - self.0 = (self.0 & !(0x00ff_ffff << 0usize)) | (((val as u32) & 0x00ff_ffff) << 0usize); - } -} -impl Default for DefaultBootVersion1 { - #[inline(always)] - fn default() -> DefaultBootVersion1 { - DefaultBootVersion1(0) - } -} -#[repr(transparent)] -#[derive(Copy, Clone, Eq, PartialEq)] -pub struct DefaultBootVersion1R1(pub u32); -impl DefaultBootVersion1R1 { - #[inline(always)] - pub const fn val(&self) -> u32 { - let val = (self.0 >> 0usize) & 0x00ff_ffff; - val as u32 - } - #[inline(always)] - pub fn set_val(&mut self, val: u32) { - self.0 = (self.0 & !(0x00ff_ffff << 0usize)) | (((val as u32) & 0x00ff_ffff) << 0usize); - } -} -impl Default for DefaultBootVersion1R1 { - #[inline(always)] - fn default() -> DefaultBootVersion1R1 { - DefaultBootVersion1R1(0) - } -} -#[repr(transparent)] -#[derive(Copy, Clone, Eq, PartialEq)] -pub struct DefaultBootVersion1R2(pub u32); -impl DefaultBootVersion1R2 { - #[inline(always)] - pub const fn val(&self) -> u32 { - let val = (self.0 >> 0usize) & 0x00ff_ffff; - val as u32 - } - #[inline(always)] - pub fn set_val(&mut self, val: u32) { - self.0 = (self.0 & !(0x00ff_ffff << 0usize)) | (((val as u32) & 0x00ff_ffff) << 0usize); - } -} -impl Default for DefaultBootVersion1R2 { - #[inline(always)] - fn default() -> DefaultBootVersion1R2 { - DefaultBootVersion1R2(0) - } -} -#[repr(transparent)] -#[derive(Copy, Clone, Eq, PartialEq)] -pub struct FlashPartitionSlotSize(pub u32); -impl FlashPartitionSlotSize { - #[inline(always)] - pub const fn val(&self) -> u32 { - let val = (self.0 >> 0usize) & 0x00ff_ffff; - val as u32 - } - #[inline(always)] - pub fn set_val(&mut self, val: u32) { - self.0 = (self.0 & !(0x00ff_ffff << 0usize)) | (((val as u32) & 0x00ff_ffff) << 0usize); - } -} -impl Default for FlashPartitionSlotSize { - #[inline(always)] - fn default() -> FlashPartitionSlotSize { - FlashPartitionSlotSize(0) - } -} -#[repr(transparent)] -#[derive(Copy, Clone, Eq, PartialEq)] -pub struct InfoCrc0(pub u32); -impl InfoCrc0 { - #[inline(always)] - pub const fn val(&self) -> u32 { - let val = (self.0 >> 0usize) & 0x00ff_ffff; - val as u32 - } - #[inline(always)] - pub fn set_val(&mut self, val: u32) { - self.0 = (self.0 & !(0x00ff_ffff << 0usize)) | (((val as u32) & 0x00ff_ffff) << 0usize); - } -} -impl Default for InfoCrc0 { - #[inline(always)] - fn default() -> InfoCrc0 { - InfoCrc0(0) - } -} -#[repr(transparent)] -#[derive(Copy, Clone, Eq, PartialEq)] -pub struct InfoCrc1(pub u32); -impl InfoCrc1 { - #[inline(always)] - pub const fn val(&self) -> u32 { - let val = (self.0 >> 0usize) & 0x00ff_ffff; - val as u32 - } - #[inline(always)] - pub fn set_val(&mut self, val: u32) { - self.0 = (self.0 & !(0x00ff_ffff << 0usize)) | (((val as u32) & 0x00ff_ffff) << 0usize); - } -} -impl Default for InfoCrc1 { - #[inline(always)] - fn default() -> InfoCrc1 { - InfoCrc1(0) - } -} -#[repr(transparent)] -#[derive(Copy, Clone, Eq, PartialEq)] -pub struct Key10(pub u32); -impl Key10 { - #[inline(always)] - pub const fn val(&self) -> u32 { - let val = (self.0 >> 0usize) & 0x00ff_ffff; - val as u32 - } - #[inline(always)] - pub fn set_val(&mut self, val: u32) { - self.0 = (self.0 & !(0x00ff_ffff << 0usize)) | (((val as u32) & 0x00ff_ffff) << 0usize); - } -} -impl Default for Key10 { - #[inline(always)] - fn default() -> Key10 { - Key10(0) - } -} -#[repr(transparent)] -#[derive(Copy, Clone, Eq, PartialEq)] -pub struct Key11(pub u32); -impl Key11 { - #[inline(always)] - pub const fn val(&self) -> u32 { - let val = (self.0 >> 0usize) & 0x00ff_ffff; - val as u32 - } - #[inline(always)] - pub fn set_val(&mut self, val: u32) { - self.0 = (self.0 & !(0x00ff_ffff << 0usize)) | (((val as u32) & 0x00ff_ffff) << 0usize); - } -} -impl Default for Key11 { - #[inline(always)] - fn default() -> Key11 { - Key11(0) - } -} -#[repr(transparent)] -#[derive(Copy, Clone, Eq, PartialEq)] -pub struct Key12(pub u32); -impl Key12 { - #[inline(always)] - pub const fn val(&self) -> u32 { - let val = (self.0 >> 0usize) & 0x00ff_ffff; - val as u32 - } - #[inline(always)] - pub fn set_val(&mut self, val: u32) { - self.0 = (self.0 & !(0x00ff_ffff << 0usize)) | (((val as u32) & 0x00ff_ffff) << 0usize); - } -} -impl Default for Key12 { - #[inline(always)] - fn default() -> Key12 { - Key12(0) - } -} -#[repr(transparent)] -#[derive(Copy, Clone, Eq, PartialEq)] -pub struct Key13(pub u32); -impl Key13 { - #[inline(always)] - pub const fn val(&self) -> u32 { - let val = (self.0 >> 0usize) & 0x00ff_ffff; - val as u32 - } - #[inline(always)] - pub fn set_val(&mut self, val: u32) { - self.0 = (self.0 & !(0x00ff_ffff << 0usize)) | (((val as u32) & 0x00ff_ffff) << 0usize); - } -} -impl Default for Key13 { - #[inline(always)] - fn default() -> Key13 { - Key13(0) - } -} -#[repr(transparent)] -#[derive(Copy, Clone, Eq, PartialEq)] -pub struct Key14(pub u32); -impl Key14 { - #[inline(always)] - pub const fn val(&self) -> u32 { - let val = (self.0 >> 0usize) & 0x00ff_ffff; - val as u32 - } - #[inline(always)] - pub fn set_val(&mut self, val: u32) { - self.0 = (self.0 & !(0x00ff_ffff << 0usize)) | (((val as u32) & 0x00ff_ffff) << 0usize); - } -} -impl Default for Key14 { - #[inline(always)] - fn default() -> Key14 { - Key14(0) - } -} -#[repr(transparent)] -#[derive(Copy, Clone, Eq, PartialEq)] -pub struct Key15(pub u32); -impl Key15 { - #[inline(always)] - pub const fn val(&self) -> u32 { - let val = (self.0 >> 0usize) & 0x00ff_ffff; - val as u32 - } - #[inline(always)] - pub fn set_val(&mut self, val: u32) { - self.0 = (self.0 & !(0x00ff_ffff << 0usize)) | (((val as u32) & 0x00ff_ffff) << 0usize); - } -} -impl Default for Key15 { - #[inline(always)] - fn default() -> Key15 { - Key15(0) - } -} -#[repr(transparent)] -#[derive(Copy, Clone, Eq, PartialEq)] -pub struct Key16(pub u32); -impl Key16 { - #[inline(always)] - pub const fn val(&self) -> u32 { - let val = (self.0 >> 0usize) & 0x00ff_ffff; - val as u32 - } - #[inline(always)] - pub fn set_val(&mut self, val: u32) { - self.0 = (self.0 & !(0x00ff_ffff << 0usize)) | (((val as u32) & 0x00ff_ffff) << 0usize); - } -} -impl Default for Key16 { - #[inline(always)] - fn default() -> Key16 { - Key16(0) - } -} -#[repr(transparent)] -#[derive(Copy, Clone, Eq, PartialEq)] -pub struct Key17(pub u32); -impl Key17 { - #[inline(always)] - pub const fn val(&self) -> u32 { - let val = (self.0 >> 0usize) & 0x00ff_ffff; - val as u32 - } - #[inline(always)] - pub fn set_val(&mut self, val: u32) { - self.0 = (self.0 & !(0x00ff_ffff << 0usize)) | (((val as u32) & 0x00ff_ffff) << 0usize); - } -} -impl Default for Key17 { - #[inline(always)] - fn default() -> Key17 { - Key17(0) - } -} -#[repr(transparent)] -#[derive(Copy, Clone, Eq, PartialEq)] -pub struct Key20(pub u32); -impl Key20 { - #[inline(always)] - pub const fn val(&self) -> u32 { - let val = (self.0 >> 0usize) & 0x00ff_ffff; - val as u32 - } - #[inline(always)] - pub fn set_val(&mut self, val: u32) { - self.0 = (self.0 & !(0x00ff_ffff << 0usize)) | (((val as u32) & 0x00ff_ffff) << 0usize); - } -} -impl Default for Key20 { - #[inline(always)] - fn default() -> Key20 { - Key20(0) - } -} -#[repr(transparent)] -#[derive(Copy, Clone, Eq, PartialEq)] -pub struct Key21(pub u32); -impl Key21 { - #[inline(always)] - pub const fn val(&self) -> u32 { - let val = (self.0 >> 0usize) & 0x00ff_ffff; - val as u32 - } - #[inline(always)] - pub fn set_val(&mut self, val: u32) { - self.0 = (self.0 & !(0x00ff_ffff << 0usize)) | (((val as u32) & 0x00ff_ffff) << 0usize); - } -} -impl Default for Key21 { - #[inline(always)] - fn default() -> Key21 { - Key21(0) - } -} -#[repr(transparent)] -#[derive(Copy, Clone, Eq, PartialEq)] -pub struct Key22(pub u32); -impl Key22 { - #[inline(always)] - pub const fn val(&self) -> u32 { - let val = (self.0 >> 0usize) & 0x00ff_ffff; - val as u32 - } - #[inline(always)] - pub fn set_val(&mut self, val: u32) { - self.0 = (self.0 & !(0x00ff_ffff << 0usize)) | (((val as u32) & 0x00ff_ffff) << 0usize); - } -} -impl Default for Key22 { - #[inline(always)] - fn default() -> Key22 { - Key22(0) - } -} -#[repr(transparent)] -#[derive(Copy, Clone, Eq, PartialEq)] -pub struct Key23(pub u32); -impl Key23 { - #[inline(always)] - pub const fn val(&self) -> u32 { - let val = (self.0 >> 0usize) & 0x00ff_ffff; - val as u32 - } - #[inline(always)] - pub fn set_val(&mut self, val: u32) { - self.0 = (self.0 & !(0x00ff_ffff << 0usize)) | (((val as u32) & 0x00ff_ffff) << 0usize); - } -} -impl Default for Key23 { - #[inline(always)] - fn default() -> Key23 { - Key23(0) - } -} -#[repr(transparent)] -#[derive(Copy, Clone, Eq, PartialEq)] -pub struct Key24(pub u32); -impl Key24 { - #[inline(always)] - pub const fn val(&self) -> u32 { - let val = (self.0 >> 0usize) & 0x00ff_ffff; - val as u32 - } - #[inline(always)] - pub fn set_val(&mut self, val: u32) { - self.0 = (self.0 & !(0x00ff_ffff << 0usize)) | (((val as u32) & 0x00ff_ffff) << 0usize); - } -} -impl Default for Key24 { - #[inline(always)] - fn default() -> Key24 { - Key24(0) - } -} -#[repr(transparent)] -#[derive(Copy, Clone, Eq, PartialEq)] -pub struct Key25(pub u32); -impl Key25 { - #[inline(always)] - pub const fn val(&self) -> u32 { - let val = (self.0 >> 0usize) & 0x00ff_ffff; - val as u32 - } - #[inline(always)] - pub fn set_val(&mut self, val: u32) { - self.0 = (self.0 & !(0x00ff_ffff << 0usize)) | (((val as u32) & 0x00ff_ffff) << 0usize); - } -} -impl Default for Key25 { - #[inline(always)] - fn default() -> Key25 { - Key25(0) - } -} -#[repr(transparent)] -#[derive(Copy, Clone, Eq, PartialEq)] -pub struct Key26(pub u32); -impl Key26 { - #[inline(always)] - pub const fn val(&self) -> u32 { - let val = (self.0 >> 0usize) & 0x00ff_ffff; - val as u32 - } - #[inline(always)] - pub fn set_val(&mut self, val: u32) { - self.0 = (self.0 & !(0x00ff_ffff << 0usize)) | (((val as u32) & 0x00ff_ffff) << 0usize); - } -} -impl Default for Key26 { - #[inline(always)] - fn default() -> Key26 { - Key26(0) - } -} -#[repr(transparent)] -#[derive(Copy, Clone, Eq, PartialEq)] -pub struct Key27(pub u32); -impl Key27 { - #[inline(always)] - pub const fn val(&self) -> u32 { - let val = (self.0 >> 0usize) & 0x00ff_ffff; - val as u32 - } - #[inline(always)] - pub fn set_val(&mut self, val: u32) { - self.0 = (self.0 & !(0x00ff_ffff << 0usize)) | (((val as u32) & 0x00ff_ffff) << 0usize); - } -} -impl Default for Key27 { - #[inline(always)] - fn default() -> Key27 { - Key27(0) - } -} -#[repr(transparent)] -#[derive(Copy, Clone, Eq, PartialEq)] -pub struct Key30(pub u32); -impl Key30 { - #[inline(always)] - pub const fn val(&self) -> u32 { - let val = (self.0 >> 0usize) & 0x00ff_ffff; - val as u32 - } - #[inline(always)] - pub fn set_val(&mut self, val: u32) { - self.0 = (self.0 & !(0x00ff_ffff << 0usize)) | (((val as u32) & 0x00ff_ffff) << 0usize); - } -} -impl Default for Key30 { - #[inline(always)] - fn default() -> Key30 { - Key30(0) - } -} -#[repr(transparent)] -#[derive(Copy, Clone, Eq, PartialEq)] -pub struct Key31(pub u32); -impl Key31 { - #[inline(always)] - pub const fn val(&self) -> u32 { - let val = (self.0 >> 0usize) & 0x00ff_ffff; - val as u32 - } - #[inline(always)] - pub fn set_val(&mut self, val: u32) { - self.0 = (self.0 & !(0x00ff_ffff << 0usize)) | (((val as u32) & 0x00ff_ffff) << 0usize); - } -} -impl Default for Key31 { - #[inline(always)] - fn default() -> Key31 { - Key31(0) - } -} -#[repr(transparent)] -#[derive(Copy, Clone, Eq, PartialEq)] -pub struct Key32(pub u32); -impl Key32 { - #[inline(always)] - pub const fn val(&self) -> u32 { - let val = (self.0 >> 0usize) & 0x00ff_ffff; - val as u32 - } - #[inline(always)] - pub fn set_val(&mut self, val: u32) { - self.0 = (self.0 & !(0x00ff_ffff << 0usize)) | (((val as u32) & 0x00ff_ffff) << 0usize); - } -} -impl Default for Key32 { - #[inline(always)] - fn default() -> Key32 { - Key32(0) - } -} -#[repr(transparent)] -#[derive(Copy, Clone, Eq, PartialEq)] -pub struct Key33(pub u32); -impl Key33 { - #[inline(always)] - pub const fn val(&self) -> u32 { - let val = (self.0 >> 0usize) & 0x00ff_ffff; - val as u32 - } - #[inline(always)] - pub fn set_val(&mut self, val: u32) { - self.0 = (self.0 & !(0x00ff_ffff << 0usize)) | (((val as u32) & 0x00ff_ffff) << 0usize); - } -} -impl Default for Key33 { - #[inline(always)] - fn default() -> Key33 { - Key33(0) - } -} -#[repr(transparent)] -#[derive(Copy, Clone, Eq, PartialEq)] -pub struct Key34(pub u32); -impl Key34 { - #[inline(always)] - pub const fn val(&self) -> u32 { - let val = (self.0 >> 0usize) & 0x00ff_ffff; - val as u32 - } - #[inline(always)] - pub fn set_val(&mut self, val: u32) { - self.0 = (self.0 & !(0x00ff_ffff << 0usize)) | (((val as u32) & 0x00ff_ffff) << 0usize); - } -} -impl Default for Key34 { - #[inline(always)] - fn default() -> Key34 { - Key34(0) - } -} -#[repr(transparent)] -#[derive(Copy, Clone, Eq, PartialEq)] -pub struct Key35(pub u32); -impl Key35 { - #[inline(always)] - pub const fn val(&self) -> u32 { - let val = (self.0 >> 0usize) & 0x00ff_ffff; - val as u32 - } - #[inline(always)] - pub fn set_val(&mut self, val: u32) { - self.0 = (self.0 & !(0x00ff_ffff << 0usize)) | (((val as u32) & 0x00ff_ffff) << 0usize); - } -} -impl Default for Key35 { - #[inline(always)] - fn default() -> Key35 { - Key35(0) - } -} -#[repr(transparent)] -#[derive(Copy, Clone, Eq, PartialEq)] -pub struct Key36(pub u32); -impl Key36 { - #[inline(always)] - pub const fn val(&self) -> u32 { - let val = (self.0 >> 0usize) & 0x00ff_ffff; - val as u32 - } - #[inline(always)] - pub fn set_val(&mut self, val: u32) { - self.0 = (self.0 & !(0x00ff_ffff << 0usize)) | (((val as u32) & 0x00ff_ffff) << 0usize); - } -} -impl Default for Key36 { - #[inline(always)] - fn default() -> Key36 { - Key36(0) - } -} -#[repr(transparent)] -#[derive(Copy, Clone, Eq, PartialEq)] -pub struct Key37(pub u32); -impl Key37 { - #[inline(always)] - pub const fn val(&self) -> u32 { - let val = (self.0 >> 0usize) & 0x00ff_ffff; - val as u32 - } - #[inline(always)] - pub fn set_val(&mut self, val: u32) { - self.0 = (self.0 & !(0x00ff_ffff << 0usize)) | (((val as u32) & 0x00ff_ffff) << 0usize); - } -} -impl Default for Key37 { - #[inline(always)] - fn default() -> Key37 { - Key37(0) - } -} -#[repr(transparent)] -#[derive(Copy, Clone, Eq, PartialEq)] -pub struct Key40(pub u32); -impl Key40 { - #[inline(always)] - pub const fn val(&self) -> u32 { - let val = (self.0 >> 0usize) & 0x00ff_ffff; - val as u32 - } - #[inline(always)] - pub fn set_val(&mut self, val: u32) { - self.0 = (self.0 & !(0x00ff_ffff << 0usize)) | (((val as u32) & 0x00ff_ffff) << 0usize); - } -} -impl Default for Key40 { - #[inline(always)] - fn default() -> Key40 { - Key40(0) - } -} -#[repr(transparent)] -#[derive(Copy, Clone, Eq, PartialEq)] -pub struct Key41(pub u32); -impl Key41 { - #[inline(always)] - pub const fn val(&self) -> u32 { - let val = (self.0 >> 0usize) & 0x00ff_ffff; - val as u32 - } - #[inline(always)] - pub fn set_val(&mut self, val: u32) { - self.0 = (self.0 & !(0x00ff_ffff << 0usize)) | (((val as u32) & 0x00ff_ffff) << 0usize); - } -} -impl Default for Key41 { - #[inline(always)] - fn default() -> Key41 { - Key41(0) - } -} -#[repr(transparent)] -#[derive(Copy, Clone, Eq, PartialEq)] -pub struct Key42(pub u32); -impl Key42 { - #[inline(always)] - pub const fn val(&self) -> u32 { - let val = (self.0 >> 0usize) & 0x00ff_ffff; - val as u32 - } - #[inline(always)] - pub fn set_val(&mut self, val: u32) { - self.0 = (self.0 & !(0x00ff_ffff << 0usize)) | (((val as u32) & 0x00ff_ffff) << 0usize); - } -} -impl Default for Key42 { - #[inline(always)] - fn default() -> Key42 { - Key42(0) - } -} -#[repr(transparent)] -#[derive(Copy, Clone, Eq, PartialEq)] -pub struct Key43(pub u32); -impl Key43 { - #[inline(always)] - pub const fn val(&self) -> u32 { - let val = (self.0 >> 0usize) & 0x00ff_ffff; - val as u32 - } - #[inline(always)] - pub fn set_val(&mut self, val: u32) { - self.0 = (self.0 & !(0x00ff_ffff << 0usize)) | (((val as u32) & 0x00ff_ffff) << 0usize); - } -} -impl Default for Key43 { - #[inline(always)] - fn default() -> Key43 { - Key43(0) - } -} -#[repr(transparent)] -#[derive(Copy, Clone, Eq, PartialEq)] -pub struct Key44(pub u32); -impl Key44 { - #[inline(always)] - pub const fn val(&self) -> u32 { - let val = (self.0 >> 0usize) & 0x00ff_ffff; - val as u32 - } - #[inline(always)] - pub fn set_val(&mut self, val: u32) { - self.0 = (self.0 & !(0x00ff_ffff << 0usize)) | (((val as u32) & 0x00ff_ffff) << 0usize); - } -} -impl Default for Key44 { - #[inline(always)] - fn default() -> Key44 { - Key44(0) - } -} -#[repr(transparent)] -#[derive(Copy, Clone, Eq, PartialEq)] -pub struct Key45(pub u32); -impl Key45 { - #[inline(always)] - pub const fn val(&self) -> u32 { - let val = (self.0 >> 0usize) & 0x00ff_ffff; - val as u32 - } - #[inline(always)] - pub fn set_val(&mut self, val: u32) { - self.0 = (self.0 & !(0x00ff_ffff << 0usize)) | (((val as u32) & 0x00ff_ffff) << 0usize); - } -} -impl Default for Key45 { - #[inline(always)] - fn default() -> Key45 { - Key45(0) - } -} -#[repr(transparent)] -#[derive(Copy, Clone, Eq, PartialEq)] -pub struct Key46(pub u32); -impl Key46 { - #[inline(always)] - pub const fn val(&self) -> u32 { - let val = (self.0 >> 0usize) & 0x00ff_ffff; - val as u32 - } - #[inline(always)] - pub fn set_val(&mut self, val: u32) { - self.0 = (self.0 & !(0x00ff_ffff << 0usize)) | (((val as u32) & 0x00ff_ffff) << 0usize); - } -} -impl Default for Key46 { - #[inline(always)] - fn default() -> Key46 { - Key46(0) - } -} -#[repr(transparent)] -#[derive(Copy, Clone, Eq, PartialEq)] -pub struct Key47(pub u32); -impl Key47 { - #[inline(always)] - pub const fn val(&self) -> u32 { - let val = (self.0 >> 0usize) & 0x00ff_ffff; - val as u32 - } - #[inline(always)] - pub fn set_val(&mut self, val: u32) { - self.0 = (self.0 & !(0x00ff_ffff << 0usize)) | (((val as u32) & 0x00ff_ffff) << 0usize); - } -} -impl Default for Key47 { - #[inline(always)] - fn default() -> Key47 { - Key47(0) - } -} -#[repr(transparent)] -#[derive(Copy, Clone, Eq, PartialEq)] -pub struct Key50(pub u32); -impl Key50 { - #[inline(always)] - pub const fn val(&self) -> u32 { - let val = (self.0 >> 0usize) & 0x00ff_ffff; - val as u32 - } - #[inline(always)] - pub fn set_val(&mut self, val: u32) { - self.0 = (self.0 & !(0x00ff_ffff << 0usize)) | (((val as u32) & 0x00ff_ffff) << 0usize); - } -} -impl Default for Key50 { - #[inline(always)] - fn default() -> Key50 { - Key50(0) - } -} -#[repr(transparent)] -#[derive(Copy, Clone, Eq, PartialEq)] -pub struct Key51(pub u32); -impl Key51 { - #[inline(always)] - pub const fn val(&self) -> u32 { - let val = (self.0 >> 0usize) & 0x00ff_ffff; - val as u32 - } - #[inline(always)] - pub fn set_val(&mut self, val: u32) { - self.0 = (self.0 & !(0x00ff_ffff << 0usize)) | (((val as u32) & 0x00ff_ffff) << 0usize); - } -} -impl Default for Key51 { - #[inline(always)] - fn default() -> Key51 { - Key51(0) - } -} -#[repr(transparent)] -#[derive(Copy, Clone, Eq, PartialEq)] -pub struct Key52(pub u32); -impl Key52 { - #[inline(always)] - pub const fn val(&self) -> u32 { - let val = (self.0 >> 0usize) & 0x00ff_ffff; - val as u32 - } - #[inline(always)] - pub fn set_val(&mut self, val: u32) { - self.0 = (self.0 & !(0x00ff_ffff << 0usize)) | (((val as u32) & 0x00ff_ffff) << 0usize); - } -} -impl Default for Key52 { - #[inline(always)] - fn default() -> Key52 { - Key52(0) - } -} -#[repr(transparent)] -#[derive(Copy, Clone, Eq, PartialEq)] -pub struct Key53(pub u32); -impl Key53 { - #[inline(always)] - pub const fn val(&self) -> u32 { - let val = (self.0 >> 0usize) & 0x00ff_ffff; - val as u32 - } - #[inline(always)] - pub fn set_val(&mut self, val: u32) { - self.0 = (self.0 & !(0x00ff_ffff << 0usize)) | (((val as u32) & 0x00ff_ffff) << 0usize); - } -} -impl Default for Key53 { - #[inline(always)] - fn default() -> Key53 { - Key53(0) - } -} -#[repr(transparent)] -#[derive(Copy, Clone, Eq, PartialEq)] -pub struct Key54(pub u32); -impl Key54 { - #[inline(always)] - pub const fn val(&self) -> u32 { - let val = (self.0 >> 0usize) & 0x00ff_ffff; - val as u32 - } - #[inline(always)] - pub fn set_val(&mut self, val: u32) { - self.0 = (self.0 & !(0x00ff_ffff << 0usize)) | (((val as u32) & 0x00ff_ffff) << 0usize); - } -} -impl Default for Key54 { - #[inline(always)] - fn default() -> Key54 { - Key54(0) - } -} -#[repr(transparent)] -#[derive(Copy, Clone, Eq, PartialEq)] -pub struct Key55(pub u32); -impl Key55 { - #[inline(always)] - pub const fn val(&self) -> u32 { - let val = (self.0 >> 0usize) & 0x00ff_ffff; - val as u32 - } - #[inline(always)] - pub fn set_val(&mut self, val: u32) { - self.0 = (self.0 & !(0x00ff_ffff << 0usize)) | (((val as u32) & 0x00ff_ffff) << 0usize); - } -} -impl Default for Key55 { - #[inline(always)] - fn default() -> Key55 { - Key55(0) - } -} -#[repr(transparent)] -#[derive(Copy, Clone, Eq, PartialEq)] -pub struct Key56(pub u32); -impl Key56 { - #[inline(always)] - pub const fn val(&self) -> u32 { - let val = (self.0 >> 0usize) & 0x00ff_ffff; - val as u32 - } - #[inline(always)] - pub fn set_val(&mut self, val: u32) { - self.0 = (self.0 & !(0x00ff_ffff << 0usize)) | (((val as u32) & 0x00ff_ffff) << 0usize); - } -} -impl Default for Key56 { - #[inline(always)] - fn default() -> Key56 { - Key56(0) - } -} -#[repr(transparent)] -#[derive(Copy, Clone, Eq, PartialEq)] -pub struct Key57(pub u32); -impl Key57 { - #[inline(always)] - pub const fn val(&self) -> u32 { - let val = (self.0 >> 0usize) & 0x00ff_ffff; - val as u32 - } - #[inline(always)] - pub fn set_val(&mut self, val: u32) { - self.0 = (self.0 & !(0x00ff_ffff << 0usize)) | (((val as u32) & 0x00ff_ffff) << 0usize); - } -} -impl Default for Key57 { - #[inline(always)] - fn default() -> Key57 { - Key57(0) - } -} -#[repr(transparent)] -#[derive(Copy, Clone, Eq, PartialEq)] -pub struct Key60(pub u32); -impl Key60 { - #[inline(always)] - pub const fn val(&self) -> u32 { - let val = (self.0 >> 0usize) & 0x00ff_ffff; - val as u32 - } - #[inline(always)] - pub fn set_val(&mut self, val: u32) { - self.0 = (self.0 & !(0x00ff_ffff << 0usize)) | (((val as u32) & 0x00ff_ffff) << 0usize); - } -} -impl Default for Key60 { - #[inline(always)] - fn default() -> Key60 { - Key60(0) - } -} -#[repr(transparent)] -#[derive(Copy, Clone, Eq, PartialEq)] -pub struct Key61(pub u32); -impl Key61 { - #[inline(always)] - pub const fn val(&self) -> u32 { - let val = (self.0 >> 0usize) & 0x00ff_ffff; - val as u32 - } - #[inline(always)] - pub fn set_val(&mut self, val: u32) { - self.0 = (self.0 & !(0x00ff_ffff << 0usize)) | (((val as u32) & 0x00ff_ffff) << 0usize); - } -} -impl Default for Key61 { - #[inline(always)] - fn default() -> Key61 { - Key61(0) - } -} -#[repr(transparent)] -#[derive(Copy, Clone, Eq, PartialEq)] -pub struct Key62(pub u32); -impl Key62 { - #[inline(always)] - pub const fn val(&self) -> u32 { - let val = (self.0 >> 0usize) & 0x00ff_ffff; - val as u32 - } - #[inline(always)] - pub fn set_val(&mut self, val: u32) { - self.0 = (self.0 & !(0x00ff_ffff << 0usize)) | (((val as u32) & 0x00ff_ffff) << 0usize); - } -} -impl Default for Key62 { - #[inline(always)] - fn default() -> Key62 { - Key62(0) - } -} -#[repr(transparent)] -#[derive(Copy, Clone, Eq, PartialEq)] -pub struct Key63(pub u32); -impl Key63 { - #[inline(always)] - pub const fn val(&self) -> u32 { - let val = (self.0 >> 0usize) & 0x00ff_ffff; - val as u32 - } - #[inline(always)] - pub fn set_val(&mut self, val: u32) { - self.0 = (self.0 & !(0x00ff_ffff << 0usize)) | (((val as u32) & 0x00ff_ffff) << 0usize); - } -} -impl Default for Key63 { - #[inline(always)] - fn default() -> Key63 { - Key63(0) - } -} -#[repr(transparent)] -#[derive(Copy, Clone, Eq, PartialEq)] -pub struct Key64(pub u32); -impl Key64 { - #[inline(always)] - pub const fn val(&self) -> u32 { - let val = (self.0 >> 0usize) & 0x00ff_ffff; - val as u32 - } - #[inline(always)] - pub fn set_val(&mut self, val: u32) { - self.0 = (self.0 & !(0x00ff_ffff << 0usize)) | (((val as u32) & 0x00ff_ffff) << 0usize); - } -} -impl Default for Key64 { - #[inline(always)] - fn default() -> Key64 { - Key64(0) - } -} -#[repr(transparent)] -#[derive(Copy, Clone, Eq, PartialEq)] -pub struct Key65(pub u32); -impl Key65 { - #[inline(always)] - pub const fn val(&self) -> u32 { - let val = (self.0 >> 0usize) & 0x00ff_ffff; - val as u32 - } - #[inline(always)] - pub fn set_val(&mut self, val: u32) { - self.0 = (self.0 & !(0x00ff_ffff << 0usize)) | (((val as u32) & 0x00ff_ffff) << 0usize); - } -} -impl Default for Key65 { - #[inline(always)] - fn default() -> Key65 { - Key65(0) - } -} -#[repr(transparent)] -#[derive(Copy, Clone, Eq, PartialEq)] -pub struct Key66(pub u32); -impl Key66 { - #[inline(always)] - pub const fn val(&self) -> u32 { - let val = (self.0 >> 0usize) & 0x00ff_ffff; - val as u32 - } - #[inline(always)] - pub fn set_val(&mut self, val: u32) { - self.0 = (self.0 & !(0x00ff_ffff << 0usize)) | (((val as u32) & 0x00ff_ffff) << 0usize); - } -} -impl Default for Key66 { - #[inline(always)] - fn default() -> Key66 { - Key66(0) - } -} -#[repr(transparent)] -#[derive(Copy, Clone, Eq, PartialEq)] -pub struct Key67(pub u32); -impl Key67 { - #[inline(always)] - pub const fn val(&self) -> u32 { - let val = (self.0 >> 0usize) & 0x00ff_ffff; - val as u32 - } - #[inline(always)] - pub fn set_val(&mut self, val: u32) { - self.0 = (self.0 & !(0x00ff_ffff << 0usize)) | (((val as u32) & 0x00ff_ffff) << 0usize); - } -} -impl Default for Key67 { - #[inline(always)] - fn default() -> Key67 { - Key67(0) - } -} -#[repr(transparent)] -#[derive(Copy, Clone, Eq, PartialEq)] -pub struct LposcCalib(pub u32); -impl LposcCalib { - #[inline(always)] - pub const fn val(&self) -> u32 { - let val = (self.0 >> 0usize) & 0x00ff_ffff; - val as u32 - } - #[inline(always)] - pub fn set_val(&mut self, val: u32) { - self.0 = (self.0 & !(0x00ff_ffff << 0usize)) | (((val as u32) & 0x00ff_ffff) << 0usize); - } -} -impl Default for LposcCalib { - #[inline(always)] - fn default() -> LposcCalib { - LposcCalib(0) - } -} -#[repr(transparent)] -#[derive(Copy, Clone, Eq, PartialEq)] -pub struct NumGpios(pub u32); -impl NumGpios { - #[inline(always)] - pub const fn val(&self) -> u32 { - let val = (self.0 >> 0usize) & 0x00ff_ffff; - val as u32 - } - #[inline(always)] - pub fn set_val(&mut self, val: u32) { - self.0 = (self.0 & !(0x00ff_ffff << 0usize)) | (((val as u32) & 0x00ff_ffff) << 0usize); - } -} -impl Default for NumGpios { - #[inline(always)] - fn default() -> NumGpios { - NumGpios(0) - } -} -#[repr(transparent)] -#[derive(Copy, Clone, Eq, PartialEq)] -pub struct OtpbootDst0(pub u32); -impl OtpbootDst0 { - #[inline(always)] - pub const fn val(&self) -> u32 { - let val = (self.0 >> 0usize) & 0x00ff_ffff; - val as u32 - } - #[inline(always)] - pub fn set_val(&mut self, val: u32) { - self.0 = (self.0 & !(0x00ff_ffff << 0usize)) | (((val as u32) & 0x00ff_ffff) << 0usize); - } -} -impl Default for OtpbootDst0 { - #[inline(always)] - fn default() -> OtpbootDst0 { - OtpbootDst0(0) - } -} -#[repr(transparent)] -#[derive(Copy, Clone, Eq, PartialEq)] -pub struct OtpbootDst1(pub u32); -impl OtpbootDst1 { - #[inline(always)] - pub const fn val(&self) -> u32 { - let val = (self.0 >> 0usize) & 0x00ff_ffff; - val as u32 - } - #[inline(always)] - pub fn set_val(&mut self, val: u32) { - self.0 = (self.0 & !(0x00ff_ffff << 0usize)) | (((val as u32) & 0x00ff_ffff) << 0usize); - } -} -impl Default for OtpbootDst1 { - #[inline(always)] - fn default() -> OtpbootDst1 { - OtpbootDst1(0) - } -} -#[repr(transparent)] -#[derive(Copy, Clone, Eq, PartialEq)] -pub struct OtpbootLen(pub u32); -impl OtpbootLen { - #[inline(always)] - pub const fn val(&self) -> u32 { - let val = (self.0 >> 0usize) & 0x00ff_ffff; - val as u32 - } - #[inline(always)] - pub fn set_val(&mut self, val: u32) { - self.0 = (self.0 & !(0x00ff_ffff << 0usize)) | (((val as u32) & 0x00ff_ffff) << 0usize); - } -} -impl Default for OtpbootLen { - #[inline(always)] - fn default() -> OtpbootLen { - OtpbootLen(0) - } -} -#[repr(transparent)] -#[derive(Copy, Clone, Eq, PartialEq)] -pub struct OtpbootSrc(pub u32); -impl OtpbootSrc { - #[inline(always)] - pub const fn val(&self) -> u32 { - let val = (self.0 >> 0usize) & 0x00ff_ffff; - val as u32 - } - #[inline(always)] - pub fn set_val(&mut self, val: u32) { - self.0 = (self.0 & !(0x00ff_ffff << 0usize)) | (((val as u32) & 0x00ff_ffff) << 0usize); - } -} -impl Default for OtpbootSrc { - #[inline(always)] - fn default() -> OtpbootSrc { - OtpbootSrc(0) - } -} -#[repr(transparent)] -#[derive(Copy, Clone, Eq, PartialEq)] -pub struct Randid0(pub u32); -impl Randid0 { - #[inline(always)] - pub const fn val(&self) -> u32 { - let val = (self.0 >> 0usize) & 0x00ff_ffff; - val as u32 - } - #[inline(always)] - pub fn set_val(&mut self, val: u32) { - self.0 = (self.0 & !(0x00ff_ffff << 0usize)) | (((val as u32) & 0x00ff_ffff) << 0usize); - } -} -impl Default for Randid0 { - #[inline(always)] - fn default() -> Randid0 { - Randid0(0) - } -} -#[repr(transparent)] -#[derive(Copy, Clone, Eq, PartialEq)] -pub struct Randid1(pub u32); -impl Randid1 { - #[inline(always)] - pub const fn val(&self) -> u32 { - let val = (self.0 >> 0usize) & 0x00ff_ffff; - val as u32 - } - #[inline(always)] - pub fn set_val(&mut self, val: u32) { - self.0 = (self.0 & !(0x00ff_ffff << 0usize)) | (((val as u32) & 0x00ff_ffff) << 0usize); - } -} -impl Default for Randid1 { - #[inline(always)] - fn default() -> Randid1 { - Randid1(0) - } -} -#[repr(transparent)] -#[derive(Copy, Clone, Eq, PartialEq)] -pub struct Randid2(pub u32); -impl Randid2 { - #[inline(always)] - pub const fn val(&self) -> u32 { - let val = (self.0 >> 0usize) & 0x00ff_ffff; - val as u32 - } - #[inline(always)] - pub fn set_val(&mut self, val: u32) { - self.0 = (self.0 & !(0x00ff_ffff << 0usize)) | (((val as u32) & 0x00ff_ffff) << 0usize); - } -} -impl Default for Randid2 { - #[inline(always)] - fn default() -> Randid2 { - Randid2(0) - } -} -#[repr(transparent)] -#[derive(Copy, Clone, Eq, PartialEq)] -pub struct Randid3(pub u32); -impl Randid3 { - #[inline(always)] - pub const fn val(&self) -> u32 { - let val = (self.0 >> 0usize) & 0x00ff_ffff; - val as u32 - } - #[inline(always)] - pub fn set_val(&mut self, val: u32) { - self.0 = (self.0 & !(0x00ff_ffff << 0usize)) | (((val as u32) & 0x00ff_ffff) << 0usize); - } -} -impl Default for Randid3 { - #[inline(always)] - fn default() -> Randid3 { - Randid3(0) - } -} -#[repr(transparent)] -#[derive(Copy, Clone, Eq, PartialEq)] -pub struct Randid4(pub u32); -impl Randid4 { - #[inline(always)] - pub const fn val(&self) -> u32 { - let val = (self.0 >> 0usize) & 0x00ff_ffff; - val as u32 - } - #[inline(always)] - pub fn set_val(&mut self, val: u32) { - self.0 = (self.0 & !(0x00ff_ffff << 0usize)) | (((val as u32) & 0x00ff_ffff) << 0usize); - } -} -impl Default for Randid4 { - #[inline(always)] - fn default() -> Randid4 { - Randid4(0) - } -} -#[repr(transparent)] -#[derive(Copy, Clone, Eq, PartialEq)] -pub struct Randid5(pub u32); -impl Randid5 { - #[inline(always)] - pub const fn val(&self) -> u32 { - let val = (self.0 >> 0usize) & 0x00ff_ffff; - val as u32 - } - #[inline(always)] - pub fn set_val(&mut self, val: u32) { - self.0 = (self.0 & !(0x00ff_ffff << 0usize)) | (((val as u32) & 0x00ff_ffff) << 0usize); - } -} -impl Default for Randid5 { - #[inline(always)] - fn default() -> Randid5 { - Randid5(0) - } -} -#[repr(transparent)] -#[derive(Copy, Clone, Eq, PartialEq)] -pub struct Randid6(pub u32); -impl Randid6 { - #[inline(always)] - pub const fn val(&self) -> u32 { - let val = (self.0 >> 0usize) & 0x00ff_ffff; - val as u32 - } - #[inline(always)] - pub fn set_val(&mut self, val: u32) { - self.0 = (self.0 & !(0x00ff_ffff << 0usize)) | (((val as u32) & 0x00ff_ffff) << 0usize); - } -} -impl Default for Randid6 { - #[inline(always)] - fn default() -> Randid6 { - Randid6(0) - } -} -#[repr(transparent)] -#[derive(Copy, Clone, Eq, PartialEq)] -pub struct Randid7(pub u32); -impl Randid7 { - #[inline(always)] - pub const fn val(&self) -> u32 { - let val = (self.0 >> 0usize) & 0x00ff_ffff; - val as u32 - } - #[inline(always)] - pub fn set_val(&mut self, val: u32) { - self.0 = (self.0 & !(0x00ff_ffff << 0usize)) | (((val as u32) & 0x00ff_ffff) << 0usize); - } -} -impl Default for Randid7 { - #[inline(always)] - fn default() -> Randid7 { - Randid7(0) - } -} -#[repr(transparent)] -#[derive(Copy, Clone, Eq, PartialEq)] -pub struct RoscCalib(pub u32); -impl RoscCalib { - #[inline(always)] - pub const fn val(&self) -> u32 { - let val = (self.0 >> 0usize) & 0x00ff_ffff; - val as u32 - } - #[inline(always)] - pub fn set_val(&mut self, val: u32) { - self.0 = (self.0 & !(0x00ff_ffff << 0usize)) | (((val as u32) & 0x00ff_ffff) << 0usize); - } -} -impl Default for RoscCalib { - #[inline(always)] - fn default() -> RoscCalib { - RoscCalib(0) - } -} -#[repr(transparent)] -#[derive(Copy, Clone, Eq, PartialEq)] -pub struct UsbBootFlagsR1(pub u32); -impl UsbBootFlagsR1 { - #[inline(always)] - pub const fn val(&self) -> u32 { - let val = (self.0 >> 0usize) & 0x00ff_ffff; - val as u32 - } - #[inline(always)] - pub fn set_val(&mut self, val: u32) { - self.0 = (self.0 & !(0x00ff_ffff << 0usize)) | (((val as u32) & 0x00ff_ffff) << 0usize); - } -} -impl Default for UsbBootFlagsR1 { - #[inline(always)] - fn default() -> UsbBootFlagsR1 { - UsbBootFlagsR1(0) - } -} -#[repr(transparent)] -#[derive(Copy, Clone, Eq, PartialEq)] -pub struct UsbBootFlagsR2(pub u32); -impl UsbBootFlagsR2 { - #[inline(always)] - pub const fn val(&self) -> u32 { - let val = (self.0 >> 0usize) & 0x00ff_ffff; - val as u32 - } - #[inline(always)] - pub fn set_val(&mut self, val: u32) { - self.0 = (self.0 & !(0x00ff_ffff << 0usize)) | (((val as u32) & 0x00ff_ffff) << 0usize); - } -} -impl Default for UsbBootFlagsR2 { - #[inline(always)] - fn default() -> UsbBootFlagsR2 { - UsbBootFlagsR2(0) - } -} pub mod accessctrl; pub mod adc; pub mod bootram; diff --git a/src/rp235x/otp.rs b/src/rp235x/otp.rs index d82ec108..b2fcf953 100644 --- a/src/rp235x/otp.rs +++ b/src/rp235x/otp.rs @@ -16,464 +16,108 @@ impl Otp { } #[doc = "Software lock register for page 0. Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page."] #[inline(always)] - pub const fn sw_lock0(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(0usize) as _) } - } - #[doc = "Software lock register for page 1. Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page."] - #[inline(always)] - pub const fn sw_lock1(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(4usize) as _) } - } - #[doc = "Software lock register for page 2. Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page."] - #[inline(always)] - pub const fn sw_lock2(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(8usize) as _) } - } - #[doc = "Software lock register for page 3. Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page."] - #[inline(always)] - pub const fn sw_lock3(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(12usize) as _) } - } - #[doc = "Software lock register for page 4. Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page."] - #[inline(always)] - pub const fn sw_lock4(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(16usize) as _) } - } - #[doc = "Software lock register for page 5. Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page."] - #[inline(always)] - pub const fn sw_lock5(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(20usize) as _) } - } - #[doc = "Software lock register for page 6. Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page."] - #[inline(always)] - pub const fn sw_lock6(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(24usize) as _) } - } - #[doc = "Software lock register for page 7. Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page."] - #[inline(always)] - pub const fn sw_lock7(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(28usize) as _) } - } - #[doc = "Software lock register for page 8. Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page."] - #[inline(always)] - pub const fn sw_lock8(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(32usize) as _) } - } - #[doc = "Software lock register for page 9. Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page."] - #[inline(always)] - pub const fn sw_lock9(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(36usize) as _) } - } - #[doc = "Software lock register for page 10. Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page."] - #[inline(always)] - pub const fn sw_lock10(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(40usize) as _) } - } - #[doc = "Software lock register for page 11. Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page."] - #[inline(always)] - pub const fn sw_lock11(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(44usize) as _) } - } - #[doc = "Software lock register for page 12. Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page."] - #[inline(always)] - pub const fn sw_lock12(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(48usize) as _) } - } - #[doc = "Software lock register for page 13. Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page."] - #[inline(always)] - pub const fn sw_lock13(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(52usize) as _) } - } - #[doc = "Software lock register for page 14. Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page."] - #[inline(always)] - pub const fn sw_lock14(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(56usize) as _) } - } - #[doc = "Software lock register for page 15. Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page."] - #[inline(always)] - pub const fn sw_lock15(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(60usize) as _) } - } - #[doc = "Software lock register for page 16. Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page."] - #[inline(always)] - pub const fn sw_lock16(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(64usize) as _) } - } - #[doc = "Software lock register for page 17. Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page."] - #[inline(always)] - pub const fn sw_lock17(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(68usize) as _) } - } - #[doc = "Software lock register for page 18. Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page."] - #[inline(always)] - pub const fn sw_lock18(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(72usize) as _) } - } - #[doc = "Software lock register for page 19. Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page."] - #[inline(always)] - pub const fn sw_lock19(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(76usize) as _) } - } - #[doc = "Software lock register for page 20. Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page."] - #[inline(always)] - pub const fn sw_lock20(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(80usize) as _) } - } - #[doc = "Software lock register for page 21. Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page."] - #[inline(always)] - pub const fn sw_lock21(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(84usize) as _) } - } - #[doc = "Software lock register for page 22. Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page."] - #[inline(always)] - pub const fn sw_lock22(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(88usize) as _) } - } - #[doc = "Software lock register for page 23. Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page."] - #[inline(always)] - pub const fn sw_lock23(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(92usize) as _) } - } - #[doc = "Software lock register for page 24. Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page."] - #[inline(always)] - pub const fn sw_lock24(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(96usize) as _) } - } - #[doc = "Software lock register for page 25. Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page."] - #[inline(always)] - pub const fn sw_lock25(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(100usize) as _) } - } - #[doc = "Software lock register for page 26. Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page."] - #[inline(always)] - pub const fn sw_lock26(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(104usize) as _) } - } - #[doc = "Software lock register for page 27. Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page."] - #[inline(always)] - pub const fn sw_lock27(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(108usize) as _) } - } - #[doc = "Software lock register for page 28. Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page."] - #[inline(always)] - pub const fn sw_lock28(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(112usize) as _) } - } - #[doc = "Software lock register for page 29. Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page."] - #[inline(always)] - pub const fn sw_lock29(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(116usize) as _) } - } - #[doc = "Software lock register for page 30. Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page."] - #[inline(always)] - pub const fn sw_lock30(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(120usize) as _) } - } - #[doc = "Software lock register for page 31. Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page."] - #[inline(always)] - pub const fn sw_lock31(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(124usize) as _) } - } - #[doc = "Software lock register for page 32. Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page."] - #[inline(always)] - pub const fn sw_lock32(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(128usize) as _) } - } - #[doc = "Software lock register for page 33. Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page."] - #[inline(always)] - pub const fn sw_lock33(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(132usize) as _) } - } - #[doc = "Software lock register for page 34. Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page."] - #[inline(always)] - pub const fn sw_lock34(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(136usize) as _) } - } - #[doc = "Software lock register for page 35. Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page."] - #[inline(always)] - pub const fn sw_lock35(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(140usize) as _) } - } - #[doc = "Software lock register for page 36. Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page."] - #[inline(always)] - pub const fn sw_lock36(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(144usize) as _) } - } - #[doc = "Software lock register for page 37. Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page."] - #[inline(always)] - pub const fn sw_lock37(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(148usize) as _) } - } - #[doc = "Software lock register for page 38. Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page."] - #[inline(always)] - pub const fn sw_lock38(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(152usize) as _) } - } - #[doc = "Software lock register for page 39. Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page."] - #[inline(always)] - pub const fn sw_lock39(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(156usize) as _) } - } - #[doc = "Software lock register for page 40. Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page."] - #[inline(always)] - pub const fn sw_lock40(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(160usize) as _) } - } - #[doc = "Software lock register for page 41. Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page."] - #[inline(always)] - pub const fn sw_lock41(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(164usize) as _) } - } - #[doc = "Software lock register for page 42. Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page."] - #[inline(always)] - pub const fn sw_lock42(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(168usize) as _) } - } - #[doc = "Software lock register for page 43. Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page."] - #[inline(always)] - pub const fn sw_lock43(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(172usize) as _) } - } - #[doc = "Software lock register for page 44. Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page."] - #[inline(always)] - pub const fn sw_lock44(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(176usize) as _) } - } - #[doc = "Software lock register for page 45. Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page."] - #[inline(always)] - pub const fn sw_lock45(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(180usize) as _) } - } - #[doc = "Software lock register for page 46. Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page."] - #[inline(always)] - pub const fn sw_lock46(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(184usize) as _) } - } - #[doc = "Software lock register for page 47. Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page."] - #[inline(always)] - pub const fn sw_lock47(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(188usize) as _) } - } - #[doc = "Software lock register for page 48. Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page."] - #[inline(always)] - pub const fn sw_lock48(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(192usize) as _) } - } - #[doc = "Software lock register for page 49. Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page."] - #[inline(always)] - pub const fn sw_lock49(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(196usize) as _) } - } - #[doc = "Software lock register for page 50. Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page."] - #[inline(always)] - pub const fn sw_lock50(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(200usize) as _) } - } - #[doc = "Software lock register for page 51. Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page."] - #[inline(always)] - pub const fn sw_lock51(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(204usize) as _) } - } - #[doc = "Software lock register for page 52. Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page."] - #[inline(always)] - pub const fn sw_lock52(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(208usize) as _) } - } - #[doc = "Software lock register for page 53. Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page."] - #[inline(always)] - pub const fn sw_lock53(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(212usize) as _) } - } - #[doc = "Software lock register for page 54. Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page."] - #[inline(always)] - pub const fn sw_lock54(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(216usize) as _) } - } - #[doc = "Software lock register for page 55. Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page."] - #[inline(always)] - pub const fn sw_lock55(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(220usize) as _) } - } - #[doc = "Software lock register for page 56. Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page."] - #[inline(always)] - pub const fn sw_lock56(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(224usize) as _) } - } - #[doc = "Software lock register for page 57. Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page."] - #[inline(always)] - pub const fn sw_lock57(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(228usize) as _) } - } - #[doc = "Software lock register for page 58. Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page."] - #[inline(always)] - pub const fn sw_lock58(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(232usize) as _) } - } - #[doc = "Software lock register for page 59. Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page."] - #[inline(always)] - pub const fn sw_lock59(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(236usize) as _) } - } - #[doc = "Software lock register for page 60. Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page."] - #[inline(always)] - pub const fn sw_lock60(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(240usize) as _) } - } - #[doc = "Software lock register for page 61. Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page."] - #[inline(always)] - pub const fn sw_lock61(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(244usize) as _) } - } - #[doc = "Software lock register for page 62. Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page."] - #[inline(always)] - pub const fn sw_lock62(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(248usize) as _) } - } - #[doc = "Software lock register for page 63. Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page."] - #[inline(always)] - pub const fn sw_lock63(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(252usize) as _) } + pub const fn sw_lock(self, n: usize) -> crate::common::Reg { + assert!(n < 64usize); + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x0usize + n * 4usize) as _) } } #[doc = "Dispatch instructions to the SBPI interface, used for programming the OTP fuses."] #[inline(always)] pub const fn sbpi_instr(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(256usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x0100usize) as _) } } #[doc = "SBPI write payload bytes 3..0"] #[inline(always)] - pub const fn sbpi_wdata_0(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(260usize) as _) } - } - #[doc = "SBPI write payload bytes 7..4"] - #[inline(always)] - pub const fn sbpi_wdata_1(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(264usize) as _) } - } - #[doc = "SBPI write payload bytes 11..8"] - #[inline(always)] - pub const fn sbpi_wdata_2(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(268usize) as _) } - } - #[doc = "SBPI write payload bytes 15..12"] - #[inline(always)] - pub const fn sbpi_wdata_3(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(272usize) as _) } + pub const fn sbpi_wdata(self, n: usize) -> crate::common::Reg { + assert!(n < 4usize); + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x0104usize + n * 4usize) as _) } } #[doc = "Read payload bytes 3..0. Once read, the data in the register will automatically clear to 0."] #[inline(always)] - pub const fn sbpi_rdata_0(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(276usize) as _) } - } - #[doc = "Read payload bytes 7..4. Once read, the data in the register will automatically clear to 0."] - #[inline(always)] - pub const fn sbpi_rdata_1(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(280usize) as _) } - } - #[doc = "Read payload bytes 11..8. Once read, the data in the register will automatically clear to 0."] - #[inline(always)] - pub const fn sbpi_rdata_2(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(284usize) as _) } - } - #[doc = "Read payload bytes 15..12. Once read, the data in the register will automatically clear to 0."] - #[inline(always)] - pub const fn sbpi_rdata_3(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(288usize) as _) } + pub const fn sbpi_rdata(self, n: usize) -> crate::common::Reg { + assert!(n < 4usize); + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x0114usize + n * 4usize) as _) } } #[inline(always)] pub const fn sbpi_status(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(292usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x0124usize) as _) } } #[doc = "Controls for APB data read interface (USER interface)"] #[inline(always)] pub const fn usr(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(296usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x0128usize) as _) } } #[doc = "Debug for OTP power-on state machine"] #[inline(always)] pub const fn dbg(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(300usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x012cusize) as _) } } #[doc = "During BIST, count address locations that have at least one leaky bit"] #[inline(always)] pub const fn bist(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(308usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x0134usize) as _) } } #[doc = "Word 0 (bits 31..0) of the key. Write only, read returns 0x0"] #[inline(always)] - pub const fn crt_key_w0(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(312usize) as _) } - } - #[doc = "Word 1 (bits 63..32) of the key. Write only, read returns 0x0"] - #[inline(always)] - pub const fn crt_key_w1(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(316usize) as _) } - } - #[doc = "Word 2 (bits 95..64) of the key. Write only, read returns 0x0"] - #[inline(always)] - pub const fn crt_key_w2(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(320usize) as _) } - } - #[doc = "Word 3 (bits 127..96) of the key. Write only, read returns 0x0"] - #[inline(always)] - pub const fn crt_key_w3(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(324usize) as _) } + pub const fn crt_key(self, n: usize) -> crate::common::Reg { + assert!(n < 4usize); + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x0138usize + n * 4usize) as _) } } #[doc = "Quickly check values of critical flags read during boot up"] #[inline(always)] pub const fn critical(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(328usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x0148usize) as _) } } #[doc = "Which keys were valid (enrolled) at boot time"] #[inline(always)] pub const fn key_valid(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(332usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x014cusize) as _) } } #[doc = "Enable a debug feature that has been disabled. Debug features are disabled if one of the relevant critical boot flags is set in OTP (DEBUG_DISABLE or SECURE_DEBUG_DISABLE), OR if a debug key is marked valid in OTP, and the matching key value has not been supplied over SWD. Specifically: - The DEBUG_DISABLE flag disables all debug features. This can be fully overridden by setting all bits of this register. - The SECURE_DEBUG_DISABLE flag disables secure processor debug. This can be fully overridden by setting the PROC0_SECURE and PROC1_SECURE bits of this register. - If a single debug key has been registered, and no matching key value has been supplied over SWD, then all debug features are disabled. This can be fully overridden by setting all bits of this register. - If both debug keys have been registered, and the Non-secure key's value (key 6) has been supplied over SWD, secure processor debug is disabled. This can be fully overridden by setting the PROC0_SECURE and PROC1_SECURE bits of this register. - If both debug keys have been registered, and the Secure key's value (key 5) has been supplied over SWD, then no debug features are disabled by the key mechanism. However, note that in this case debug features may still be disabled by the critical boot flags."] #[inline(always)] pub const fn debugen(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(336usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x0150usize) as _) } } #[doc = "Write 1s to lock corresponding bits in DEBUGEN. This register is reset by the processor cold reset."] #[inline(always)] pub const fn debugen_lock(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(340usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x0154usize) as _) } } #[doc = "Architecture select (Arm/RISC-V). The default and allowable values of this register are constrained by the critical boot flags. This register is reset by the earliest reset in the switched core power domain (before a processor cold reset). Cores sample their architecture select signal on a warm reset. The source of the warm reset could be the system power-up state machine, the watchdog timer, Arm SYSRESETREQ or from RISC-V hartresetreq. Note that when an Arm core is deselected, its cold reset domain is also held in reset, since in particular the SYSRESETREQ bit becomes inaccessible once the core is deselected. Note also the RISC-V cores do not have a cold reset domain, since their corresponding controls are located in the Debug Module."] #[inline(always)] pub const fn archsel(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(344usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x0158usize) as _) } } #[doc = "Get the current architecture select state of each core. Cores sample the current value of the ARCHSEL register when their warm reset is released, at which point the corresponding bit in this register will also update."] #[inline(always)] pub const fn archsel_status( self, ) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(348usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x015cusize) as _) } } #[doc = "Tell the bootrom to ignore scratch register boot vectors (both power manager and watchdog) on the next power up. If an early boot stage has soft-locked some OTP pages in order to protect their contents from later stages, there is a risk that Secure code running at a later stage can unlock the pages by performing a watchdog reset that resets the OTP. This register can be used to ensure that the bootloader runs as normal on the next power up, preventing Secure code at a later stage from accessing OTP in its unlocked state. Should be used in conjunction with the power manager BOOTDIS register."] #[inline(always)] pub const fn bootdis(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(352usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x0160usize) as _) } } #[doc = "Raw Interrupts"] #[inline(always)] - pub const fn intr(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(356usize) as _) } + pub const fn intr(self) -> crate::common::Reg { + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x0164usize) as _) } } #[doc = "Interrupt Enable"] #[inline(always)] - pub const fn inte(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(360usize) as _) } + pub const fn inte(self) -> crate::common::Reg { + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x0168usize) as _) } } #[doc = "Interrupt Force"] #[inline(always)] - pub const fn intf(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(364usize) as _) } + pub const fn intf(self) -> crate::common::Reg { + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x016cusize) as _) } } #[doc = "Interrupt status after masking & forcing"] #[inline(always)] - pub const fn ints(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(368usize) as _) } + pub const fn ints(self) -> crate::common::Reg { + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x0170usize) as _) } } } pub mod regs; diff --git a/src/rp235x/otp/regs.rs b/src/rp235x/otp/regs.rs index 321411cb..9c46134b 100644 --- a/src/rp235x/otp/regs.rs +++ b/src/rp235x/otp/regs.rs @@ -466,8 +466,8 @@ impl Default for DebugenLock { #[doc = "Interrupt Enable"] #[repr(transparent)] #[derive(Copy, Clone, Eq, PartialEq)] -pub struct Inte(pub u32); -impl Inte { +pub struct Int(pub u32); +impl Int { #[inline(always)] pub const fn sbpi_flag_n(&self) -> bool { let val = (self.0 >> 0usize) & 0x01; @@ -514,181 +514,10 @@ impl Inte { self.0 = (self.0 & !(0x01 << 4usize)) | (((val as u32) & 0x01) << 4usize); } } -impl Default for Inte { +impl Default for Int { #[inline(always)] - fn default() -> Inte { - Inte(0) - } -} -#[doc = "Interrupt Force"] -#[repr(transparent)] -#[derive(Copy, Clone, Eq, PartialEq)] -pub struct Intf(pub u32); -impl Intf { - #[inline(always)] - pub const fn sbpi_flag_n(&self) -> bool { - let val = (self.0 >> 0usize) & 0x01; - val != 0 - } - #[inline(always)] - pub fn set_sbpi_flag_n(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize); - } - #[inline(always)] - pub const fn sbpi_wr_fail(&self) -> bool { - let val = (self.0 >> 1usize) & 0x01; - val != 0 - } - #[inline(always)] - pub fn set_sbpi_wr_fail(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize); - } - #[inline(always)] - pub const fn apb_dctrl_fail(&self) -> bool { - let val = (self.0 >> 2usize) & 0x01; - val != 0 - } - #[inline(always)] - pub fn set_apb_dctrl_fail(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 2usize)) | (((val as u32) & 0x01) << 2usize); - } - #[inline(always)] - pub const fn apb_rd_sec_fail(&self) -> bool { - let val = (self.0 >> 3usize) & 0x01; - val != 0 - } - #[inline(always)] - pub fn set_apb_rd_sec_fail(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 3usize)) | (((val as u32) & 0x01) << 3usize); - } - #[inline(always)] - pub const fn apb_rd_nsec_fail(&self) -> bool { - let val = (self.0 >> 4usize) & 0x01; - val != 0 - } - #[inline(always)] - pub fn set_apb_rd_nsec_fail(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 4usize)) | (((val as u32) & 0x01) << 4usize); - } -} -impl Default for Intf { - #[inline(always)] - fn default() -> Intf { - Intf(0) - } -} -#[doc = "Raw Interrupts"] -#[repr(transparent)] -#[derive(Copy, Clone, Eq, PartialEq)] -pub struct Intr(pub u32); -impl Intr { - #[inline(always)] - pub const fn sbpi_flag_n(&self) -> bool { - let val = (self.0 >> 0usize) & 0x01; - val != 0 - } - #[inline(always)] - pub fn set_sbpi_flag_n(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize); - } - #[inline(always)] - pub const fn sbpi_wr_fail(&self) -> bool { - let val = (self.0 >> 1usize) & 0x01; - val != 0 - } - #[inline(always)] - pub fn set_sbpi_wr_fail(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize); - } - #[inline(always)] - pub const fn apb_dctrl_fail(&self) -> bool { - let val = (self.0 >> 2usize) & 0x01; - val != 0 - } - #[inline(always)] - pub fn set_apb_dctrl_fail(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 2usize)) | (((val as u32) & 0x01) << 2usize); - } - #[inline(always)] - pub const fn apb_rd_sec_fail(&self) -> bool { - let val = (self.0 >> 3usize) & 0x01; - val != 0 - } - #[inline(always)] - pub fn set_apb_rd_sec_fail(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 3usize)) | (((val as u32) & 0x01) << 3usize); - } - #[inline(always)] - pub const fn apb_rd_nsec_fail(&self) -> bool { - let val = (self.0 >> 4usize) & 0x01; - val != 0 - } - #[inline(always)] - pub fn set_apb_rd_nsec_fail(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 4usize)) | (((val as u32) & 0x01) << 4usize); - } -} -impl Default for Intr { - #[inline(always)] - fn default() -> Intr { - Intr(0) - } -} -#[doc = "Interrupt status after masking & forcing"] -#[repr(transparent)] -#[derive(Copy, Clone, Eq, PartialEq)] -pub struct Ints(pub u32); -impl Ints { - #[inline(always)] - pub const fn sbpi_flag_n(&self) -> bool { - let val = (self.0 >> 0usize) & 0x01; - val != 0 - } - #[inline(always)] - pub fn set_sbpi_flag_n(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize); - } - #[inline(always)] - pub const fn sbpi_wr_fail(&self) -> bool { - let val = (self.0 >> 1usize) & 0x01; - val != 0 - } - #[inline(always)] - pub fn set_sbpi_wr_fail(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize); - } - #[inline(always)] - pub const fn apb_dctrl_fail(&self) -> bool { - let val = (self.0 >> 2usize) & 0x01; - val != 0 - } - #[inline(always)] - pub fn set_apb_dctrl_fail(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 2usize)) | (((val as u32) & 0x01) << 2usize); - } - #[inline(always)] - pub const fn apb_rd_sec_fail(&self) -> bool { - let val = (self.0 >> 3usize) & 0x01; - val != 0 - } - #[inline(always)] - pub fn set_apb_rd_sec_fail(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 3usize)) | (((val as u32) & 0x01) << 3usize); - } - #[inline(always)] - pub const fn apb_rd_nsec_fail(&self) -> bool { - let val = (self.0 >> 4usize) & 0x01; - val != 0 - } - #[inline(always)] - pub fn set_apb_rd_nsec_fail(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 4usize)) | (((val as u32) & 0x01) << 4usize); - } -} -impl Default for Ints { - #[inline(always)] - fn default() -> Ints { - Ints(0) + fn default() -> Int { + Int(0) } } #[doc = "Which keys were valid (enrolled) at boot time"] @@ -865,2180 +694,38 @@ impl Default for SbpiStatus { SbpiStatus(0) } } -#[doc = "Software lock register for page 0. Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page."] -#[repr(transparent)] -#[derive(Copy, Clone, Eq, PartialEq)] -pub struct SwLock0(pub u32); -impl SwLock0 { - #[doc = "Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code."] - #[inline(always)] - pub const fn sec(&self) -> super::vals::SwLock0sec { - let val = (self.0 >> 0usize) & 0x03; - super::vals::SwLock0sec::from_bits(val as u8) - } - #[doc = "Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code."] - #[inline(always)] - pub fn set_sec(&mut self, val: super::vals::SwLock0sec) { - self.0 = (self.0 & !(0x03 << 0usize)) | (((val.to_bits() as u32) & 0x03) << 0usize); - } - #[doc = "Non-secure lock status. Writes are OR'd with the current value."] - #[inline(always)] - pub const fn nsec(&self) -> super::vals::SwLock0nsec { - let val = (self.0 >> 2usize) & 0x03; - super::vals::SwLock0nsec::from_bits(val as u8) - } - #[doc = "Non-secure lock status. Writes are OR'd with the current value."] - #[inline(always)] - pub fn set_nsec(&mut self, val: super::vals::SwLock0nsec) { - self.0 = (self.0 & !(0x03 << 2usize)) | (((val.to_bits() as u32) & 0x03) << 2usize); - } -} -impl Default for SwLock0 { - #[inline(always)] - fn default() -> SwLock0 { - SwLock0(0) - } -} -#[doc = "Software lock register for page 1. Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page."] -#[repr(transparent)] -#[derive(Copy, Clone, Eq, PartialEq)] -pub struct SwLock1(pub u32); -impl SwLock1 { - #[doc = "Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code."] - #[inline(always)] - pub const fn sec(&self) -> super::vals::SwLock1sec { - let val = (self.0 >> 0usize) & 0x03; - super::vals::SwLock1sec::from_bits(val as u8) - } - #[doc = "Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code."] - #[inline(always)] - pub fn set_sec(&mut self, val: super::vals::SwLock1sec) { - self.0 = (self.0 & !(0x03 << 0usize)) | (((val.to_bits() as u32) & 0x03) << 0usize); - } - #[doc = "Non-secure lock status. Writes are OR'd with the current value."] - #[inline(always)] - pub const fn nsec(&self) -> super::vals::SwLock1nsec { - let val = (self.0 >> 2usize) & 0x03; - super::vals::SwLock1nsec::from_bits(val as u8) - } - #[doc = "Non-secure lock status. Writes are OR'd with the current value."] - #[inline(always)] - pub fn set_nsec(&mut self, val: super::vals::SwLock1nsec) { - self.0 = (self.0 & !(0x03 << 2usize)) | (((val.to_bits() as u32) & 0x03) << 2usize); - } -} -impl Default for SwLock1 { - #[inline(always)] - fn default() -> SwLock1 { - SwLock1(0) - } -} -#[doc = "Software lock register for page 10. Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page."] -#[repr(transparent)] -#[derive(Copy, Clone, Eq, PartialEq)] -pub struct SwLock10(pub u32); -impl SwLock10 { - #[doc = "Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code."] - #[inline(always)] - pub const fn sec(&self) -> super::vals::SwLock10sec { - let val = (self.0 >> 0usize) & 0x03; - super::vals::SwLock10sec::from_bits(val as u8) - } - #[doc = "Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code."] - #[inline(always)] - pub fn set_sec(&mut self, val: super::vals::SwLock10sec) { - self.0 = (self.0 & !(0x03 << 0usize)) | (((val.to_bits() as u32) & 0x03) << 0usize); - } - #[doc = "Non-secure lock status. Writes are OR'd with the current value."] - #[inline(always)] - pub const fn nsec(&self) -> super::vals::SwLock10nsec { - let val = (self.0 >> 2usize) & 0x03; - super::vals::SwLock10nsec::from_bits(val as u8) - } - #[doc = "Non-secure lock status. Writes are OR'd with the current value."] - #[inline(always)] - pub fn set_nsec(&mut self, val: super::vals::SwLock10nsec) { - self.0 = (self.0 & !(0x03 << 2usize)) | (((val.to_bits() as u32) & 0x03) << 2usize); - } -} -impl Default for SwLock10 { - #[inline(always)] - fn default() -> SwLock10 { - SwLock10(0) - } -} -#[doc = "Software lock register for page 11. Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page."] -#[repr(transparent)] -#[derive(Copy, Clone, Eq, PartialEq)] -pub struct SwLock11(pub u32); -impl SwLock11 { - #[doc = "Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code."] - #[inline(always)] - pub const fn sec(&self) -> super::vals::SwLock11sec { - let val = (self.0 >> 0usize) & 0x03; - super::vals::SwLock11sec::from_bits(val as u8) - } - #[doc = "Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code."] - #[inline(always)] - pub fn set_sec(&mut self, val: super::vals::SwLock11sec) { - self.0 = (self.0 & !(0x03 << 0usize)) | (((val.to_bits() as u32) & 0x03) << 0usize); - } - #[doc = "Non-secure lock status. Writes are OR'd with the current value."] - #[inline(always)] - pub const fn nsec(&self) -> super::vals::SwLock11nsec { - let val = (self.0 >> 2usize) & 0x03; - super::vals::SwLock11nsec::from_bits(val as u8) - } - #[doc = "Non-secure lock status. Writes are OR'd with the current value."] - #[inline(always)] - pub fn set_nsec(&mut self, val: super::vals::SwLock11nsec) { - self.0 = (self.0 & !(0x03 << 2usize)) | (((val.to_bits() as u32) & 0x03) << 2usize); - } -} -impl Default for SwLock11 { - #[inline(always)] - fn default() -> SwLock11 { - SwLock11(0) - } -} -#[doc = "Software lock register for page 12. Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page."] -#[repr(transparent)] -#[derive(Copy, Clone, Eq, PartialEq)] -pub struct SwLock12(pub u32); -impl SwLock12 { - #[doc = "Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code."] - #[inline(always)] - pub const fn sec(&self) -> super::vals::SwLock12sec { - let val = (self.0 >> 0usize) & 0x03; - super::vals::SwLock12sec::from_bits(val as u8) - } - #[doc = "Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code."] - #[inline(always)] - pub fn set_sec(&mut self, val: super::vals::SwLock12sec) { - self.0 = (self.0 & !(0x03 << 0usize)) | (((val.to_bits() as u32) & 0x03) << 0usize); - } - #[doc = "Non-secure lock status. Writes are OR'd with the current value."] - #[inline(always)] - pub const fn nsec(&self) -> super::vals::SwLock12nsec { - let val = (self.0 >> 2usize) & 0x03; - super::vals::SwLock12nsec::from_bits(val as u8) - } - #[doc = "Non-secure lock status. Writes are OR'd with the current value."] - #[inline(always)] - pub fn set_nsec(&mut self, val: super::vals::SwLock12nsec) { - self.0 = (self.0 & !(0x03 << 2usize)) | (((val.to_bits() as u32) & 0x03) << 2usize); - } -} -impl Default for SwLock12 { - #[inline(always)] - fn default() -> SwLock12 { - SwLock12(0) - } -} -#[doc = "Software lock register for page 13. Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page."] -#[repr(transparent)] -#[derive(Copy, Clone, Eq, PartialEq)] -pub struct SwLock13(pub u32); -impl SwLock13 { - #[doc = "Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code."] - #[inline(always)] - pub const fn sec(&self) -> super::vals::SwLock13sec { - let val = (self.0 >> 0usize) & 0x03; - super::vals::SwLock13sec::from_bits(val as u8) - } - #[doc = "Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code."] - #[inline(always)] - pub fn set_sec(&mut self, val: super::vals::SwLock13sec) { - self.0 = (self.0 & !(0x03 << 0usize)) | (((val.to_bits() as u32) & 0x03) << 0usize); - } - #[doc = "Non-secure lock status. Writes are OR'd with the current value."] - #[inline(always)] - pub const fn nsec(&self) -> super::vals::SwLock13nsec { - let val = (self.0 >> 2usize) & 0x03; - super::vals::SwLock13nsec::from_bits(val as u8) - } - #[doc = "Non-secure lock status. Writes are OR'd with the current value."] - #[inline(always)] - pub fn set_nsec(&mut self, val: super::vals::SwLock13nsec) { - self.0 = (self.0 & !(0x03 << 2usize)) | (((val.to_bits() as u32) & 0x03) << 2usize); - } -} -impl Default for SwLock13 { - #[inline(always)] - fn default() -> SwLock13 { - SwLock13(0) - } -} -#[doc = "Software lock register for page 14. Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page."] -#[repr(transparent)] -#[derive(Copy, Clone, Eq, PartialEq)] -pub struct SwLock14(pub u32); -impl SwLock14 { - #[doc = "Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code."] - #[inline(always)] - pub const fn sec(&self) -> super::vals::SwLock14sec { - let val = (self.0 >> 0usize) & 0x03; - super::vals::SwLock14sec::from_bits(val as u8) - } - #[doc = "Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code."] - #[inline(always)] - pub fn set_sec(&mut self, val: super::vals::SwLock14sec) { - self.0 = (self.0 & !(0x03 << 0usize)) | (((val.to_bits() as u32) & 0x03) << 0usize); - } - #[doc = "Non-secure lock status. Writes are OR'd with the current value."] - #[inline(always)] - pub const fn nsec(&self) -> super::vals::SwLock14nsec { - let val = (self.0 >> 2usize) & 0x03; - super::vals::SwLock14nsec::from_bits(val as u8) - } - #[doc = "Non-secure lock status. Writes are OR'd with the current value."] - #[inline(always)] - pub fn set_nsec(&mut self, val: super::vals::SwLock14nsec) { - self.0 = (self.0 & !(0x03 << 2usize)) | (((val.to_bits() as u32) & 0x03) << 2usize); - } -} -impl Default for SwLock14 { - #[inline(always)] - fn default() -> SwLock14 { - SwLock14(0) - } -} -#[doc = "Software lock register for page 15. Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page."] -#[repr(transparent)] -#[derive(Copy, Clone, Eq, PartialEq)] -pub struct SwLock15(pub u32); -impl SwLock15 { - #[doc = "Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code."] - #[inline(always)] - pub const fn sec(&self) -> super::vals::SwLock15sec { - let val = (self.0 >> 0usize) & 0x03; - super::vals::SwLock15sec::from_bits(val as u8) - } - #[doc = "Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code."] - #[inline(always)] - pub fn set_sec(&mut self, val: super::vals::SwLock15sec) { - self.0 = (self.0 & !(0x03 << 0usize)) | (((val.to_bits() as u32) & 0x03) << 0usize); - } - #[doc = "Non-secure lock status. Writes are OR'd with the current value."] - #[inline(always)] - pub const fn nsec(&self) -> super::vals::SwLock15nsec { - let val = (self.0 >> 2usize) & 0x03; - super::vals::SwLock15nsec::from_bits(val as u8) - } - #[doc = "Non-secure lock status. Writes are OR'd with the current value."] - #[inline(always)] - pub fn set_nsec(&mut self, val: super::vals::SwLock15nsec) { - self.0 = (self.0 & !(0x03 << 2usize)) | (((val.to_bits() as u32) & 0x03) << 2usize); - } -} -impl Default for SwLock15 { - #[inline(always)] - fn default() -> SwLock15 { - SwLock15(0) - } -} -#[doc = "Software lock register for page 16. Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page."] -#[repr(transparent)] -#[derive(Copy, Clone, Eq, PartialEq)] -pub struct SwLock16(pub u32); -impl SwLock16 { - #[doc = "Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code."] - #[inline(always)] - pub const fn sec(&self) -> super::vals::SwLock16sec { - let val = (self.0 >> 0usize) & 0x03; - super::vals::SwLock16sec::from_bits(val as u8) - } - #[doc = "Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code."] - #[inline(always)] - pub fn set_sec(&mut self, val: super::vals::SwLock16sec) { - self.0 = (self.0 & !(0x03 << 0usize)) | (((val.to_bits() as u32) & 0x03) << 0usize); - } - #[doc = "Non-secure lock status. Writes are OR'd with the current value."] - #[inline(always)] - pub const fn nsec(&self) -> super::vals::SwLock16nsec { - let val = (self.0 >> 2usize) & 0x03; - super::vals::SwLock16nsec::from_bits(val as u8) - } - #[doc = "Non-secure lock status. Writes are OR'd with the current value."] - #[inline(always)] - pub fn set_nsec(&mut self, val: super::vals::SwLock16nsec) { - self.0 = (self.0 & !(0x03 << 2usize)) | (((val.to_bits() as u32) & 0x03) << 2usize); - } -} -impl Default for SwLock16 { - #[inline(always)] - fn default() -> SwLock16 { - SwLock16(0) - } -} -#[doc = "Software lock register for page 17. Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page."] -#[repr(transparent)] -#[derive(Copy, Clone, Eq, PartialEq)] -pub struct SwLock17(pub u32); -impl SwLock17 { - #[doc = "Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code."] - #[inline(always)] - pub const fn sec(&self) -> super::vals::SwLock17sec { - let val = (self.0 >> 0usize) & 0x03; - super::vals::SwLock17sec::from_bits(val as u8) - } - #[doc = "Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code."] - #[inline(always)] - pub fn set_sec(&mut self, val: super::vals::SwLock17sec) { - self.0 = (self.0 & !(0x03 << 0usize)) | (((val.to_bits() as u32) & 0x03) << 0usize); - } - #[doc = "Non-secure lock status. Writes are OR'd with the current value."] - #[inline(always)] - pub const fn nsec(&self) -> super::vals::SwLock17nsec { - let val = (self.0 >> 2usize) & 0x03; - super::vals::SwLock17nsec::from_bits(val as u8) - } - #[doc = "Non-secure lock status. Writes are OR'd with the current value."] - #[inline(always)] - pub fn set_nsec(&mut self, val: super::vals::SwLock17nsec) { - self.0 = (self.0 & !(0x03 << 2usize)) | (((val.to_bits() as u32) & 0x03) << 2usize); - } -} -impl Default for SwLock17 { - #[inline(always)] - fn default() -> SwLock17 { - SwLock17(0) - } -} -#[doc = "Software lock register for page 18. Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page."] -#[repr(transparent)] -#[derive(Copy, Clone, Eq, PartialEq)] -pub struct SwLock18(pub u32); -impl SwLock18 { - #[doc = "Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code."] - #[inline(always)] - pub const fn sec(&self) -> super::vals::SwLock18sec { - let val = (self.0 >> 0usize) & 0x03; - super::vals::SwLock18sec::from_bits(val as u8) - } - #[doc = "Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code."] - #[inline(always)] - pub fn set_sec(&mut self, val: super::vals::SwLock18sec) { - self.0 = (self.0 & !(0x03 << 0usize)) | (((val.to_bits() as u32) & 0x03) << 0usize); - } - #[doc = "Non-secure lock status. Writes are OR'd with the current value."] - #[inline(always)] - pub const fn nsec(&self) -> super::vals::SwLock18nsec { - let val = (self.0 >> 2usize) & 0x03; - super::vals::SwLock18nsec::from_bits(val as u8) - } - #[doc = "Non-secure lock status. Writes are OR'd with the current value."] - #[inline(always)] - pub fn set_nsec(&mut self, val: super::vals::SwLock18nsec) { - self.0 = (self.0 & !(0x03 << 2usize)) | (((val.to_bits() as u32) & 0x03) << 2usize); - } -} -impl Default for SwLock18 { - #[inline(always)] - fn default() -> SwLock18 { - SwLock18(0) - } -} -#[doc = "Software lock register for page 19. Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page."] -#[repr(transparent)] -#[derive(Copy, Clone, Eq, PartialEq)] -pub struct SwLock19(pub u32); -impl SwLock19 { - #[doc = "Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code."] - #[inline(always)] - pub const fn sec(&self) -> super::vals::SwLock19sec { - let val = (self.0 >> 0usize) & 0x03; - super::vals::SwLock19sec::from_bits(val as u8) - } - #[doc = "Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code."] - #[inline(always)] - pub fn set_sec(&mut self, val: super::vals::SwLock19sec) { - self.0 = (self.0 & !(0x03 << 0usize)) | (((val.to_bits() as u32) & 0x03) << 0usize); - } - #[doc = "Non-secure lock status. Writes are OR'd with the current value."] - #[inline(always)] - pub const fn nsec(&self) -> super::vals::SwLock19nsec { - let val = (self.0 >> 2usize) & 0x03; - super::vals::SwLock19nsec::from_bits(val as u8) - } - #[doc = "Non-secure lock status. Writes are OR'd with the current value."] - #[inline(always)] - pub fn set_nsec(&mut self, val: super::vals::SwLock19nsec) { - self.0 = (self.0 & !(0x03 << 2usize)) | (((val.to_bits() as u32) & 0x03) << 2usize); - } -} -impl Default for SwLock19 { - #[inline(always)] - fn default() -> SwLock19 { - SwLock19(0) - } -} #[doc = "Software lock register for page 2. Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page."] #[repr(transparent)] #[derive(Copy, Clone, Eq, PartialEq)] -pub struct SwLock2(pub u32); -impl SwLock2 { - #[doc = "Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code."] - #[inline(always)] - pub const fn sec(&self) -> super::vals::SwLock2sec { - let val = (self.0 >> 0usize) & 0x03; - super::vals::SwLock2sec::from_bits(val as u8) - } - #[doc = "Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code."] - #[inline(always)] - pub fn set_sec(&mut self, val: super::vals::SwLock2sec) { - self.0 = (self.0 & !(0x03 << 0usize)) | (((val.to_bits() as u32) & 0x03) << 0usize); - } - #[doc = "Non-secure lock status. Writes are OR'd with the current value."] - #[inline(always)] - pub const fn nsec(&self) -> super::vals::SwLock2nsec { - let val = (self.0 >> 2usize) & 0x03; - super::vals::SwLock2nsec::from_bits(val as u8) - } - #[doc = "Non-secure lock status. Writes are OR'd with the current value."] - #[inline(always)] - pub fn set_nsec(&mut self, val: super::vals::SwLock2nsec) { - self.0 = (self.0 & !(0x03 << 2usize)) | (((val.to_bits() as u32) & 0x03) << 2usize); - } -} -impl Default for SwLock2 { - #[inline(always)] - fn default() -> SwLock2 { - SwLock2(0) - } -} -#[doc = "Software lock register for page 20. Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page."] -#[repr(transparent)] -#[derive(Copy, Clone, Eq, PartialEq)] -pub struct SwLock20(pub u32); -impl SwLock20 { - #[doc = "Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code."] - #[inline(always)] - pub const fn sec(&self) -> super::vals::SwLock20sec { - let val = (self.0 >> 0usize) & 0x03; - super::vals::SwLock20sec::from_bits(val as u8) - } - #[doc = "Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code."] - #[inline(always)] - pub fn set_sec(&mut self, val: super::vals::SwLock20sec) { - self.0 = (self.0 & !(0x03 << 0usize)) | (((val.to_bits() as u32) & 0x03) << 0usize); - } - #[doc = "Non-secure lock status. Writes are OR'd with the current value."] - #[inline(always)] - pub const fn nsec(&self) -> super::vals::SwLock20nsec { - let val = (self.0 >> 2usize) & 0x03; - super::vals::SwLock20nsec::from_bits(val as u8) - } - #[doc = "Non-secure lock status. Writes are OR'd with the current value."] - #[inline(always)] - pub fn set_nsec(&mut self, val: super::vals::SwLock20nsec) { - self.0 = (self.0 & !(0x03 << 2usize)) | (((val.to_bits() as u32) & 0x03) << 2usize); - } -} -impl Default for SwLock20 { - #[inline(always)] - fn default() -> SwLock20 { - SwLock20(0) - } -} -#[doc = "Software lock register for page 21. Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page."] -#[repr(transparent)] -#[derive(Copy, Clone, Eq, PartialEq)] -pub struct SwLock21(pub u32); -impl SwLock21 { - #[doc = "Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code."] - #[inline(always)] - pub const fn sec(&self) -> super::vals::SwLock21sec { - let val = (self.0 >> 0usize) & 0x03; - super::vals::SwLock21sec::from_bits(val as u8) - } - #[doc = "Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code."] - #[inline(always)] - pub fn set_sec(&mut self, val: super::vals::SwLock21sec) { - self.0 = (self.0 & !(0x03 << 0usize)) | (((val.to_bits() as u32) & 0x03) << 0usize); - } - #[doc = "Non-secure lock status. Writes are OR'd with the current value."] - #[inline(always)] - pub const fn nsec(&self) -> super::vals::SwLock21nsec { - let val = (self.0 >> 2usize) & 0x03; - super::vals::SwLock21nsec::from_bits(val as u8) - } - #[doc = "Non-secure lock status. Writes are OR'd with the current value."] - #[inline(always)] - pub fn set_nsec(&mut self, val: super::vals::SwLock21nsec) { - self.0 = (self.0 & !(0x03 << 2usize)) | (((val.to_bits() as u32) & 0x03) << 2usize); - } -} -impl Default for SwLock21 { - #[inline(always)] - fn default() -> SwLock21 { - SwLock21(0) - } -} -#[doc = "Software lock register for page 22. Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page."] -#[repr(transparent)] -#[derive(Copy, Clone, Eq, PartialEq)] -pub struct SwLock22(pub u32); -impl SwLock22 { - #[doc = "Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code."] - #[inline(always)] - pub const fn sec(&self) -> super::vals::SwLock22sec { - let val = (self.0 >> 0usize) & 0x03; - super::vals::SwLock22sec::from_bits(val as u8) - } - #[doc = "Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code."] - #[inline(always)] - pub fn set_sec(&mut self, val: super::vals::SwLock22sec) { - self.0 = (self.0 & !(0x03 << 0usize)) | (((val.to_bits() as u32) & 0x03) << 0usize); - } - #[doc = "Non-secure lock status. Writes are OR'd with the current value."] - #[inline(always)] - pub const fn nsec(&self) -> super::vals::SwLock22nsec { - let val = (self.0 >> 2usize) & 0x03; - super::vals::SwLock22nsec::from_bits(val as u8) - } - #[doc = "Non-secure lock status. Writes are OR'd with the current value."] - #[inline(always)] - pub fn set_nsec(&mut self, val: super::vals::SwLock22nsec) { - self.0 = (self.0 & !(0x03 << 2usize)) | (((val.to_bits() as u32) & 0x03) << 2usize); - } -} -impl Default for SwLock22 { - #[inline(always)] - fn default() -> SwLock22 { - SwLock22(0) - } -} -#[doc = "Software lock register for page 23. Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page."] -#[repr(transparent)] -#[derive(Copy, Clone, Eq, PartialEq)] -pub struct SwLock23(pub u32); -impl SwLock23 { - #[doc = "Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code."] - #[inline(always)] - pub const fn sec(&self) -> super::vals::SwLock23sec { - let val = (self.0 >> 0usize) & 0x03; - super::vals::SwLock23sec::from_bits(val as u8) - } - #[doc = "Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code."] - #[inline(always)] - pub fn set_sec(&mut self, val: super::vals::SwLock23sec) { - self.0 = (self.0 & !(0x03 << 0usize)) | (((val.to_bits() as u32) & 0x03) << 0usize); - } - #[doc = "Non-secure lock status. Writes are OR'd with the current value."] - #[inline(always)] - pub const fn nsec(&self) -> super::vals::SwLock23nsec { - let val = (self.0 >> 2usize) & 0x03; - super::vals::SwLock23nsec::from_bits(val as u8) - } - #[doc = "Non-secure lock status. Writes are OR'd with the current value."] - #[inline(always)] - pub fn set_nsec(&mut self, val: super::vals::SwLock23nsec) { - self.0 = (self.0 & !(0x03 << 2usize)) | (((val.to_bits() as u32) & 0x03) << 2usize); - } -} -impl Default for SwLock23 { - #[inline(always)] - fn default() -> SwLock23 { - SwLock23(0) - } -} -#[doc = "Software lock register for page 24. Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page."] -#[repr(transparent)] -#[derive(Copy, Clone, Eq, PartialEq)] -pub struct SwLock24(pub u32); -impl SwLock24 { - #[doc = "Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code."] - #[inline(always)] - pub const fn sec(&self) -> super::vals::SwLock24sec { - let val = (self.0 >> 0usize) & 0x03; - super::vals::SwLock24sec::from_bits(val as u8) - } - #[doc = "Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code."] - #[inline(always)] - pub fn set_sec(&mut self, val: super::vals::SwLock24sec) { - self.0 = (self.0 & !(0x03 << 0usize)) | (((val.to_bits() as u32) & 0x03) << 0usize); - } - #[doc = "Non-secure lock status. Writes are OR'd with the current value."] - #[inline(always)] - pub const fn nsec(&self) -> super::vals::SwLock24nsec { - let val = (self.0 >> 2usize) & 0x03; - super::vals::SwLock24nsec::from_bits(val as u8) - } - #[doc = "Non-secure lock status. Writes are OR'd with the current value."] - #[inline(always)] - pub fn set_nsec(&mut self, val: super::vals::SwLock24nsec) { - self.0 = (self.0 & !(0x03 << 2usize)) | (((val.to_bits() as u32) & 0x03) << 2usize); - } -} -impl Default for SwLock24 { - #[inline(always)] - fn default() -> SwLock24 { - SwLock24(0) - } -} -#[doc = "Software lock register for page 25. Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page."] -#[repr(transparent)] -#[derive(Copy, Clone, Eq, PartialEq)] -pub struct SwLock25(pub u32); -impl SwLock25 { - #[doc = "Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code."] - #[inline(always)] - pub const fn sec(&self) -> super::vals::SwLock25sec { - let val = (self.0 >> 0usize) & 0x03; - super::vals::SwLock25sec::from_bits(val as u8) - } - #[doc = "Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code."] - #[inline(always)] - pub fn set_sec(&mut self, val: super::vals::SwLock25sec) { - self.0 = (self.0 & !(0x03 << 0usize)) | (((val.to_bits() as u32) & 0x03) << 0usize); - } - #[doc = "Non-secure lock status. Writes are OR'd with the current value."] - #[inline(always)] - pub const fn nsec(&self) -> super::vals::SwLock25nsec { - let val = (self.0 >> 2usize) & 0x03; - super::vals::SwLock25nsec::from_bits(val as u8) - } - #[doc = "Non-secure lock status. Writes are OR'd with the current value."] - #[inline(always)] - pub fn set_nsec(&mut self, val: super::vals::SwLock25nsec) { - self.0 = (self.0 & !(0x03 << 2usize)) | (((val.to_bits() as u32) & 0x03) << 2usize); - } -} -impl Default for SwLock25 { - #[inline(always)] - fn default() -> SwLock25 { - SwLock25(0) - } -} -#[doc = "Software lock register for page 26. Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page."] -#[repr(transparent)] -#[derive(Copy, Clone, Eq, PartialEq)] -pub struct SwLock26(pub u32); -impl SwLock26 { - #[doc = "Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code."] - #[inline(always)] - pub const fn sec(&self) -> super::vals::SwLock26sec { - let val = (self.0 >> 0usize) & 0x03; - super::vals::SwLock26sec::from_bits(val as u8) - } - #[doc = "Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code."] - #[inline(always)] - pub fn set_sec(&mut self, val: super::vals::SwLock26sec) { - self.0 = (self.0 & !(0x03 << 0usize)) | (((val.to_bits() as u32) & 0x03) << 0usize); - } - #[doc = "Non-secure lock status. Writes are OR'd with the current value."] - #[inline(always)] - pub const fn nsec(&self) -> super::vals::SwLock26nsec { - let val = (self.0 >> 2usize) & 0x03; - super::vals::SwLock26nsec::from_bits(val as u8) - } - #[doc = "Non-secure lock status. Writes are OR'd with the current value."] - #[inline(always)] - pub fn set_nsec(&mut self, val: super::vals::SwLock26nsec) { - self.0 = (self.0 & !(0x03 << 2usize)) | (((val.to_bits() as u32) & 0x03) << 2usize); - } -} -impl Default for SwLock26 { - #[inline(always)] - fn default() -> SwLock26 { - SwLock26(0) - } -} -#[doc = "Software lock register for page 27. Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page."] -#[repr(transparent)] -#[derive(Copy, Clone, Eq, PartialEq)] -pub struct SwLock27(pub u32); -impl SwLock27 { - #[doc = "Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code."] - #[inline(always)] - pub const fn sec(&self) -> super::vals::SwLock27sec { - let val = (self.0 >> 0usize) & 0x03; - super::vals::SwLock27sec::from_bits(val as u8) - } - #[doc = "Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code."] - #[inline(always)] - pub fn set_sec(&mut self, val: super::vals::SwLock27sec) { - self.0 = (self.0 & !(0x03 << 0usize)) | (((val.to_bits() as u32) & 0x03) << 0usize); - } - #[doc = "Non-secure lock status. Writes are OR'd with the current value."] - #[inline(always)] - pub const fn nsec(&self) -> super::vals::SwLock27nsec { - let val = (self.0 >> 2usize) & 0x03; - super::vals::SwLock27nsec::from_bits(val as u8) - } - #[doc = "Non-secure lock status. Writes are OR'd with the current value."] - #[inline(always)] - pub fn set_nsec(&mut self, val: super::vals::SwLock27nsec) { - self.0 = (self.0 & !(0x03 << 2usize)) | (((val.to_bits() as u32) & 0x03) << 2usize); - } -} -impl Default for SwLock27 { - #[inline(always)] - fn default() -> SwLock27 { - SwLock27(0) - } -} -#[doc = "Software lock register for page 28. Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page."] -#[repr(transparent)] -#[derive(Copy, Clone, Eq, PartialEq)] -pub struct SwLock28(pub u32); -impl SwLock28 { - #[doc = "Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code."] - #[inline(always)] - pub const fn sec(&self) -> super::vals::SwLock28sec { - let val = (self.0 >> 0usize) & 0x03; - super::vals::SwLock28sec::from_bits(val as u8) - } - #[doc = "Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code."] - #[inline(always)] - pub fn set_sec(&mut self, val: super::vals::SwLock28sec) { - self.0 = (self.0 & !(0x03 << 0usize)) | (((val.to_bits() as u32) & 0x03) << 0usize); - } - #[doc = "Non-secure lock status. Writes are OR'd with the current value."] - #[inline(always)] - pub const fn nsec(&self) -> super::vals::SwLock28nsec { - let val = (self.0 >> 2usize) & 0x03; - super::vals::SwLock28nsec::from_bits(val as u8) - } - #[doc = "Non-secure lock status. Writes are OR'd with the current value."] - #[inline(always)] - pub fn set_nsec(&mut self, val: super::vals::SwLock28nsec) { - self.0 = (self.0 & !(0x03 << 2usize)) | (((val.to_bits() as u32) & 0x03) << 2usize); - } -} -impl Default for SwLock28 { - #[inline(always)] - fn default() -> SwLock28 { - SwLock28(0) - } -} -#[doc = "Software lock register for page 29. Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page."] -#[repr(transparent)] -#[derive(Copy, Clone, Eq, PartialEq)] -pub struct SwLock29(pub u32); -impl SwLock29 { - #[doc = "Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code."] - #[inline(always)] - pub const fn sec(&self) -> super::vals::SwLock29sec { - let val = (self.0 >> 0usize) & 0x03; - super::vals::SwLock29sec::from_bits(val as u8) - } - #[doc = "Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code."] - #[inline(always)] - pub fn set_sec(&mut self, val: super::vals::SwLock29sec) { - self.0 = (self.0 & !(0x03 << 0usize)) | (((val.to_bits() as u32) & 0x03) << 0usize); - } - #[doc = "Non-secure lock status. Writes are OR'd with the current value."] - #[inline(always)] - pub const fn nsec(&self) -> super::vals::SwLock29nsec { - let val = (self.0 >> 2usize) & 0x03; - super::vals::SwLock29nsec::from_bits(val as u8) - } - #[doc = "Non-secure lock status. Writes are OR'd with the current value."] - #[inline(always)] - pub fn set_nsec(&mut self, val: super::vals::SwLock29nsec) { - self.0 = (self.0 & !(0x03 << 2usize)) | (((val.to_bits() as u32) & 0x03) << 2usize); - } -} -impl Default for SwLock29 { - #[inline(always)] - fn default() -> SwLock29 { - SwLock29(0) - } -} -#[doc = "Software lock register for page 3. Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page."] -#[repr(transparent)] -#[derive(Copy, Clone, Eq, PartialEq)] -pub struct SwLock3(pub u32); -impl SwLock3 { - #[doc = "Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code."] - #[inline(always)] - pub const fn sec(&self) -> super::vals::SwLock3sec { - let val = (self.0 >> 0usize) & 0x03; - super::vals::SwLock3sec::from_bits(val as u8) - } - #[doc = "Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code."] - #[inline(always)] - pub fn set_sec(&mut self, val: super::vals::SwLock3sec) { - self.0 = (self.0 & !(0x03 << 0usize)) | (((val.to_bits() as u32) & 0x03) << 0usize); - } - #[doc = "Non-secure lock status. Writes are OR'd with the current value."] - #[inline(always)] - pub const fn nsec(&self) -> super::vals::SwLock3nsec { - let val = (self.0 >> 2usize) & 0x03; - super::vals::SwLock3nsec::from_bits(val as u8) - } - #[doc = "Non-secure lock status. Writes are OR'd with the current value."] - #[inline(always)] - pub fn set_nsec(&mut self, val: super::vals::SwLock3nsec) { - self.0 = (self.0 & !(0x03 << 2usize)) | (((val.to_bits() as u32) & 0x03) << 2usize); - } -} -impl Default for SwLock3 { - #[inline(always)] - fn default() -> SwLock3 { - SwLock3(0) - } -} -#[doc = "Software lock register for page 30. Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page."] -#[repr(transparent)] -#[derive(Copy, Clone, Eq, PartialEq)] -pub struct SwLock30(pub u32); -impl SwLock30 { - #[doc = "Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code."] - #[inline(always)] - pub const fn sec(&self) -> super::vals::SwLock30sec { - let val = (self.0 >> 0usize) & 0x03; - super::vals::SwLock30sec::from_bits(val as u8) - } - #[doc = "Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code."] - #[inline(always)] - pub fn set_sec(&mut self, val: super::vals::SwLock30sec) { - self.0 = (self.0 & !(0x03 << 0usize)) | (((val.to_bits() as u32) & 0x03) << 0usize); - } - #[doc = "Non-secure lock status. Writes are OR'd with the current value."] - #[inline(always)] - pub const fn nsec(&self) -> super::vals::SwLock30nsec { - let val = (self.0 >> 2usize) & 0x03; - super::vals::SwLock30nsec::from_bits(val as u8) - } - #[doc = "Non-secure lock status. Writes are OR'd with the current value."] - #[inline(always)] - pub fn set_nsec(&mut self, val: super::vals::SwLock30nsec) { - self.0 = (self.0 & !(0x03 << 2usize)) | (((val.to_bits() as u32) & 0x03) << 2usize); - } -} -impl Default for SwLock30 { - #[inline(always)] - fn default() -> SwLock30 { - SwLock30(0) - } -} -#[doc = "Software lock register for page 31. Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page."] -#[repr(transparent)] -#[derive(Copy, Clone, Eq, PartialEq)] -pub struct SwLock31(pub u32); -impl SwLock31 { - #[doc = "Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code."] - #[inline(always)] - pub const fn sec(&self) -> super::vals::SwLock31sec { - let val = (self.0 >> 0usize) & 0x03; - super::vals::SwLock31sec::from_bits(val as u8) - } - #[doc = "Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code."] - #[inline(always)] - pub fn set_sec(&mut self, val: super::vals::SwLock31sec) { - self.0 = (self.0 & !(0x03 << 0usize)) | (((val.to_bits() as u32) & 0x03) << 0usize); - } - #[doc = "Non-secure lock status. Writes are OR'd with the current value."] - #[inline(always)] - pub const fn nsec(&self) -> super::vals::SwLock31nsec { - let val = (self.0 >> 2usize) & 0x03; - super::vals::SwLock31nsec::from_bits(val as u8) - } - #[doc = "Non-secure lock status. Writes are OR'd with the current value."] - #[inline(always)] - pub fn set_nsec(&mut self, val: super::vals::SwLock31nsec) { - self.0 = (self.0 & !(0x03 << 2usize)) | (((val.to_bits() as u32) & 0x03) << 2usize); - } -} -impl Default for SwLock31 { - #[inline(always)] - fn default() -> SwLock31 { - SwLock31(0) - } -} -#[doc = "Software lock register for page 32. Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page."] -#[repr(transparent)] -#[derive(Copy, Clone, Eq, PartialEq)] -pub struct SwLock32(pub u32); -impl SwLock32 { - #[doc = "Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code."] - #[inline(always)] - pub const fn sec(&self) -> super::vals::SwLock32sec { - let val = (self.0 >> 0usize) & 0x03; - super::vals::SwLock32sec::from_bits(val as u8) - } - #[doc = "Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code."] - #[inline(always)] - pub fn set_sec(&mut self, val: super::vals::SwLock32sec) { - self.0 = (self.0 & !(0x03 << 0usize)) | (((val.to_bits() as u32) & 0x03) << 0usize); - } - #[doc = "Non-secure lock status. Writes are OR'd with the current value."] - #[inline(always)] - pub const fn nsec(&self) -> super::vals::SwLock32nsec { - let val = (self.0 >> 2usize) & 0x03; - super::vals::SwLock32nsec::from_bits(val as u8) - } - #[doc = "Non-secure lock status. Writes are OR'd with the current value."] - #[inline(always)] - pub fn set_nsec(&mut self, val: super::vals::SwLock32nsec) { - self.0 = (self.0 & !(0x03 << 2usize)) | (((val.to_bits() as u32) & 0x03) << 2usize); - } -} -impl Default for SwLock32 { - #[inline(always)] - fn default() -> SwLock32 { - SwLock32(0) - } -} -#[doc = "Software lock register for page 33. Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page."] -#[repr(transparent)] -#[derive(Copy, Clone, Eq, PartialEq)] -pub struct SwLock33(pub u32); -impl SwLock33 { - #[doc = "Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code."] - #[inline(always)] - pub const fn sec(&self) -> super::vals::SwLock33sec { - let val = (self.0 >> 0usize) & 0x03; - super::vals::SwLock33sec::from_bits(val as u8) - } - #[doc = "Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code."] - #[inline(always)] - pub fn set_sec(&mut self, val: super::vals::SwLock33sec) { - self.0 = (self.0 & !(0x03 << 0usize)) | (((val.to_bits() as u32) & 0x03) << 0usize); - } - #[doc = "Non-secure lock status. Writes are OR'd with the current value."] - #[inline(always)] - pub const fn nsec(&self) -> super::vals::SwLock33nsec { - let val = (self.0 >> 2usize) & 0x03; - super::vals::SwLock33nsec::from_bits(val as u8) - } - #[doc = "Non-secure lock status. Writes are OR'd with the current value."] - #[inline(always)] - pub fn set_nsec(&mut self, val: super::vals::SwLock33nsec) { - self.0 = (self.0 & !(0x03 << 2usize)) | (((val.to_bits() as u32) & 0x03) << 2usize); - } -} -impl Default for SwLock33 { - #[inline(always)] - fn default() -> SwLock33 { - SwLock33(0) - } -} -#[doc = "Software lock register for page 34. Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page."] -#[repr(transparent)] -#[derive(Copy, Clone, Eq, PartialEq)] -pub struct SwLock34(pub u32); -impl SwLock34 { - #[doc = "Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code."] - #[inline(always)] - pub const fn sec(&self) -> super::vals::SwLock34sec { - let val = (self.0 >> 0usize) & 0x03; - super::vals::SwLock34sec::from_bits(val as u8) - } - #[doc = "Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code."] - #[inline(always)] - pub fn set_sec(&mut self, val: super::vals::SwLock34sec) { - self.0 = (self.0 & !(0x03 << 0usize)) | (((val.to_bits() as u32) & 0x03) << 0usize); - } - #[doc = "Non-secure lock status. Writes are OR'd with the current value."] - #[inline(always)] - pub const fn nsec(&self) -> super::vals::SwLock34nsec { - let val = (self.0 >> 2usize) & 0x03; - super::vals::SwLock34nsec::from_bits(val as u8) - } - #[doc = "Non-secure lock status. Writes are OR'd with the current value."] - #[inline(always)] - pub fn set_nsec(&mut self, val: super::vals::SwLock34nsec) { - self.0 = (self.0 & !(0x03 << 2usize)) | (((val.to_bits() as u32) & 0x03) << 2usize); - } -} -impl Default for SwLock34 { - #[inline(always)] - fn default() -> SwLock34 { - SwLock34(0) - } -} -#[doc = "Software lock register for page 35. Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page."] -#[repr(transparent)] -#[derive(Copy, Clone, Eq, PartialEq)] -pub struct SwLock35(pub u32); -impl SwLock35 { - #[doc = "Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code."] - #[inline(always)] - pub const fn sec(&self) -> super::vals::SwLock35sec { - let val = (self.0 >> 0usize) & 0x03; - super::vals::SwLock35sec::from_bits(val as u8) - } - #[doc = "Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code."] - #[inline(always)] - pub fn set_sec(&mut self, val: super::vals::SwLock35sec) { - self.0 = (self.0 & !(0x03 << 0usize)) | (((val.to_bits() as u32) & 0x03) << 0usize); - } - #[doc = "Non-secure lock status. Writes are OR'd with the current value."] - #[inline(always)] - pub const fn nsec(&self) -> super::vals::SwLock35nsec { - let val = (self.0 >> 2usize) & 0x03; - super::vals::SwLock35nsec::from_bits(val as u8) - } - #[doc = "Non-secure lock status. Writes are OR'd with the current value."] - #[inline(always)] - pub fn set_nsec(&mut self, val: super::vals::SwLock35nsec) { - self.0 = (self.0 & !(0x03 << 2usize)) | (((val.to_bits() as u32) & 0x03) << 2usize); - } -} -impl Default for SwLock35 { - #[inline(always)] - fn default() -> SwLock35 { - SwLock35(0) - } -} -#[doc = "Software lock register for page 36. Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page."] -#[repr(transparent)] -#[derive(Copy, Clone, Eq, PartialEq)] -pub struct SwLock36(pub u32); -impl SwLock36 { - #[doc = "Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code."] - #[inline(always)] - pub const fn sec(&self) -> super::vals::SwLock36sec { - let val = (self.0 >> 0usize) & 0x03; - super::vals::SwLock36sec::from_bits(val as u8) - } - #[doc = "Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code."] - #[inline(always)] - pub fn set_sec(&mut self, val: super::vals::SwLock36sec) { - self.0 = (self.0 & !(0x03 << 0usize)) | (((val.to_bits() as u32) & 0x03) << 0usize); - } - #[doc = "Non-secure lock status. Writes are OR'd with the current value."] - #[inline(always)] - pub const fn nsec(&self) -> super::vals::SwLock36nsec { - let val = (self.0 >> 2usize) & 0x03; - super::vals::SwLock36nsec::from_bits(val as u8) - } - #[doc = "Non-secure lock status. Writes are OR'd with the current value."] - #[inline(always)] - pub fn set_nsec(&mut self, val: super::vals::SwLock36nsec) { - self.0 = (self.0 & !(0x03 << 2usize)) | (((val.to_bits() as u32) & 0x03) << 2usize); - } -} -impl Default for SwLock36 { - #[inline(always)] - fn default() -> SwLock36 { - SwLock36(0) - } -} -#[doc = "Software lock register for page 37. Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page."] -#[repr(transparent)] -#[derive(Copy, Clone, Eq, PartialEq)] -pub struct SwLock37(pub u32); -impl SwLock37 { - #[doc = "Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code."] - #[inline(always)] - pub const fn sec(&self) -> super::vals::SwLock37sec { - let val = (self.0 >> 0usize) & 0x03; - super::vals::SwLock37sec::from_bits(val as u8) - } - #[doc = "Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code."] - #[inline(always)] - pub fn set_sec(&mut self, val: super::vals::SwLock37sec) { - self.0 = (self.0 & !(0x03 << 0usize)) | (((val.to_bits() as u32) & 0x03) << 0usize); - } - #[doc = "Non-secure lock status. Writes are OR'd with the current value."] - #[inline(always)] - pub const fn nsec(&self) -> super::vals::SwLock37nsec { - let val = (self.0 >> 2usize) & 0x03; - super::vals::SwLock37nsec::from_bits(val as u8) - } - #[doc = "Non-secure lock status. Writes are OR'd with the current value."] - #[inline(always)] - pub fn set_nsec(&mut self, val: super::vals::SwLock37nsec) { - self.0 = (self.0 & !(0x03 << 2usize)) | (((val.to_bits() as u32) & 0x03) << 2usize); - } -} -impl Default for SwLock37 { - #[inline(always)] - fn default() -> SwLock37 { - SwLock37(0) - } -} -#[doc = "Software lock register for page 38. Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page."] -#[repr(transparent)] -#[derive(Copy, Clone, Eq, PartialEq)] -pub struct SwLock38(pub u32); -impl SwLock38 { - #[doc = "Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code."] - #[inline(always)] - pub const fn sec(&self) -> super::vals::SwLock38sec { - let val = (self.0 >> 0usize) & 0x03; - super::vals::SwLock38sec::from_bits(val as u8) - } - #[doc = "Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code."] - #[inline(always)] - pub fn set_sec(&mut self, val: super::vals::SwLock38sec) { - self.0 = (self.0 & !(0x03 << 0usize)) | (((val.to_bits() as u32) & 0x03) << 0usize); - } - #[doc = "Non-secure lock status. Writes are OR'd with the current value."] - #[inline(always)] - pub const fn nsec(&self) -> super::vals::SwLock38nsec { - let val = (self.0 >> 2usize) & 0x03; - super::vals::SwLock38nsec::from_bits(val as u8) - } - #[doc = "Non-secure lock status. Writes are OR'd with the current value."] - #[inline(always)] - pub fn set_nsec(&mut self, val: super::vals::SwLock38nsec) { - self.0 = (self.0 & !(0x03 << 2usize)) | (((val.to_bits() as u32) & 0x03) << 2usize); - } -} -impl Default for SwLock38 { - #[inline(always)] - fn default() -> SwLock38 { - SwLock38(0) - } -} -#[doc = "Software lock register for page 39. Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page."] -#[repr(transparent)] -#[derive(Copy, Clone, Eq, PartialEq)] -pub struct SwLock39(pub u32); -impl SwLock39 { - #[doc = "Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code."] - #[inline(always)] - pub const fn sec(&self) -> super::vals::SwLock39sec { - let val = (self.0 >> 0usize) & 0x03; - super::vals::SwLock39sec::from_bits(val as u8) - } - #[doc = "Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code."] - #[inline(always)] - pub fn set_sec(&mut self, val: super::vals::SwLock39sec) { - self.0 = (self.0 & !(0x03 << 0usize)) | (((val.to_bits() as u32) & 0x03) << 0usize); - } - #[doc = "Non-secure lock status. Writes are OR'd with the current value."] - #[inline(always)] - pub const fn nsec(&self) -> super::vals::SwLock39nsec { - let val = (self.0 >> 2usize) & 0x03; - super::vals::SwLock39nsec::from_bits(val as u8) - } - #[doc = "Non-secure lock status. Writes are OR'd with the current value."] - #[inline(always)] - pub fn set_nsec(&mut self, val: super::vals::SwLock39nsec) { - self.0 = (self.0 & !(0x03 << 2usize)) | (((val.to_bits() as u32) & 0x03) << 2usize); - } -} -impl Default for SwLock39 { - #[inline(always)] - fn default() -> SwLock39 { - SwLock39(0) - } -} -#[doc = "Software lock register for page 4. Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page."] -#[repr(transparent)] -#[derive(Copy, Clone, Eq, PartialEq)] -pub struct SwLock4(pub u32); -impl SwLock4 { - #[doc = "Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code."] - #[inline(always)] - pub const fn sec(&self) -> super::vals::SwLock4sec { - let val = (self.0 >> 0usize) & 0x03; - super::vals::SwLock4sec::from_bits(val as u8) - } - #[doc = "Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code."] - #[inline(always)] - pub fn set_sec(&mut self, val: super::vals::SwLock4sec) { - self.0 = (self.0 & !(0x03 << 0usize)) | (((val.to_bits() as u32) & 0x03) << 0usize); - } - #[doc = "Non-secure lock status. Writes are OR'd with the current value."] - #[inline(always)] - pub const fn nsec(&self) -> super::vals::SwLock4nsec { - let val = (self.0 >> 2usize) & 0x03; - super::vals::SwLock4nsec::from_bits(val as u8) - } - #[doc = "Non-secure lock status. Writes are OR'd with the current value."] - #[inline(always)] - pub fn set_nsec(&mut self, val: super::vals::SwLock4nsec) { - self.0 = (self.0 & !(0x03 << 2usize)) | (((val.to_bits() as u32) & 0x03) << 2usize); - } -} -impl Default for SwLock4 { - #[inline(always)] - fn default() -> SwLock4 { - SwLock4(0) - } -} -#[doc = "Software lock register for page 40. Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page."] -#[repr(transparent)] -#[derive(Copy, Clone, Eq, PartialEq)] -pub struct SwLock40(pub u32); -impl SwLock40 { - #[doc = "Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code."] - #[inline(always)] - pub const fn sec(&self) -> super::vals::SwLock40sec { - let val = (self.0 >> 0usize) & 0x03; - super::vals::SwLock40sec::from_bits(val as u8) - } - #[doc = "Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code."] - #[inline(always)] - pub fn set_sec(&mut self, val: super::vals::SwLock40sec) { - self.0 = (self.0 & !(0x03 << 0usize)) | (((val.to_bits() as u32) & 0x03) << 0usize); - } - #[doc = "Non-secure lock status. Writes are OR'd with the current value."] - #[inline(always)] - pub const fn nsec(&self) -> super::vals::SwLock40nsec { - let val = (self.0 >> 2usize) & 0x03; - super::vals::SwLock40nsec::from_bits(val as u8) - } - #[doc = "Non-secure lock status. Writes are OR'd with the current value."] - #[inline(always)] - pub fn set_nsec(&mut self, val: super::vals::SwLock40nsec) { - self.0 = (self.0 & !(0x03 << 2usize)) | (((val.to_bits() as u32) & 0x03) << 2usize); - } -} -impl Default for SwLock40 { - #[inline(always)] - fn default() -> SwLock40 { - SwLock40(0) - } -} -#[doc = "Software lock register for page 41. Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page."] -#[repr(transparent)] -#[derive(Copy, Clone, Eq, PartialEq)] -pub struct SwLock41(pub u32); -impl SwLock41 { - #[doc = "Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code."] - #[inline(always)] - pub const fn sec(&self) -> super::vals::SwLock41sec { - let val = (self.0 >> 0usize) & 0x03; - super::vals::SwLock41sec::from_bits(val as u8) - } - #[doc = "Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code."] - #[inline(always)] - pub fn set_sec(&mut self, val: super::vals::SwLock41sec) { - self.0 = (self.0 & !(0x03 << 0usize)) | (((val.to_bits() as u32) & 0x03) << 0usize); - } - #[doc = "Non-secure lock status. Writes are OR'd with the current value."] - #[inline(always)] - pub const fn nsec(&self) -> super::vals::SwLock41nsec { - let val = (self.0 >> 2usize) & 0x03; - super::vals::SwLock41nsec::from_bits(val as u8) - } - #[doc = "Non-secure lock status. Writes are OR'd with the current value."] - #[inline(always)] - pub fn set_nsec(&mut self, val: super::vals::SwLock41nsec) { - self.0 = (self.0 & !(0x03 << 2usize)) | (((val.to_bits() as u32) & 0x03) << 2usize); - } -} -impl Default for SwLock41 { - #[inline(always)] - fn default() -> SwLock41 { - SwLock41(0) - } -} -#[doc = "Software lock register for page 42. Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page."] -#[repr(transparent)] -#[derive(Copy, Clone, Eq, PartialEq)] -pub struct SwLock42(pub u32); -impl SwLock42 { - #[doc = "Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code."] - #[inline(always)] - pub const fn sec(&self) -> super::vals::SwLock42sec { - let val = (self.0 >> 0usize) & 0x03; - super::vals::SwLock42sec::from_bits(val as u8) - } - #[doc = "Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code."] - #[inline(always)] - pub fn set_sec(&mut self, val: super::vals::SwLock42sec) { - self.0 = (self.0 & !(0x03 << 0usize)) | (((val.to_bits() as u32) & 0x03) << 0usize); - } - #[doc = "Non-secure lock status. Writes are OR'd with the current value."] - #[inline(always)] - pub const fn nsec(&self) -> super::vals::SwLock42nsec { - let val = (self.0 >> 2usize) & 0x03; - super::vals::SwLock42nsec::from_bits(val as u8) - } - #[doc = "Non-secure lock status. Writes are OR'd with the current value."] - #[inline(always)] - pub fn set_nsec(&mut self, val: super::vals::SwLock42nsec) { - self.0 = (self.0 & !(0x03 << 2usize)) | (((val.to_bits() as u32) & 0x03) << 2usize); - } -} -impl Default for SwLock42 { - #[inline(always)] - fn default() -> SwLock42 { - SwLock42(0) - } -} -#[doc = "Software lock register for page 43. Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page."] -#[repr(transparent)] -#[derive(Copy, Clone, Eq, PartialEq)] -pub struct SwLock43(pub u32); -impl SwLock43 { - #[doc = "Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code."] - #[inline(always)] - pub const fn sec(&self) -> super::vals::SwLock43sec { - let val = (self.0 >> 0usize) & 0x03; - super::vals::SwLock43sec::from_bits(val as u8) - } - #[doc = "Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code."] - #[inline(always)] - pub fn set_sec(&mut self, val: super::vals::SwLock43sec) { - self.0 = (self.0 & !(0x03 << 0usize)) | (((val.to_bits() as u32) & 0x03) << 0usize); - } - #[doc = "Non-secure lock status. Writes are OR'd with the current value."] - #[inline(always)] - pub const fn nsec(&self) -> super::vals::SwLock43nsec { - let val = (self.0 >> 2usize) & 0x03; - super::vals::SwLock43nsec::from_bits(val as u8) - } - #[doc = "Non-secure lock status. Writes are OR'd with the current value."] - #[inline(always)] - pub fn set_nsec(&mut self, val: super::vals::SwLock43nsec) { - self.0 = (self.0 & !(0x03 << 2usize)) | (((val.to_bits() as u32) & 0x03) << 2usize); - } -} -impl Default for SwLock43 { - #[inline(always)] - fn default() -> SwLock43 { - SwLock43(0) - } -} -#[doc = "Software lock register for page 44. Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page."] -#[repr(transparent)] -#[derive(Copy, Clone, Eq, PartialEq)] -pub struct SwLock44(pub u32); -impl SwLock44 { - #[doc = "Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code."] - #[inline(always)] - pub const fn sec(&self) -> super::vals::SwLock44sec { - let val = (self.0 >> 0usize) & 0x03; - super::vals::SwLock44sec::from_bits(val as u8) - } - #[doc = "Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code."] - #[inline(always)] - pub fn set_sec(&mut self, val: super::vals::SwLock44sec) { - self.0 = (self.0 & !(0x03 << 0usize)) | (((val.to_bits() as u32) & 0x03) << 0usize); - } - #[doc = "Non-secure lock status. Writes are OR'd with the current value."] - #[inline(always)] - pub const fn nsec(&self) -> super::vals::SwLock44nsec { - let val = (self.0 >> 2usize) & 0x03; - super::vals::SwLock44nsec::from_bits(val as u8) - } - #[doc = "Non-secure lock status. Writes are OR'd with the current value."] - #[inline(always)] - pub fn set_nsec(&mut self, val: super::vals::SwLock44nsec) { - self.0 = (self.0 & !(0x03 << 2usize)) | (((val.to_bits() as u32) & 0x03) << 2usize); - } -} -impl Default for SwLock44 { - #[inline(always)] - fn default() -> SwLock44 { - SwLock44(0) - } -} -#[doc = "Software lock register for page 45. Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page."] -#[repr(transparent)] -#[derive(Copy, Clone, Eq, PartialEq)] -pub struct SwLock45(pub u32); -impl SwLock45 { - #[doc = "Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code."] - #[inline(always)] - pub const fn sec(&self) -> super::vals::SwLock45sec { - let val = (self.0 >> 0usize) & 0x03; - super::vals::SwLock45sec::from_bits(val as u8) - } - #[doc = "Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code."] - #[inline(always)] - pub fn set_sec(&mut self, val: super::vals::SwLock45sec) { - self.0 = (self.0 & !(0x03 << 0usize)) | (((val.to_bits() as u32) & 0x03) << 0usize); - } - #[doc = "Non-secure lock status. Writes are OR'd with the current value."] - #[inline(always)] - pub const fn nsec(&self) -> super::vals::SwLock45nsec { - let val = (self.0 >> 2usize) & 0x03; - super::vals::SwLock45nsec::from_bits(val as u8) - } - #[doc = "Non-secure lock status. Writes are OR'd with the current value."] - #[inline(always)] - pub fn set_nsec(&mut self, val: super::vals::SwLock45nsec) { - self.0 = (self.0 & !(0x03 << 2usize)) | (((val.to_bits() as u32) & 0x03) << 2usize); - } -} -impl Default for SwLock45 { - #[inline(always)] - fn default() -> SwLock45 { - SwLock45(0) - } -} -#[doc = "Software lock register for page 46. Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page."] -#[repr(transparent)] -#[derive(Copy, Clone, Eq, PartialEq)] -pub struct SwLock46(pub u32); -impl SwLock46 { - #[doc = "Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code."] - #[inline(always)] - pub const fn sec(&self) -> super::vals::SwLock46sec { - let val = (self.0 >> 0usize) & 0x03; - super::vals::SwLock46sec::from_bits(val as u8) - } - #[doc = "Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code."] - #[inline(always)] - pub fn set_sec(&mut self, val: super::vals::SwLock46sec) { - self.0 = (self.0 & !(0x03 << 0usize)) | (((val.to_bits() as u32) & 0x03) << 0usize); - } - #[doc = "Non-secure lock status. Writes are OR'd with the current value."] - #[inline(always)] - pub const fn nsec(&self) -> super::vals::SwLock46nsec { - let val = (self.0 >> 2usize) & 0x03; - super::vals::SwLock46nsec::from_bits(val as u8) - } - #[doc = "Non-secure lock status. Writes are OR'd with the current value."] - #[inline(always)] - pub fn set_nsec(&mut self, val: super::vals::SwLock46nsec) { - self.0 = (self.0 & !(0x03 << 2usize)) | (((val.to_bits() as u32) & 0x03) << 2usize); - } -} -impl Default for SwLock46 { - #[inline(always)] - fn default() -> SwLock46 { - SwLock46(0) - } -} -#[doc = "Software lock register for page 47. Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page."] -#[repr(transparent)] -#[derive(Copy, Clone, Eq, PartialEq)] -pub struct SwLock47(pub u32); -impl SwLock47 { - #[doc = "Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code."] - #[inline(always)] - pub const fn sec(&self) -> super::vals::SwLock47sec { - let val = (self.0 >> 0usize) & 0x03; - super::vals::SwLock47sec::from_bits(val as u8) - } - #[doc = "Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code."] - #[inline(always)] - pub fn set_sec(&mut self, val: super::vals::SwLock47sec) { - self.0 = (self.0 & !(0x03 << 0usize)) | (((val.to_bits() as u32) & 0x03) << 0usize); - } - #[doc = "Non-secure lock status. Writes are OR'd with the current value."] - #[inline(always)] - pub const fn nsec(&self) -> super::vals::SwLock47nsec { - let val = (self.0 >> 2usize) & 0x03; - super::vals::SwLock47nsec::from_bits(val as u8) - } - #[doc = "Non-secure lock status. Writes are OR'd with the current value."] - #[inline(always)] - pub fn set_nsec(&mut self, val: super::vals::SwLock47nsec) { - self.0 = (self.0 & !(0x03 << 2usize)) | (((val.to_bits() as u32) & 0x03) << 2usize); - } -} -impl Default for SwLock47 { - #[inline(always)] - fn default() -> SwLock47 { - SwLock47(0) - } -} -#[doc = "Software lock register for page 48. Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page."] -#[repr(transparent)] -#[derive(Copy, Clone, Eq, PartialEq)] -pub struct SwLock48(pub u32); -impl SwLock48 { - #[doc = "Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code."] - #[inline(always)] - pub const fn sec(&self) -> super::vals::SwLock48sec { - let val = (self.0 >> 0usize) & 0x03; - super::vals::SwLock48sec::from_bits(val as u8) - } - #[doc = "Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code."] - #[inline(always)] - pub fn set_sec(&mut self, val: super::vals::SwLock48sec) { - self.0 = (self.0 & !(0x03 << 0usize)) | (((val.to_bits() as u32) & 0x03) << 0usize); - } - #[doc = "Non-secure lock status. Writes are OR'd with the current value."] - #[inline(always)] - pub const fn nsec(&self) -> super::vals::SwLock48nsec { - let val = (self.0 >> 2usize) & 0x03; - super::vals::SwLock48nsec::from_bits(val as u8) - } - #[doc = "Non-secure lock status. Writes are OR'd with the current value."] - #[inline(always)] - pub fn set_nsec(&mut self, val: super::vals::SwLock48nsec) { - self.0 = (self.0 & !(0x03 << 2usize)) | (((val.to_bits() as u32) & 0x03) << 2usize); - } -} -impl Default for SwLock48 { - #[inline(always)] - fn default() -> SwLock48 { - SwLock48(0) - } -} -#[doc = "Software lock register for page 49. Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page."] -#[repr(transparent)] -#[derive(Copy, Clone, Eq, PartialEq)] -pub struct SwLock49(pub u32); -impl SwLock49 { - #[doc = "Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code."] - #[inline(always)] - pub const fn sec(&self) -> super::vals::SwLock49sec { - let val = (self.0 >> 0usize) & 0x03; - super::vals::SwLock49sec::from_bits(val as u8) - } - #[doc = "Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code."] - #[inline(always)] - pub fn set_sec(&mut self, val: super::vals::SwLock49sec) { - self.0 = (self.0 & !(0x03 << 0usize)) | (((val.to_bits() as u32) & 0x03) << 0usize); - } - #[doc = "Non-secure lock status. Writes are OR'd with the current value."] - #[inline(always)] - pub const fn nsec(&self) -> super::vals::SwLock49nsec { - let val = (self.0 >> 2usize) & 0x03; - super::vals::SwLock49nsec::from_bits(val as u8) - } - #[doc = "Non-secure lock status. Writes are OR'd with the current value."] - #[inline(always)] - pub fn set_nsec(&mut self, val: super::vals::SwLock49nsec) { - self.0 = (self.0 & !(0x03 << 2usize)) | (((val.to_bits() as u32) & 0x03) << 2usize); - } -} -impl Default for SwLock49 { - #[inline(always)] - fn default() -> SwLock49 { - SwLock49(0) - } -} -#[doc = "Software lock register for page 5. Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page."] -#[repr(transparent)] -#[derive(Copy, Clone, Eq, PartialEq)] -pub struct SwLock5(pub u32); -impl SwLock5 { - #[doc = "Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code."] - #[inline(always)] - pub const fn sec(&self) -> super::vals::SwLock5sec { - let val = (self.0 >> 0usize) & 0x03; - super::vals::SwLock5sec::from_bits(val as u8) - } - #[doc = "Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code."] - #[inline(always)] - pub fn set_sec(&mut self, val: super::vals::SwLock5sec) { - self.0 = (self.0 & !(0x03 << 0usize)) | (((val.to_bits() as u32) & 0x03) << 0usize); - } - #[doc = "Non-secure lock status. Writes are OR'd with the current value."] - #[inline(always)] - pub const fn nsec(&self) -> super::vals::SwLock5nsec { - let val = (self.0 >> 2usize) & 0x03; - super::vals::SwLock5nsec::from_bits(val as u8) - } - #[doc = "Non-secure lock status. Writes are OR'd with the current value."] - #[inline(always)] - pub fn set_nsec(&mut self, val: super::vals::SwLock5nsec) { - self.0 = (self.0 & !(0x03 << 2usize)) | (((val.to_bits() as u32) & 0x03) << 2usize); - } -} -impl Default for SwLock5 { - #[inline(always)] - fn default() -> SwLock5 { - SwLock5(0) - } -} -#[doc = "Software lock register for page 50. Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page."] -#[repr(transparent)] -#[derive(Copy, Clone, Eq, PartialEq)] -pub struct SwLock50(pub u32); -impl SwLock50 { - #[doc = "Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code."] - #[inline(always)] - pub const fn sec(&self) -> super::vals::SwLock50sec { - let val = (self.0 >> 0usize) & 0x03; - super::vals::SwLock50sec::from_bits(val as u8) - } - #[doc = "Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code."] - #[inline(always)] - pub fn set_sec(&mut self, val: super::vals::SwLock50sec) { - self.0 = (self.0 & !(0x03 << 0usize)) | (((val.to_bits() as u32) & 0x03) << 0usize); - } - #[doc = "Non-secure lock status. Writes are OR'd with the current value."] - #[inline(always)] - pub const fn nsec(&self) -> super::vals::SwLock50nsec { - let val = (self.0 >> 2usize) & 0x03; - super::vals::SwLock50nsec::from_bits(val as u8) - } - #[doc = "Non-secure lock status. Writes are OR'd with the current value."] - #[inline(always)] - pub fn set_nsec(&mut self, val: super::vals::SwLock50nsec) { - self.0 = (self.0 & !(0x03 << 2usize)) | (((val.to_bits() as u32) & 0x03) << 2usize); - } -} -impl Default for SwLock50 { - #[inline(always)] - fn default() -> SwLock50 { - SwLock50(0) - } -} -#[doc = "Software lock register for page 51. Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page."] -#[repr(transparent)] -#[derive(Copy, Clone, Eq, PartialEq)] -pub struct SwLock51(pub u32); -impl SwLock51 { - #[doc = "Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code."] - #[inline(always)] - pub const fn sec(&self) -> super::vals::SwLock51sec { - let val = (self.0 >> 0usize) & 0x03; - super::vals::SwLock51sec::from_bits(val as u8) - } - #[doc = "Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code."] - #[inline(always)] - pub fn set_sec(&mut self, val: super::vals::SwLock51sec) { - self.0 = (self.0 & !(0x03 << 0usize)) | (((val.to_bits() as u32) & 0x03) << 0usize); - } - #[doc = "Non-secure lock status. Writes are OR'd with the current value."] - #[inline(always)] - pub const fn nsec(&self) -> super::vals::SwLock51nsec { - let val = (self.0 >> 2usize) & 0x03; - super::vals::SwLock51nsec::from_bits(val as u8) - } - #[doc = "Non-secure lock status. Writes are OR'd with the current value."] - #[inline(always)] - pub fn set_nsec(&mut self, val: super::vals::SwLock51nsec) { - self.0 = (self.0 & !(0x03 << 2usize)) | (((val.to_bits() as u32) & 0x03) << 2usize); - } -} -impl Default for SwLock51 { - #[inline(always)] - fn default() -> SwLock51 { - SwLock51(0) - } -} -#[doc = "Software lock register for page 52. Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page."] -#[repr(transparent)] -#[derive(Copy, Clone, Eq, PartialEq)] -pub struct SwLock52(pub u32); -impl SwLock52 { - #[doc = "Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code."] - #[inline(always)] - pub const fn sec(&self) -> super::vals::SwLock52sec { - let val = (self.0 >> 0usize) & 0x03; - super::vals::SwLock52sec::from_bits(val as u8) - } - #[doc = "Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code."] - #[inline(always)] - pub fn set_sec(&mut self, val: super::vals::SwLock52sec) { - self.0 = (self.0 & !(0x03 << 0usize)) | (((val.to_bits() as u32) & 0x03) << 0usize); - } - #[doc = "Non-secure lock status. Writes are OR'd with the current value."] - #[inline(always)] - pub const fn nsec(&self) -> super::vals::SwLock52nsec { - let val = (self.0 >> 2usize) & 0x03; - super::vals::SwLock52nsec::from_bits(val as u8) - } - #[doc = "Non-secure lock status. Writes are OR'd with the current value."] - #[inline(always)] - pub fn set_nsec(&mut self, val: super::vals::SwLock52nsec) { - self.0 = (self.0 & !(0x03 << 2usize)) | (((val.to_bits() as u32) & 0x03) << 2usize); - } -} -impl Default for SwLock52 { - #[inline(always)] - fn default() -> SwLock52 { - SwLock52(0) - } -} -#[doc = "Software lock register for page 53. Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page."] -#[repr(transparent)] -#[derive(Copy, Clone, Eq, PartialEq)] -pub struct SwLock53(pub u32); -impl SwLock53 { - #[doc = "Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code."] - #[inline(always)] - pub const fn sec(&self) -> super::vals::SwLock53sec { - let val = (self.0 >> 0usize) & 0x03; - super::vals::SwLock53sec::from_bits(val as u8) - } - #[doc = "Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code."] - #[inline(always)] - pub fn set_sec(&mut self, val: super::vals::SwLock53sec) { - self.0 = (self.0 & !(0x03 << 0usize)) | (((val.to_bits() as u32) & 0x03) << 0usize); - } - #[doc = "Non-secure lock status. Writes are OR'd with the current value."] - #[inline(always)] - pub const fn nsec(&self) -> super::vals::SwLock53nsec { - let val = (self.0 >> 2usize) & 0x03; - super::vals::SwLock53nsec::from_bits(val as u8) - } - #[doc = "Non-secure lock status. Writes are OR'd with the current value."] - #[inline(always)] - pub fn set_nsec(&mut self, val: super::vals::SwLock53nsec) { - self.0 = (self.0 & !(0x03 << 2usize)) | (((val.to_bits() as u32) & 0x03) << 2usize); - } -} -impl Default for SwLock53 { - #[inline(always)] - fn default() -> SwLock53 { - SwLock53(0) - } -} -#[doc = "Software lock register for page 54. Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page."] -#[repr(transparent)] -#[derive(Copy, Clone, Eq, PartialEq)] -pub struct SwLock54(pub u32); -impl SwLock54 { - #[doc = "Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code."] - #[inline(always)] - pub const fn sec(&self) -> super::vals::SwLock54sec { - let val = (self.0 >> 0usize) & 0x03; - super::vals::SwLock54sec::from_bits(val as u8) - } - #[doc = "Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code."] - #[inline(always)] - pub fn set_sec(&mut self, val: super::vals::SwLock54sec) { - self.0 = (self.0 & !(0x03 << 0usize)) | (((val.to_bits() as u32) & 0x03) << 0usize); - } - #[doc = "Non-secure lock status. Writes are OR'd with the current value."] - #[inline(always)] - pub const fn nsec(&self) -> super::vals::SwLock54nsec { - let val = (self.0 >> 2usize) & 0x03; - super::vals::SwLock54nsec::from_bits(val as u8) - } - #[doc = "Non-secure lock status. Writes are OR'd with the current value."] - #[inline(always)] - pub fn set_nsec(&mut self, val: super::vals::SwLock54nsec) { - self.0 = (self.0 & !(0x03 << 2usize)) | (((val.to_bits() as u32) & 0x03) << 2usize); - } -} -impl Default for SwLock54 { - #[inline(always)] - fn default() -> SwLock54 { - SwLock54(0) - } -} -#[doc = "Software lock register for page 55. Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page."] -#[repr(transparent)] -#[derive(Copy, Clone, Eq, PartialEq)] -pub struct SwLock55(pub u32); -impl SwLock55 { - #[doc = "Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code."] - #[inline(always)] - pub const fn sec(&self) -> super::vals::SwLock55sec { - let val = (self.0 >> 0usize) & 0x03; - super::vals::SwLock55sec::from_bits(val as u8) - } - #[doc = "Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code."] - #[inline(always)] - pub fn set_sec(&mut self, val: super::vals::SwLock55sec) { - self.0 = (self.0 & !(0x03 << 0usize)) | (((val.to_bits() as u32) & 0x03) << 0usize); - } - #[doc = "Non-secure lock status. Writes are OR'd with the current value."] - #[inline(always)] - pub const fn nsec(&self) -> super::vals::SwLock55nsec { - let val = (self.0 >> 2usize) & 0x03; - super::vals::SwLock55nsec::from_bits(val as u8) - } - #[doc = "Non-secure lock status. Writes are OR'd with the current value."] - #[inline(always)] - pub fn set_nsec(&mut self, val: super::vals::SwLock55nsec) { - self.0 = (self.0 & !(0x03 << 2usize)) | (((val.to_bits() as u32) & 0x03) << 2usize); - } -} -impl Default for SwLock55 { - #[inline(always)] - fn default() -> SwLock55 { - SwLock55(0) - } -} -#[doc = "Software lock register for page 56. Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page."] -#[repr(transparent)] -#[derive(Copy, Clone, Eq, PartialEq)] -pub struct SwLock56(pub u32); -impl SwLock56 { - #[doc = "Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code."] - #[inline(always)] - pub const fn sec(&self) -> super::vals::SwLock56sec { - let val = (self.0 >> 0usize) & 0x03; - super::vals::SwLock56sec::from_bits(val as u8) - } - #[doc = "Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code."] - #[inline(always)] - pub fn set_sec(&mut self, val: super::vals::SwLock56sec) { - self.0 = (self.0 & !(0x03 << 0usize)) | (((val.to_bits() as u32) & 0x03) << 0usize); - } - #[doc = "Non-secure lock status. Writes are OR'd with the current value."] - #[inline(always)] - pub const fn nsec(&self) -> super::vals::SwLock56nsec { - let val = (self.0 >> 2usize) & 0x03; - super::vals::SwLock56nsec::from_bits(val as u8) - } - #[doc = "Non-secure lock status. Writes are OR'd with the current value."] - #[inline(always)] - pub fn set_nsec(&mut self, val: super::vals::SwLock56nsec) { - self.0 = (self.0 & !(0x03 << 2usize)) | (((val.to_bits() as u32) & 0x03) << 2usize); - } -} -impl Default for SwLock56 { - #[inline(always)] - fn default() -> SwLock56 { - SwLock56(0) - } -} -#[doc = "Software lock register for page 57. Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page."] -#[repr(transparent)] -#[derive(Copy, Clone, Eq, PartialEq)] -pub struct SwLock57(pub u32); -impl SwLock57 { - #[doc = "Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code."] - #[inline(always)] - pub const fn sec(&self) -> super::vals::SwLock57sec { - let val = (self.0 >> 0usize) & 0x03; - super::vals::SwLock57sec::from_bits(val as u8) - } - #[doc = "Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code."] - #[inline(always)] - pub fn set_sec(&mut self, val: super::vals::SwLock57sec) { - self.0 = (self.0 & !(0x03 << 0usize)) | (((val.to_bits() as u32) & 0x03) << 0usize); - } - #[doc = "Non-secure lock status. Writes are OR'd with the current value."] - #[inline(always)] - pub const fn nsec(&self) -> super::vals::SwLock57nsec { - let val = (self.0 >> 2usize) & 0x03; - super::vals::SwLock57nsec::from_bits(val as u8) - } - #[doc = "Non-secure lock status. Writes are OR'd with the current value."] - #[inline(always)] - pub fn set_nsec(&mut self, val: super::vals::SwLock57nsec) { - self.0 = (self.0 & !(0x03 << 2usize)) | (((val.to_bits() as u32) & 0x03) << 2usize); - } -} -impl Default for SwLock57 { - #[inline(always)] - fn default() -> SwLock57 { - SwLock57(0) - } -} -#[doc = "Software lock register for page 58. Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page."] -#[repr(transparent)] -#[derive(Copy, Clone, Eq, PartialEq)] -pub struct SwLock58(pub u32); -impl SwLock58 { - #[doc = "Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code."] - #[inline(always)] - pub const fn sec(&self) -> super::vals::SwLock58sec { - let val = (self.0 >> 0usize) & 0x03; - super::vals::SwLock58sec::from_bits(val as u8) - } - #[doc = "Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code."] - #[inline(always)] - pub fn set_sec(&mut self, val: super::vals::SwLock58sec) { - self.0 = (self.0 & !(0x03 << 0usize)) | (((val.to_bits() as u32) & 0x03) << 0usize); - } - #[doc = "Non-secure lock status. Writes are OR'd with the current value."] - #[inline(always)] - pub const fn nsec(&self) -> super::vals::SwLock58nsec { - let val = (self.0 >> 2usize) & 0x03; - super::vals::SwLock58nsec::from_bits(val as u8) - } - #[doc = "Non-secure lock status. Writes are OR'd with the current value."] - #[inline(always)] - pub fn set_nsec(&mut self, val: super::vals::SwLock58nsec) { - self.0 = (self.0 & !(0x03 << 2usize)) | (((val.to_bits() as u32) & 0x03) << 2usize); - } -} -impl Default for SwLock58 { - #[inline(always)] - fn default() -> SwLock58 { - SwLock58(0) - } -} -#[doc = "Software lock register for page 59. Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page."] -#[repr(transparent)] -#[derive(Copy, Clone, Eq, PartialEq)] -pub struct SwLock59(pub u32); -impl SwLock59 { - #[doc = "Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code."] - #[inline(always)] - pub const fn sec(&self) -> super::vals::SwLock59sec { - let val = (self.0 >> 0usize) & 0x03; - super::vals::SwLock59sec::from_bits(val as u8) - } - #[doc = "Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code."] - #[inline(always)] - pub fn set_sec(&mut self, val: super::vals::SwLock59sec) { - self.0 = (self.0 & !(0x03 << 0usize)) | (((val.to_bits() as u32) & 0x03) << 0usize); - } - #[doc = "Non-secure lock status. Writes are OR'd with the current value."] - #[inline(always)] - pub const fn nsec(&self) -> super::vals::SwLock59nsec { - let val = (self.0 >> 2usize) & 0x03; - super::vals::SwLock59nsec::from_bits(val as u8) - } - #[doc = "Non-secure lock status. Writes are OR'd with the current value."] - #[inline(always)] - pub fn set_nsec(&mut self, val: super::vals::SwLock59nsec) { - self.0 = (self.0 & !(0x03 << 2usize)) | (((val.to_bits() as u32) & 0x03) << 2usize); - } -} -impl Default for SwLock59 { - #[inline(always)] - fn default() -> SwLock59 { - SwLock59(0) - } -} -#[doc = "Software lock register for page 6. Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page."] -#[repr(transparent)] -#[derive(Copy, Clone, Eq, PartialEq)] -pub struct SwLock6(pub u32); -impl SwLock6 { - #[doc = "Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code."] - #[inline(always)] - pub const fn sec(&self) -> super::vals::SwLock6sec { - let val = (self.0 >> 0usize) & 0x03; - super::vals::SwLock6sec::from_bits(val as u8) - } - #[doc = "Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code."] - #[inline(always)] - pub fn set_sec(&mut self, val: super::vals::SwLock6sec) { - self.0 = (self.0 & !(0x03 << 0usize)) | (((val.to_bits() as u32) & 0x03) << 0usize); - } - #[doc = "Non-secure lock status. Writes are OR'd with the current value."] - #[inline(always)] - pub const fn nsec(&self) -> super::vals::SwLock6nsec { - let val = (self.0 >> 2usize) & 0x03; - super::vals::SwLock6nsec::from_bits(val as u8) - } - #[doc = "Non-secure lock status. Writes are OR'd with the current value."] - #[inline(always)] - pub fn set_nsec(&mut self, val: super::vals::SwLock6nsec) { - self.0 = (self.0 & !(0x03 << 2usize)) | (((val.to_bits() as u32) & 0x03) << 2usize); - } -} -impl Default for SwLock6 { - #[inline(always)] - fn default() -> SwLock6 { - SwLock6(0) - } -} -#[doc = "Software lock register for page 60. Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page."] -#[repr(transparent)] -#[derive(Copy, Clone, Eq, PartialEq)] -pub struct SwLock60(pub u32); -impl SwLock60 { - #[doc = "Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code."] - #[inline(always)] - pub const fn sec(&self) -> super::vals::SwLock60sec { - let val = (self.0 >> 0usize) & 0x03; - super::vals::SwLock60sec::from_bits(val as u8) - } - #[doc = "Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code."] - #[inline(always)] - pub fn set_sec(&mut self, val: super::vals::SwLock60sec) { - self.0 = (self.0 & !(0x03 << 0usize)) | (((val.to_bits() as u32) & 0x03) << 0usize); - } - #[doc = "Non-secure lock status. Writes are OR'd with the current value."] - #[inline(always)] - pub const fn nsec(&self) -> super::vals::SwLock60nsec { - let val = (self.0 >> 2usize) & 0x03; - super::vals::SwLock60nsec::from_bits(val as u8) - } - #[doc = "Non-secure lock status. Writes are OR'd with the current value."] - #[inline(always)] - pub fn set_nsec(&mut self, val: super::vals::SwLock60nsec) { - self.0 = (self.0 & !(0x03 << 2usize)) | (((val.to_bits() as u32) & 0x03) << 2usize); - } -} -impl Default for SwLock60 { - #[inline(always)] - fn default() -> SwLock60 { - SwLock60(0) - } -} -#[doc = "Software lock register for page 61. Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page."] -#[repr(transparent)] -#[derive(Copy, Clone, Eq, PartialEq)] -pub struct SwLock61(pub u32); -impl SwLock61 { - #[doc = "Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code."] - #[inline(always)] - pub const fn sec(&self) -> super::vals::SwLock61sec { - let val = (self.0 >> 0usize) & 0x03; - super::vals::SwLock61sec::from_bits(val as u8) - } - #[doc = "Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code."] - #[inline(always)] - pub fn set_sec(&mut self, val: super::vals::SwLock61sec) { - self.0 = (self.0 & !(0x03 << 0usize)) | (((val.to_bits() as u32) & 0x03) << 0usize); - } - #[doc = "Non-secure lock status. Writes are OR'd with the current value."] - #[inline(always)] - pub const fn nsec(&self) -> super::vals::SwLock61nsec { - let val = (self.0 >> 2usize) & 0x03; - super::vals::SwLock61nsec::from_bits(val as u8) - } - #[doc = "Non-secure lock status. Writes are OR'd with the current value."] - #[inline(always)] - pub fn set_nsec(&mut self, val: super::vals::SwLock61nsec) { - self.0 = (self.0 & !(0x03 << 2usize)) | (((val.to_bits() as u32) & 0x03) << 2usize); - } -} -impl Default for SwLock61 { - #[inline(always)] - fn default() -> SwLock61 { - SwLock61(0) - } -} -#[doc = "Software lock register for page 62. Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page."] -#[repr(transparent)] -#[derive(Copy, Clone, Eq, PartialEq)] -pub struct SwLock62(pub u32); -impl SwLock62 { - #[doc = "Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code."] - #[inline(always)] - pub const fn sec(&self) -> super::vals::SwLock62sec { - let val = (self.0 >> 0usize) & 0x03; - super::vals::SwLock62sec::from_bits(val as u8) - } - #[doc = "Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code."] - #[inline(always)] - pub fn set_sec(&mut self, val: super::vals::SwLock62sec) { - self.0 = (self.0 & !(0x03 << 0usize)) | (((val.to_bits() as u32) & 0x03) << 0usize); - } - #[doc = "Non-secure lock status. Writes are OR'd with the current value."] - #[inline(always)] - pub const fn nsec(&self) -> super::vals::SwLock62nsec { - let val = (self.0 >> 2usize) & 0x03; - super::vals::SwLock62nsec::from_bits(val as u8) - } - #[doc = "Non-secure lock status. Writes are OR'd with the current value."] - #[inline(always)] - pub fn set_nsec(&mut self, val: super::vals::SwLock62nsec) { - self.0 = (self.0 & !(0x03 << 2usize)) | (((val.to_bits() as u32) & 0x03) << 2usize); - } -} -impl Default for SwLock62 { - #[inline(always)] - fn default() -> SwLock62 { - SwLock62(0) - } -} -#[doc = "Software lock register for page 63. Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page."] -#[repr(transparent)] -#[derive(Copy, Clone, Eq, PartialEq)] -pub struct SwLock63(pub u32); -impl SwLock63 { - #[doc = "Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code."] - #[inline(always)] - pub const fn sec(&self) -> super::vals::SwLock63sec { - let val = (self.0 >> 0usize) & 0x03; - super::vals::SwLock63sec::from_bits(val as u8) - } - #[doc = "Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code."] - #[inline(always)] - pub fn set_sec(&mut self, val: super::vals::SwLock63sec) { - self.0 = (self.0 & !(0x03 << 0usize)) | (((val.to_bits() as u32) & 0x03) << 0usize); - } - #[doc = "Non-secure lock status. Writes are OR'd with the current value."] - #[inline(always)] - pub const fn nsec(&self) -> super::vals::SwLock63nsec { - let val = (self.0 >> 2usize) & 0x03; - super::vals::SwLock63nsec::from_bits(val as u8) - } - #[doc = "Non-secure lock status. Writes are OR'd with the current value."] - #[inline(always)] - pub fn set_nsec(&mut self, val: super::vals::SwLock63nsec) { - self.0 = (self.0 & !(0x03 << 2usize)) | (((val.to_bits() as u32) & 0x03) << 2usize); - } -} -impl Default for SwLock63 { - #[inline(always)] - fn default() -> SwLock63 { - SwLock63(0) - } -} -#[doc = "Software lock register for page 7. Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page."] -#[repr(transparent)] -#[derive(Copy, Clone, Eq, PartialEq)] -pub struct SwLock7(pub u32); -impl SwLock7 { - #[doc = "Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code."] - #[inline(always)] - pub const fn sec(&self) -> super::vals::SwLock7sec { - let val = (self.0 >> 0usize) & 0x03; - super::vals::SwLock7sec::from_bits(val as u8) - } - #[doc = "Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code."] - #[inline(always)] - pub fn set_sec(&mut self, val: super::vals::SwLock7sec) { - self.0 = (self.0 & !(0x03 << 0usize)) | (((val.to_bits() as u32) & 0x03) << 0usize); - } - #[doc = "Non-secure lock status. Writes are OR'd with the current value."] - #[inline(always)] - pub const fn nsec(&self) -> super::vals::SwLock7nsec { - let val = (self.0 >> 2usize) & 0x03; - super::vals::SwLock7nsec::from_bits(val as u8) - } - #[doc = "Non-secure lock status. Writes are OR'd with the current value."] - #[inline(always)] - pub fn set_nsec(&mut self, val: super::vals::SwLock7nsec) { - self.0 = (self.0 & !(0x03 << 2usize)) | (((val.to_bits() as u32) & 0x03) << 2usize); - } -} -impl Default for SwLock7 { - #[inline(always)] - fn default() -> SwLock7 { - SwLock7(0) - } -} -#[doc = "Software lock register for page 8. Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page."] -#[repr(transparent)] -#[derive(Copy, Clone, Eq, PartialEq)] -pub struct SwLock8(pub u32); -impl SwLock8 { - #[doc = "Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code."] - #[inline(always)] - pub const fn sec(&self) -> super::vals::SwLock8sec { - let val = (self.0 >> 0usize) & 0x03; - super::vals::SwLock8sec::from_bits(val as u8) - } - #[doc = "Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code."] - #[inline(always)] - pub fn set_sec(&mut self, val: super::vals::SwLock8sec) { - self.0 = (self.0 & !(0x03 << 0usize)) | (((val.to_bits() as u32) & 0x03) << 0usize); - } - #[doc = "Non-secure lock status. Writes are OR'd with the current value."] - #[inline(always)] - pub const fn nsec(&self) -> super::vals::SwLock8nsec { - let val = (self.0 >> 2usize) & 0x03; - super::vals::SwLock8nsec::from_bits(val as u8) - } - #[doc = "Non-secure lock status. Writes are OR'd with the current value."] - #[inline(always)] - pub fn set_nsec(&mut self, val: super::vals::SwLock8nsec) { - self.0 = (self.0 & !(0x03 << 2usize)) | (((val.to_bits() as u32) & 0x03) << 2usize); - } -} -impl Default for SwLock8 { - #[inline(always)] - fn default() -> SwLock8 { - SwLock8(0) - } -} -#[doc = "Software lock register for page 9. Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page."] -#[repr(transparent)] -#[derive(Copy, Clone, Eq, PartialEq)] -pub struct SwLock9(pub u32); -impl SwLock9 { +pub struct SwLock(pub u32); +impl SwLock { #[doc = "Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code."] #[inline(always)] - pub const fn sec(&self) -> super::vals::SwLock9sec { + pub const fn sec(&self) -> super::vals::SwLockSec { let val = (self.0 >> 0usize) & 0x03; - super::vals::SwLock9sec::from_bits(val as u8) + super::vals::SwLockSec::from_bits(val as u8) } #[doc = "Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code."] #[inline(always)] - pub fn set_sec(&mut self, val: super::vals::SwLock9sec) { + pub fn set_sec(&mut self, val: super::vals::SwLockSec) { self.0 = (self.0 & !(0x03 << 0usize)) | (((val.to_bits() as u32) & 0x03) << 0usize); } #[doc = "Non-secure lock status. Writes are OR'd with the current value."] #[inline(always)] - pub const fn nsec(&self) -> super::vals::SwLock9nsec { + pub const fn nsec(&self) -> super::vals::SwLockNsec { let val = (self.0 >> 2usize) & 0x03; - super::vals::SwLock9nsec::from_bits(val as u8) + super::vals::SwLockNsec::from_bits(val as u8) } #[doc = "Non-secure lock status. Writes are OR'd with the current value."] #[inline(always)] - pub fn set_nsec(&mut self, val: super::vals::SwLock9nsec) { + pub fn set_nsec(&mut self, val: super::vals::SwLockNsec) { self.0 = (self.0 & !(0x03 << 2usize)) | (((val.to_bits() as u32) & 0x03) << 2usize); } } -impl Default for SwLock9 { +impl Default for SwLock { #[inline(always)] - fn default() -> SwLock9 { - SwLock9(0) + fn default() -> SwLock { + SwLock(0) } } #[doc = "Controls for APB data read interface (USER interface)"] diff --git a/src/rp235x/otp/vals.rs b/src/rp235x/otp/vals.rs index 315ba766..d311d35f 100644 --- a/src/rp235x/otp/vals.rs +++ b/src/rp235x/otp/vals.rs @@ -2,7 +2,7 @@ #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] pub enum ArchselCore0 { #[doc = "Switch core 0 to Arm (Cortex-M33)"] - ARM = 0, + ARM = 0x0, #[doc = "Switch core 0 to RISC-V (Hazard3)"] RISCV = 0x01, } @@ -32,7 +32,7 @@ impl From for u8 { #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] pub enum ArchselCore1 { #[doc = "Switch core 1 to Arm (Cortex-M33)"] - ARM = 0, + ARM = 0x0, #[doc = "Switch core 1 to RISC-V (Hazard3)"] RISCV = 0x01, } @@ -62,7 +62,7 @@ impl From for u8 { #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] pub enum ArchselStatusCore0 { #[doc = "Core 0 is currently Arm (Cortex-M33)"] - ARM = 0, + ARM = 0x0, #[doc = "Core 0 is currently RISC-V (Hazard3)"] RISCV = 0x01, } @@ -92,7 +92,7 @@ impl From for u8 { #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] pub enum ArchselStatusCore1 { #[doc = "Core 1 is currently Arm (Cortex-M33)"] - ARM = 0, + ARM = 0x0, #[doc = "Core 1 is currently RISC-V (Hazard3)"] RISCV = 0x01, } @@ -120,15 +120,15 @@ impl From for u8 { } #[repr(u8)] #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] -pub enum SwLock0nsec { - READ_WRITE = 0, +pub enum SwLockNsec { + READ_WRITE = 0x0, READ_ONLY = 0x01, _RESERVED_2 = 0x02, INACCESSIBLE = 0x03, } -impl SwLock0nsec { +impl SwLockNsec { #[inline(always)] - pub const fn from_bits(val: u8) -> SwLock0nsec { + pub const fn from_bits(val: u8) -> SwLockNsec { unsafe { core::mem::transmute(val & 0x03) } } #[inline(always)] @@ -136,29 +136,29 @@ impl SwLock0nsec { unsafe { core::mem::transmute(self) } } } -impl From for SwLock0nsec { +impl From for SwLockNsec { #[inline(always)] - fn from(val: u8) -> SwLock0nsec { - SwLock0nsec::from_bits(val) + fn from(val: u8) -> SwLockNsec { + SwLockNsec::from_bits(val) } } -impl From for u8 { +impl From for u8 { #[inline(always)] - fn from(val: SwLock0nsec) -> u8 { - SwLock0nsec::to_bits(val) + fn from(val: SwLockNsec) -> u8 { + SwLockNsec::to_bits(val) } } #[repr(u8)] #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] -pub enum SwLock0sec { - READ_WRITE = 0, +pub enum SwLockSec { + READ_WRITE = 0x0, READ_ONLY = 0x01, _RESERVED_2 = 0x02, INACCESSIBLE = 0x03, } -impl SwLock0sec { +impl SwLockSec { #[inline(always)] - pub const fn from_bits(val: u8) -> SwLock0sec { + pub const fn from_bits(val: u8) -> SwLockSec { unsafe { core::mem::transmute(val & 0x03) } } #[inline(always)] @@ -166,3795 +166,15 @@ impl SwLock0sec { unsafe { core::mem::transmute(self) } } } -impl From for SwLock0sec { +impl From for SwLockSec { #[inline(always)] - fn from(val: u8) -> SwLock0sec { - SwLock0sec::from_bits(val) + fn from(val: u8) -> SwLockSec { + SwLockSec::from_bits(val) } } -impl From for u8 { +impl From for u8 { #[inline(always)] - fn from(val: SwLock0sec) -> u8 { - SwLock0sec::to_bits(val) - } -} -#[repr(u8)] -#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] -pub enum SwLock10nsec { - READ_WRITE = 0, - READ_ONLY = 0x01, - _RESERVED_2 = 0x02, - INACCESSIBLE = 0x03, -} -impl SwLock10nsec { - #[inline(always)] - pub const fn from_bits(val: u8) -> SwLock10nsec { - unsafe { core::mem::transmute(val & 0x03) } - } - #[inline(always)] - pub const fn to_bits(self) -> u8 { - unsafe { core::mem::transmute(self) } - } -} -impl From for SwLock10nsec { - #[inline(always)] - fn from(val: u8) -> SwLock10nsec { - SwLock10nsec::from_bits(val) - } -} -impl From for u8 { - #[inline(always)] - fn from(val: SwLock10nsec) -> u8 { - SwLock10nsec::to_bits(val) - } -} -#[repr(u8)] -#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] -pub enum SwLock10sec { - READ_WRITE = 0, - READ_ONLY = 0x01, - _RESERVED_2 = 0x02, - INACCESSIBLE = 0x03, -} -impl SwLock10sec { - #[inline(always)] - pub const fn from_bits(val: u8) -> SwLock10sec { - unsafe { core::mem::transmute(val & 0x03) } - } - #[inline(always)] - pub const fn to_bits(self) -> u8 { - unsafe { core::mem::transmute(self) } - } -} -impl From for SwLock10sec { - #[inline(always)] - fn from(val: u8) -> SwLock10sec { - SwLock10sec::from_bits(val) - } -} -impl From for u8 { - #[inline(always)] - fn from(val: SwLock10sec) -> u8 { - SwLock10sec::to_bits(val) - } -} -#[repr(u8)] -#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] -pub enum SwLock11nsec { - READ_WRITE = 0, - READ_ONLY = 0x01, - _RESERVED_2 = 0x02, - INACCESSIBLE = 0x03, -} -impl SwLock11nsec { - #[inline(always)] - pub const fn from_bits(val: u8) -> SwLock11nsec { - unsafe { core::mem::transmute(val & 0x03) } - } - #[inline(always)] - pub const fn to_bits(self) -> u8 { - unsafe { core::mem::transmute(self) } - } -} -impl From for SwLock11nsec { - #[inline(always)] - fn from(val: u8) -> SwLock11nsec { - SwLock11nsec::from_bits(val) - } -} -impl From for u8 { - #[inline(always)] - fn from(val: SwLock11nsec) -> u8 { - SwLock11nsec::to_bits(val) - } -} -#[repr(u8)] -#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] -pub enum SwLock11sec { - READ_WRITE = 0, - READ_ONLY = 0x01, - _RESERVED_2 = 0x02, - INACCESSIBLE = 0x03, -} -impl SwLock11sec { - #[inline(always)] - pub const fn from_bits(val: u8) -> SwLock11sec { - unsafe { core::mem::transmute(val & 0x03) } - } - #[inline(always)] - pub const fn to_bits(self) -> u8 { - unsafe { core::mem::transmute(self) } - } -} -impl From for SwLock11sec { - #[inline(always)] - fn from(val: u8) -> SwLock11sec { - SwLock11sec::from_bits(val) - } -} -impl From for u8 { - #[inline(always)] - fn from(val: SwLock11sec) -> u8 { - SwLock11sec::to_bits(val) - } -} -#[repr(u8)] -#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] -pub enum SwLock12nsec { - READ_WRITE = 0, - READ_ONLY = 0x01, - _RESERVED_2 = 0x02, - INACCESSIBLE = 0x03, -} -impl SwLock12nsec { - #[inline(always)] - pub const fn from_bits(val: u8) -> SwLock12nsec { - unsafe { core::mem::transmute(val & 0x03) } - } - #[inline(always)] - pub const fn to_bits(self) -> u8 { - unsafe { core::mem::transmute(self) } - } -} -impl From for SwLock12nsec { - #[inline(always)] - fn from(val: u8) -> SwLock12nsec { - SwLock12nsec::from_bits(val) - } -} -impl From for u8 { - #[inline(always)] - fn from(val: SwLock12nsec) -> u8 { - SwLock12nsec::to_bits(val) - } -} -#[repr(u8)] -#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] -pub enum SwLock12sec { - READ_WRITE = 0, - READ_ONLY = 0x01, - _RESERVED_2 = 0x02, - INACCESSIBLE = 0x03, -} -impl SwLock12sec { - #[inline(always)] - pub const fn from_bits(val: u8) -> SwLock12sec { - unsafe { core::mem::transmute(val & 0x03) } - } - #[inline(always)] - pub const fn to_bits(self) -> u8 { - unsafe { core::mem::transmute(self) } - } -} -impl From for SwLock12sec { - #[inline(always)] - fn from(val: u8) -> SwLock12sec { - SwLock12sec::from_bits(val) - } -} -impl From for u8 { - #[inline(always)] - fn from(val: SwLock12sec) -> u8 { - SwLock12sec::to_bits(val) - } -} -#[repr(u8)] -#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] -pub enum SwLock13nsec { - READ_WRITE = 0, - READ_ONLY = 0x01, - _RESERVED_2 = 0x02, - INACCESSIBLE = 0x03, -} -impl SwLock13nsec { - #[inline(always)] - pub const fn from_bits(val: u8) -> SwLock13nsec { - unsafe { core::mem::transmute(val & 0x03) } - } - #[inline(always)] - pub const fn to_bits(self) -> u8 { - unsafe { core::mem::transmute(self) } - } -} -impl From for SwLock13nsec { - #[inline(always)] - fn from(val: u8) -> SwLock13nsec { - SwLock13nsec::from_bits(val) - } -} -impl From for u8 { - #[inline(always)] - fn from(val: SwLock13nsec) -> u8 { - SwLock13nsec::to_bits(val) - } -} -#[repr(u8)] -#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] -pub enum SwLock13sec { - READ_WRITE = 0, - READ_ONLY = 0x01, - _RESERVED_2 = 0x02, - INACCESSIBLE = 0x03, -} -impl SwLock13sec { - #[inline(always)] - pub const fn from_bits(val: u8) -> SwLock13sec { - unsafe { core::mem::transmute(val & 0x03) } - } - #[inline(always)] - pub const fn to_bits(self) -> u8 { - unsafe { core::mem::transmute(self) } - } -} -impl From for SwLock13sec { - #[inline(always)] - fn from(val: u8) -> SwLock13sec { - SwLock13sec::from_bits(val) - } -} -impl From for u8 { - #[inline(always)] - fn from(val: SwLock13sec) -> u8 { - SwLock13sec::to_bits(val) - } -} -#[repr(u8)] -#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] -pub enum SwLock14nsec { - READ_WRITE = 0, - READ_ONLY = 0x01, - _RESERVED_2 = 0x02, - INACCESSIBLE = 0x03, -} -impl SwLock14nsec { - #[inline(always)] - pub const fn from_bits(val: u8) -> SwLock14nsec { - unsafe { core::mem::transmute(val & 0x03) } - } - #[inline(always)] - pub const fn to_bits(self) -> u8 { - unsafe { core::mem::transmute(self) } - } -} -impl From for SwLock14nsec { - #[inline(always)] - fn from(val: u8) -> SwLock14nsec { - SwLock14nsec::from_bits(val) - } -} -impl From for u8 { - #[inline(always)] - fn from(val: SwLock14nsec) -> u8 { - SwLock14nsec::to_bits(val) - } -} -#[repr(u8)] -#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] -pub enum SwLock14sec { - READ_WRITE = 0, - READ_ONLY = 0x01, - _RESERVED_2 = 0x02, - INACCESSIBLE = 0x03, -} -impl SwLock14sec { - #[inline(always)] - pub const fn from_bits(val: u8) -> SwLock14sec { - unsafe { core::mem::transmute(val & 0x03) } - } - #[inline(always)] - pub const fn to_bits(self) -> u8 { - unsafe { core::mem::transmute(self) } - } -} -impl From for SwLock14sec { - #[inline(always)] - fn from(val: u8) -> SwLock14sec { - SwLock14sec::from_bits(val) - } -} -impl From for u8 { - #[inline(always)] - fn from(val: SwLock14sec) -> u8 { - SwLock14sec::to_bits(val) - } -} -#[repr(u8)] -#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] -pub enum SwLock15nsec { - READ_WRITE = 0, - READ_ONLY = 0x01, - _RESERVED_2 = 0x02, - INACCESSIBLE = 0x03, -} -impl SwLock15nsec { - #[inline(always)] - pub const fn from_bits(val: u8) -> SwLock15nsec { - unsafe { core::mem::transmute(val & 0x03) } - } - #[inline(always)] - pub const fn to_bits(self) -> u8 { - unsafe { core::mem::transmute(self) } - } -} -impl From for SwLock15nsec { - #[inline(always)] - fn from(val: u8) -> SwLock15nsec { - SwLock15nsec::from_bits(val) - } -} -impl From for u8 { - #[inline(always)] - fn from(val: SwLock15nsec) -> u8 { - SwLock15nsec::to_bits(val) - } -} -#[repr(u8)] -#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] -pub enum SwLock15sec { - READ_WRITE = 0, - READ_ONLY = 0x01, - _RESERVED_2 = 0x02, - INACCESSIBLE = 0x03, -} -impl SwLock15sec { - #[inline(always)] - pub const fn from_bits(val: u8) -> SwLock15sec { - unsafe { core::mem::transmute(val & 0x03) } - } - #[inline(always)] - pub const fn to_bits(self) -> u8 { - unsafe { core::mem::transmute(self) } - } -} -impl From for SwLock15sec { - #[inline(always)] - fn from(val: u8) -> SwLock15sec { - SwLock15sec::from_bits(val) - } -} -impl From for u8 { - #[inline(always)] - fn from(val: SwLock15sec) -> u8 { - SwLock15sec::to_bits(val) - } -} -#[repr(u8)] -#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] -pub enum SwLock16nsec { - READ_WRITE = 0, - READ_ONLY = 0x01, - _RESERVED_2 = 0x02, - INACCESSIBLE = 0x03, -} -impl SwLock16nsec { - #[inline(always)] - pub const fn from_bits(val: u8) -> SwLock16nsec { - unsafe { core::mem::transmute(val & 0x03) } - } - #[inline(always)] - pub const fn to_bits(self) -> u8 { - unsafe { core::mem::transmute(self) } - } -} -impl From for SwLock16nsec { - #[inline(always)] - fn from(val: u8) -> SwLock16nsec { - SwLock16nsec::from_bits(val) - } -} -impl From for u8 { - #[inline(always)] - fn from(val: SwLock16nsec) -> u8 { - SwLock16nsec::to_bits(val) - } -} -#[repr(u8)] -#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] -pub enum SwLock16sec { - READ_WRITE = 0, - READ_ONLY = 0x01, - _RESERVED_2 = 0x02, - INACCESSIBLE = 0x03, -} -impl SwLock16sec { - #[inline(always)] - pub const fn from_bits(val: u8) -> SwLock16sec { - unsafe { core::mem::transmute(val & 0x03) } - } - #[inline(always)] - pub const fn to_bits(self) -> u8 { - unsafe { core::mem::transmute(self) } - } -} -impl From for SwLock16sec { - #[inline(always)] - fn from(val: u8) -> SwLock16sec { - SwLock16sec::from_bits(val) - } -} -impl From for u8 { - #[inline(always)] - fn from(val: SwLock16sec) -> u8 { - SwLock16sec::to_bits(val) - } -} -#[repr(u8)] -#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] -pub enum SwLock17nsec { - READ_WRITE = 0, - READ_ONLY = 0x01, - _RESERVED_2 = 0x02, - INACCESSIBLE = 0x03, -} -impl SwLock17nsec { - #[inline(always)] - pub const fn from_bits(val: u8) -> SwLock17nsec { - unsafe { core::mem::transmute(val & 0x03) } - } - #[inline(always)] - pub const fn to_bits(self) -> u8 { - unsafe { core::mem::transmute(self) } - } -} -impl From for SwLock17nsec { - #[inline(always)] - fn from(val: u8) -> SwLock17nsec { - SwLock17nsec::from_bits(val) - } -} -impl From for u8 { - #[inline(always)] - fn from(val: SwLock17nsec) -> u8 { - SwLock17nsec::to_bits(val) - } -} -#[repr(u8)] -#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] -pub enum SwLock17sec { - READ_WRITE = 0, - READ_ONLY = 0x01, - _RESERVED_2 = 0x02, - INACCESSIBLE = 0x03, -} -impl SwLock17sec { - #[inline(always)] - pub const fn from_bits(val: u8) -> SwLock17sec { - unsafe { core::mem::transmute(val & 0x03) } - } - #[inline(always)] - pub const fn to_bits(self) -> u8 { - unsafe { core::mem::transmute(self) } - } -} -impl From for SwLock17sec { - #[inline(always)] - fn from(val: u8) -> SwLock17sec { - SwLock17sec::from_bits(val) - } -} -impl From for u8 { - #[inline(always)] - fn from(val: SwLock17sec) -> u8 { - SwLock17sec::to_bits(val) - } -} -#[repr(u8)] -#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] -pub enum SwLock18nsec { - READ_WRITE = 0, - READ_ONLY = 0x01, - _RESERVED_2 = 0x02, - INACCESSIBLE = 0x03, -} -impl SwLock18nsec { - #[inline(always)] - pub const fn from_bits(val: u8) -> SwLock18nsec { - unsafe { core::mem::transmute(val & 0x03) } - } - #[inline(always)] - pub const fn to_bits(self) -> u8 { - unsafe { core::mem::transmute(self) } - } -} -impl From for SwLock18nsec { - #[inline(always)] - fn from(val: u8) -> SwLock18nsec { - SwLock18nsec::from_bits(val) - } -} -impl From for u8 { - #[inline(always)] - fn from(val: SwLock18nsec) -> u8 { - SwLock18nsec::to_bits(val) - } -} -#[repr(u8)] -#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] -pub enum SwLock18sec { - READ_WRITE = 0, - READ_ONLY = 0x01, - _RESERVED_2 = 0x02, - INACCESSIBLE = 0x03, -} -impl SwLock18sec { - #[inline(always)] - pub const fn from_bits(val: u8) -> SwLock18sec { - unsafe { core::mem::transmute(val & 0x03) } - } - #[inline(always)] - pub const fn to_bits(self) -> u8 { - unsafe { core::mem::transmute(self) } - } -} -impl From for SwLock18sec { - #[inline(always)] - fn from(val: u8) -> SwLock18sec { - SwLock18sec::from_bits(val) - } -} -impl From for u8 { - #[inline(always)] - fn from(val: SwLock18sec) -> u8 { - SwLock18sec::to_bits(val) - } -} -#[repr(u8)] -#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] -pub enum SwLock19nsec { - READ_WRITE = 0, - READ_ONLY = 0x01, - _RESERVED_2 = 0x02, - INACCESSIBLE = 0x03, -} -impl SwLock19nsec { - #[inline(always)] - pub const fn from_bits(val: u8) -> SwLock19nsec { - unsafe { core::mem::transmute(val & 0x03) } - } - #[inline(always)] - pub const fn to_bits(self) -> u8 { - unsafe { core::mem::transmute(self) } - } -} -impl From for SwLock19nsec { - #[inline(always)] - fn from(val: u8) -> SwLock19nsec { - SwLock19nsec::from_bits(val) - } -} -impl From for u8 { - #[inline(always)] - fn from(val: SwLock19nsec) -> u8 { - SwLock19nsec::to_bits(val) - } -} -#[repr(u8)] -#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] -pub enum SwLock19sec { - READ_WRITE = 0, - READ_ONLY = 0x01, - _RESERVED_2 = 0x02, - INACCESSIBLE = 0x03, -} -impl SwLock19sec { - #[inline(always)] - pub const fn from_bits(val: u8) -> SwLock19sec { - unsafe { core::mem::transmute(val & 0x03) } - } - #[inline(always)] - pub const fn to_bits(self) -> u8 { - unsafe { core::mem::transmute(self) } - } -} -impl From for SwLock19sec { - #[inline(always)] - fn from(val: u8) -> SwLock19sec { - SwLock19sec::from_bits(val) - } -} -impl From for u8 { - #[inline(always)] - fn from(val: SwLock19sec) -> u8 { - SwLock19sec::to_bits(val) - } -} -#[repr(u8)] -#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] -pub enum SwLock1nsec { - READ_WRITE = 0, - READ_ONLY = 0x01, - _RESERVED_2 = 0x02, - INACCESSIBLE = 0x03, -} -impl SwLock1nsec { - #[inline(always)] - pub const fn from_bits(val: u8) -> SwLock1nsec { - unsafe { core::mem::transmute(val & 0x03) } - } - #[inline(always)] - pub const fn to_bits(self) -> u8 { - unsafe { core::mem::transmute(self) } - } -} -impl From for SwLock1nsec { - #[inline(always)] - fn from(val: u8) -> SwLock1nsec { - SwLock1nsec::from_bits(val) - } -} -impl From for u8 { - #[inline(always)] - fn from(val: SwLock1nsec) -> u8 { - SwLock1nsec::to_bits(val) - } -} -#[repr(u8)] -#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] -pub enum SwLock1sec { - READ_WRITE = 0, - READ_ONLY = 0x01, - _RESERVED_2 = 0x02, - INACCESSIBLE = 0x03, -} -impl SwLock1sec { - #[inline(always)] - pub const fn from_bits(val: u8) -> SwLock1sec { - unsafe { core::mem::transmute(val & 0x03) } - } - #[inline(always)] - pub const fn to_bits(self) -> u8 { - unsafe { core::mem::transmute(self) } - } -} -impl From for SwLock1sec { - #[inline(always)] - fn from(val: u8) -> SwLock1sec { - SwLock1sec::from_bits(val) - } -} -impl From for u8 { - #[inline(always)] - fn from(val: SwLock1sec) -> u8 { - SwLock1sec::to_bits(val) - } -} -#[repr(u8)] -#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] -pub enum SwLock20nsec { - READ_WRITE = 0, - READ_ONLY = 0x01, - _RESERVED_2 = 0x02, - INACCESSIBLE = 0x03, -} -impl SwLock20nsec { - #[inline(always)] - pub const fn from_bits(val: u8) -> SwLock20nsec { - unsafe { core::mem::transmute(val & 0x03) } - } - #[inline(always)] - pub const fn to_bits(self) -> u8 { - unsafe { core::mem::transmute(self) } - } -} -impl From for SwLock20nsec { - #[inline(always)] - fn from(val: u8) -> SwLock20nsec { - SwLock20nsec::from_bits(val) - } -} -impl From for u8 { - #[inline(always)] - fn from(val: SwLock20nsec) -> u8 { - SwLock20nsec::to_bits(val) - } -} -#[repr(u8)] -#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] -pub enum SwLock20sec { - READ_WRITE = 0, - READ_ONLY = 0x01, - _RESERVED_2 = 0x02, - INACCESSIBLE = 0x03, -} -impl SwLock20sec { - #[inline(always)] - pub const fn from_bits(val: u8) -> SwLock20sec { - unsafe { core::mem::transmute(val & 0x03) } - } - #[inline(always)] - pub const fn to_bits(self) -> u8 { - unsafe { core::mem::transmute(self) } - } -} -impl From for SwLock20sec { - #[inline(always)] - fn from(val: u8) -> SwLock20sec { - SwLock20sec::from_bits(val) - } -} -impl From for u8 { - #[inline(always)] - fn from(val: SwLock20sec) -> u8 { - SwLock20sec::to_bits(val) - } -} -#[repr(u8)] -#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] -pub enum SwLock21nsec { - READ_WRITE = 0, - READ_ONLY = 0x01, - _RESERVED_2 = 0x02, - INACCESSIBLE = 0x03, -} -impl SwLock21nsec { - #[inline(always)] - pub const fn from_bits(val: u8) -> SwLock21nsec { - unsafe { core::mem::transmute(val & 0x03) } - } - #[inline(always)] - pub const fn to_bits(self) -> u8 { - unsafe { core::mem::transmute(self) } - } -} -impl From for SwLock21nsec { - #[inline(always)] - fn from(val: u8) -> SwLock21nsec { - SwLock21nsec::from_bits(val) - } -} -impl From for u8 { - #[inline(always)] - fn from(val: SwLock21nsec) -> u8 { - SwLock21nsec::to_bits(val) - } -} -#[repr(u8)] -#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] -pub enum SwLock21sec { - READ_WRITE = 0, - READ_ONLY = 0x01, - _RESERVED_2 = 0x02, - INACCESSIBLE = 0x03, -} -impl SwLock21sec { - #[inline(always)] - pub const fn from_bits(val: u8) -> SwLock21sec { - unsafe { core::mem::transmute(val & 0x03) } - } - #[inline(always)] - pub const fn to_bits(self) -> u8 { - unsafe { core::mem::transmute(self) } - } -} -impl From for SwLock21sec { - #[inline(always)] - fn from(val: u8) -> SwLock21sec { - SwLock21sec::from_bits(val) - } -} -impl From for u8 { - #[inline(always)] - fn from(val: SwLock21sec) -> u8 { - SwLock21sec::to_bits(val) - } -} -#[repr(u8)] -#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] -pub enum SwLock22nsec { - READ_WRITE = 0, - READ_ONLY = 0x01, - _RESERVED_2 = 0x02, - INACCESSIBLE = 0x03, -} -impl SwLock22nsec { - #[inline(always)] - pub const fn from_bits(val: u8) -> SwLock22nsec { - unsafe { core::mem::transmute(val & 0x03) } - } - #[inline(always)] - pub const fn to_bits(self) -> u8 { - unsafe { core::mem::transmute(self) } - } -} -impl From for SwLock22nsec { - #[inline(always)] - fn from(val: u8) -> SwLock22nsec { - SwLock22nsec::from_bits(val) - } -} -impl From for u8 { - #[inline(always)] - fn from(val: SwLock22nsec) -> u8 { - SwLock22nsec::to_bits(val) - } -} -#[repr(u8)] -#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] -pub enum SwLock22sec { - READ_WRITE = 0, - READ_ONLY = 0x01, - _RESERVED_2 = 0x02, - INACCESSIBLE = 0x03, -} -impl SwLock22sec { - #[inline(always)] - pub const fn from_bits(val: u8) -> SwLock22sec { - unsafe { core::mem::transmute(val & 0x03) } - } - #[inline(always)] - pub const fn to_bits(self) -> u8 { - unsafe { core::mem::transmute(self) } - } -} -impl From for SwLock22sec { - #[inline(always)] - fn from(val: u8) -> SwLock22sec { - SwLock22sec::from_bits(val) - } -} -impl From for u8 { - #[inline(always)] - fn from(val: SwLock22sec) -> u8 { - SwLock22sec::to_bits(val) - } -} -#[repr(u8)] -#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] -pub enum SwLock23nsec { - READ_WRITE = 0, - READ_ONLY = 0x01, - _RESERVED_2 = 0x02, - INACCESSIBLE = 0x03, -} -impl SwLock23nsec { - #[inline(always)] - pub const fn from_bits(val: u8) -> SwLock23nsec { - unsafe { core::mem::transmute(val & 0x03) } - } - #[inline(always)] - pub const fn to_bits(self) -> u8 { - unsafe { core::mem::transmute(self) } - } -} -impl From for SwLock23nsec { - #[inline(always)] - fn from(val: u8) -> SwLock23nsec { - SwLock23nsec::from_bits(val) - } -} -impl From for u8 { - #[inline(always)] - fn from(val: SwLock23nsec) -> u8 { - SwLock23nsec::to_bits(val) - } -} -#[repr(u8)] -#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] -pub enum SwLock23sec { - READ_WRITE = 0, - READ_ONLY = 0x01, - _RESERVED_2 = 0x02, - INACCESSIBLE = 0x03, -} -impl SwLock23sec { - #[inline(always)] - pub const fn from_bits(val: u8) -> SwLock23sec { - unsafe { core::mem::transmute(val & 0x03) } - } - #[inline(always)] - pub const fn to_bits(self) -> u8 { - unsafe { core::mem::transmute(self) } - } -} -impl From for SwLock23sec { - #[inline(always)] - fn from(val: u8) -> SwLock23sec { - SwLock23sec::from_bits(val) - } -} -impl From for u8 { - #[inline(always)] - fn from(val: SwLock23sec) -> u8 { - SwLock23sec::to_bits(val) - } -} -#[repr(u8)] -#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] -pub enum SwLock24nsec { - READ_WRITE = 0, - READ_ONLY = 0x01, - _RESERVED_2 = 0x02, - INACCESSIBLE = 0x03, -} -impl SwLock24nsec { - #[inline(always)] - pub const fn from_bits(val: u8) -> SwLock24nsec { - unsafe { core::mem::transmute(val & 0x03) } - } - #[inline(always)] - pub const fn to_bits(self) -> u8 { - unsafe { core::mem::transmute(self) } - } -} -impl From for SwLock24nsec { - #[inline(always)] - fn from(val: u8) -> SwLock24nsec { - SwLock24nsec::from_bits(val) - } -} -impl From for u8 { - #[inline(always)] - fn from(val: SwLock24nsec) -> u8 { - SwLock24nsec::to_bits(val) - } -} -#[repr(u8)] -#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] -pub enum SwLock24sec { - READ_WRITE = 0, - READ_ONLY = 0x01, - _RESERVED_2 = 0x02, - INACCESSIBLE = 0x03, -} -impl SwLock24sec { - #[inline(always)] - pub const fn from_bits(val: u8) -> SwLock24sec { - unsafe { core::mem::transmute(val & 0x03) } - } - #[inline(always)] - pub const fn to_bits(self) -> u8 { - unsafe { core::mem::transmute(self) } - } -} -impl From for SwLock24sec { - #[inline(always)] - fn from(val: u8) -> SwLock24sec { - SwLock24sec::from_bits(val) - } -} -impl From for u8 { - #[inline(always)] - fn from(val: SwLock24sec) -> u8 { - SwLock24sec::to_bits(val) - } -} -#[repr(u8)] -#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] -pub enum SwLock25nsec { - READ_WRITE = 0, - READ_ONLY = 0x01, - _RESERVED_2 = 0x02, - INACCESSIBLE = 0x03, -} -impl SwLock25nsec { - #[inline(always)] - pub const fn from_bits(val: u8) -> SwLock25nsec { - unsafe { core::mem::transmute(val & 0x03) } - } - #[inline(always)] - pub const fn to_bits(self) -> u8 { - unsafe { core::mem::transmute(self) } - } -} -impl From for SwLock25nsec { - #[inline(always)] - fn from(val: u8) -> SwLock25nsec { - SwLock25nsec::from_bits(val) - } -} -impl From for u8 { - #[inline(always)] - fn from(val: SwLock25nsec) -> u8 { - SwLock25nsec::to_bits(val) - } -} -#[repr(u8)] -#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] -pub enum SwLock25sec { - READ_WRITE = 0, - READ_ONLY = 0x01, - _RESERVED_2 = 0x02, - INACCESSIBLE = 0x03, -} -impl SwLock25sec { - #[inline(always)] - pub const fn from_bits(val: u8) -> SwLock25sec { - unsafe { core::mem::transmute(val & 0x03) } - } - #[inline(always)] - pub const fn to_bits(self) -> u8 { - unsafe { core::mem::transmute(self) } - } -} -impl From for SwLock25sec { - #[inline(always)] - fn from(val: u8) -> SwLock25sec { - SwLock25sec::from_bits(val) - } -} -impl From for u8 { - #[inline(always)] - fn from(val: SwLock25sec) -> u8 { - SwLock25sec::to_bits(val) - } -} -#[repr(u8)] -#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] -pub enum SwLock26nsec { - READ_WRITE = 0, - READ_ONLY = 0x01, - _RESERVED_2 = 0x02, - INACCESSIBLE = 0x03, -} -impl SwLock26nsec { - #[inline(always)] - pub const fn from_bits(val: u8) -> SwLock26nsec { - unsafe { core::mem::transmute(val & 0x03) } - } - #[inline(always)] - pub const fn to_bits(self) -> u8 { - unsafe { core::mem::transmute(self) } - } -} -impl From for SwLock26nsec { - #[inline(always)] - fn from(val: u8) -> SwLock26nsec { - SwLock26nsec::from_bits(val) - } -} -impl From for u8 { - #[inline(always)] - fn from(val: SwLock26nsec) -> u8 { - SwLock26nsec::to_bits(val) - } -} -#[repr(u8)] -#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] -pub enum SwLock26sec { - READ_WRITE = 0, - READ_ONLY = 0x01, - _RESERVED_2 = 0x02, - INACCESSIBLE = 0x03, -} -impl SwLock26sec { - #[inline(always)] - pub const fn from_bits(val: u8) -> SwLock26sec { - unsafe { core::mem::transmute(val & 0x03) } - } - #[inline(always)] - pub const fn to_bits(self) -> u8 { - unsafe { core::mem::transmute(self) } - } -} -impl From for SwLock26sec { - #[inline(always)] - fn from(val: u8) -> SwLock26sec { - SwLock26sec::from_bits(val) - } -} -impl From for u8 { - #[inline(always)] - fn from(val: SwLock26sec) -> u8 { - SwLock26sec::to_bits(val) - } -} -#[repr(u8)] -#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] -pub enum SwLock27nsec { - READ_WRITE = 0, - READ_ONLY = 0x01, - _RESERVED_2 = 0x02, - INACCESSIBLE = 0x03, -} -impl SwLock27nsec { - #[inline(always)] - pub const fn from_bits(val: u8) -> SwLock27nsec { - unsafe { core::mem::transmute(val & 0x03) } - } - #[inline(always)] - pub const fn to_bits(self) -> u8 { - unsafe { core::mem::transmute(self) } - } -} -impl From for SwLock27nsec { - #[inline(always)] - fn from(val: u8) -> SwLock27nsec { - SwLock27nsec::from_bits(val) - } -} -impl From for u8 { - #[inline(always)] - fn from(val: SwLock27nsec) -> u8 { - SwLock27nsec::to_bits(val) - } -} -#[repr(u8)] -#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] -pub enum SwLock27sec { - READ_WRITE = 0, - READ_ONLY = 0x01, - _RESERVED_2 = 0x02, - INACCESSIBLE = 0x03, -} -impl SwLock27sec { - #[inline(always)] - pub const fn from_bits(val: u8) -> SwLock27sec { - unsafe { core::mem::transmute(val & 0x03) } - } - #[inline(always)] - pub const fn to_bits(self) -> u8 { - unsafe { core::mem::transmute(self) } - } -} -impl From for SwLock27sec { - #[inline(always)] - fn from(val: u8) -> SwLock27sec { - SwLock27sec::from_bits(val) - } -} -impl From for u8 { - #[inline(always)] - fn from(val: SwLock27sec) -> u8 { - SwLock27sec::to_bits(val) - } -} -#[repr(u8)] -#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] -pub enum SwLock28nsec { - READ_WRITE = 0, - READ_ONLY = 0x01, - _RESERVED_2 = 0x02, - INACCESSIBLE = 0x03, -} -impl SwLock28nsec { - #[inline(always)] - pub const fn from_bits(val: u8) -> SwLock28nsec { - unsafe { core::mem::transmute(val & 0x03) } - } - #[inline(always)] - pub const fn to_bits(self) -> u8 { - unsafe { core::mem::transmute(self) } - } -} -impl From for SwLock28nsec { - #[inline(always)] - fn from(val: u8) -> SwLock28nsec { - SwLock28nsec::from_bits(val) - } -} -impl From for u8 { - #[inline(always)] - fn from(val: SwLock28nsec) -> u8 { - SwLock28nsec::to_bits(val) - } -} -#[repr(u8)] -#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] -pub enum SwLock28sec { - READ_WRITE = 0, - READ_ONLY = 0x01, - _RESERVED_2 = 0x02, - INACCESSIBLE = 0x03, -} -impl SwLock28sec { - #[inline(always)] - pub const fn from_bits(val: u8) -> SwLock28sec { - unsafe { core::mem::transmute(val & 0x03) } - } - #[inline(always)] - pub const fn to_bits(self) -> u8 { - unsafe { core::mem::transmute(self) } - } -} -impl From for SwLock28sec { - #[inline(always)] - fn from(val: u8) -> SwLock28sec { - SwLock28sec::from_bits(val) - } -} -impl From for u8 { - #[inline(always)] - fn from(val: SwLock28sec) -> u8 { - SwLock28sec::to_bits(val) - } -} -#[repr(u8)] -#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] -pub enum SwLock29nsec { - READ_WRITE = 0, - READ_ONLY = 0x01, - _RESERVED_2 = 0x02, - INACCESSIBLE = 0x03, -} -impl SwLock29nsec { - #[inline(always)] - pub const fn from_bits(val: u8) -> SwLock29nsec { - unsafe { core::mem::transmute(val & 0x03) } - } - #[inline(always)] - pub const fn to_bits(self) -> u8 { - unsafe { core::mem::transmute(self) } - } -} -impl From for SwLock29nsec { - #[inline(always)] - fn from(val: u8) -> SwLock29nsec { - SwLock29nsec::from_bits(val) - } -} -impl From for u8 { - #[inline(always)] - fn from(val: SwLock29nsec) -> u8 { - SwLock29nsec::to_bits(val) - } -} -#[repr(u8)] -#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] -pub enum SwLock29sec { - READ_WRITE = 0, - READ_ONLY = 0x01, - _RESERVED_2 = 0x02, - INACCESSIBLE = 0x03, -} -impl SwLock29sec { - #[inline(always)] - pub const fn from_bits(val: u8) -> SwLock29sec { - unsafe { core::mem::transmute(val & 0x03) } - } - #[inline(always)] - pub const fn to_bits(self) -> u8 { - unsafe { core::mem::transmute(self) } - } -} -impl From for SwLock29sec { - #[inline(always)] - fn from(val: u8) -> SwLock29sec { - SwLock29sec::from_bits(val) - } -} -impl From for u8 { - #[inline(always)] - fn from(val: SwLock29sec) -> u8 { - SwLock29sec::to_bits(val) - } -} -#[repr(u8)] -#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] -pub enum SwLock2nsec { - READ_WRITE = 0, - READ_ONLY = 0x01, - _RESERVED_2 = 0x02, - INACCESSIBLE = 0x03, -} -impl SwLock2nsec { - #[inline(always)] - pub const fn from_bits(val: u8) -> SwLock2nsec { - unsafe { core::mem::transmute(val & 0x03) } - } - #[inline(always)] - pub const fn to_bits(self) -> u8 { - unsafe { core::mem::transmute(self) } - } -} -impl From for SwLock2nsec { - #[inline(always)] - fn from(val: u8) -> SwLock2nsec { - SwLock2nsec::from_bits(val) - } -} -impl From for u8 { - #[inline(always)] - fn from(val: SwLock2nsec) -> u8 { - SwLock2nsec::to_bits(val) - } -} -#[repr(u8)] -#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] -pub enum SwLock2sec { - READ_WRITE = 0, - READ_ONLY = 0x01, - _RESERVED_2 = 0x02, - INACCESSIBLE = 0x03, -} -impl SwLock2sec { - #[inline(always)] - pub const fn from_bits(val: u8) -> SwLock2sec { - unsafe { core::mem::transmute(val & 0x03) } - } - #[inline(always)] - pub const fn to_bits(self) -> u8 { - unsafe { core::mem::transmute(self) } - } -} -impl From for SwLock2sec { - #[inline(always)] - fn from(val: u8) -> SwLock2sec { - SwLock2sec::from_bits(val) - } -} -impl From for u8 { - #[inline(always)] - fn from(val: SwLock2sec) -> u8 { - SwLock2sec::to_bits(val) - } -} -#[repr(u8)] -#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] -pub enum SwLock30nsec { - READ_WRITE = 0, - READ_ONLY = 0x01, - _RESERVED_2 = 0x02, - INACCESSIBLE = 0x03, -} -impl SwLock30nsec { - #[inline(always)] - pub const fn from_bits(val: u8) -> SwLock30nsec { - unsafe { core::mem::transmute(val & 0x03) } - } - #[inline(always)] - pub const fn to_bits(self) -> u8 { - unsafe { core::mem::transmute(self) } - } -} -impl From for SwLock30nsec { - #[inline(always)] - fn from(val: u8) -> SwLock30nsec { - SwLock30nsec::from_bits(val) - } -} -impl From for u8 { - #[inline(always)] - fn from(val: SwLock30nsec) -> u8 { - SwLock30nsec::to_bits(val) - } -} -#[repr(u8)] -#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] -pub enum SwLock30sec { - READ_WRITE = 0, - READ_ONLY = 0x01, - _RESERVED_2 = 0x02, - INACCESSIBLE = 0x03, -} -impl SwLock30sec { - #[inline(always)] - pub const fn from_bits(val: u8) -> SwLock30sec { - unsafe { core::mem::transmute(val & 0x03) } - } - #[inline(always)] - pub const fn to_bits(self) -> u8 { - unsafe { core::mem::transmute(self) } - } -} -impl From for SwLock30sec { - #[inline(always)] - fn from(val: u8) -> SwLock30sec { - SwLock30sec::from_bits(val) - } -} -impl From for u8 { - #[inline(always)] - fn from(val: SwLock30sec) -> u8 { - SwLock30sec::to_bits(val) - } -} -#[repr(u8)] -#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] -pub enum SwLock31nsec { - READ_WRITE = 0, - READ_ONLY = 0x01, - _RESERVED_2 = 0x02, - INACCESSIBLE = 0x03, -} -impl SwLock31nsec { - #[inline(always)] - pub const fn from_bits(val: u8) -> SwLock31nsec { - unsafe { core::mem::transmute(val & 0x03) } - } - #[inline(always)] - pub const fn to_bits(self) -> u8 { - unsafe { core::mem::transmute(self) } - } -} -impl From for SwLock31nsec { - #[inline(always)] - fn from(val: u8) -> SwLock31nsec { - SwLock31nsec::from_bits(val) - } -} -impl From for u8 { - #[inline(always)] - fn from(val: SwLock31nsec) -> u8 { - SwLock31nsec::to_bits(val) - } -} -#[repr(u8)] -#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] -pub enum SwLock31sec { - READ_WRITE = 0, - READ_ONLY = 0x01, - _RESERVED_2 = 0x02, - INACCESSIBLE = 0x03, -} -impl SwLock31sec { - #[inline(always)] - pub const fn from_bits(val: u8) -> SwLock31sec { - unsafe { core::mem::transmute(val & 0x03) } - } - #[inline(always)] - pub const fn to_bits(self) -> u8 { - unsafe { core::mem::transmute(self) } - } -} -impl From for SwLock31sec { - #[inline(always)] - fn from(val: u8) -> SwLock31sec { - SwLock31sec::from_bits(val) - } -} -impl From for u8 { - #[inline(always)] - fn from(val: SwLock31sec) -> u8 { - SwLock31sec::to_bits(val) - } -} -#[repr(u8)] -#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] -pub enum SwLock32nsec { - READ_WRITE = 0, - READ_ONLY = 0x01, - _RESERVED_2 = 0x02, - INACCESSIBLE = 0x03, -} -impl SwLock32nsec { - #[inline(always)] - pub const fn from_bits(val: u8) -> SwLock32nsec { - unsafe { core::mem::transmute(val & 0x03) } - } - #[inline(always)] - pub const fn to_bits(self) -> u8 { - unsafe { core::mem::transmute(self) } - } -} -impl From for SwLock32nsec { - #[inline(always)] - fn from(val: u8) -> SwLock32nsec { - SwLock32nsec::from_bits(val) - } -} -impl From for u8 { - #[inline(always)] - fn from(val: SwLock32nsec) -> u8 { - SwLock32nsec::to_bits(val) - } -} -#[repr(u8)] -#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] -pub enum SwLock32sec { - READ_WRITE = 0, - READ_ONLY = 0x01, - _RESERVED_2 = 0x02, - INACCESSIBLE = 0x03, -} -impl SwLock32sec { - #[inline(always)] - pub const fn from_bits(val: u8) -> SwLock32sec { - unsafe { core::mem::transmute(val & 0x03) } - } - #[inline(always)] - pub const fn to_bits(self) -> u8 { - unsafe { core::mem::transmute(self) } - } -} -impl From for SwLock32sec { - #[inline(always)] - fn from(val: u8) -> SwLock32sec { - SwLock32sec::from_bits(val) - } -} -impl From for u8 { - #[inline(always)] - fn from(val: SwLock32sec) -> u8 { - SwLock32sec::to_bits(val) - } -} -#[repr(u8)] -#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] -pub enum SwLock33nsec { - READ_WRITE = 0, - READ_ONLY = 0x01, - _RESERVED_2 = 0x02, - INACCESSIBLE = 0x03, -} -impl SwLock33nsec { - #[inline(always)] - pub const fn from_bits(val: u8) -> SwLock33nsec { - unsafe { core::mem::transmute(val & 0x03) } - } - #[inline(always)] - pub const fn to_bits(self) -> u8 { - unsafe { core::mem::transmute(self) } - } -} -impl From for SwLock33nsec { - #[inline(always)] - fn from(val: u8) -> SwLock33nsec { - SwLock33nsec::from_bits(val) - } -} -impl From for u8 { - #[inline(always)] - fn from(val: SwLock33nsec) -> u8 { - SwLock33nsec::to_bits(val) - } -} -#[repr(u8)] -#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] -pub enum SwLock33sec { - READ_WRITE = 0, - READ_ONLY = 0x01, - _RESERVED_2 = 0x02, - INACCESSIBLE = 0x03, -} -impl SwLock33sec { - #[inline(always)] - pub const fn from_bits(val: u8) -> SwLock33sec { - unsafe { core::mem::transmute(val & 0x03) } - } - #[inline(always)] - pub const fn to_bits(self) -> u8 { - unsafe { core::mem::transmute(self) } - } -} -impl From for SwLock33sec { - #[inline(always)] - fn from(val: u8) -> SwLock33sec { - SwLock33sec::from_bits(val) - } -} -impl From for u8 { - #[inline(always)] - fn from(val: SwLock33sec) -> u8 { - SwLock33sec::to_bits(val) - } -} -#[repr(u8)] -#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] -pub enum SwLock34nsec { - READ_WRITE = 0, - READ_ONLY = 0x01, - _RESERVED_2 = 0x02, - INACCESSIBLE = 0x03, -} -impl SwLock34nsec { - #[inline(always)] - pub const fn from_bits(val: u8) -> SwLock34nsec { - unsafe { core::mem::transmute(val & 0x03) } - } - #[inline(always)] - pub const fn to_bits(self) -> u8 { - unsafe { core::mem::transmute(self) } - } -} -impl From for SwLock34nsec { - #[inline(always)] - fn from(val: u8) -> SwLock34nsec { - SwLock34nsec::from_bits(val) - } -} -impl From for u8 { - #[inline(always)] - fn from(val: SwLock34nsec) -> u8 { - SwLock34nsec::to_bits(val) - } -} -#[repr(u8)] -#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] -pub enum SwLock34sec { - READ_WRITE = 0, - READ_ONLY = 0x01, - _RESERVED_2 = 0x02, - INACCESSIBLE = 0x03, -} -impl SwLock34sec { - #[inline(always)] - pub const fn from_bits(val: u8) -> SwLock34sec { - unsafe { core::mem::transmute(val & 0x03) } - } - #[inline(always)] - pub const fn to_bits(self) -> u8 { - unsafe { core::mem::transmute(self) } - } -} -impl From for SwLock34sec { - #[inline(always)] - fn from(val: u8) -> SwLock34sec { - SwLock34sec::from_bits(val) - } -} -impl From for u8 { - #[inline(always)] - fn from(val: SwLock34sec) -> u8 { - SwLock34sec::to_bits(val) - } -} -#[repr(u8)] -#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] -pub enum SwLock35nsec { - READ_WRITE = 0, - READ_ONLY = 0x01, - _RESERVED_2 = 0x02, - INACCESSIBLE = 0x03, -} -impl SwLock35nsec { - #[inline(always)] - pub const fn from_bits(val: u8) -> SwLock35nsec { - unsafe { core::mem::transmute(val & 0x03) } - } - #[inline(always)] - pub const fn to_bits(self) -> u8 { - unsafe { core::mem::transmute(self) } - } -} -impl From for SwLock35nsec { - #[inline(always)] - fn from(val: u8) -> SwLock35nsec { - SwLock35nsec::from_bits(val) - } -} -impl From for u8 { - #[inline(always)] - fn from(val: SwLock35nsec) -> u8 { - SwLock35nsec::to_bits(val) - } -} -#[repr(u8)] -#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] -pub enum SwLock35sec { - READ_WRITE = 0, - READ_ONLY = 0x01, - _RESERVED_2 = 0x02, - INACCESSIBLE = 0x03, -} -impl SwLock35sec { - #[inline(always)] - pub const fn from_bits(val: u8) -> SwLock35sec { - unsafe { core::mem::transmute(val & 0x03) } - } - #[inline(always)] - pub const fn to_bits(self) -> u8 { - unsafe { core::mem::transmute(self) } - } -} -impl From for SwLock35sec { - #[inline(always)] - fn from(val: u8) -> SwLock35sec { - SwLock35sec::from_bits(val) - } -} -impl From for u8 { - #[inline(always)] - fn from(val: SwLock35sec) -> u8 { - SwLock35sec::to_bits(val) - } -} -#[repr(u8)] -#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] -pub enum SwLock36nsec { - READ_WRITE = 0, - READ_ONLY = 0x01, - _RESERVED_2 = 0x02, - INACCESSIBLE = 0x03, -} -impl SwLock36nsec { - #[inline(always)] - pub const fn from_bits(val: u8) -> SwLock36nsec { - unsafe { core::mem::transmute(val & 0x03) } - } - #[inline(always)] - pub const fn to_bits(self) -> u8 { - unsafe { core::mem::transmute(self) } - } -} -impl From for SwLock36nsec { - #[inline(always)] - fn from(val: u8) -> SwLock36nsec { - SwLock36nsec::from_bits(val) - } -} -impl From for u8 { - #[inline(always)] - fn from(val: SwLock36nsec) -> u8 { - SwLock36nsec::to_bits(val) - } -} -#[repr(u8)] -#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] -pub enum SwLock36sec { - READ_WRITE = 0, - READ_ONLY = 0x01, - _RESERVED_2 = 0x02, - INACCESSIBLE = 0x03, -} -impl SwLock36sec { - #[inline(always)] - pub const fn from_bits(val: u8) -> SwLock36sec { - unsafe { core::mem::transmute(val & 0x03) } - } - #[inline(always)] - pub const fn to_bits(self) -> u8 { - unsafe { core::mem::transmute(self) } - } -} -impl From for SwLock36sec { - #[inline(always)] - fn from(val: u8) -> SwLock36sec { - SwLock36sec::from_bits(val) - } -} -impl From for u8 { - #[inline(always)] - fn from(val: SwLock36sec) -> u8 { - SwLock36sec::to_bits(val) - } -} -#[repr(u8)] -#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] -pub enum SwLock37nsec { - READ_WRITE = 0, - READ_ONLY = 0x01, - _RESERVED_2 = 0x02, - INACCESSIBLE = 0x03, -} -impl SwLock37nsec { - #[inline(always)] - pub const fn from_bits(val: u8) -> SwLock37nsec { - unsafe { core::mem::transmute(val & 0x03) } - } - #[inline(always)] - pub const fn to_bits(self) -> u8 { - unsafe { core::mem::transmute(self) } - } -} -impl From for SwLock37nsec { - #[inline(always)] - fn from(val: u8) -> SwLock37nsec { - SwLock37nsec::from_bits(val) - } -} -impl From for u8 { - #[inline(always)] - fn from(val: SwLock37nsec) -> u8 { - SwLock37nsec::to_bits(val) - } -} -#[repr(u8)] -#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] -pub enum SwLock37sec { - READ_WRITE = 0, - READ_ONLY = 0x01, - _RESERVED_2 = 0x02, - INACCESSIBLE = 0x03, -} -impl SwLock37sec { - #[inline(always)] - pub const fn from_bits(val: u8) -> SwLock37sec { - unsafe { core::mem::transmute(val & 0x03) } - } - #[inline(always)] - pub const fn to_bits(self) -> u8 { - unsafe { core::mem::transmute(self) } - } -} -impl From for SwLock37sec { - #[inline(always)] - fn from(val: u8) -> SwLock37sec { - SwLock37sec::from_bits(val) - } -} -impl From for u8 { - #[inline(always)] - fn from(val: SwLock37sec) -> u8 { - SwLock37sec::to_bits(val) - } -} -#[repr(u8)] -#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] -pub enum SwLock38nsec { - READ_WRITE = 0, - READ_ONLY = 0x01, - _RESERVED_2 = 0x02, - INACCESSIBLE = 0x03, -} -impl SwLock38nsec { - #[inline(always)] - pub const fn from_bits(val: u8) -> SwLock38nsec { - unsafe { core::mem::transmute(val & 0x03) } - } - #[inline(always)] - pub const fn to_bits(self) -> u8 { - unsafe { core::mem::transmute(self) } - } -} -impl From for SwLock38nsec { - #[inline(always)] - fn from(val: u8) -> SwLock38nsec { - SwLock38nsec::from_bits(val) - } -} -impl From for u8 { - #[inline(always)] - fn from(val: SwLock38nsec) -> u8 { - SwLock38nsec::to_bits(val) - } -} -#[repr(u8)] -#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] -pub enum SwLock38sec { - READ_WRITE = 0, - READ_ONLY = 0x01, - _RESERVED_2 = 0x02, - INACCESSIBLE = 0x03, -} -impl SwLock38sec { - #[inline(always)] - pub const fn from_bits(val: u8) -> SwLock38sec { - unsafe { core::mem::transmute(val & 0x03) } - } - #[inline(always)] - pub const fn to_bits(self) -> u8 { - unsafe { core::mem::transmute(self) } - } -} -impl From for SwLock38sec { - #[inline(always)] - fn from(val: u8) -> SwLock38sec { - SwLock38sec::from_bits(val) - } -} -impl From for u8 { - #[inline(always)] - fn from(val: SwLock38sec) -> u8 { - SwLock38sec::to_bits(val) - } -} -#[repr(u8)] -#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] -pub enum SwLock39nsec { - READ_WRITE = 0, - READ_ONLY = 0x01, - _RESERVED_2 = 0x02, - INACCESSIBLE = 0x03, -} -impl SwLock39nsec { - #[inline(always)] - pub const fn from_bits(val: u8) -> SwLock39nsec { - unsafe { core::mem::transmute(val & 0x03) } - } - #[inline(always)] - pub const fn to_bits(self) -> u8 { - unsafe { core::mem::transmute(self) } - } -} -impl From for SwLock39nsec { - #[inline(always)] - fn from(val: u8) -> SwLock39nsec { - SwLock39nsec::from_bits(val) - } -} -impl From for u8 { - #[inline(always)] - fn from(val: SwLock39nsec) -> u8 { - SwLock39nsec::to_bits(val) - } -} -#[repr(u8)] -#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] -pub enum SwLock39sec { - READ_WRITE = 0, - READ_ONLY = 0x01, - _RESERVED_2 = 0x02, - INACCESSIBLE = 0x03, -} -impl SwLock39sec { - #[inline(always)] - pub const fn from_bits(val: u8) -> SwLock39sec { - unsafe { core::mem::transmute(val & 0x03) } - } - #[inline(always)] - pub const fn to_bits(self) -> u8 { - unsafe { core::mem::transmute(self) } - } -} -impl From for SwLock39sec { - #[inline(always)] - fn from(val: u8) -> SwLock39sec { - SwLock39sec::from_bits(val) - } -} -impl From for u8 { - #[inline(always)] - fn from(val: SwLock39sec) -> u8 { - SwLock39sec::to_bits(val) - } -} -#[repr(u8)] -#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] -pub enum SwLock3nsec { - READ_WRITE = 0, - READ_ONLY = 0x01, - _RESERVED_2 = 0x02, - INACCESSIBLE = 0x03, -} -impl SwLock3nsec { - #[inline(always)] - pub const fn from_bits(val: u8) -> SwLock3nsec { - unsafe { core::mem::transmute(val & 0x03) } - } - #[inline(always)] - pub const fn to_bits(self) -> u8 { - unsafe { core::mem::transmute(self) } - } -} -impl From for SwLock3nsec { - #[inline(always)] - fn from(val: u8) -> SwLock3nsec { - SwLock3nsec::from_bits(val) - } -} -impl From for u8 { - #[inline(always)] - fn from(val: SwLock3nsec) -> u8 { - SwLock3nsec::to_bits(val) - } -} -#[repr(u8)] -#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] -pub enum SwLock3sec { - READ_WRITE = 0, - READ_ONLY = 0x01, - _RESERVED_2 = 0x02, - INACCESSIBLE = 0x03, -} -impl SwLock3sec { - #[inline(always)] - pub const fn from_bits(val: u8) -> SwLock3sec { - unsafe { core::mem::transmute(val & 0x03) } - } - #[inline(always)] - pub const fn to_bits(self) -> u8 { - unsafe { core::mem::transmute(self) } - } -} -impl From for SwLock3sec { - #[inline(always)] - fn from(val: u8) -> SwLock3sec { - SwLock3sec::from_bits(val) - } -} -impl From for u8 { - #[inline(always)] - fn from(val: SwLock3sec) -> u8 { - SwLock3sec::to_bits(val) - } -} -#[repr(u8)] -#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] -pub enum SwLock40nsec { - READ_WRITE = 0, - READ_ONLY = 0x01, - _RESERVED_2 = 0x02, - INACCESSIBLE = 0x03, -} -impl SwLock40nsec { - #[inline(always)] - pub const fn from_bits(val: u8) -> SwLock40nsec { - unsafe { core::mem::transmute(val & 0x03) } - } - #[inline(always)] - pub const fn to_bits(self) -> u8 { - unsafe { core::mem::transmute(self) } - } -} -impl From for SwLock40nsec { - #[inline(always)] - fn from(val: u8) -> SwLock40nsec { - SwLock40nsec::from_bits(val) - } -} -impl From for u8 { - #[inline(always)] - fn from(val: SwLock40nsec) -> u8 { - SwLock40nsec::to_bits(val) - } -} -#[repr(u8)] -#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] -pub enum SwLock40sec { - READ_WRITE = 0, - READ_ONLY = 0x01, - _RESERVED_2 = 0x02, - INACCESSIBLE = 0x03, -} -impl SwLock40sec { - #[inline(always)] - pub const fn from_bits(val: u8) -> SwLock40sec { - unsafe { core::mem::transmute(val & 0x03) } - } - #[inline(always)] - pub const fn to_bits(self) -> u8 { - unsafe { core::mem::transmute(self) } - } -} -impl From for SwLock40sec { - #[inline(always)] - fn from(val: u8) -> SwLock40sec { - SwLock40sec::from_bits(val) - } -} -impl From for u8 { - #[inline(always)] - fn from(val: SwLock40sec) -> u8 { - SwLock40sec::to_bits(val) - } -} -#[repr(u8)] -#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] -pub enum SwLock41nsec { - READ_WRITE = 0, - READ_ONLY = 0x01, - _RESERVED_2 = 0x02, - INACCESSIBLE = 0x03, -} -impl SwLock41nsec { - #[inline(always)] - pub const fn from_bits(val: u8) -> SwLock41nsec { - unsafe { core::mem::transmute(val & 0x03) } - } - #[inline(always)] - pub const fn to_bits(self) -> u8 { - unsafe { core::mem::transmute(self) } - } -} -impl From for SwLock41nsec { - #[inline(always)] - fn from(val: u8) -> SwLock41nsec { - SwLock41nsec::from_bits(val) - } -} -impl From for u8 { - #[inline(always)] - fn from(val: SwLock41nsec) -> u8 { - SwLock41nsec::to_bits(val) - } -} -#[repr(u8)] -#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] -pub enum SwLock41sec { - READ_WRITE = 0, - READ_ONLY = 0x01, - _RESERVED_2 = 0x02, - INACCESSIBLE = 0x03, -} -impl SwLock41sec { - #[inline(always)] - pub const fn from_bits(val: u8) -> SwLock41sec { - unsafe { core::mem::transmute(val & 0x03) } - } - #[inline(always)] - pub const fn to_bits(self) -> u8 { - unsafe { core::mem::transmute(self) } - } -} -impl From for SwLock41sec { - #[inline(always)] - fn from(val: u8) -> SwLock41sec { - SwLock41sec::from_bits(val) - } -} -impl From for u8 { - #[inline(always)] - fn from(val: SwLock41sec) -> u8 { - SwLock41sec::to_bits(val) - } -} -#[repr(u8)] -#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] -pub enum SwLock42nsec { - READ_WRITE = 0, - READ_ONLY = 0x01, - _RESERVED_2 = 0x02, - INACCESSIBLE = 0x03, -} -impl SwLock42nsec { - #[inline(always)] - pub const fn from_bits(val: u8) -> SwLock42nsec { - unsafe { core::mem::transmute(val & 0x03) } - } - #[inline(always)] - pub const fn to_bits(self) -> u8 { - unsafe { core::mem::transmute(self) } - } -} -impl From for SwLock42nsec { - #[inline(always)] - fn from(val: u8) -> SwLock42nsec { - SwLock42nsec::from_bits(val) - } -} -impl From for u8 { - #[inline(always)] - fn from(val: SwLock42nsec) -> u8 { - SwLock42nsec::to_bits(val) - } -} -#[repr(u8)] -#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] -pub enum SwLock42sec { - READ_WRITE = 0, - READ_ONLY = 0x01, - _RESERVED_2 = 0x02, - INACCESSIBLE = 0x03, -} -impl SwLock42sec { - #[inline(always)] - pub const fn from_bits(val: u8) -> SwLock42sec { - unsafe { core::mem::transmute(val & 0x03) } - } - #[inline(always)] - pub const fn to_bits(self) -> u8 { - unsafe { core::mem::transmute(self) } - } -} -impl From for SwLock42sec { - #[inline(always)] - fn from(val: u8) -> SwLock42sec { - SwLock42sec::from_bits(val) - } -} -impl From for u8 { - #[inline(always)] - fn from(val: SwLock42sec) -> u8 { - SwLock42sec::to_bits(val) - } -} -#[repr(u8)] -#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] -pub enum SwLock43nsec { - READ_WRITE = 0, - READ_ONLY = 0x01, - _RESERVED_2 = 0x02, - INACCESSIBLE = 0x03, -} -impl SwLock43nsec { - #[inline(always)] - pub const fn from_bits(val: u8) -> SwLock43nsec { - unsafe { core::mem::transmute(val & 0x03) } - } - #[inline(always)] - pub const fn to_bits(self) -> u8 { - unsafe { core::mem::transmute(self) } - } -} -impl From for SwLock43nsec { - #[inline(always)] - fn from(val: u8) -> SwLock43nsec { - SwLock43nsec::from_bits(val) - } -} -impl From for u8 { - #[inline(always)] - fn from(val: SwLock43nsec) -> u8 { - SwLock43nsec::to_bits(val) - } -} -#[repr(u8)] -#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] -pub enum SwLock43sec { - READ_WRITE = 0, - READ_ONLY = 0x01, - _RESERVED_2 = 0x02, - INACCESSIBLE = 0x03, -} -impl SwLock43sec { - #[inline(always)] - pub const fn from_bits(val: u8) -> SwLock43sec { - unsafe { core::mem::transmute(val & 0x03) } - } - #[inline(always)] - pub const fn to_bits(self) -> u8 { - unsafe { core::mem::transmute(self) } - } -} -impl From for SwLock43sec { - #[inline(always)] - fn from(val: u8) -> SwLock43sec { - SwLock43sec::from_bits(val) - } -} -impl From for u8 { - #[inline(always)] - fn from(val: SwLock43sec) -> u8 { - SwLock43sec::to_bits(val) - } -} -#[repr(u8)] -#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] -pub enum SwLock44nsec { - READ_WRITE = 0, - READ_ONLY = 0x01, - _RESERVED_2 = 0x02, - INACCESSIBLE = 0x03, -} -impl SwLock44nsec { - #[inline(always)] - pub const fn from_bits(val: u8) -> SwLock44nsec { - unsafe { core::mem::transmute(val & 0x03) } - } - #[inline(always)] - pub const fn to_bits(self) -> u8 { - unsafe { core::mem::transmute(self) } - } -} -impl From for SwLock44nsec { - #[inline(always)] - fn from(val: u8) -> SwLock44nsec { - SwLock44nsec::from_bits(val) - } -} -impl From for u8 { - #[inline(always)] - fn from(val: SwLock44nsec) -> u8 { - SwLock44nsec::to_bits(val) - } -} -#[repr(u8)] -#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] -pub enum SwLock44sec { - READ_WRITE = 0, - READ_ONLY = 0x01, - _RESERVED_2 = 0x02, - INACCESSIBLE = 0x03, -} -impl SwLock44sec { - #[inline(always)] - pub const fn from_bits(val: u8) -> SwLock44sec { - unsafe { core::mem::transmute(val & 0x03) } - } - #[inline(always)] - pub const fn to_bits(self) -> u8 { - unsafe { core::mem::transmute(self) } - } -} -impl From for SwLock44sec { - #[inline(always)] - fn from(val: u8) -> SwLock44sec { - SwLock44sec::from_bits(val) - } -} -impl From for u8 { - #[inline(always)] - fn from(val: SwLock44sec) -> u8 { - SwLock44sec::to_bits(val) - } -} -#[repr(u8)] -#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] -pub enum SwLock45nsec { - READ_WRITE = 0, - READ_ONLY = 0x01, - _RESERVED_2 = 0x02, - INACCESSIBLE = 0x03, -} -impl SwLock45nsec { - #[inline(always)] - pub const fn from_bits(val: u8) -> SwLock45nsec { - unsafe { core::mem::transmute(val & 0x03) } - } - #[inline(always)] - pub const fn to_bits(self) -> u8 { - unsafe { core::mem::transmute(self) } - } -} -impl From for SwLock45nsec { - #[inline(always)] - fn from(val: u8) -> SwLock45nsec { - SwLock45nsec::from_bits(val) - } -} -impl From for u8 { - #[inline(always)] - fn from(val: SwLock45nsec) -> u8 { - SwLock45nsec::to_bits(val) - } -} -#[repr(u8)] -#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] -pub enum SwLock45sec { - READ_WRITE = 0, - READ_ONLY = 0x01, - _RESERVED_2 = 0x02, - INACCESSIBLE = 0x03, -} -impl SwLock45sec { - #[inline(always)] - pub const fn from_bits(val: u8) -> SwLock45sec { - unsafe { core::mem::transmute(val & 0x03) } - } - #[inline(always)] - pub const fn to_bits(self) -> u8 { - unsafe { core::mem::transmute(self) } - } -} -impl From for SwLock45sec { - #[inline(always)] - fn from(val: u8) -> SwLock45sec { - SwLock45sec::from_bits(val) - } -} -impl From for u8 { - #[inline(always)] - fn from(val: SwLock45sec) -> u8 { - SwLock45sec::to_bits(val) - } -} -#[repr(u8)] -#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] -pub enum SwLock46nsec { - READ_WRITE = 0, - READ_ONLY = 0x01, - _RESERVED_2 = 0x02, - INACCESSIBLE = 0x03, -} -impl SwLock46nsec { - #[inline(always)] - pub const fn from_bits(val: u8) -> SwLock46nsec { - unsafe { core::mem::transmute(val & 0x03) } - } - #[inline(always)] - pub const fn to_bits(self) -> u8 { - unsafe { core::mem::transmute(self) } - } -} -impl From for SwLock46nsec { - #[inline(always)] - fn from(val: u8) -> SwLock46nsec { - SwLock46nsec::from_bits(val) - } -} -impl From for u8 { - #[inline(always)] - fn from(val: SwLock46nsec) -> u8 { - SwLock46nsec::to_bits(val) - } -} -#[repr(u8)] -#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] -pub enum SwLock46sec { - READ_WRITE = 0, - READ_ONLY = 0x01, - _RESERVED_2 = 0x02, - INACCESSIBLE = 0x03, -} -impl SwLock46sec { - #[inline(always)] - pub const fn from_bits(val: u8) -> SwLock46sec { - unsafe { core::mem::transmute(val & 0x03) } - } - #[inline(always)] - pub const fn to_bits(self) -> u8 { - unsafe { core::mem::transmute(self) } - } -} -impl From for SwLock46sec { - #[inline(always)] - fn from(val: u8) -> SwLock46sec { - SwLock46sec::from_bits(val) - } -} -impl From for u8 { - #[inline(always)] - fn from(val: SwLock46sec) -> u8 { - SwLock46sec::to_bits(val) - } -} -#[repr(u8)] -#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] -pub enum SwLock47nsec { - READ_WRITE = 0, - READ_ONLY = 0x01, - _RESERVED_2 = 0x02, - INACCESSIBLE = 0x03, -} -impl SwLock47nsec { - #[inline(always)] - pub const fn from_bits(val: u8) -> SwLock47nsec { - unsafe { core::mem::transmute(val & 0x03) } - } - #[inline(always)] - pub const fn to_bits(self) -> u8 { - unsafe { core::mem::transmute(self) } - } -} -impl From for SwLock47nsec { - #[inline(always)] - fn from(val: u8) -> SwLock47nsec { - SwLock47nsec::from_bits(val) - } -} -impl From for u8 { - #[inline(always)] - fn from(val: SwLock47nsec) -> u8 { - SwLock47nsec::to_bits(val) - } -} -#[repr(u8)] -#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] -pub enum SwLock47sec { - READ_WRITE = 0, - READ_ONLY = 0x01, - _RESERVED_2 = 0x02, - INACCESSIBLE = 0x03, -} -impl SwLock47sec { - #[inline(always)] - pub const fn from_bits(val: u8) -> SwLock47sec { - unsafe { core::mem::transmute(val & 0x03) } - } - #[inline(always)] - pub const fn to_bits(self) -> u8 { - unsafe { core::mem::transmute(self) } - } -} -impl From for SwLock47sec { - #[inline(always)] - fn from(val: u8) -> SwLock47sec { - SwLock47sec::from_bits(val) - } -} -impl From for u8 { - #[inline(always)] - fn from(val: SwLock47sec) -> u8 { - SwLock47sec::to_bits(val) - } -} -#[repr(u8)] -#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] -pub enum SwLock48nsec { - READ_WRITE = 0, - READ_ONLY = 0x01, - _RESERVED_2 = 0x02, - INACCESSIBLE = 0x03, -} -impl SwLock48nsec { - #[inline(always)] - pub const fn from_bits(val: u8) -> SwLock48nsec { - unsafe { core::mem::transmute(val & 0x03) } - } - #[inline(always)] - pub const fn to_bits(self) -> u8 { - unsafe { core::mem::transmute(self) } - } -} -impl From for SwLock48nsec { - #[inline(always)] - fn from(val: u8) -> SwLock48nsec { - SwLock48nsec::from_bits(val) - } -} -impl From for u8 { - #[inline(always)] - fn from(val: SwLock48nsec) -> u8 { - SwLock48nsec::to_bits(val) - } -} -#[repr(u8)] -#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] -pub enum SwLock48sec { - READ_WRITE = 0, - READ_ONLY = 0x01, - _RESERVED_2 = 0x02, - INACCESSIBLE = 0x03, -} -impl SwLock48sec { - #[inline(always)] - pub const fn from_bits(val: u8) -> SwLock48sec { - unsafe { core::mem::transmute(val & 0x03) } - } - #[inline(always)] - pub const fn to_bits(self) -> u8 { - unsafe { core::mem::transmute(self) } - } -} -impl From for SwLock48sec { - #[inline(always)] - fn from(val: u8) -> SwLock48sec { - SwLock48sec::from_bits(val) - } -} -impl From for u8 { - #[inline(always)] - fn from(val: SwLock48sec) -> u8 { - SwLock48sec::to_bits(val) - } -} -#[repr(u8)] -#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] -pub enum SwLock49nsec { - READ_WRITE = 0, - READ_ONLY = 0x01, - _RESERVED_2 = 0x02, - INACCESSIBLE = 0x03, -} -impl SwLock49nsec { - #[inline(always)] - pub const fn from_bits(val: u8) -> SwLock49nsec { - unsafe { core::mem::transmute(val & 0x03) } - } - #[inline(always)] - pub const fn to_bits(self) -> u8 { - unsafe { core::mem::transmute(self) } - } -} -impl From for SwLock49nsec { - #[inline(always)] - fn from(val: u8) -> SwLock49nsec { - SwLock49nsec::from_bits(val) - } -} -impl From for u8 { - #[inline(always)] - fn from(val: SwLock49nsec) -> u8 { - SwLock49nsec::to_bits(val) - } -} -#[repr(u8)] -#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] -pub enum SwLock49sec { - READ_WRITE = 0, - READ_ONLY = 0x01, - _RESERVED_2 = 0x02, - INACCESSIBLE = 0x03, -} -impl SwLock49sec { - #[inline(always)] - pub const fn from_bits(val: u8) -> SwLock49sec { - unsafe { core::mem::transmute(val & 0x03) } - } - #[inline(always)] - pub const fn to_bits(self) -> u8 { - unsafe { core::mem::transmute(self) } - } -} -impl From for SwLock49sec { - #[inline(always)] - fn from(val: u8) -> SwLock49sec { - SwLock49sec::from_bits(val) - } -} -impl From for u8 { - #[inline(always)] - fn from(val: SwLock49sec) -> u8 { - SwLock49sec::to_bits(val) - } -} -#[repr(u8)] -#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] -pub enum SwLock4nsec { - READ_WRITE = 0, - READ_ONLY = 0x01, - _RESERVED_2 = 0x02, - INACCESSIBLE = 0x03, -} -impl SwLock4nsec { - #[inline(always)] - pub const fn from_bits(val: u8) -> SwLock4nsec { - unsafe { core::mem::transmute(val & 0x03) } - } - #[inline(always)] - pub const fn to_bits(self) -> u8 { - unsafe { core::mem::transmute(self) } - } -} -impl From for SwLock4nsec { - #[inline(always)] - fn from(val: u8) -> SwLock4nsec { - SwLock4nsec::from_bits(val) - } -} -impl From for u8 { - #[inline(always)] - fn from(val: SwLock4nsec) -> u8 { - SwLock4nsec::to_bits(val) - } -} -#[repr(u8)] -#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] -pub enum SwLock4sec { - READ_WRITE = 0, - READ_ONLY = 0x01, - _RESERVED_2 = 0x02, - INACCESSIBLE = 0x03, -} -impl SwLock4sec { - #[inline(always)] - pub const fn from_bits(val: u8) -> SwLock4sec { - unsafe { core::mem::transmute(val & 0x03) } - } - #[inline(always)] - pub const fn to_bits(self) -> u8 { - unsafe { core::mem::transmute(self) } - } -} -impl From for SwLock4sec { - #[inline(always)] - fn from(val: u8) -> SwLock4sec { - SwLock4sec::from_bits(val) - } -} -impl From for u8 { - #[inline(always)] - fn from(val: SwLock4sec) -> u8 { - SwLock4sec::to_bits(val) - } -} -#[repr(u8)] -#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] -pub enum SwLock50nsec { - READ_WRITE = 0, - READ_ONLY = 0x01, - _RESERVED_2 = 0x02, - INACCESSIBLE = 0x03, -} -impl SwLock50nsec { - #[inline(always)] - pub const fn from_bits(val: u8) -> SwLock50nsec { - unsafe { core::mem::transmute(val & 0x03) } - } - #[inline(always)] - pub const fn to_bits(self) -> u8 { - unsafe { core::mem::transmute(self) } - } -} -impl From for SwLock50nsec { - #[inline(always)] - fn from(val: u8) -> SwLock50nsec { - SwLock50nsec::from_bits(val) - } -} -impl From for u8 { - #[inline(always)] - fn from(val: SwLock50nsec) -> u8 { - SwLock50nsec::to_bits(val) - } -} -#[repr(u8)] -#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] -pub enum SwLock50sec { - READ_WRITE = 0, - READ_ONLY = 0x01, - _RESERVED_2 = 0x02, - INACCESSIBLE = 0x03, -} -impl SwLock50sec { - #[inline(always)] - pub const fn from_bits(val: u8) -> SwLock50sec { - unsafe { core::mem::transmute(val & 0x03) } - } - #[inline(always)] - pub const fn to_bits(self) -> u8 { - unsafe { core::mem::transmute(self) } - } -} -impl From for SwLock50sec { - #[inline(always)] - fn from(val: u8) -> SwLock50sec { - SwLock50sec::from_bits(val) - } -} -impl From for u8 { - #[inline(always)] - fn from(val: SwLock50sec) -> u8 { - SwLock50sec::to_bits(val) - } -} -#[repr(u8)] -#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] -pub enum SwLock51nsec { - READ_WRITE = 0, - READ_ONLY = 0x01, - _RESERVED_2 = 0x02, - INACCESSIBLE = 0x03, -} -impl SwLock51nsec { - #[inline(always)] - pub const fn from_bits(val: u8) -> SwLock51nsec { - unsafe { core::mem::transmute(val & 0x03) } - } - #[inline(always)] - pub const fn to_bits(self) -> u8 { - unsafe { core::mem::transmute(self) } - } -} -impl From for SwLock51nsec { - #[inline(always)] - fn from(val: u8) -> SwLock51nsec { - SwLock51nsec::from_bits(val) - } -} -impl From for u8 { - #[inline(always)] - fn from(val: SwLock51nsec) -> u8 { - SwLock51nsec::to_bits(val) - } -} -#[repr(u8)] -#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] -pub enum SwLock51sec { - READ_WRITE = 0, - READ_ONLY = 0x01, - _RESERVED_2 = 0x02, - INACCESSIBLE = 0x03, -} -impl SwLock51sec { - #[inline(always)] - pub const fn from_bits(val: u8) -> SwLock51sec { - unsafe { core::mem::transmute(val & 0x03) } - } - #[inline(always)] - pub const fn to_bits(self) -> u8 { - unsafe { core::mem::transmute(self) } - } -} -impl From for SwLock51sec { - #[inline(always)] - fn from(val: u8) -> SwLock51sec { - SwLock51sec::from_bits(val) - } -} -impl From for u8 { - #[inline(always)] - fn from(val: SwLock51sec) -> u8 { - SwLock51sec::to_bits(val) - } -} -#[repr(u8)] -#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] -pub enum SwLock52nsec { - READ_WRITE = 0, - READ_ONLY = 0x01, - _RESERVED_2 = 0x02, - INACCESSIBLE = 0x03, -} -impl SwLock52nsec { - #[inline(always)] - pub const fn from_bits(val: u8) -> SwLock52nsec { - unsafe { core::mem::transmute(val & 0x03) } - } - #[inline(always)] - pub const fn to_bits(self) -> u8 { - unsafe { core::mem::transmute(self) } - } -} -impl From for SwLock52nsec { - #[inline(always)] - fn from(val: u8) -> SwLock52nsec { - SwLock52nsec::from_bits(val) - } -} -impl From for u8 { - #[inline(always)] - fn from(val: SwLock52nsec) -> u8 { - SwLock52nsec::to_bits(val) - } -} -#[repr(u8)] -#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] -pub enum SwLock52sec { - READ_WRITE = 0, - READ_ONLY = 0x01, - _RESERVED_2 = 0x02, - INACCESSIBLE = 0x03, -} -impl SwLock52sec { - #[inline(always)] - pub const fn from_bits(val: u8) -> SwLock52sec { - unsafe { core::mem::transmute(val & 0x03) } - } - #[inline(always)] - pub const fn to_bits(self) -> u8 { - unsafe { core::mem::transmute(self) } - } -} -impl From for SwLock52sec { - #[inline(always)] - fn from(val: u8) -> SwLock52sec { - SwLock52sec::from_bits(val) - } -} -impl From for u8 { - #[inline(always)] - fn from(val: SwLock52sec) -> u8 { - SwLock52sec::to_bits(val) - } -} -#[repr(u8)] -#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] -pub enum SwLock53nsec { - READ_WRITE = 0, - READ_ONLY = 0x01, - _RESERVED_2 = 0x02, - INACCESSIBLE = 0x03, -} -impl SwLock53nsec { - #[inline(always)] - pub const fn from_bits(val: u8) -> SwLock53nsec { - unsafe { core::mem::transmute(val & 0x03) } - } - #[inline(always)] - pub const fn to_bits(self) -> u8 { - unsafe { core::mem::transmute(self) } - } -} -impl From for SwLock53nsec { - #[inline(always)] - fn from(val: u8) -> SwLock53nsec { - SwLock53nsec::from_bits(val) - } -} -impl From for u8 { - #[inline(always)] - fn from(val: SwLock53nsec) -> u8 { - SwLock53nsec::to_bits(val) - } -} -#[repr(u8)] -#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] -pub enum SwLock53sec { - READ_WRITE = 0, - READ_ONLY = 0x01, - _RESERVED_2 = 0x02, - INACCESSIBLE = 0x03, -} -impl SwLock53sec { - #[inline(always)] - pub const fn from_bits(val: u8) -> SwLock53sec { - unsafe { core::mem::transmute(val & 0x03) } - } - #[inline(always)] - pub const fn to_bits(self) -> u8 { - unsafe { core::mem::transmute(self) } - } -} -impl From for SwLock53sec { - #[inline(always)] - fn from(val: u8) -> SwLock53sec { - SwLock53sec::from_bits(val) - } -} -impl From for u8 { - #[inline(always)] - fn from(val: SwLock53sec) -> u8 { - SwLock53sec::to_bits(val) - } -} -#[repr(u8)] -#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] -pub enum SwLock54nsec { - READ_WRITE = 0, - READ_ONLY = 0x01, - _RESERVED_2 = 0x02, - INACCESSIBLE = 0x03, -} -impl SwLock54nsec { - #[inline(always)] - pub const fn from_bits(val: u8) -> SwLock54nsec { - unsafe { core::mem::transmute(val & 0x03) } - } - #[inline(always)] - pub const fn to_bits(self) -> u8 { - unsafe { core::mem::transmute(self) } - } -} -impl From for SwLock54nsec { - #[inline(always)] - fn from(val: u8) -> SwLock54nsec { - SwLock54nsec::from_bits(val) - } -} -impl From for u8 { - #[inline(always)] - fn from(val: SwLock54nsec) -> u8 { - SwLock54nsec::to_bits(val) - } -} -#[repr(u8)] -#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] -pub enum SwLock54sec { - READ_WRITE = 0, - READ_ONLY = 0x01, - _RESERVED_2 = 0x02, - INACCESSIBLE = 0x03, -} -impl SwLock54sec { - #[inline(always)] - pub const fn from_bits(val: u8) -> SwLock54sec { - unsafe { core::mem::transmute(val & 0x03) } - } - #[inline(always)] - pub const fn to_bits(self) -> u8 { - unsafe { core::mem::transmute(self) } - } -} -impl From for SwLock54sec { - #[inline(always)] - fn from(val: u8) -> SwLock54sec { - SwLock54sec::from_bits(val) - } -} -impl From for u8 { - #[inline(always)] - fn from(val: SwLock54sec) -> u8 { - SwLock54sec::to_bits(val) - } -} -#[repr(u8)] -#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] -pub enum SwLock55nsec { - READ_WRITE = 0, - READ_ONLY = 0x01, - _RESERVED_2 = 0x02, - INACCESSIBLE = 0x03, -} -impl SwLock55nsec { - #[inline(always)] - pub const fn from_bits(val: u8) -> SwLock55nsec { - unsafe { core::mem::transmute(val & 0x03) } - } - #[inline(always)] - pub const fn to_bits(self) -> u8 { - unsafe { core::mem::transmute(self) } - } -} -impl From for SwLock55nsec { - #[inline(always)] - fn from(val: u8) -> SwLock55nsec { - SwLock55nsec::from_bits(val) - } -} -impl From for u8 { - #[inline(always)] - fn from(val: SwLock55nsec) -> u8 { - SwLock55nsec::to_bits(val) - } -} -#[repr(u8)] -#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] -pub enum SwLock55sec { - READ_WRITE = 0, - READ_ONLY = 0x01, - _RESERVED_2 = 0x02, - INACCESSIBLE = 0x03, -} -impl SwLock55sec { - #[inline(always)] - pub const fn from_bits(val: u8) -> SwLock55sec { - unsafe { core::mem::transmute(val & 0x03) } - } - #[inline(always)] - pub const fn to_bits(self) -> u8 { - unsafe { core::mem::transmute(self) } - } -} -impl From for SwLock55sec { - #[inline(always)] - fn from(val: u8) -> SwLock55sec { - SwLock55sec::from_bits(val) - } -} -impl From for u8 { - #[inline(always)] - fn from(val: SwLock55sec) -> u8 { - SwLock55sec::to_bits(val) - } -} -#[repr(u8)] -#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] -pub enum SwLock56nsec { - READ_WRITE = 0, - READ_ONLY = 0x01, - _RESERVED_2 = 0x02, - INACCESSIBLE = 0x03, -} -impl SwLock56nsec { - #[inline(always)] - pub const fn from_bits(val: u8) -> SwLock56nsec { - unsafe { core::mem::transmute(val & 0x03) } - } - #[inline(always)] - pub const fn to_bits(self) -> u8 { - unsafe { core::mem::transmute(self) } - } -} -impl From for SwLock56nsec { - #[inline(always)] - fn from(val: u8) -> SwLock56nsec { - SwLock56nsec::from_bits(val) - } -} -impl From for u8 { - #[inline(always)] - fn from(val: SwLock56nsec) -> u8 { - SwLock56nsec::to_bits(val) - } -} -#[repr(u8)] -#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] -pub enum SwLock56sec { - READ_WRITE = 0, - READ_ONLY = 0x01, - _RESERVED_2 = 0x02, - INACCESSIBLE = 0x03, -} -impl SwLock56sec { - #[inline(always)] - pub const fn from_bits(val: u8) -> SwLock56sec { - unsafe { core::mem::transmute(val & 0x03) } - } - #[inline(always)] - pub const fn to_bits(self) -> u8 { - unsafe { core::mem::transmute(self) } - } -} -impl From for SwLock56sec { - #[inline(always)] - fn from(val: u8) -> SwLock56sec { - SwLock56sec::from_bits(val) - } -} -impl From for u8 { - #[inline(always)] - fn from(val: SwLock56sec) -> u8 { - SwLock56sec::to_bits(val) - } -} -#[repr(u8)] -#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] -pub enum SwLock57nsec { - READ_WRITE = 0, - READ_ONLY = 0x01, - _RESERVED_2 = 0x02, - INACCESSIBLE = 0x03, -} -impl SwLock57nsec { - #[inline(always)] - pub const fn from_bits(val: u8) -> SwLock57nsec { - unsafe { core::mem::transmute(val & 0x03) } - } - #[inline(always)] - pub const fn to_bits(self) -> u8 { - unsafe { core::mem::transmute(self) } - } -} -impl From for SwLock57nsec { - #[inline(always)] - fn from(val: u8) -> SwLock57nsec { - SwLock57nsec::from_bits(val) - } -} -impl From for u8 { - #[inline(always)] - fn from(val: SwLock57nsec) -> u8 { - SwLock57nsec::to_bits(val) - } -} -#[repr(u8)] -#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] -pub enum SwLock57sec { - READ_WRITE = 0, - READ_ONLY = 0x01, - _RESERVED_2 = 0x02, - INACCESSIBLE = 0x03, -} -impl SwLock57sec { - #[inline(always)] - pub const fn from_bits(val: u8) -> SwLock57sec { - unsafe { core::mem::transmute(val & 0x03) } - } - #[inline(always)] - pub const fn to_bits(self) -> u8 { - unsafe { core::mem::transmute(self) } - } -} -impl From for SwLock57sec { - #[inline(always)] - fn from(val: u8) -> SwLock57sec { - SwLock57sec::from_bits(val) - } -} -impl From for u8 { - #[inline(always)] - fn from(val: SwLock57sec) -> u8 { - SwLock57sec::to_bits(val) - } -} -#[repr(u8)] -#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] -pub enum SwLock58nsec { - READ_WRITE = 0, - READ_ONLY = 0x01, - _RESERVED_2 = 0x02, - INACCESSIBLE = 0x03, -} -impl SwLock58nsec { - #[inline(always)] - pub const fn from_bits(val: u8) -> SwLock58nsec { - unsafe { core::mem::transmute(val & 0x03) } - } - #[inline(always)] - pub const fn to_bits(self) -> u8 { - unsafe { core::mem::transmute(self) } - } -} -impl From for SwLock58nsec { - #[inline(always)] - fn from(val: u8) -> SwLock58nsec { - SwLock58nsec::from_bits(val) - } -} -impl From for u8 { - #[inline(always)] - fn from(val: SwLock58nsec) -> u8 { - SwLock58nsec::to_bits(val) - } -} -#[repr(u8)] -#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] -pub enum SwLock58sec { - READ_WRITE = 0, - READ_ONLY = 0x01, - _RESERVED_2 = 0x02, - INACCESSIBLE = 0x03, -} -impl SwLock58sec { - #[inline(always)] - pub const fn from_bits(val: u8) -> SwLock58sec { - unsafe { core::mem::transmute(val & 0x03) } - } - #[inline(always)] - pub const fn to_bits(self) -> u8 { - unsafe { core::mem::transmute(self) } - } -} -impl From for SwLock58sec { - #[inline(always)] - fn from(val: u8) -> SwLock58sec { - SwLock58sec::from_bits(val) - } -} -impl From for u8 { - #[inline(always)] - fn from(val: SwLock58sec) -> u8 { - SwLock58sec::to_bits(val) - } -} -#[repr(u8)] -#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] -pub enum SwLock59nsec { - READ_WRITE = 0, - READ_ONLY = 0x01, - _RESERVED_2 = 0x02, - INACCESSIBLE = 0x03, -} -impl SwLock59nsec { - #[inline(always)] - pub const fn from_bits(val: u8) -> SwLock59nsec { - unsafe { core::mem::transmute(val & 0x03) } - } - #[inline(always)] - pub const fn to_bits(self) -> u8 { - unsafe { core::mem::transmute(self) } - } -} -impl From for SwLock59nsec { - #[inline(always)] - fn from(val: u8) -> SwLock59nsec { - SwLock59nsec::from_bits(val) - } -} -impl From for u8 { - #[inline(always)] - fn from(val: SwLock59nsec) -> u8 { - SwLock59nsec::to_bits(val) - } -} -#[repr(u8)] -#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] -pub enum SwLock59sec { - READ_WRITE = 0, - READ_ONLY = 0x01, - _RESERVED_2 = 0x02, - INACCESSIBLE = 0x03, -} -impl SwLock59sec { - #[inline(always)] - pub const fn from_bits(val: u8) -> SwLock59sec { - unsafe { core::mem::transmute(val & 0x03) } - } - #[inline(always)] - pub const fn to_bits(self) -> u8 { - unsafe { core::mem::transmute(self) } - } -} -impl From for SwLock59sec { - #[inline(always)] - fn from(val: u8) -> SwLock59sec { - SwLock59sec::from_bits(val) - } -} -impl From for u8 { - #[inline(always)] - fn from(val: SwLock59sec) -> u8 { - SwLock59sec::to_bits(val) - } -} -#[repr(u8)] -#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] -pub enum SwLock5nsec { - READ_WRITE = 0, - READ_ONLY = 0x01, - _RESERVED_2 = 0x02, - INACCESSIBLE = 0x03, -} -impl SwLock5nsec { - #[inline(always)] - pub const fn from_bits(val: u8) -> SwLock5nsec { - unsafe { core::mem::transmute(val & 0x03) } - } - #[inline(always)] - pub const fn to_bits(self) -> u8 { - unsafe { core::mem::transmute(self) } - } -} -impl From for SwLock5nsec { - #[inline(always)] - fn from(val: u8) -> SwLock5nsec { - SwLock5nsec::from_bits(val) - } -} -impl From for u8 { - #[inline(always)] - fn from(val: SwLock5nsec) -> u8 { - SwLock5nsec::to_bits(val) - } -} -#[repr(u8)] -#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] -pub enum SwLock5sec { - READ_WRITE = 0, - READ_ONLY = 0x01, - _RESERVED_2 = 0x02, - INACCESSIBLE = 0x03, -} -impl SwLock5sec { - #[inline(always)] - pub const fn from_bits(val: u8) -> SwLock5sec { - unsafe { core::mem::transmute(val & 0x03) } - } - #[inline(always)] - pub const fn to_bits(self) -> u8 { - unsafe { core::mem::transmute(self) } - } -} -impl From for SwLock5sec { - #[inline(always)] - fn from(val: u8) -> SwLock5sec { - SwLock5sec::from_bits(val) - } -} -impl From for u8 { - #[inline(always)] - fn from(val: SwLock5sec) -> u8 { - SwLock5sec::to_bits(val) - } -} -#[repr(u8)] -#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] -pub enum SwLock60nsec { - READ_WRITE = 0, - READ_ONLY = 0x01, - _RESERVED_2 = 0x02, - INACCESSIBLE = 0x03, -} -impl SwLock60nsec { - #[inline(always)] - pub const fn from_bits(val: u8) -> SwLock60nsec { - unsafe { core::mem::transmute(val & 0x03) } - } - #[inline(always)] - pub const fn to_bits(self) -> u8 { - unsafe { core::mem::transmute(self) } - } -} -impl From for SwLock60nsec { - #[inline(always)] - fn from(val: u8) -> SwLock60nsec { - SwLock60nsec::from_bits(val) - } -} -impl From for u8 { - #[inline(always)] - fn from(val: SwLock60nsec) -> u8 { - SwLock60nsec::to_bits(val) - } -} -#[repr(u8)] -#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] -pub enum SwLock60sec { - READ_WRITE = 0, - READ_ONLY = 0x01, - _RESERVED_2 = 0x02, - INACCESSIBLE = 0x03, -} -impl SwLock60sec { - #[inline(always)] - pub const fn from_bits(val: u8) -> SwLock60sec { - unsafe { core::mem::transmute(val & 0x03) } - } - #[inline(always)] - pub const fn to_bits(self) -> u8 { - unsafe { core::mem::transmute(self) } - } -} -impl From for SwLock60sec { - #[inline(always)] - fn from(val: u8) -> SwLock60sec { - SwLock60sec::from_bits(val) - } -} -impl From for u8 { - #[inline(always)] - fn from(val: SwLock60sec) -> u8 { - SwLock60sec::to_bits(val) - } -} -#[repr(u8)] -#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] -pub enum SwLock61nsec { - READ_WRITE = 0, - READ_ONLY = 0x01, - _RESERVED_2 = 0x02, - INACCESSIBLE = 0x03, -} -impl SwLock61nsec { - #[inline(always)] - pub const fn from_bits(val: u8) -> SwLock61nsec { - unsafe { core::mem::transmute(val & 0x03) } - } - #[inline(always)] - pub const fn to_bits(self) -> u8 { - unsafe { core::mem::transmute(self) } - } -} -impl From for SwLock61nsec { - #[inline(always)] - fn from(val: u8) -> SwLock61nsec { - SwLock61nsec::from_bits(val) - } -} -impl From for u8 { - #[inline(always)] - fn from(val: SwLock61nsec) -> u8 { - SwLock61nsec::to_bits(val) - } -} -#[repr(u8)] -#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] -pub enum SwLock61sec { - READ_WRITE = 0, - READ_ONLY = 0x01, - _RESERVED_2 = 0x02, - INACCESSIBLE = 0x03, -} -impl SwLock61sec { - #[inline(always)] - pub const fn from_bits(val: u8) -> SwLock61sec { - unsafe { core::mem::transmute(val & 0x03) } - } - #[inline(always)] - pub const fn to_bits(self) -> u8 { - unsafe { core::mem::transmute(self) } - } -} -impl From for SwLock61sec { - #[inline(always)] - fn from(val: u8) -> SwLock61sec { - SwLock61sec::from_bits(val) - } -} -impl From for u8 { - #[inline(always)] - fn from(val: SwLock61sec) -> u8 { - SwLock61sec::to_bits(val) - } -} -#[repr(u8)] -#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] -pub enum SwLock62nsec { - READ_WRITE = 0, - READ_ONLY = 0x01, - _RESERVED_2 = 0x02, - INACCESSIBLE = 0x03, -} -impl SwLock62nsec { - #[inline(always)] - pub const fn from_bits(val: u8) -> SwLock62nsec { - unsafe { core::mem::transmute(val & 0x03) } - } - #[inline(always)] - pub const fn to_bits(self) -> u8 { - unsafe { core::mem::transmute(self) } - } -} -impl From for SwLock62nsec { - #[inline(always)] - fn from(val: u8) -> SwLock62nsec { - SwLock62nsec::from_bits(val) - } -} -impl From for u8 { - #[inline(always)] - fn from(val: SwLock62nsec) -> u8 { - SwLock62nsec::to_bits(val) - } -} -#[repr(u8)] -#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] -pub enum SwLock62sec { - READ_WRITE = 0, - READ_ONLY = 0x01, - _RESERVED_2 = 0x02, - INACCESSIBLE = 0x03, -} -impl SwLock62sec { - #[inline(always)] - pub const fn from_bits(val: u8) -> SwLock62sec { - unsafe { core::mem::transmute(val & 0x03) } - } - #[inline(always)] - pub const fn to_bits(self) -> u8 { - unsafe { core::mem::transmute(self) } - } -} -impl From for SwLock62sec { - #[inline(always)] - fn from(val: u8) -> SwLock62sec { - SwLock62sec::from_bits(val) - } -} -impl From for u8 { - #[inline(always)] - fn from(val: SwLock62sec) -> u8 { - SwLock62sec::to_bits(val) - } -} -#[repr(u8)] -#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] -pub enum SwLock63nsec { - READ_WRITE = 0, - READ_ONLY = 0x01, - _RESERVED_2 = 0x02, - INACCESSIBLE = 0x03, -} -impl SwLock63nsec { - #[inline(always)] - pub const fn from_bits(val: u8) -> SwLock63nsec { - unsafe { core::mem::transmute(val & 0x03) } - } - #[inline(always)] - pub const fn to_bits(self) -> u8 { - unsafe { core::mem::transmute(self) } - } -} -impl From for SwLock63nsec { - #[inline(always)] - fn from(val: u8) -> SwLock63nsec { - SwLock63nsec::from_bits(val) - } -} -impl From for u8 { - #[inline(always)] - fn from(val: SwLock63nsec) -> u8 { - SwLock63nsec::to_bits(val) - } -} -#[repr(u8)] -#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] -pub enum SwLock63sec { - READ_WRITE = 0, - READ_ONLY = 0x01, - _RESERVED_2 = 0x02, - INACCESSIBLE = 0x03, -} -impl SwLock63sec { - #[inline(always)] - pub const fn from_bits(val: u8) -> SwLock63sec { - unsafe { core::mem::transmute(val & 0x03) } - } - #[inline(always)] - pub const fn to_bits(self) -> u8 { - unsafe { core::mem::transmute(self) } - } -} -impl From for SwLock63sec { - #[inline(always)] - fn from(val: u8) -> SwLock63sec { - SwLock63sec::from_bits(val) - } -} -impl From for u8 { - #[inline(always)] - fn from(val: SwLock63sec) -> u8 { - SwLock63sec::to_bits(val) - } -} -#[repr(u8)] -#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] -pub enum SwLock6nsec { - READ_WRITE = 0, - READ_ONLY = 0x01, - _RESERVED_2 = 0x02, - INACCESSIBLE = 0x03, -} -impl SwLock6nsec { - #[inline(always)] - pub const fn from_bits(val: u8) -> SwLock6nsec { - unsafe { core::mem::transmute(val & 0x03) } - } - #[inline(always)] - pub const fn to_bits(self) -> u8 { - unsafe { core::mem::transmute(self) } - } -} -impl From for SwLock6nsec { - #[inline(always)] - fn from(val: u8) -> SwLock6nsec { - SwLock6nsec::from_bits(val) - } -} -impl From for u8 { - #[inline(always)] - fn from(val: SwLock6nsec) -> u8 { - SwLock6nsec::to_bits(val) - } -} -#[repr(u8)] -#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] -pub enum SwLock6sec { - READ_WRITE = 0, - READ_ONLY = 0x01, - _RESERVED_2 = 0x02, - INACCESSIBLE = 0x03, -} -impl SwLock6sec { - #[inline(always)] - pub const fn from_bits(val: u8) -> SwLock6sec { - unsafe { core::mem::transmute(val & 0x03) } - } - #[inline(always)] - pub const fn to_bits(self) -> u8 { - unsafe { core::mem::transmute(self) } - } -} -impl From for SwLock6sec { - #[inline(always)] - fn from(val: u8) -> SwLock6sec { - SwLock6sec::from_bits(val) - } -} -impl From for u8 { - #[inline(always)] - fn from(val: SwLock6sec) -> u8 { - SwLock6sec::to_bits(val) - } -} -#[repr(u8)] -#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] -pub enum SwLock7nsec { - READ_WRITE = 0, - READ_ONLY = 0x01, - _RESERVED_2 = 0x02, - INACCESSIBLE = 0x03, -} -impl SwLock7nsec { - #[inline(always)] - pub const fn from_bits(val: u8) -> SwLock7nsec { - unsafe { core::mem::transmute(val & 0x03) } - } - #[inline(always)] - pub const fn to_bits(self) -> u8 { - unsafe { core::mem::transmute(self) } - } -} -impl From for SwLock7nsec { - #[inline(always)] - fn from(val: u8) -> SwLock7nsec { - SwLock7nsec::from_bits(val) - } -} -impl From for u8 { - #[inline(always)] - fn from(val: SwLock7nsec) -> u8 { - SwLock7nsec::to_bits(val) - } -} -#[repr(u8)] -#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] -pub enum SwLock7sec { - READ_WRITE = 0, - READ_ONLY = 0x01, - _RESERVED_2 = 0x02, - INACCESSIBLE = 0x03, -} -impl SwLock7sec { - #[inline(always)] - pub const fn from_bits(val: u8) -> SwLock7sec { - unsafe { core::mem::transmute(val & 0x03) } - } - #[inline(always)] - pub const fn to_bits(self) -> u8 { - unsafe { core::mem::transmute(self) } - } -} -impl From for SwLock7sec { - #[inline(always)] - fn from(val: u8) -> SwLock7sec { - SwLock7sec::from_bits(val) - } -} -impl From for u8 { - #[inline(always)] - fn from(val: SwLock7sec) -> u8 { - SwLock7sec::to_bits(val) - } -} -#[repr(u8)] -#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] -pub enum SwLock8nsec { - READ_WRITE = 0, - READ_ONLY = 0x01, - _RESERVED_2 = 0x02, - INACCESSIBLE = 0x03, -} -impl SwLock8nsec { - #[inline(always)] - pub const fn from_bits(val: u8) -> SwLock8nsec { - unsafe { core::mem::transmute(val & 0x03) } - } - #[inline(always)] - pub const fn to_bits(self) -> u8 { - unsafe { core::mem::transmute(self) } - } -} -impl From for SwLock8nsec { - #[inline(always)] - fn from(val: u8) -> SwLock8nsec { - SwLock8nsec::from_bits(val) - } -} -impl From for u8 { - #[inline(always)] - fn from(val: SwLock8nsec) -> u8 { - SwLock8nsec::to_bits(val) - } -} -#[repr(u8)] -#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] -pub enum SwLock8sec { - READ_WRITE = 0, - READ_ONLY = 0x01, - _RESERVED_2 = 0x02, - INACCESSIBLE = 0x03, -} -impl SwLock8sec { - #[inline(always)] - pub const fn from_bits(val: u8) -> SwLock8sec { - unsafe { core::mem::transmute(val & 0x03) } - } - #[inline(always)] - pub const fn to_bits(self) -> u8 { - unsafe { core::mem::transmute(self) } - } -} -impl From for SwLock8sec { - #[inline(always)] - fn from(val: u8) -> SwLock8sec { - SwLock8sec::from_bits(val) - } -} -impl From for u8 { - #[inline(always)] - fn from(val: SwLock8sec) -> u8 { - SwLock8sec::to_bits(val) - } -} -#[repr(u8)] -#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] -pub enum SwLock9nsec { - READ_WRITE = 0, - READ_ONLY = 0x01, - _RESERVED_2 = 0x02, - INACCESSIBLE = 0x03, -} -impl SwLock9nsec { - #[inline(always)] - pub const fn from_bits(val: u8) -> SwLock9nsec { - unsafe { core::mem::transmute(val & 0x03) } - } - #[inline(always)] - pub const fn to_bits(self) -> u8 { - unsafe { core::mem::transmute(self) } - } -} -impl From for SwLock9nsec { - #[inline(always)] - fn from(val: u8) -> SwLock9nsec { - SwLock9nsec::from_bits(val) - } -} -impl From for u8 { - #[inline(always)] - fn from(val: SwLock9nsec) -> u8 { - SwLock9nsec::to_bits(val) - } -} -#[repr(u8)] -#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] -pub enum SwLock9sec { - READ_WRITE = 0, - READ_ONLY = 0x01, - _RESERVED_2 = 0x02, - INACCESSIBLE = 0x03, -} -impl SwLock9sec { - #[inline(always)] - pub const fn from_bits(val: u8) -> SwLock9sec { - unsafe { core::mem::transmute(val & 0x03) } - } - #[inline(always)] - pub const fn to_bits(self) -> u8 { - unsafe { core::mem::transmute(self) } - } -} -impl From for SwLock9sec { - #[inline(always)] - fn from(val: u8) -> SwLock9sec { - SwLock9sec::from_bits(val) - } -} -impl From for u8 { - #[inline(always)] - fn from(val: SwLock9sec) -> u8 { - SwLock9sec::to_bits(val) + fn from(val: SwLockSec) -> u8 { + SwLockSec::to_bits(val) } } diff --git a/src/rp235x/otp_data.rs b/src/rp235x/otp_data.rs index 72d6a89a..7244f5e8 100644 --- a/src/rp235x/otp_data.rs +++ b/src/rp235x/otp_data.rs @@ -17,705 +17,705 @@ impl OtpData { #[doc = "Bits 15:0 of public device ID. (ECC) The CHIPID0..3 rows contain a 64-bit random identifier for this chip, which can be read from the USB bootloader PICOBOOT interface or from the get_sys_info ROM API. The number of random bits makes the occurrence of twins exceedingly unlikely: for example, a fleet of a hundred million devices has a 99.97% probability of no twinned IDs. This is estimated to be lower than the occurrence of process errors in the assignment of sequential random IDs, and for practical purposes CHIPID may be treated as unique."] #[inline(always)] pub const fn chipid0(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(0usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x0usize) as _) } } #[doc = "Bits 31:16 of public device ID (ECC)"] #[inline(always)] pub const fn chipid1(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(2usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x02usize) as _) } } #[doc = "Bits 47:32 of public device ID (ECC)"] #[inline(always)] pub const fn chipid2(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(4usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x04usize) as _) } } #[doc = "Bits 63:48 of public device ID (ECC)"] #[inline(always)] pub const fn chipid3(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(6usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x06usize) as _) } } #[doc = "Bits 15:0 of private per-device random number (ECC) The RANDID0..7 rows form a 128-bit random number generated during device test. This ID is not exposed through the USB PICOBOOT GET_INFO command or the ROM `get_sys_info()` API. However note that the USB PICOBOOT OTP access point can read the entirety of page 0, so this value is not meaningfully private unless the USB PICOBOOT interface is disabled via the DISABLE_BOOTSEL_USB_PICOBOOT_IFC flag in BOOT_FLAGS0."] #[inline(always)] pub const fn randid0(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(8usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x08usize) as _) } } #[doc = "Bits 31:16 of private per-device random number (ECC)"] #[inline(always)] pub const fn randid1(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(10usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x0ausize) as _) } } #[doc = "Bits 47:32 of private per-device random number (ECC)"] #[inline(always)] pub const fn randid2(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(12usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x0cusize) as _) } } #[doc = "Bits 63:48 of private per-device random number (ECC)"] #[inline(always)] pub const fn randid3(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(14usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x0eusize) as _) } } #[doc = "Bits 79:64 of private per-device random number (ECC)"] #[inline(always)] pub const fn randid4(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(16usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x10usize) as _) } } #[doc = "Bits 95:80 of private per-device random number (ECC)"] #[inline(always)] pub const fn randid5(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(18usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x12usize) as _) } } #[doc = "Bits 111:96 of private per-device random number (ECC)"] #[inline(always)] pub const fn randid6(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(20usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x14usize) as _) } } #[doc = "Bits 127:112 of private per-device random number (ECC)"] #[inline(always)] pub const fn randid7(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(22usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x16usize) as _) } } #[doc = "Ring oscillator frequency in kHz, measured during manufacturing (ECC) This is measured at 1.1 V, at room temperature, with the ROSC configuration registers in their reset state."] #[inline(always)] pub const fn rosc_calib(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(32usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x20usize) as _) } } #[doc = "Low-power oscillator frequency in Hz, measured during manufacturing (ECC) This is measured at 1.1V, at room temperature, with the LPOSC trim register in its reset state."] #[inline(always)] pub const fn lposc_calib(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(34usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x22usize) as _) } } #[doc = "The number of main user GPIOs (bank 0). Should read 48 in the QFN80 package, and 30 in the QFN60 package. (ECC)"] #[inline(always)] pub const fn num_gpios(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(48usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x30usize) as _) } } #[doc = "Lower 16 bits of CRC32 of OTP addresses 0x00 through 0x6b (polynomial 0x4c11db7, input reflected, output reflected, seed all-ones, final XOR all-ones) (ECC)"] #[inline(always)] pub const fn info_crc0(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(108usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x6cusize) as _) } } #[doc = "Upper 16 bits of CRC32 of OTP addresses 0x00 through 0x6b (ECC)"] #[inline(always)] pub const fn info_crc1(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(110usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x6eusize) as _) } } #[doc = "Stores information about external flash device(s). (ECC) Assumed to be valid if BOOT_FLAGS0_FLASH_DEVINFO_ENABLE is set."] #[inline(always)] pub const fn flash_devinfo(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(168usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0xa8usize) as _) } } #[doc = "Gap between partition table slot 0 and slot 1 at the start of flash (the default size is 4096 bytes) (ECC) Enabled by the OVERRIDE_FLASH_PARTITION_SLOT_SIZE bit in BOOT_FLAGS, the size is 4096 * (value + 1)"] #[inline(always)] pub const fn flash_partition_slot_size(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(170usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0xaausize) as _) } } #[doc = "Pin configuration for LED status, used by USB bootloader. (ECC) Must be valid if BOOT_FLAGS0_ENABLE_BOOTSEL_LED is set."] #[inline(always)] pub const fn bootsel_led_cfg( self, ) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(172usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0xacusize) as _) } } #[doc = "Optional PLL configuration for BOOTSEL mode. (ECC) This should be configured to produce an exact 48 MHz based on the crystal oscillator frequency. User mode software may also use this value to calculate the expected crystal frequency based on an assumed 48 MHz PLL output. If no configuration is given, the crystal is assumed to be 12 MHz. The PLL frequency can be calculated as: PLL out = (XOSC frequency / (REFDIV+1)) x FBDIV / (POSTDIV1 x POSTDIV2) Conversely the crystal frequency can be calculated as: XOSC frequency = 48 MHz x (REFDIV+1) x (POSTDIV1 x POSTDIV2) / FBDIV (Note the +1 on REFDIV is because the value stored in this OTP location is the actual divisor value minus one.) Used if and only if ENABLE_BOOTSEL_NON_DEFAULT_PLL_XOSC_CFG is set in BOOT_FLAGS0. That bit should be set only after this row and BOOTSEL_XOSC_CFG are both correctly programmed."] #[inline(always)] pub const fn bootsel_pll_cfg( self, ) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(174usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0xaeusize) as _) } } #[doc = "Non-default crystal oscillator configuration for the USB bootloader. (ECC) These values may also be used by user code configuring the crystal oscillator. Used if and only if ENABLE_BOOTSEL_NON_DEFAULT_PLL_XOSC_CFG is set in BOOT_FLAGS0. That bit should be set only after this row and BOOTSEL_PLL_CFG are both correctly programmed."] #[inline(always)] pub const fn bootsel_xosc_cfg( self, ) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(176usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0xb0usize) as _) } } #[doc = "Row index of the USB_WHITE_LABEL structure within OTP (ECC) The table has 16 rows, each of which are also ECC and marked valid by the corresponding valid bit in USB_BOOT_FLAGS (ECC). The entries are either _VALUEs where the 16 bit value is used as is, or _STRDEFs which acts as a pointers to a string value. The value stored in a _STRDEF is two separate bytes: The low seven bits of the first (LSB) byte indicates the number of characters in the string, and the top bit of the first (LSB) byte if set to indicate that each character in the string is two bytes (Unicode) versus one byte if unset. The second (MSB) byte represents the location of the string data, and is encoded as the number of rows from this USB_WHITE_LABEL_ADDR; i.e. the row of the start of the string is USB_WHITE_LABEL_ADDR value + msb_byte. In each case, the corresponding valid bit enables replacing the default value for the corresponding item provided by the boot rom. Note that Unicode _STRDEFs are only supported for USB_DEVICE_PRODUCT_STRDEF, USB_DEVICE_SERIAL_NUMBER_STRDEF and USB_DEVICE_MANUFACTURER_STRDEF. Unicode values will be ignored if specified for other fields, and non-unicode values for these three items will be converted to Unicode characters by setting the upper 8 bits to zero. Note that if the USB_WHITE_LABEL structure or the corresponding strings are not readable by BOOTSEL mode based on OTP permissions, or if alignment requirements are not met, then the corresponding default values are used. The index values indicate where each field is located (row USB_WHITE_LABEL_ADDR value + index):"] #[inline(always)] pub const fn usb_white_label_addr( self, ) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(184usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0xb8usize) as _) } } #[doc = "OTP start row for the OTP boot image. (ECC) If OTP boot is enabled, the bootrom will load from this location into SRAM and then directly enter the loaded image. Note that the image must be signed if SECURE_BOOT_ENABLE is set. The image itself is assumed to be ECC-protected. This must be an even number. Equivalently, the OTP boot image must start at a word-aligned location in the ECC read data address window."] #[inline(always)] pub const fn otpboot_src(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(188usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0xbcusize) as _) } } #[doc = "Length in rows of the OTP boot image. (ECC) OTPBOOT_LEN must be even. The total image size must be a multiple of 4 bytes (32 bits)."] #[inline(always)] pub const fn otpboot_len(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(190usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0xbeusize) as _) } } #[doc = "Bits 15:0 of the OTP boot image load destination (and entry point). (ECC) This must be a location in main SRAM (main SRAM is addresses 0x20000000 through 0x20082000) and must be word-aligned."] #[inline(always)] pub const fn otpboot_dst0(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(192usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0xc0usize) as _) } } #[doc = "Bits 31:16 of the OTP boot image load destination (and entry point). (ECC) This must be a location in main SRAM (main SRAM is addresses 0x20000000 through 0x20082000) and must be word-aligned."] #[inline(always)] pub const fn otpboot_dst1(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(194usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0xc2usize) as _) } } #[doc = "Bits 15:0 of SHA-256 hash of boot key 0 (ECC)"] #[inline(always)] pub const fn bootkey0_0(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(256usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x0100usize) as _) } } #[doc = "Bits 31:16 of SHA-256 hash of boot key 0 (ECC)"] #[inline(always)] pub const fn bootkey0_1(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(258usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x0102usize) as _) } } #[doc = "Bits 47:32 of SHA-256 hash of boot key 0 (ECC)"] #[inline(always)] pub const fn bootkey0_2(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(260usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x0104usize) as _) } } #[doc = "Bits 63:48 of SHA-256 hash of boot key 0 (ECC)"] #[inline(always)] pub const fn bootkey0_3(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(262usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x0106usize) as _) } } #[doc = "Bits 79:64 of SHA-256 hash of boot key 0 (ECC)"] #[inline(always)] pub const fn bootkey0_4(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(264usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x0108usize) as _) } } #[doc = "Bits 95:80 of SHA-256 hash of boot key 0 (ECC)"] #[inline(always)] pub const fn bootkey0_5(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(266usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x010ausize) as _) } } #[doc = "Bits 111:96 of SHA-256 hash of boot key 0 (ECC)"] #[inline(always)] pub const fn bootkey0_6(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(268usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x010cusize) as _) } } #[doc = "Bits 127:112 of SHA-256 hash of boot key 0 (ECC)"] #[inline(always)] pub const fn bootkey0_7(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(270usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x010eusize) as _) } } #[doc = "Bits 143:128 of SHA-256 hash of boot key 0 (ECC)"] #[inline(always)] pub const fn bootkey0_8(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(272usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x0110usize) as _) } } #[doc = "Bits 159:144 of SHA-256 hash of boot key 0 (ECC)"] #[inline(always)] pub const fn bootkey0_9(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(274usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x0112usize) as _) } } #[doc = "Bits 175:160 of SHA-256 hash of boot key 0 (ECC)"] #[inline(always)] pub const fn bootkey0_10(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(276usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x0114usize) as _) } } #[doc = "Bits 191:176 of SHA-256 hash of boot key 0 (ECC)"] #[inline(always)] pub const fn bootkey0_11(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(278usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x0116usize) as _) } } #[doc = "Bits 207:192 of SHA-256 hash of boot key 0 (ECC)"] #[inline(always)] pub const fn bootkey0_12(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(280usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x0118usize) as _) } } #[doc = "Bits 223:208 of SHA-256 hash of boot key 0 (ECC)"] #[inline(always)] pub const fn bootkey0_13(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(282usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x011ausize) as _) } } #[doc = "Bits 239:224 of SHA-256 hash of boot key 0 (ECC)"] #[inline(always)] pub const fn bootkey0_14(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(284usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x011cusize) as _) } } #[doc = "Bits 255:240 of SHA-256 hash of boot key 0 (ECC)"] #[inline(always)] pub const fn bootkey0_15(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(286usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x011eusize) as _) } } #[doc = "Bits 15:0 of SHA-256 hash of boot key 1 (ECC)"] #[inline(always)] pub const fn bootkey1_0(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(288usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x0120usize) as _) } } #[doc = "Bits 31:16 of SHA-256 hash of boot key 1 (ECC)"] #[inline(always)] pub const fn bootkey1_1(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(290usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x0122usize) as _) } } #[doc = "Bits 47:32 of SHA-256 hash of boot key 1 (ECC)"] #[inline(always)] pub const fn bootkey1_2(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(292usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x0124usize) as _) } } #[doc = "Bits 63:48 of SHA-256 hash of boot key 1 (ECC)"] #[inline(always)] pub const fn bootkey1_3(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(294usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x0126usize) as _) } } #[doc = "Bits 79:64 of SHA-256 hash of boot key 1 (ECC)"] #[inline(always)] pub const fn bootkey1_4(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(296usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x0128usize) as _) } } #[doc = "Bits 95:80 of SHA-256 hash of boot key 1 (ECC)"] #[inline(always)] pub const fn bootkey1_5(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(298usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x012ausize) as _) } } #[doc = "Bits 111:96 of SHA-256 hash of boot key 1 (ECC)"] #[inline(always)] pub const fn bootkey1_6(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(300usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x012cusize) as _) } } #[doc = "Bits 127:112 of SHA-256 hash of boot key 1 (ECC)"] #[inline(always)] pub const fn bootkey1_7(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(302usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x012eusize) as _) } } #[doc = "Bits 143:128 of SHA-256 hash of boot key 1 (ECC)"] #[inline(always)] pub const fn bootkey1_8(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(304usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x0130usize) as _) } } #[doc = "Bits 159:144 of SHA-256 hash of boot key 1 (ECC)"] #[inline(always)] pub const fn bootkey1_9(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(306usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x0132usize) as _) } } #[doc = "Bits 175:160 of SHA-256 hash of boot key 1 (ECC)"] #[inline(always)] pub const fn bootkey1_10(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(308usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x0134usize) as _) } } #[doc = "Bits 191:176 of SHA-256 hash of boot key 1 (ECC)"] #[inline(always)] pub const fn bootkey1_11(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(310usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x0136usize) as _) } } #[doc = "Bits 207:192 of SHA-256 hash of boot key 1 (ECC)"] #[inline(always)] pub const fn bootkey1_12(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(312usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x0138usize) as _) } } #[doc = "Bits 223:208 of SHA-256 hash of boot key 1 (ECC)"] #[inline(always)] pub const fn bootkey1_13(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(314usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x013ausize) as _) } } #[doc = "Bits 239:224 of SHA-256 hash of boot key 1 (ECC)"] #[inline(always)] pub const fn bootkey1_14(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(316usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x013cusize) as _) } } #[doc = "Bits 255:240 of SHA-256 hash of boot key 1 (ECC)"] #[inline(always)] pub const fn bootkey1_15(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(318usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x013eusize) as _) } } #[doc = "Bits 15:0 of SHA-256 hash of boot key 2 (ECC)"] #[inline(always)] pub const fn bootkey2_0(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(320usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x0140usize) as _) } } #[doc = "Bits 31:16 of SHA-256 hash of boot key 2 (ECC)"] #[inline(always)] pub const fn bootkey2_1(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(322usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x0142usize) as _) } } #[doc = "Bits 47:32 of SHA-256 hash of boot key 2 (ECC)"] #[inline(always)] pub const fn bootkey2_2(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(324usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x0144usize) as _) } } #[doc = "Bits 63:48 of SHA-256 hash of boot key 2 (ECC)"] #[inline(always)] pub const fn bootkey2_3(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(326usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x0146usize) as _) } } #[doc = "Bits 79:64 of SHA-256 hash of boot key 2 (ECC)"] #[inline(always)] pub const fn bootkey2_4(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(328usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x0148usize) as _) } } #[doc = "Bits 95:80 of SHA-256 hash of boot key 2 (ECC)"] #[inline(always)] pub const fn bootkey2_5(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(330usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x014ausize) as _) } } #[doc = "Bits 111:96 of SHA-256 hash of boot key 2 (ECC)"] #[inline(always)] pub const fn bootkey2_6(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(332usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x014cusize) as _) } } #[doc = "Bits 127:112 of SHA-256 hash of boot key 2 (ECC)"] #[inline(always)] pub const fn bootkey2_7(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(334usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x014eusize) as _) } } #[doc = "Bits 143:128 of SHA-256 hash of boot key 2 (ECC)"] #[inline(always)] pub const fn bootkey2_8(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(336usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x0150usize) as _) } } #[doc = "Bits 159:144 of SHA-256 hash of boot key 2 (ECC)"] #[inline(always)] pub const fn bootkey2_9(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(338usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x0152usize) as _) } } #[doc = "Bits 175:160 of SHA-256 hash of boot key 2 (ECC)"] #[inline(always)] pub const fn bootkey2_10(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(340usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x0154usize) as _) } } #[doc = "Bits 191:176 of SHA-256 hash of boot key 2 (ECC)"] #[inline(always)] pub const fn bootkey2_11(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(342usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x0156usize) as _) } } #[doc = "Bits 207:192 of SHA-256 hash of boot key 2 (ECC)"] #[inline(always)] pub const fn bootkey2_12(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(344usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x0158usize) as _) } } #[doc = "Bits 223:208 of SHA-256 hash of boot key 2 (ECC)"] #[inline(always)] pub const fn bootkey2_13(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(346usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x015ausize) as _) } } #[doc = "Bits 239:224 of SHA-256 hash of boot key 2 (ECC)"] #[inline(always)] pub const fn bootkey2_14(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(348usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x015cusize) as _) } } #[doc = "Bits 255:240 of SHA-256 hash of boot key 2 (ECC)"] #[inline(always)] pub const fn bootkey2_15(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(350usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x015eusize) as _) } } #[doc = "Bits 15:0 of SHA-256 hash of boot key 3 (ECC)"] #[inline(always)] pub const fn bootkey3_0(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(352usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x0160usize) as _) } } #[doc = "Bits 31:16 of SHA-256 hash of boot key 3 (ECC)"] #[inline(always)] pub const fn bootkey3_1(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(354usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x0162usize) as _) } } #[doc = "Bits 47:32 of SHA-256 hash of boot key 3 (ECC)"] #[inline(always)] pub const fn bootkey3_2(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(356usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x0164usize) as _) } } #[doc = "Bits 63:48 of SHA-256 hash of boot key 3 (ECC)"] #[inline(always)] pub const fn bootkey3_3(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(358usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x0166usize) as _) } } #[doc = "Bits 79:64 of SHA-256 hash of boot key 3 (ECC)"] #[inline(always)] pub const fn bootkey3_4(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(360usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x0168usize) as _) } } #[doc = "Bits 95:80 of SHA-256 hash of boot key 3 (ECC)"] #[inline(always)] pub const fn bootkey3_5(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(362usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x016ausize) as _) } } #[doc = "Bits 111:96 of SHA-256 hash of boot key 3 (ECC)"] #[inline(always)] pub const fn bootkey3_6(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(364usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x016cusize) as _) } } #[doc = "Bits 127:112 of SHA-256 hash of boot key 3 (ECC)"] #[inline(always)] pub const fn bootkey3_7(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(366usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x016eusize) as _) } } #[doc = "Bits 143:128 of SHA-256 hash of boot key 3 (ECC)"] #[inline(always)] pub const fn bootkey3_8(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(368usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x0170usize) as _) } } #[doc = "Bits 159:144 of SHA-256 hash of boot key 3 (ECC)"] #[inline(always)] pub const fn bootkey3_9(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(370usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x0172usize) as _) } } #[doc = "Bits 175:160 of SHA-256 hash of boot key 3 (ECC)"] #[inline(always)] pub const fn bootkey3_10(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(372usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x0174usize) as _) } } #[doc = "Bits 191:176 of SHA-256 hash of boot key 3 (ECC)"] #[inline(always)] pub const fn bootkey3_11(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(374usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x0176usize) as _) } } #[doc = "Bits 207:192 of SHA-256 hash of boot key 3 (ECC)"] #[inline(always)] pub const fn bootkey3_12(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(376usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x0178usize) as _) } } #[doc = "Bits 223:208 of SHA-256 hash of boot key 3 (ECC)"] #[inline(always)] pub const fn bootkey3_13(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(378usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x017ausize) as _) } } #[doc = "Bits 239:224 of SHA-256 hash of boot key 3 (ECC)"] #[inline(always)] pub const fn bootkey3_14(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(380usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x017cusize) as _) } } #[doc = "Bits 255:240 of SHA-256 hash of boot key 3 (ECC)"] #[inline(always)] pub const fn bootkey3_15(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(382usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x017eusize) as _) } } #[doc = "Bits 15:0 of OTP access key 1 (ECC)"] #[inline(always)] pub const fn key1_0(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(7824usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x1e90usize) as _) } } #[doc = "Bits 31:16 of OTP access key 1 (ECC)"] #[inline(always)] pub const fn key1_1(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(7826usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x1e92usize) as _) } } #[doc = "Bits 47:32 of OTP access key 1 (ECC)"] #[inline(always)] pub const fn key1_2(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(7828usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x1e94usize) as _) } } #[doc = "Bits 63:48 of OTP access key 1 (ECC)"] #[inline(always)] pub const fn key1_3(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(7830usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x1e96usize) as _) } } #[doc = "Bits 79:64 of OTP access key 1 (ECC)"] #[inline(always)] pub const fn key1_4(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(7832usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x1e98usize) as _) } } #[doc = "Bits 95:80 of OTP access key 1 (ECC)"] #[inline(always)] pub const fn key1_5(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(7834usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x1e9ausize) as _) } } #[doc = "Bits 111:96 of OTP access key 1 (ECC)"] #[inline(always)] pub const fn key1_6(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(7836usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x1e9cusize) as _) } } #[doc = "Bits 127:112 of OTP access key 1 (ECC)"] #[inline(always)] pub const fn key1_7(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(7838usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x1e9eusize) as _) } } #[doc = "Bits 15:0 of OTP access key 2 (ECC)"] #[inline(always)] pub const fn key2_0(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(7840usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x1ea0usize) as _) } } #[doc = "Bits 31:16 of OTP access key 2 (ECC)"] #[inline(always)] pub const fn key2_1(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(7842usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x1ea2usize) as _) } } #[doc = "Bits 47:32 of OTP access key 2 (ECC)"] #[inline(always)] pub const fn key2_2(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(7844usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x1ea4usize) as _) } } #[doc = "Bits 63:48 of OTP access key 2 (ECC)"] #[inline(always)] pub const fn key2_3(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(7846usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x1ea6usize) as _) } } #[doc = "Bits 79:64 of OTP access key 2 (ECC)"] #[inline(always)] pub const fn key2_4(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(7848usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x1ea8usize) as _) } } #[doc = "Bits 95:80 of OTP access key 2 (ECC)"] #[inline(always)] pub const fn key2_5(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(7850usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x1eaausize) as _) } } #[doc = "Bits 111:96 of OTP access key 2 (ECC)"] #[inline(always)] pub const fn key2_6(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(7852usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x1eacusize) as _) } } #[doc = "Bits 127:112 of OTP access key 2 (ECC)"] #[inline(always)] pub const fn key2_7(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(7854usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x1eaeusize) as _) } } #[doc = "Bits 15:0 of OTP access key 3 (ECC)"] #[inline(always)] pub const fn key3_0(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(7856usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x1eb0usize) as _) } } #[doc = "Bits 31:16 of OTP access key 3 (ECC)"] #[inline(always)] pub const fn key3_1(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(7858usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x1eb2usize) as _) } } #[doc = "Bits 47:32 of OTP access key 3 (ECC)"] #[inline(always)] pub const fn key3_2(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(7860usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x1eb4usize) as _) } } #[doc = "Bits 63:48 of OTP access key 3 (ECC)"] #[inline(always)] pub const fn key3_3(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(7862usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x1eb6usize) as _) } } #[doc = "Bits 79:64 of OTP access key 3 (ECC)"] #[inline(always)] pub const fn key3_4(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(7864usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x1eb8usize) as _) } } #[doc = "Bits 95:80 of OTP access key 3 (ECC)"] #[inline(always)] pub const fn key3_5(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(7866usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x1ebausize) as _) } } #[doc = "Bits 111:96 of OTP access key 3 (ECC)"] #[inline(always)] pub const fn key3_6(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(7868usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x1ebcusize) as _) } } #[doc = "Bits 127:112 of OTP access key 3 (ECC)"] #[inline(always)] pub const fn key3_7(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(7870usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x1ebeusize) as _) } } #[doc = "Bits 15:0 of OTP access key 4 (ECC)"] #[inline(always)] pub const fn key4_0(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(7872usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x1ec0usize) as _) } } #[doc = "Bits 31:16 of OTP access key 4 (ECC)"] #[inline(always)] pub const fn key4_1(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(7874usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x1ec2usize) as _) } } #[doc = "Bits 47:32 of OTP access key 4 (ECC)"] #[inline(always)] pub const fn key4_2(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(7876usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x1ec4usize) as _) } } #[doc = "Bits 63:48 of OTP access key 4 (ECC)"] #[inline(always)] pub const fn key4_3(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(7878usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x1ec6usize) as _) } } #[doc = "Bits 79:64 of OTP access key 4 (ECC)"] #[inline(always)] pub const fn key4_4(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(7880usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x1ec8usize) as _) } } #[doc = "Bits 95:80 of OTP access key 4 (ECC)"] #[inline(always)] pub const fn key4_5(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(7882usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x1ecausize) as _) } } #[doc = "Bits 111:96 of OTP access key 4 (ECC)"] #[inline(always)] pub const fn key4_6(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(7884usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x1eccusize) as _) } } #[doc = "Bits 127:112 of OTP access key 4 (ECC)"] #[inline(always)] pub const fn key4_7(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(7886usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x1eceusize) as _) } } #[doc = "Bits 15:0 of OTP access key 5 (ECC)"] #[inline(always)] pub const fn key5_0(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(7888usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x1ed0usize) as _) } } #[doc = "Bits 31:16 of OTP access key 5 (ECC)"] #[inline(always)] pub const fn key5_1(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(7890usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x1ed2usize) as _) } } #[doc = "Bits 47:32 of OTP access key 5 (ECC)"] #[inline(always)] pub const fn key5_2(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(7892usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x1ed4usize) as _) } } #[doc = "Bits 63:48 of OTP access key 5 (ECC)"] #[inline(always)] pub const fn key5_3(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(7894usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x1ed6usize) as _) } } #[doc = "Bits 79:64 of OTP access key 5 (ECC)"] #[inline(always)] pub const fn key5_4(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(7896usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x1ed8usize) as _) } } #[doc = "Bits 95:80 of OTP access key 5 (ECC)"] #[inline(always)] pub const fn key5_5(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(7898usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x1edausize) as _) } } #[doc = "Bits 111:96 of OTP access key 5 (ECC)"] #[inline(always)] pub const fn key5_6(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(7900usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x1edcusize) as _) } } #[doc = "Bits 127:112 of OTP access key 5 (ECC)"] #[inline(always)] pub const fn key5_7(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(7902usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x1edeusize) as _) } } #[doc = "Bits 15:0 of OTP access key 6 (ECC)"] #[inline(always)] pub const fn key6_0(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(7904usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x1ee0usize) as _) } } #[doc = "Bits 31:16 of OTP access key 6 (ECC)"] #[inline(always)] pub const fn key6_1(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(7906usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x1ee2usize) as _) } } #[doc = "Bits 47:32 of OTP access key 6 (ECC)"] #[inline(always)] pub const fn key6_2(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(7908usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x1ee4usize) as _) } } #[doc = "Bits 63:48 of OTP access key 6 (ECC)"] #[inline(always)] pub const fn key6_3(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(7910usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x1ee6usize) as _) } } #[doc = "Bits 79:64 of OTP access key 6 (ECC)"] #[inline(always)] pub const fn key6_4(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(7912usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x1ee8usize) as _) } } #[doc = "Bits 95:80 of OTP access key 6 (ECC)"] #[inline(always)] pub const fn key6_5(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(7914usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x1eeausize) as _) } } #[doc = "Bits 111:96 of OTP access key 6 (ECC)"] #[inline(always)] pub const fn key6_6(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(7916usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x1eecusize) as _) } } #[doc = "Bits 127:112 of OTP access key 6 (ECC)"] #[inline(always)] pub const fn key6_7(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(7918usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x1eeeusize) as _) } } } pub mod regs; diff --git a/src/rp235x/otp_data/vals.rs b/src/rp235x/otp_data/vals.rs index 68e29e02..70b21e6a 100644 --- a/src/rp235x/otp_data/vals.rs +++ b/src/rp235x/otp_data/vals.rs @@ -1,7 +1,7 @@ #[repr(u8)] #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] pub enum Cs0size { - NONE = 0, + NONE = 0x0, _8K = 0x01, _16K = 0x02, _32K = 0x03, @@ -43,7 +43,7 @@ impl From for u8 { #[repr(u8)] #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] pub enum Cs1size { - NONE = 0, + NONE = 0x0, _8K = 0x01, _16K = 0x02, _32K = 0x03, @@ -85,7 +85,7 @@ impl From for u8 { #[repr(u8)] #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] pub enum Range { - _1_15MHZ = 0, + _1_15MHZ = 0x0, _10_30MHZ = 0x01, _25_60MHZ = 0x02, _40_100MHZ = 0x03, @@ -116,7 +116,7 @@ impl From for u8 { #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] pub struct UsbWhiteLabelAddr(pub u16); impl UsbWhiteLabelAddr { - pub const INDEX_USB_DEVICE_VID_VALUE: Self = Self(0); + pub const INDEX_USB_DEVICE_VID_VALUE: Self = Self(0x0); pub const INDEX_USB_DEVICE_PID_VALUE: Self = Self(0x01); pub const INDEX_USB_DEVICE_BCD_DEVICE_VALUE: Self = Self(0x02); pub const INDEX_USB_DEVICE_LANG_ID_VALUE: Self = Self(0x03); diff --git a/src/rp235x/otp_data_raw.rs b/src/rp235x/otp_data_raw.rs index 6d5c4953..9646bfe6 100644 --- a/src/rp235x/otp_data_raw.rs +++ b/src/rp235x/otp_data_raw.rs @@ -1,3 +1,155 @@ +#[derive(Copy, Clone, Eq, PartialEq)] +pub struct BootKey { + ptr: *mut u8, +} +unsafe impl Send for BootKey {} +unsafe impl Sync for BootKey {} +impl BootKey { + #[inline(always)] + pub const unsafe fn from_ptr(ptr: *mut ()) -> Self { + Self { ptr: ptr as _ } + } + #[inline(always)] + pub const fn as_ptr(&self) -> *mut () { + self.ptr as _ + } + #[doc = "Bits 15:0 of SHA-256 hash of boot key 1 (ECC)"] + #[inline(always)] + pub const fn part0(self) -> crate::common::Reg { + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x0usize) as _) } + } + #[doc = "Bits 31:16 of SHA-256 hash of boot key 1 (ECC)"] + #[inline(always)] + pub const fn part1(self) -> crate::common::Reg { + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x04usize) as _) } + } + #[doc = "Bits 47:32 of SHA-256 hash of boot key 1 (ECC)"] + #[inline(always)] + pub const fn part2(self) -> crate::common::Reg { + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x08usize) as _) } + } + #[doc = "Bits 63:48 of SHA-256 hash of boot key 1 (ECC)"] + #[inline(always)] + pub const fn part3(self) -> crate::common::Reg { + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x0cusize) as _) } + } + #[doc = "Bits 79:64 of SHA-256 hash of boot key 1 (ECC)"] + #[inline(always)] + pub const fn part4(self) -> crate::common::Reg { + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x10usize) as _) } + } + #[doc = "Bits 95:80 of SHA-256 hash of boot key 1 (ECC)"] + #[inline(always)] + pub const fn part5(self) -> crate::common::Reg { + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x14usize) as _) } + } + #[doc = "Bits 111:96 of SHA-256 hash of boot key 1 (ECC)"] + #[inline(always)] + pub const fn part6(self) -> crate::common::Reg { + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x18usize) as _) } + } + #[doc = "Bits 127:112 of SHA-256 hash of boot key 1 (ECC)"] + #[inline(always)] + pub const fn part7(self) -> crate::common::Reg { + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x1cusize) as _) } + } + #[doc = "Bits 143:128 of SHA-256 hash of boot key 1 (ECC)"] + #[inline(always)] + pub const fn part8(self) -> crate::common::Reg { + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x20usize) as _) } + } + #[doc = "Bits 159:144 of SHA-256 hash of boot key 1 (ECC)"] + #[inline(always)] + pub const fn part9(self) -> crate::common::Reg { + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x24usize) as _) } + } + #[doc = "Bits 175:160 of SHA-256 hash of boot key 1 (ECC)"] + #[inline(always)] + pub const fn part10(self) -> crate::common::Reg { + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x28usize) as _) } + } + #[doc = "Bits 191:176 of SHA-256 hash of boot key 1 (ECC)"] + #[inline(always)] + pub const fn part11(self) -> crate::common::Reg { + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x2cusize) as _) } + } + #[doc = "Bits 207:192 of SHA-256 hash of boot key 1 (ECC)"] + #[inline(always)] + pub const fn part12(self) -> crate::common::Reg { + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x30usize) as _) } + } + #[doc = "Bits 223:208 of SHA-256 hash of boot key 1 (ECC)"] + #[inline(always)] + pub const fn part13(self) -> crate::common::Reg { + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x34usize) as _) } + } + #[doc = "Bits 239:224 of SHA-256 hash of boot key 1 (ECC)"] + #[inline(always)] + pub const fn part14(self) -> crate::common::Reg { + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x38usize) as _) } + } + #[doc = "Bits 255:240 of SHA-256 hash of boot key 1 (ECC)"] + #[inline(always)] + pub const fn part15(self) -> crate::common::Reg { + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x3cusize) as _) } + } +} +#[derive(Copy, Clone, Eq, PartialEq)] +pub struct Key { + ptr: *mut u8, +} +unsafe impl Send for Key {} +unsafe impl Sync for Key {} +impl Key { + #[inline(always)] + pub const unsafe fn from_ptr(ptr: *mut ()) -> Self { + Self { ptr: ptr as _ } + } + #[inline(always)] + pub const fn as_ptr(&self) -> *mut () { + self.ptr as _ + } + #[doc = "Bits 15:0 of OTP access key 1 (ECC)"] + #[inline(always)] + pub const fn part0(self) -> crate::common::Reg { + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x0usize) as _) } + } + #[doc = "Bits 31:16 of OTP access key 1 (ECC)"] + #[inline(always)] + pub const fn part1(self) -> crate::common::Reg { + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x04usize) as _) } + } + #[doc = "Bits 47:32 of OTP access key 1 (ECC)"] + #[inline(always)] + pub const fn part2(self) -> crate::common::Reg { + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x08usize) as _) } + } + #[doc = "Bits 63:48 of OTP access key 1 (ECC)"] + #[inline(always)] + pub const fn part3(self) -> crate::common::Reg { + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x0cusize) as _) } + } + #[doc = "Bits 79:64 of OTP access key 1 (ECC)"] + #[inline(always)] + pub const fn part4(self) -> crate::common::Reg { + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x10usize) as _) } + } + #[doc = "Bits 95:80 of OTP access key 1 (ECC)"] + #[inline(always)] + pub const fn part5(self) -> crate::common::Reg { + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x14usize) as _) } + } + #[doc = "Bits 111:96 of OTP access key 1 (ECC)"] + #[inline(always)] + pub const fn part6(self) -> crate::common::Reg { + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x18usize) as _) } + } + #[doc = "Bits 127:112 of OTP access key 1 (ECC)"] + #[inline(always)] + pub const fn part7(self) -> crate::common::Reg { + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x1cusize) as _) } + } +} #[doc = "Predefined OTP data layout for RP2350"] #[derive(Copy, Clone, Eq, PartialEq)] pub struct OtpDataRaw { @@ -16,1557 +168,351 @@ impl OtpDataRaw { } #[doc = "Bits 15:0 of public device ID. (ECC) The CHIPID0..3 rows contain a 64-bit random identifier for this chip, which can be read from the USB bootloader PICOBOOT interface or from the get_sys_info ROM API. The number of random bits makes the occurrence of twins exceedingly unlikely: for example, a fleet of a hundred million devices has a 99.97% probability of no twinned IDs. This is estimated to be lower than the occurrence of process errors in the assignment of sequential random IDs, and for practical purposes CHIPID may be treated as unique."] #[inline(always)] - pub const fn chipid0(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(0usize) as _) } + pub const fn chipid0(self) -> crate::common::Reg { + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x0usize) as _) } } #[doc = "Bits 31:16 of public device ID (ECC)"] #[inline(always)] - pub const fn chipid1(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(4usize) as _) } + pub const fn chipid1(self) -> crate::common::Reg { + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x04usize) as _) } } #[doc = "Bits 47:32 of public device ID (ECC)"] #[inline(always)] - pub const fn chipid2(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(8usize) as _) } + pub const fn chipid2(self) -> crate::common::Reg { + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x08usize) as _) } } #[doc = "Bits 63:48 of public device ID (ECC)"] #[inline(always)] - pub const fn chipid3(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(12usize) as _) } + pub const fn chipid3(self) -> crate::common::Reg { + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x0cusize) as _) } } #[doc = "Bits 15:0 of private per-device random number (ECC) The RANDID0..7 rows form a 128-bit random number generated during device test. This ID is not exposed through the USB PICOBOOT GET_INFO command or the ROM `get_sys_info()` API. However note that the USB PICOBOOT OTP access point can read the entirety of page 0, so this value is not meaningfully private unless the USB PICOBOOT interface is disabled via the DISABLE_BOOTSEL_USB_PICOBOOT_IFC flag in BOOT_FLAGS0."] #[inline(always)] - pub const fn randid0(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(16usize) as _) } + pub const fn randid0(self) -> crate::common::Reg { + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x10usize) as _) } } #[doc = "Bits 31:16 of private per-device random number (ECC)"] #[inline(always)] - pub const fn randid1(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(20usize) as _) } + pub const fn randid1(self) -> crate::common::Reg { + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x14usize) as _) } } #[doc = "Bits 47:32 of private per-device random number (ECC)"] #[inline(always)] - pub const fn randid2(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(24usize) as _) } + pub const fn randid2(self) -> crate::common::Reg { + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x18usize) as _) } } #[doc = "Bits 63:48 of private per-device random number (ECC)"] #[inline(always)] - pub const fn randid3(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(28usize) as _) } + pub const fn randid3(self) -> crate::common::Reg { + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x1cusize) as _) } } #[doc = "Bits 79:64 of private per-device random number (ECC)"] #[inline(always)] - pub const fn randid4(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(32usize) as _) } + pub const fn randid4(self) -> crate::common::Reg { + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x20usize) as _) } } #[doc = "Bits 95:80 of private per-device random number (ECC)"] #[inline(always)] - pub const fn randid5(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(36usize) as _) } + pub const fn randid5(self) -> crate::common::Reg { + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x24usize) as _) } } #[doc = "Bits 111:96 of private per-device random number (ECC)"] #[inline(always)] - pub const fn randid6(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(40usize) as _) } + pub const fn randid6(self) -> crate::common::Reg { + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x28usize) as _) } } #[doc = "Bits 127:112 of private per-device random number (ECC)"] #[inline(always)] - pub const fn randid7(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(44usize) as _) } + pub const fn randid7(self) -> crate::common::Reg { + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x2cusize) as _) } } #[doc = "Ring oscillator frequency in kHz, measured during manufacturing (ECC) This is measured at 1.1 V, at room temperature, with the ROSC configuration registers in their reset state."] #[inline(always)] - pub const fn rosc_calib(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(64usize) as _) } + pub const fn rosc_calib(self) -> crate::common::Reg { + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x40usize) as _) } } #[doc = "Low-power oscillator frequency in Hz, measured during manufacturing (ECC) This is measured at 1.1V, at room temperature, with the LPOSC trim register in its reset state."] #[inline(always)] - pub const fn lposc_calib(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(68usize) as _) } + pub const fn lposc_calib(self) -> crate::common::Reg { + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x44usize) as _) } } #[doc = "The number of main user GPIOs (bank 0). Should read 48 in the QFN80 package, and 30 in the QFN60 package. (ECC)"] #[inline(always)] - pub const fn num_gpios(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(96usize) as _) } + pub const fn num_gpios(self) -> crate::common::Reg { + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x60usize) as _) } } #[doc = "Lower 16 bits of CRC32 of OTP addresses 0x00 through 0x6b (polynomial 0x4c11db7, input reflected, output reflected, seed all-ones, final XOR all-ones) (ECC)"] #[inline(always)] - pub const fn info_crc0(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(216usize) as _) } + pub const fn info_crc0(self) -> crate::common::Reg { + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0xd8usize) as _) } } #[doc = "Upper 16 bits of CRC32 of OTP addresses 0x00 through 0x6b (ECC)"] #[inline(always)] - pub const fn info_crc1(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(220usize) as _) } + pub const fn info_crc1(self) -> crate::common::Reg { + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0xdcusize) as _) } } #[doc = "Page 0 critical boot flags (RBIT-8)"] #[inline(always)] pub const fn crit0(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(224usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0xe0usize) as _) } } #[doc = "Redundant copy of CRIT0"] #[inline(always)] - pub const fn crit0_r1(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(228usize) as _) } + pub const fn crit0_r1(self) -> crate::common::Reg { + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0xe4usize) as _) } } #[doc = "Redundant copy of CRIT0"] #[inline(always)] - pub const fn crit0_r2(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(232usize) as _) } + pub const fn crit0_r2(self) -> crate::common::Reg { + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0xe8usize) as _) } } #[doc = "Redundant copy of CRIT0"] #[inline(always)] - pub const fn crit0_r3(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(236usize) as _) } + pub const fn crit0_r3(self) -> crate::common::Reg { + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0xecusize) as _) } } #[doc = "Redundant copy of CRIT0"] #[inline(always)] - pub const fn crit0_r4(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(240usize) as _) } + pub const fn crit0_r4(self) -> crate::common::Reg { + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0xf0usize) as _) } } #[doc = "Redundant copy of CRIT0"] #[inline(always)] - pub const fn crit0_r5(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(244usize) as _) } + pub const fn crit0_r5(self) -> crate::common::Reg { + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0xf4usize) as _) } } #[doc = "Redundant copy of CRIT0"] #[inline(always)] - pub const fn crit0_r6(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(248usize) as _) } + pub const fn crit0_r6(self) -> crate::common::Reg { + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0xf8usize) as _) } } #[doc = "Redundant copy of CRIT0"] #[inline(always)] - pub const fn crit0_r7(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(252usize) as _) } + pub const fn crit0_r7(self) -> crate::common::Reg { + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0xfcusize) as _) } } #[doc = "Page 1 critical boot flags (RBIT-8)"] #[inline(always)] pub const fn crit1(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(256usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x0100usize) as _) } } #[doc = "Redundant copy of CRIT1"] #[inline(always)] - pub const fn crit1_r1(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(260usize) as _) } + pub const fn crit1_r1(self) -> crate::common::Reg { + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x0104usize) as _) } } #[doc = "Redundant copy of CRIT1"] #[inline(always)] - pub const fn crit1_r2(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(264usize) as _) } + pub const fn crit1_r2(self) -> crate::common::Reg { + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x0108usize) as _) } } #[doc = "Redundant copy of CRIT1"] #[inline(always)] - pub const fn crit1_r3(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(268usize) as _) } + pub const fn crit1_r3(self) -> crate::common::Reg { + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x010cusize) as _) } } #[doc = "Redundant copy of CRIT1"] #[inline(always)] - pub const fn crit1_r4(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(272usize) as _) } + pub const fn crit1_r4(self) -> crate::common::Reg { + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x0110usize) as _) } } #[doc = "Redundant copy of CRIT1"] #[inline(always)] - pub const fn crit1_r5(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(276usize) as _) } + pub const fn crit1_r5(self) -> crate::common::Reg { + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x0114usize) as _) } } #[doc = "Redundant copy of CRIT1"] #[inline(always)] - pub const fn crit1_r6(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(280usize) as _) } + pub const fn crit1_r6(self) -> crate::common::Reg { + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x0118usize) as _) } } #[doc = "Redundant copy of CRIT1"] #[inline(always)] - pub const fn crit1_r7(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(284usize) as _) } + pub const fn crit1_r7(self) -> crate::common::Reg { + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x011cusize) as _) } } #[doc = "Disable/Enable boot paths/features in the RP2350 mask ROM. Disables always supersede enables. Enables are provided where there are other configurations in OTP that must be valid. (RBIT-3)"] #[inline(always)] pub const fn boot_flags0(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(288usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x0120usize) as _) } } #[doc = "Redundant copy of BOOT_FLAGS0"] #[inline(always)] - pub const fn boot_flags0_r1( - self, - ) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(292usize) as _) } + pub const fn boot_flags0_r1(self) -> crate::common::Reg { + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x0124usize) as _) } } #[doc = "Redundant copy of BOOT_FLAGS0"] #[inline(always)] - pub const fn boot_flags0_r2( - self, - ) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(296usize) as _) } + pub const fn boot_flags0_r2(self) -> crate::common::Reg { + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x0128usize) as _) } } #[doc = "Disable/Enable boot paths/features in the RP2350 mask ROM. Disables always supersede enables. Enables are provided where there are other configurations in OTP that must be valid. (RBIT-3)"] #[inline(always)] pub const fn boot_flags1(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(300usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x012cusize) as _) } } #[doc = "Redundant copy of BOOT_FLAGS1"] #[inline(always)] - pub const fn boot_flags1_r1( - self, - ) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(304usize) as _) } + pub const fn boot_flags1_r1(self) -> crate::common::Reg { + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x0130usize) as _) } } #[doc = "Redundant copy of BOOT_FLAGS1"] #[inline(always)] - pub const fn boot_flags1_r2( - self, - ) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(308usize) as _) } + pub const fn boot_flags1_r2(self) -> crate::common::Reg { + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x0134usize) as _) } } #[doc = "Default boot version thermometer counter, bits 23:0 (RBIT-3)"] #[inline(always)] - pub const fn default_boot_version0( - self, - ) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(312usize) as _) } + pub const fn default_boot_version0(self) -> crate::common::Reg { + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x0138usize) as _) } } #[doc = "Redundant copy of DEFAULT_BOOT_VERSION0"] #[inline(always)] - pub const fn default_boot_version0_r1( - self, - ) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(316usize) as _) } + pub const fn default_boot_version0_r1(self) -> crate::common::Reg { + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x013cusize) as _) } } #[doc = "Redundant copy of DEFAULT_BOOT_VERSION0"] #[inline(always)] - pub const fn default_boot_version0_r2( - self, - ) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(320usize) as _) } + pub const fn default_boot_version0_r2(self) -> crate::common::Reg { + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x0140usize) as _) } } #[doc = "Default boot version thermometer counter, bits 47:24 (RBIT-3)"] #[inline(always)] - pub const fn default_boot_version1( - self, - ) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(324usize) as _) } + pub const fn default_boot_version1(self) -> crate::common::Reg { + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x0144usize) as _) } } #[doc = "Redundant copy of DEFAULT_BOOT_VERSION1"] #[inline(always)] - pub const fn default_boot_version1_r1( - self, - ) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(328usize) as _) } + pub const fn default_boot_version1_r1(self) -> crate::common::Reg { + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x0148usize) as _) } } #[doc = "Redundant copy of DEFAULT_BOOT_VERSION1"] #[inline(always)] - pub const fn default_boot_version1_r2( - self, - ) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(332usize) as _) } + pub const fn default_boot_version1_r2(self) -> crate::common::Reg { + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x014cusize) as _) } } #[doc = "Stores information about external flash device(s). (ECC) Assumed to be valid if BOOT_FLAGS0_FLASH_DEVINFO_ENABLE is set."] #[inline(always)] pub const fn flash_devinfo(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(336usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x0150usize) as _) } } #[doc = "Gap between partition table slot 0 and slot 1 at the start of flash (the default size is 4096 bytes) (ECC) Enabled by the OVERRIDE_FLASH_PARTITION_SLOT_SIZE bit in BOOT_FLAGS, the size is 4096 * (value + 1)"] #[inline(always)] - pub const fn flash_partition_slot_size( - self, - ) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(340usize) as _) } + pub const fn flash_partition_slot_size(self) -> crate::common::Reg { + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x0154usize) as _) } } #[doc = "Pin configuration for LED status, used by USB bootloader. (ECC) Must be valid if BOOT_FLAGS0_ENABLE_BOOTSEL_LED is set."] #[inline(always)] pub const fn bootsel_led_cfg( self, ) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(344usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x0158usize) as _) } } #[doc = "Optional PLL configuration for BOOTSEL mode. (ECC) This should be configured to produce an exact 48 MHz based on the crystal oscillator frequency. User mode software may also use this value to calculate the expected crystal frequency based on an assumed 48 MHz PLL output. If no configuration is given, the crystal is assumed to be 12 MHz. The PLL frequency can be calculated as: PLL out = (XOSC frequency / (REFDIV+1)) x FBDIV / (POSTDIV1 x POSTDIV2) Conversely the crystal frequency can be calculated as: XOSC frequency = 48 MHz x (REFDIV+1) x (POSTDIV1 x POSTDIV2) / FBDIV (Note the +1 on REFDIV is because the value stored in this OTP location is the actual divisor value minus one.) Used if and only if ENABLE_BOOTSEL_NON_DEFAULT_PLL_XOSC_CFG is set in BOOT_FLAGS0. That bit should be set only after this row and BOOTSEL_XOSC_CFG are both correctly programmed."] #[inline(always)] pub const fn bootsel_pll_cfg( self, ) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(348usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x015cusize) as _) } } #[doc = "Non-default crystal oscillator configuration for the USB bootloader. (ECC) These values may also be used by user code configuring the crystal oscillator. Used if and only if ENABLE_BOOTSEL_NON_DEFAULT_PLL_XOSC_CFG is set in BOOT_FLAGS0. That bit should be set only after this row and BOOTSEL_PLL_CFG are both correctly programmed."] #[inline(always)] pub const fn bootsel_xosc_cfg( self, ) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(352usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x0160usize) as _) } } #[doc = "USB boot specific feature flags (RBIT-3)"] #[inline(always)] pub const fn usb_boot_flags(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(356usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x0164usize) as _) } } #[doc = "Redundant copy of USB_BOOT_FLAGS"] #[inline(always)] - pub const fn usb_boot_flags_r1( - self, - ) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(360usize) as _) } + pub const fn usb_boot_flags_r1(self) -> crate::common::Reg { + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x0168usize) as _) } } #[doc = "Redundant copy of USB_BOOT_FLAGS"] #[inline(always)] - pub const fn usb_boot_flags_r2( - self, - ) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(364usize) as _) } + pub const fn usb_boot_flags_r2(self) -> crate::common::Reg { + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x016cusize) as _) } } #[doc = "Row index of the USB_WHITE_LABEL structure within OTP (ECC) The table has 16 rows, each of which are also ECC and marked valid by the corresponding valid bit in USB_BOOT_FLAGS (ECC). The entries are either _VALUEs where the 16 bit value is used as is, or _STRDEFs which acts as a pointers to a string value. The value stored in a _STRDEF is two separate bytes: The low seven bits of the first (LSB) byte indicates the number of characters in the string, and the top bit of the first (LSB) byte if set to indicate that each character in the string is two bytes (Unicode) versus one byte if unset. The second (MSB) byte represents the location of the string data, and is encoded as the number of rows from this USB_WHITE_LABEL_ADDR; i.e. the row of the start of the string is USB_WHITE_LABEL_ADDR value + msb_byte. In each case, the corresponding valid bit enables replacing the default value for the corresponding item provided by the boot rom. Note that Unicode _STRDEFs are only supported for USB_DEVICE_PRODUCT_STRDEF, USB_DEVICE_SERIAL_NUMBER_STRDEF and USB_DEVICE_MANUFACTURER_STRDEF. Unicode values will be ignored if specified for other fields, and non-unicode values for these three items will be converted to Unicode characters by setting the upper 8 bits to zero. Note that if the USB_WHITE_LABEL structure or the corresponding strings are not readable by BOOTSEL mode based on OTP permissions, or if alignment requirements are not met, then the corresponding default values are used. The index values indicate where each field is located (row USB_WHITE_LABEL_ADDR value + index):"] #[inline(always)] pub const fn usb_white_label_addr( self, ) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(368usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x0170usize) as _) } } #[doc = "OTP start row for the OTP boot image. (ECC) If OTP boot is enabled, the bootrom will load from this location into SRAM and then directly enter the loaded image. Note that the image must be signed if SECURE_BOOT_ENABLE is set. The image itself is assumed to be ECC-protected. This must be an even number. Equivalently, the OTP boot image must start at a word-aligned location in the ECC read data address window."] #[inline(always)] - pub const fn otpboot_src(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(376usize) as _) } + pub const fn otpboot_src(self) -> crate::common::Reg { + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x0178usize) as _) } } #[doc = "Length in rows of the OTP boot image. (ECC) OTPBOOT_LEN must be even. The total image size must be a multiple of 4 bytes (32 bits)."] #[inline(always)] - pub const fn otpboot_len(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(380usize) as _) } + pub const fn otpboot_len(self) -> crate::common::Reg { + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x017cusize) as _) } } #[doc = "Bits 15:0 of the OTP boot image load destination (and entry point). (ECC) This must be a location in main SRAM (main SRAM is addresses 0x20000000 through 0x20082000) and must be word-aligned."] #[inline(always)] - pub const fn otpboot_dst0(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(384usize) as _) } + pub const fn otpboot_dst0(self) -> crate::common::Reg { + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x0180usize) as _) } } #[doc = "Bits 31:16 of the OTP boot image load destination (and entry point). (ECC) This must be a location in main SRAM (main SRAM is addresses 0x20000000 through 0x20082000) and must be word-aligned."] #[inline(always)] - pub const fn otpboot_dst1(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(388usize) as _) } - } - #[doc = "Bits 15:0 of SHA-256 hash of boot key 0 (ECC)"] - #[inline(always)] - pub const fn bootkey0_0(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(512usize) as _) } - } - #[doc = "Bits 31:16 of SHA-256 hash of boot key 0 (ECC)"] - #[inline(always)] - pub const fn bootkey0_1(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(516usize) as _) } - } - #[doc = "Bits 47:32 of SHA-256 hash of boot key 0 (ECC)"] - #[inline(always)] - pub const fn bootkey0_2(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(520usize) as _) } - } - #[doc = "Bits 63:48 of SHA-256 hash of boot key 0 (ECC)"] - #[inline(always)] - pub const fn bootkey0_3(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(524usize) as _) } - } - #[doc = "Bits 79:64 of SHA-256 hash of boot key 0 (ECC)"] - #[inline(always)] - pub const fn bootkey0_4(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(528usize) as _) } - } - #[doc = "Bits 95:80 of SHA-256 hash of boot key 0 (ECC)"] - #[inline(always)] - pub const fn bootkey0_5(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(532usize) as _) } - } - #[doc = "Bits 111:96 of SHA-256 hash of boot key 0 (ECC)"] - #[inline(always)] - pub const fn bootkey0_6(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(536usize) as _) } - } - #[doc = "Bits 127:112 of SHA-256 hash of boot key 0 (ECC)"] - #[inline(always)] - pub const fn bootkey0_7(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(540usize) as _) } - } - #[doc = "Bits 143:128 of SHA-256 hash of boot key 0 (ECC)"] - #[inline(always)] - pub const fn bootkey0_8(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(544usize) as _) } - } - #[doc = "Bits 159:144 of SHA-256 hash of boot key 0 (ECC)"] - #[inline(always)] - pub const fn bootkey0_9(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(548usize) as _) } - } - #[doc = "Bits 175:160 of SHA-256 hash of boot key 0 (ECC)"] - #[inline(always)] - pub const fn bootkey0_10(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(552usize) as _) } - } - #[doc = "Bits 191:176 of SHA-256 hash of boot key 0 (ECC)"] - #[inline(always)] - pub const fn bootkey0_11(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(556usize) as _) } - } - #[doc = "Bits 207:192 of SHA-256 hash of boot key 0 (ECC)"] - #[inline(always)] - pub const fn bootkey0_12(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(560usize) as _) } - } - #[doc = "Bits 223:208 of SHA-256 hash of boot key 0 (ECC)"] - #[inline(always)] - pub const fn bootkey0_13(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(564usize) as _) } - } - #[doc = "Bits 239:224 of SHA-256 hash of boot key 0 (ECC)"] - #[inline(always)] - pub const fn bootkey0_14(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(568usize) as _) } - } - #[doc = "Bits 255:240 of SHA-256 hash of boot key 0 (ECC)"] - #[inline(always)] - pub const fn bootkey0_15(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(572usize) as _) } - } - #[doc = "Bits 15:0 of SHA-256 hash of boot key 1 (ECC)"] - #[inline(always)] - pub const fn bootkey1_0(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(576usize) as _) } - } - #[doc = "Bits 31:16 of SHA-256 hash of boot key 1 (ECC)"] - #[inline(always)] - pub const fn bootkey1_1(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(580usize) as _) } - } - #[doc = "Bits 47:32 of SHA-256 hash of boot key 1 (ECC)"] - #[inline(always)] - pub const fn bootkey1_2(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(584usize) as _) } - } - #[doc = "Bits 63:48 of SHA-256 hash of boot key 1 (ECC)"] - #[inline(always)] - pub const fn bootkey1_3(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(588usize) as _) } - } - #[doc = "Bits 79:64 of SHA-256 hash of boot key 1 (ECC)"] - #[inline(always)] - pub const fn bootkey1_4(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(592usize) as _) } - } - #[doc = "Bits 95:80 of SHA-256 hash of boot key 1 (ECC)"] - #[inline(always)] - pub const fn bootkey1_5(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(596usize) as _) } - } - #[doc = "Bits 111:96 of SHA-256 hash of boot key 1 (ECC)"] - #[inline(always)] - pub const fn bootkey1_6(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(600usize) as _) } - } - #[doc = "Bits 127:112 of SHA-256 hash of boot key 1 (ECC)"] - #[inline(always)] - pub const fn bootkey1_7(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(604usize) as _) } - } - #[doc = "Bits 143:128 of SHA-256 hash of boot key 1 (ECC)"] - #[inline(always)] - pub const fn bootkey1_8(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(608usize) as _) } - } - #[doc = "Bits 159:144 of SHA-256 hash of boot key 1 (ECC)"] - #[inline(always)] - pub const fn bootkey1_9(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(612usize) as _) } - } - #[doc = "Bits 175:160 of SHA-256 hash of boot key 1 (ECC)"] - #[inline(always)] - pub const fn bootkey1_10(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(616usize) as _) } - } - #[doc = "Bits 191:176 of SHA-256 hash of boot key 1 (ECC)"] - #[inline(always)] - pub const fn bootkey1_11(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(620usize) as _) } - } - #[doc = "Bits 207:192 of SHA-256 hash of boot key 1 (ECC)"] - #[inline(always)] - pub const fn bootkey1_12(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(624usize) as _) } - } - #[doc = "Bits 223:208 of SHA-256 hash of boot key 1 (ECC)"] - #[inline(always)] - pub const fn bootkey1_13(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(628usize) as _) } - } - #[doc = "Bits 239:224 of SHA-256 hash of boot key 1 (ECC)"] - #[inline(always)] - pub const fn bootkey1_14(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(632usize) as _) } - } - #[doc = "Bits 255:240 of SHA-256 hash of boot key 1 (ECC)"] - #[inline(always)] - pub const fn bootkey1_15(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(636usize) as _) } - } - #[doc = "Bits 15:0 of SHA-256 hash of boot key 2 (ECC)"] - #[inline(always)] - pub const fn bootkey2_0(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(640usize) as _) } - } - #[doc = "Bits 31:16 of SHA-256 hash of boot key 2 (ECC)"] - #[inline(always)] - pub const fn bootkey2_1(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(644usize) as _) } - } - #[doc = "Bits 47:32 of SHA-256 hash of boot key 2 (ECC)"] - #[inline(always)] - pub const fn bootkey2_2(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(648usize) as _) } - } - #[doc = "Bits 63:48 of SHA-256 hash of boot key 2 (ECC)"] - #[inline(always)] - pub const fn bootkey2_3(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(652usize) as _) } - } - #[doc = "Bits 79:64 of SHA-256 hash of boot key 2 (ECC)"] - #[inline(always)] - pub const fn bootkey2_4(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(656usize) as _) } - } - #[doc = "Bits 95:80 of SHA-256 hash of boot key 2 (ECC)"] - #[inline(always)] - pub const fn bootkey2_5(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(660usize) as _) } - } - #[doc = "Bits 111:96 of SHA-256 hash of boot key 2 (ECC)"] - #[inline(always)] - pub const fn bootkey2_6(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(664usize) as _) } - } - #[doc = "Bits 127:112 of SHA-256 hash of boot key 2 (ECC)"] - #[inline(always)] - pub const fn bootkey2_7(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(668usize) as _) } - } - #[doc = "Bits 143:128 of SHA-256 hash of boot key 2 (ECC)"] - #[inline(always)] - pub const fn bootkey2_8(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(672usize) as _) } - } - #[doc = "Bits 159:144 of SHA-256 hash of boot key 2 (ECC)"] - #[inline(always)] - pub const fn bootkey2_9(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(676usize) as _) } - } - #[doc = "Bits 175:160 of SHA-256 hash of boot key 2 (ECC)"] - #[inline(always)] - pub const fn bootkey2_10(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(680usize) as _) } - } - #[doc = "Bits 191:176 of SHA-256 hash of boot key 2 (ECC)"] - #[inline(always)] - pub const fn bootkey2_11(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(684usize) as _) } - } - #[doc = "Bits 207:192 of SHA-256 hash of boot key 2 (ECC)"] - #[inline(always)] - pub const fn bootkey2_12(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(688usize) as _) } - } - #[doc = "Bits 223:208 of SHA-256 hash of boot key 2 (ECC)"] - #[inline(always)] - pub const fn bootkey2_13(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(692usize) as _) } - } - #[doc = "Bits 239:224 of SHA-256 hash of boot key 2 (ECC)"] - #[inline(always)] - pub const fn bootkey2_14(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(696usize) as _) } - } - #[doc = "Bits 255:240 of SHA-256 hash of boot key 2 (ECC)"] - #[inline(always)] - pub const fn bootkey2_15(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(700usize) as _) } - } - #[doc = "Bits 15:0 of SHA-256 hash of boot key 3 (ECC)"] - #[inline(always)] - pub const fn bootkey3_0(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(704usize) as _) } - } - #[doc = "Bits 31:16 of SHA-256 hash of boot key 3 (ECC)"] - #[inline(always)] - pub const fn bootkey3_1(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(708usize) as _) } - } - #[doc = "Bits 47:32 of SHA-256 hash of boot key 3 (ECC)"] - #[inline(always)] - pub const fn bootkey3_2(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(712usize) as _) } - } - #[doc = "Bits 63:48 of SHA-256 hash of boot key 3 (ECC)"] - #[inline(always)] - pub const fn bootkey3_3(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(716usize) as _) } - } - #[doc = "Bits 79:64 of SHA-256 hash of boot key 3 (ECC)"] - #[inline(always)] - pub const fn bootkey3_4(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(720usize) as _) } - } - #[doc = "Bits 95:80 of SHA-256 hash of boot key 3 (ECC)"] - #[inline(always)] - pub const fn bootkey3_5(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(724usize) as _) } - } - #[doc = "Bits 111:96 of SHA-256 hash of boot key 3 (ECC)"] - #[inline(always)] - pub const fn bootkey3_6(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(728usize) as _) } - } - #[doc = "Bits 127:112 of SHA-256 hash of boot key 3 (ECC)"] - #[inline(always)] - pub const fn bootkey3_7(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(732usize) as _) } - } - #[doc = "Bits 143:128 of SHA-256 hash of boot key 3 (ECC)"] - #[inline(always)] - pub const fn bootkey3_8(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(736usize) as _) } - } - #[doc = "Bits 159:144 of SHA-256 hash of boot key 3 (ECC)"] - #[inline(always)] - pub const fn bootkey3_9(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(740usize) as _) } - } - #[doc = "Bits 175:160 of SHA-256 hash of boot key 3 (ECC)"] - #[inline(always)] - pub const fn bootkey3_10(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(744usize) as _) } + pub const fn otpboot_dst1(self) -> crate::common::Reg { + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x0184usize) as _) } } - #[doc = "Bits 191:176 of SHA-256 hash of boot key 3 (ECC)"] #[inline(always)] - pub const fn bootkey3_11(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(748usize) as _) } + pub const fn bootkey(self, n: usize) -> BootKey { + assert!(n < 4usize); + unsafe { BootKey::from_ptr(self.ptr.add(0x0200usize + n * 64usize) as _) } } - #[doc = "Bits 207:192 of SHA-256 hash of boot key 3 (ECC)"] #[inline(always)] - pub const fn bootkey3_12(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(752usize) as _) } + pub const fn key(self, n: usize) -> Key { + assert!(n < 6usize); + unsafe { Key::from_ptr(self.ptr.add(0x3d20usize + n * 32usize) as _) } } - #[doc = "Bits 223:208 of SHA-256 hash of boot key 3 (ECC)"] + #[doc = "Valid flag for key 1. Once the valid flag is set, the key can no longer be read or written, and becomes a valid fixed key for protecting OTP pages."] #[inline(always)] - pub const fn bootkey3_13(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(756usize) as _) } + pub const fn key_valid( + self, + n: usize, + ) -> crate::common::Reg { + assert!(n < 6usize); + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x3de4usize + n * 4usize) as _) } } - #[doc = "Bits 239:224 of SHA-256 hash of boot key 3 (ECC)"] #[inline(always)] - pub const fn bootkey3_14(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(760usize) as _) } + pub const fn page_lock(self, n: usize) -> PageLock { + assert!(n < 64usize); + unsafe { PageLock::from_ptr(self.ptr.add(0x3e00usize + n * 8usize) as _) } } - #[doc = "Bits 255:240 of SHA-256 hash of boot key 3 (ECC)"] +} +#[derive(Copy, Clone, Eq, PartialEq)] +pub struct PageLock { + ptr: *mut u8, +} +unsafe impl Send for PageLock {} +unsafe impl Sync for PageLock {} +impl PageLock { #[inline(always)] - pub const fn bootkey3_15(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(764usize) as _) } + pub const unsafe fn from_ptr(ptr: *mut ()) -> Self { + Self { ptr: ptr as _ } } - #[doc = "Bits 15:0 of OTP access key 1 (ECC)"] #[inline(always)] - pub const fn key1_0(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(15648usize) as _) } + pub const fn as_ptr(&self) -> *mut () { + self.ptr as _ } - #[doc = "Bits 31:16 of OTP access key 1 (ECC)"] + #[doc = "Lock configuration LSBs for page 62 (rows 0xf80 through 0xfbf). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions."] #[inline(always)] - pub const fn key1_1(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(15652usize) as _) } - } - #[doc = "Bits 47:32 of OTP access key 1 (ECC)"] - #[inline(always)] - pub const fn key1_2(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(15656usize) as _) } - } - #[doc = "Bits 63:48 of OTP access key 1 (ECC)"] - #[inline(always)] - pub const fn key1_3(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(15660usize) as _) } - } - #[doc = "Bits 79:64 of OTP access key 1 (ECC)"] - #[inline(always)] - pub const fn key1_4(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(15664usize) as _) } - } - #[doc = "Bits 95:80 of OTP access key 1 (ECC)"] - #[inline(always)] - pub const fn key1_5(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(15668usize) as _) } - } - #[doc = "Bits 111:96 of OTP access key 1 (ECC)"] - #[inline(always)] - pub const fn key1_6(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(15672usize) as _) } - } - #[doc = "Bits 127:112 of OTP access key 1 (ECC)"] - #[inline(always)] - pub const fn key1_7(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(15676usize) as _) } - } - #[doc = "Bits 15:0 of OTP access key 2 (ECC)"] - #[inline(always)] - pub const fn key2_0(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(15680usize) as _) } - } - #[doc = "Bits 31:16 of OTP access key 2 (ECC)"] - #[inline(always)] - pub const fn key2_1(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(15684usize) as _) } - } - #[doc = "Bits 47:32 of OTP access key 2 (ECC)"] - #[inline(always)] - pub const fn key2_2(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(15688usize) as _) } - } - #[doc = "Bits 63:48 of OTP access key 2 (ECC)"] - #[inline(always)] - pub const fn key2_3(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(15692usize) as _) } - } - #[doc = "Bits 79:64 of OTP access key 2 (ECC)"] - #[inline(always)] - pub const fn key2_4(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(15696usize) as _) } - } - #[doc = "Bits 95:80 of OTP access key 2 (ECC)"] - #[inline(always)] - pub const fn key2_5(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(15700usize) as _) } - } - #[doc = "Bits 111:96 of OTP access key 2 (ECC)"] - #[inline(always)] - pub const fn key2_6(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(15704usize) as _) } - } - #[doc = "Bits 127:112 of OTP access key 2 (ECC)"] - #[inline(always)] - pub const fn key2_7(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(15708usize) as _) } - } - #[doc = "Bits 15:0 of OTP access key 3 (ECC)"] - #[inline(always)] - pub const fn key3_0(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(15712usize) as _) } - } - #[doc = "Bits 31:16 of OTP access key 3 (ECC)"] - #[inline(always)] - pub const fn key3_1(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(15716usize) as _) } - } - #[doc = "Bits 47:32 of OTP access key 3 (ECC)"] - #[inline(always)] - pub const fn key3_2(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(15720usize) as _) } - } - #[doc = "Bits 63:48 of OTP access key 3 (ECC)"] - #[inline(always)] - pub const fn key3_3(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(15724usize) as _) } - } - #[doc = "Bits 79:64 of OTP access key 3 (ECC)"] - #[inline(always)] - pub const fn key3_4(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(15728usize) as _) } - } - #[doc = "Bits 95:80 of OTP access key 3 (ECC)"] - #[inline(always)] - pub const fn key3_5(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(15732usize) as _) } - } - #[doc = "Bits 111:96 of OTP access key 3 (ECC)"] - #[inline(always)] - pub const fn key3_6(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(15736usize) as _) } - } - #[doc = "Bits 127:112 of OTP access key 3 (ECC)"] - #[inline(always)] - pub const fn key3_7(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(15740usize) as _) } - } - #[doc = "Bits 15:0 of OTP access key 4 (ECC)"] - #[inline(always)] - pub const fn key4_0(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(15744usize) as _) } - } - #[doc = "Bits 31:16 of OTP access key 4 (ECC)"] - #[inline(always)] - pub const fn key4_1(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(15748usize) as _) } - } - #[doc = "Bits 47:32 of OTP access key 4 (ECC)"] - #[inline(always)] - pub const fn key4_2(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(15752usize) as _) } - } - #[doc = "Bits 63:48 of OTP access key 4 (ECC)"] - #[inline(always)] - pub const fn key4_3(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(15756usize) as _) } - } - #[doc = "Bits 79:64 of OTP access key 4 (ECC)"] - #[inline(always)] - pub const fn key4_4(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(15760usize) as _) } - } - #[doc = "Bits 95:80 of OTP access key 4 (ECC)"] - #[inline(always)] - pub const fn key4_5(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(15764usize) as _) } - } - #[doc = "Bits 111:96 of OTP access key 4 (ECC)"] - #[inline(always)] - pub const fn key4_6(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(15768usize) as _) } - } - #[doc = "Bits 127:112 of OTP access key 4 (ECC)"] - #[inline(always)] - pub const fn key4_7(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(15772usize) as _) } - } - #[doc = "Bits 15:0 of OTP access key 5 (ECC)"] - #[inline(always)] - pub const fn key5_0(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(15776usize) as _) } - } - #[doc = "Bits 31:16 of OTP access key 5 (ECC)"] - #[inline(always)] - pub const fn key5_1(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(15780usize) as _) } - } - #[doc = "Bits 47:32 of OTP access key 5 (ECC)"] - #[inline(always)] - pub const fn key5_2(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(15784usize) as _) } - } - #[doc = "Bits 63:48 of OTP access key 5 (ECC)"] - #[inline(always)] - pub const fn key5_3(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(15788usize) as _) } - } - #[doc = "Bits 79:64 of OTP access key 5 (ECC)"] - #[inline(always)] - pub const fn key5_4(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(15792usize) as _) } - } - #[doc = "Bits 95:80 of OTP access key 5 (ECC)"] - #[inline(always)] - pub const fn key5_5(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(15796usize) as _) } - } - #[doc = "Bits 111:96 of OTP access key 5 (ECC)"] - #[inline(always)] - pub const fn key5_6(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(15800usize) as _) } - } - #[doc = "Bits 127:112 of OTP access key 5 (ECC)"] - #[inline(always)] - pub const fn key5_7(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(15804usize) as _) } - } - #[doc = "Bits 15:0 of OTP access key 6 (ECC)"] - #[inline(always)] - pub const fn key6_0(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(15808usize) as _) } - } - #[doc = "Bits 31:16 of OTP access key 6 (ECC)"] - #[inline(always)] - pub const fn key6_1(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(15812usize) as _) } - } - #[doc = "Bits 47:32 of OTP access key 6 (ECC)"] - #[inline(always)] - pub const fn key6_2(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(15816usize) as _) } - } - #[doc = "Bits 63:48 of OTP access key 6 (ECC)"] - #[inline(always)] - pub const fn key6_3(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(15820usize) as _) } - } - #[doc = "Bits 79:64 of OTP access key 6 (ECC)"] - #[inline(always)] - pub const fn key6_4(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(15824usize) as _) } - } - #[doc = "Bits 95:80 of OTP access key 6 (ECC)"] - #[inline(always)] - pub const fn key6_5(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(15828usize) as _) } - } - #[doc = "Bits 111:96 of OTP access key 6 (ECC)"] - #[inline(always)] - pub const fn key6_6(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(15832usize) as _) } - } - #[doc = "Bits 127:112 of OTP access key 6 (ECC)"] - #[inline(always)] - pub const fn key6_7(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(15836usize) as _) } - } - #[doc = "Valid flag for key 1. Once the valid flag is set, the key can no longer be read or written, and becomes a valid fixed key for protecting OTP pages."] - #[inline(always)] - pub const fn key1_valid(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(15844usize) as _) } - } - #[doc = "Valid flag for key 2. Once the valid flag is set, the key can no longer be read or written, and becomes a valid fixed key for protecting OTP pages."] - #[inline(always)] - pub const fn key2_valid(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(15848usize) as _) } - } - #[doc = "Valid flag for key 3. Once the valid flag is set, the key can no longer be read or written, and becomes a valid fixed key for protecting OTP pages."] - #[inline(always)] - pub const fn key3_valid(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(15852usize) as _) } - } - #[doc = "Valid flag for key 4. Once the valid flag is set, the key can no longer be read or written, and becomes a valid fixed key for protecting OTP pages."] - #[inline(always)] - pub const fn key4_valid(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(15856usize) as _) } - } - #[doc = "Valid flag for key 5. Once the valid flag is set, the key can no longer be read or written, and becomes a valid fixed key for protecting OTP pages."] - #[inline(always)] - pub const fn key5_valid(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(15860usize) as _) } - } - #[doc = "Valid flag for key 6. Once the valid flag is set, the key can no longer be read or written, and becomes a valid fixed key for protecting OTP pages."] - #[inline(always)] - pub const fn key6_valid(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(15864usize) as _) } - } - #[doc = "Lock configuration LSBs for page 0 (rows 0x0 through 0x3f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions."] - #[inline(always)] - pub const fn page0_lock0(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(15872usize) as _) } - } - #[doc = "Lock configuration MSBs for page 0 (rows 0x0 through 0x3f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions."] - #[inline(always)] - pub const fn page0_lock1(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(15876usize) as _) } - } - #[doc = "Lock configuration LSBs for page 1 (rows 0x40 through 0x7f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions."] - #[inline(always)] - pub const fn page1_lock0(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(15880usize) as _) } - } - #[doc = "Lock configuration MSBs for page 1 (rows 0x40 through 0x7f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions."] - #[inline(always)] - pub const fn page1_lock1(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(15884usize) as _) } - } - #[doc = "Lock configuration LSBs for page 2 (rows 0x80 through 0xbf). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions."] - #[inline(always)] - pub const fn page2_lock0(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(15888usize) as _) } - } - #[doc = "Lock configuration MSBs for page 2 (rows 0x80 through 0xbf). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions."] - #[inline(always)] - pub const fn page2_lock1(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(15892usize) as _) } - } - #[doc = "Lock configuration LSBs for page 3 (rows 0xc0 through 0xff). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions."] - #[inline(always)] - pub const fn page3_lock0(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(15896usize) as _) } - } - #[doc = "Lock configuration MSBs for page 3 (rows 0xc0 through 0xff). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions."] - #[inline(always)] - pub const fn page3_lock1(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(15900usize) as _) } - } - #[doc = "Lock configuration LSBs for page 4 (rows 0x100 through 0x13f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions."] - #[inline(always)] - pub const fn page4_lock0(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(15904usize) as _) } - } - #[doc = "Lock configuration MSBs for page 4 (rows 0x100 through 0x13f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions."] - #[inline(always)] - pub const fn page4_lock1(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(15908usize) as _) } - } - #[doc = "Lock configuration LSBs for page 5 (rows 0x140 through 0x17f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions."] - #[inline(always)] - pub const fn page5_lock0(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(15912usize) as _) } - } - #[doc = "Lock configuration MSBs for page 5 (rows 0x140 through 0x17f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions."] - #[inline(always)] - pub const fn page5_lock1(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(15916usize) as _) } - } - #[doc = "Lock configuration LSBs for page 6 (rows 0x180 through 0x1bf). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions."] - #[inline(always)] - pub const fn page6_lock0(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(15920usize) as _) } - } - #[doc = "Lock configuration MSBs for page 6 (rows 0x180 through 0x1bf). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions."] - #[inline(always)] - pub const fn page6_lock1(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(15924usize) as _) } - } - #[doc = "Lock configuration LSBs for page 7 (rows 0x1c0 through 0x1ff). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions."] - #[inline(always)] - pub const fn page7_lock0(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(15928usize) as _) } - } - #[doc = "Lock configuration MSBs for page 7 (rows 0x1c0 through 0x1ff). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions."] - #[inline(always)] - pub const fn page7_lock1(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(15932usize) as _) } - } - #[doc = "Lock configuration LSBs for page 8 (rows 0x200 through 0x23f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions."] - #[inline(always)] - pub const fn page8_lock0(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(15936usize) as _) } - } - #[doc = "Lock configuration MSBs for page 8 (rows 0x200 through 0x23f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions."] - #[inline(always)] - pub const fn page8_lock1(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(15940usize) as _) } - } - #[doc = "Lock configuration LSBs for page 9 (rows 0x240 through 0x27f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions."] - #[inline(always)] - pub const fn page9_lock0(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(15944usize) as _) } - } - #[doc = "Lock configuration MSBs for page 9 (rows 0x240 through 0x27f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions."] - #[inline(always)] - pub const fn page9_lock1(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(15948usize) as _) } - } - #[doc = "Lock configuration LSBs for page 10 (rows 0x280 through 0x2bf). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions."] - #[inline(always)] - pub const fn page10_lock0(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(15952usize) as _) } - } - #[doc = "Lock configuration MSBs for page 10 (rows 0x280 through 0x2bf). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions."] - #[inline(always)] - pub const fn page10_lock1(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(15956usize) as _) } - } - #[doc = "Lock configuration LSBs for page 11 (rows 0x2c0 through 0x2ff). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions."] - #[inline(always)] - pub const fn page11_lock0(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(15960usize) as _) } - } - #[doc = "Lock configuration MSBs for page 11 (rows 0x2c0 through 0x2ff). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions."] - #[inline(always)] - pub const fn page11_lock1(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(15964usize) as _) } - } - #[doc = "Lock configuration LSBs for page 12 (rows 0x300 through 0x33f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions."] - #[inline(always)] - pub const fn page12_lock0(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(15968usize) as _) } - } - #[doc = "Lock configuration MSBs for page 12 (rows 0x300 through 0x33f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions."] - #[inline(always)] - pub const fn page12_lock1(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(15972usize) as _) } - } - #[doc = "Lock configuration LSBs for page 13 (rows 0x340 through 0x37f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions."] - #[inline(always)] - pub const fn page13_lock0(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(15976usize) as _) } - } - #[doc = "Lock configuration MSBs for page 13 (rows 0x340 through 0x37f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions."] - #[inline(always)] - pub const fn page13_lock1(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(15980usize) as _) } - } - #[doc = "Lock configuration LSBs for page 14 (rows 0x380 through 0x3bf). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions."] - #[inline(always)] - pub const fn page14_lock0(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(15984usize) as _) } - } - #[doc = "Lock configuration MSBs for page 14 (rows 0x380 through 0x3bf). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions."] - #[inline(always)] - pub const fn page14_lock1(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(15988usize) as _) } - } - #[doc = "Lock configuration LSBs for page 15 (rows 0x3c0 through 0x3ff). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions."] - #[inline(always)] - pub const fn page15_lock0(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(15992usize) as _) } - } - #[doc = "Lock configuration MSBs for page 15 (rows 0x3c0 through 0x3ff). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions."] - #[inline(always)] - pub const fn page15_lock1(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(15996usize) as _) } - } - #[doc = "Lock configuration LSBs for page 16 (rows 0x400 through 0x43f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions."] - #[inline(always)] - pub const fn page16_lock0(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(16000usize) as _) } - } - #[doc = "Lock configuration MSBs for page 16 (rows 0x400 through 0x43f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions."] - #[inline(always)] - pub const fn page16_lock1(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(16004usize) as _) } - } - #[doc = "Lock configuration LSBs for page 17 (rows 0x440 through 0x47f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions."] - #[inline(always)] - pub const fn page17_lock0(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(16008usize) as _) } - } - #[doc = "Lock configuration MSBs for page 17 (rows 0x440 through 0x47f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions."] - #[inline(always)] - pub const fn page17_lock1(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(16012usize) as _) } - } - #[doc = "Lock configuration LSBs for page 18 (rows 0x480 through 0x4bf). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions."] - #[inline(always)] - pub const fn page18_lock0(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(16016usize) as _) } - } - #[doc = "Lock configuration MSBs for page 18 (rows 0x480 through 0x4bf). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions."] - #[inline(always)] - pub const fn page18_lock1(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(16020usize) as _) } - } - #[doc = "Lock configuration LSBs for page 19 (rows 0x4c0 through 0x4ff). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions."] - #[inline(always)] - pub const fn page19_lock0(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(16024usize) as _) } - } - #[doc = "Lock configuration MSBs for page 19 (rows 0x4c0 through 0x4ff). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions."] - #[inline(always)] - pub const fn page19_lock1(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(16028usize) as _) } - } - #[doc = "Lock configuration LSBs for page 20 (rows 0x500 through 0x53f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions."] - #[inline(always)] - pub const fn page20_lock0(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(16032usize) as _) } - } - #[doc = "Lock configuration MSBs for page 20 (rows 0x500 through 0x53f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions."] - #[inline(always)] - pub const fn page20_lock1(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(16036usize) as _) } - } - #[doc = "Lock configuration LSBs for page 21 (rows 0x540 through 0x57f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions."] - #[inline(always)] - pub const fn page21_lock0(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(16040usize) as _) } - } - #[doc = "Lock configuration MSBs for page 21 (rows 0x540 through 0x57f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions."] - #[inline(always)] - pub const fn page21_lock1(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(16044usize) as _) } - } - #[doc = "Lock configuration LSBs for page 22 (rows 0x580 through 0x5bf). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions."] - #[inline(always)] - pub const fn page22_lock0(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(16048usize) as _) } - } - #[doc = "Lock configuration MSBs for page 22 (rows 0x580 through 0x5bf). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions."] - #[inline(always)] - pub const fn page22_lock1(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(16052usize) as _) } - } - #[doc = "Lock configuration LSBs for page 23 (rows 0x5c0 through 0x5ff). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions."] - #[inline(always)] - pub const fn page23_lock0(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(16056usize) as _) } - } - #[doc = "Lock configuration MSBs for page 23 (rows 0x5c0 through 0x5ff). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions."] - #[inline(always)] - pub const fn page23_lock1(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(16060usize) as _) } - } - #[doc = "Lock configuration LSBs for page 24 (rows 0x600 through 0x63f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions."] - #[inline(always)] - pub const fn page24_lock0(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(16064usize) as _) } - } - #[doc = "Lock configuration MSBs for page 24 (rows 0x600 through 0x63f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions."] - #[inline(always)] - pub const fn page24_lock1(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(16068usize) as _) } - } - #[doc = "Lock configuration LSBs for page 25 (rows 0x640 through 0x67f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions."] - #[inline(always)] - pub const fn page25_lock0(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(16072usize) as _) } - } - #[doc = "Lock configuration MSBs for page 25 (rows 0x640 through 0x67f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions."] - #[inline(always)] - pub const fn page25_lock1(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(16076usize) as _) } - } - #[doc = "Lock configuration LSBs for page 26 (rows 0x680 through 0x6bf). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions."] - #[inline(always)] - pub const fn page26_lock0(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(16080usize) as _) } - } - #[doc = "Lock configuration MSBs for page 26 (rows 0x680 through 0x6bf). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions."] - #[inline(always)] - pub const fn page26_lock1(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(16084usize) as _) } - } - #[doc = "Lock configuration LSBs for page 27 (rows 0x6c0 through 0x6ff). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions."] - #[inline(always)] - pub const fn page27_lock0(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(16088usize) as _) } - } - #[doc = "Lock configuration MSBs for page 27 (rows 0x6c0 through 0x6ff). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions."] - #[inline(always)] - pub const fn page27_lock1(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(16092usize) as _) } - } - #[doc = "Lock configuration LSBs for page 28 (rows 0x700 through 0x73f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions."] - #[inline(always)] - pub const fn page28_lock0(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(16096usize) as _) } - } - #[doc = "Lock configuration MSBs for page 28 (rows 0x700 through 0x73f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions."] - #[inline(always)] - pub const fn page28_lock1(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(16100usize) as _) } - } - #[doc = "Lock configuration LSBs for page 29 (rows 0x740 through 0x77f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions."] - #[inline(always)] - pub const fn page29_lock0(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(16104usize) as _) } - } - #[doc = "Lock configuration MSBs for page 29 (rows 0x740 through 0x77f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions."] - #[inline(always)] - pub const fn page29_lock1(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(16108usize) as _) } - } - #[doc = "Lock configuration LSBs for page 30 (rows 0x780 through 0x7bf). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions."] - #[inline(always)] - pub const fn page30_lock0(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(16112usize) as _) } - } - #[doc = "Lock configuration MSBs for page 30 (rows 0x780 through 0x7bf). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions."] - #[inline(always)] - pub const fn page30_lock1(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(16116usize) as _) } - } - #[doc = "Lock configuration LSBs for page 31 (rows 0x7c0 through 0x7ff). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions."] - #[inline(always)] - pub const fn page31_lock0(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(16120usize) as _) } - } - #[doc = "Lock configuration MSBs for page 31 (rows 0x7c0 through 0x7ff). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions."] - #[inline(always)] - pub const fn page31_lock1(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(16124usize) as _) } - } - #[doc = "Lock configuration LSBs for page 32 (rows 0x800 through 0x83f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions."] - #[inline(always)] - pub const fn page32_lock0(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(16128usize) as _) } - } - #[doc = "Lock configuration MSBs for page 32 (rows 0x800 through 0x83f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions."] - #[inline(always)] - pub const fn page32_lock1(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(16132usize) as _) } - } - #[doc = "Lock configuration LSBs for page 33 (rows 0x840 through 0x87f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions."] - #[inline(always)] - pub const fn page33_lock0(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(16136usize) as _) } - } - #[doc = "Lock configuration MSBs for page 33 (rows 0x840 through 0x87f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions."] - #[inline(always)] - pub const fn page33_lock1(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(16140usize) as _) } - } - #[doc = "Lock configuration LSBs for page 34 (rows 0x880 through 0x8bf). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions."] - #[inline(always)] - pub const fn page34_lock0(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(16144usize) as _) } - } - #[doc = "Lock configuration MSBs for page 34 (rows 0x880 through 0x8bf). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions."] - #[inline(always)] - pub const fn page34_lock1(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(16148usize) as _) } - } - #[doc = "Lock configuration LSBs for page 35 (rows 0x8c0 through 0x8ff). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions."] - #[inline(always)] - pub const fn page35_lock0(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(16152usize) as _) } - } - #[doc = "Lock configuration MSBs for page 35 (rows 0x8c0 through 0x8ff). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions."] - #[inline(always)] - pub const fn page35_lock1(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(16156usize) as _) } - } - #[doc = "Lock configuration LSBs for page 36 (rows 0x900 through 0x93f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions."] - #[inline(always)] - pub const fn page36_lock0(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(16160usize) as _) } - } - #[doc = "Lock configuration MSBs for page 36 (rows 0x900 through 0x93f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions."] - #[inline(always)] - pub const fn page36_lock1(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(16164usize) as _) } - } - #[doc = "Lock configuration LSBs for page 37 (rows 0x940 through 0x97f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions."] - #[inline(always)] - pub const fn page37_lock0(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(16168usize) as _) } - } - #[doc = "Lock configuration MSBs for page 37 (rows 0x940 through 0x97f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions."] - #[inline(always)] - pub const fn page37_lock1(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(16172usize) as _) } - } - #[doc = "Lock configuration LSBs for page 38 (rows 0x980 through 0x9bf). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions."] - #[inline(always)] - pub const fn page38_lock0(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(16176usize) as _) } - } - #[doc = "Lock configuration MSBs for page 38 (rows 0x980 through 0x9bf). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions."] - #[inline(always)] - pub const fn page38_lock1(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(16180usize) as _) } - } - #[doc = "Lock configuration LSBs for page 39 (rows 0x9c0 through 0x9ff). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions."] - #[inline(always)] - pub const fn page39_lock0(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(16184usize) as _) } - } - #[doc = "Lock configuration MSBs for page 39 (rows 0x9c0 through 0x9ff). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions."] - #[inline(always)] - pub const fn page39_lock1(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(16188usize) as _) } - } - #[doc = "Lock configuration LSBs for page 40 (rows 0xa00 through 0xa3f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions."] - #[inline(always)] - pub const fn page40_lock0(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(16192usize) as _) } - } - #[doc = "Lock configuration MSBs for page 40 (rows 0xa00 through 0xa3f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions."] - #[inline(always)] - pub const fn page40_lock1(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(16196usize) as _) } - } - #[doc = "Lock configuration LSBs for page 41 (rows 0xa40 through 0xa7f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions."] - #[inline(always)] - pub const fn page41_lock0(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(16200usize) as _) } - } - #[doc = "Lock configuration MSBs for page 41 (rows 0xa40 through 0xa7f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions."] - #[inline(always)] - pub const fn page41_lock1(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(16204usize) as _) } - } - #[doc = "Lock configuration LSBs for page 42 (rows 0xa80 through 0xabf). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions."] - #[inline(always)] - pub const fn page42_lock0(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(16208usize) as _) } - } - #[doc = "Lock configuration MSBs for page 42 (rows 0xa80 through 0xabf). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions."] - #[inline(always)] - pub const fn page42_lock1(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(16212usize) as _) } - } - #[doc = "Lock configuration LSBs for page 43 (rows 0xac0 through 0xaff). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions."] - #[inline(always)] - pub const fn page43_lock0(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(16216usize) as _) } - } - #[doc = "Lock configuration MSBs for page 43 (rows 0xac0 through 0xaff). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions."] - #[inline(always)] - pub const fn page43_lock1(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(16220usize) as _) } - } - #[doc = "Lock configuration LSBs for page 44 (rows 0xb00 through 0xb3f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions."] - #[inline(always)] - pub const fn page44_lock0(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(16224usize) as _) } - } - #[doc = "Lock configuration MSBs for page 44 (rows 0xb00 through 0xb3f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions."] - #[inline(always)] - pub const fn page44_lock1(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(16228usize) as _) } - } - #[doc = "Lock configuration LSBs for page 45 (rows 0xb40 through 0xb7f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions."] - #[inline(always)] - pub const fn page45_lock0(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(16232usize) as _) } - } - #[doc = "Lock configuration MSBs for page 45 (rows 0xb40 through 0xb7f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions."] - #[inline(always)] - pub const fn page45_lock1(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(16236usize) as _) } - } - #[doc = "Lock configuration LSBs for page 46 (rows 0xb80 through 0xbbf). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions."] - #[inline(always)] - pub const fn page46_lock0(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(16240usize) as _) } - } - #[doc = "Lock configuration MSBs for page 46 (rows 0xb80 through 0xbbf). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions."] - #[inline(always)] - pub const fn page46_lock1(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(16244usize) as _) } - } - #[doc = "Lock configuration LSBs for page 47 (rows 0xbc0 through 0xbff). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions."] - #[inline(always)] - pub const fn page47_lock0(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(16248usize) as _) } - } - #[doc = "Lock configuration MSBs for page 47 (rows 0xbc0 through 0xbff). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions."] - #[inline(always)] - pub const fn page47_lock1(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(16252usize) as _) } - } - #[doc = "Lock configuration LSBs for page 48 (rows 0xc00 through 0xc3f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions."] - #[inline(always)] - pub const fn page48_lock0(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(16256usize) as _) } - } - #[doc = "Lock configuration MSBs for page 48 (rows 0xc00 through 0xc3f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions."] - #[inline(always)] - pub const fn page48_lock1(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(16260usize) as _) } - } - #[doc = "Lock configuration LSBs for page 49 (rows 0xc40 through 0xc7f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions."] - #[inline(always)] - pub const fn page49_lock0(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(16264usize) as _) } - } - #[doc = "Lock configuration MSBs for page 49 (rows 0xc40 through 0xc7f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions."] - #[inline(always)] - pub const fn page49_lock1(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(16268usize) as _) } - } - #[doc = "Lock configuration LSBs for page 50 (rows 0xc80 through 0xcbf). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions."] - #[inline(always)] - pub const fn page50_lock0(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(16272usize) as _) } - } - #[doc = "Lock configuration MSBs for page 50 (rows 0xc80 through 0xcbf). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions."] - #[inline(always)] - pub const fn page50_lock1(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(16276usize) as _) } - } - #[doc = "Lock configuration LSBs for page 51 (rows 0xcc0 through 0xcff). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions."] - #[inline(always)] - pub const fn page51_lock0(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(16280usize) as _) } - } - #[doc = "Lock configuration MSBs for page 51 (rows 0xcc0 through 0xcff). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions."] - #[inline(always)] - pub const fn page51_lock1(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(16284usize) as _) } - } - #[doc = "Lock configuration LSBs for page 52 (rows 0xd00 through 0xd3f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions."] - #[inline(always)] - pub const fn page52_lock0(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(16288usize) as _) } - } - #[doc = "Lock configuration MSBs for page 52 (rows 0xd00 through 0xd3f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions."] - #[inline(always)] - pub const fn page52_lock1(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(16292usize) as _) } - } - #[doc = "Lock configuration LSBs for page 53 (rows 0xd40 through 0xd7f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions."] - #[inline(always)] - pub const fn page53_lock0(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(16296usize) as _) } - } - #[doc = "Lock configuration MSBs for page 53 (rows 0xd40 through 0xd7f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions."] - #[inline(always)] - pub const fn page53_lock1(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(16300usize) as _) } - } - #[doc = "Lock configuration LSBs for page 54 (rows 0xd80 through 0xdbf). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions."] - #[inline(always)] - pub const fn page54_lock0(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(16304usize) as _) } - } - #[doc = "Lock configuration MSBs for page 54 (rows 0xd80 through 0xdbf). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions."] - #[inline(always)] - pub const fn page54_lock1(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(16308usize) as _) } - } - #[doc = "Lock configuration LSBs for page 55 (rows 0xdc0 through 0xdff). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions."] - #[inline(always)] - pub const fn page55_lock0(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(16312usize) as _) } - } - #[doc = "Lock configuration MSBs for page 55 (rows 0xdc0 through 0xdff). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions."] - #[inline(always)] - pub const fn page55_lock1(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(16316usize) as _) } - } - #[doc = "Lock configuration LSBs for page 56 (rows 0xe00 through 0xe3f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions."] - #[inline(always)] - pub const fn page56_lock0(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(16320usize) as _) } - } - #[doc = "Lock configuration MSBs for page 56 (rows 0xe00 through 0xe3f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions."] - #[inline(always)] - pub const fn page56_lock1(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(16324usize) as _) } - } - #[doc = "Lock configuration LSBs for page 57 (rows 0xe40 through 0xe7f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions."] - #[inline(always)] - pub const fn page57_lock0(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(16328usize) as _) } - } - #[doc = "Lock configuration MSBs for page 57 (rows 0xe40 through 0xe7f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions."] - #[inline(always)] - pub const fn page57_lock1(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(16332usize) as _) } - } - #[doc = "Lock configuration LSBs for page 58 (rows 0xe80 through 0xebf). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions."] - #[inline(always)] - pub const fn page58_lock0(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(16336usize) as _) } - } - #[doc = "Lock configuration MSBs for page 58 (rows 0xe80 through 0xebf). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions."] - #[inline(always)] - pub const fn page58_lock1(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(16340usize) as _) } - } - #[doc = "Lock configuration LSBs for page 59 (rows 0xec0 through 0xeff). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions."] - #[inline(always)] - pub const fn page59_lock0(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(16344usize) as _) } - } - #[doc = "Lock configuration MSBs for page 59 (rows 0xec0 through 0xeff). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions."] - #[inline(always)] - pub const fn page59_lock1(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(16348usize) as _) } - } - #[doc = "Lock configuration LSBs for page 60 (rows 0xf00 through 0xf3f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions."] - #[inline(always)] - pub const fn page60_lock0(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(16352usize) as _) } - } - #[doc = "Lock configuration MSBs for page 60 (rows 0xf00 through 0xf3f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions."] - #[inline(always)] - pub const fn page60_lock1(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(16356usize) as _) } - } - #[doc = "Lock configuration LSBs for page 61 (rows 0xf40 through 0xf7f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions."] - #[inline(always)] - pub const fn page61_lock0(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(16360usize) as _) } - } - #[doc = "Lock configuration MSBs for page 61 (rows 0xf40 through 0xf7f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions."] - #[inline(always)] - pub const fn page61_lock1(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(16364usize) as _) } - } - #[doc = "Lock configuration LSBs for page 62 (rows 0xf80 through 0xfbf). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions."] - #[inline(always)] - pub const fn page62_lock0(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(16368usize) as _) } + pub const fn lock0(self) -> crate::common::Reg { + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x0usize) as _) } } #[doc = "Lock configuration MSBs for page 62 (rows 0xf80 through 0xfbf). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions."] #[inline(always)] - pub const fn page62_lock1(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(16372usize) as _) } - } - #[doc = "Lock configuration LSBs for page 63 (rows 0xfc0 through 0xfff). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions."] - #[inline(always)] - pub const fn page63_lock0(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(16376usize) as _) } - } - #[doc = "Lock configuration MSBs for page 63 (rows 0xfc0 through 0xfff). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions."] - #[inline(always)] - pub const fn page63_lock1(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(16380usize) as _) } + pub const fn lock1(self) -> crate::common::Reg { + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x04usize) as _) } } } pub mod regs; diff --git a/src/rp235x/otp_data_raw/regs.rs b/src/rp235x/otp_data_raw/regs.rs index 3f489d3e..4d2bdc8c 100644 --- a/src/rp235x/otp_data_raw/regs.rs +++ b/src/rp235x/otp_data_raw/regs.rs @@ -584,226 +584,11 @@ impl Default for FlashDevinfo { FlashDevinfo(0) } } -#[doc = "Valid flag for key 1. Once the valid flag is set, the key can no longer be read or written, and becomes a valid fixed key for protecting OTP pages."] -#[repr(transparent)] -#[derive(Copy, Clone, Eq, PartialEq)] -pub struct Key1valid(pub u32); -impl Key1valid { - #[inline(always)] - pub const fn valid(&self) -> bool { - let val = (self.0 >> 0usize) & 0x01; - val != 0 - } - #[inline(always)] - pub fn set_valid(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize); - } - #[doc = "Redundant copy of VALID, with 3-way majority vote"] - #[inline(always)] - pub const fn valid_r1(&self) -> bool { - let val = (self.0 >> 8usize) & 0x01; - val != 0 - } - #[doc = "Redundant copy of VALID, with 3-way majority vote"] - #[inline(always)] - pub fn set_valid_r1(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 8usize)) | (((val as u32) & 0x01) << 8usize); - } - #[doc = "Redundant copy of VALID, with 3-way majority vote"] - #[inline(always)] - pub const fn valid_r2(&self) -> bool { - let val = (self.0 >> 16usize) & 0x01; - val != 0 - } - #[doc = "Redundant copy of VALID, with 3-way majority vote"] - #[inline(always)] - pub fn set_valid_r2(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 16usize)) | (((val as u32) & 0x01) << 16usize); - } -} -impl Default for Key1valid { - #[inline(always)] - fn default() -> Key1valid { - Key1valid(0) - } -} -#[doc = "Valid flag for key 2. Once the valid flag is set, the key can no longer be read or written, and becomes a valid fixed key for protecting OTP pages."] -#[repr(transparent)] -#[derive(Copy, Clone, Eq, PartialEq)] -pub struct Key2valid(pub u32); -impl Key2valid { - #[inline(always)] - pub const fn valid(&self) -> bool { - let val = (self.0 >> 0usize) & 0x01; - val != 0 - } - #[inline(always)] - pub fn set_valid(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize); - } - #[doc = "Redundant copy of VALID, with 3-way majority vote"] - #[inline(always)] - pub const fn valid_r1(&self) -> bool { - let val = (self.0 >> 8usize) & 0x01; - val != 0 - } - #[doc = "Redundant copy of VALID, with 3-way majority vote"] - #[inline(always)] - pub fn set_valid_r1(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 8usize)) | (((val as u32) & 0x01) << 8usize); - } - #[doc = "Redundant copy of VALID, with 3-way majority vote"] - #[inline(always)] - pub const fn valid_r2(&self) -> bool { - let val = (self.0 >> 16usize) & 0x01; - val != 0 - } - #[doc = "Redundant copy of VALID, with 3-way majority vote"] - #[inline(always)] - pub fn set_valid_r2(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 16usize)) | (((val as u32) & 0x01) << 16usize); - } -} -impl Default for Key2valid { - #[inline(always)] - fn default() -> Key2valid { - Key2valid(0) - } -} -#[doc = "Valid flag for key 3. Once the valid flag is set, the key can no longer be read or written, and becomes a valid fixed key for protecting OTP pages."] -#[repr(transparent)] -#[derive(Copy, Clone, Eq, PartialEq)] -pub struct Key3valid(pub u32); -impl Key3valid { - #[inline(always)] - pub const fn valid(&self) -> bool { - let val = (self.0 >> 0usize) & 0x01; - val != 0 - } - #[inline(always)] - pub fn set_valid(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize); - } - #[doc = "Redundant copy of VALID, with 3-way majority vote"] - #[inline(always)] - pub const fn valid_r1(&self) -> bool { - let val = (self.0 >> 8usize) & 0x01; - val != 0 - } - #[doc = "Redundant copy of VALID, with 3-way majority vote"] - #[inline(always)] - pub fn set_valid_r1(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 8usize)) | (((val as u32) & 0x01) << 8usize); - } - #[doc = "Redundant copy of VALID, with 3-way majority vote"] - #[inline(always)] - pub const fn valid_r2(&self) -> bool { - let val = (self.0 >> 16usize) & 0x01; - val != 0 - } - #[doc = "Redundant copy of VALID, with 3-way majority vote"] - #[inline(always)] - pub fn set_valid_r2(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 16usize)) | (((val as u32) & 0x01) << 16usize); - } -} -impl Default for Key3valid { - #[inline(always)] - fn default() -> Key3valid { - Key3valid(0) - } -} -#[doc = "Valid flag for key 4. Once the valid flag is set, the key can no longer be read or written, and becomes a valid fixed key for protecting OTP pages."] -#[repr(transparent)] -#[derive(Copy, Clone, Eq, PartialEq)] -pub struct Key4valid(pub u32); -impl Key4valid { - #[inline(always)] - pub const fn valid(&self) -> bool { - let val = (self.0 >> 0usize) & 0x01; - val != 0 - } - #[inline(always)] - pub fn set_valid(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize); - } - #[doc = "Redundant copy of VALID, with 3-way majority vote"] - #[inline(always)] - pub const fn valid_r1(&self) -> bool { - let val = (self.0 >> 8usize) & 0x01; - val != 0 - } - #[doc = "Redundant copy of VALID, with 3-way majority vote"] - #[inline(always)] - pub fn set_valid_r1(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 8usize)) | (((val as u32) & 0x01) << 8usize); - } - #[doc = "Redundant copy of VALID, with 3-way majority vote"] - #[inline(always)] - pub const fn valid_r2(&self) -> bool { - let val = (self.0 >> 16usize) & 0x01; - val != 0 - } - #[doc = "Redundant copy of VALID, with 3-way majority vote"] - #[inline(always)] - pub fn set_valid_r2(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 16usize)) | (((val as u32) & 0x01) << 16usize); - } -} -impl Default for Key4valid { - #[inline(always)] - fn default() -> Key4valid { - Key4valid(0) - } -} -#[doc = "Valid flag for key 5. Once the valid flag is set, the key can no longer be read or written, and becomes a valid fixed key for protecting OTP pages."] -#[repr(transparent)] -#[derive(Copy, Clone, Eq, PartialEq)] -pub struct Key5valid(pub u32); -impl Key5valid { - #[inline(always)] - pub const fn valid(&self) -> bool { - let val = (self.0 >> 0usize) & 0x01; - val != 0 - } - #[inline(always)] - pub fn set_valid(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize); - } - #[doc = "Redundant copy of VALID, with 3-way majority vote"] - #[inline(always)] - pub const fn valid_r1(&self) -> bool { - let val = (self.0 >> 8usize) & 0x01; - val != 0 - } - #[doc = "Redundant copy of VALID, with 3-way majority vote"] - #[inline(always)] - pub fn set_valid_r1(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 8usize)) | (((val as u32) & 0x01) << 8usize); - } - #[doc = "Redundant copy of VALID, with 3-way majority vote"] - #[inline(always)] - pub const fn valid_r2(&self) -> bool { - let val = (self.0 >> 16usize) & 0x01; - val != 0 - } - #[doc = "Redundant copy of VALID, with 3-way majority vote"] - #[inline(always)] - pub fn set_valid_r2(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 16usize)) | (((val as u32) & 0x01) << 16usize); - } -} -impl Default for Key5valid { - #[inline(always)] - fn default() -> Key5valid { - Key5valid(0) - } -} #[doc = "Valid flag for key 6. Once the valid flag is set, the key can no longer be read or written, and becomes a valid fixed key for protecting OTP pages."] #[repr(transparent)] #[derive(Copy, Clone, Eq, PartialEq)] -pub struct Key6valid(pub u32); -impl Key6valid { +pub struct KeyValid(pub u32); +impl KeyValid { #[inline(always)] pub const fn valid(&self) -> bool { let val = (self.0 >> 0usize) & 0x01; @@ -836,17 +621,17 @@ impl Key6valid { self.0 = (self.0 & !(0x01 << 16usize)) | (((val as u32) & 0x01) << 16usize); } } -impl Default for Key6valid { +impl Default for KeyValid { #[inline(always)] - fn default() -> Key6valid { - Key6valid(0) + fn default() -> KeyValid { + KeyValid(0) } } -#[doc = "Lock configuration LSBs for page 0 (rows 0x0 through 0x3f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions."] +#[doc = "Lock configuration LSBs for page 63 (rows 0xfc0 through 0xfff). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions."] #[repr(transparent)] #[derive(Copy, Clone, Eq, PartialEq)] -pub struct Page0lock0(pub u32); -impl Page0lock0 { +pub struct PageLock0(pub u32); +impl PageLock0 { #[doc = "Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required."] #[inline(always)] pub const fn key_w(&self) -> u8 { @@ -871,81 +656,25 @@ impl Page0lock0 { } #[doc = "State when at least one key is registered for this page and no matching key has been entered."] #[inline(always)] - pub const fn no_key_state(&self) -> super::vals::Page0lock0noKeyState { + pub const fn no_key_state(&self) -> super::vals::PageLockNoKeyState { let val = (self.0 >> 6usize) & 0x01; - super::vals::Page0lock0noKeyState::from_bits(val as u8) + super::vals::PageLockNoKeyState::from_bits(val as u8) } #[doc = "State when at least one key is registered for this page and no matching key has been entered."] #[inline(always)] - pub fn set_no_key_state(&mut self, val: super::vals::Page0lock0noKeyState) { + pub fn set_no_key_state(&mut self, val: super::vals::PageLockNoKeyState) { self.0 = (self.0 & !(0x01 << 6usize)) | (((val.to_bits() as u32) & 0x01) << 6usize); } - #[doc = "Redundant copy of bits 7:0"] - #[inline(always)] - pub const fn r1(&self) -> u8 { - let val = (self.0 >> 8usize) & 0xff; - val as u8 - } - #[doc = "Redundant copy of bits 7:0"] - #[inline(always)] - pub fn set_r1(&mut self, val: u8) { - self.0 = (self.0 & !(0xff << 8usize)) | (((val as u32) & 0xff) << 8usize); - } - #[doc = "Redundant copy of bits 7:0"] - #[inline(always)] - pub const fn r2(&self) -> u8 { - let val = (self.0 >> 16usize) & 0xff; - val as u8 - } - #[doc = "Redundant copy of bits 7:0"] - #[inline(always)] - pub fn set_r2(&mut self, val: u8) { - self.0 = (self.0 & !(0xff << 16usize)) | (((val as u32) & 0xff) << 16usize); - } -} -impl Default for Page0lock0 { - #[inline(always)] - fn default() -> Page0lock0 { - Page0lock0(0) - } -} -#[doc = "Lock configuration MSBs for page 0 (rows 0x0 through 0x3f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions."] -#[repr(transparent)] -#[derive(Copy, Clone, Eq, PartialEq)] -pub struct Page0lock1(pub u32); -impl Page0lock1 { - #[doc = "Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers."] - #[inline(always)] - pub const fn lock_s(&self) -> super::vals::Page0lock1lockS { - let val = (self.0 >> 0usize) & 0x03; - super::vals::Page0lock1lockS::from_bits(val as u8) - } - #[doc = "Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers."] - #[inline(always)] - pub fn set_lock_s(&mut self, val: super::vals::Page0lock1lockS) { - self.0 = (self.0 & !(0x03 << 0usize)) | (((val.to_bits() as u32) & 0x03) << 0usize); - } - #[doc = "Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API."] - #[inline(always)] - pub const fn lock_ns(&self) -> super::vals::Page0lock1lockNs { - let val = (self.0 >> 2usize) & 0x03; - super::vals::Page0lock1lockNs::from_bits(val as u8) - } - #[doc = "Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API."] - #[inline(always)] - pub fn set_lock_ns(&mut self, val: super::vals::Page0lock1lockNs) { - self.0 = (self.0 & !(0x03 << 2usize)) | (((val.to_bits() as u32) & 0x03) << 2usize); - } - #[doc = "Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers."] + #[doc = "Decommission for RMA of a suspected faulty device. This re-enables the factory test JTAG interface, and makes pages 3 through 61 of the OTP permanently inaccessible."] #[inline(always)] - pub const fn lock_bl(&self) -> super::vals::Page0lock1lockBl { - let val = (self.0 >> 4usize) & 0x03; - super::vals::Page0lock1lockBl::from_bits(val as u8) + pub const fn rma(&self) -> bool { + let val = (self.0 >> 7usize) & 0x01; + val != 0 } - #[doc = "Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers."] + #[doc = "Decommission for RMA of a suspected faulty device. This re-enables the factory test JTAG interface, and makes pages 3 through 61 of the OTP permanently inaccessible."] #[inline(always)] - pub fn set_lock_bl(&mut self, val: super::vals::Page0lock1lockBl) { - self.0 = (self.0 & !(0x03 << 4usize)) | (((val.to_bits() as u32) & 0x03) << 4usize); + pub fn set_rma(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 7usize)) | (((val as u32) & 0x01) << 7usize); } #[doc = "Redundant copy of bits 7:0"] #[inline(always)] @@ -970,8434 +699,48 @@ impl Page0lock1 { self.0 = (self.0 & !(0xff << 16usize)) | (((val as u32) & 0xff) << 16usize); } } -impl Default for Page0lock1 { +impl Default for PageLock0 { #[inline(always)] - fn default() -> Page0lock1 { - Page0lock1(0) + fn default() -> PageLock0 { + PageLock0(0) } } -#[doc = "Lock configuration LSBs for page 10 (rows 0x280 through 0x2bf). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions."] -#[repr(transparent)] -#[derive(Copy, Clone, Eq, PartialEq)] -pub struct Page10lock0(pub u32); -impl Page10lock0 { - #[doc = "Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required."] - #[inline(always)] - pub const fn key_w(&self) -> u8 { - let val = (self.0 >> 0usize) & 0x07; - val as u8 - } - #[doc = "Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required."] - #[inline(always)] - pub fn set_key_w(&mut self, val: u8) { - self.0 = (self.0 & !(0x07 << 0usize)) | (((val as u32) & 0x07) << 0usize); - } - #[doc = "Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required."] - #[inline(always)] - pub const fn key_r(&self) -> u8 { - let val = (self.0 >> 3usize) & 0x07; - val as u8 - } - #[doc = "Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required."] - #[inline(always)] - pub fn set_key_r(&mut self, val: u8) { - self.0 = (self.0 & !(0x07 << 3usize)) | (((val as u32) & 0x07) << 3usize); - } - #[doc = "State when at least one key is registered for this page and no matching key has been entered."] - #[inline(always)] - pub const fn no_key_state(&self) -> super::vals::Page10lock0noKeyState { - let val = (self.0 >> 6usize) & 0x01; - super::vals::Page10lock0noKeyState::from_bits(val as u8) - } - #[doc = "State when at least one key is registered for this page and no matching key has been entered."] - #[inline(always)] - pub fn set_no_key_state(&mut self, val: super::vals::Page10lock0noKeyState) { - self.0 = (self.0 & !(0x01 << 6usize)) | (((val.to_bits() as u32) & 0x01) << 6usize); - } - #[doc = "Redundant copy of bits 7:0"] - #[inline(always)] - pub const fn r1(&self) -> u8 { - let val = (self.0 >> 8usize) & 0xff; - val as u8 - } - #[doc = "Redundant copy of bits 7:0"] - #[inline(always)] - pub fn set_r1(&mut self, val: u8) { - self.0 = (self.0 & !(0xff << 8usize)) | (((val as u32) & 0xff) << 8usize); - } - #[doc = "Redundant copy of bits 7:0"] - #[inline(always)] - pub const fn r2(&self) -> u8 { - let val = (self.0 >> 16usize) & 0xff; - val as u8 - } - #[doc = "Redundant copy of bits 7:0"] - #[inline(always)] - pub fn set_r2(&mut self, val: u8) { - self.0 = (self.0 & !(0xff << 16usize)) | (((val as u32) & 0xff) << 16usize); - } -} -impl Default for Page10lock0 { - #[inline(always)] - fn default() -> Page10lock0 { - Page10lock0(0) - } -} -#[doc = "Lock configuration MSBs for page 10 (rows 0x280 through 0x2bf). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions."] -#[repr(transparent)] -#[derive(Copy, Clone, Eq, PartialEq)] -pub struct Page10lock1(pub u32); -impl Page10lock1 { - #[doc = "Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers."] - #[inline(always)] - pub const fn lock_s(&self) -> super::vals::Page10lock1lockS { - let val = (self.0 >> 0usize) & 0x03; - super::vals::Page10lock1lockS::from_bits(val as u8) - } - #[doc = "Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers."] - #[inline(always)] - pub fn set_lock_s(&mut self, val: super::vals::Page10lock1lockS) { - self.0 = (self.0 & !(0x03 << 0usize)) | (((val.to_bits() as u32) & 0x03) << 0usize); - } - #[doc = "Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API."] - #[inline(always)] - pub const fn lock_ns(&self) -> super::vals::Page10lock1lockNs { - let val = (self.0 >> 2usize) & 0x03; - super::vals::Page10lock1lockNs::from_bits(val as u8) - } - #[doc = "Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API."] - #[inline(always)] - pub fn set_lock_ns(&mut self, val: super::vals::Page10lock1lockNs) { - self.0 = (self.0 & !(0x03 << 2usize)) | (((val.to_bits() as u32) & 0x03) << 2usize); - } - #[doc = "Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers."] - #[inline(always)] - pub const fn lock_bl(&self) -> super::vals::Page10lock1lockBl { - let val = (self.0 >> 4usize) & 0x03; - super::vals::Page10lock1lockBl::from_bits(val as u8) - } - #[doc = "Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers."] - #[inline(always)] - pub fn set_lock_bl(&mut self, val: super::vals::Page10lock1lockBl) { - self.0 = (self.0 & !(0x03 << 4usize)) | (((val.to_bits() as u32) & 0x03) << 4usize); - } - #[doc = "Redundant copy of bits 7:0"] - #[inline(always)] - pub const fn r1(&self) -> u8 { - let val = (self.0 >> 8usize) & 0xff; - val as u8 - } - #[doc = "Redundant copy of bits 7:0"] - #[inline(always)] - pub fn set_r1(&mut self, val: u8) { - self.0 = (self.0 & !(0xff << 8usize)) | (((val as u32) & 0xff) << 8usize); - } - #[doc = "Redundant copy of bits 7:0"] - #[inline(always)] - pub const fn r2(&self) -> u8 { - let val = (self.0 >> 16usize) & 0xff; - val as u8 - } - #[doc = "Redundant copy of bits 7:0"] - #[inline(always)] - pub fn set_r2(&mut self, val: u8) { - self.0 = (self.0 & !(0xff << 16usize)) | (((val as u32) & 0xff) << 16usize); - } -} -impl Default for Page10lock1 { - #[inline(always)] - fn default() -> Page10lock1 { - Page10lock1(0) - } -} -#[doc = "Lock configuration LSBs for page 11 (rows 0x2c0 through 0x2ff). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions."] -#[repr(transparent)] -#[derive(Copy, Clone, Eq, PartialEq)] -pub struct Page11lock0(pub u32); -impl Page11lock0 { - #[doc = "Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required."] - #[inline(always)] - pub const fn key_w(&self) -> u8 { - let val = (self.0 >> 0usize) & 0x07; - val as u8 - } - #[doc = "Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required."] - #[inline(always)] - pub fn set_key_w(&mut self, val: u8) { - self.0 = (self.0 & !(0x07 << 0usize)) | (((val as u32) & 0x07) << 0usize); - } - #[doc = "Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required."] - #[inline(always)] - pub const fn key_r(&self) -> u8 { - let val = (self.0 >> 3usize) & 0x07; - val as u8 - } - #[doc = "Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required."] - #[inline(always)] - pub fn set_key_r(&mut self, val: u8) { - self.0 = (self.0 & !(0x07 << 3usize)) | (((val as u32) & 0x07) << 3usize); - } - #[doc = "State when at least one key is registered for this page and no matching key has been entered."] - #[inline(always)] - pub const fn no_key_state(&self) -> super::vals::Page11lock0noKeyState { - let val = (self.0 >> 6usize) & 0x01; - super::vals::Page11lock0noKeyState::from_bits(val as u8) - } - #[doc = "State when at least one key is registered for this page and no matching key has been entered."] - #[inline(always)] - pub fn set_no_key_state(&mut self, val: super::vals::Page11lock0noKeyState) { - self.0 = (self.0 & !(0x01 << 6usize)) | (((val.to_bits() as u32) & 0x01) << 6usize); - } - #[doc = "Redundant copy of bits 7:0"] - #[inline(always)] - pub const fn r1(&self) -> u8 { - let val = (self.0 >> 8usize) & 0xff; - val as u8 - } - #[doc = "Redundant copy of bits 7:0"] - #[inline(always)] - pub fn set_r1(&mut self, val: u8) { - self.0 = (self.0 & !(0xff << 8usize)) | (((val as u32) & 0xff) << 8usize); - } - #[doc = "Redundant copy of bits 7:0"] - #[inline(always)] - pub const fn r2(&self) -> u8 { - let val = (self.0 >> 16usize) & 0xff; - val as u8 - } - #[doc = "Redundant copy of bits 7:0"] - #[inline(always)] - pub fn set_r2(&mut self, val: u8) { - self.0 = (self.0 & !(0xff << 16usize)) | (((val as u32) & 0xff) << 16usize); - } -} -impl Default for Page11lock0 { - #[inline(always)] - fn default() -> Page11lock0 { - Page11lock0(0) - } -} -#[doc = "Lock configuration MSBs for page 11 (rows 0x2c0 through 0x2ff). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions."] -#[repr(transparent)] -#[derive(Copy, Clone, Eq, PartialEq)] -pub struct Page11lock1(pub u32); -impl Page11lock1 { - #[doc = "Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers."] - #[inline(always)] - pub const fn lock_s(&self) -> super::vals::Page11lock1lockS { - let val = (self.0 >> 0usize) & 0x03; - super::vals::Page11lock1lockS::from_bits(val as u8) - } - #[doc = "Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers."] - #[inline(always)] - pub fn set_lock_s(&mut self, val: super::vals::Page11lock1lockS) { - self.0 = (self.0 & !(0x03 << 0usize)) | (((val.to_bits() as u32) & 0x03) << 0usize); - } - #[doc = "Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API."] - #[inline(always)] - pub const fn lock_ns(&self) -> super::vals::Page11lock1lockNs { - let val = (self.0 >> 2usize) & 0x03; - super::vals::Page11lock1lockNs::from_bits(val as u8) - } - #[doc = "Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API."] - #[inline(always)] - pub fn set_lock_ns(&mut self, val: super::vals::Page11lock1lockNs) { - self.0 = (self.0 & !(0x03 << 2usize)) | (((val.to_bits() as u32) & 0x03) << 2usize); - } - #[doc = "Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers."] - #[inline(always)] - pub const fn lock_bl(&self) -> super::vals::Page11lock1lockBl { - let val = (self.0 >> 4usize) & 0x03; - super::vals::Page11lock1lockBl::from_bits(val as u8) - } - #[doc = "Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers."] - #[inline(always)] - pub fn set_lock_bl(&mut self, val: super::vals::Page11lock1lockBl) { - self.0 = (self.0 & !(0x03 << 4usize)) | (((val.to_bits() as u32) & 0x03) << 4usize); - } - #[doc = "Redundant copy of bits 7:0"] - #[inline(always)] - pub const fn r1(&self) -> u8 { - let val = (self.0 >> 8usize) & 0xff; - val as u8 - } - #[doc = "Redundant copy of bits 7:0"] - #[inline(always)] - pub fn set_r1(&mut self, val: u8) { - self.0 = (self.0 & !(0xff << 8usize)) | (((val as u32) & 0xff) << 8usize); - } - #[doc = "Redundant copy of bits 7:0"] - #[inline(always)] - pub const fn r2(&self) -> u8 { - let val = (self.0 >> 16usize) & 0xff; - val as u8 - } - #[doc = "Redundant copy of bits 7:0"] - #[inline(always)] - pub fn set_r2(&mut self, val: u8) { - self.0 = (self.0 & !(0xff << 16usize)) | (((val as u32) & 0xff) << 16usize); - } -} -impl Default for Page11lock1 { - #[inline(always)] - fn default() -> Page11lock1 { - Page11lock1(0) - } -} -#[doc = "Lock configuration LSBs for page 12 (rows 0x300 through 0x33f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions."] -#[repr(transparent)] -#[derive(Copy, Clone, Eq, PartialEq)] -pub struct Page12lock0(pub u32); -impl Page12lock0 { - #[doc = "Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required."] - #[inline(always)] - pub const fn key_w(&self) -> u8 { - let val = (self.0 >> 0usize) & 0x07; - val as u8 - } - #[doc = "Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required."] - #[inline(always)] - pub fn set_key_w(&mut self, val: u8) { - self.0 = (self.0 & !(0x07 << 0usize)) | (((val as u32) & 0x07) << 0usize); - } - #[doc = "Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required."] - #[inline(always)] - pub const fn key_r(&self) -> u8 { - let val = (self.0 >> 3usize) & 0x07; - val as u8 - } - #[doc = "Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required."] - #[inline(always)] - pub fn set_key_r(&mut self, val: u8) { - self.0 = (self.0 & !(0x07 << 3usize)) | (((val as u32) & 0x07) << 3usize); - } - #[doc = "State when at least one key is registered for this page and no matching key has been entered."] - #[inline(always)] - pub const fn no_key_state(&self) -> super::vals::Page12lock0noKeyState { - let val = (self.0 >> 6usize) & 0x01; - super::vals::Page12lock0noKeyState::from_bits(val as u8) - } - #[doc = "State when at least one key is registered for this page and no matching key has been entered."] - #[inline(always)] - pub fn set_no_key_state(&mut self, val: super::vals::Page12lock0noKeyState) { - self.0 = (self.0 & !(0x01 << 6usize)) | (((val.to_bits() as u32) & 0x01) << 6usize); - } - #[doc = "Redundant copy of bits 7:0"] - #[inline(always)] - pub const fn r1(&self) -> u8 { - let val = (self.0 >> 8usize) & 0xff; - val as u8 - } - #[doc = "Redundant copy of bits 7:0"] - #[inline(always)] - pub fn set_r1(&mut self, val: u8) { - self.0 = (self.0 & !(0xff << 8usize)) | (((val as u32) & 0xff) << 8usize); - } - #[doc = "Redundant copy of bits 7:0"] - #[inline(always)] - pub const fn r2(&self) -> u8 { - let val = (self.0 >> 16usize) & 0xff; - val as u8 - } - #[doc = "Redundant copy of bits 7:0"] - #[inline(always)] - pub fn set_r2(&mut self, val: u8) { - self.0 = (self.0 & !(0xff << 16usize)) | (((val as u32) & 0xff) << 16usize); - } -} -impl Default for Page12lock0 { - #[inline(always)] - fn default() -> Page12lock0 { - Page12lock0(0) - } -} -#[doc = "Lock configuration MSBs for page 12 (rows 0x300 through 0x33f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions."] -#[repr(transparent)] -#[derive(Copy, Clone, Eq, PartialEq)] -pub struct Page12lock1(pub u32); -impl Page12lock1 { - #[doc = "Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers."] - #[inline(always)] - pub const fn lock_s(&self) -> super::vals::Page12lock1lockS { - let val = (self.0 >> 0usize) & 0x03; - super::vals::Page12lock1lockS::from_bits(val as u8) - } - #[doc = "Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers."] - #[inline(always)] - pub fn set_lock_s(&mut self, val: super::vals::Page12lock1lockS) { - self.0 = (self.0 & !(0x03 << 0usize)) | (((val.to_bits() as u32) & 0x03) << 0usize); - } - #[doc = "Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API."] - #[inline(always)] - pub const fn lock_ns(&self) -> super::vals::Page12lock1lockNs { - let val = (self.0 >> 2usize) & 0x03; - super::vals::Page12lock1lockNs::from_bits(val as u8) - } - #[doc = "Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API."] - #[inline(always)] - pub fn set_lock_ns(&mut self, val: super::vals::Page12lock1lockNs) { - self.0 = (self.0 & !(0x03 << 2usize)) | (((val.to_bits() as u32) & 0x03) << 2usize); - } - #[doc = "Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers."] - #[inline(always)] - pub const fn lock_bl(&self) -> super::vals::Page12lock1lockBl { - let val = (self.0 >> 4usize) & 0x03; - super::vals::Page12lock1lockBl::from_bits(val as u8) - } - #[doc = "Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers."] - #[inline(always)] - pub fn set_lock_bl(&mut self, val: super::vals::Page12lock1lockBl) { - self.0 = (self.0 & !(0x03 << 4usize)) | (((val.to_bits() as u32) & 0x03) << 4usize); - } - #[doc = "Redundant copy of bits 7:0"] - #[inline(always)] - pub const fn r1(&self) -> u8 { - let val = (self.0 >> 8usize) & 0xff; - val as u8 - } - #[doc = "Redundant copy of bits 7:0"] - #[inline(always)] - pub fn set_r1(&mut self, val: u8) { - self.0 = (self.0 & !(0xff << 8usize)) | (((val as u32) & 0xff) << 8usize); - } - #[doc = "Redundant copy of bits 7:0"] - #[inline(always)] - pub const fn r2(&self) -> u8 { - let val = (self.0 >> 16usize) & 0xff; - val as u8 - } - #[doc = "Redundant copy of bits 7:0"] - #[inline(always)] - pub fn set_r2(&mut self, val: u8) { - self.0 = (self.0 & !(0xff << 16usize)) | (((val as u32) & 0xff) << 16usize); - } -} -impl Default for Page12lock1 { - #[inline(always)] - fn default() -> Page12lock1 { - Page12lock1(0) - } -} -#[doc = "Lock configuration LSBs for page 13 (rows 0x340 through 0x37f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions."] -#[repr(transparent)] -#[derive(Copy, Clone, Eq, PartialEq)] -pub struct Page13lock0(pub u32); -impl Page13lock0 { - #[doc = "Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required."] - #[inline(always)] - pub const fn key_w(&self) -> u8 { - let val = (self.0 >> 0usize) & 0x07; - val as u8 - } - #[doc = "Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required."] - #[inline(always)] - pub fn set_key_w(&mut self, val: u8) { - self.0 = (self.0 & !(0x07 << 0usize)) | (((val as u32) & 0x07) << 0usize); - } - #[doc = "Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required."] - #[inline(always)] - pub const fn key_r(&self) -> u8 { - let val = (self.0 >> 3usize) & 0x07; - val as u8 - } - #[doc = "Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required."] - #[inline(always)] - pub fn set_key_r(&mut self, val: u8) { - self.0 = (self.0 & !(0x07 << 3usize)) | (((val as u32) & 0x07) << 3usize); - } - #[doc = "State when at least one key is registered for this page and no matching key has been entered."] - #[inline(always)] - pub const fn no_key_state(&self) -> super::vals::Page13lock0noKeyState { - let val = (self.0 >> 6usize) & 0x01; - super::vals::Page13lock0noKeyState::from_bits(val as u8) - } - #[doc = "State when at least one key is registered for this page and no matching key has been entered."] - #[inline(always)] - pub fn set_no_key_state(&mut self, val: super::vals::Page13lock0noKeyState) { - self.0 = (self.0 & !(0x01 << 6usize)) | (((val.to_bits() as u32) & 0x01) << 6usize); - } - #[doc = "Redundant copy of bits 7:0"] - #[inline(always)] - pub const fn r1(&self) -> u8 { - let val = (self.0 >> 8usize) & 0xff; - val as u8 - } - #[doc = "Redundant copy of bits 7:0"] - #[inline(always)] - pub fn set_r1(&mut self, val: u8) { - self.0 = (self.0 & !(0xff << 8usize)) | (((val as u32) & 0xff) << 8usize); - } - #[doc = "Redundant copy of bits 7:0"] - #[inline(always)] - pub const fn r2(&self) -> u8 { - let val = (self.0 >> 16usize) & 0xff; - val as u8 - } - #[doc = "Redundant copy of bits 7:0"] - #[inline(always)] - pub fn set_r2(&mut self, val: u8) { - self.0 = (self.0 & !(0xff << 16usize)) | (((val as u32) & 0xff) << 16usize); - } -} -impl Default for Page13lock0 { - #[inline(always)] - fn default() -> Page13lock0 { - Page13lock0(0) - } -} -#[doc = "Lock configuration MSBs for page 13 (rows 0x340 through 0x37f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions."] -#[repr(transparent)] -#[derive(Copy, Clone, Eq, PartialEq)] -pub struct Page13lock1(pub u32); -impl Page13lock1 { - #[doc = "Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers."] - #[inline(always)] - pub const fn lock_s(&self) -> super::vals::Page13lock1lockS { - let val = (self.0 >> 0usize) & 0x03; - super::vals::Page13lock1lockS::from_bits(val as u8) - } - #[doc = "Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers."] - #[inline(always)] - pub fn set_lock_s(&mut self, val: super::vals::Page13lock1lockS) { - self.0 = (self.0 & !(0x03 << 0usize)) | (((val.to_bits() as u32) & 0x03) << 0usize); - } - #[doc = "Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API."] - #[inline(always)] - pub const fn lock_ns(&self) -> super::vals::Page13lock1lockNs { - let val = (self.0 >> 2usize) & 0x03; - super::vals::Page13lock1lockNs::from_bits(val as u8) - } - #[doc = "Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API."] - #[inline(always)] - pub fn set_lock_ns(&mut self, val: super::vals::Page13lock1lockNs) { - self.0 = (self.0 & !(0x03 << 2usize)) | (((val.to_bits() as u32) & 0x03) << 2usize); - } - #[doc = "Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers."] - #[inline(always)] - pub const fn lock_bl(&self) -> super::vals::Page13lock1lockBl { - let val = (self.0 >> 4usize) & 0x03; - super::vals::Page13lock1lockBl::from_bits(val as u8) - } - #[doc = "Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers."] - #[inline(always)] - pub fn set_lock_bl(&mut self, val: super::vals::Page13lock1lockBl) { - self.0 = (self.0 & !(0x03 << 4usize)) | (((val.to_bits() as u32) & 0x03) << 4usize); - } - #[doc = "Redundant copy of bits 7:0"] - #[inline(always)] - pub const fn r1(&self) -> u8 { - let val = (self.0 >> 8usize) & 0xff; - val as u8 - } - #[doc = "Redundant copy of bits 7:0"] - #[inline(always)] - pub fn set_r1(&mut self, val: u8) { - self.0 = (self.0 & !(0xff << 8usize)) | (((val as u32) & 0xff) << 8usize); - } - #[doc = "Redundant copy of bits 7:0"] - #[inline(always)] - pub const fn r2(&self) -> u8 { - let val = (self.0 >> 16usize) & 0xff; - val as u8 - } - #[doc = "Redundant copy of bits 7:0"] - #[inline(always)] - pub fn set_r2(&mut self, val: u8) { - self.0 = (self.0 & !(0xff << 16usize)) | (((val as u32) & 0xff) << 16usize); - } -} -impl Default for Page13lock1 { - #[inline(always)] - fn default() -> Page13lock1 { - Page13lock1(0) - } -} -#[doc = "Lock configuration LSBs for page 14 (rows 0x380 through 0x3bf). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions."] -#[repr(transparent)] -#[derive(Copy, Clone, Eq, PartialEq)] -pub struct Page14lock0(pub u32); -impl Page14lock0 { - #[doc = "Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required."] - #[inline(always)] - pub const fn key_w(&self) -> u8 { - let val = (self.0 >> 0usize) & 0x07; - val as u8 - } - #[doc = "Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required."] - #[inline(always)] - pub fn set_key_w(&mut self, val: u8) { - self.0 = (self.0 & !(0x07 << 0usize)) | (((val as u32) & 0x07) << 0usize); - } - #[doc = "Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required."] - #[inline(always)] - pub const fn key_r(&self) -> u8 { - let val = (self.0 >> 3usize) & 0x07; - val as u8 - } - #[doc = "Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required."] - #[inline(always)] - pub fn set_key_r(&mut self, val: u8) { - self.0 = (self.0 & !(0x07 << 3usize)) | (((val as u32) & 0x07) << 3usize); - } - #[doc = "State when at least one key is registered for this page and no matching key has been entered."] - #[inline(always)] - pub const fn no_key_state(&self) -> super::vals::Page14lock0noKeyState { - let val = (self.0 >> 6usize) & 0x01; - super::vals::Page14lock0noKeyState::from_bits(val as u8) - } - #[doc = "State when at least one key is registered for this page and no matching key has been entered."] - #[inline(always)] - pub fn set_no_key_state(&mut self, val: super::vals::Page14lock0noKeyState) { - self.0 = (self.0 & !(0x01 << 6usize)) | (((val.to_bits() as u32) & 0x01) << 6usize); - } - #[doc = "Redundant copy of bits 7:0"] - #[inline(always)] - pub const fn r1(&self) -> u8 { - let val = (self.0 >> 8usize) & 0xff; - val as u8 - } - #[doc = "Redundant copy of bits 7:0"] - #[inline(always)] - pub fn set_r1(&mut self, val: u8) { - self.0 = (self.0 & !(0xff << 8usize)) | (((val as u32) & 0xff) << 8usize); - } - #[doc = "Redundant copy of bits 7:0"] - #[inline(always)] - pub const fn r2(&self) -> u8 { - let val = (self.0 >> 16usize) & 0xff; - val as u8 - } - #[doc = "Redundant copy of bits 7:0"] - #[inline(always)] - pub fn set_r2(&mut self, val: u8) { - self.0 = (self.0 & !(0xff << 16usize)) | (((val as u32) & 0xff) << 16usize); - } -} -impl Default for Page14lock0 { - #[inline(always)] - fn default() -> Page14lock0 { - Page14lock0(0) - } -} -#[doc = "Lock configuration MSBs for page 14 (rows 0x380 through 0x3bf). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions."] -#[repr(transparent)] -#[derive(Copy, Clone, Eq, PartialEq)] -pub struct Page14lock1(pub u32); -impl Page14lock1 { - #[doc = "Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers."] - #[inline(always)] - pub const fn lock_s(&self) -> super::vals::Page14lock1lockS { - let val = (self.0 >> 0usize) & 0x03; - super::vals::Page14lock1lockS::from_bits(val as u8) - } - #[doc = "Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers."] - #[inline(always)] - pub fn set_lock_s(&mut self, val: super::vals::Page14lock1lockS) { - self.0 = (self.0 & !(0x03 << 0usize)) | (((val.to_bits() as u32) & 0x03) << 0usize); - } - #[doc = "Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API."] - #[inline(always)] - pub const fn lock_ns(&self) -> super::vals::Page14lock1lockNs { - let val = (self.0 >> 2usize) & 0x03; - super::vals::Page14lock1lockNs::from_bits(val as u8) - } - #[doc = "Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API."] - #[inline(always)] - pub fn set_lock_ns(&mut self, val: super::vals::Page14lock1lockNs) { - self.0 = (self.0 & !(0x03 << 2usize)) | (((val.to_bits() as u32) & 0x03) << 2usize); - } - #[doc = "Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers."] - #[inline(always)] - pub const fn lock_bl(&self) -> super::vals::Page14lock1lockBl { - let val = (self.0 >> 4usize) & 0x03; - super::vals::Page14lock1lockBl::from_bits(val as u8) - } - #[doc = "Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers."] - #[inline(always)] - pub fn set_lock_bl(&mut self, val: super::vals::Page14lock1lockBl) { - self.0 = (self.0 & !(0x03 << 4usize)) | (((val.to_bits() as u32) & 0x03) << 4usize); - } - #[doc = "Redundant copy of bits 7:0"] - #[inline(always)] - pub const fn r1(&self) -> u8 { - let val = (self.0 >> 8usize) & 0xff; - val as u8 - } - #[doc = "Redundant copy of bits 7:0"] - #[inline(always)] - pub fn set_r1(&mut self, val: u8) { - self.0 = (self.0 & !(0xff << 8usize)) | (((val as u32) & 0xff) << 8usize); - } - #[doc = "Redundant copy of bits 7:0"] - #[inline(always)] - pub const fn r2(&self) -> u8 { - let val = (self.0 >> 16usize) & 0xff; - val as u8 - } - #[doc = "Redundant copy of bits 7:0"] - #[inline(always)] - pub fn set_r2(&mut self, val: u8) { - self.0 = (self.0 & !(0xff << 16usize)) | (((val as u32) & 0xff) << 16usize); - } -} -impl Default for Page14lock1 { - #[inline(always)] - fn default() -> Page14lock1 { - Page14lock1(0) - } -} -#[doc = "Lock configuration LSBs for page 15 (rows 0x3c0 through 0x3ff). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions."] -#[repr(transparent)] -#[derive(Copy, Clone, Eq, PartialEq)] -pub struct Page15lock0(pub u32); -impl Page15lock0 { - #[doc = "Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required."] - #[inline(always)] - pub const fn key_w(&self) -> u8 { - let val = (self.0 >> 0usize) & 0x07; - val as u8 - } - #[doc = "Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required."] - #[inline(always)] - pub fn set_key_w(&mut self, val: u8) { - self.0 = (self.0 & !(0x07 << 0usize)) | (((val as u32) & 0x07) << 0usize); - } - #[doc = "Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required."] - #[inline(always)] - pub const fn key_r(&self) -> u8 { - let val = (self.0 >> 3usize) & 0x07; - val as u8 - } - #[doc = "Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required."] - #[inline(always)] - pub fn set_key_r(&mut self, val: u8) { - self.0 = (self.0 & !(0x07 << 3usize)) | (((val as u32) & 0x07) << 3usize); - } - #[doc = "State when at least one key is registered for this page and no matching key has been entered."] - #[inline(always)] - pub const fn no_key_state(&self) -> super::vals::Page15lock0noKeyState { - let val = (self.0 >> 6usize) & 0x01; - super::vals::Page15lock0noKeyState::from_bits(val as u8) - } - #[doc = "State when at least one key is registered for this page and no matching key has been entered."] - #[inline(always)] - pub fn set_no_key_state(&mut self, val: super::vals::Page15lock0noKeyState) { - self.0 = (self.0 & !(0x01 << 6usize)) | (((val.to_bits() as u32) & 0x01) << 6usize); - } - #[doc = "Redundant copy of bits 7:0"] - #[inline(always)] - pub const fn r1(&self) -> u8 { - let val = (self.0 >> 8usize) & 0xff; - val as u8 - } - #[doc = "Redundant copy of bits 7:0"] - #[inline(always)] - pub fn set_r1(&mut self, val: u8) { - self.0 = (self.0 & !(0xff << 8usize)) | (((val as u32) & 0xff) << 8usize); - } - #[doc = "Redundant copy of bits 7:0"] - #[inline(always)] - pub const fn r2(&self) -> u8 { - let val = (self.0 >> 16usize) & 0xff; - val as u8 - } - #[doc = "Redundant copy of bits 7:0"] - #[inline(always)] - pub fn set_r2(&mut self, val: u8) { - self.0 = (self.0 & !(0xff << 16usize)) | (((val as u32) & 0xff) << 16usize); - } -} -impl Default for Page15lock0 { - #[inline(always)] - fn default() -> Page15lock0 { - Page15lock0(0) - } -} -#[doc = "Lock configuration MSBs for page 15 (rows 0x3c0 through 0x3ff). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions."] -#[repr(transparent)] -#[derive(Copy, Clone, Eq, PartialEq)] -pub struct Page15lock1(pub u32); -impl Page15lock1 { - #[doc = "Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers."] - #[inline(always)] - pub const fn lock_s(&self) -> super::vals::Page15lock1lockS { - let val = (self.0 >> 0usize) & 0x03; - super::vals::Page15lock1lockS::from_bits(val as u8) - } - #[doc = "Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers."] - #[inline(always)] - pub fn set_lock_s(&mut self, val: super::vals::Page15lock1lockS) { - self.0 = (self.0 & !(0x03 << 0usize)) | (((val.to_bits() as u32) & 0x03) << 0usize); - } - #[doc = "Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API."] - #[inline(always)] - pub const fn lock_ns(&self) -> super::vals::Page15lock1lockNs { - let val = (self.0 >> 2usize) & 0x03; - super::vals::Page15lock1lockNs::from_bits(val as u8) - } - #[doc = "Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API."] - #[inline(always)] - pub fn set_lock_ns(&mut self, val: super::vals::Page15lock1lockNs) { - self.0 = (self.0 & !(0x03 << 2usize)) | (((val.to_bits() as u32) & 0x03) << 2usize); - } - #[doc = "Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers."] - #[inline(always)] - pub const fn lock_bl(&self) -> super::vals::Page15lock1lockBl { - let val = (self.0 >> 4usize) & 0x03; - super::vals::Page15lock1lockBl::from_bits(val as u8) - } - #[doc = "Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers."] - #[inline(always)] - pub fn set_lock_bl(&mut self, val: super::vals::Page15lock1lockBl) { - self.0 = (self.0 & !(0x03 << 4usize)) | (((val.to_bits() as u32) & 0x03) << 4usize); - } - #[doc = "Redundant copy of bits 7:0"] - #[inline(always)] - pub const fn r1(&self) -> u8 { - let val = (self.0 >> 8usize) & 0xff; - val as u8 - } - #[doc = "Redundant copy of bits 7:0"] - #[inline(always)] - pub fn set_r1(&mut self, val: u8) { - self.0 = (self.0 & !(0xff << 8usize)) | (((val as u32) & 0xff) << 8usize); - } - #[doc = "Redundant copy of bits 7:0"] - #[inline(always)] - pub const fn r2(&self) -> u8 { - let val = (self.0 >> 16usize) & 0xff; - val as u8 - } - #[doc = "Redundant copy of bits 7:0"] - #[inline(always)] - pub fn set_r2(&mut self, val: u8) { - self.0 = (self.0 & !(0xff << 16usize)) | (((val as u32) & 0xff) << 16usize); - } -} -impl Default for Page15lock1 { - #[inline(always)] - fn default() -> Page15lock1 { - Page15lock1(0) - } -} -#[doc = "Lock configuration LSBs for page 16 (rows 0x400 through 0x43f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions."] -#[repr(transparent)] -#[derive(Copy, Clone, Eq, PartialEq)] -pub struct Page16lock0(pub u32); -impl Page16lock0 { - #[doc = "Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required."] - #[inline(always)] - pub const fn key_w(&self) -> u8 { - let val = (self.0 >> 0usize) & 0x07; - val as u8 - } - #[doc = "Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required."] - #[inline(always)] - pub fn set_key_w(&mut self, val: u8) { - self.0 = (self.0 & !(0x07 << 0usize)) | (((val as u32) & 0x07) << 0usize); - } - #[doc = "Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required."] - #[inline(always)] - pub const fn key_r(&self) -> u8 { - let val = (self.0 >> 3usize) & 0x07; - val as u8 - } - #[doc = "Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required."] - #[inline(always)] - pub fn set_key_r(&mut self, val: u8) { - self.0 = (self.0 & !(0x07 << 3usize)) | (((val as u32) & 0x07) << 3usize); - } - #[doc = "State when at least one key is registered for this page and no matching key has been entered."] - #[inline(always)] - pub const fn no_key_state(&self) -> super::vals::Page16lock0noKeyState { - let val = (self.0 >> 6usize) & 0x01; - super::vals::Page16lock0noKeyState::from_bits(val as u8) - } - #[doc = "State when at least one key is registered for this page and no matching key has been entered."] - #[inline(always)] - pub fn set_no_key_state(&mut self, val: super::vals::Page16lock0noKeyState) { - self.0 = (self.0 & !(0x01 << 6usize)) | (((val.to_bits() as u32) & 0x01) << 6usize); - } - #[doc = "Redundant copy of bits 7:0"] - #[inline(always)] - pub const fn r1(&self) -> u8 { - let val = (self.0 >> 8usize) & 0xff; - val as u8 - } - #[doc = "Redundant copy of bits 7:0"] - #[inline(always)] - pub fn set_r1(&mut self, val: u8) { - self.0 = (self.0 & !(0xff << 8usize)) | (((val as u32) & 0xff) << 8usize); - } - #[doc = "Redundant copy of bits 7:0"] - #[inline(always)] - pub const fn r2(&self) -> u8 { - let val = (self.0 >> 16usize) & 0xff; - val as u8 - } - #[doc = "Redundant copy of bits 7:0"] - #[inline(always)] - pub fn set_r2(&mut self, val: u8) { - self.0 = (self.0 & !(0xff << 16usize)) | (((val as u32) & 0xff) << 16usize); - } -} -impl Default for Page16lock0 { - #[inline(always)] - fn default() -> Page16lock0 { - Page16lock0(0) - } -} -#[doc = "Lock configuration MSBs for page 16 (rows 0x400 through 0x43f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions."] -#[repr(transparent)] -#[derive(Copy, Clone, Eq, PartialEq)] -pub struct Page16lock1(pub u32); -impl Page16lock1 { - #[doc = "Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers."] - #[inline(always)] - pub const fn lock_s(&self) -> super::vals::Page16lock1lockS { - let val = (self.0 >> 0usize) & 0x03; - super::vals::Page16lock1lockS::from_bits(val as u8) - } - #[doc = "Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers."] - #[inline(always)] - pub fn set_lock_s(&mut self, val: super::vals::Page16lock1lockS) { - self.0 = (self.0 & !(0x03 << 0usize)) | (((val.to_bits() as u32) & 0x03) << 0usize); - } - #[doc = "Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API."] - #[inline(always)] - pub const fn lock_ns(&self) -> super::vals::Page16lock1lockNs { - let val = (self.0 >> 2usize) & 0x03; - super::vals::Page16lock1lockNs::from_bits(val as u8) - } - #[doc = "Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API."] - #[inline(always)] - pub fn set_lock_ns(&mut self, val: super::vals::Page16lock1lockNs) { - self.0 = (self.0 & !(0x03 << 2usize)) | (((val.to_bits() as u32) & 0x03) << 2usize); - } - #[doc = "Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers."] - #[inline(always)] - pub const fn lock_bl(&self) -> super::vals::Page16lock1lockBl { - let val = (self.0 >> 4usize) & 0x03; - super::vals::Page16lock1lockBl::from_bits(val as u8) - } - #[doc = "Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers."] - #[inline(always)] - pub fn set_lock_bl(&mut self, val: super::vals::Page16lock1lockBl) { - self.0 = (self.0 & !(0x03 << 4usize)) | (((val.to_bits() as u32) & 0x03) << 4usize); - } - #[doc = "Redundant copy of bits 7:0"] - #[inline(always)] - pub const fn r1(&self) -> u8 { - let val = (self.0 >> 8usize) & 0xff; - val as u8 - } - #[doc = "Redundant copy of bits 7:0"] - #[inline(always)] - pub fn set_r1(&mut self, val: u8) { - self.0 = (self.0 & !(0xff << 8usize)) | (((val as u32) & 0xff) << 8usize); - } - #[doc = "Redundant copy of bits 7:0"] - #[inline(always)] - pub const fn r2(&self) -> u8 { - let val = (self.0 >> 16usize) & 0xff; - val as u8 - } - #[doc = "Redundant copy of bits 7:0"] - #[inline(always)] - pub fn set_r2(&mut self, val: u8) { - self.0 = (self.0 & !(0xff << 16usize)) | (((val as u32) & 0xff) << 16usize); - } -} -impl Default for Page16lock1 { - #[inline(always)] - fn default() -> Page16lock1 { - Page16lock1(0) - } -} -#[doc = "Lock configuration LSBs for page 17 (rows 0x440 through 0x47f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions."] -#[repr(transparent)] -#[derive(Copy, Clone, Eq, PartialEq)] -pub struct Page17lock0(pub u32); -impl Page17lock0 { - #[doc = "Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required."] - #[inline(always)] - pub const fn key_w(&self) -> u8 { - let val = (self.0 >> 0usize) & 0x07; - val as u8 - } - #[doc = "Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required."] - #[inline(always)] - pub fn set_key_w(&mut self, val: u8) { - self.0 = (self.0 & !(0x07 << 0usize)) | (((val as u32) & 0x07) << 0usize); - } - #[doc = "Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required."] - #[inline(always)] - pub const fn key_r(&self) -> u8 { - let val = (self.0 >> 3usize) & 0x07; - val as u8 - } - #[doc = "Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required."] - #[inline(always)] - pub fn set_key_r(&mut self, val: u8) { - self.0 = (self.0 & !(0x07 << 3usize)) | (((val as u32) & 0x07) << 3usize); - } - #[doc = "State when at least one key is registered for this page and no matching key has been entered."] - #[inline(always)] - pub const fn no_key_state(&self) -> super::vals::Page17lock0noKeyState { - let val = (self.0 >> 6usize) & 0x01; - super::vals::Page17lock0noKeyState::from_bits(val as u8) - } - #[doc = "State when at least one key is registered for this page and no matching key has been entered."] - #[inline(always)] - pub fn set_no_key_state(&mut self, val: super::vals::Page17lock0noKeyState) { - self.0 = (self.0 & !(0x01 << 6usize)) | (((val.to_bits() as u32) & 0x01) << 6usize); - } - #[doc = "Redundant copy of bits 7:0"] - #[inline(always)] - pub const fn r1(&self) -> u8 { - let val = (self.0 >> 8usize) & 0xff; - val as u8 - } - #[doc = "Redundant copy of bits 7:0"] - #[inline(always)] - pub fn set_r1(&mut self, val: u8) { - self.0 = (self.0 & !(0xff << 8usize)) | (((val as u32) & 0xff) << 8usize); - } - #[doc = "Redundant copy of bits 7:0"] - #[inline(always)] - pub const fn r2(&self) -> u8 { - let val = (self.0 >> 16usize) & 0xff; - val as u8 - } - #[doc = "Redundant copy of bits 7:0"] - #[inline(always)] - pub fn set_r2(&mut self, val: u8) { - self.0 = (self.0 & !(0xff << 16usize)) | (((val as u32) & 0xff) << 16usize); - } -} -impl Default for Page17lock0 { - #[inline(always)] - fn default() -> Page17lock0 { - Page17lock0(0) - } -} -#[doc = "Lock configuration MSBs for page 17 (rows 0x440 through 0x47f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions."] -#[repr(transparent)] -#[derive(Copy, Clone, Eq, PartialEq)] -pub struct Page17lock1(pub u32); -impl Page17lock1 { - #[doc = "Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers."] - #[inline(always)] - pub const fn lock_s(&self) -> super::vals::Page17lock1lockS { - let val = (self.0 >> 0usize) & 0x03; - super::vals::Page17lock1lockS::from_bits(val as u8) - } - #[doc = "Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers."] - #[inline(always)] - pub fn set_lock_s(&mut self, val: super::vals::Page17lock1lockS) { - self.0 = (self.0 & !(0x03 << 0usize)) | (((val.to_bits() as u32) & 0x03) << 0usize); - } - #[doc = "Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API."] - #[inline(always)] - pub const fn lock_ns(&self) -> super::vals::Page17lock1lockNs { - let val = (self.0 >> 2usize) & 0x03; - super::vals::Page17lock1lockNs::from_bits(val as u8) - } - #[doc = "Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API."] - #[inline(always)] - pub fn set_lock_ns(&mut self, val: super::vals::Page17lock1lockNs) { - self.0 = (self.0 & !(0x03 << 2usize)) | (((val.to_bits() as u32) & 0x03) << 2usize); - } - #[doc = "Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers."] - #[inline(always)] - pub const fn lock_bl(&self) -> super::vals::Page17lock1lockBl { - let val = (self.0 >> 4usize) & 0x03; - super::vals::Page17lock1lockBl::from_bits(val as u8) - } - #[doc = "Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers."] - #[inline(always)] - pub fn set_lock_bl(&mut self, val: super::vals::Page17lock1lockBl) { - self.0 = (self.0 & !(0x03 << 4usize)) | (((val.to_bits() as u32) & 0x03) << 4usize); - } - #[doc = "Redundant copy of bits 7:0"] - #[inline(always)] - pub const fn r1(&self) -> u8 { - let val = (self.0 >> 8usize) & 0xff; - val as u8 - } - #[doc = "Redundant copy of bits 7:0"] - #[inline(always)] - pub fn set_r1(&mut self, val: u8) { - self.0 = (self.0 & !(0xff << 8usize)) | (((val as u32) & 0xff) << 8usize); - } - #[doc = "Redundant copy of bits 7:0"] - #[inline(always)] - pub const fn r2(&self) -> u8 { - let val = (self.0 >> 16usize) & 0xff; - val as u8 - } - #[doc = "Redundant copy of bits 7:0"] - #[inline(always)] - pub fn set_r2(&mut self, val: u8) { - self.0 = (self.0 & !(0xff << 16usize)) | (((val as u32) & 0xff) << 16usize); - } -} -impl Default for Page17lock1 { - #[inline(always)] - fn default() -> Page17lock1 { - Page17lock1(0) - } -} -#[doc = "Lock configuration LSBs for page 18 (rows 0x480 through 0x4bf). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions."] -#[repr(transparent)] -#[derive(Copy, Clone, Eq, PartialEq)] -pub struct Page18lock0(pub u32); -impl Page18lock0 { - #[doc = "Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required."] - #[inline(always)] - pub const fn key_w(&self) -> u8 { - let val = (self.0 >> 0usize) & 0x07; - val as u8 - } - #[doc = "Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required."] - #[inline(always)] - pub fn set_key_w(&mut self, val: u8) { - self.0 = (self.0 & !(0x07 << 0usize)) | (((val as u32) & 0x07) << 0usize); - } - #[doc = "Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required."] - #[inline(always)] - pub const fn key_r(&self) -> u8 { - let val = (self.0 >> 3usize) & 0x07; - val as u8 - } - #[doc = "Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required."] - #[inline(always)] - pub fn set_key_r(&mut self, val: u8) { - self.0 = (self.0 & !(0x07 << 3usize)) | (((val as u32) & 0x07) << 3usize); - } - #[doc = "State when at least one key is registered for this page and no matching key has been entered."] - #[inline(always)] - pub const fn no_key_state(&self) -> super::vals::Page18lock0noKeyState { - let val = (self.0 >> 6usize) & 0x01; - super::vals::Page18lock0noKeyState::from_bits(val as u8) - } - #[doc = "State when at least one key is registered for this page and no matching key has been entered."] - #[inline(always)] - pub fn set_no_key_state(&mut self, val: super::vals::Page18lock0noKeyState) { - self.0 = (self.0 & !(0x01 << 6usize)) | (((val.to_bits() as u32) & 0x01) << 6usize); - } - #[doc = "Redundant copy of bits 7:0"] - #[inline(always)] - pub const fn r1(&self) -> u8 { - let val = (self.0 >> 8usize) & 0xff; - val as u8 - } - #[doc = "Redundant copy of bits 7:0"] - #[inline(always)] - pub fn set_r1(&mut self, val: u8) { - self.0 = (self.0 & !(0xff << 8usize)) | (((val as u32) & 0xff) << 8usize); - } - #[doc = "Redundant copy of bits 7:0"] - #[inline(always)] - pub const fn r2(&self) -> u8 { - let val = (self.0 >> 16usize) & 0xff; - val as u8 - } - #[doc = "Redundant copy of bits 7:0"] - #[inline(always)] - pub fn set_r2(&mut self, val: u8) { - self.0 = (self.0 & !(0xff << 16usize)) | (((val as u32) & 0xff) << 16usize); - } -} -impl Default for Page18lock0 { - #[inline(always)] - fn default() -> Page18lock0 { - Page18lock0(0) - } -} -#[doc = "Lock configuration MSBs for page 18 (rows 0x480 through 0x4bf). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions."] -#[repr(transparent)] -#[derive(Copy, Clone, Eq, PartialEq)] -pub struct Page18lock1(pub u32); -impl Page18lock1 { - #[doc = "Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers."] - #[inline(always)] - pub const fn lock_s(&self) -> super::vals::Page18lock1lockS { - let val = (self.0 >> 0usize) & 0x03; - super::vals::Page18lock1lockS::from_bits(val as u8) - } - #[doc = "Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers."] - #[inline(always)] - pub fn set_lock_s(&mut self, val: super::vals::Page18lock1lockS) { - self.0 = (self.0 & !(0x03 << 0usize)) | (((val.to_bits() as u32) & 0x03) << 0usize); - } - #[doc = "Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API."] - #[inline(always)] - pub const fn lock_ns(&self) -> super::vals::Page18lock1lockNs { - let val = (self.0 >> 2usize) & 0x03; - super::vals::Page18lock1lockNs::from_bits(val as u8) - } - #[doc = "Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API."] - #[inline(always)] - pub fn set_lock_ns(&mut self, val: super::vals::Page18lock1lockNs) { - self.0 = (self.0 & !(0x03 << 2usize)) | (((val.to_bits() as u32) & 0x03) << 2usize); - } - #[doc = "Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers."] - #[inline(always)] - pub const fn lock_bl(&self) -> super::vals::Page18lock1lockBl { - let val = (self.0 >> 4usize) & 0x03; - super::vals::Page18lock1lockBl::from_bits(val as u8) - } - #[doc = "Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers."] - #[inline(always)] - pub fn set_lock_bl(&mut self, val: super::vals::Page18lock1lockBl) { - self.0 = (self.0 & !(0x03 << 4usize)) | (((val.to_bits() as u32) & 0x03) << 4usize); - } - #[doc = "Redundant copy of bits 7:0"] - #[inline(always)] - pub const fn r1(&self) -> u8 { - let val = (self.0 >> 8usize) & 0xff; - val as u8 - } - #[doc = "Redundant copy of bits 7:0"] - #[inline(always)] - pub fn set_r1(&mut self, val: u8) { - self.0 = (self.0 & !(0xff << 8usize)) | (((val as u32) & 0xff) << 8usize); - } - #[doc = "Redundant copy of bits 7:0"] - #[inline(always)] - pub const fn r2(&self) -> u8 { - let val = (self.0 >> 16usize) & 0xff; - val as u8 - } - #[doc = "Redundant copy of bits 7:0"] - #[inline(always)] - pub fn set_r2(&mut self, val: u8) { - self.0 = (self.0 & !(0xff << 16usize)) | (((val as u32) & 0xff) << 16usize); - } -} -impl Default for Page18lock1 { - #[inline(always)] - fn default() -> Page18lock1 { - Page18lock1(0) - } -} -#[doc = "Lock configuration LSBs for page 19 (rows 0x4c0 through 0x4ff). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions."] -#[repr(transparent)] -#[derive(Copy, Clone, Eq, PartialEq)] -pub struct Page19lock0(pub u32); -impl Page19lock0 { - #[doc = "Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required."] - #[inline(always)] - pub const fn key_w(&self) -> u8 { - let val = (self.0 >> 0usize) & 0x07; - val as u8 - } - #[doc = "Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required."] - #[inline(always)] - pub fn set_key_w(&mut self, val: u8) { - self.0 = (self.0 & !(0x07 << 0usize)) | (((val as u32) & 0x07) << 0usize); - } - #[doc = "Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required."] - #[inline(always)] - pub const fn key_r(&self) -> u8 { - let val = (self.0 >> 3usize) & 0x07; - val as u8 - } - #[doc = "Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required."] - #[inline(always)] - pub fn set_key_r(&mut self, val: u8) { - self.0 = (self.0 & !(0x07 << 3usize)) | (((val as u32) & 0x07) << 3usize); - } - #[doc = "State when at least one key is registered for this page and no matching key has been entered."] - #[inline(always)] - pub const fn no_key_state(&self) -> super::vals::Page19lock0noKeyState { - let val = (self.0 >> 6usize) & 0x01; - super::vals::Page19lock0noKeyState::from_bits(val as u8) - } - #[doc = "State when at least one key is registered for this page and no matching key has been entered."] - #[inline(always)] - pub fn set_no_key_state(&mut self, val: super::vals::Page19lock0noKeyState) { - self.0 = (self.0 & !(0x01 << 6usize)) | (((val.to_bits() as u32) & 0x01) << 6usize); - } - #[doc = "Redundant copy of bits 7:0"] - #[inline(always)] - pub const fn r1(&self) -> u8 { - let val = (self.0 >> 8usize) & 0xff; - val as u8 - } - #[doc = "Redundant copy of bits 7:0"] - #[inline(always)] - pub fn set_r1(&mut self, val: u8) { - self.0 = (self.0 & !(0xff << 8usize)) | (((val as u32) & 0xff) << 8usize); - } - #[doc = "Redundant copy of bits 7:0"] - #[inline(always)] - pub const fn r2(&self) -> u8 { - let val = (self.0 >> 16usize) & 0xff; - val as u8 - } - #[doc = "Redundant copy of bits 7:0"] - #[inline(always)] - pub fn set_r2(&mut self, val: u8) { - self.0 = (self.0 & !(0xff << 16usize)) | (((val as u32) & 0xff) << 16usize); - } -} -impl Default for Page19lock0 { - #[inline(always)] - fn default() -> Page19lock0 { - Page19lock0(0) - } -} -#[doc = "Lock configuration MSBs for page 19 (rows 0x4c0 through 0x4ff). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions."] -#[repr(transparent)] -#[derive(Copy, Clone, Eq, PartialEq)] -pub struct Page19lock1(pub u32); -impl Page19lock1 { - #[doc = "Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers."] - #[inline(always)] - pub const fn lock_s(&self) -> super::vals::Page19lock1lockS { - let val = (self.0 >> 0usize) & 0x03; - super::vals::Page19lock1lockS::from_bits(val as u8) - } - #[doc = "Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers."] - #[inline(always)] - pub fn set_lock_s(&mut self, val: super::vals::Page19lock1lockS) { - self.0 = (self.0 & !(0x03 << 0usize)) | (((val.to_bits() as u32) & 0x03) << 0usize); - } - #[doc = "Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API."] - #[inline(always)] - pub const fn lock_ns(&self) -> super::vals::Page19lock1lockNs { - let val = (self.0 >> 2usize) & 0x03; - super::vals::Page19lock1lockNs::from_bits(val as u8) - } - #[doc = "Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API."] - #[inline(always)] - pub fn set_lock_ns(&mut self, val: super::vals::Page19lock1lockNs) { - self.0 = (self.0 & !(0x03 << 2usize)) | (((val.to_bits() as u32) & 0x03) << 2usize); - } - #[doc = "Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers."] - #[inline(always)] - pub const fn lock_bl(&self) -> super::vals::Page19lock1lockBl { - let val = (self.0 >> 4usize) & 0x03; - super::vals::Page19lock1lockBl::from_bits(val as u8) - } - #[doc = "Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers."] - #[inline(always)] - pub fn set_lock_bl(&mut self, val: super::vals::Page19lock1lockBl) { - self.0 = (self.0 & !(0x03 << 4usize)) | (((val.to_bits() as u32) & 0x03) << 4usize); - } - #[doc = "Redundant copy of bits 7:0"] - #[inline(always)] - pub const fn r1(&self) -> u8 { - let val = (self.0 >> 8usize) & 0xff; - val as u8 - } - #[doc = "Redundant copy of bits 7:0"] - #[inline(always)] - pub fn set_r1(&mut self, val: u8) { - self.0 = (self.0 & !(0xff << 8usize)) | (((val as u32) & 0xff) << 8usize); - } - #[doc = "Redundant copy of bits 7:0"] - #[inline(always)] - pub const fn r2(&self) -> u8 { - let val = (self.0 >> 16usize) & 0xff; - val as u8 - } - #[doc = "Redundant copy of bits 7:0"] - #[inline(always)] - pub fn set_r2(&mut self, val: u8) { - self.0 = (self.0 & !(0xff << 16usize)) | (((val as u32) & 0xff) << 16usize); - } -} -impl Default for Page19lock1 { - #[inline(always)] - fn default() -> Page19lock1 { - Page19lock1(0) - } -} -#[doc = "Lock configuration LSBs for page 1 (rows 0x40 through 0x7f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions."] -#[repr(transparent)] -#[derive(Copy, Clone, Eq, PartialEq)] -pub struct Page1lock0(pub u32); -impl Page1lock0 { - #[doc = "Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required."] - #[inline(always)] - pub const fn key_w(&self) -> u8 { - let val = (self.0 >> 0usize) & 0x07; - val as u8 - } - #[doc = "Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required."] - #[inline(always)] - pub fn set_key_w(&mut self, val: u8) { - self.0 = (self.0 & !(0x07 << 0usize)) | (((val as u32) & 0x07) << 0usize); - } - #[doc = "Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required."] - #[inline(always)] - pub const fn key_r(&self) -> u8 { - let val = (self.0 >> 3usize) & 0x07; - val as u8 - } - #[doc = "Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required."] - #[inline(always)] - pub fn set_key_r(&mut self, val: u8) { - self.0 = (self.0 & !(0x07 << 3usize)) | (((val as u32) & 0x07) << 3usize); - } - #[doc = "State when at least one key is registered for this page and no matching key has been entered."] - #[inline(always)] - pub const fn no_key_state(&self) -> super::vals::Page1lock0noKeyState { - let val = (self.0 >> 6usize) & 0x01; - super::vals::Page1lock0noKeyState::from_bits(val as u8) - } - #[doc = "State when at least one key is registered for this page and no matching key has been entered."] - #[inline(always)] - pub fn set_no_key_state(&mut self, val: super::vals::Page1lock0noKeyState) { - self.0 = (self.0 & !(0x01 << 6usize)) | (((val.to_bits() as u32) & 0x01) << 6usize); - } - #[doc = "Redundant copy of bits 7:0"] - #[inline(always)] - pub const fn r1(&self) -> u8 { - let val = (self.0 >> 8usize) & 0xff; - val as u8 - } - #[doc = "Redundant copy of bits 7:0"] - #[inline(always)] - pub fn set_r1(&mut self, val: u8) { - self.0 = (self.0 & !(0xff << 8usize)) | (((val as u32) & 0xff) << 8usize); - } - #[doc = "Redundant copy of bits 7:0"] - #[inline(always)] - pub const fn r2(&self) -> u8 { - let val = (self.0 >> 16usize) & 0xff; - val as u8 - } - #[doc = "Redundant copy of bits 7:0"] - #[inline(always)] - pub fn set_r2(&mut self, val: u8) { - self.0 = (self.0 & !(0xff << 16usize)) | (((val as u32) & 0xff) << 16usize); - } -} -impl Default for Page1lock0 { - #[inline(always)] - fn default() -> Page1lock0 { - Page1lock0(0) - } -} -#[doc = "Lock configuration MSBs for page 1 (rows 0x40 through 0x7f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions."] -#[repr(transparent)] -#[derive(Copy, Clone, Eq, PartialEq)] -pub struct Page1lock1(pub u32); -impl Page1lock1 { - #[doc = "Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers."] - #[inline(always)] - pub const fn lock_s(&self) -> super::vals::Page1lock1lockS { - let val = (self.0 >> 0usize) & 0x03; - super::vals::Page1lock1lockS::from_bits(val as u8) - } - #[doc = "Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers."] - #[inline(always)] - pub fn set_lock_s(&mut self, val: super::vals::Page1lock1lockS) { - self.0 = (self.0 & !(0x03 << 0usize)) | (((val.to_bits() as u32) & 0x03) << 0usize); - } - #[doc = "Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API."] - #[inline(always)] - pub const fn lock_ns(&self) -> super::vals::Page1lock1lockNs { - let val = (self.0 >> 2usize) & 0x03; - super::vals::Page1lock1lockNs::from_bits(val as u8) - } - #[doc = "Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API."] - #[inline(always)] - pub fn set_lock_ns(&mut self, val: super::vals::Page1lock1lockNs) { - self.0 = (self.0 & !(0x03 << 2usize)) | (((val.to_bits() as u32) & 0x03) << 2usize); - } - #[doc = "Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers."] - #[inline(always)] - pub const fn lock_bl(&self) -> super::vals::Page1lock1lockBl { - let val = (self.0 >> 4usize) & 0x03; - super::vals::Page1lock1lockBl::from_bits(val as u8) - } - #[doc = "Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers."] - #[inline(always)] - pub fn set_lock_bl(&mut self, val: super::vals::Page1lock1lockBl) { - self.0 = (self.0 & !(0x03 << 4usize)) | (((val.to_bits() as u32) & 0x03) << 4usize); - } - #[doc = "Redundant copy of bits 7:0"] - #[inline(always)] - pub const fn r1(&self) -> u8 { - let val = (self.0 >> 8usize) & 0xff; - val as u8 - } - #[doc = "Redundant copy of bits 7:0"] - #[inline(always)] - pub fn set_r1(&mut self, val: u8) { - self.0 = (self.0 & !(0xff << 8usize)) | (((val as u32) & 0xff) << 8usize); - } - #[doc = "Redundant copy of bits 7:0"] - #[inline(always)] - pub const fn r2(&self) -> u8 { - let val = (self.0 >> 16usize) & 0xff; - val as u8 - } - #[doc = "Redundant copy of bits 7:0"] - #[inline(always)] - pub fn set_r2(&mut self, val: u8) { - self.0 = (self.0 & !(0xff << 16usize)) | (((val as u32) & 0xff) << 16usize); - } -} -impl Default for Page1lock1 { - #[inline(always)] - fn default() -> Page1lock1 { - Page1lock1(0) - } -} -#[doc = "Lock configuration LSBs for page 20 (rows 0x500 through 0x53f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions."] -#[repr(transparent)] -#[derive(Copy, Clone, Eq, PartialEq)] -pub struct Page20lock0(pub u32); -impl Page20lock0 { - #[doc = "Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required."] - #[inline(always)] - pub const fn key_w(&self) -> u8 { - let val = (self.0 >> 0usize) & 0x07; - val as u8 - } - #[doc = "Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required."] - #[inline(always)] - pub fn set_key_w(&mut self, val: u8) { - self.0 = (self.0 & !(0x07 << 0usize)) | (((val as u32) & 0x07) << 0usize); - } - #[doc = "Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required."] - #[inline(always)] - pub const fn key_r(&self) -> u8 { - let val = (self.0 >> 3usize) & 0x07; - val as u8 - } - #[doc = "Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required."] - #[inline(always)] - pub fn set_key_r(&mut self, val: u8) { - self.0 = (self.0 & !(0x07 << 3usize)) | (((val as u32) & 0x07) << 3usize); - } - #[doc = "State when at least one key is registered for this page and no matching key has been entered."] - #[inline(always)] - pub const fn no_key_state(&self) -> super::vals::Page20lock0noKeyState { - let val = (self.0 >> 6usize) & 0x01; - super::vals::Page20lock0noKeyState::from_bits(val as u8) - } - #[doc = "State when at least one key is registered for this page and no matching key has been entered."] - #[inline(always)] - pub fn set_no_key_state(&mut self, val: super::vals::Page20lock0noKeyState) { - self.0 = (self.0 & !(0x01 << 6usize)) | (((val.to_bits() as u32) & 0x01) << 6usize); - } - #[doc = "Redundant copy of bits 7:0"] - #[inline(always)] - pub const fn r1(&self) -> u8 { - let val = (self.0 >> 8usize) & 0xff; - val as u8 - } - #[doc = "Redundant copy of bits 7:0"] - #[inline(always)] - pub fn set_r1(&mut self, val: u8) { - self.0 = (self.0 & !(0xff << 8usize)) | (((val as u32) & 0xff) << 8usize); - } - #[doc = "Redundant copy of bits 7:0"] - #[inline(always)] - pub const fn r2(&self) -> u8 { - let val = (self.0 >> 16usize) & 0xff; - val as u8 - } - #[doc = "Redundant copy of bits 7:0"] - #[inline(always)] - pub fn set_r2(&mut self, val: u8) { - self.0 = (self.0 & !(0xff << 16usize)) | (((val as u32) & 0xff) << 16usize); - } -} -impl Default for Page20lock0 { - #[inline(always)] - fn default() -> Page20lock0 { - Page20lock0(0) - } -} -#[doc = "Lock configuration MSBs for page 20 (rows 0x500 through 0x53f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions."] -#[repr(transparent)] -#[derive(Copy, Clone, Eq, PartialEq)] -pub struct Page20lock1(pub u32); -impl Page20lock1 { - #[doc = "Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers."] - #[inline(always)] - pub const fn lock_s(&self) -> super::vals::Page20lock1lockS { - let val = (self.0 >> 0usize) & 0x03; - super::vals::Page20lock1lockS::from_bits(val as u8) - } - #[doc = "Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers."] - #[inline(always)] - pub fn set_lock_s(&mut self, val: super::vals::Page20lock1lockS) { - self.0 = (self.0 & !(0x03 << 0usize)) | (((val.to_bits() as u32) & 0x03) << 0usize); - } - #[doc = "Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API."] - #[inline(always)] - pub const fn lock_ns(&self) -> super::vals::Page20lock1lockNs { - let val = (self.0 >> 2usize) & 0x03; - super::vals::Page20lock1lockNs::from_bits(val as u8) - } - #[doc = "Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API."] - #[inline(always)] - pub fn set_lock_ns(&mut self, val: super::vals::Page20lock1lockNs) { - self.0 = (self.0 & !(0x03 << 2usize)) | (((val.to_bits() as u32) & 0x03) << 2usize); - } - #[doc = "Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers."] - #[inline(always)] - pub const fn lock_bl(&self) -> super::vals::Page20lock1lockBl { - let val = (self.0 >> 4usize) & 0x03; - super::vals::Page20lock1lockBl::from_bits(val as u8) - } - #[doc = "Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers."] - #[inline(always)] - pub fn set_lock_bl(&mut self, val: super::vals::Page20lock1lockBl) { - self.0 = (self.0 & !(0x03 << 4usize)) | (((val.to_bits() as u32) & 0x03) << 4usize); - } - #[doc = "Redundant copy of bits 7:0"] - #[inline(always)] - pub const fn r1(&self) -> u8 { - let val = (self.0 >> 8usize) & 0xff; - val as u8 - } - #[doc = "Redundant copy of bits 7:0"] - #[inline(always)] - pub fn set_r1(&mut self, val: u8) { - self.0 = (self.0 & !(0xff << 8usize)) | (((val as u32) & 0xff) << 8usize); - } - #[doc = "Redundant copy of bits 7:0"] - #[inline(always)] - pub const fn r2(&self) -> u8 { - let val = (self.0 >> 16usize) & 0xff; - val as u8 - } - #[doc = "Redundant copy of bits 7:0"] - #[inline(always)] - pub fn set_r2(&mut self, val: u8) { - self.0 = (self.0 & !(0xff << 16usize)) | (((val as u32) & 0xff) << 16usize); - } -} -impl Default for Page20lock1 { - #[inline(always)] - fn default() -> Page20lock1 { - Page20lock1(0) - } -} -#[doc = "Lock configuration LSBs for page 21 (rows 0x540 through 0x57f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions."] -#[repr(transparent)] -#[derive(Copy, Clone, Eq, PartialEq)] -pub struct Page21lock0(pub u32); -impl Page21lock0 { - #[doc = "Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required."] - #[inline(always)] - pub const fn key_w(&self) -> u8 { - let val = (self.0 >> 0usize) & 0x07; - val as u8 - } - #[doc = "Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required."] - #[inline(always)] - pub fn set_key_w(&mut self, val: u8) { - self.0 = (self.0 & !(0x07 << 0usize)) | (((val as u32) & 0x07) << 0usize); - } - #[doc = "Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required."] - #[inline(always)] - pub const fn key_r(&self) -> u8 { - let val = (self.0 >> 3usize) & 0x07; - val as u8 - } - #[doc = "Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required."] - #[inline(always)] - pub fn set_key_r(&mut self, val: u8) { - self.0 = (self.0 & !(0x07 << 3usize)) | (((val as u32) & 0x07) << 3usize); - } - #[doc = "State when at least one key is registered for this page and no matching key has been entered."] - #[inline(always)] - pub const fn no_key_state(&self) -> super::vals::Page21lock0noKeyState { - let val = (self.0 >> 6usize) & 0x01; - super::vals::Page21lock0noKeyState::from_bits(val as u8) - } - #[doc = "State when at least one key is registered for this page and no matching key has been entered."] - #[inline(always)] - pub fn set_no_key_state(&mut self, val: super::vals::Page21lock0noKeyState) { - self.0 = (self.0 & !(0x01 << 6usize)) | (((val.to_bits() as u32) & 0x01) << 6usize); - } - #[doc = "Redundant copy of bits 7:0"] - #[inline(always)] - pub const fn r1(&self) -> u8 { - let val = (self.0 >> 8usize) & 0xff; - val as u8 - } - #[doc = "Redundant copy of bits 7:0"] - #[inline(always)] - pub fn set_r1(&mut self, val: u8) { - self.0 = (self.0 & !(0xff << 8usize)) | (((val as u32) & 0xff) << 8usize); - } - #[doc = "Redundant copy of bits 7:0"] - #[inline(always)] - pub const fn r2(&self) -> u8 { - let val = (self.0 >> 16usize) & 0xff; - val as u8 - } - #[doc = "Redundant copy of bits 7:0"] - #[inline(always)] - pub fn set_r2(&mut self, val: u8) { - self.0 = (self.0 & !(0xff << 16usize)) | (((val as u32) & 0xff) << 16usize); - } -} -impl Default for Page21lock0 { - #[inline(always)] - fn default() -> Page21lock0 { - Page21lock0(0) - } -} -#[doc = "Lock configuration MSBs for page 21 (rows 0x540 through 0x57f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions."] -#[repr(transparent)] -#[derive(Copy, Clone, Eq, PartialEq)] -pub struct Page21lock1(pub u32); -impl Page21lock1 { - #[doc = "Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers."] - #[inline(always)] - pub const fn lock_s(&self) -> super::vals::Page21lock1lockS { - let val = (self.0 >> 0usize) & 0x03; - super::vals::Page21lock1lockS::from_bits(val as u8) - } - #[doc = "Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers."] - #[inline(always)] - pub fn set_lock_s(&mut self, val: super::vals::Page21lock1lockS) { - self.0 = (self.0 & !(0x03 << 0usize)) | (((val.to_bits() as u32) & 0x03) << 0usize); - } - #[doc = "Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API."] - #[inline(always)] - pub const fn lock_ns(&self) -> super::vals::Page21lock1lockNs { - let val = (self.0 >> 2usize) & 0x03; - super::vals::Page21lock1lockNs::from_bits(val as u8) - } - #[doc = "Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API."] - #[inline(always)] - pub fn set_lock_ns(&mut self, val: super::vals::Page21lock1lockNs) { - self.0 = (self.0 & !(0x03 << 2usize)) | (((val.to_bits() as u32) & 0x03) << 2usize); - } - #[doc = "Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers."] - #[inline(always)] - pub const fn lock_bl(&self) -> super::vals::Page21lock1lockBl { - let val = (self.0 >> 4usize) & 0x03; - super::vals::Page21lock1lockBl::from_bits(val as u8) - } - #[doc = "Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers."] - #[inline(always)] - pub fn set_lock_bl(&mut self, val: super::vals::Page21lock1lockBl) { - self.0 = (self.0 & !(0x03 << 4usize)) | (((val.to_bits() as u32) & 0x03) << 4usize); - } - #[doc = "Redundant copy of bits 7:0"] - #[inline(always)] - pub const fn r1(&self) -> u8 { - let val = (self.0 >> 8usize) & 0xff; - val as u8 - } - #[doc = "Redundant copy of bits 7:0"] - #[inline(always)] - pub fn set_r1(&mut self, val: u8) { - self.0 = (self.0 & !(0xff << 8usize)) | (((val as u32) & 0xff) << 8usize); - } - #[doc = "Redundant copy of bits 7:0"] - #[inline(always)] - pub const fn r2(&self) -> u8 { - let val = (self.0 >> 16usize) & 0xff; - val as u8 - } - #[doc = "Redundant copy of bits 7:0"] - #[inline(always)] - pub fn set_r2(&mut self, val: u8) { - self.0 = (self.0 & !(0xff << 16usize)) | (((val as u32) & 0xff) << 16usize); - } -} -impl Default for Page21lock1 { - #[inline(always)] - fn default() -> Page21lock1 { - Page21lock1(0) - } -} -#[doc = "Lock configuration LSBs for page 22 (rows 0x580 through 0x5bf). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions."] -#[repr(transparent)] -#[derive(Copy, Clone, Eq, PartialEq)] -pub struct Page22lock0(pub u32); -impl Page22lock0 { - #[doc = "Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required."] - #[inline(always)] - pub const fn key_w(&self) -> u8 { - let val = (self.0 >> 0usize) & 0x07; - val as u8 - } - #[doc = "Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required."] - #[inline(always)] - pub fn set_key_w(&mut self, val: u8) { - self.0 = (self.0 & !(0x07 << 0usize)) | (((val as u32) & 0x07) << 0usize); - } - #[doc = "Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required."] - #[inline(always)] - pub const fn key_r(&self) -> u8 { - let val = (self.0 >> 3usize) & 0x07; - val as u8 - } - #[doc = "Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required."] - #[inline(always)] - pub fn set_key_r(&mut self, val: u8) { - self.0 = (self.0 & !(0x07 << 3usize)) | (((val as u32) & 0x07) << 3usize); - } - #[doc = "State when at least one key is registered for this page and no matching key has been entered."] - #[inline(always)] - pub const fn no_key_state(&self) -> super::vals::Page22lock0noKeyState { - let val = (self.0 >> 6usize) & 0x01; - super::vals::Page22lock0noKeyState::from_bits(val as u8) - } - #[doc = "State when at least one key is registered for this page and no matching key has been entered."] - #[inline(always)] - pub fn set_no_key_state(&mut self, val: super::vals::Page22lock0noKeyState) { - self.0 = (self.0 & !(0x01 << 6usize)) | (((val.to_bits() as u32) & 0x01) << 6usize); - } - #[doc = "Redundant copy of bits 7:0"] - #[inline(always)] - pub const fn r1(&self) -> u8 { - let val = (self.0 >> 8usize) & 0xff; - val as u8 - } - #[doc = "Redundant copy of bits 7:0"] - #[inline(always)] - pub fn set_r1(&mut self, val: u8) { - self.0 = (self.0 & !(0xff << 8usize)) | (((val as u32) & 0xff) << 8usize); - } - #[doc = "Redundant copy of bits 7:0"] - #[inline(always)] - pub const fn r2(&self) -> u8 { - let val = (self.0 >> 16usize) & 0xff; - val as u8 - } - #[doc = "Redundant copy of bits 7:0"] - #[inline(always)] - pub fn set_r2(&mut self, val: u8) { - self.0 = (self.0 & !(0xff << 16usize)) | (((val as u32) & 0xff) << 16usize); - } -} -impl Default for Page22lock0 { - #[inline(always)] - fn default() -> Page22lock0 { - Page22lock0(0) - } -} -#[doc = "Lock configuration MSBs for page 22 (rows 0x580 through 0x5bf). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions."] -#[repr(transparent)] -#[derive(Copy, Clone, Eq, PartialEq)] -pub struct Page22lock1(pub u32); -impl Page22lock1 { - #[doc = "Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers."] - #[inline(always)] - pub const fn lock_s(&self) -> super::vals::Page22lock1lockS { - let val = (self.0 >> 0usize) & 0x03; - super::vals::Page22lock1lockS::from_bits(val as u8) - } - #[doc = "Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers."] - #[inline(always)] - pub fn set_lock_s(&mut self, val: super::vals::Page22lock1lockS) { - self.0 = (self.0 & !(0x03 << 0usize)) | (((val.to_bits() as u32) & 0x03) << 0usize); - } - #[doc = "Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API."] - #[inline(always)] - pub const fn lock_ns(&self) -> super::vals::Page22lock1lockNs { - let val = (self.0 >> 2usize) & 0x03; - super::vals::Page22lock1lockNs::from_bits(val as u8) - } - #[doc = "Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API."] - #[inline(always)] - pub fn set_lock_ns(&mut self, val: super::vals::Page22lock1lockNs) { - self.0 = (self.0 & !(0x03 << 2usize)) | (((val.to_bits() as u32) & 0x03) << 2usize); - } - #[doc = "Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers."] - #[inline(always)] - pub const fn lock_bl(&self) -> super::vals::Page22lock1lockBl { - let val = (self.0 >> 4usize) & 0x03; - super::vals::Page22lock1lockBl::from_bits(val as u8) - } - #[doc = "Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers."] - #[inline(always)] - pub fn set_lock_bl(&mut self, val: super::vals::Page22lock1lockBl) { - self.0 = (self.0 & !(0x03 << 4usize)) | (((val.to_bits() as u32) & 0x03) << 4usize); - } - #[doc = "Redundant copy of bits 7:0"] - #[inline(always)] - pub const fn r1(&self) -> u8 { - let val = (self.0 >> 8usize) & 0xff; - val as u8 - } - #[doc = "Redundant copy of bits 7:0"] - #[inline(always)] - pub fn set_r1(&mut self, val: u8) { - self.0 = (self.0 & !(0xff << 8usize)) | (((val as u32) & 0xff) << 8usize); - } - #[doc = "Redundant copy of bits 7:0"] - #[inline(always)] - pub const fn r2(&self) -> u8 { - let val = (self.0 >> 16usize) & 0xff; - val as u8 - } - #[doc = "Redundant copy of bits 7:0"] - #[inline(always)] - pub fn set_r2(&mut self, val: u8) { - self.0 = (self.0 & !(0xff << 16usize)) | (((val as u32) & 0xff) << 16usize); - } -} -impl Default for Page22lock1 { - #[inline(always)] - fn default() -> Page22lock1 { - Page22lock1(0) - } -} -#[doc = "Lock configuration LSBs for page 23 (rows 0x5c0 through 0x5ff). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions."] -#[repr(transparent)] -#[derive(Copy, Clone, Eq, PartialEq)] -pub struct Page23lock0(pub u32); -impl Page23lock0 { - #[doc = "Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required."] - #[inline(always)] - pub const fn key_w(&self) -> u8 { - let val = (self.0 >> 0usize) & 0x07; - val as u8 - } - #[doc = "Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required."] - #[inline(always)] - pub fn set_key_w(&mut self, val: u8) { - self.0 = (self.0 & !(0x07 << 0usize)) | (((val as u32) & 0x07) << 0usize); - } - #[doc = "Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required."] - #[inline(always)] - pub const fn key_r(&self) -> u8 { - let val = (self.0 >> 3usize) & 0x07; - val as u8 - } - #[doc = "Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required."] - #[inline(always)] - pub fn set_key_r(&mut self, val: u8) { - self.0 = (self.0 & !(0x07 << 3usize)) | (((val as u32) & 0x07) << 3usize); - } - #[doc = "State when at least one key is registered for this page and no matching key has been entered."] - #[inline(always)] - pub const fn no_key_state(&self) -> super::vals::Page23lock0noKeyState { - let val = (self.0 >> 6usize) & 0x01; - super::vals::Page23lock0noKeyState::from_bits(val as u8) - } - #[doc = "State when at least one key is registered for this page and no matching key has been entered."] - #[inline(always)] - pub fn set_no_key_state(&mut self, val: super::vals::Page23lock0noKeyState) { - self.0 = (self.0 & !(0x01 << 6usize)) | (((val.to_bits() as u32) & 0x01) << 6usize); - } - #[doc = "Redundant copy of bits 7:0"] - #[inline(always)] - pub const fn r1(&self) -> u8 { - let val = (self.0 >> 8usize) & 0xff; - val as u8 - } - #[doc = "Redundant copy of bits 7:0"] - #[inline(always)] - pub fn set_r1(&mut self, val: u8) { - self.0 = (self.0 & !(0xff << 8usize)) | (((val as u32) & 0xff) << 8usize); - } - #[doc = "Redundant copy of bits 7:0"] - #[inline(always)] - pub const fn r2(&self) -> u8 { - let val = (self.0 >> 16usize) & 0xff; - val as u8 - } - #[doc = "Redundant copy of bits 7:0"] - #[inline(always)] - pub fn set_r2(&mut self, val: u8) { - self.0 = (self.0 & !(0xff << 16usize)) | (((val as u32) & 0xff) << 16usize); - } -} -impl Default for Page23lock0 { - #[inline(always)] - fn default() -> Page23lock0 { - Page23lock0(0) - } -} -#[doc = "Lock configuration MSBs for page 23 (rows 0x5c0 through 0x5ff). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions."] -#[repr(transparent)] -#[derive(Copy, Clone, Eq, PartialEq)] -pub struct Page23lock1(pub u32); -impl Page23lock1 { - #[doc = "Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers."] - #[inline(always)] - pub const fn lock_s(&self) -> super::vals::Page23lock1lockS { - let val = (self.0 >> 0usize) & 0x03; - super::vals::Page23lock1lockS::from_bits(val as u8) - } - #[doc = "Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers."] - #[inline(always)] - pub fn set_lock_s(&mut self, val: super::vals::Page23lock1lockS) { - self.0 = (self.0 & !(0x03 << 0usize)) | (((val.to_bits() as u32) & 0x03) << 0usize); - } - #[doc = "Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API."] - #[inline(always)] - pub const fn lock_ns(&self) -> super::vals::Page23lock1lockNs { - let val = (self.0 >> 2usize) & 0x03; - super::vals::Page23lock1lockNs::from_bits(val as u8) - } - #[doc = "Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API."] - #[inline(always)] - pub fn set_lock_ns(&mut self, val: super::vals::Page23lock1lockNs) { - self.0 = (self.0 & !(0x03 << 2usize)) | (((val.to_bits() as u32) & 0x03) << 2usize); - } - #[doc = "Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers."] - #[inline(always)] - pub const fn lock_bl(&self) -> super::vals::Page23lock1lockBl { - let val = (self.0 >> 4usize) & 0x03; - super::vals::Page23lock1lockBl::from_bits(val as u8) - } - #[doc = "Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers."] - #[inline(always)] - pub fn set_lock_bl(&mut self, val: super::vals::Page23lock1lockBl) { - self.0 = (self.0 & !(0x03 << 4usize)) | (((val.to_bits() as u32) & 0x03) << 4usize); - } - #[doc = "Redundant copy of bits 7:0"] - #[inline(always)] - pub const fn r1(&self) -> u8 { - let val = (self.0 >> 8usize) & 0xff; - val as u8 - } - #[doc = "Redundant copy of bits 7:0"] - #[inline(always)] - pub fn set_r1(&mut self, val: u8) { - self.0 = (self.0 & !(0xff << 8usize)) | (((val as u32) & 0xff) << 8usize); - } - #[doc = "Redundant copy of bits 7:0"] - #[inline(always)] - pub const fn r2(&self) -> u8 { - let val = (self.0 >> 16usize) & 0xff; - val as u8 - } - #[doc = "Redundant copy of bits 7:0"] - #[inline(always)] - pub fn set_r2(&mut self, val: u8) { - self.0 = (self.0 & !(0xff << 16usize)) | (((val as u32) & 0xff) << 16usize); - } -} -impl Default for Page23lock1 { - #[inline(always)] - fn default() -> Page23lock1 { - Page23lock1(0) - } -} -#[doc = "Lock configuration LSBs for page 24 (rows 0x600 through 0x63f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions."] -#[repr(transparent)] -#[derive(Copy, Clone, Eq, PartialEq)] -pub struct Page24lock0(pub u32); -impl Page24lock0 { - #[doc = "Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required."] - #[inline(always)] - pub const fn key_w(&self) -> u8 { - let val = (self.0 >> 0usize) & 0x07; - val as u8 - } - #[doc = "Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required."] - #[inline(always)] - pub fn set_key_w(&mut self, val: u8) { - self.0 = (self.0 & !(0x07 << 0usize)) | (((val as u32) & 0x07) << 0usize); - } - #[doc = "Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required."] - #[inline(always)] - pub const fn key_r(&self) -> u8 { - let val = (self.0 >> 3usize) & 0x07; - val as u8 - } - #[doc = "Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required."] - #[inline(always)] - pub fn set_key_r(&mut self, val: u8) { - self.0 = (self.0 & !(0x07 << 3usize)) | (((val as u32) & 0x07) << 3usize); - } - #[doc = "State when at least one key is registered for this page and no matching key has been entered."] - #[inline(always)] - pub const fn no_key_state(&self) -> super::vals::Page24lock0noKeyState { - let val = (self.0 >> 6usize) & 0x01; - super::vals::Page24lock0noKeyState::from_bits(val as u8) - } - #[doc = "State when at least one key is registered for this page and no matching key has been entered."] - #[inline(always)] - pub fn set_no_key_state(&mut self, val: super::vals::Page24lock0noKeyState) { - self.0 = (self.0 & !(0x01 << 6usize)) | (((val.to_bits() as u32) & 0x01) << 6usize); - } - #[doc = "Redundant copy of bits 7:0"] - #[inline(always)] - pub const fn r1(&self) -> u8 { - let val = (self.0 >> 8usize) & 0xff; - val as u8 - } - #[doc = "Redundant copy of bits 7:0"] - #[inline(always)] - pub fn set_r1(&mut self, val: u8) { - self.0 = (self.0 & !(0xff << 8usize)) | (((val as u32) & 0xff) << 8usize); - } - #[doc = "Redundant copy of bits 7:0"] - #[inline(always)] - pub const fn r2(&self) -> u8 { - let val = (self.0 >> 16usize) & 0xff; - val as u8 - } - #[doc = "Redundant copy of bits 7:0"] - #[inline(always)] - pub fn set_r2(&mut self, val: u8) { - self.0 = (self.0 & !(0xff << 16usize)) | (((val as u32) & 0xff) << 16usize); - } -} -impl Default for Page24lock0 { - #[inline(always)] - fn default() -> Page24lock0 { - Page24lock0(0) - } -} -#[doc = "Lock configuration MSBs for page 24 (rows 0x600 through 0x63f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions."] -#[repr(transparent)] -#[derive(Copy, Clone, Eq, PartialEq)] -pub struct Page24lock1(pub u32); -impl Page24lock1 { - #[doc = "Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers."] - #[inline(always)] - pub const fn lock_s(&self) -> super::vals::Page24lock1lockS { - let val = (self.0 >> 0usize) & 0x03; - super::vals::Page24lock1lockS::from_bits(val as u8) - } - #[doc = "Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers."] - #[inline(always)] - pub fn set_lock_s(&mut self, val: super::vals::Page24lock1lockS) { - self.0 = (self.0 & !(0x03 << 0usize)) | (((val.to_bits() as u32) & 0x03) << 0usize); - } - #[doc = "Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API."] - #[inline(always)] - pub const fn lock_ns(&self) -> super::vals::Page24lock1lockNs { - let val = (self.0 >> 2usize) & 0x03; - super::vals::Page24lock1lockNs::from_bits(val as u8) - } - #[doc = "Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API."] - #[inline(always)] - pub fn set_lock_ns(&mut self, val: super::vals::Page24lock1lockNs) { - self.0 = (self.0 & !(0x03 << 2usize)) | (((val.to_bits() as u32) & 0x03) << 2usize); - } - #[doc = "Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers."] - #[inline(always)] - pub const fn lock_bl(&self) -> super::vals::Page24lock1lockBl { - let val = (self.0 >> 4usize) & 0x03; - super::vals::Page24lock1lockBl::from_bits(val as u8) - } - #[doc = "Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers."] - #[inline(always)] - pub fn set_lock_bl(&mut self, val: super::vals::Page24lock1lockBl) { - self.0 = (self.0 & !(0x03 << 4usize)) | (((val.to_bits() as u32) & 0x03) << 4usize); - } - #[doc = "Redundant copy of bits 7:0"] - #[inline(always)] - pub const fn r1(&self) -> u8 { - let val = (self.0 >> 8usize) & 0xff; - val as u8 - } - #[doc = "Redundant copy of bits 7:0"] - #[inline(always)] - pub fn set_r1(&mut self, val: u8) { - self.0 = (self.0 & !(0xff << 8usize)) | (((val as u32) & 0xff) << 8usize); - } - #[doc = "Redundant copy of bits 7:0"] - #[inline(always)] - pub const fn r2(&self) -> u8 { - let val = (self.0 >> 16usize) & 0xff; - val as u8 - } - #[doc = "Redundant copy of bits 7:0"] - #[inline(always)] - pub fn set_r2(&mut self, val: u8) { - self.0 = (self.0 & !(0xff << 16usize)) | (((val as u32) & 0xff) << 16usize); - } -} -impl Default for Page24lock1 { - #[inline(always)] - fn default() -> Page24lock1 { - Page24lock1(0) - } -} -#[doc = "Lock configuration LSBs for page 25 (rows 0x640 through 0x67f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions."] -#[repr(transparent)] -#[derive(Copy, Clone, Eq, PartialEq)] -pub struct Page25lock0(pub u32); -impl Page25lock0 { - #[doc = "Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required."] - #[inline(always)] - pub const fn key_w(&self) -> u8 { - let val = (self.0 >> 0usize) & 0x07; - val as u8 - } - #[doc = "Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required."] - #[inline(always)] - pub fn set_key_w(&mut self, val: u8) { - self.0 = (self.0 & !(0x07 << 0usize)) | (((val as u32) & 0x07) << 0usize); - } - #[doc = "Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required."] - #[inline(always)] - pub const fn key_r(&self) -> u8 { - let val = (self.0 >> 3usize) & 0x07; - val as u8 - } - #[doc = "Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required."] - #[inline(always)] - pub fn set_key_r(&mut self, val: u8) { - self.0 = (self.0 & !(0x07 << 3usize)) | (((val as u32) & 0x07) << 3usize); - } - #[doc = "State when at least one key is registered for this page and no matching key has been entered."] - #[inline(always)] - pub const fn no_key_state(&self) -> super::vals::Page25lock0noKeyState { - let val = (self.0 >> 6usize) & 0x01; - super::vals::Page25lock0noKeyState::from_bits(val as u8) - } - #[doc = "State when at least one key is registered for this page and no matching key has been entered."] - #[inline(always)] - pub fn set_no_key_state(&mut self, val: super::vals::Page25lock0noKeyState) { - self.0 = (self.0 & !(0x01 << 6usize)) | (((val.to_bits() as u32) & 0x01) << 6usize); - } - #[doc = "Redundant copy of bits 7:0"] - #[inline(always)] - pub const fn r1(&self) -> u8 { - let val = (self.0 >> 8usize) & 0xff; - val as u8 - } - #[doc = "Redundant copy of bits 7:0"] - #[inline(always)] - pub fn set_r1(&mut self, val: u8) { - self.0 = (self.0 & !(0xff << 8usize)) | (((val as u32) & 0xff) << 8usize); - } - #[doc = "Redundant copy of bits 7:0"] - #[inline(always)] - pub const fn r2(&self) -> u8 { - let val = (self.0 >> 16usize) & 0xff; - val as u8 - } - #[doc = "Redundant copy of bits 7:0"] - #[inline(always)] - pub fn set_r2(&mut self, val: u8) { - self.0 = (self.0 & !(0xff << 16usize)) | (((val as u32) & 0xff) << 16usize); - } -} -impl Default for Page25lock0 { - #[inline(always)] - fn default() -> Page25lock0 { - Page25lock0(0) - } -} -#[doc = "Lock configuration MSBs for page 25 (rows 0x640 through 0x67f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions."] -#[repr(transparent)] -#[derive(Copy, Clone, Eq, PartialEq)] -pub struct Page25lock1(pub u32); -impl Page25lock1 { - #[doc = "Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers."] - #[inline(always)] - pub const fn lock_s(&self) -> super::vals::Page25lock1lockS { - let val = (self.0 >> 0usize) & 0x03; - super::vals::Page25lock1lockS::from_bits(val as u8) - } - #[doc = "Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers."] - #[inline(always)] - pub fn set_lock_s(&mut self, val: super::vals::Page25lock1lockS) { - self.0 = (self.0 & !(0x03 << 0usize)) | (((val.to_bits() as u32) & 0x03) << 0usize); - } - #[doc = "Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API."] - #[inline(always)] - pub const fn lock_ns(&self) -> super::vals::Page25lock1lockNs { - let val = (self.0 >> 2usize) & 0x03; - super::vals::Page25lock1lockNs::from_bits(val as u8) - } - #[doc = "Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API."] - #[inline(always)] - pub fn set_lock_ns(&mut self, val: super::vals::Page25lock1lockNs) { - self.0 = (self.0 & !(0x03 << 2usize)) | (((val.to_bits() as u32) & 0x03) << 2usize); - } - #[doc = "Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers."] - #[inline(always)] - pub const fn lock_bl(&self) -> super::vals::Page25lock1lockBl { - let val = (self.0 >> 4usize) & 0x03; - super::vals::Page25lock1lockBl::from_bits(val as u8) - } - #[doc = "Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers."] - #[inline(always)] - pub fn set_lock_bl(&mut self, val: super::vals::Page25lock1lockBl) { - self.0 = (self.0 & !(0x03 << 4usize)) | (((val.to_bits() as u32) & 0x03) << 4usize); - } - #[doc = "Redundant copy of bits 7:0"] - #[inline(always)] - pub const fn r1(&self) -> u8 { - let val = (self.0 >> 8usize) & 0xff; - val as u8 - } - #[doc = "Redundant copy of bits 7:0"] - #[inline(always)] - pub fn set_r1(&mut self, val: u8) { - self.0 = (self.0 & !(0xff << 8usize)) | (((val as u32) & 0xff) << 8usize); - } - #[doc = "Redundant copy of bits 7:0"] - #[inline(always)] - pub const fn r2(&self) -> u8 { - let val = (self.0 >> 16usize) & 0xff; - val as u8 - } - #[doc = "Redundant copy of bits 7:0"] - #[inline(always)] - pub fn set_r2(&mut self, val: u8) { - self.0 = (self.0 & !(0xff << 16usize)) | (((val as u32) & 0xff) << 16usize); - } -} -impl Default for Page25lock1 { - #[inline(always)] - fn default() -> Page25lock1 { - Page25lock1(0) - } -} -#[doc = "Lock configuration LSBs for page 26 (rows 0x680 through 0x6bf). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions."] -#[repr(transparent)] -#[derive(Copy, Clone, Eq, PartialEq)] -pub struct Page26lock0(pub u32); -impl Page26lock0 { - #[doc = "Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required."] - #[inline(always)] - pub const fn key_w(&self) -> u8 { - let val = (self.0 >> 0usize) & 0x07; - val as u8 - } - #[doc = "Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required."] - #[inline(always)] - pub fn set_key_w(&mut self, val: u8) { - self.0 = (self.0 & !(0x07 << 0usize)) | (((val as u32) & 0x07) << 0usize); - } - #[doc = "Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required."] - #[inline(always)] - pub const fn key_r(&self) -> u8 { - let val = (self.0 >> 3usize) & 0x07; - val as u8 - } - #[doc = "Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required."] - #[inline(always)] - pub fn set_key_r(&mut self, val: u8) { - self.0 = (self.0 & !(0x07 << 3usize)) | (((val as u32) & 0x07) << 3usize); - } - #[doc = "State when at least one key is registered for this page and no matching key has been entered."] - #[inline(always)] - pub const fn no_key_state(&self) -> super::vals::Page26lock0noKeyState { - let val = (self.0 >> 6usize) & 0x01; - super::vals::Page26lock0noKeyState::from_bits(val as u8) - } - #[doc = "State when at least one key is registered for this page and no matching key has been entered."] - #[inline(always)] - pub fn set_no_key_state(&mut self, val: super::vals::Page26lock0noKeyState) { - self.0 = (self.0 & !(0x01 << 6usize)) | (((val.to_bits() as u32) & 0x01) << 6usize); - } - #[doc = "Redundant copy of bits 7:0"] - #[inline(always)] - pub const fn r1(&self) -> u8 { - let val = (self.0 >> 8usize) & 0xff; - val as u8 - } - #[doc = "Redundant copy of bits 7:0"] - #[inline(always)] - pub fn set_r1(&mut self, val: u8) { - self.0 = (self.0 & !(0xff << 8usize)) | (((val as u32) & 0xff) << 8usize); - } - #[doc = "Redundant copy of bits 7:0"] - #[inline(always)] - pub const fn r2(&self) -> u8 { - let val = (self.0 >> 16usize) & 0xff; - val as u8 - } - #[doc = "Redundant copy of bits 7:0"] - #[inline(always)] - pub fn set_r2(&mut self, val: u8) { - self.0 = (self.0 & !(0xff << 16usize)) | (((val as u32) & 0xff) << 16usize); - } -} -impl Default for Page26lock0 { - #[inline(always)] - fn default() -> Page26lock0 { - Page26lock0(0) - } -} -#[doc = "Lock configuration MSBs for page 26 (rows 0x680 through 0x6bf). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions."] -#[repr(transparent)] -#[derive(Copy, Clone, Eq, PartialEq)] -pub struct Page26lock1(pub u32); -impl Page26lock1 { - #[doc = "Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers."] - #[inline(always)] - pub const fn lock_s(&self) -> super::vals::Page26lock1lockS { - let val = (self.0 >> 0usize) & 0x03; - super::vals::Page26lock1lockS::from_bits(val as u8) - } - #[doc = "Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers."] - #[inline(always)] - pub fn set_lock_s(&mut self, val: super::vals::Page26lock1lockS) { - self.0 = (self.0 & !(0x03 << 0usize)) | (((val.to_bits() as u32) & 0x03) << 0usize); - } - #[doc = "Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API."] - #[inline(always)] - pub const fn lock_ns(&self) -> super::vals::Page26lock1lockNs { - let val = (self.0 >> 2usize) & 0x03; - super::vals::Page26lock1lockNs::from_bits(val as u8) - } - #[doc = "Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API."] - #[inline(always)] - pub fn set_lock_ns(&mut self, val: super::vals::Page26lock1lockNs) { - self.0 = (self.0 & !(0x03 << 2usize)) | (((val.to_bits() as u32) & 0x03) << 2usize); - } - #[doc = "Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers."] - #[inline(always)] - pub const fn lock_bl(&self) -> super::vals::Page26lock1lockBl { - let val = (self.0 >> 4usize) & 0x03; - super::vals::Page26lock1lockBl::from_bits(val as u8) - } - #[doc = "Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers."] - #[inline(always)] - pub fn set_lock_bl(&mut self, val: super::vals::Page26lock1lockBl) { - self.0 = (self.0 & !(0x03 << 4usize)) | (((val.to_bits() as u32) & 0x03) << 4usize); - } - #[doc = "Redundant copy of bits 7:0"] - #[inline(always)] - pub const fn r1(&self) -> u8 { - let val = (self.0 >> 8usize) & 0xff; - val as u8 - } - #[doc = "Redundant copy of bits 7:0"] - #[inline(always)] - pub fn set_r1(&mut self, val: u8) { - self.0 = (self.0 & !(0xff << 8usize)) | (((val as u32) & 0xff) << 8usize); - } - #[doc = "Redundant copy of bits 7:0"] - #[inline(always)] - pub const fn r2(&self) -> u8 { - let val = (self.0 >> 16usize) & 0xff; - val as u8 - } - #[doc = "Redundant copy of bits 7:0"] - #[inline(always)] - pub fn set_r2(&mut self, val: u8) { - self.0 = (self.0 & !(0xff << 16usize)) | (((val as u32) & 0xff) << 16usize); - } -} -impl Default for Page26lock1 { - #[inline(always)] - fn default() -> Page26lock1 { - Page26lock1(0) - } -} -#[doc = "Lock configuration LSBs for page 27 (rows 0x6c0 through 0x6ff). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions."] -#[repr(transparent)] -#[derive(Copy, Clone, Eq, PartialEq)] -pub struct Page27lock0(pub u32); -impl Page27lock0 { - #[doc = "Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required."] - #[inline(always)] - pub const fn key_w(&self) -> u8 { - let val = (self.0 >> 0usize) & 0x07; - val as u8 - } - #[doc = "Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required."] - #[inline(always)] - pub fn set_key_w(&mut self, val: u8) { - self.0 = (self.0 & !(0x07 << 0usize)) | (((val as u32) & 0x07) << 0usize); - } - #[doc = "Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required."] - #[inline(always)] - pub const fn key_r(&self) -> u8 { - let val = (self.0 >> 3usize) & 0x07; - val as u8 - } - #[doc = "Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required."] - #[inline(always)] - pub fn set_key_r(&mut self, val: u8) { - self.0 = (self.0 & !(0x07 << 3usize)) | (((val as u32) & 0x07) << 3usize); - } - #[doc = "State when at least one key is registered for this page and no matching key has been entered."] - #[inline(always)] - pub const fn no_key_state(&self) -> super::vals::Page27lock0noKeyState { - let val = (self.0 >> 6usize) & 0x01; - super::vals::Page27lock0noKeyState::from_bits(val as u8) - } - #[doc = "State when at least one key is registered for this page and no matching key has been entered."] - #[inline(always)] - pub fn set_no_key_state(&mut self, val: super::vals::Page27lock0noKeyState) { - self.0 = (self.0 & !(0x01 << 6usize)) | (((val.to_bits() as u32) & 0x01) << 6usize); - } - #[doc = "Redundant copy of bits 7:0"] - #[inline(always)] - pub const fn r1(&self) -> u8 { - let val = (self.0 >> 8usize) & 0xff; - val as u8 - } - #[doc = "Redundant copy of bits 7:0"] - #[inline(always)] - pub fn set_r1(&mut self, val: u8) { - self.0 = (self.0 & !(0xff << 8usize)) | (((val as u32) & 0xff) << 8usize); - } - #[doc = "Redundant copy of bits 7:0"] - #[inline(always)] - pub const fn r2(&self) -> u8 { - let val = (self.0 >> 16usize) & 0xff; - val as u8 - } - #[doc = "Redundant copy of bits 7:0"] - #[inline(always)] - pub fn set_r2(&mut self, val: u8) { - self.0 = (self.0 & !(0xff << 16usize)) | (((val as u32) & 0xff) << 16usize); - } -} -impl Default for Page27lock0 { - #[inline(always)] - fn default() -> Page27lock0 { - Page27lock0(0) - } -} -#[doc = "Lock configuration MSBs for page 27 (rows 0x6c0 through 0x6ff). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions."] -#[repr(transparent)] -#[derive(Copy, Clone, Eq, PartialEq)] -pub struct Page27lock1(pub u32); -impl Page27lock1 { - #[doc = "Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers."] - #[inline(always)] - pub const fn lock_s(&self) -> super::vals::Page27lock1lockS { - let val = (self.0 >> 0usize) & 0x03; - super::vals::Page27lock1lockS::from_bits(val as u8) - } - #[doc = "Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers."] - #[inline(always)] - pub fn set_lock_s(&mut self, val: super::vals::Page27lock1lockS) { - self.0 = (self.0 & !(0x03 << 0usize)) | (((val.to_bits() as u32) & 0x03) << 0usize); - } - #[doc = "Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API."] - #[inline(always)] - pub const fn lock_ns(&self) -> super::vals::Page27lock1lockNs { - let val = (self.0 >> 2usize) & 0x03; - super::vals::Page27lock1lockNs::from_bits(val as u8) - } - #[doc = "Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API."] - #[inline(always)] - pub fn set_lock_ns(&mut self, val: super::vals::Page27lock1lockNs) { - self.0 = (self.0 & !(0x03 << 2usize)) | (((val.to_bits() as u32) & 0x03) << 2usize); - } - #[doc = "Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers."] - #[inline(always)] - pub const fn lock_bl(&self) -> super::vals::Page27lock1lockBl { - let val = (self.0 >> 4usize) & 0x03; - super::vals::Page27lock1lockBl::from_bits(val as u8) - } - #[doc = "Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers."] - #[inline(always)] - pub fn set_lock_bl(&mut self, val: super::vals::Page27lock1lockBl) { - self.0 = (self.0 & !(0x03 << 4usize)) | (((val.to_bits() as u32) & 0x03) << 4usize); - } - #[doc = "Redundant copy of bits 7:0"] - #[inline(always)] - pub const fn r1(&self) -> u8 { - let val = (self.0 >> 8usize) & 0xff; - val as u8 - } - #[doc = "Redundant copy of bits 7:0"] - #[inline(always)] - pub fn set_r1(&mut self, val: u8) { - self.0 = (self.0 & !(0xff << 8usize)) | (((val as u32) & 0xff) << 8usize); - } - #[doc = "Redundant copy of bits 7:0"] - #[inline(always)] - pub const fn r2(&self) -> u8 { - let val = (self.0 >> 16usize) & 0xff; - val as u8 - } - #[doc = "Redundant copy of bits 7:0"] - #[inline(always)] - pub fn set_r2(&mut self, val: u8) { - self.0 = (self.0 & !(0xff << 16usize)) | (((val as u32) & 0xff) << 16usize); - } -} -impl Default for Page27lock1 { - #[inline(always)] - fn default() -> Page27lock1 { - Page27lock1(0) - } -} -#[doc = "Lock configuration LSBs for page 28 (rows 0x700 through 0x73f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions."] -#[repr(transparent)] -#[derive(Copy, Clone, Eq, PartialEq)] -pub struct Page28lock0(pub u32); -impl Page28lock0 { - #[doc = "Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required."] - #[inline(always)] - pub const fn key_w(&self) -> u8 { - let val = (self.0 >> 0usize) & 0x07; - val as u8 - } - #[doc = "Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required."] - #[inline(always)] - pub fn set_key_w(&mut self, val: u8) { - self.0 = (self.0 & !(0x07 << 0usize)) | (((val as u32) & 0x07) << 0usize); - } - #[doc = "Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required."] - #[inline(always)] - pub const fn key_r(&self) -> u8 { - let val = (self.0 >> 3usize) & 0x07; - val as u8 - } - #[doc = "Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required."] - #[inline(always)] - pub fn set_key_r(&mut self, val: u8) { - self.0 = (self.0 & !(0x07 << 3usize)) | (((val as u32) & 0x07) << 3usize); - } - #[doc = "State when at least one key is registered for this page and no matching key has been entered."] - #[inline(always)] - pub const fn no_key_state(&self) -> super::vals::Page28lock0noKeyState { - let val = (self.0 >> 6usize) & 0x01; - super::vals::Page28lock0noKeyState::from_bits(val as u8) - } - #[doc = "State when at least one key is registered for this page and no matching key has been entered."] - #[inline(always)] - pub fn set_no_key_state(&mut self, val: super::vals::Page28lock0noKeyState) { - self.0 = (self.0 & !(0x01 << 6usize)) | (((val.to_bits() as u32) & 0x01) << 6usize); - } - #[doc = "Redundant copy of bits 7:0"] - #[inline(always)] - pub const fn r1(&self) -> u8 { - let val = (self.0 >> 8usize) & 0xff; - val as u8 - } - #[doc = "Redundant copy of bits 7:0"] - #[inline(always)] - pub fn set_r1(&mut self, val: u8) { - self.0 = (self.0 & !(0xff << 8usize)) | (((val as u32) & 0xff) << 8usize); - } - #[doc = "Redundant copy of bits 7:0"] - #[inline(always)] - pub const fn r2(&self) -> u8 { - let val = (self.0 >> 16usize) & 0xff; - val as u8 - } - #[doc = "Redundant copy of bits 7:0"] - #[inline(always)] - pub fn set_r2(&mut self, val: u8) { - self.0 = (self.0 & !(0xff << 16usize)) | (((val as u32) & 0xff) << 16usize); - } -} -impl Default for Page28lock0 { - #[inline(always)] - fn default() -> Page28lock0 { - Page28lock0(0) - } -} -#[doc = "Lock configuration MSBs for page 28 (rows 0x700 through 0x73f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions."] -#[repr(transparent)] -#[derive(Copy, Clone, Eq, PartialEq)] -pub struct Page28lock1(pub u32); -impl Page28lock1 { - #[doc = "Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers."] - #[inline(always)] - pub const fn lock_s(&self) -> super::vals::Page28lock1lockS { - let val = (self.0 >> 0usize) & 0x03; - super::vals::Page28lock1lockS::from_bits(val as u8) - } - #[doc = "Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers."] - #[inline(always)] - pub fn set_lock_s(&mut self, val: super::vals::Page28lock1lockS) { - self.0 = (self.0 & !(0x03 << 0usize)) | (((val.to_bits() as u32) & 0x03) << 0usize); - } - #[doc = "Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API."] - #[inline(always)] - pub const fn lock_ns(&self) -> super::vals::Page28lock1lockNs { - let val = (self.0 >> 2usize) & 0x03; - super::vals::Page28lock1lockNs::from_bits(val as u8) - } - #[doc = "Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API."] - #[inline(always)] - pub fn set_lock_ns(&mut self, val: super::vals::Page28lock1lockNs) { - self.0 = (self.0 & !(0x03 << 2usize)) | (((val.to_bits() as u32) & 0x03) << 2usize); - } - #[doc = "Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers."] - #[inline(always)] - pub const fn lock_bl(&self) -> super::vals::Page28lock1lockBl { - let val = (self.0 >> 4usize) & 0x03; - super::vals::Page28lock1lockBl::from_bits(val as u8) - } - #[doc = "Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers."] - #[inline(always)] - pub fn set_lock_bl(&mut self, val: super::vals::Page28lock1lockBl) { - self.0 = (self.0 & !(0x03 << 4usize)) | (((val.to_bits() as u32) & 0x03) << 4usize); - } - #[doc = "Redundant copy of bits 7:0"] - #[inline(always)] - pub const fn r1(&self) -> u8 { - let val = (self.0 >> 8usize) & 0xff; - val as u8 - } - #[doc = "Redundant copy of bits 7:0"] - #[inline(always)] - pub fn set_r1(&mut self, val: u8) { - self.0 = (self.0 & !(0xff << 8usize)) | (((val as u32) & 0xff) << 8usize); - } - #[doc = "Redundant copy of bits 7:0"] - #[inline(always)] - pub const fn r2(&self) -> u8 { - let val = (self.0 >> 16usize) & 0xff; - val as u8 - } - #[doc = "Redundant copy of bits 7:0"] - #[inline(always)] - pub fn set_r2(&mut self, val: u8) { - self.0 = (self.0 & !(0xff << 16usize)) | (((val as u32) & 0xff) << 16usize); - } -} -impl Default for Page28lock1 { - #[inline(always)] - fn default() -> Page28lock1 { - Page28lock1(0) - } -} -#[doc = "Lock configuration LSBs for page 29 (rows 0x740 through 0x77f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions."] -#[repr(transparent)] -#[derive(Copy, Clone, Eq, PartialEq)] -pub struct Page29lock0(pub u32); -impl Page29lock0 { - #[doc = "Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required."] - #[inline(always)] - pub const fn key_w(&self) -> u8 { - let val = (self.0 >> 0usize) & 0x07; - val as u8 - } - #[doc = "Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required."] - #[inline(always)] - pub fn set_key_w(&mut self, val: u8) { - self.0 = (self.0 & !(0x07 << 0usize)) | (((val as u32) & 0x07) << 0usize); - } - #[doc = "Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required."] - #[inline(always)] - pub const fn key_r(&self) -> u8 { - let val = (self.0 >> 3usize) & 0x07; - val as u8 - } - #[doc = "Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required."] - #[inline(always)] - pub fn set_key_r(&mut self, val: u8) { - self.0 = (self.0 & !(0x07 << 3usize)) | (((val as u32) & 0x07) << 3usize); - } - #[doc = "State when at least one key is registered for this page and no matching key has been entered."] - #[inline(always)] - pub const fn no_key_state(&self) -> super::vals::Page29lock0noKeyState { - let val = (self.0 >> 6usize) & 0x01; - super::vals::Page29lock0noKeyState::from_bits(val as u8) - } - #[doc = "State when at least one key is registered for this page and no matching key has been entered."] - #[inline(always)] - pub fn set_no_key_state(&mut self, val: super::vals::Page29lock0noKeyState) { - self.0 = (self.0 & !(0x01 << 6usize)) | (((val.to_bits() as u32) & 0x01) << 6usize); - } - #[doc = "Redundant copy of bits 7:0"] - #[inline(always)] - pub const fn r1(&self) -> u8 { - let val = (self.0 >> 8usize) & 0xff; - val as u8 - } - #[doc = "Redundant copy of bits 7:0"] - #[inline(always)] - pub fn set_r1(&mut self, val: u8) { - self.0 = (self.0 & !(0xff << 8usize)) | (((val as u32) & 0xff) << 8usize); - } - #[doc = "Redundant copy of bits 7:0"] - #[inline(always)] - pub const fn r2(&self) -> u8 { - let val = (self.0 >> 16usize) & 0xff; - val as u8 - } - #[doc = "Redundant copy of bits 7:0"] - #[inline(always)] - pub fn set_r2(&mut self, val: u8) { - self.0 = (self.0 & !(0xff << 16usize)) | (((val as u32) & 0xff) << 16usize); - } -} -impl Default for Page29lock0 { - #[inline(always)] - fn default() -> Page29lock0 { - Page29lock0(0) - } -} -#[doc = "Lock configuration MSBs for page 29 (rows 0x740 through 0x77f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions."] -#[repr(transparent)] -#[derive(Copy, Clone, Eq, PartialEq)] -pub struct Page29lock1(pub u32); -impl Page29lock1 { - #[doc = "Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers."] - #[inline(always)] - pub const fn lock_s(&self) -> super::vals::Page29lock1lockS { - let val = (self.0 >> 0usize) & 0x03; - super::vals::Page29lock1lockS::from_bits(val as u8) - } - #[doc = "Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers."] - #[inline(always)] - pub fn set_lock_s(&mut self, val: super::vals::Page29lock1lockS) { - self.0 = (self.0 & !(0x03 << 0usize)) | (((val.to_bits() as u32) & 0x03) << 0usize); - } - #[doc = "Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API."] - #[inline(always)] - pub const fn lock_ns(&self) -> super::vals::Page29lock1lockNs { - let val = (self.0 >> 2usize) & 0x03; - super::vals::Page29lock1lockNs::from_bits(val as u8) - } - #[doc = "Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API."] - #[inline(always)] - pub fn set_lock_ns(&mut self, val: super::vals::Page29lock1lockNs) { - self.0 = (self.0 & !(0x03 << 2usize)) | (((val.to_bits() as u32) & 0x03) << 2usize); - } - #[doc = "Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers."] - #[inline(always)] - pub const fn lock_bl(&self) -> super::vals::Page29lock1lockBl { - let val = (self.0 >> 4usize) & 0x03; - super::vals::Page29lock1lockBl::from_bits(val as u8) - } - #[doc = "Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers."] - #[inline(always)] - pub fn set_lock_bl(&mut self, val: super::vals::Page29lock1lockBl) { - self.0 = (self.0 & !(0x03 << 4usize)) | (((val.to_bits() as u32) & 0x03) << 4usize); - } - #[doc = "Redundant copy of bits 7:0"] - #[inline(always)] - pub const fn r1(&self) -> u8 { - let val = (self.0 >> 8usize) & 0xff; - val as u8 - } - #[doc = "Redundant copy of bits 7:0"] - #[inline(always)] - pub fn set_r1(&mut self, val: u8) { - self.0 = (self.0 & !(0xff << 8usize)) | (((val as u32) & 0xff) << 8usize); - } - #[doc = "Redundant copy of bits 7:0"] - #[inline(always)] - pub const fn r2(&self) -> u8 { - let val = (self.0 >> 16usize) & 0xff; - val as u8 - } - #[doc = "Redundant copy of bits 7:0"] - #[inline(always)] - pub fn set_r2(&mut self, val: u8) { - self.0 = (self.0 & !(0xff << 16usize)) | (((val as u32) & 0xff) << 16usize); - } -} -impl Default for Page29lock1 { - #[inline(always)] - fn default() -> Page29lock1 { - Page29lock1(0) - } -} -#[doc = "Lock configuration LSBs for page 2 (rows 0x80 through 0xbf). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions."] -#[repr(transparent)] -#[derive(Copy, Clone, Eq, PartialEq)] -pub struct Page2lock0(pub u32); -impl Page2lock0 { - #[doc = "Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required."] - #[inline(always)] - pub const fn key_w(&self) -> u8 { - let val = (self.0 >> 0usize) & 0x07; - val as u8 - } - #[doc = "Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required."] - #[inline(always)] - pub fn set_key_w(&mut self, val: u8) { - self.0 = (self.0 & !(0x07 << 0usize)) | (((val as u32) & 0x07) << 0usize); - } - #[doc = "Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required."] - #[inline(always)] - pub const fn key_r(&self) -> u8 { - let val = (self.0 >> 3usize) & 0x07; - val as u8 - } - #[doc = "Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required."] - #[inline(always)] - pub fn set_key_r(&mut self, val: u8) { - self.0 = (self.0 & !(0x07 << 3usize)) | (((val as u32) & 0x07) << 3usize); - } - #[doc = "State when at least one key is registered for this page and no matching key has been entered."] - #[inline(always)] - pub const fn no_key_state(&self) -> super::vals::Page2lock0noKeyState { - let val = (self.0 >> 6usize) & 0x01; - super::vals::Page2lock0noKeyState::from_bits(val as u8) - } - #[doc = "State when at least one key is registered for this page and no matching key has been entered."] - #[inline(always)] - pub fn set_no_key_state(&mut self, val: super::vals::Page2lock0noKeyState) { - self.0 = (self.0 & !(0x01 << 6usize)) | (((val.to_bits() as u32) & 0x01) << 6usize); - } - #[doc = "Redundant copy of bits 7:0"] - #[inline(always)] - pub const fn r1(&self) -> u8 { - let val = (self.0 >> 8usize) & 0xff; - val as u8 - } - #[doc = "Redundant copy of bits 7:0"] - #[inline(always)] - pub fn set_r1(&mut self, val: u8) { - self.0 = (self.0 & !(0xff << 8usize)) | (((val as u32) & 0xff) << 8usize); - } - #[doc = "Redundant copy of bits 7:0"] - #[inline(always)] - pub const fn r2(&self) -> u8 { - let val = (self.0 >> 16usize) & 0xff; - val as u8 - } - #[doc = "Redundant copy of bits 7:0"] - #[inline(always)] - pub fn set_r2(&mut self, val: u8) { - self.0 = (self.0 & !(0xff << 16usize)) | (((val as u32) & 0xff) << 16usize); - } -} -impl Default for Page2lock0 { - #[inline(always)] - fn default() -> Page2lock0 { - Page2lock0(0) - } -} -#[doc = "Lock configuration MSBs for page 2 (rows 0x80 through 0xbf). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions."] -#[repr(transparent)] -#[derive(Copy, Clone, Eq, PartialEq)] -pub struct Page2lock1(pub u32); -impl Page2lock1 { - #[doc = "Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers."] - #[inline(always)] - pub const fn lock_s(&self) -> super::vals::Page2lock1lockS { - let val = (self.0 >> 0usize) & 0x03; - super::vals::Page2lock1lockS::from_bits(val as u8) - } - #[doc = "Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers."] - #[inline(always)] - pub fn set_lock_s(&mut self, val: super::vals::Page2lock1lockS) { - self.0 = (self.0 & !(0x03 << 0usize)) | (((val.to_bits() as u32) & 0x03) << 0usize); - } - #[doc = "Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API."] - #[inline(always)] - pub const fn lock_ns(&self) -> super::vals::Page2lock1lockNs { - let val = (self.0 >> 2usize) & 0x03; - super::vals::Page2lock1lockNs::from_bits(val as u8) - } - #[doc = "Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API."] - #[inline(always)] - pub fn set_lock_ns(&mut self, val: super::vals::Page2lock1lockNs) { - self.0 = (self.0 & !(0x03 << 2usize)) | (((val.to_bits() as u32) & 0x03) << 2usize); - } - #[doc = "Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers."] - #[inline(always)] - pub const fn lock_bl(&self) -> super::vals::Page2lock1lockBl { - let val = (self.0 >> 4usize) & 0x03; - super::vals::Page2lock1lockBl::from_bits(val as u8) - } - #[doc = "Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers."] - #[inline(always)] - pub fn set_lock_bl(&mut self, val: super::vals::Page2lock1lockBl) { - self.0 = (self.0 & !(0x03 << 4usize)) | (((val.to_bits() as u32) & 0x03) << 4usize); - } - #[doc = "Redundant copy of bits 7:0"] - #[inline(always)] - pub const fn r1(&self) -> u8 { - let val = (self.0 >> 8usize) & 0xff; - val as u8 - } - #[doc = "Redundant copy of bits 7:0"] - #[inline(always)] - pub fn set_r1(&mut self, val: u8) { - self.0 = (self.0 & !(0xff << 8usize)) | (((val as u32) & 0xff) << 8usize); - } - #[doc = "Redundant copy of bits 7:0"] - #[inline(always)] - pub const fn r2(&self) -> u8 { - let val = (self.0 >> 16usize) & 0xff; - val as u8 - } - #[doc = "Redundant copy of bits 7:0"] - #[inline(always)] - pub fn set_r2(&mut self, val: u8) { - self.0 = (self.0 & !(0xff << 16usize)) | (((val as u32) & 0xff) << 16usize); - } -} -impl Default for Page2lock1 { - #[inline(always)] - fn default() -> Page2lock1 { - Page2lock1(0) - } -} -#[doc = "Lock configuration LSBs for page 30 (rows 0x780 through 0x7bf). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions."] -#[repr(transparent)] -#[derive(Copy, Clone, Eq, PartialEq)] -pub struct Page30lock0(pub u32); -impl Page30lock0 { - #[doc = "Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required."] - #[inline(always)] - pub const fn key_w(&self) -> u8 { - let val = (self.0 >> 0usize) & 0x07; - val as u8 - } - #[doc = "Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required."] - #[inline(always)] - pub fn set_key_w(&mut self, val: u8) { - self.0 = (self.0 & !(0x07 << 0usize)) | (((val as u32) & 0x07) << 0usize); - } - #[doc = "Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required."] - #[inline(always)] - pub const fn key_r(&self) -> u8 { - let val = (self.0 >> 3usize) & 0x07; - val as u8 - } - #[doc = "Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required."] - #[inline(always)] - pub fn set_key_r(&mut self, val: u8) { - self.0 = (self.0 & !(0x07 << 3usize)) | (((val as u32) & 0x07) << 3usize); - } - #[doc = "State when at least one key is registered for this page and no matching key has been entered."] - #[inline(always)] - pub const fn no_key_state(&self) -> super::vals::Page30lock0noKeyState { - let val = (self.0 >> 6usize) & 0x01; - super::vals::Page30lock0noKeyState::from_bits(val as u8) - } - #[doc = "State when at least one key is registered for this page and no matching key has been entered."] - #[inline(always)] - pub fn set_no_key_state(&mut self, val: super::vals::Page30lock0noKeyState) { - self.0 = (self.0 & !(0x01 << 6usize)) | (((val.to_bits() as u32) & 0x01) << 6usize); - } - #[doc = "Redundant copy of bits 7:0"] - #[inline(always)] - pub const fn r1(&self) -> u8 { - let val = (self.0 >> 8usize) & 0xff; - val as u8 - } - #[doc = "Redundant copy of bits 7:0"] - #[inline(always)] - pub fn set_r1(&mut self, val: u8) { - self.0 = (self.0 & !(0xff << 8usize)) | (((val as u32) & 0xff) << 8usize); - } - #[doc = "Redundant copy of bits 7:0"] - #[inline(always)] - pub const fn r2(&self) -> u8 { - let val = (self.0 >> 16usize) & 0xff; - val as u8 - } - #[doc = "Redundant copy of bits 7:0"] - #[inline(always)] - pub fn set_r2(&mut self, val: u8) { - self.0 = (self.0 & !(0xff << 16usize)) | (((val as u32) & 0xff) << 16usize); - } -} -impl Default for Page30lock0 { - #[inline(always)] - fn default() -> Page30lock0 { - Page30lock0(0) - } -} -#[doc = "Lock configuration MSBs for page 30 (rows 0x780 through 0x7bf). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions."] -#[repr(transparent)] -#[derive(Copy, Clone, Eq, PartialEq)] -pub struct Page30lock1(pub u32); -impl Page30lock1 { - #[doc = "Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers."] - #[inline(always)] - pub const fn lock_s(&self) -> super::vals::Page30lock1lockS { - let val = (self.0 >> 0usize) & 0x03; - super::vals::Page30lock1lockS::from_bits(val as u8) - } - #[doc = "Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers."] - #[inline(always)] - pub fn set_lock_s(&mut self, val: super::vals::Page30lock1lockS) { - self.0 = (self.0 & !(0x03 << 0usize)) | (((val.to_bits() as u32) & 0x03) << 0usize); - } - #[doc = "Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API."] - #[inline(always)] - pub const fn lock_ns(&self) -> super::vals::Page30lock1lockNs { - let val = (self.0 >> 2usize) & 0x03; - super::vals::Page30lock1lockNs::from_bits(val as u8) - } - #[doc = "Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API."] - #[inline(always)] - pub fn set_lock_ns(&mut self, val: super::vals::Page30lock1lockNs) { - self.0 = (self.0 & !(0x03 << 2usize)) | (((val.to_bits() as u32) & 0x03) << 2usize); - } - #[doc = "Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers."] - #[inline(always)] - pub const fn lock_bl(&self) -> super::vals::Page30lock1lockBl { - let val = (self.0 >> 4usize) & 0x03; - super::vals::Page30lock1lockBl::from_bits(val as u8) - } - #[doc = "Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers."] - #[inline(always)] - pub fn set_lock_bl(&mut self, val: super::vals::Page30lock1lockBl) { - self.0 = (self.0 & !(0x03 << 4usize)) | (((val.to_bits() as u32) & 0x03) << 4usize); - } - #[doc = "Redundant copy of bits 7:0"] - #[inline(always)] - pub const fn r1(&self) -> u8 { - let val = (self.0 >> 8usize) & 0xff; - val as u8 - } - #[doc = "Redundant copy of bits 7:0"] - #[inline(always)] - pub fn set_r1(&mut self, val: u8) { - self.0 = (self.0 & !(0xff << 8usize)) | (((val as u32) & 0xff) << 8usize); - } - #[doc = "Redundant copy of bits 7:0"] - #[inline(always)] - pub const fn r2(&self) -> u8 { - let val = (self.0 >> 16usize) & 0xff; - val as u8 - } - #[doc = "Redundant copy of bits 7:0"] - #[inline(always)] - pub fn set_r2(&mut self, val: u8) { - self.0 = (self.0 & !(0xff << 16usize)) | (((val as u32) & 0xff) << 16usize); - } -} -impl Default for Page30lock1 { - #[inline(always)] - fn default() -> Page30lock1 { - Page30lock1(0) - } -} -#[doc = "Lock configuration LSBs for page 31 (rows 0x7c0 through 0x7ff). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions."] -#[repr(transparent)] -#[derive(Copy, Clone, Eq, PartialEq)] -pub struct Page31lock0(pub u32); -impl Page31lock0 { - #[doc = "Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required."] - #[inline(always)] - pub const fn key_w(&self) -> u8 { - let val = (self.0 >> 0usize) & 0x07; - val as u8 - } - #[doc = "Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required."] - #[inline(always)] - pub fn set_key_w(&mut self, val: u8) { - self.0 = (self.0 & !(0x07 << 0usize)) | (((val as u32) & 0x07) << 0usize); - } - #[doc = "Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required."] - #[inline(always)] - pub const fn key_r(&self) -> u8 { - let val = (self.0 >> 3usize) & 0x07; - val as u8 - } - #[doc = "Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required."] - #[inline(always)] - pub fn set_key_r(&mut self, val: u8) { - self.0 = (self.0 & !(0x07 << 3usize)) | (((val as u32) & 0x07) << 3usize); - } - #[doc = "State when at least one key is registered for this page and no matching key has been entered."] - #[inline(always)] - pub const fn no_key_state(&self) -> super::vals::Page31lock0noKeyState { - let val = (self.0 >> 6usize) & 0x01; - super::vals::Page31lock0noKeyState::from_bits(val as u8) - } - #[doc = "State when at least one key is registered for this page and no matching key has been entered."] - #[inline(always)] - pub fn set_no_key_state(&mut self, val: super::vals::Page31lock0noKeyState) { - self.0 = (self.0 & !(0x01 << 6usize)) | (((val.to_bits() as u32) & 0x01) << 6usize); - } - #[doc = "Redundant copy of bits 7:0"] - #[inline(always)] - pub const fn r1(&self) -> u8 { - let val = (self.0 >> 8usize) & 0xff; - val as u8 - } - #[doc = "Redundant copy of bits 7:0"] - #[inline(always)] - pub fn set_r1(&mut self, val: u8) { - self.0 = (self.0 & !(0xff << 8usize)) | (((val as u32) & 0xff) << 8usize); - } - #[doc = "Redundant copy of bits 7:0"] - #[inline(always)] - pub const fn r2(&self) -> u8 { - let val = (self.0 >> 16usize) & 0xff; - val as u8 - } - #[doc = "Redundant copy of bits 7:0"] - #[inline(always)] - pub fn set_r2(&mut self, val: u8) { - self.0 = (self.0 & !(0xff << 16usize)) | (((val as u32) & 0xff) << 16usize); - } -} -impl Default for Page31lock0 { - #[inline(always)] - fn default() -> Page31lock0 { - Page31lock0(0) - } -} -#[doc = "Lock configuration MSBs for page 31 (rows 0x7c0 through 0x7ff). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions."] -#[repr(transparent)] -#[derive(Copy, Clone, Eq, PartialEq)] -pub struct Page31lock1(pub u32); -impl Page31lock1 { - #[doc = "Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers."] - #[inline(always)] - pub const fn lock_s(&self) -> super::vals::Page31lock1lockS { - let val = (self.0 >> 0usize) & 0x03; - super::vals::Page31lock1lockS::from_bits(val as u8) - } - #[doc = "Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers."] - #[inline(always)] - pub fn set_lock_s(&mut self, val: super::vals::Page31lock1lockS) { - self.0 = (self.0 & !(0x03 << 0usize)) | (((val.to_bits() as u32) & 0x03) << 0usize); - } - #[doc = "Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API."] - #[inline(always)] - pub const fn lock_ns(&self) -> super::vals::Page31lock1lockNs { - let val = (self.0 >> 2usize) & 0x03; - super::vals::Page31lock1lockNs::from_bits(val as u8) - } - #[doc = "Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API."] - #[inline(always)] - pub fn set_lock_ns(&mut self, val: super::vals::Page31lock1lockNs) { - self.0 = (self.0 & !(0x03 << 2usize)) | (((val.to_bits() as u32) & 0x03) << 2usize); - } - #[doc = "Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers."] - #[inline(always)] - pub const fn lock_bl(&self) -> super::vals::Page31lock1lockBl { - let val = (self.0 >> 4usize) & 0x03; - super::vals::Page31lock1lockBl::from_bits(val as u8) - } - #[doc = "Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers."] - #[inline(always)] - pub fn set_lock_bl(&mut self, val: super::vals::Page31lock1lockBl) { - self.0 = (self.0 & !(0x03 << 4usize)) | (((val.to_bits() as u32) & 0x03) << 4usize); - } - #[doc = "Redundant copy of bits 7:0"] - #[inline(always)] - pub const fn r1(&self) -> u8 { - let val = (self.0 >> 8usize) & 0xff; - val as u8 - } - #[doc = "Redundant copy of bits 7:0"] - #[inline(always)] - pub fn set_r1(&mut self, val: u8) { - self.0 = (self.0 & !(0xff << 8usize)) | (((val as u32) & 0xff) << 8usize); - } - #[doc = "Redundant copy of bits 7:0"] - #[inline(always)] - pub const fn r2(&self) -> u8 { - let val = (self.0 >> 16usize) & 0xff; - val as u8 - } - #[doc = "Redundant copy of bits 7:0"] - #[inline(always)] - pub fn set_r2(&mut self, val: u8) { - self.0 = (self.0 & !(0xff << 16usize)) | (((val as u32) & 0xff) << 16usize); - } -} -impl Default for Page31lock1 { - #[inline(always)] - fn default() -> Page31lock1 { - Page31lock1(0) - } -} -#[doc = "Lock configuration LSBs for page 32 (rows 0x800 through 0x83f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions."] -#[repr(transparent)] -#[derive(Copy, Clone, Eq, PartialEq)] -pub struct Page32lock0(pub u32); -impl Page32lock0 { - #[doc = "Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required."] - #[inline(always)] - pub const fn key_w(&self) -> u8 { - let val = (self.0 >> 0usize) & 0x07; - val as u8 - } - #[doc = "Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required."] - #[inline(always)] - pub fn set_key_w(&mut self, val: u8) { - self.0 = (self.0 & !(0x07 << 0usize)) | (((val as u32) & 0x07) << 0usize); - } - #[doc = "Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required."] - #[inline(always)] - pub const fn key_r(&self) -> u8 { - let val = (self.0 >> 3usize) & 0x07; - val as u8 - } - #[doc = "Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required."] - #[inline(always)] - pub fn set_key_r(&mut self, val: u8) { - self.0 = (self.0 & !(0x07 << 3usize)) | (((val as u32) & 0x07) << 3usize); - } - #[doc = "State when at least one key is registered for this page and no matching key has been entered."] - #[inline(always)] - pub const fn no_key_state(&self) -> super::vals::Page32lock0noKeyState { - let val = (self.0 >> 6usize) & 0x01; - super::vals::Page32lock0noKeyState::from_bits(val as u8) - } - #[doc = "State when at least one key is registered for this page and no matching key has been entered."] - #[inline(always)] - pub fn set_no_key_state(&mut self, val: super::vals::Page32lock0noKeyState) { - self.0 = (self.0 & !(0x01 << 6usize)) | (((val.to_bits() as u32) & 0x01) << 6usize); - } - #[doc = "Redundant copy of bits 7:0"] - #[inline(always)] - pub const fn r1(&self) -> u8 { - let val = (self.0 >> 8usize) & 0xff; - val as u8 - } - #[doc = "Redundant copy of bits 7:0"] - #[inline(always)] - pub fn set_r1(&mut self, val: u8) { - self.0 = (self.0 & !(0xff << 8usize)) | (((val as u32) & 0xff) << 8usize); - } - #[doc = "Redundant copy of bits 7:0"] - #[inline(always)] - pub const fn r2(&self) -> u8 { - let val = (self.0 >> 16usize) & 0xff; - val as u8 - } - #[doc = "Redundant copy of bits 7:0"] - #[inline(always)] - pub fn set_r2(&mut self, val: u8) { - self.0 = (self.0 & !(0xff << 16usize)) | (((val as u32) & 0xff) << 16usize); - } -} -impl Default for Page32lock0 { - #[inline(always)] - fn default() -> Page32lock0 { - Page32lock0(0) - } -} -#[doc = "Lock configuration MSBs for page 32 (rows 0x800 through 0x83f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions."] -#[repr(transparent)] -#[derive(Copy, Clone, Eq, PartialEq)] -pub struct Page32lock1(pub u32); -impl Page32lock1 { - #[doc = "Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers."] - #[inline(always)] - pub const fn lock_s(&self) -> super::vals::Page32lock1lockS { - let val = (self.0 >> 0usize) & 0x03; - super::vals::Page32lock1lockS::from_bits(val as u8) - } - #[doc = "Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers."] - #[inline(always)] - pub fn set_lock_s(&mut self, val: super::vals::Page32lock1lockS) { - self.0 = (self.0 & !(0x03 << 0usize)) | (((val.to_bits() as u32) & 0x03) << 0usize); - } - #[doc = "Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API."] - #[inline(always)] - pub const fn lock_ns(&self) -> super::vals::Page32lock1lockNs { - let val = (self.0 >> 2usize) & 0x03; - super::vals::Page32lock1lockNs::from_bits(val as u8) - } - #[doc = "Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API."] - #[inline(always)] - pub fn set_lock_ns(&mut self, val: super::vals::Page32lock1lockNs) { - self.0 = (self.0 & !(0x03 << 2usize)) | (((val.to_bits() as u32) & 0x03) << 2usize); - } - #[doc = "Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers."] - #[inline(always)] - pub const fn lock_bl(&self) -> super::vals::Page32lock1lockBl { - let val = (self.0 >> 4usize) & 0x03; - super::vals::Page32lock1lockBl::from_bits(val as u8) - } - #[doc = "Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers."] - #[inline(always)] - pub fn set_lock_bl(&mut self, val: super::vals::Page32lock1lockBl) { - self.0 = (self.0 & !(0x03 << 4usize)) | (((val.to_bits() as u32) & 0x03) << 4usize); - } - #[doc = "Redundant copy of bits 7:0"] - #[inline(always)] - pub const fn r1(&self) -> u8 { - let val = (self.0 >> 8usize) & 0xff; - val as u8 - } - #[doc = "Redundant copy of bits 7:0"] - #[inline(always)] - pub fn set_r1(&mut self, val: u8) { - self.0 = (self.0 & !(0xff << 8usize)) | (((val as u32) & 0xff) << 8usize); - } - #[doc = "Redundant copy of bits 7:0"] - #[inline(always)] - pub const fn r2(&self) -> u8 { - let val = (self.0 >> 16usize) & 0xff; - val as u8 - } - #[doc = "Redundant copy of bits 7:0"] - #[inline(always)] - pub fn set_r2(&mut self, val: u8) { - self.0 = (self.0 & !(0xff << 16usize)) | (((val as u32) & 0xff) << 16usize); - } -} -impl Default for Page32lock1 { - #[inline(always)] - fn default() -> Page32lock1 { - Page32lock1(0) - } -} -#[doc = "Lock configuration LSBs for page 33 (rows 0x840 through 0x87f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions."] -#[repr(transparent)] -#[derive(Copy, Clone, Eq, PartialEq)] -pub struct Page33lock0(pub u32); -impl Page33lock0 { - #[doc = "Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required."] - #[inline(always)] - pub const fn key_w(&self) -> u8 { - let val = (self.0 >> 0usize) & 0x07; - val as u8 - } - #[doc = "Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required."] - #[inline(always)] - pub fn set_key_w(&mut self, val: u8) { - self.0 = (self.0 & !(0x07 << 0usize)) | (((val as u32) & 0x07) << 0usize); - } - #[doc = "Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required."] - #[inline(always)] - pub const fn key_r(&self) -> u8 { - let val = (self.0 >> 3usize) & 0x07; - val as u8 - } - #[doc = "Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required."] - #[inline(always)] - pub fn set_key_r(&mut self, val: u8) { - self.0 = (self.0 & !(0x07 << 3usize)) | (((val as u32) & 0x07) << 3usize); - } - #[doc = "State when at least one key is registered for this page and no matching key has been entered."] - #[inline(always)] - pub const fn no_key_state(&self) -> super::vals::Page33lock0noKeyState { - let val = (self.0 >> 6usize) & 0x01; - super::vals::Page33lock0noKeyState::from_bits(val as u8) - } - #[doc = "State when at least one key is registered for this page and no matching key has been entered."] - #[inline(always)] - pub fn set_no_key_state(&mut self, val: super::vals::Page33lock0noKeyState) { - self.0 = (self.0 & !(0x01 << 6usize)) | (((val.to_bits() as u32) & 0x01) << 6usize); - } - #[doc = "Redundant copy of bits 7:0"] - #[inline(always)] - pub const fn r1(&self) -> u8 { - let val = (self.0 >> 8usize) & 0xff; - val as u8 - } - #[doc = "Redundant copy of bits 7:0"] - #[inline(always)] - pub fn set_r1(&mut self, val: u8) { - self.0 = (self.0 & !(0xff << 8usize)) | (((val as u32) & 0xff) << 8usize); - } - #[doc = "Redundant copy of bits 7:0"] - #[inline(always)] - pub const fn r2(&self) -> u8 { - let val = (self.0 >> 16usize) & 0xff; - val as u8 - } - #[doc = "Redundant copy of bits 7:0"] - #[inline(always)] - pub fn set_r2(&mut self, val: u8) { - self.0 = (self.0 & !(0xff << 16usize)) | (((val as u32) & 0xff) << 16usize); - } -} -impl Default for Page33lock0 { - #[inline(always)] - fn default() -> Page33lock0 { - Page33lock0(0) - } -} -#[doc = "Lock configuration MSBs for page 33 (rows 0x840 through 0x87f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions."] -#[repr(transparent)] -#[derive(Copy, Clone, Eq, PartialEq)] -pub struct Page33lock1(pub u32); -impl Page33lock1 { - #[doc = "Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers."] - #[inline(always)] - pub const fn lock_s(&self) -> super::vals::Page33lock1lockS { - let val = (self.0 >> 0usize) & 0x03; - super::vals::Page33lock1lockS::from_bits(val as u8) - } - #[doc = "Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers."] - #[inline(always)] - pub fn set_lock_s(&mut self, val: super::vals::Page33lock1lockS) { - self.0 = (self.0 & !(0x03 << 0usize)) | (((val.to_bits() as u32) & 0x03) << 0usize); - } - #[doc = "Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API."] - #[inline(always)] - pub const fn lock_ns(&self) -> super::vals::Page33lock1lockNs { - let val = (self.0 >> 2usize) & 0x03; - super::vals::Page33lock1lockNs::from_bits(val as u8) - } - #[doc = "Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API."] - #[inline(always)] - pub fn set_lock_ns(&mut self, val: super::vals::Page33lock1lockNs) { - self.0 = (self.0 & !(0x03 << 2usize)) | (((val.to_bits() as u32) & 0x03) << 2usize); - } - #[doc = "Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers."] - #[inline(always)] - pub const fn lock_bl(&self) -> super::vals::Page33lock1lockBl { - let val = (self.0 >> 4usize) & 0x03; - super::vals::Page33lock1lockBl::from_bits(val as u8) - } - #[doc = "Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers."] - #[inline(always)] - pub fn set_lock_bl(&mut self, val: super::vals::Page33lock1lockBl) { - self.0 = (self.0 & !(0x03 << 4usize)) | (((val.to_bits() as u32) & 0x03) << 4usize); - } - #[doc = "Redundant copy of bits 7:0"] - #[inline(always)] - pub const fn r1(&self) -> u8 { - let val = (self.0 >> 8usize) & 0xff; - val as u8 - } - #[doc = "Redundant copy of bits 7:0"] - #[inline(always)] - pub fn set_r1(&mut self, val: u8) { - self.0 = (self.0 & !(0xff << 8usize)) | (((val as u32) & 0xff) << 8usize); - } - #[doc = "Redundant copy of bits 7:0"] - #[inline(always)] - pub const fn r2(&self) -> u8 { - let val = (self.0 >> 16usize) & 0xff; - val as u8 - } - #[doc = "Redundant copy of bits 7:0"] - #[inline(always)] - pub fn set_r2(&mut self, val: u8) { - self.0 = (self.0 & !(0xff << 16usize)) | (((val as u32) & 0xff) << 16usize); - } -} -impl Default for Page33lock1 { - #[inline(always)] - fn default() -> Page33lock1 { - Page33lock1(0) - } -} -#[doc = "Lock configuration LSBs for page 34 (rows 0x880 through 0x8bf). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions."] -#[repr(transparent)] -#[derive(Copy, Clone, Eq, PartialEq)] -pub struct Page34lock0(pub u32); -impl Page34lock0 { - #[doc = "Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required."] - #[inline(always)] - pub const fn key_w(&self) -> u8 { - let val = (self.0 >> 0usize) & 0x07; - val as u8 - } - #[doc = "Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required."] - #[inline(always)] - pub fn set_key_w(&mut self, val: u8) { - self.0 = (self.0 & !(0x07 << 0usize)) | (((val as u32) & 0x07) << 0usize); - } - #[doc = "Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required."] - #[inline(always)] - pub const fn key_r(&self) -> u8 { - let val = (self.0 >> 3usize) & 0x07; - val as u8 - } - #[doc = "Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required."] - #[inline(always)] - pub fn set_key_r(&mut self, val: u8) { - self.0 = (self.0 & !(0x07 << 3usize)) | (((val as u32) & 0x07) << 3usize); - } - #[doc = "State when at least one key is registered for this page and no matching key has been entered."] - #[inline(always)] - pub const fn no_key_state(&self) -> super::vals::Page34lock0noKeyState { - let val = (self.0 >> 6usize) & 0x01; - super::vals::Page34lock0noKeyState::from_bits(val as u8) - } - #[doc = "State when at least one key is registered for this page and no matching key has been entered."] - #[inline(always)] - pub fn set_no_key_state(&mut self, val: super::vals::Page34lock0noKeyState) { - self.0 = (self.0 & !(0x01 << 6usize)) | (((val.to_bits() as u32) & 0x01) << 6usize); - } - #[doc = "Redundant copy of bits 7:0"] - #[inline(always)] - pub const fn r1(&self) -> u8 { - let val = (self.0 >> 8usize) & 0xff; - val as u8 - } - #[doc = "Redundant copy of bits 7:0"] - #[inline(always)] - pub fn set_r1(&mut self, val: u8) { - self.0 = (self.0 & !(0xff << 8usize)) | (((val as u32) & 0xff) << 8usize); - } - #[doc = "Redundant copy of bits 7:0"] - #[inline(always)] - pub const fn r2(&self) -> u8 { - let val = (self.0 >> 16usize) & 0xff; - val as u8 - } - #[doc = "Redundant copy of bits 7:0"] - #[inline(always)] - pub fn set_r2(&mut self, val: u8) { - self.0 = (self.0 & !(0xff << 16usize)) | (((val as u32) & 0xff) << 16usize); - } -} -impl Default for Page34lock0 { - #[inline(always)] - fn default() -> Page34lock0 { - Page34lock0(0) - } -} -#[doc = "Lock configuration MSBs for page 34 (rows 0x880 through 0x8bf). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions."] -#[repr(transparent)] -#[derive(Copy, Clone, Eq, PartialEq)] -pub struct Page34lock1(pub u32); -impl Page34lock1 { - #[doc = "Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers."] - #[inline(always)] - pub const fn lock_s(&self) -> super::vals::Page34lock1lockS { - let val = (self.0 >> 0usize) & 0x03; - super::vals::Page34lock1lockS::from_bits(val as u8) - } - #[doc = "Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers."] - #[inline(always)] - pub fn set_lock_s(&mut self, val: super::vals::Page34lock1lockS) { - self.0 = (self.0 & !(0x03 << 0usize)) | (((val.to_bits() as u32) & 0x03) << 0usize); - } - #[doc = "Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API."] - #[inline(always)] - pub const fn lock_ns(&self) -> super::vals::Page34lock1lockNs { - let val = (self.0 >> 2usize) & 0x03; - super::vals::Page34lock1lockNs::from_bits(val as u8) - } - #[doc = "Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API."] - #[inline(always)] - pub fn set_lock_ns(&mut self, val: super::vals::Page34lock1lockNs) { - self.0 = (self.0 & !(0x03 << 2usize)) | (((val.to_bits() as u32) & 0x03) << 2usize); - } - #[doc = "Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers."] - #[inline(always)] - pub const fn lock_bl(&self) -> super::vals::Page34lock1lockBl { - let val = (self.0 >> 4usize) & 0x03; - super::vals::Page34lock1lockBl::from_bits(val as u8) - } - #[doc = "Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers."] - #[inline(always)] - pub fn set_lock_bl(&mut self, val: super::vals::Page34lock1lockBl) { - self.0 = (self.0 & !(0x03 << 4usize)) | (((val.to_bits() as u32) & 0x03) << 4usize); - } - #[doc = "Redundant copy of bits 7:0"] - #[inline(always)] - pub const fn r1(&self) -> u8 { - let val = (self.0 >> 8usize) & 0xff; - val as u8 - } - #[doc = "Redundant copy of bits 7:0"] - #[inline(always)] - pub fn set_r1(&mut self, val: u8) { - self.0 = (self.0 & !(0xff << 8usize)) | (((val as u32) & 0xff) << 8usize); - } - #[doc = "Redundant copy of bits 7:0"] - #[inline(always)] - pub const fn r2(&self) -> u8 { - let val = (self.0 >> 16usize) & 0xff; - val as u8 - } - #[doc = "Redundant copy of bits 7:0"] - #[inline(always)] - pub fn set_r2(&mut self, val: u8) { - self.0 = (self.0 & !(0xff << 16usize)) | (((val as u32) & 0xff) << 16usize); - } -} -impl Default for Page34lock1 { - #[inline(always)] - fn default() -> Page34lock1 { - Page34lock1(0) - } -} -#[doc = "Lock configuration LSBs for page 35 (rows 0x8c0 through 0x8ff). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions."] -#[repr(transparent)] -#[derive(Copy, Clone, Eq, PartialEq)] -pub struct Page35lock0(pub u32); -impl Page35lock0 { - #[doc = "Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required."] - #[inline(always)] - pub const fn key_w(&self) -> u8 { - let val = (self.0 >> 0usize) & 0x07; - val as u8 - } - #[doc = "Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required."] - #[inline(always)] - pub fn set_key_w(&mut self, val: u8) { - self.0 = (self.0 & !(0x07 << 0usize)) | (((val as u32) & 0x07) << 0usize); - } - #[doc = "Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required."] - #[inline(always)] - pub const fn key_r(&self) -> u8 { - let val = (self.0 >> 3usize) & 0x07; - val as u8 - } - #[doc = "Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required."] - #[inline(always)] - pub fn set_key_r(&mut self, val: u8) { - self.0 = (self.0 & !(0x07 << 3usize)) | (((val as u32) & 0x07) << 3usize); - } - #[doc = "State when at least one key is registered for this page and no matching key has been entered."] - #[inline(always)] - pub const fn no_key_state(&self) -> super::vals::Page35lock0noKeyState { - let val = (self.0 >> 6usize) & 0x01; - super::vals::Page35lock0noKeyState::from_bits(val as u8) - } - #[doc = "State when at least one key is registered for this page and no matching key has been entered."] - #[inline(always)] - pub fn set_no_key_state(&mut self, val: super::vals::Page35lock0noKeyState) { - self.0 = (self.0 & !(0x01 << 6usize)) | (((val.to_bits() as u32) & 0x01) << 6usize); - } - #[doc = "Redundant copy of bits 7:0"] - #[inline(always)] - pub const fn r1(&self) -> u8 { - let val = (self.0 >> 8usize) & 0xff; - val as u8 - } - #[doc = "Redundant copy of bits 7:0"] - #[inline(always)] - pub fn set_r1(&mut self, val: u8) { - self.0 = (self.0 & !(0xff << 8usize)) | (((val as u32) & 0xff) << 8usize); - } - #[doc = "Redundant copy of bits 7:0"] - #[inline(always)] - pub const fn r2(&self) -> u8 { - let val = (self.0 >> 16usize) & 0xff; - val as u8 - } - #[doc = "Redundant copy of bits 7:0"] - #[inline(always)] - pub fn set_r2(&mut self, val: u8) { - self.0 = (self.0 & !(0xff << 16usize)) | (((val as u32) & 0xff) << 16usize); - } -} -impl Default for Page35lock0 { - #[inline(always)] - fn default() -> Page35lock0 { - Page35lock0(0) - } -} -#[doc = "Lock configuration MSBs for page 35 (rows 0x8c0 through 0x8ff). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions."] -#[repr(transparent)] -#[derive(Copy, Clone, Eq, PartialEq)] -pub struct Page35lock1(pub u32); -impl Page35lock1 { - #[doc = "Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers."] - #[inline(always)] - pub const fn lock_s(&self) -> super::vals::Page35lock1lockS { - let val = (self.0 >> 0usize) & 0x03; - super::vals::Page35lock1lockS::from_bits(val as u8) - } - #[doc = "Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers."] - #[inline(always)] - pub fn set_lock_s(&mut self, val: super::vals::Page35lock1lockS) { - self.0 = (self.0 & !(0x03 << 0usize)) | (((val.to_bits() as u32) & 0x03) << 0usize); - } - #[doc = "Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API."] - #[inline(always)] - pub const fn lock_ns(&self) -> super::vals::Page35lock1lockNs { - let val = (self.0 >> 2usize) & 0x03; - super::vals::Page35lock1lockNs::from_bits(val as u8) - } - #[doc = "Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API."] - #[inline(always)] - pub fn set_lock_ns(&mut self, val: super::vals::Page35lock1lockNs) { - self.0 = (self.0 & !(0x03 << 2usize)) | (((val.to_bits() as u32) & 0x03) << 2usize); - } - #[doc = "Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers."] - #[inline(always)] - pub const fn lock_bl(&self) -> super::vals::Page35lock1lockBl { - let val = (self.0 >> 4usize) & 0x03; - super::vals::Page35lock1lockBl::from_bits(val as u8) - } - #[doc = "Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers."] - #[inline(always)] - pub fn set_lock_bl(&mut self, val: super::vals::Page35lock1lockBl) { - self.0 = (self.0 & !(0x03 << 4usize)) | (((val.to_bits() as u32) & 0x03) << 4usize); - } - #[doc = "Redundant copy of bits 7:0"] - #[inline(always)] - pub const fn r1(&self) -> u8 { - let val = (self.0 >> 8usize) & 0xff; - val as u8 - } - #[doc = "Redundant copy of bits 7:0"] - #[inline(always)] - pub fn set_r1(&mut self, val: u8) { - self.0 = (self.0 & !(0xff << 8usize)) | (((val as u32) & 0xff) << 8usize); - } - #[doc = "Redundant copy of bits 7:0"] - #[inline(always)] - pub const fn r2(&self) -> u8 { - let val = (self.0 >> 16usize) & 0xff; - val as u8 - } - #[doc = "Redundant copy of bits 7:0"] - #[inline(always)] - pub fn set_r2(&mut self, val: u8) { - self.0 = (self.0 & !(0xff << 16usize)) | (((val as u32) & 0xff) << 16usize); - } -} -impl Default for Page35lock1 { - #[inline(always)] - fn default() -> Page35lock1 { - Page35lock1(0) - } -} -#[doc = "Lock configuration LSBs for page 36 (rows 0x900 through 0x93f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions."] -#[repr(transparent)] -#[derive(Copy, Clone, Eq, PartialEq)] -pub struct Page36lock0(pub u32); -impl Page36lock0 { - #[doc = "Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required."] - #[inline(always)] - pub const fn key_w(&self) -> u8 { - let val = (self.0 >> 0usize) & 0x07; - val as u8 - } - #[doc = "Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required."] - #[inline(always)] - pub fn set_key_w(&mut self, val: u8) { - self.0 = (self.0 & !(0x07 << 0usize)) | (((val as u32) & 0x07) << 0usize); - } - #[doc = "Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required."] - #[inline(always)] - pub const fn key_r(&self) -> u8 { - let val = (self.0 >> 3usize) & 0x07; - val as u8 - } - #[doc = "Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required."] - #[inline(always)] - pub fn set_key_r(&mut self, val: u8) { - self.0 = (self.0 & !(0x07 << 3usize)) | (((val as u32) & 0x07) << 3usize); - } - #[doc = "State when at least one key is registered for this page and no matching key has been entered."] - #[inline(always)] - pub const fn no_key_state(&self) -> super::vals::Page36lock0noKeyState { - let val = (self.0 >> 6usize) & 0x01; - super::vals::Page36lock0noKeyState::from_bits(val as u8) - } - #[doc = "State when at least one key is registered for this page and no matching key has been entered."] - #[inline(always)] - pub fn set_no_key_state(&mut self, val: super::vals::Page36lock0noKeyState) { - self.0 = (self.0 & !(0x01 << 6usize)) | (((val.to_bits() as u32) & 0x01) << 6usize); - } - #[doc = "Redundant copy of bits 7:0"] - #[inline(always)] - pub const fn r1(&self) -> u8 { - let val = (self.0 >> 8usize) & 0xff; - val as u8 - } - #[doc = "Redundant copy of bits 7:0"] - #[inline(always)] - pub fn set_r1(&mut self, val: u8) { - self.0 = (self.0 & !(0xff << 8usize)) | (((val as u32) & 0xff) << 8usize); - } - #[doc = "Redundant copy of bits 7:0"] - #[inline(always)] - pub const fn r2(&self) -> u8 { - let val = (self.0 >> 16usize) & 0xff; - val as u8 - } - #[doc = "Redundant copy of bits 7:0"] - #[inline(always)] - pub fn set_r2(&mut self, val: u8) { - self.0 = (self.0 & !(0xff << 16usize)) | (((val as u32) & 0xff) << 16usize); - } -} -impl Default for Page36lock0 { - #[inline(always)] - fn default() -> Page36lock0 { - Page36lock0(0) - } -} -#[doc = "Lock configuration MSBs for page 36 (rows 0x900 through 0x93f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions."] -#[repr(transparent)] -#[derive(Copy, Clone, Eq, PartialEq)] -pub struct Page36lock1(pub u32); -impl Page36lock1 { - #[doc = "Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers."] - #[inline(always)] - pub const fn lock_s(&self) -> super::vals::Page36lock1lockS { - let val = (self.0 >> 0usize) & 0x03; - super::vals::Page36lock1lockS::from_bits(val as u8) - } - #[doc = "Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers."] - #[inline(always)] - pub fn set_lock_s(&mut self, val: super::vals::Page36lock1lockS) { - self.0 = (self.0 & !(0x03 << 0usize)) | (((val.to_bits() as u32) & 0x03) << 0usize); - } - #[doc = "Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API."] - #[inline(always)] - pub const fn lock_ns(&self) -> super::vals::Page36lock1lockNs { - let val = (self.0 >> 2usize) & 0x03; - super::vals::Page36lock1lockNs::from_bits(val as u8) - } - #[doc = "Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API."] - #[inline(always)] - pub fn set_lock_ns(&mut self, val: super::vals::Page36lock1lockNs) { - self.0 = (self.0 & !(0x03 << 2usize)) | (((val.to_bits() as u32) & 0x03) << 2usize); - } - #[doc = "Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers."] - #[inline(always)] - pub const fn lock_bl(&self) -> super::vals::Page36lock1lockBl { - let val = (self.0 >> 4usize) & 0x03; - super::vals::Page36lock1lockBl::from_bits(val as u8) - } - #[doc = "Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers."] - #[inline(always)] - pub fn set_lock_bl(&mut self, val: super::vals::Page36lock1lockBl) { - self.0 = (self.0 & !(0x03 << 4usize)) | (((val.to_bits() as u32) & 0x03) << 4usize); - } - #[doc = "Redundant copy of bits 7:0"] - #[inline(always)] - pub const fn r1(&self) -> u8 { - let val = (self.0 >> 8usize) & 0xff; - val as u8 - } - #[doc = "Redundant copy of bits 7:0"] - #[inline(always)] - pub fn set_r1(&mut self, val: u8) { - self.0 = (self.0 & !(0xff << 8usize)) | (((val as u32) & 0xff) << 8usize); - } - #[doc = "Redundant copy of bits 7:0"] - #[inline(always)] - pub const fn r2(&self) -> u8 { - let val = (self.0 >> 16usize) & 0xff; - val as u8 - } - #[doc = "Redundant copy of bits 7:0"] - #[inline(always)] - pub fn set_r2(&mut self, val: u8) { - self.0 = (self.0 & !(0xff << 16usize)) | (((val as u32) & 0xff) << 16usize); - } -} -impl Default for Page36lock1 { - #[inline(always)] - fn default() -> Page36lock1 { - Page36lock1(0) - } -} -#[doc = "Lock configuration LSBs for page 37 (rows 0x940 through 0x97f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions."] -#[repr(transparent)] -#[derive(Copy, Clone, Eq, PartialEq)] -pub struct Page37lock0(pub u32); -impl Page37lock0 { - #[doc = "Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required."] - #[inline(always)] - pub const fn key_w(&self) -> u8 { - let val = (self.0 >> 0usize) & 0x07; - val as u8 - } - #[doc = "Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required."] - #[inline(always)] - pub fn set_key_w(&mut self, val: u8) { - self.0 = (self.0 & !(0x07 << 0usize)) | (((val as u32) & 0x07) << 0usize); - } - #[doc = "Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required."] - #[inline(always)] - pub const fn key_r(&self) -> u8 { - let val = (self.0 >> 3usize) & 0x07; - val as u8 - } - #[doc = "Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required."] - #[inline(always)] - pub fn set_key_r(&mut self, val: u8) { - self.0 = (self.0 & !(0x07 << 3usize)) | (((val as u32) & 0x07) << 3usize); - } - #[doc = "State when at least one key is registered for this page and no matching key has been entered."] - #[inline(always)] - pub const fn no_key_state(&self) -> super::vals::Page37lock0noKeyState { - let val = (self.0 >> 6usize) & 0x01; - super::vals::Page37lock0noKeyState::from_bits(val as u8) - } - #[doc = "State when at least one key is registered for this page and no matching key has been entered."] - #[inline(always)] - pub fn set_no_key_state(&mut self, val: super::vals::Page37lock0noKeyState) { - self.0 = (self.0 & !(0x01 << 6usize)) | (((val.to_bits() as u32) & 0x01) << 6usize); - } - #[doc = "Redundant copy of bits 7:0"] - #[inline(always)] - pub const fn r1(&self) -> u8 { - let val = (self.0 >> 8usize) & 0xff; - val as u8 - } - #[doc = "Redundant copy of bits 7:0"] - #[inline(always)] - pub fn set_r1(&mut self, val: u8) { - self.0 = (self.0 & !(0xff << 8usize)) | (((val as u32) & 0xff) << 8usize); - } - #[doc = "Redundant copy of bits 7:0"] - #[inline(always)] - pub const fn r2(&self) -> u8 { - let val = (self.0 >> 16usize) & 0xff; - val as u8 - } - #[doc = "Redundant copy of bits 7:0"] - #[inline(always)] - pub fn set_r2(&mut self, val: u8) { - self.0 = (self.0 & !(0xff << 16usize)) | (((val as u32) & 0xff) << 16usize); - } -} -impl Default for Page37lock0 { - #[inline(always)] - fn default() -> Page37lock0 { - Page37lock0(0) - } -} -#[doc = "Lock configuration MSBs for page 37 (rows 0x940 through 0x97f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions."] -#[repr(transparent)] -#[derive(Copy, Clone, Eq, PartialEq)] -pub struct Page37lock1(pub u32); -impl Page37lock1 { - #[doc = "Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers."] - #[inline(always)] - pub const fn lock_s(&self) -> super::vals::Page37lock1lockS { - let val = (self.0 >> 0usize) & 0x03; - super::vals::Page37lock1lockS::from_bits(val as u8) - } - #[doc = "Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers."] - #[inline(always)] - pub fn set_lock_s(&mut self, val: super::vals::Page37lock1lockS) { - self.0 = (self.0 & !(0x03 << 0usize)) | (((val.to_bits() as u32) & 0x03) << 0usize); - } - #[doc = "Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API."] - #[inline(always)] - pub const fn lock_ns(&self) -> super::vals::Page37lock1lockNs { - let val = (self.0 >> 2usize) & 0x03; - super::vals::Page37lock1lockNs::from_bits(val as u8) - } - #[doc = "Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API."] - #[inline(always)] - pub fn set_lock_ns(&mut self, val: super::vals::Page37lock1lockNs) { - self.0 = (self.0 & !(0x03 << 2usize)) | (((val.to_bits() as u32) & 0x03) << 2usize); - } - #[doc = "Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers."] - #[inline(always)] - pub const fn lock_bl(&self) -> super::vals::Page37lock1lockBl { - let val = (self.0 >> 4usize) & 0x03; - super::vals::Page37lock1lockBl::from_bits(val as u8) - } - #[doc = "Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers."] - #[inline(always)] - pub fn set_lock_bl(&mut self, val: super::vals::Page37lock1lockBl) { - self.0 = (self.0 & !(0x03 << 4usize)) | (((val.to_bits() as u32) & 0x03) << 4usize); - } - #[doc = "Redundant copy of bits 7:0"] - #[inline(always)] - pub const fn r1(&self) -> u8 { - let val = (self.0 >> 8usize) & 0xff; - val as u8 - } - #[doc = "Redundant copy of bits 7:0"] - #[inline(always)] - pub fn set_r1(&mut self, val: u8) { - self.0 = (self.0 & !(0xff << 8usize)) | (((val as u32) & 0xff) << 8usize); - } - #[doc = "Redundant copy of bits 7:0"] - #[inline(always)] - pub const fn r2(&self) -> u8 { - let val = (self.0 >> 16usize) & 0xff; - val as u8 - } - #[doc = "Redundant copy of bits 7:0"] - #[inline(always)] - pub fn set_r2(&mut self, val: u8) { - self.0 = (self.0 & !(0xff << 16usize)) | (((val as u32) & 0xff) << 16usize); - } -} -impl Default for Page37lock1 { - #[inline(always)] - fn default() -> Page37lock1 { - Page37lock1(0) - } -} -#[doc = "Lock configuration LSBs for page 38 (rows 0x980 through 0x9bf). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions."] -#[repr(transparent)] -#[derive(Copy, Clone, Eq, PartialEq)] -pub struct Page38lock0(pub u32); -impl Page38lock0 { - #[doc = "Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required."] - #[inline(always)] - pub const fn key_w(&self) -> u8 { - let val = (self.0 >> 0usize) & 0x07; - val as u8 - } - #[doc = "Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required."] - #[inline(always)] - pub fn set_key_w(&mut self, val: u8) { - self.0 = (self.0 & !(0x07 << 0usize)) | (((val as u32) & 0x07) << 0usize); - } - #[doc = "Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required."] - #[inline(always)] - pub const fn key_r(&self) -> u8 { - let val = (self.0 >> 3usize) & 0x07; - val as u8 - } - #[doc = "Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required."] - #[inline(always)] - pub fn set_key_r(&mut self, val: u8) { - self.0 = (self.0 & !(0x07 << 3usize)) | (((val as u32) & 0x07) << 3usize); - } - #[doc = "State when at least one key is registered for this page and no matching key has been entered."] - #[inline(always)] - pub const fn no_key_state(&self) -> super::vals::Page38lock0noKeyState { - let val = (self.0 >> 6usize) & 0x01; - super::vals::Page38lock0noKeyState::from_bits(val as u8) - } - #[doc = "State when at least one key is registered for this page and no matching key has been entered."] - #[inline(always)] - pub fn set_no_key_state(&mut self, val: super::vals::Page38lock0noKeyState) { - self.0 = (self.0 & !(0x01 << 6usize)) | (((val.to_bits() as u32) & 0x01) << 6usize); - } - #[doc = "Redundant copy of bits 7:0"] - #[inline(always)] - pub const fn r1(&self) -> u8 { - let val = (self.0 >> 8usize) & 0xff; - val as u8 - } - #[doc = "Redundant copy of bits 7:0"] - #[inline(always)] - pub fn set_r1(&mut self, val: u8) { - self.0 = (self.0 & !(0xff << 8usize)) | (((val as u32) & 0xff) << 8usize); - } - #[doc = "Redundant copy of bits 7:0"] - #[inline(always)] - pub const fn r2(&self) -> u8 { - let val = (self.0 >> 16usize) & 0xff; - val as u8 - } - #[doc = "Redundant copy of bits 7:0"] - #[inline(always)] - pub fn set_r2(&mut self, val: u8) { - self.0 = (self.0 & !(0xff << 16usize)) | (((val as u32) & 0xff) << 16usize); - } -} -impl Default for Page38lock0 { - #[inline(always)] - fn default() -> Page38lock0 { - Page38lock0(0) - } -} -#[doc = "Lock configuration MSBs for page 38 (rows 0x980 through 0x9bf). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions."] -#[repr(transparent)] -#[derive(Copy, Clone, Eq, PartialEq)] -pub struct Page38lock1(pub u32); -impl Page38lock1 { - #[doc = "Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers."] - #[inline(always)] - pub const fn lock_s(&self) -> super::vals::Page38lock1lockS { - let val = (self.0 >> 0usize) & 0x03; - super::vals::Page38lock1lockS::from_bits(val as u8) - } - #[doc = "Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers."] - #[inline(always)] - pub fn set_lock_s(&mut self, val: super::vals::Page38lock1lockS) { - self.0 = (self.0 & !(0x03 << 0usize)) | (((val.to_bits() as u32) & 0x03) << 0usize); - } - #[doc = "Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API."] - #[inline(always)] - pub const fn lock_ns(&self) -> super::vals::Page38lock1lockNs { - let val = (self.0 >> 2usize) & 0x03; - super::vals::Page38lock1lockNs::from_bits(val as u8) - } - #[doc = "Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API."] - #[inline(always)] - pub fn set_lock_ns(&mut self, val: super::vals::Page38lock1lockNs) { - self.0 = (self.0 & !(0x03 << 2usize)) | (((val.to_bits() as u32) & 0x03) << 2usize); - } - #[doc = "Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers."] - #[inline(always)] - pub const fn lock_bl(&self) -> super::vals::Page38lock1lockBl { - let val = (self.0 >> 4usize) & 0x03; - super::vals::Page38lock1lockBl::from_bits(val as u8) - } - #[doc = "Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers."] - #[inline(always)] - pub fn set_lock_bl(&mut self, val: super::vals::Page38lock1lockBl) { - self.0 = (self.0 & !(0x03 << 4usize)) | (((val.to_bits() as u32) & 0x03) << 4usize); - } - #[doc = "Redundant copy of bits 7:0"] - #[inline(always)] - pub const fn r1(&self) -> u8 { - let val = (self.0 >> 8usize) & 0xff; - val as u8 - } - #[doc = "Redundant copy of bits 7:0"] - #[inline(always)] - pub fn set_r1(&mut self, val: u8) { - self.0 = (self.0 & !(0xff << 8usize)) | (((val as u32) & 0xff) << 8usize); - } - #[doc = "Redundant copy of bits 7:0"] - #[inline(always)] - pub const fn r2(&self) -> u8 { - let val = (self.0 >> 16usize) & 0xff; - val as u8 - } - #[doc = "Redundant copy of bits 7:0"] - #[inline(always)] - pub fn set_r2(&mut self, val: u8) { - self.0 = (self.0 & !(0xff << 16usize)) | (((val as u32) & 0xff) << 16usize); - } -} -impl Default for Page38lock1 { - #[inline(always)] - fn default() -> Page38lock1 { - Page38lock1(0) - } -} -#[doc = "Lock configuration LSBs for page 39 (rows 0x9c0 through 0x9ff). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions."] -#[repr(transparent)] -#[derive(Copy, Clone, Eq, PartialEq)] -pub struct Page39lock0(pub u32); -impl Page39lock0 { - #[doc = "Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required."] - #[inline(always)] - pub const fn key_w(&self) -> u8 { - let val = (self.0 >> 0usize) & 0x07; - val as u8 - } - #[doc = "Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required."] - #[inline(always)] - pub fn set_key_w(&mut self, val: u8) { - self.0 = (self.0 & !(0x07 << 0usize)) | (((val as u32) & 0x07) << 0usize); - } - #[doc = "Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required."] - #[inline(always)] - pub const fn key_r(&self) -> u8 { - let val = (self.0 >> 3usize) & 0x07; - val as u8 - } - #[doc = "Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required."] - #[inline(always)] - pub fn set_key_r(&mut self, val: u8) { - self.0 = (self.0 & !(0x07 << 3usize)) | (((val as u32) & 0x07) << 3usize); - } - #[doc = "State when at least one key is registered for this page and no matching key has been entered."] - #[inline(always)] - pub const fn no_key_state(&self) -> super::vals::Page39lock0noKeyState { - let val = (self.0 >> 6usize) & 0x01; - super::vals::Page39lock0noKeyState::from_bits(val as u8) - } - #[doc = "State when at least one key is registered for this page and no matching key has been entered."] - #[inline(always)] - pub fn set_no_key_state(&mut self, val: super::vals::Page39lock0noKeyState) { - self.0 = (self.0 & !(0x01 << 6usize)) | (((val.to_bits() as u32) & 0x01) << 6usize); - } - #[doc = "Redundant copy of bits 7:0"] - #[inline(always)] - pub const fn r1(&self) -> u8 { - let val = (self.0 >> 8usize) & 0xff; - val as u8 - } - #[doc = "Redundant copy of bits 7:0"] - #[inline(always)] - pub fn set_r1(&mut self, val: u8) { - self.0 = (self.0 & !(0xff << 8usize)) | (((val as u32) & 0xff) << 8usize); - } - #[doc = "Redundant copy of bits 7:0"] - #[inline(always)] - pub const fn r2(&self) -> u8 { - let val = (self.0 >> 16usize) & 0xff; - val as u8 - } - #[doc = "Redundant copy of bits 7:0"] - #[inline(always)] - pub fn set_r2(&mut self, val: u8) { - self.0 = (self.0 & !(0xff << 16usize)) | (((val as u32) & 0xff) << 16usize); - } -} -impl Default for Page39lock0 { - #[inline(always)] - fn default() -> Page39lock0 { - Page39lock0(0) - } -} -#[doc = "Lock configuration MSBs for page 39 (rows 0x9c0 through 0x9ff). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions."] -#[repr(transparent)] -#[derive(Copy, Clone, Eq, PartialEq)] -pub struct Page39lock1(pub u32); -impl Page39lock1 { - #[doc = "Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers."] - #[inline(always)] - pub const fn lock_s(&self) -> super::vals::Page39lock1lockS { - let val = (self.0 >> 0usize) & 0x03; - super::vals::Page39lock1lockS::from_bits(val as u8) - } - #[doc = "Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers."] - #[inline(always)] - pub fn set_lock_s(&mut self, val: super::vals::Page39lock1lockS) { - self.0 = (self.0 & !(0x03 << 0usize)) | (((val.to_bits() as u32) & 0x03) << 0usize); - } - #[doc = "Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API."] - #[inline(always)] - pub const fn lock_ns(&self) -> super::vals::Page39lock1lockNs { - let val = (self.0 >> 2usize) & 0x03; - super::vals::Page39lock1lockNs::from_bits(val as u8) - } - #[doc = "Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API."] - #[inline(always)] - pub fn set_lock_ns(&mut self, val: super::vals::Page39lock1lockNs) { - self.0 = (self.0 & !(0x03 << 2usize)) | (((val.to_bits() as u32) & 0x03) << 2usize); - } - #[doc = "Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers."] - #[inline(always)] - pub const fn lock_bl(&self) -> super::vals::Page39lock1lockBl { - let val = (self.0 >> 4usize) & 0x03; - super::vals::Page39lock1lockBl::from_bits(val as u8) - } - #[doc = "Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers."] - #[inline(always)] - pub fn set_lock_bl(&mut self, val: super::vals::Page39lock1lockBl) { - self.0 = (self.0 & !(0x03 << 4usize)) | (((val.to_bits() as u32) & 0x03) << 4usize); - } - #[doc = "Redundant copy of bits 7:0"] - #[inline(always)] - pub const fn r1(&self) -> u8 { - let val = (self.0 >> 8usize) & 0xff; - val as u8 - } - #[doc = "Redundant copy of bits 7:0"] - #[inline(always)] - pub fn set_r1(&mut self, val: u8) { - self.0 = (self.0 & !(0xff << 8usize)) | (((val as u32) & 0xff) << 8usize); - } - #[doc = "Redundant copy of bits 7:0"] - #[inline(always)] - pub const fn r2(&self) -> u8 { - let val = (self.0 >> 16usize) & 0xff; - val as u8 - } - #[doc = "Redundant copy of bits 7:0"] - #[inline(always)] - pub fn set_r2(&mut self, val: u8) { - self.0 = (self.0 & !(0xff << 16usize)) | (((val as u32) & 0xff) << 16usize); - } -} -impl Default for Page39lock1 { - #[inline(always)] - fn default() -> Page39lock1 { - Page39lock1(0) - } -} -#[doc = "Lock configuration LSBs for page 3 (rows 0xc0 through 0xff). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions."] -#[repr(transparent)] -#[derive(Copy, Clone, Eq, PartialEq)] -pub struct Page3lock0(pub u32); -impl Page3lock0 { - #[doc = "Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required."] - #[inline(always)] - pub const fn key_w(&self) -> u8 { - let val = (self.0 >> 0usize) & 0x07; - val as u8 - } - #[doc = "Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required."] - #[inline(always)] - pub fn set_key_w(&mut self, val: u8) { - self.0 = (self.0 & !(0x07 << 0usize)) | (((val as u32) & 0x07) << 0usize); - } - #[doc = "Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required."] - #[inline(always)] - pub const fn key_r(&self) -> u8 { - let val = (self.0 >> 3usize) & 0x07; - val as u8 - } - #[doc = "Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required."] - #[inline(always)] - pub fn set_key_r(&mut self, val: u8) { - self.0 = (self.0 & !(0x07 << 3usize)) | (((val as u32) & 0x07) << 3usize); - } - #[doc = "State when at least one key is registered for this page and no matching key has been entered."] - #[inline(always)] - pub const fn no_key_state(&self) -> super::vals::Page3lock0noKeyState { - let val = (self.0 >> 6usize) & 0x01; - super::vals::Page3lock0noKeyState::from_bits(val as u8) - } - #[doc = "State when at least one key is registered for this page and no matching key has been entered."] - #[inline(always)] - pub fn set_no_key_state(&mut self, val: super::vals::Page3lock0noKeyState) { - self.0 = (self.0 & !(0x01 << 6usize)) | (((val.to_bits() as u32) & 0x01) << 6usize); - } - #[doc = "Redundant copy of bits 7:0"] - #[inline(always)] - pub const fn r1(&self) -> u8 { - let val = (self.0 >> 8usize) & 0xff; - val as u8 - } - #[doc = "Redundant copy of bits 7:0"] - #[inline(always)] - pub fn set_r1(&mut self, val: u8) { - self.0 = (self.0 & !(0xff << 8usize)) | (((val as u32) & 0xff) << 8usize); - } - #[doc = "Redundant copy of bits 7:0"] - #[inline(always)] - pub const fn r2(&self) -> u8 { - let val = (self.0 >> 16usize) & 0xff; - val as u8 - } - #[doc = "Redundant copy of bits 7:0"] - #[inline(always)] - pub fn set_r2(&mut self, val: u8) { - self.0 = (self.0 & !(0xff << 16usize)) | (((val as u32) & 0xff) << 16usize); - } -} -impl Default for Page3lock0 { - #[inline(always)] - fn default() -> Page3lock0 { - Page3lock0(0) - } -} -#[doc = "Lock configuration MSBs for page 3 (rows 0xc0 through 0xff). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions."] -#[repr(transparent)] -#[derive(Copy, Clone, Eq, PartialEq)] -pub struct Page3lock1(pub u32); -impl Page3lock1 { - #[doc = "Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers."] - #[inline(always)] - pub const fn lock_s(&self) -> super::vals::Page3lock1lockS { - let val = (self.0 >> 0usize) & 0x03; - super::vals::Page3lock1lockS::from_bits(val as u8) - } - #[doc = "Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers."] - #[inline(always)] - pub fn set_lock_s(&mut self, val: super::vals::Page3lock1lockS) { - self.0 = (self.0 & !(0x03 << 0usize)) | (((val.to_bits() as u32) & 0x03) << 0usize); - } - #[doc = "Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API."] - #[inline(always)] - pub const fn lock_ns(&self) -> super::vals::Page3lock1lockNs { - let val = (self.0 >> 2usize) & 0x03; - super::vals::Page3lock1lockNs::from_bits(val as u8) - } - #[doc = "Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API."] - #[inline(always)] - pub fn set_lock_ns(&mut self, val: super::vals::Page3lock1lockNs) { - self.0 = (self.0 & !(0x03 << 2usize)) | (((val.to_bits() as u32) & 0x03) << 2usize); - } - #[doc = "Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers."] - #[inline(always)] - pub const fn lock_bl(&self) -> super::vals::Page3lock1lockBl { - let val = (self.0 >> 4usize) & 0x03; - super::vals::Page3lock1lockBl::from_bits(val as u8) - } - #[doc = "Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers."] - #[inline(always)] - pub fn set_lock_bl(&mut self, val: super::vals::Page3lock1lockBl) { - self.0 = (self.0 & !(0x03 << 4usize)) | (((val.to_bits() as u32) & 0x03) << 4usize); - } - #[doc = "Redundant copy of bits 7:0"] - #[inline(always)] - pub const fn r1(&self) -> u8 { - let val = (self.0 >> 8usize) & 0xff; - val as u8 - } - #[doc = "Redundant copy of bits 7:0"] - #[inline(always)] - pub fn set_r1(&mut self, val: u8) { - self.0 = (self.0 & !(0xff << 8usize)) | (((val as u32) & 0xff) << 8usize); - } - #[doc = "Redundant copy of bits 7:0"] - #[inline(always)] - pub const fn r2(&self) -> u8 { - let val = (self.0 >> 16usize) & 0xff; - val as u8 - } - #[doc = "Redundant copy of bits 7:0"] - #[inline(always)] - pub fn set_r2(&mut self, val: u8) { - self.0 = (self.0 & !(0xff << 16usize)) | (((val as u32) & 0xff) << 16usize); - } -} -impl Default for Page3lock1 { - #[inline(always)] - fn default() -> Page3lock1 { - Page3lock1(0) - } -} -#[doc = "Lock configuration LSBs for page 40 (rows 0xa00 through 0xa3f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions."] -#[repr(transparent)] -#[derive(Copy, Clone, Eq, PartialEq)] -pub struct Page40lock0(pub u32); -impl Page40lock0 { - #[doc = "Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required."] - #[inline(always)] - pub const fn key_w(&self) -> u8 { - let val = (self.0 >> 0usize) & 0x07; - val as u8 - } - #[doc = "Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required."] - #[inline(always)] - pub fn set_key_w(&mut self, val: u8) { - self.0 = (self.0 & !(0x07 << 0usize)) | (((val as u32) & 0x07) << 0usize); - } - #[doc = "Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required."] - #[inline(always)] - pub const fn key_r(&self) -> u8 { - let val = (self.0 >> 3usize) & 0x07; - val as u8 - } - #[doc = "Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required."] - #[inline(always)] - pub fn set_key_r(&mut self, val: u8) { - self.0 = (self.0 & !(0x07 << 3usize)) | (((val as u32) & 0x07) << 3usize); - } - #[doc = "State when at least one key is registered for this page and no matching key has been entered."] - #[inline(always)] - pub const fn no_key_state(&self) -> super::vals::Page40lock0noKeyState { - let val = (self.0 >> 6usize) & 0x01; - super::vals::Page40lock0noKeyState::from_bits(val as u8) - } - #[doc = "State when at least one key is registered for this page and no matching key has been entered."] - #[inline(always)] - pub fn set_no_key_state(&mut self, val: super::vals::Page40lock0noKeyState) { - self.0 = (self.0 & !(0x01 << 6usize)) | (((val.to_bits() as u32) & 0x01) << 6usize); - } - #[doc = "Redundant copy of bits 7:0"] - #[inline(always)] - pub const fn r1(&self) -> u8 { - let val = (self.0 >> 8usize) & 0xff; - val as u8 - } - #[doc = "Redundant copy of bits 7:0"] - #[inline(always)] - pub fn set_r1(&mut self, val: u8) { - self.0 = (self.0 & !(0xff << 8usize)) | (((val as u32) & 0xff) << 8usize); - } - #[doc = "Redundant copy of bits 7:0"] - #[inline(always)] - pub const fn r2(&self) -> u8 { - let val = (self.0 >> 16usize) & 0xff; - val as u8 - } - #[doc = "Redundant copy of bits 7:0"] - #[inline(always)] - pub fn set_r2(&mut self, val: u8) { - self.0 = (self.0 & !(0xff << 16usize)) | (((val as u32) & 0xff) << 16usize); - } -} -impl Default for Page40lock0 { - #[inline(always)] - fn default() -> Page40lock0 { - Page40lock0(0) - } -} -#[doc = "Lock configuration MSBs for page 40 (rows 0xa00 through 0xa3f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions."] -#[repr(transparent)] -#[derive(Copy, Clone, Eq, PartialEq)] -pub struct Page40lock1(pub u32); -impl Page40lock1 { - #[doc = "Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers."] - #[inline(always)] - pub const fn lock_s(&self) -> super::vals::Page40lock1lockS { - let val = (self.0 >> 0usize) & 0x03; - super::vals::Page40lock1lockS::from_bits(val as u8) - } - #[doc = "Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers."] - #[inline(always)] - pub fn set_lock_s(&mut self, val: super::vals::Page40lock1lockS) { - self.0 = (self.0 & !(0x03 << 0usize)) | (((val.to_bits() as u32) & 0x03) << 0usize); - } - #[doc = "Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API."] - #[inline(always)] - pub const fn lock_ns(&self) -> super::vals::Page40lock1lockNs { - let val = (self.0 >> 2usize) & 0x03; - super::vals::Page40lock1lockNs::from_bits(val as u8) - } - #[doc = "Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API."] - #[inline(always)] - pub fn set_lock_ns(&mut self, val: super::vals::Page40lock1lockNs) { - self.0 = (self.0 & !(0x03 << 2usize)) | (((val.to_bits() as u32) & 0x03) << 2usize); - } - #[doc = "Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers."] - #[inline(always)] - pub const fn lock_bl(&self) -> super::vals::Page40lock1lockBl { - let val = (self.0 >> 4usize) & 0x03; - super::vals::Page40lock1lockBl::from_bits(val as u8) - } - #[doc = "Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers."] - #[inline(always)] - pub fn set_lock_bl(&mut self, val: super::vals::Page40lock1lockBl) { - self.0 = (self.0 & !(0x03 << 4usize)) | (((val.to_bits() as u32) & 0x03) << 4usize); - } - #[doc = "Redundant copy of bits 7:0"] - #[inline(always)] - pub const fn r1(&self) -> u8 { - let val = (self.0 >> 8usize) & 0xff; - val as u8 - } - #[doc = "Redundant copy of bits 7:0"] - #[inline(always)] - pub fn set_r1(&mut self, val: u8) { - self.0 = (self.0 & !(0xff << 8usize)) | (((val as u32) & 0xff) << 8usize); - } - #[doc = "Redundant copy of bits 7:0"] - #[inline(always)] - pub const fn r2(&self) -> u8 { - let val = (self.0 >> 16usize) & 0xff; - val as u8 - } - #[doc = "Redundant copy of bits 7:0"] - #[inline(always)] - pub fn set_r2(&mut self, val: u8) { - self.0 = (self.0 & !(0xff << 16usize)) | (((val as u32) & 0xff) << 16usize); - } -} -impl Default for Page40lock1 { - #[inline(always)] - fn default() -> Page40lock1 { - Page40lock1(0) - } -} -#[doc = "Lock configuration LSBs for page 41 (rows 0xa40 through 0xa7f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions."] -#[repr(transparent)] -#[derive(Copy, Clone, Eq, PartialEq)] -pub struct Page41lock0(pub u32); -impl Page41lock0 { - #[doc = "Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required."] - #[inline(always)] - pub const fn key_w(&self) -> u8 { - let val = (self.0 >> 0usize) & 0x07; - val as u8 - } - #[doc = "Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required."] - #[inline(always)] - pub fn set_key_w(&mut self, val: u8) { - self.0 = (self.0 & !(0x07 << 0usize)) | (((val as u32) & 0x07) << 0usize); - } - #[doc = "Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required."] - #[inline(always)] - pub const fn key_r(&self) -> u8 { - let val = (self.0 >> 3usize) & 0x07; - val as u8 - } - #[doc = "Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required."] - #[inline(always)] - pub fn set_key_r(&mut self, val: u8) { - self.0 = (self.0 & !(0x07 << 3usize)) | (((val as u32) & 0x07) << 3usize); - } - #[doc = "State when at least one key is registered for this page and no matching key has been entered."] - #[inline(always)] - pub const fn no_key_state(&self) -> super::vals::Page41lock0noKeyState { - let val = (self.0 >> 6usize) & 0x01; - super::vals::Page41lock0noKeyState::from_bits(val as u8) - } - #[doc = "State when at least one key is registered for this page and no matching key has been entered."] - #[inline(always)] - pub fn set_no_key_state(&mut self, val: super::vals::Page41lock0noKeyState) { - self.0 = (self.0 & !(0x01 << 6usize)) | (((val.to_bits() as u32) & 0x01) << 6usize); - } - #[doc = "Redundant copy of bits 7:0"] - #[inline(always)] - pub const fn r1(&self) -> u8 { - let val = (self.0 >> 8usize) & 0xff; - val as u8 - } - #[doc = "Redundant copy of bits 7:0"] - #[inline(always)] - pub fn set_r1(&mut self, val: u8) { - self.0 = (self.0 & !(0xff << 8usize)) | (((val as u32) & 0xff) << 8usize); - } - #[doc = "Redundant copy of bits 7:0"] - #[inline(always)] - pub const fn r2(&self) -> u8 { - let val = (self.0 >> 16usize) & 0xff; - val as u8 - } - #[doc = "Redundant copy of bits 7:0"] - #[inline(always)] - pub fn set_r2(&mut self, val: u8) { - self.0 = (self.0 & !(0xff << 16usize)) | (((val as u32) & 0xff) << 16usize); - } -} -impl Default for Page41lock0 { - #[inline(always)] - fn default() -> Page41lock0 { - Page41lock0(0) - } -} -#[doc = "Lock configuration MSBs for page 41 (rows 0xa40 through 0xa7f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions."] -#[repr(transparent)] -#[derive(Copy, Clone, Eq, PartialEq)] -pub struct Page41lock1(pub u32); -impl Page41lock1 { - #[doc = "Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers."] - #[inline(always)] - pub const fn lock_s(&self) -> super::vals::Page41lock1lockS { - let val = (self.0 >> 0usize) & 0x03; - super::vals::Page41lock1lockS::from_bits(val as u8) - } - #[doc = "Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers."] - #[inline(always)] - pub fn set_lock_s(&mut self, val: super::vals::Page41lock1lockS) { - self.0 = (self.0 & !(0x03 << 0usize)) | (((val.to_bits() as u32) & 0x03) << 0usize); - } - #[doc = "Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API."] - #[inline(always)] - pub const fn lock_ns(&self) -> super::vals::Page41lock1lockNs { - let val = (self.0 >> 2usize) & 0x03; - super::vals::Page41lock1lockNs::from_bits(val as u8) - } - #[doc = "Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API."] - #[inline(always)] - pub fn set_lock_ns(&mut self, val: super::vals::Page41lock1lockNs) { - self.0 = (self.0 & !(0x03 << 2usize)) | (((val.to_bits() as u32) & 0x03) << 2usize); - } - #[doc = "Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers."] - #[inline(always)] - pub const fn lock_bl(&self) -> super::vals::Page41lock1lockBl { - let val = (self.0 >> 4usize) & 0x03; - super::vals::Page41lock1lockBl::from_bits(val as u8) - } - #[doc = "Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers."] - #[inline(always)] - pub fn set_lock_bl(&mut self, val: super::vals::Page41lock1lockBl) { - self.0 = (self.0 & !(0x03 << 4usize)) | (((val.to_bits() as u32) & 0x03) << 4usize); - } - #[doc = "Redundant copy of bits 7:0"] - #[inline(always)] - pub const fn r1(&self) -> u8 { - let val = (self.0 >> 8usize) & 0xff; - val as u8 - } - #[doc = "Redundant copy of bits 7:0"] - #[inline(always)] - pub fn set_r1(&mut self, val: u8) { - self.0 = (self.0 & !(0xff << 8usize)) | (((val as u32) & 0xff) << 8usize); - } - #[doc = "Redundant copy of bits 7:0"] - #[inline(always)] - pub const fn r2(&self) -> u8 { - let val = (self.0 >> 16usize) & 0xff; - val as u8 - } - #[doc = "Redundant copy of bits 7:0"] - #[inline(always)] - pub fn set_r2(&mut self, val: u8) { - self.0 = (self.0 & !(0xff << 16usize)) | (((val as u32) & 0xff) << 16usize); - } -} -impl Default for Page41lock1 { - #[inline(always)] - fn default() -> Page41lock1 { - Page41lock1(0) - } -} -#[doc = "Lock configuration LSBs for page 42 (rows 0xa80 through 0xabf). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions."] -#[repr(transparent)] -#[derive(Copy, Clone, Eq, PartialEq)] -pub struct Page42lock0(pub u32); -impl Page42lock0 { - #[doc = "Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required."] - #[inline(always)] - pub const fn key_w(&self) -> u8 { - let val = (self.0 >> 0usize) & 0x07; - val as u8 - } - #[doc = "Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required."] - #[inline(always)] - pub fn set_key_w(&mut self, val: u8) { - self.0 = (self.0 & !(0x07 << 0usize)) | (((val as u32) & 0x07) << 0usize); - } - #[doc = "Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required."] - #[inline(always)] - pub const fn key_r(&self) -> u8 { - let val = (self.0 >> 3usize) & 0x07; - val as u8 - } - #[doc = "Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required."] - #[inline(always)] - pub fn set_key_r(&mut self, val: u8) { - self.0 = (self.0 & !(0x07 << 3usize)) | (((val as u32) & 0x07) << 3usize); - } - #[doc = "State when at least one key is registered for this page and no matching key has been entered."] - #[inline(always)] - pub const fn no_key_state(&self) -> super::vals::Page42lock0noKeyState { - let val = (self.0 >> 6usize) & 0x01; - super::vals::Page42lock0noKeyState::from_bits(val as u8) - } - #[doc = "State when at least one key is registered for this page and no matching key has been entered."] - #[inline(always)] - pub fn set_no_key_state(&mut self, val: super::vals::Page42lock0noKeyState) { - self.0 = (self.0 & !(0x01 << 6usize)) | (((val.to_bits() as u32) & 0x01) << 6usize); - } - #[doc = "Redundant copy of bits 7:0"] - #[inline(always)] - pub const fn r1(&self) -> u8 { - let val = (self.0 >> 8usize) & 0xff; - val as u8 - } - #[doc = "Redundant copy of bits 7:0"] - #[inline(always)] - pub fn set_r1(&mut self, val: u8) { - self.0 = (self.0 & !(0xff << 8usize)) | (((val as u32) & 0xff) << 8usize); - } - #[doc = "Redundant copy of bits 7:0"] - #[inline(always)] - pub const fn r2(&self) -> u8 { - let val = (self.0 >> 16usize) & 0xff; - val as u8 - } - #[doc = "Redundant copy of bits 7:0"] - #[inline(always)] - pub fn set_r2(&mut self, val: u8) { - self.0 = (self.0 & !(0xff << 16usize)) | (((val as u32) & 0xff) << 16usize); - } -} -impl Default for Page42lock0 { - #[inline(always)] - fn default() -> Page42lock0 { - Page42lock0(0) - } -} -#[doc = "Lock configuration MSBs for page 42 (rows 0xa80 through 0xabf). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions."] -#[repr(transparent)] -#[derive(Copy, Clone, Eq, PartialEq)] -pub struct Page42lock1(pub u32); -impl Page42lock1 { - #[doc = "Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers."] - #[inline(always)] - pub const fn lock_s(&self) -> super::vals::Page42lock1lockS { - let val = (self.0 >> 0usize) & 0x03; - super::vals::Page42lock1lockS::from_bits(val as u8) - } - #[doc = "Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers."] - #[inline(always)] - pub fn set_lock_s(&mut self, val: super::vals::Page42lock1lockS) { - self.0 = (self.0 & !(0x03 << 0usize)) | (((val.to_bits() as u32) & 0x03) << 0usize); - } - #[doc = "Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API."] - #[inline(always)] - pub const fn lock_ns(&self) -> super::vals::Page42lock1lockNs { - let val = (self.0 >> 2usize) & 0x03; - super::vals::Page42lock1lockNs::from_bits(val as u8) - } - #[doc = "Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API."] - #[inline(always)] - pub fn set_lock_ns(&mut self, val: super::vals::Page42lock1lockNs) { - self.0 = (self.0 & !(0x03 << 2usize)) | (((val.to_bits() as u32) & 0x03) << 2usize); - } - #[doc = "Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers."] - #[inline(always)] - pub const fn lock_bl(&self) -> super::vals::Page42lock1lockBl { - let val = (self.0 >> 4usize) & 0x03; - super::vals::Page42lock1lockBl::from_bits(val as u8) - } - #[doc = "Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers."] - #[inline(always)] - pub fn set_lock_bl(&mut self, val: super::vals::Page42lock1lockBl) { - self.0 = (self.0 & !(0x03 << 4usize)) | (((val.to_bits() as u32) & 0x03) << 4usize); - } - #[doc = "Redundant copy of bits 7:0"] - #[inline(always)] - pub const fn r1(&self) -> u8 { - let val = (self.0 >> 8usize) & 0xff; - val as u8 - } - #[doc = "Redundant copy of bits 7:0"] - #[inline(always)] - pub fn set_r1(&mut self, val: u8) { - self.0 = (self.0 & !(0xff << 8usize)) | (((val as u32) & 0xff) << 8usize); - } - #[doc = "Redundant copy of bits 7:0"] - #[inline(always)] - pub const fn r2(&self) -> u8 { - let val = (self.0 >> 16usize) & 0xff; - val as u8 - } - #[doc = "Redundant copy of bits 7:0"] - #[inline(always)] - pub fn set_r2(&mut self, val: u8) { - self.0 = (self.0 & !(0xff << 16usize)) | (((val as u32) & 0xff) << 16usize); - } -} -impl Default for Page42lock1 { - #[inline(always)] - fn default() -> Page42lock1 { - Page42lock1(0) - } -} -#[doc = "Lock configuration LSBs for page 43 (rows 0xac0 through 0xaff). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions."] -#[repr(transparent)] -#[derive(Copy, Clone, Eq, PartialEq)] -pub struct Page43lock0(pub u32); -impl Page43lock0 { - #[doc = "Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required."] - #[inline(always)] - pub const fn key_w(&self) -> u8 { - let val = (self.0 >> 0usize) & 0x07; - val as u8 - } - #[doc = "Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required."] - #[inline(always)] - pub fn set_key_w(&mut self, val: u8) { - self.0 = (self.0 & !(0x07 << 0usize)) | (((val as u32) & 0x07) << 0usize); - } - #[doc = "Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required."] - #[inline(always)] - pub const fn key_r(&self) -> u8 { - let val = (self.0 >> 3usize) & 0x07; - val as u8 - } - #[doc = "Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required."] - #[inline(always)] - pub fn set_key_r(&mut self, val: u8) { - self.0 = (self.0 & !(0x07 << 3usize)) | (((val as u32) & 0x07) << 3usize); - } - #[doc = "State when at least one key is registered for this page and no matching key has been entered."] - #[inline(always)] - pub const fn no_key_state(&self) -> super::vals::Page43lock0noKeyState { - let val = (self.0 >> 6usize) & 0x01; - super::vals::Page43lock0noKeyState::from_bits(val as u8) - } - #[doc = "State when at least one key is registered for this page and no matching key has been entered."] - #[inline(always)] - pub fn set_no_key_state(&mut self, val: super::vals::Page43lock0noKeyState) { - self.0 = (self.0 & !(0x01 << 6usize)) | (((val.to_bits() as u32) & 0x01) << 6usize); - } - #[doc = "Redundant copy of bits 7:0"] - #[inline(always)] - pub const fn r1(&self) -> u8 { - let val = (self.0 >> 8usize) & 0xff; - val as u8 - } - #[doc = "Redundant copy of bits 7:0"] - #[inline(always)] - pub fn set_r1(&mut self, val: u8) { - self.0 = (self.0 & !(0xff << 8usize)) | (((val as u32) & 0xff) << 8usize); - } - #[doc = "Redundant copy of bits 7:0"] - #[inline(always)] - pub const fn r2(&self) -> u8 { - let val = (self.0 >> 16usize) & 0xff; - val as u8 - } - #[doc = "Redundant copy of bits 7:0"] - #[inline(always)] - pub fn set_r2(&mut self, val: u8) { - self.0 = (self.0 & !(0xff << 16usize)) | (((val as u32) & 0xff) << 16usize); - } -} -impl Default for Page43lock0 { - #[inline(always)] - fn default() -> Page43lock0 { - Page43lock0(0) - } -} -#[doc = "Lock configuration MSBs for page 43 (rows 0xac0 through 0xaff). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions."] -#[repr(transparent)] -#[derive(Copy, Clone, Eq, PartialEq)] -pub struct Page43lock1(pub u32); -impl Page43lock1 { - #[doc = "Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers."] - #[inline(always)] - pub const fn lock_s(&self) -> super::vals::Page43lock1lockS { - let val = (self.0 >> 0usize) & 0x03; - super::vals::Page43lock1lockS::from_bits(val as u8) - } - #[doc = "Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers."] - #[inline(always)] - pub fn set_lock_s(&mut self, val: super::vals::Page43lock1lockS) { - self.0 = (self.0 & !(0x03 << 0usize)) | (((val.to_bits() as u32) & 0x03) << 0usize); - } - #[doc = "Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API."] - #[inline(always)] - pub const fn lock_ns(&self) -> super::vals::Page43lock1lockNs { - let val = (self.0 >> 2usize) & 0x03; - super::vals::Page43lock1lockNs::from_bits(val as u8) - } - #[doc = "Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API."] - #[inline(always)] - pub fn set_lock_ns(&mut self, val: super::vals::Page43lock1lockNs) { - self.0 = (self.0 & !(0x03 << 2usize)) | (((val.to_bits() as u32) & 0x03) << 2usize); - } - #[doc = "Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers."] - #[inline(always)] - pub const fn lock_bl(&self) -> super::vals::Page43lock1lockBl { - let val = (self.0 >> 4usize) & 0x03; - super::vals::Page43lock1lockBl::from_bits(val as u8) - } - #[doc = "Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers."] - #[inline(always)] - pub fn set_lock_bl(&mut self, val: super::vals::Page43lock1lockBl) { - self.0 = (self.0 & !(0x03 << 4usize)) | (((val.to_bits() as u32) & 0x03) << 4usize); - } - #[doc = "Redundant copy of bits 7:0"] - #[inline(always)] - pub const fn r1(&self) -> u8 { - let val = (self.0 >> 8usize) & 0xff; - val as u8 - } - #[doc = "Redundant copy of bits 7:0"] - #[inline(always)] - pub fn set_r1(&mut self, val: u8) { - self.0 = (self.0 & !(0xff << 8usize)) | (((val as u32) & 0xff) << 8usize); - } - #[doc = "Redundant copy of bits 7:0"] - #[inline(always)] - pub const fn r2(&self) -> u8 { - let val = (self.0 >> 16usize) & 0xff; - val as u8 - } - #[doc = "Redundant copy of bits 7:0"] - #[inline(always)] - pub fn set_r2(&mut self, val: u8) { - self.0 = (self.0 & !(0xff << 16usize)) | (((val as u32) & 0xff) << 16usize); - } -} -impl Default for Page43lock1 { - #[inline(always)] - fn default() -> Page43lock1 { - Page43lock1(0) - } -} -#[doc = "Lock configuration LSBs for page 44 (rows 0xb00 through 0xb3f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions."] -#[repr(transparent)] -#[derive(Copy, Clone, Eq, PartialEq)] -pub struct Page44lock0(pub u32); -impl Page44lock0 { - #[doc = "Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required."] - #[inline(always)] - pub const fn key_w(&self) -> u8 { - let val = (self.0 >> 0usize) & 0x07; - val as u8 - } - #[doc = "Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required."] - #[inline(always)] - pub fn set_key_w(&mut self, val: u8) { - self.0 = (self.0 & !(0x07 << 0usize)) | (((val as u32) & 0x07) << 0usize); - } - #[doc = "Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required."] - #[inline(always)] - pub const fn key_r(&self) -> u8 { - let val = (self.0 >> 3usize) & 0x07; - val as u8 - } - #[doc = "Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required."] - #[inline(always)] - pub fn set_key_r(&mut self, val: u8) { - self.0 = (self.0 & !(0x07 << 3usize)) | (((val as u32) & 0x07) << 3usize); - } - #[doc = "State when at least one key is registered for this page and no matching key has been entered."] - #[inline(always)] - pub const fn no_key_state(&self) -> super::vals::Page44lock0noKeyState { - let val = (self.0 >> 6usize) & 0x01; - super::vals::Page44lock0noKeyState::from_bits(val as u8) - } - #[doc = "State when at least one key is registered for this page and no matching key has been entered."] - #[inline(always)] - pub fn set_no_key_state(&mut self, val: super::vals::Page44lock0noKeyState) { - self.0 = (self.0 & !(0x01 << 6usize)) | (((val.to_bits() as u32) & 0x01) << 6usize); - } - #[doc = "Redundant copy of bits 7:0"] - #[inline(always)] - pub const fn r1(&self) -> u8 { - let val = (self.0 >> 8usize) & 0xff; - val as u8 - } - #[doc = "Redundant copy of bits 7:0"] - #[inline(always)] - pub fn set_r1(&mut self, val: u8) { - self.0 = (self.0 & !(0xff << 8usize)) | (((val as u32) & 0xff) << 8usize); - } - #[doc = "Redundant copy of bits 7:0"] - #[inline(always)] - pub const fn r2(&self) -> u8 { - let val = (self.0 >> 16usize) & 0xff; - val as u8 - } - #[doc = "Redundant copy of bits 7:0"] - #[inline(always)] - pub fn set_r2(&mut self, val: u8) { - self.0 = (self.0 & !(0xff << 16usize)) | (((val as u32) & 0xff) << 16usize); - } -} -impl Default for Page44lock0 { - #[inline(always)] - fn default() -> Page44lock0 { - Page44lock0(0) - } -} -#[doc = "Lock configuration MSBs for page 44 (rows 0xb00 through 0xb3f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions."] -#[repr(transparent)] -#[derive(Copy, Clone, Eq, PartialEq)] -pub struct Page44lock1(pub u32); -impl Page44lock1 { - #[doc = "Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers."] - #[inline(always)] - pub const fn lock_s(&self) -> super::vals::Page44lock1lockS { - let val = (self.0 >> 0usize) & 0x03; - super::vals::Page44lock1lockS::from_bits(val as u8) - } - #[doc = "Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers."] - #[inline(always)] - pub fn set_lock_s(&mut self, val: super::vals::Page44lock1lockS) { - self.0 = (self.0 & !(0x03 << 0usize)) | (((val.to_bits() as u32) & 0x03) << 0usize); - } - #[doc = "Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API."] - #[inline(always)] - pub const fn lock_ns(&self) -> super::vals::Page44lock1lockNs { - let val = (self.0 >> 2usize) & 0x03; - super::vals::Page44lock1lockNs::from_bits(val as u8) - } - #[doc = "Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API."] - #[inline(always)] - pub fn set_lock_ns(&mut self, val: super::vals::Page44lock1lockNs) { - self.0 = (self.0 & !(0x03 << 2usize)) | (((val.to_bits() as u32) & 0x03) << 2usize); - } - #[doc = "Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers."] - #[inline(always)] - pub const fn lock_bl(&self) -> super::vals::Page44lock1lockBl { - let val = (self.0 >> 4usize) & 0x03; - super::vals::Page44lock1lockBl::from_bits(val as u8) - } - #[doc = "Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers."] - #[inline(always)] - pub fn set_lock_bl(&mut self, val: super::vals::Page44lock1lockBl) { - self.0 = (self.0 & !(0x03 << 4usize)) | (((val.to_bits() as u32) & 0x03) << 4usize); - } - #[doc = "Redundant copy of bits 7:0"] - #[inline(always)] - pub const fn r1(&self) -> u8 { - let val = (self.0 >> 8usize) & 0xff; - val as u8 - } - #[doc = "Redundant copy of bits 7:0"] - #[inline(always)] - pub fn set_r1(&mut self, val: u8) { - self.0 = (self.0 & !(0xff << 8usize)) | (((val as u32) & 0xff) << 8usize); - } - #[doc = "Redundant copy of bits 7:0"] - #[inline(always)] - pub const fn r2(&self) -> u8 { - let val = (self.0 >> 16usize) & 0xff; - val as u8 - } - #[doc = "Redundant copy of bits 7:0"] - #[inline(always)] - pub fn set_r2(&mut self, val: u8) { - self.0 = (self.0 & !(0xff << 16usize)) | (((val as u32) & 0xff) << 16usize); - } -} -impl Default for Page44lock1 { - #[inline(always)] - fn default() -> Page44lock1 { - Page44lock1(0) - } -} -#[doc = "Lock configuration LSBs for page 45 (rows 0xb40 through 0xb7f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions."] -#[repr(transparent)] -#[derive(Copy, Clone, Eq, PartialEq)] -pub struct Page45lock0(pub u32); -impl Page45lock0 { - #[doc = "Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required."] - #[inline(always)] - pub const fn key_w(&self) -> u8 { - let val = (self.0 >> 0usize) & 0x07; - val as u8 - } - #[doc = "Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required."] - #[inline(always)] - pub fn set_key_w(&mut self, val: u8) { - self.0 = (self.0 & !(0x07 << 0usize)) | (((val as u32) & 0x07) << 0usize); - } - #[doc = "Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required."] - #[inline(always)] - pub const fn key_r(&self) -> u8 { - let val = (self.0 >> 3usize) & 0x07; - val as u8 - } - #[doc = "Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required."] - #[inline(always)] - pub fn set_key_r(&mut self, val: u8) { - self.0 = (self.0 & !(0x07 << 3usize)) | (((val as u32) & 0x07) << 3usize); - } - #[doc = "State when at least one key is registered for this page and no matching key has been entered."] - #[inline(always)] - pub const fn no_key_state(&self) -> super::vals::Page45lock0noKeyState { - let val = (self.0 >> 6usize) & 0x01; - super::vals::Page45lock0noKeyState::from_bits(val as u8) - } - #[doc = "State when at least one key is registered for this page and no matching key has been entered."] - #[inline(always)] - pub fn set_no_key_state(&mut self, val: super::vals::Page45lock0noKeyState) { - self.0 = (self.0 & !(0x01 << 6usize)) | (((val.to_bits() as u32) & 0x01) << 6usize); - } - #[doc = "Redundant copy of bits 7:0"] - #[inline(always)] - pub const fn r1(&self) -> u8 { - let val = (self.0 >> 8usize) & 0xff; - val as u8 - } - #[doc = "Redundant copy of bits 7:0"] - #[inline(always)] - pub fn set_r1(&mut self, val: u8) { - self.0 = (self.0 & !(0xff << 8usize)) | (((val as u32) & 0xff) << 8usize); - } - #[doc = "Redundant copy of bits 7:0"] - #[inline(always)] - pub const fn r2(&self) -> u8 { - let val = (self.0 >> 16usize) & 0xff; - val as u8 - } - #[doc = "Redundant copy of bits 7:0"] - #[inline(always)] - pub fn set_r2(&mut self, val: u8) { - self.0 = (self.0 & !(0xff << 16usize)) | (((val as u32) & 0xff) << 16usize); - } -} -impl Default for Page45lock0 { - #[inline(always)] - fn default() -> Page45lock0 { - Page45lock0(0) - } -} -#[doc = "Lock configuration MSBs for page 45 (rows 0xb40 through 0xb7f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions."] -#[repr(transparent)] -#[derive(Copy, Clone, Eq, PartialEq)] -pub struct Page45lock1(pub u32); -impl Page45lock1 { - #[doc = "Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers."] - #[inline(always)] - pub const fn lock_s(&self) -> super::vals::Page45lock1lockS { - let val = (self.0 >> 0usize) & 0x03; - super::vals::Page45lock1lockS::from_bits(val as u8) - } - #[doc = "Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers."] - #[inline(always)] - pub fn set_lock_s(&mut self, val: super::vals::Page45lock1lockS) { - self.0 = (self.0 & !(0x03 << 0usize)) | (((val.to_bits() as u32) & 0x03) << 0usize); - } - #[doc = "Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API."] - #[inline(always)] - pub const fn lock_ns(&self) -> super::vals::Page45lock1lockNs { - let val = (self.0 >> 2usize) & 0x03; - super::vals::Page45lock1lockNs::from_bits(val as u8) - } - #[doc = "Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API."] - #[inline(always)] - pub fn set_lock_ns(&mut self, val: super::vals::Page45lock1lockNs) { - self.0 = (self.0 & !(0x03 << 2usize)) | (((val.to_bits() as u32) & 0x03) << 2usize); - } - #[doc = "Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers."] - #[inline(always)] - pub const fn lock_bl(&self) -> super::vals::Page45lock1lockBl { - let val = (self.0 >> 4usize) & 0x03; - super::vals::Page45lock1lockBl::from_bits(val as u8) - } - #[doc = "Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers."] - #[inline(always)] - pub fn set_lock_bl(&mut self, val: super::vals::Page45lock1lockBl) { - self.0 = (self.0 & !(0x03 << 4usize)) | (((val.to_bits() as u32) & 0x03) << 4usize); - } - #[doc = "Redundant copy of bits 7:0"] - #[inline(always)] - pub const fn r1(&self) -> u8 { - let val = (self.0 >> 8usize) & 0xff; - val as u8 - } - #[doc = "Redundant copy of bits 7:0"] - #[inline(always)] - pub fn set_r1(&mut self, val: u8) { - self.0 = (self.0 & !(0xff << 8usize)) | (((val as u32) & 0xff) << 8usize); - } - #[doc = "Redundant copy of bits 7:0"] - #[inline(always)] - pub const fn r2(&self) -> u8 { - let val = (self.0 >> 16usize) & 0xff; - val as u8 - } - #[doc = "Redundant copy of bits 7:0"] - #[inline(always)] - pub fn set_r2(&mut self, val: u8) { - self.0 = (self.0 & !(0xff << 16usize)) | (((val as u32) & 0xff) << 16usize); - } -} -impl Default for Page45lock1 { - #[inline(always)] - fn default() -> Page45lock1 { - Page45lock1(0) - } -} -#[doc = "Lock configuration LSBs for page 46 (rows 0xb80 through 0xbbf). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions."] -#[repr(transparent)] -#[derive(Copy, Clone, Eq, PartialEq)] -pub struct Page46lock0(pub u32); -impl Page46lock0 { - #[doc = "Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required."] - #[inline(always)] - pub const fn key_w(&self) -> u8 { - let val = (self.0 >> 0usize) & 0x07; - val as u8 - } - #[doc = "Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required."] - #[inline(always)] - pub fn set_key_w(&mut self, val: u8) { - self.0 = (self.0 & !(0x07 << 0usize)) | (((val as u32) & 0x07) << 0usize); - } - #[doc = "Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required."] - #[inline(always)] - pub const fn key_r(&self) -> u8 { - let val = (self.0 >> 3usize) & 0x07; - val as u8 - } - #[doc = "Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required."] - #[inline(always)] - pub fn set_key_r(&mut self, val: u8) { - self.0 = (self.0 & !(0x07 << 3usize)) | (((val as u32) & 0x07) << 3usize); - } - #[doc = "State when at least one key is registered for this page and no matching key has been entered."] - #[inline(always)] - pub const fn no_key_state(&self) -> super::vals::Page46lock0noKeyState { - let val = (self.0 >> 6usize) & 0x01; - super::vals::Page46lock0noKeyState::from_bits(val as u8) - } - #[doc = "State when at least one key is registered for this page and no matching key has been entered."] - #[inline(always)] - pub fn set_no_key_state(&mut self, val: super::vals::Page46lock0noKeyState) { - self.0 = (self.0 & !(0x01 << 6usize)) | (((val.to_bits() as u32) & 0x01) << 6usize); - } - #[doc = "Redundant copy of bits 7:0"] - #[inline(always)] - pub const fn r1(&self) -> u8 { - let val = (self.0 >> 8usize) & 0xff; - val as u8 - } - #[doc = "Redundant copy of bits 7:0"] - #[inline(always)] - pub fn set_r1(&mut self, val: u8) { - self.0 = (self.0 & !(0xff << 8usize)) | (((val as u32) & 0xff) << 8usize); - } - #[doc = "Redundant copy of bits 7:0"] - #[inline(always)] - pub const fn r2(&self) -> u8 { - let val = (self.0 >> 16usize) & 0xff; - val as u8 - } - #[doc = "Redundant copy of bits 7:0"] - #[inline(always)] - pub fn set_r2(&mut self, val: u8) { - self.0 = (self.0 & !(0xff << 16usize)) | (((val as u32) & 0xff) << 16usize); - } -} -impl Default for Page46lock0 { - #[inline(always)] - fn default() -> Page46lock0 { - Page46lock0(0) - } -} -#[doc = "Lock configuration MSBs for page 46 (rows 0xb80 through 0xbbf). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions."] -#[repr(transparent)] -#[derive(Copy, Clone, Eq, PartialEq)] -pub struct Page46lock1(pub u32); -impl Page46lock1 { - #[doc = "Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers."] - #[inline(always)] - pub const fn lock_s(&self) -> super::vals::Page46lock1lockS { - let val = (self.0 >> 0usize) & 0x03; - super::vals::Page46lock1lockS::from_bits(val as u8) - } - #[doc = "Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers."] - #[inline(always)] - pub fn set_lock_s(&mut self, val: super::vals::Page46lock1lockS) { - self.0 = (self.0 & !(0x03 << 0usize)) | (((val.to_bits() as u32) & 0x03) << 0usize); - } - #[doc = "Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API."] - #[inline(always)] - pub const fn lock_ns(&self) -> super::vals::Page46lock1lockNs { - let val = (self.0 >> 2usize) & 0x03; - super::vals::Page46lock1lockNs::from_bits(val as u8) - } - #[doc = "Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API."] - #[inline(always)] - pub fn set_lock_ns(&mut self, val: super::vals::Page46lock1lockNs) { - self.0 = (self.0 & !(0x03 << 2usize)) | (((val.to_bits() as u32) & 0x03) << 2usize); - } - #[doc = "Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers."] - #[inline(always)] - pub const fn lock_bl(&self) -> super::vals::Page46lock1lockBl { - let val = (self.0 >> 4usize) & 0x03; - super::vals::Page46lock1lockBl::from_bits(val as u8) - } - #[doc = "Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers."] - #[inline(always)] - pub fn set_lock_bl(&mut self, val: super::vals::Page46lock1lockBl) { - self.0 = (self.0 & !(0x03 << 4usize)) | (((val.to_bits() as u32) & 0x03) << 4usize); - } - #[doc = "Redundant copy of bits 7:0"] - #[inline(always)] - pub const fn r1(&self) -> u8 { - let val = (self.0 >> 8usize) & 0xff; - val as u8 - } - #[doc = "Redundant copy of bits 7:0"] - #[inline(always)] - pub fn set_r1(&mut self, val: u8) { - self.0 = (self.0 & !(0xff << 8usize)) | (((val as u32) & 0xff) << 8usize); - } - #[doc = "Redundant copy of bits 7:0"] - #[inline(always)] - pub const fn r2(&self) -> u8 { - let val = (self.0 >> 16usize) & 0xff; - val as u8 - } - #[doc = "Redundant copy of bits 7:0"] - #[inline(always)] - pub fn set_r2(&mut self, val: u8) { - self.0 = (self.0 & !(0xff << 16usize)) | (((val as u32) & 0xff) << 16usize); - } -} -impl Default for Page46lock1 { - #[inline(always)] - fn default() -> Page46lock1 { - Page46lock1(0) - } -} -#[doc = "Lock configuration LSBs for page 47 (rows 0xbc0 through 0xbff). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions."] -#[repr(transparent)] -#[derive(Copy, Clone, Eq, PartialEq)] -pub struct Page47lock0(pub u32); -impl Page47lock0 { - #[doc = "Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required."] - #[inline(always)] - pub const fn key_w(&self) -> u8 { - let val = (self.0 >> 0usize) & 0x07; - val as u8 - } - #[doc = "Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required."] - #[inline(always)] - pub fn set_key_w(&mut self, val: u8) { - self.0 = (self.0 & !(0x07 << 0usize)) | (((val as u32) & 0x07) << 0usize); - } - #[doc = "Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required."] - #[inline(always)] - pub const fn key_r(&self) -> u8 { - let val = (self.0 >> 3usize) & 0x07; - val as u8 - } - #[doc = "Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required."] - #[inline(always)] - pub fn set_key_r(&mut self, val: u8) { - self.0 = (self.0 & !(0x07 << 3usize)) | (((val as u32) & 0x07) << 3usize); - } - #[doc = "State when at least one key is registered for this page and no matching key has been entered."] - #[inline(always)] - pub const fn no_key_state(&self) -> super::vals::Page47lock0noKeyState { - let val = (self.0 >> 6usize) & 0x01; - super::vals::Page47lock0noKeyState::from_bits(val as u8) - } - #[doc = "State when at least one key is registered for this page and no matching key has been entered."] - #[inline(always)] - pub fn set_no_key_state(&mut self, val: super::vals::Page47lock0noKeyState) { - self.0 = (self.0 & !(0x01 << 6usize)) | (((val.to_bits() as u32) & 0x01) << 6usize); - } - #[doc = "Redundant copy of bits 7:0"] - #[inline(always)] - pub const fn r1(&self) -> u8 { - let val = (self.0 >> 8usize) & 0xff; - val as u8 - } - #[doc = "Redundant copy of bits 7:0"] - #[inline(always)] - pub fn set_r1(&mut self, val: u8) { - self.0 = (self.0 & !(0xff << 8usize)) | (((val as u32) & 0xff) << 8usize); - } - #[doc = "Redundant copy of bits 7:0"] - #[inline(always)] - pub const fn r2(&self) -> u8 { - let val = (self.0 >> 16usize) & 0xff; - val as u8 - } - #[doc = "Redundant copy of bits 7:0"] - #[inline(always)] - pub fn set_r2(&mut self, val: u8) { - self.0 = (self.0 & !(0xff << 16usize)) | (((val as u32) & 0xff) << 16usize); - } -} -impl Default for Page47lock0 { - #[inline(always)] - fn default() -> Page47lock0 { - Page47lock0(0) - } -} -#[doc = "Lock configuration MSBs for page 47 (rows 0xbc0 through 0xbff). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions."] -#[repr(transparent)] -#[derive(Copy, Clone, Eq, PartialEq)] -pub struct Page47lock1(pub u32); -impl Page47lock1 { - #[doc = "Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers."] - #[inline(always)] - pub const fn lock_s(&self) -> super::vals::Page47lock1lockS { - let val = (self.0 >> 0usize) & 0x03; - super::vals::Page47lock1lockS::from_bits(val as u8) - } - #[doc = "Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers."] - #[inline(always)] - pub fn set_lock_s(&mut self, val: super::vals::Page47lock1lockS) { - self.0 = (self.0 & !(0x03 << 0usize)) | (((val.to_bits() as u32) & 0x03) << 0usize); - } - #[doc = "Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API."] - #[inline(always)] - pub const fn lock_ns(&self) -> super::vals::Page47lock1lockNs { - let val = (self.0 >> 2usize) & 0x03; - super::vals::Page47lock1lockNs::from_bits(val as u8) - } - #[doc = "Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API."] - #[inline(always)] - pub fn set_lock_ns(&mut self, val: super::vals::Page47lock1lockNs) { - self.0 = (self.0 & !(0x03 << 2usize)) | (((val.to_bits() as u32) & 0x03) << 2usize); - } - #[doc = "Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers."] - #[inline(always)] - pub const fn lock_bl(&self) -> super::vals::Page47lock1lockBl { - let val = (self.0 >> 4usize) & 0x03; - super::vals::Page47lock1lockBl::from_bits(val as u8) - } - #[doc = "Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers."] - #[inline(always)] - pub fn set_lock_bl(&mut self, val: super::vals::Page47lock1lockBl) { - self.0 = (self.0 & !(0x03 << 4usize)) | (((val.to_bits() as u32) & 0x03) << 4usize); - } - #[doc = "Redundant copy of bits 7:0"] - #[inline(always)] - pub const fn r1(&self) -> u8 { - let val = (self.0 >> 8usize) & 0xff; - val as u8 - } - #[doc = "Redundant copy of bits 7:0"] - #[inline(always)] - pub fn set_r1(&mut self, val: u8) { - self.0 = (self.0 & !(0xff << 8usize)) | (((val as u32) & 0xff) << 8usize); - } - #[doc = "Redundant copy of bits 7:0"] - #[inline(always)] - pub const fn r2(&self) -> u8 { - let val = (self.0 >> 16usize) & 0xff; - val as u8 - } - #[doc = "Redundant copy of bits 7:0"] - #[inline(always)] - pub fn set_r2(&mut self, val: u8) { - self.0 = (self.0 & !(0xff << 16usize)) | (((val as u32) & 0xff) << 16usize); - } -} -impl Default for Page47lock1 { - #[inline(always)] - fn default() -> Page47lock1 { - Page47lock1(0) - } -} -#[doc = "Lock configuration LSBs for page 48 (rows 0xc00 through 0xc3f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions."] -#[repr(transparent)] -#[derive(Copy, Clone, Eq, PartialEq)] -pub struct Page48lock0(pub u32); -impl Page48lock0 { - #[doc = "Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required."] - #[inline(always)] - pub const fn key_w(&self) -> u8 { - let val = (self.0 >> 0usize) & 0x07; - val as u8 - } - #[doc = "Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required."] - #[inline(always)] - pub fn set_key_w(&mut self, val: u8) { - self.0 = (self.0 & !(0x07 << 0usize)) | (((val as u32) & 0x07) << 0usize); - } - #[doc = "Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required."] - #[inline(always)] - pub const fn key_r(&self) -> u8 { - let val = (self.0 >> 3usize) & 0x07; - val as u8 - } - #[doc = "Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required."] - #[inline(always)] - pub fn set_key_r(&mut self, val: u8) { - self.0 = (self.0 & !(0x07 << 3usize)) | (((val as u32) & 0x07) << 3usize); - } - #[doc = "State when at least one key is registered for this page and no matching key has been entered."] - #[inline(always)] - pub const fn no_key_state(&self) -> super::vals::Page48lock0noKeyState { - let val = (self.0 >> 6usize) & 0x01; - super::vals::Page48lock0noKeyState::from_bits(val as u8) - } - #[doc = "State when at least one key is registered for this page and no matching key has been entered."] - #[inline(always)] - pub fn set_no_key_state(&mut self, val: super::vals::Page48lock0noKeyState) { - self.0 = (self.0 & !(0x01 << 6usize)) | (((val.to_bits() as u32) & 0x01) << 6usize); - } - #[doc = "Redundant copy of bits 7:0"] - #[inline(always)] - pub const fn r1(&self) -> u8 { - let val = (self.0 >> 8usize) & 0xff; - val as u8 - } - #[doc = "Redundant copy of bits 7:0"] - #[inline(always)] - pub fn set_r1(&mut self, val: u8) { - self.0 = (self.0 & !(0xff << 8usize)) | (((val as u32) & 0xff) << 8usize); - } - #[doc = "Redundant copy of bits 7:0"] - #[inline(always)] - pub const fn r2(&self) -> u8 { - let val = (self.0 >> 16usize) & 0xff; - val as u8 - } - #[doc = "Redundant copy of bits 7:0"] - #[inline(always)] - pub fn set_r2(&mut self, val: u8) { - self.0 = (self.0 & !(0xff << 16usize)) | (((val as u32) & 0xff) << 16usize); - } -} -impl Default for Page48lock0 { - #[inline(always)] - fn default() -> Page48lock0 { - Page48lock0(0) - } -} -#[doc = "Lock configuration MSBs for page 48 (rows 0xc00 through 0xc3f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions."] -#[repr(transparent)] -#[derive(Copy, Clone, Eq, PartialEq)] -pub struct Page48lock1(pub u32); -impl Page48lock1 { - #[doc = "Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers."] - #[inline(always)] - pub const fn lock_s(&self) -> super::vals::Page48lock1lockS { - let val = (self.0 >> 0usize) & 0x03; - super::vals::Page48lock1lockS::from_bits(val as u8) - } - #[doc = "Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers."] - #[inline(always)] - pub fn set_lock_s(&mut self, val: super::vals::Page48lock1lockS) { - self.0 = (self.0 & !(0x03 << 0usize)) | (((val.to_bits() as u32) & 0x03) << 0usize); - } - #[doc = "Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API."] - #[inline(always)] - pub const fn lock_ns(&self) -> super::vals::Page48lock1lockNs { - let val = (self.0 >> 2usize) & 0x03; - super::vals::Page48lock1lockNs::from_bits(val as u8) - } - #[doc = "Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API."] - #[inline(always)] - pub fn set_lock_ns(&mut self, val: super::vals::Page48lock1lockNs) { - self.0 = (self.0 & !(0x03 << 2usize)) | (((val.to_bits() as u32) & 0x03) << 2usize); - } - #[doc = "Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers."] - #[inline(always)] - pub const fn lock_bl(&self) -> super::vals::Page48lock1lockBl { - let val = (self.0 >> 4usize) & 0x03; - super::vals::Page48lock1lockBl::from_bits(val as u8) - } - #[doc = "Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers."] - #[inline(always)] - pub fn set_lock_bl(&mut self, val: super::vals::Page48lock1lockBl) { - self.0 = (self.0 & !(0x03 << 4usize)) | (((val.to_bits() as u32) & 0x03) << 4usize); - } - #[doc = "Redundant copy of bits 7:0"] - #[inline(always)] - pub const fn r1(&self) -> u8 { - let val = (self.0 >> 8usize) & 0xff; - val as u8 - } - #[doc = "Redundant copy of bits 7:0"] - #[inline(always)] - pub fn set_r1(&mut self, val: u8) { - self.0 = (self.0 & !(0xff << 8usize)) | (((val as u32) & 0xff) << 8usize); - } - #[doc = "Redundant copy of bits 7:0"] - #[inline(always)] - pub const fn r2(&self) -> u8 { - let val = (self.0 >> 16usize) & 0xff; - val as u8 - } - #[doc = "Redundant copy of bits 7:0"] - #[inline(always)] - pub fn set_r2(&mut self, val: u8) { - self.0 = (self.0 & !(0xff << 16usize)) | (((val as u32) & 0xff) << 16usize); - } -} -impl Default for Page48lock1 { - #[inline(always)] - fn default() -> Page48lock1 { - Page48lock1(0) - } -} -#[doc = "Lock configuration LSBs for page 49 (rows 0xc40 through 0xc7f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions."] -#[repr(transparent)] -#[derive(Copy, Clone, Eq, PartialEq)] -pub struct Page49lock0(pub u32); -impl Page49lock0 { - #[doc = "Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required."] - #[inline(always)] - pub const fn key_w(&self) -> u8 { - let val = (self.0 >> 0usize) & 0x07; - val as u8 - } - #[doc = "Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required."] - #[inline(always)] - pub fn set_key_w(&mut self, val: u8) { - self.0 = (self.0 & !(0x07 << 0usize)) | (((val as u32) & 0x07) << 0usize); - } - #[doc = "Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required."] - #[inline(always)] - pub const fn key_r(&self) -> u8 { - let val = (self.0 >> 3usize) & 0x07; - val as u8 - } - #[doc = "Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required."] - #[inline(always)] - pub fn set_key_r(&mut self, val: u8) { - self.0 = (self.0 & !(0x07 << 3usize)) | (((val as u32) & 0x07) << 3usize); - } - #[doc = "State when at least one key is registered for this page and no matching key has been entered."] - #[inline(always)] - pub const fn no_key_state(&self) -> super::vals::Page49lock0noKeyState { - let val = (self.0 >> 6usize) & 0x01; - super::vals::Page49lock0noKeyState::from_bits(val as u8) - } - #[doc = "State when at least one key is registered for this page and no matching key has been entered."] - #[inline(always)] - pub fn set_no_key_state(&mut self, val: super::vals::Page49lock0noKeyState) { - self.0 = (self.0 & !(0x01 << 6usize)) | (((val.to_bits() as u32) & 0x01) << 6usize); - } - #[doc = "Redundant copy of bits 7:0"] - #[inline(always)] - pub const fn r1(&self) -> u8 { - let val = (self.0 >> 8usize) & 0xff; - val as u8 - } - #[doc = "Redundant copy of bits 7:0"] - #[inline(always)] - pub fn set_r1(&mut self, val: u8) { - self.0 = (self.0 & !(0xff << 8usize)) | (((val as u32) & 0xff) << 8usize); - } - #[doc = "Redundant copy of bits 7:0"] - #[inline(always)] - pub const fn r2(&self) -> u8 { - let val = (self.0 >> 16usize) & 0xff; - val as u8 - } - #[doc = "Redundant copy of bits 7:0"] - #[inline(always)] - pub fn set_r2(&mut self, val: u8) { - self.0 = (self.0 & !(0xff << 16usize)) | (((val as u32) & 0xff) << 16usize); - } -} -impl Default for Page49lock0 { - #[inline(always)] - fn default() -> Page49lock0 { - Page49lock0(0) - } -} -#[doc = "Lock configuration MSBs for page 49 (rows 0xc40 through 0xc7f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions."] -#[repr(transparent)] -#[derive(Copy, Clone, Eq, PartialEq)] -pub struct Page49lock1(pub u32); -impl Page49lock1 { - #[doc = "Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers."] - #[inline(always)] - pub const fn lock_s(&self) -> super::vals::Page49lock1lockS { - let val = (self.0 >> 0usize) & 0x03; - super::vals::Page49lock1lockS::from_bits(val as u8) - } - #[doc = "Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers."] - #[inline(always)] - pub fn set_lock_s(&mut self, val: super::vals::Page49lock1lockS) { - self.0 = (self.0 & !(0x03 << 0usize)) | (((val.to_bits() as u32) & 0x03) << 0usize); - } - #[doc = "Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API."] - #[inline(always)] - pub const fn lock_ns(&self) -> super::vals::Page49lock1lockNs { - let val = (self.0 >> 2usize) & 0x03; - super::vals::Page49lock1lockNs::from_bits(val as u8) - } - #[doc = "Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API."] - #[inline(always)] - pub fn set_lock_ns(&mut self, val: super::vals::Page49lock1lockNs) { - self.0 = (self.0 & !(0x03 << 2usize)) | (((val.to_bits() as u32) & 0x03) << 2usize); - } - #[doc = "Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers."] - #[inline(always)] - pub const fn lock_bl(&self) -> super::vals::Page49lock1lockBl { - let val = (self.0 >> 4usize) & 0x03; - super::vals::Page49lock1lockBl::from_bits(val as u8) - } - #[doc = "Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers."] - #[inline(always)] - pub fn set_lock_bl(&mut self, val: super::vals::Page49lock1lockBl) { - self.0 = (self.0 & !(0x03 << 4usize)) | (((val.to_bits() as u32) & 0x03) << 4usize); - } - #[doc = "Redundant copy of bits 7:0"] - #[inline(always)] - pub const fn r1(&self) -> u8 { - let val = (self.0 >> 8usize) & 0xff; - val as u8 - } - #[doc = "Redundant copy of bits 7:0"] - #[inline(always)] - pub fn set_r1(&mut self, val: u8) { - self.0 = (self.0 & !(0xff << 8usize)) | (((val as u32) & 0xff) << 8usize); - } - #[doc = "Redundant copy of bits 7:0"] - #[inline(always)] - pub const fn r2(&self) -> u8 { - let val = (self.0 >> 16usize) & 0xff; - val as u8 - } - #[doc = "Redundant copy of bits 7:0"] - #[inline(always)] - pub fn set_r2(&mut self, val: u8) { - self.0 = (self.0 & !(0xff << 16usize)) | (((val as u32) & 0xff) << 16usize); - } -} -impl Default for Page49lock1 { - #[inline(always)] - fn default() -> Page49lock1 { - Page49lock1(0) - } -} -#[doc = "Lock configuration LSBs for page 4 (rows 0x100 through 0x13f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions."] -#[repr(transparent)] -#[derive(Copy, Clone, Eq, PartialEq)] -pub struct Page4lock0(pub u32); -impl Page4lock0 { - #[doc = "Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required."] - #[inline(always)] - pub const fn key_w(&self) -> u8 { - let val = (self.0 >> 0usize) & 0x07; - val as u8 - } - #[doc = "Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required."] - #[inline(always)] - pub fn set_key_w(&mut self, val: u8) { - self.0 = (self.0 & !(0x07 << 0usize)) | (((val as u32) & 0x07) << 0usize); - } - #[doc = "Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required."] - #[inline(always)] - pub const fn key_r(&self) -> u8 { - let val = (self.0 >> 3usize) & 0x07; - val as u8 - } - #[doc = "Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required."] - #[inline(always)] - pub fn set_key_r(&mut self, val: u8) { - self.0 = (self.0 & !(0x07 << 3usize)) | (((val as u32) & 0x07) << 3usize); - } - #[doc = "State when at least one key is registered for this page and no matching key has been entered."] - #[inline(always)] - pub const fn no_key_state(&self) -> super::vals::Page4lock0noKeyState { - let val = (self.0 >> 6usize) & 0x01; - super::vals::Page4lock0noKeyState::from_bits(val as u8) - } - #[doc = "State when at least one key is registered for this page and no matching key has been entered."] - #[inline(always)] - pub fn set_no_key_state(&mut self, val: super::vals::Page4lock0noKeyState) { - self.0 = (self.0 & !(0x01 << 6usize)) | (((val.to_bits() as u32) & 0x01) << 6usize); - } - #[doc = "Redundant copy of bits 7:0"] - #[inline(always)] - pub const fn r1(&self) -> u8 { - let val = (self.0 >> 8usize) & 0xff; - val as u8 - } - #[doc = "Redundant copy of bits 7:0"] - #[inline(always)] - pub fn set_r1(&mut self, val: u8) { - self.0 = (self.0 & !(0xff << 8usize)) | (((val as u32) & 0xff) << 8usize); - } - #[doc = "Redundant copy of bits 7:0"] - #[inline(always)] - pub const fn r2(&self) -> u8 { - let val = (self.0 >> 16usize) & 0xff; - val as u8 - } - #[doc = "Redundant copy of bits 7:0"] - #[inline(always)] - pub fn set_r2(&mut self, val: u8) { - self.0 = (self.0 & !(0xff << 16usize)) | (((val as u32) & 0xff) << 16usize); - } -} -impl Default for Page4lock0 { - #[inline(always)] - fn default() -> Page4lock0 { - Page4lock0(0) - } -} -#[doc = "Lock configuration MSBs for page 4 (rows 0x100 through 0x13f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions."] -#[repr(transparent)] -#[derive(Copy, Clone, Eq, PartialEq)] -pub struct Page4lock1(pub u32); -impl Page4lock1 { - #[doc = "Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers."] - #[inline(always)] - pub const fn lock_s(&self) -> super::vals::Page4lock1lockS { - let val = (self.0 >> 0usize) & 0x03; - super::vals::Page4lock1lockS::from_bits(val as u8) - } - #[doc = "Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers."] - #[inline(always)] - pub fn set_lock_s(&mut self, val: super::vals::Page4lock1lockS) { - self.0 = (self.0 & !(0x03 << 0usize)) | (((val.to_bits() as u32) & 0x03) << 0usize); - } - #[doc = "Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API."] - #[inline(always)] - pub const fn lock_ns(&self) -> super::vals::Page4lock1lockNs { - let val = (self.0 >> 2usize) & 0x03; - super::vals::Page4lock1lockNs::from_bits(val as u8) - } - #[doc = "Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API."] - #[inline(always)] - pub fn set_lock_ns(&mut self, val: super::vals::Page4lock1lockNs) { - self.0 = (self.0 & !(0x03 << 2usize)) | (((val.to_bits() as u32) & 0x03) << 2usize); - } - #[doc = "Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers."] - #[inline(always)] - pub const fn lock_bl(&self) -> super::vals::Page4lock1lockBl { - let val = (self.0 >> 4usize) & 0x03; - super::vals::Page4lock1lockBl::from_bits(val as u8) - } - #[doc = "Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers."] - #[inline(always)] - pub fn set_lock_bl(&mut self, val: super::vals::Page4lock1lockBl) { - self.0 = (self.0 & !(0x03 << 4usize)) | (((val.to_bits() as u32) & 0x03) << 4usize); - } - #[doc = "Redundant copy of bits 7:0"] - #[inline(always)] - pub const fn r1(&self) -> u8 { - let val = (self.0 >> 8usize) & 0xff; - val as u8 - } - #[doc = "Redundant copy of bits 7:0"] - #[inline(always)] - pub fn set_r1(&mut self, val: u8) { - self.0 = (self.0 & !(0xff << 8usize)) | (((val as u32) & 0xff) << 8usize); - } - #[doc = "Redundant copy of bits 7:0"] - #[inline(always)] - pub const fn r2(&self) -> u8 { - let val = (self.0 >> 16usize) & 0xff; - val as u8 - } - #[doc = "Redundant copy of bits 7:0"] - #[inline(always)] - pub fn set_r2(&mut self, val: u8) { - self.0 = (self.0 & !(0xff << 16usize)) | (((val as u32) & 0xff) << 16usize); - } -} -impl Default for Page4lock1 { - #[inline(always)] - fn default() -> Page4lock1 { - Page4lock1(0) - } -} -#[doc = "Lock configuration LSBs for page 50 (rows 0xc80 through 0xcbf). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions."] -#[repr(transparent)] -#[derive(Copy, Clone, Eq, PartialEq)] -pub struct Page50lock0(pub u32); -impl Page50lock0 { - #[doc = "Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required."] - #[inline(always)] - pub const fn key_w(&self) -> u8 { - let val = (self.0 >> 0usize) & 0x07; - val as u8 - } - #[doc = "Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required."] - #[inline(always)] - pub fn set_key_w(&mut self, val: u8) { - self.0 = (self.0 & !(0x07 << 0usize)) | (((val as u32) & 0x07) << 0usize); - } - #[doc = "Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required."] - #[inline(always)] - pub const fn key_r(&self) -> u8 { - let val = (self.0 >> 3usize) & 0x07; - val as u8 - } - #[doc = "Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required."] - #[inline(always)] - pub fn set_key_r(&mut self, val: u8) { - self.0 = (self.0 & !(0x07 << 3usize)) | (((val as u32) & 0x07) << 3usize); - } - #[doc = "State when at least one key is registered for this page and no matching key has been entered."] - #[inline(always)] - pub const fn no_key_state(&self) -> super::vals::Page50lock0noKeyState { - let val = (self.0 >> 6usize) & 0x01; - super::vals::Page50lock0noKeyState::from_bits(val as u8) - } - #[doc = "State when at least one key is registered for this page and no matching key has been entered."] - #[inline(always)] - pub fn set_no_key_state(&mut self, val: super::vals::Page50lock0noKeyState) { - self.0 = (self.0 & !(0x01 << 6usize)) | (((val.to_bits() as u32) & 0x01) << 6usize); - } - #[doc = "Redundant copy of bits 7:0"] - #[inline(always)] - pub const fn r1(&self) -> u8 { - let val = (self.0 >> 8usize) & 0xff; - val as u8 - } - #[doc = "Redundant copy of bits 7:0"] - #[inline(always)] - pub fn set_r1(&mut self, val: u8) { - self.0 = (self.0 & !(0xff << 8usize)) | (((val as u32) & 0xff) << 8usize); - } - #[doc = "Redundant copy of bits 7:0"] - #[inline(always)] - pub const fn r2(&self) -> u8 { - let val = (self.0 >> 16usize) & 0xff; - val as u8 - } - #[doc = "Redundant copy of bits 7:0"] - #[inline(always)] - pub fn set_r2(&mut self, val: u8) { - self.0 = (self.0 & !(0xff << 16usize)) | (((val as u32) & 0xff) << 16usize); - } -} -impl Default for Page50lock0 { - #[inline(always)] - fn default() -> Page50lock0 { - Page50lock0(0) - } -} -#[doc = "Lock configuration MSBs for page 50 (rows 0xc80 through 0xcbf). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions."] -#[repr(transparent)] -#[derive(Copy, Clone, Eq, PartialEq)] -pub struct Page50lock1(pub u32); -impl Page50lock1 { - #[doc = "Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers."] - #[inline(always)] - pub const fn lock_s(&self) -> super::vals::Page50lock1lockS { - let val = (self.0 >> 0usize) & 0x03; - super::vals::Page50lock1lockS::from_bits(val as u8) - } - #[doc = "Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers."] - #[inline(always)] - pub fn set_lock_s(&mut self, val: super::vals::Page50lock1lockS) { - self.0 = (self.0 & !(0x03 << 0usize)) | (((val.to_bits() as u32) & 0x03) << 0usize); - } - #[doc = "Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API."] - #[inline(always)] - pub const fn lock_ns(&self) -> super::vals::Page50lock1lockNs { - let val = (self.0 >> 2usize) & 0x03; - super::vals::Page50lock1lockNs::from_bits(val as u8) - } - #[doc = "Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API."] - #[inline(always)] - pub fn set_lock_ns(&mut self, val: super::vals::Page50lock1lockNs) { - self.0 = (self.0 & !(0x03 << 2usize)) | (((val.to_bits() as u32) & 0x03) << 2usize); - } - #[doc = "Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers."] - #[inline(always)] - pub const fn lock_bl(&self) -> super::vals::Page50lock1lockBl { - let val = (self.0 >> 4usize) & 0x03; - super::vals::Page50lock1lockBl::from_bits(val as u8) - } - #[doc = "Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers."] - #[inline(always)] - pub fn set_lock_bl(&mut self, val: super::vals::Page50lock1lockBl) { - self.0 = (self.0 & !(0x03 << 4usize)) | (((val.to_bits() as u32) & 0x03) << 4usize); - } - #[doc = "Redundant copy of bits 7:0"] - #[inline(always)] - pub const fn r1(&self) -> u8 { - let val = (self.0 >> 8usize) & 0xff; - val as u8 - } - #[doc = "Redundant copy of bits 7:0"] - #[inline(always)] - pub fn set_r1(&mut self, val: u8) { - self.0 = (self.0 & !(0xff << 8usize)) | (((val as u32) & 0xff) << 8usize); - } - #[doc = "Redundant copy of bits 7:0"] - #[inline(always)] - pub const fn r2(&self) -> u8 { - let val = (self.0 >> 16usize) & 0xff; - val as u8 - } - #[doc = "Redundant copy of bits 7:0"] - #[inline(always)] - pub fn set_r2(&mut self, val: u8) { - self.0 = (self.0 & !(0xff << 16usize)) | (((val as u32) & 0xff) << 16usize); - } -} -impl Default for Page50lock1 { - #[inline(always)] - fn default() -> Page50lock1 { - Page50lock1(0) - } -} -#[doc = "Lock configuration LSBs for page 51 (rows 0xcc0 through 0xcff). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions."] -#[repr(transparent)] -#[derive(Copy, Clone, Eq, PartialEq)] -pub struct Page51lock0(pub u32); -impl Page51lock0 { - #[doc = "Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required."] - #[inline(always)] - pub const fn key_w(&self) -> u8 { - let val = (self.0 >> 0usize) & 0x07; - val as u8 - } - #[doc = "Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required."] - #[inline(always)] - pub fn set_key_w(&mut self, val: u8) { - self.0 = (self.0 & !(0x07 << 0usize)) | (((val as u32) & 0x07) << 0usize); - } - #[doc = "Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required."] - #[inline(always)] - pub const fn key_r(&self) -> u8 { - let val = (self.0 >> 3usize) & 0x07; - val as u8 - } - #[doc = "Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required."] - #[inline(always)] - pub fn set_key_r(&mut self, val: u8) { - self.0 = (self.0 & !(0x07 << 3usize)) | (((val as u32) & 0x07) << 3usize); - } - #[doc = "State when at least one key is registered for this page and no matching key has been entered."] - #[inline(always)] - pub const fn no_key_state(&self) -> super::vals::Page51lock0noKeyState { - let val = (self.0 >> 6usize) & 0x01; - super::vals::Page51lock0noKeyState::from_bits(val as u8) - } - #[doc = "State when at least one key is registered for this page and no matching key has been entered."] - #[inline(always)] - pub fn set_no_key_state(&mut self, val: super::vals::Page51lock0noKeyState) { - self.0 = (self.0 & !(0x01 << 6usize)) | (((val.to_bits() as u32) & 0x01) << 6usize); - } - #[doc = "Redundant copy of bits 7:0"] - #[inline(always)] - pub const fn r1(&self) -> u8 { - let val = (self.0 >> 8usize) & 0xff; - val as u8 - } - #[doc = "Redundant copy of bits 7:0"] - #[inline(always)] - pub fn set_r1(&mut self, val: u8) { - self.0 = (self.0 & !(0xff << 8usize)) | (((val as u32) & 0xff) << 8usize); - } - #[doc = "Redundant copy of bits 7:0"] - #[inline(always)] - pub const fn r2(&self) -> u8 { - let val = (self.0 >> 16usize) & 0xff; - val as u8 - } - #[doc = "Redundant copy of bits 7:0"] - #[inline(always)] - pub fn set_r2(&mut self, val: u8) { - self.0 = (self.0 & !(0xff << 16usize)) | (((val as u32) & 0xff) << 16usize); - } -} -impl Default for Page51lock0 { - #[inline(always)] - fn default() -> Page51lock0 { - Page51lock0(0) - } -} -#[doc = "Lock configuration MSBs for page 51 (rows 0xcc0 through 0xcff). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions."] -#[repr(transparent)] -#[derive(Copy, Clone, Eq, PartialEq)] -pub struct Page51lock1(pub u32); -impl Page51lock1 { - #[doc = "Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers."] - #[inline(always)] - pub const fn lock_s(&self) -> super::vals::Page51lock1lockS { - let val = (self.0 >> 0usize) & 0x03; - super::vals::Page51lock1lockS::from_bits(val as u8) - } - #[doc = "Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers."] - #[inline(always)] - pub fn set_lock_s(&mut self, val: super::vals::Page51lock1lockS) { - self.0 = (self.0 & !(0x03 << 0usize)) | (((val.to_bits() as u32) & 0x03) << 0usize); - } - #[doc = "Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API."] - #[inline(always)] - pub const fn lock_ns(&self) -> super::vals::Page51lock1lockNs { - let val = (self.0 >> 2usize) & 0x03; - super::vals::Page51lock1lockNs::from_bits(val as u8) - } - #[doc = "Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API."] - #[inline(always)] - pub fn set_lock_ns(&mut self, val: super::vals::Page51lock1lockNs) { - self.0 = (self.0 & !(0x03 << 2usize)) | (((val.to_bits() as u32) & 0x03) << 2usize); - } - #[doc = "Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers."] - #[inline(always)] - pub const fn lock_bl(&self) -> super::vals::Page51lock1lockBl { - let val = (self.0 >> 4usize) & 0x03; - super::vals::Page51lock1lockBl::from_bits(val as u8) - } - #[doc = "Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers."] - #[inline(always)] - pub fn set_lock_bl(&mut self, val: super::vals::Page51lock1lockBl) { - self.0 = (self.0 & !(0x03 << 4usize)) | (((val.to_bits() as u32) & 0x03) << 4usize); - } - #[doc = "Redundant copy of bits 7:0"] - #[inline(always)] - pub const fn r1(&self) -> u8 { - let val = (self.0 >> 8usize) & 0xff; - val as u8 - } - #[doc = "Redundant copy of bits 7:0"] - #[inline(always)] - pub fn set_r1(&mut self, val: u8) { - self.0 = (self.0 & !(0xff << 8usize)) | (((val as u32) & 0xff) << 8usize); - } - #[doc = "Redundant copy of bits 7:0"] - #[inline(always)] - pub const fn r2(&self) -> u8 { - let val = (self.0 >> 16usize) & 0xff; - val as u8 - } - #[doc = "Redundant copy of bits 7:0"] - #[inline(always)] - pub fn set_r2(&mut self, val: u8) { - self.0 = (self.0 & !(0xff << 16usize)) | (((val as u32) & 0xff) << 16usize); - } -} -impl Default for Page51lock1 { - #[inline(always)] - fn default() -> Page51lock1 { - Page51lock1(0) - } -} -#[doc = "Lock configuration LSBs for page 52 (rows 0xd00 through 0xd3f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions."] -#[repr(transparent)] -#[derive(Copy, Clone, Eq, PartialEq)] -pub struct Page52lock0(pub u32); -impl Page52lock0 { - #[doc = "Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required."] - #[inline(always)] - pub const fn key_w(&self) -> u8 { - let val = (self.0 >> 0usize) & 0x07; - val as u8 - } - #[doc = "Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required."] - #[inline(always)] - pub fn set_key_w(&mut self, val: u8) { - self.0 = (self.0 & !(0x07 << 0usize)) | (((val as u32) & 0x07) << 0usize); - } - #[doc = "Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required."] - #[inline(always)] - pub const fn key_r(&self) -> u8 { - let val = (self.0 >> 3usize) & 0x07; - val as u8 - } - #[doc = "Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required."] - #[inline(always)] - pub fn set_key_r(&mut self, val: u8) { - self.0 = (self.0 & !(0x07 << 3usize)) | (((val as u32) & 0x07) << 3usize); - } - #[doc = "State when at least one key is registered for this page and no matching key has been entered."] - #[inline(always)] - pub const fn no_key_state(&self) -> super::vals::Page52lock0noKeyState { - let val = (self.0 >> 6usize) & 0x01; - super::vals::Page52lock0noKeyState::from_bits(val as u8) - } - #[doc = "State when at least one key is registered for this page and no matching key has been entered."] - #[inline(always)] - pub fn set_no_key_state(&mut self, val: super::vals::Page52lock0noKeyState) { - self.0 = (self.0 & !(0x01 << 6usize)) | (((val.to_bits() as u32) & 0x01) << 6usize); - } - #[doc = "Redundant copy of bits 7:0"] - #[inline(always)] - pub const fn r1(&self) -> u8 { - let val = (self.0 >> 8usize) & 0xff; - val as u8 - } - #[doc = "Redundant copy of bits 7:0"] - #[inline(always)] - pub fn set_r1(&mut self, val: u8) { - self.0 = (self.0 & !(0xff << 8usize)) | (((val as u32) & 0xff) << 8usize); - } - #[doc = "Redundant copy of bits 7:0"] - #[inline(always)] - pub const fn r2(&self) -> u8 { - let val = (self.0 >> 16usize) & 0xff; - val as u8 - } - #[doc = "Redundant copy of bits 7:0"] - #[inline(always)] - pub fn set_r2(&mut self, val: u8) { - self.0 = (self.0 & !(0xff << 16usize)) | (((val as u32) & 0xff) << 16usize); - } -} -impl Default for Page52lock0 { - #[inline(always)] - fn default() -> Page52lock0 { - Page52lock0(0) - } -} -#[doc = "Lock configuration MSBs for page 52 (rows 0xd00 through 0xd3f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions."] -#[repr(transparent)] -#[derive(Copy, Clone, Eq, PartialEq)] -pub struct Page52lock1(pub u32); -impl Page52lock1 { - #[doc = "Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers."] - #[inline(always)] - pub const fn lock_s(&self) -> super::vals::Page52lock1lockS { - let val = (self.0 >> 0usize) & 0x03; - super::vals::Page52lock1lockS::from_bits(val as u8) - } - #[doc = "Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers."] - #[inline(always)] - pub fn set_lock_s(&mut self, val: super::vals::Page52lock1lockS) { - self.0 = (self.0 & !(0x03 << 0usize)) | (((val.to_bits() as u32) & 0x03) << 0usize); - } - #[doc = "Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API."] - #[inline(always)] - pub const fn lock_ns(&self) -> super::vals::Page52lock1lockNs { - let val = (self.0 >> 2usize) & 0x03; - super::vals::Page52lock1lockNs::from_bits(val as u8) - } - #[doc = "Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API."] - #[inline(always)] - pub fn set_lock_ns(&mut self, val: super::vals::Page52lock1lockNs) { - self.0 = (self.0 & !(0x03 << 2usize)) | (((val.to_bits() as u32) & 0x03) << 2usize); - } - #[doc = "Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers."] - #[inline(always)] - pub const fn lock_bl(&self) -> super::vals::Page52lock1lockBl { - let val = (self.0 >> 4usize) & 0x03; - super::vals::Page52lock1lockBl::from_bits(val as u8) - } - #[doc = "Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers."] - #[inline(always)] - pub fn set_lock_bl(&mut self, val: super::vals::Page52lock1lockBl) { - self.0 = (self.0 & !(0x03 << 4usize)) | (((val.to_bits() as u32) & 0x03) << 4usize); - } - #[doc = "Redundant copy of bits 7:0"] - #[inline(always)] - pub const fn r1(&self) -> u8 { - let val = (self.0 >> 8usize) & 0xff; - val as u8 - } - #[doc = "Redundant copy of bits 7:0"] - #[inline(always)] - pub fn set_r1(&mut self, val: u8) { - self.0 = (self.0 & !(0xff << 8usize)) | (((val as u32) & 0xff) << 8usize); - } - #[doc = "Redundant copy of bits 7:0"] - #[inline(always)] - pub const fn r2(&self) -> u8 { - let val = (self.0 >> 16usize) & 0xff; - val as u8 - } - #[doc = "Redundant copy of bits 7:0"] - #[inline(always)] - pub fn set_r2(&mut self, val: u8) { - self.0 = (self.0 & !(0xff << 16usize)) | (((val as u32) & 0xff) << 16usize); - } -} -impl Default for Page52lock1 { - #[inline(always)] - fn default() -> Page52lock1 { - Page52lock1(0) - } -} -#[doc = "Lock configuration LSBs for page 53 (rows 0xd40 through 0xd7f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions."] -#[repr(transparent)] -#[derive(Copy, Clone, Eq, PartialEq)] -pub struct Page53lock0(pub u32); -impl Page53lock0 { - #[doc = "Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required."] - #[inline(always)] - pub const fn key_w(&self) -> u8 { - let val = (self.0 >> 0usize) & 0x07; - val as u8 - } - #[doc = "Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required."] - #[inline(always)] - pub fn set_key_w(&mut self, val: u8) { - self.0 = (self.0 & !(0x07 << 0usize)) | (((val as u32) & 0x07) << 0usize); - } - #[doc = "Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required."] - #[inline(always)] - pub const fn key_r(&self) -> u8 { - let val = (self.0 >> 3usize) & 0x07; - val as u8 - } - #[doc = "Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required."] - #[inline(always)] - pub fn set_key_r(&mut self, val: u8) { - self.0 = (self.0 & !(0x07 << 3usize)) | (((val as u32) & 0x07) << 3usize); - } - #[doc = "State when at least one key is registered for this page and no matching key has been entered."] - #[inline(always)] - pub const fn no_key_state(&self) -> super::vals::Page53lock0noKeyState { - let val = (self.0 >> 6usize) & 0x01; - super::vals::Page53lock0noKeyState::from_bits(val as u8) - } - #[doc = "State when at least one key is registered for this page and no matching key has been entered."] - #[inline(always)] - pub fn set_no_key_state(&mut self, val: super::vals::Page53lock0noKeyState) { - self.0 = (self.0 & !(0x01 << 6usize)) | (((val.to_bits() as u32) & 0x01) << 6usize); - } - #[doc = "Redundant copy of bits 7:0"] - #[inline(always)] - pub const fn r1(&self) -> u8 { - let val = (self.0 >> 8usize) & 0xff; - val as u8 - } - #[doc = "Redundant copy of bits 7:0"] - #[inline(always)] - pub fn set_r1(&mut self, val: u8) { - self.0 = (self.0 & !(0xff << 8usize)) | (((val as u32) & 0xff) << 8usize); - } - #[doc = "Redundant copy of bits 7:0"] - #[inline(always)] - pub const fn r2(&self) -> u8 { - let val = (self.0 >> 16usize) & 0xff; - val as u8 - } - #[doc = "Redundant copy of bits 7:0"] - #[inline(always)] - pub fn set_r2(&mut self, val: u8) { - self.0 = (self.0 & !(0xff << 16usize)) | (((val as u32) & 0xff) << 16usize); - } -} -impl Default for Page53lock0 { - #[inline(always)] - fn default() -> Page53lock0 { - Page53lock0(0) - } -} -#[doc = "Lock configuration MSBs for page 53 (rows 0xd40 through 0xd7f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions."] -#[repr(transparent)] -#[derive(Copy, Clone, Eq, PartialEq)] -pub struct Page53lock1(pub u32); -impl Page53lock1 { - #[doc = "Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers."] - #[inline(always)] - pub const fn lock_s(&self) -> super::vals::Page53lock1lockS { - let val = (self.0 >> 0usize) & 0x03; - super::vals::Page53lock1lockS::from_bits(val as u8) - } - #[doc = "Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers."] - #[inline(always)] - pub fn set_lock_s(&mut self, val: super::vals::Page53lock1lockS) { - self.0 = (self.0 & !(0x03 << 0usize)) | (((val.to_bits() as u32) & 0x03) << 0usize); - } - #[doc = "Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API."] - #[inline(always)] - pub const fn lock_ns(&self) -> super::vals::Page53lock1lockNs { - let val = (self.0 >> 2usize) & 0x03; - super::vals::Page53lock1lockNs::from_bits(val as u8) - } - #[doc = "Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API."] - #[inline(always)] - pub fn set_lock_ns(&mut self, val: super::vals::Page53lock1lockNs) { - self.0 = (self.0 & !(0x03 << 2usize)) | (((val.to_bits() as u32) & 0x03) << 2usize); - } - #[doc = "Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers."] - #[inline(always)] - pub const fn lock_bl(&self) -> super::vals::Page53lock1lockBl { - let val = (self.0 >> 4usize) & 0x03; - super::vals::Page53lock1lockBl::from_bits(val as u8) - } - #[doc = "Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers."] - #[inline(always)] - pub fn set_lock_bl(&mut self, val: super::vals::Page53lock1lockBl) { - self.0 = (self.0 & !(0x03 << 4usize)) | (((val.to_bits() as u32) & 0x03) << 4usize); - } - #[doc = "Redundant copy of bits 7:0"] - #[inline(always)] - pub const fn r1(&self) -> u8 { - let val = (self.0 >> 8usize) & 0xff; - val as u8 - } - #[doc = "Redundant copy of bits 7:0"] - #[inline(always)] - pub fn set_r1(&mut self, val: u8) { - self.0 = (self.0 & !(0xff << 8usize)) | (((val as u32) & 0xff) << 8usize); - } - #[doc = "Redundant copy of bits 7:0"] - #[inline(always)] - pub const fn r2(&self) -> u8 { - let val = (self.0 >> 16usize) & 0xff; - val as u8 - } - #[doc = "Redundant copy of bits 7:0"] - #[inline(always)] - pub fn set_r2(&mut self, val: u8) { - self.0 = (self.0 & !(0xff << 16usize)) | (((val as u32) & 0xff) << 16usize); - } -} -impl Default for Page53lock1 { - #[inline(always)] - fn default() -> Page53lock1 { - Page53lock1(0) - } -} -#[doc = "Lock configuration LSBs for page 54 (rows 0xd80 through 0xdbf). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions."] -#[repr(transparent)] -#[derive(Copy, Clone, Eq, PartialEq)] -pub struct Page54lock0(pub u32); -impl Page54lock0 { - #[doc = "Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required."] - #[inline(always)] - pub const fn key_w(&self) -> u8 { - let val = (self.0 >> 0usize) & 0x07; - val as u8 - } - #[doc = "Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required."] - #[inline(always)] - pub fn set_key_w(&mut self, val: u8) { - self.0 = (self.0 & !(0x07 << 0usize)) | (((val as u32) & 0x07) << 0usize); - } - #[doc = "Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required."] - #[inline(always)] - pub const fn key_r(&self) -> u8 { - let val = (self.0 >> 3usize) & 0x07; - val as u8 - } - #[doc = "Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required."] - #[inline(always)] - pub fn set_key_r(&mut self, val: u8) { - self.0 = (self.0 & !(0x07 << 3usize)) | (((val as u32) & 0x07) << 3usize); - } - #[doc = "State when at least one key is registered for this page and no matching key has been entered."] - #[inline(always)] - pub const fn no_key_state(&self) -> super::vals::Page54lock0noKeyState { - let val = (self.0 >> 6usize) & 0x01; - super::vals::Page54lock0noKeyState::from_bits(val as u8) - } - #[doc = "State when at least one key is registered for this page and no matching key has been entered."] - #[inline(always)] - pub fn set_no_key_state(&mut self, val: super::vals::Page54lock0noKeyState) { - self.0 = (self.0 & !(0x01 << 6usize)) | (((val.to_bits() as u32) & 0x01) << 6usize); - } - #[doc = "Redundant copy of bits 7:0"] - #[inline(always)] - pub const fn r1(&self) -> u8 { - let val = (self.0 >> 8usize) & 0xff; - val as u8 - } - #[doc = "Redundant copy of bits 7:0"] - #[inline(always)] - pub fn set_r1(&mut self, val: u8) { - self.0 = (self.0 & !(0xff << 8usize)) | (((val as u32) & 0xff) << 8usize); - } - #[doc = "Redundant copy of bits 7:0"] - #[inline(always)] - pub const fn r2(&self) -> u8 { - let val = (self.0 >> 16usize) & 0xff; - val as u8 - } - #[doc = "Redundant copy of bits 7:0"] - #[inline(always)] - pub fn set_r2(&mut self, val: u8) { - self.0 = (self.0 & !(0xff << 16usize)) | (((val as u32) & 0xff) << 16usize); - } -} -impl Default for Page54lock0 { - #[inline(always)] - fn default() -> Page54lock0 { - Page54lock0(0) - } -} -#[doc = "Lock configuration MSBs for page 54 (rows 0xd80 through 0xdbf). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions."] -#[repr(transparent)] -#[derive(Copy, Clone, Eq, PartialEq)] -pub struct Page54lock1(pub u32); -impl Page54lock1 { - #[doc = "Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers."] - #[inline(always)] - pub const fn lock_s(&self) -> super::vals::Page54lock1lockS { - let val = (self.0 >> 0usize) & 0x03; - super::vals::Page54lock1lockS::from_bits(val as u8) - } - #[doc = "Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers."] - #[inline(always)] - pub fn set_lock_s(&mut self, val: super::vals::Page54lock1lockS) { - self.0 = (self.0 & !(0x03 << 0usize)) | (((val.to_bits() as u32) & 0x03) << 0usize); - } - #[doc = "Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API."] - #[inline(always)] - pub const fn lock_ns(&self) -> super::vals::Page54lock1lockNs { - let val = (self.0 >> 2usize) & 0x03; - super::vals::Page54lock1lockNs::from_bits(val as u8) - } - #[doc = "Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API."] - #[inline(always)] - pub fn set_lock_ns(&mut self, val: super::vals::Page54lock1lockNs) { - self.0 = (self.0 & !(0x03 << 2usize)) | (((val.to_bits() as u32) & 0x03) << 2usize); - } - #[doc = "Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers."] - #[inline(always)] - pub const fn lock_bl(&self) -> super::vals::Page54lock1lockBl { - let val = (self.0 >> 4usize) & 0x03; - super::vals::Page54lock1lockBl::from_bits(val as u8) - } - #[doc = "Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers."] - #[inline(always)] - pub fn set_lock_bl(&mut self, val: super::vals::Page54lock1lockBl) { - self.0 = (self.0 & !(0x03 << 4usize)) | (((val.to_bits() as u32) & 0x03) << 4usize); - } - #[doc = "Redundant copy of bits 7:0"] - #[inline(always)] - pub const fn r1(&self) -> u8 { - let val = (self.0 >> 8usize) & 0xff; - val as u8 - } - #[doc = "Redundant copy of bits 7:0"] - #[inline(always)] - pub fn set_r1(&mut self, val: u8) { - self.0 = (self.0 & !(0xff << 8usize)) | (((val as u32) & 0xff) << 8usize); - } - #[doc = "Redundant copy of bits 7:0"] - #[inline(always)] - pub const fn r2(&self) -> u8 { - let val = (self.0 >> 16usize) & 0xff; - val as u8 - } - #[doc = "Redundant copy of bits 7:0"] - #[inline(always)] - pub fn set_r2(&mut self, val: u8) { - self.0 = (self.0 & !(0xff << 16usize)) | (((val as u32) & 0xff) << 16usize); - } -} -impl Default for Page54lock1 { - #[inline(always)] - fn default() -> Page54lock1 { - Page54lock1(0) - } -} -#[doc = "Lock configuration LSBs for page 55 (rows 0xdc0 through 0xdff). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions."] -#[repr(transparent)] -#[derive(Copy, Clone, Eq, PartialEq)] -pub struct Page55lock0(pub u32); -impl Page55lock0 { - #[doc = "Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required."] - #[inline(always)] - pub const fn key_w(&self) -> u8 { - let val = (self.0 >> 0usize) & 0x07; - val as u8 - } - #[doc = "Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required."] - #[inline(always)] - pub fn set_key_w(&mut self, val: u8) { - self.0 = (self.0 & !(0x07 << 0usize)) | (((val as u32) & 0x07) << 0usize); - } - #[doc = "Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required."] - #[inline(always)] - pub const fn key_r(&self) -> u8 { - let val = (self.0 >> 3usize) & 0x07; - val as u8 - } - #[doc = "Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required."] - #[inline(always)] - pub fn set_key_r(&mut self, val: u8) { - self.0 = (self.0 & !(0x07 << 3usize)) | (((val as u32) & 0x07) << 3usize); - } - #[doc = "State when at least one key is registered for this page and no matching key has been entered."] - #[inline(always)] - pub const fn no_key_state(&self) -> super::vals::Page55lock0noKeyState { - let val = (self.0 >> 6usize) & 0x01; - super::vals::Page55lock0noKeyState::from_bits(val as u8) - } - #[doc = "State when at least one key is registered for this page and no matching key has been entered."] - #[inline(always)] - pub fn set_no_key_state(&mut self, val: super::vals::Page55lock0noKeyState) { - self.0 = (self.0 & !(0x01 << 6usize)) | (((val.to_bits() as u32) & 0x01) << 6usize); - } - #[doc = "Redundant copy of bits 7:0"] - #[inline(always)] - pub const fn r1(&self) -> u8 { - let val = (self.0 >> 8usize) & 0xff; - val as u8 - } - #[doc = "Redundant copy of bits 7:0"] - #[inline(always)] - pub fn set_r1(&mut self, val: u8) { - self.0 = (self.0 & !(0xff << 8usize)) | (((val as u32) & 0xff) << 8usize); - } - #[doc = "Redundant copy of bits 7:0"] - #[inline(always)] - pub const fn r2(&self) -> u8 { - let val = (self.0 >> 16usize) & 0xff; - val as u8 - } - #[doc = "Redundant copy of bits 7:0"] - #[inline(always)] - pub fn set_r2(&mut self, val: u8) { - self.0 = (self.0 & !(0xff << 16usize)) | (((val as u32) & 0xff) << 16usize); - } -} -impl Default for Page55lock0 { - #[inline(always)] - fn default() -> Page55lock0 { - Page55lock0(0) - } -} -#[doc = "Lock configuration MSBs for page 55 (rows 0xdc0 through 0xdff). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions."] -#[repr(transparent)] -#[derive(Copy, Clone, Eq, PartialEq)] -pub struct Page55lock1(pub u32); -impl Page55lock1 { - #[doc = "Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers."] - #[inline(always)] - pub const fn lock_s(&self) -> super::vals::Page55lock1lockS { - let val = (self.0 >> 0usize) & 0x03; - super::vals::Page55lock1lockS::from_bits(val as u8) - } - #[doc = "Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers."] - #[inline(always)] - pub fn set_lock_s(&mut self, val: super::vals::Page55lock1lockS) { - self.0 = (self.0 & !(0x03 << 0usize)) | (((val.to_bits() as u32) & 0x03) << 0usize); - } - #[doc = "Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API."] - #[inline(always)] - pub const fn lock_ns(&self) -> super::vals::Page55lock1lockNs { - let val = (self.0 >> 2usize) & 0x03; - super::vals::Page55lock1lockNs::from_bits(val as u8) - } - #[doc = "Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API."] - #[inline(always)] - pub fn set_lock_ns(&mut self, val: super::vals::Page55lock1lockNs) { - self.0 = (self.0 & !(0x03 << 2usize)) | (((val.to_bits() as u32) & 0x03) << 2usize); - } - #[doc = "Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers."] - #[inline(always)] - pub const fn lock_bl(&self) -> super::vals::Page55lock1lockBl { - let val = (self.0 >> 4usize) & 0x03; - super::vals::Page55lock1lockBl::from_bits(val as u8) - } - #[doc = "Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers."] - #[inline(always)] - pub fn set_lock_bl(&mut self, val: super::vals::Page55lock1lockBl) { - self.0 = (self.0 & !(0x03 << 4usize)) | (((val.to_bits() as u32) & 0x03) << 4usize); - } - #[doc = "Redundant copy of bits 7:0"] - #[inline(always)] - pub const fn r1(&self) -> u8 { - let val = (self.0 >> 8usize) & 0xff; - val as u8 - } - #[doc = "Redundant copy of bits 7:0"] - #[inline(always)] - pub fn set_r1(&mut self, val: u8) { - self.0 = (self.0 & !(0xff << 8usize)) | (((val as u32) & 0xff) << 8usize); - } - #[doc = "Redundant copy of bits 7:0"] - #[inline(always)] - pub const fn r2(&self) -> u8 { - let val = (self.0 >> 16usize) & 0xff; - val as u8 - } - #[doc = "Redundant copy of bits 7:0"] - #[inline(always)] - pub fn set_r2(&mut self, val: u8) { - self.0 = (self.0 & !(0xff << 16usize)) | (((val as u32) & 0xff) << 16usize); - } -} -impl Default for Page55lock1 { - #[inline(always)] - fn default() -> Page55lock1 { - Page55lock1(0) - } -} -#[doc = "Lock configuration LSBs for page 56 (rows 0xe00 through 0xe3f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions."] -#[repr(transparent)] -#[derive(Copy, Clone, Eq, PartialEq)] -pub struct Page56lock0(pub u32); -impl Page56lock0 { - #[doc = "Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required."] - #[inline(always)] - pub const fn key_w(&self) -> u8 { - let val = (self.0 >> 0usize) & 0x07; - val as u8 - } - #[doc = "Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required."] - #[inline(always)] - pub fn set_key_w(&mut self, val: u8) { - self.0 = (self.0 & !(0x07 << 0usize)) | (((val as u32) & 0x07) << 0usize); - } - #[doc = "Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required."] - #[inline(always)] - pub const fn key_r(&self) -> u8 { - let val = (self.0 >> 3usize) & 0x07; - val as u8 - } - #[doc = "Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required."] - #[inline(always)] - pub fn set_key_r(&mut self, val: u8) { - self.0 = (self.0 & !(0x07 << 3usize)) | (((val as u32) & 0x07) << 3usize); - } - #[doc = "State when at least one key is registered for this page and no matching key has been entered."] - #[inline(always)] - pub const fn no_key_state(&self) -> super::vals::Page56lock0noKeyState { - let val = (self.0 >> 6usize) & 0x01; - super::vals::Page56lock0noKeyState::from_bits(val as u8) - } - #[doc = "State when at least one key is registered for this page and no matching key has been entered."] - #[inline(always)] - pub fn set_no_key_state(&mut self, val: super::vals::Page56lock0noKeyState) { - self.0 = (self.0 & !(0x01 << 6usize)) | (((val.to_bits() as u32) & 0x01) << 6usize); - } - #[doc = "Redundant copy of bits 7:0"] - #[inline(always)] - pub const fn r1(&self) -> u8 { - let val = (self.0 >> 8usize) & 0xff; - val as u8 - } - #[doc = "Redundant copy of bits 7:0"] - #[inline(always)] - pub fn set_r1(&mut self, val: u8) { - self.0 = (self.0 & !(0xff << 8usize)) | (((val as u32) & 0xff) << 8usize); - } - #[doc = "Redundant copy of bits 7:0"] - #[inline(always)] - pub const fn r2(&self) -> u8 { - let val = (self.0 >> 16usize) & 0xff; - val as u8 - } - #[doc = "Redundant copy of bits 7:0"] - #[inline(always)] - pub fn set_r2(&mut self, val: u8) { - self.0 = (self.0 & !(0xff << 16usize)) | (((val as u32) & 0xff) << 16usize); - } -} -impl Default for Page56lock0 { - #[inline(always)] - fn default() -> Page56lock0 { - Page56lock0(0) - } -} -#[doc = "Lock configuration MSBs for page 56 (rows 0xe00 through 0xe3f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions."] -#[repr(transparent)] -#[derive(Copy, Clone, Eq, PartialEq)] -pub struct Page56lock1(pub u32); -impl Page56lock1 { - #[doc = "Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers."] - #[inline(always)] - pub const fn lock_s(&self) -> super::vals::Page56lock1lockS { - let val = (self.0 >> 0usize) & 0x03; - super::vals::Page56lock1lockS::from_bits(val as u8) - } - #[doc = "Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers."] - #[inline(always)] - pub fn set_lock_s(&mut self, val: super::vals::Page56lock1lockS) { - self.0 = (self.0 & !(0x03 << 0usize)) | (((val.to_bits() as u32) & 0x03) << 0usize); - } - #[doc = "Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API."] - #[inline(always)] - pub const fn lock_ns(&self) -> super::vals::Page56lock1lockNs { - let val = (self.0 >> 2usize) & 0x03; - super::vals::Page56lock1lockNs::from_bits(val as u8) - } - #[doc = "Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API."] - #[inline(always)] - pub fn set_lock_ns(&mut self, val: super::vals::Page56lock1lockNs) { - self.0 = (self.0 & !(0x03 << 2usize)) | (((val.to_bits() as u32) & 0x03) << 2usize); - } - #[doc = "Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers."] - #[inline(always)] - pub const fn lock_bl(&self) -> super::vals::Page56lock1lockBl { - let val = (self.0 >> 4usize) & 0x03; - super::vals::Page56lock1lockBl::from_bits(val as u8) - } - #[doc = "Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers."] - #[inline(always)] - pub fn set_lock_bl(&mut self, val: super::vals::Page56lock1lockBl) { - self.0 = (self.0 & !(0x03 << 4usize)) | (((val.to_bits() as u32) & 0x03) << 4usize); - } - #[doc = "Redundant copy of bits 7:0"] - #[inline(always)] - pub const fn r1(&self) -> u8 { - let val = (self.0 >> 8usize) & 0xff; - val as u8 - } - #[doc = "Redundant copy of bits 7:0"] - #[inline(always)] - pub fn set_r1(&mut self, val: u8) { - self.0 = (self.0 & !(0xff << 8usize)) | (((val as u32) & 0xff) << 8usize); - } - #[doc = "Redundant copy of bits 7:0"] - #[inline(always)] - pub const fn r2(&self) -> u8 { - let val = (self.0 >> 16usize) & 0xff; - val as u8 - } - #[doc = "Redundant copy of bits 7:0"] - #[inline(always)] - pub fn set_r2(&mut self, val: u8) { - self.0 = (self.0 & !(0xff << 16usize)) | (((val as u32) & 0xff) << 16usize); - } -} -impl Default for Page56lock1 { - #[inline(always)] - fn default() -> Page56lock1 { - Page56lock1(0) - } -} -#[doc = "Lock configuration LSBs for page 57 (rows 0xe40 through 0xe7f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions."] -#[repr(transparent)] -#[derive(Copy, Clone, Eq, PartialEq)] -pub struct Page57lock0(pub u32); -impl Page57lock0 { - #[doc = "Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required."] - #[inline(always)] - pub const fn key_w(&self) -> u8 { - let val = (self.0 >> 0usize) & 0x07; - val as u8 - } - #[doc = "Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required."] - #[inline(always)] - pub fn set_key_w(&mut self, val: u8) { - self.0 = (self.0 & !(0x07 << 0usize)) | (((val as u32) & 0x07) << 0usize); - } - #[doc = "Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required."] - #[inline(always)] - pub const fn key_r(&self) -> u8 { - let val = (self.0 >> 3usize) & 0x07; - val as u8 - } - #[doc = "Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required."] - #[inline(always)] - pub fn set_key_r(&mut self, val: u8) { - self.0 = (self.0 & !(0x07 << 3usize)) | (((val as u32) & 0x07) << 3usize); - } - #[doc = "State when at least one key is registered for this page and no matching key has been entered."] - #[inline(always)] - pub const fn no_key_state(&self) -> super::vals::Page57lock0noKeyState { - let val = (self.0 >> 6usize) & 0x01; - super::vals::Page57lock0noKeyState::from_bits(val as u8) - } - #[doc = "State when at least one key is registered for this page and no matching key has been entered."] - #[inline(always)] - pub fn set_no_key_state(&mut self, val: super::vals::Page57lock0noKeyState) { - self.0 = (self.0 & !(0x01 << 6usize)) | (((val.to_bits() as u32) & 0x01) << 6usize); - } - #[doc = "Redundant copy of bits 7:0"] - #[inline(always)] - pub const fn r1(&self) -> u8 { - let val = (self.0 >> 8usize) & 0xff; - val as u8 - } - #[doc = "Redundant copy of bits 7:0"] - #[inline(always)] - pub fn set_r1(&mut self, val: u8) { - self.0 = (self.0 & !(0xff << 8usize)) | (((val as u32) & 0xff) << 8usize); - } - #[doc = "Redundant copy of bits 7:0"] - #[inline(always)] - pub const fn r2(&self) -> u8 { - let val = (self.0 >> 16usize) & 0xff; - val as u8 - } - #[doc = "Redundant copy of bits 7:0"] - #[inline(always)] - pub fn set_r2(&mut self, val: u8) { - self.0 = (self.0 & !(0xff << 16usize)) | (((val as u32) & 0xff) << 16usize); - } -} -impl Default for Page57lock0 { - #[inline(always)] - fn default() -> Page57lock0 { - Page57lock0(0) - } -} -#[doc = "Lock configuration MSBs for page 57 (rows 0xe40 through 0xe7f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions."] -#[repr(transparent)] -#[derive(Copy, Clone, Eq, PartialEq)] -pub struct Page57lock1(pub u32); -impl Page57lock1 { - #[doc = "Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers."] - #[inline(always)] - pub const fn lock_s(&self) -> super::vals::Page57lock1lockS { - let val = (self.0 >> 0usize) & 0x03; - super::vals::Page57lock1lockS::from_bits(val as u8) - } - #[doc = "Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers."] - #[inline(always)] - pub fn set_lock_s(&mut self, val: super::vals::Page57lock1lockS) { - self.0 = (self.0 & !(0x03 << 0usize)) | (((val.to_bits() as u32) & 0x03) << 0usize); - } - #[doc = "Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API."] - #[inline(always)] - pub const fn lock_ns(&self) -> super::vals::Page57lock1lockNs { - let val = (self.0 >> 2usize) & 0x03; - super::vals::Page57lock1lockNs::from_bits(val as u8) - } - #[doc = "Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API."] - #[inline(always)] - pub fn set_lock_ns(&mut self, val: super::vals::Page57lock1lockNs) { - self.0 = (self.0 & !(0x03 << 2usize)) | (((val.to_bits() as u32) & 0x03) << 2usize); - } - #[doc = "Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers."] - #[inline(always)] - pub const fn lock_bl(&self) -> super::vals::Page57lock1lockBl { - let val = (self.0 >> 4usize) & 0x03; - super::vals::Page57lock1lockBl::from_bits(val as u8) - } - #[doc = "Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers."] - #[inline(always)] - pub fn set_lock_bl(&mut self, val: super::vals::Page57lock1lockBl) { - self.0 = (self.0 & !(0x03 << 4usize)) | (((val.to_bits() as u32) & 0x03) << 4usize); - } - #[doc = "Redundant copy of bits 7:0"] - #[inline(always)] - pub const fn r1(&self) -> u8 { - let val = (self.0 >> 8usize) & 0xff; - val as u8 - } - #[doc = "Redundant copy of bits 7:0"] - #[inline(always)] - pub fn set_r1(&mut self, val: u8) { - self.0 = (self.0 & !(0xff << 8usize)) | (((val as u32) & 0xff) << 8usize); - } - #[doc = "Redundant copy of bits 7:0"] - #[inline(always)] - pub const fn r2(&self) -> u8 { - let val = (self.0 >> 16usize) & 0xff; - val as u8 - } - #[doc = "Redundant copy of bits 7:0"] - #[inline(always)] - pub fn set_r2(&mut self, val: u8) { - self.0 = (self.0 & !(0xff << 16usize)) | (((val as u32) & 0xff) << 16usize); - } -} -impl Default for Page57lock1 { - #[inline(always)] - fn default() -> Page57lock1 { - Page57lock1(0) - } -} -#[doc = "Lock configuration LSBs for page 58 (rows 0xe80 through 0xebf). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions."] -#[repr(transparent)] -#[derive(Copy, Clone, Eq, PartialEq)] -pub struct Page58lock0(pub u32); -impl Page58lock0 { - #[doc = "Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required."] - #[inline(always)] - pub const fn key_w(&self) -> u8 { - let val = (self.0 >> 0usize) & 0x07; - val as u8 - } - #[doc = "Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required."] - #[inline(always)] - pub fn set_key_w(&mut self, val: u8) { - self.0 = (self.0 & !(0x07 << 0usize)) | (((val as u32) & 0x07) << 0usize); - } - #[doc = "Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required."] - #[inline(always)] - pub const fn key_r(&self) -> u8 { - let val = (self.0 >> 3usize) & 0x07; - val as u8 - } - #[doc = "Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required."] - #[inline(always)] - pub fn set_key_r(&mut self, val: u8) { - self.0 = (self.0 & !(0x07 << 3usize)) | (((val as u32) & 0x07) << 3usize); - } - #[doc = "State when at least one key is registered for this page and no matching key has been entered."] - #[inline(always)] - pub const fn no_key_state(&self) -> super::vals::Page58lock0noKeyState { - let val = (self.0 >> 6usize) & 0x01; - super::vals::Page58lock0noKeyState::from_bits(val as u8) - } - #[doc = "State when at least one key is registered for this page and no matching key has been entered."] - #[inline(always)] - pub fn set_no_key_state(&mut self, val: super::vals::Page58lock0noKeyState) { - self.0 = (self.0 & !(0x01 << 6usize)) | (((val.to_bits() as u32) & 0x01) << 6usize); - } - #[doc = "Redundant copy of bits 7:0"] - #[inline(always)] - pub const fn r1(&self) -> u8 { - let val = (self.0 >> 8usize) & 0xff; - val as u8 - } - #[doc = "Redundant copy of bits 7:0"] - #[inline(always)] - pub fn set_r1(&mut self, val: u8) { - self.0 = (self.0 & !(0xff << 8usize)) | (((val as u32) & 0xff) << 8usize); - } - #[doc = "Redundant copy of bits 7:0"] - #[inline(always)] - pub const fn r2(&self) -> u8 { - let val = (self.0 >> 16usize) & 0xff; - val as u8 - } - #[doc = "Redundant copy of bits 7:0"] - #[inline(always)] - pub fn set_r2(&mut self, val: u8) { - self.0 = (self.0 & !(0xff << 16usize)) | (((val as u32) & 0xff) << 16usize); - } -} -impl Default for Page58lock0 { - #[inline(always)] - fn default() -> Page58lock0 { - Page58lock0(0) - } -} -#[doc = "Lock configuration MSBs for page 58 (rows 0xe80 through 0xebf). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions."] -#[repr(transparent)] -#[derive(Copy, Clone, Eq, PartialEq)] -pub struct Page58lock1(pub u32); -impl Page58lock1 { - #[doc = "Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers."] - #[inline(always)] - pub const fn lock_s(&self) -> super::vals::Page58lock1lockS { - let val = (self.0 >> 0usize) & 0x03; - super::vals::Page58lock1lockS::from_bits(val as u8) - } - #[doc = "Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers."] - #[inline(always)] - pub fn set_lock_s(&mut self, val: super::vals::Page58lock1lockS) { - self.0 = (self.0 & !(0x03 << 0usize)) | (((val.to_bits() as u32) & 0x03) << 0usize); - } - #[doc = "Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API."] - #[inline(always)] - pub const fn lock_ns(&self) -> super::vals::Page58lock1lockNs { - let val = (self.0 >> 2usize) & 0x03; - super::vals::Page58lock1lockNs::from_bits(val as u8) - } - #[doc = "Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API."] - #[inline(always)] - pub fn set_lock_ns(&mut self, val: super::vals::Page58lock1lockNs) { - self.0 = (self.0 & !(0x03 << 2usize)) | (((val.to_bits() as u32) & 0x03) << 2usize); - } - #[doc = "Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers."] - #[inline(always)] - pub const fn lock_bl(&self) -> super::vals::Page58lock1lockBl { - let val = (self.0 >> 4usize) & 0x03; - super::vals::Page58lock1lockBl::from_bits(val as u8) - } - #[doc = "Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers."] - #[inline(always)] - pub fn set_lock_bl(&mut self, val: super::vals::Page58lock1lockBl) { - self.0 = (self.0 & !(0x03 << 4usize)) | (((val.to_bits() as u32) & 0x03) << 4usize); - } - #[doc = "Redundant copy of bits 7:0"] - #[inline(always)] - pub const fn r1(&self) -> u8 { - let val = (self.0 >> 8usize) & 0xff; - val as u8 - } - #[doc = "Redundant copy of bits 7:0"] - #[inline(always)] - pub fn set_r1(&mut self, val: u8) { - self.0 = (self.0 & !(0xff << 8usize)) | (((val as u32) & 0xff) << 8usize); - } - #[doc = "Redundant copy of bits 7:0"] - #[inline(always)] - pub const fn r2(&self) -> u8 { - let val = (self.0 >> 16usize) & 0xff; - val as u8 - } - #[doc = "Redundant copy of bits 7:0"] - #[inline(always)] - pub fn set_r2(&mut self, val: u8) { - self.0 = (self.0 & !(0xff << 16usize)) | (((val as u32) & 0xff) << 16usize); - } -} -impl Default for Page58lock1 { - #[inline(always)] - fn default() -> Page58lock1 { - Page58lock1(0) - } -} -#[doc = "Lock configuration LSBs for page 59 (rows 0xec0 through 0xeff). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions."] -#[repr(transparent)] -#[derive(Copy, Clone, Eq, PartialEq)] -pub struct Page59lock0(pub u32); -impl Page59lock0 { - #[doc = "Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required."] - #[inline(always)] - pub const fn key_w(&self) -> u8 { - let val = (self.0 >> 0usize) & 0x07; - val as u8 - } - #[doc = "Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required."] - #[inline(always)] - pub fn set_key_w(&mut self, val: u8) { - self.0 = (self.0 & !(0x07 << 0usize)) | (((val as u32) & 0x07) << 0usize); - } - #[doc = "Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required."] - #[inline(always)] - pub const fn key_r(&self) -> u8 { - let val = (self.0 >> 3usize) & 0x07; - val as u8 - } - #[doc = "Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required."] - #[inline(always)] - pub fn set_key_r(&mut self, val: u8) { - self.0 = (self.0 & !(0x07 << 3usize)) | (((val as u32) & 0x07) << 3usize); - } - #[doc = "State when at least one key is registered for this page and no matching key has been entered."] - #[inline(always)] - pub const fn no_key_state(&self) -> super::vals::Page59lock0noKeyState { - let val = (self.0 >> 6usize) & 0x01; - super::vals::Page59lock0noKeyState::from_bits(val as u8) - } - #[doc = "State when at least one key is registered for this page and no matching key has been entered."] - #[inline(always)] - pub fn set_no_key_state(&mut self, val: super::vals::Page59lock0noKeyState) { - self.0 = (self.0 & !(0x01 << 6usize)) | (((val.to_bits() as u32) & 0x01) << 6usize); - } - #[doc = "Redundant copy of bits 7:0"] - #[inline(always)] - pub const fn r1(&self) -> u8 { - let val = (self.0 >> 8usize) & 0xff; - val as u8 - } - #[doc = "Redundant copy of bits 7:0"] - #[inline(always)] - pub fn set_r1(&mut self, val: u8) { - self.0 = (self.0 & !(0xff << 8usize)) | (((val as u32) & 0xff) << 8usize); - } - #[doc = "Redundant copy of bits 7:0"] - #[inline(always)] - pub const fn r2(&self) -> u8 { - let val = (self.0 >> 16usize) & 0xff; - val as u8 - } - #[doc = "Redundant copy of bits 7:0"] - #[inline(always)] - pub fn set_r2(&mut self, val: u8) { - self.0 = (self.0 & !(0xff << 16usize)) | (((val as u32) & 0xff) << 16usize); - } -} -impl Default for Page59lock0 { - #[inline(always)] - fn default() -> Page59lock0 { - Page59lock0(0) - } -} -#[doc = "Lock configuration MSBs for page 59 (rows 0xec0 through 0xeff). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions."] -#[repr(transparent)] -#[derive(Copy, Clone, Eq, PartialEq)] -pub struct Page59lock1(pub u32); -impl Page59lock1 { - #[doc = "Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers."] - #[inline(always)] - pub const fn lock_s(&self) -> super::vals::Page59lock1lockS { - let val = (self.0 >> 0usize) & 0x03; - super::vals::Page59lock1lockS::from_bits(val as u8) - } - #[doc = "Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers."] - #[inline(always)] - pub fn set_lock_s(&mut self, val: super::vals::Page59lock1lockS) { - self.0 = (self.0 & !(0x03 << 0usize)) | (((val.to_bits() as u32) & 0x03) << 0usize); - } - #[doc = "Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API."] - #[inline(always)] - pub const fn lock_ns(&self) -> super::vals::Page59lock1lockNs { - let val = (self.0 >> 2usize) & 0x03; - super::vals::Page59lock1lockNs::from_bits(val as u8) - } - #[doc = "Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API."] - #[inline(always)] - pub fn set_lock_ns(&mut self, val: super::vals::Page59lock1lockNs) { - self.0 = (self.0 & !(0x03 << 2usize)) | (((val.to_bits() as u32) & 0x03) << 2usize); - } - #[doc = "Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers."] - #[inline(always)] - pub const fn lock_bl(&self) -> super::vals::Page59lock1lockBl { - let val = (self.0 >> 4usize) & 0x03; - super::vals::Page59lock1lockBl::from_bits(val as u8) - } - #[doc = "Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers."] - #[inline(always)] - pub fn set_lock_bl(&mut self, val: super::vals::Page59lock1lockBl) { - self.0 = (self.0 & !(0x03 << 4usize)) | (((val.to_bits() as u32) & 0x03) << 4usize); - } - #[doc = "Redundant copy of bits 7:0"] - #[inline(always)] - pub const fn r1(&self) -> u8 { - let val = (self.0 >> 8usize) & 0xff; - val as u8 - } - #[doc = "Redundant copy of bits 7:0"] - #[inline(always)] - pub fn set_r1(&mut self, val: u8) { - self.0 = (self.0 & !(0xff << 8usize)) | (((val as u32) & 0xff) << 8usize); - } - #[doc = "Redundant copy of bits 7:0"] - #[inline(always)] - pub const fn r2(&self) -> u8 { - let val = (self.0 >> 16usize) & 0xff; - val as u8 - } - #[doc = "Redundant copy of bits 7:0"] - #[inline(always)] - pub fn set_r2(&mut self, val: u8) { - self.0 = (self.0 & !(0xff << 16usize)) | (((val as u32) & 0xff) << 16usize); - } -} -impl Default for Page59lock1 { - #[inline(always)] - fn default() -> Page59lock1 { - Page59lock1(0) - } -} -#[doc = "Lock configuration LSBs for page 5 (rows 0x140 through 0x17f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions."] -#[repr(transparent)] -#[derive(Copy, Clone, Eq, PartialEq)] -pub struct Page5lock0(pub u32); -impl Page5lock0 { - #[doc = "Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required."] - #[inline(always)] - pub const fn key_w(&self) -> u8 { - let val = (self.0 >> 0usize) & 0x07; - val as u8 - } - #[doc = "Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required."] - #[inline(always)] - pub fn set_key_w(&mut self, val: u8) { - self.0 = (self.0 & !(0x07 << 0usize)) | (((val as u32) & 0x07) << 0usize); - } - #[doc = "Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required."] - #[inline(always)] - pub const fn key_r(&self) -> u8 { - let val = (self.0 >> 3usize) & 0x07; - val as u8 - } - #[doc = "Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required."] - #[inline(always)] - pub fn set_key_r(&mut self, val: u8) { - self.0 = (self.0 & !(0x07 << 3usize)) | (((val as u32) & 0x07) << 3usize); - } - #[doc = "State when at least one key is registered for this page and no matching key has been entered."] - #[inline(always)] - pub const fn no_key_state(&self) -> super::vals::Page5lock0noKeyState { - let val = (self.0 >> 6usize) & 0x01; - super::vals::Page5lock0noKeyState::from_bits(val as u8) - } - #[doc = "State when at least one key is registered for this page and no matching key has been entered."] - #[inline(always)] - pub fn set_no_key_state(&mut self, val: super::vals::Page5lock0noKeyState) { - self.0 = (self.0 & !(0x01 << 6usize)) | (((val.to_bits() as u32) & 0x01) << 6usize); - } - #[doc = "Redundant copy of bits 7:0"] - #[inline(always)] - pub const fn r1(&self) -> u8 { - let val = (self.0 >> 8usize) & 0xff; - val as u8 - } - #[doc = "Redundant copy of bits 7:0"] - #[inline(always)] - pub fn set_r1(&mut self, val: u8) { - self.0 = (self.0 & !(0xff << 8usize)) | (((val as u32) & 0xff) << 8usize); - } - #[doc = "Redundant copy of bits 7:0"] - #[inline(always)] - pub const fn r2(&self) -> u8 { - let val = (self.0 >> 16usize) & 0xff; - val as u8 - } - #[doc = "Redundant copy of bits 7:0"] - #[inline(always)] - pub fn set_r2(&mut self, val: u8) { - self.0 = (self.0 & !(0xff << 16usize)) | (((val as u32) & 0xff) << 16usize); - } -} -impl Default for Page5lock0 { - #[inline(always)] - fn default() -> Page5lock0 { - Page5lock0(0) - } -} -#[doc = "Lock configuration MSBs for page 5 (rows 0x140 through 0x17f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions."] -#[repr(transparent)] -#[derive(Copy, Clone, Eq, PartialEq)] -pub struct Page5lock1(pub u32); -impl Page5lock1 { - #[doc = "Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers."] - #[inline(always)] - pub const fn lock_s(&self) -> super::vals::Page5lock1lockS { - let val = (self.0 >> 0usize) & 0x03; - super::vals::Page5lock1lockS::from_bits(val as u8) - } - #[doc = "Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers."] - #[inline(always)] - pub fn set_lock_s(&mut self, val: super::vals::Page5lock1lockS) { - self.0 = (self.0 & !(0x03 << 0usize)) | (((val.to_bits() as u32) & 0x03) << 0usize); - } - #[doc = "Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API."] - #[inline(always)] - pub const fn lock_ns(&self) -> super::vals::Page5lock1lockNs { - let val = (self.0 >> 2usize) & 0x03; - super::vals::Page5lock1lockNs::from_bits(val as u8) - } - #[doc = "Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API."] - #[inline(always)] - pub fn set_lock_ns(&mut self, val: super::vals::Page5lock1lockNs) { - self.0 = (self.0 & !(0x03 << 2usize)) | (((val.to_bits() as u32) & 0x03) << 2usize); - } - #[doc = "Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers."] - #[inline(always)] - pub const fn lock_bl(&self) -> super::vals::Page5lock1lockBl { - let val = (self.0 >> 4usize) & 0x03; - super::vals::Page5lock1lockBl::from_bits(val as u8) - } - #[doc = "Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers."] - #[inline(always)] - pub fn set_lock_bl(&mut self, val: super::vals::Page5lock1lockBl) { - self.0 = (self.0 & !(0x03 << 4usize)) | (((val.to_bits() as u32) & 0x03) << 4usize); - } - #[doc = "Redundant copy of bits 7:0"] - #[inline(always)] - pub const fn r1(&self) -> u8 { - let val = (self.0 >> 8usize) & 0xff; - val as u8 - } - #[doc = "Redundant copy of bits 7:0"] - #[inline(always)] - pub fn set_r1(&mut self, val: u8) { - self.0 = (self.0 & !(0xff << 8usize)) | (((val as u32) & 0xff) << 8usize); - } - #[doc = "Redundant copy of bits 7:0"] - #[inline(always)] - pub const fn r2(&self) -> u8 { - let val = (self.0 >> 16usize) & 0xff; - val as u8 - } - #[doc = "Redundant copy of bits 7:0"] - #[inline(always)] - pub fn set_r2(&mut self, val: u8) { - self.0 = (self.0 & !(0xff << 16usize)) | (((val as u32) & 0xff) << 16usize); - } -} -impl Default for Page5lock1 { - #[inline(always)] - fn default() -> Page5lock1 { - Page5lock1(0) - } -} -#[doc = "Lock configuration LSBs for page 60 (rows 0xf00 through 0xf3f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions."] -#[repr(transparent)] -#[derive(Copy, Clone, Eq, PartialEq)] -pub struct Page60lock0(pub u32); -impl Page60lock0 { - #[doc = "Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required."] - #[inline(always)] - pub const fn key_w(&self) -> u8 { - let val = (self.0 >> 0usize) & 0x07; - val as u8 - } - #[doc = "Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required."] - #[inline(always)] - pub fn set_key_w(&mut self, val: u8) { - self.0 = (self.0 & !(0x07 << 0usize)) | (((val as u32) & 0x07) << 0usize); - } - #[doc = "Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required."] - #[inline(always)] - pub const fn key_r(&self) -> u8 { - let val = (self.0 >> 3usize) & 0x07; - val as u8 - } - #[doc = "Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required."] - #[inline(always)] - pub fn set_key_r(&mut self, val: u8) { - self.0 = (self.0 & !(0x07 << 3usize)) | (((val as u32) & 0x07) << 3usize); - } - #[doc = "State when at least one key is registered for this page and no matching key has been entered."] - #[inline(always)] - pub const fn no_key_state(&self) -> super::vals::Page60lock0noKeyState { - let val = (self.0 >> 6usize) & 0x01; - super::vals::Page60lock0noKeyState::from_bits(val as u8) - } - #[doc = "State when at least one key is registered for this page and no matching key has been entered."] - #[inline(always)] - pub fn set_no_key_state(&mut self, val: super::vals::Page60lock0noKeyState) { - self.0 = (self.0 & !(0x01 << 6usize)) | (((val.to_bits() as u32) & 0x01) << 6usize); - } - #[doc = "Redundant copy of bits 7:0"] - #[inline(always)] - pub const fn r1(&self) -> u8 { - let val = (self.0 >> 8usize) & 0xff; - val as u8 - } - #[doc = "Redundant copy of bits 7:0"] - #[inline(always)] - pub fn set_r1(&mut self, val: u8) { - self.0 = (self.0 & !(0xff << 8usize)) | (((val as u32) & 0xff) << 8usize); - } - #[doc = "Redundant copy of bits 7:0"] - #[inline(always)] - pub const fn r2(&self) -> u8 { - let val = (self.0 >> 16usize) & 0xff; - val as u8 - } - #[doc = "Redundant copy of bits 7:0"] - #[inline(always)] - pub fn set_r2(&mut self, val: u8) { - self.0 = (self.0 & !(0xff << 16usize)) | (((val as u32) & 0xff) << 16usize); - } -} -impl Default for Page60lock0 { - #[inline(always)] - fn default() -> Page60lock0 { - Page60lock0(0) - } -} -#[doc = "Lock configuration MSBs for page 60 (rows 0xf00 through 0xf3f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions."] -#[repr(transparent)] -#[derive(Copy, Clone, Eq, PartialEq)] -pub struct Page60lock1(pub u32); -impl Page60lock1 { - #[doc = "Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers."] - #[inline(always)] - pub const fn lock_s(&self) -> super::vals::Page60lock1lockS { - let val = (self.0 >> 0usize) & 0x03; - super::vals::Page60lock1lockS::from_bits(val as u8) - } - #[doc = "Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers."] - #[inline(always)] - pub fn set_lock_s(&mut self, val: super::vals::Page60lock1lockS) { - self.0 = (self.0 & !(0x03 << 0usize)) | (((val.to_bits() as u32) & 0x03) << 0usize); - } - #[doc = "Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API."] - #[inline(always)] - pub const fn lock_ns(&self) -> super::vals::Page60lock1lockNs { - let val = (self.0 >> 2usize) & 0x03; - super::vals::Page60lock1lockNs::from_bits(val as u8) - } - #[doc = "Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API."] - #[inline(always)] - pub fn set_lock_ns(&mut self, val: super::vals::Page60lock1lockNs) { - self.0 = (self.0 & !(0x03 << 2usize)) | (((val.to_bits() as u32) & 0x03) << 2usize); - } - #[doc = "Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers."] - #[inline(always)] - pub const fn lock_bl(&self) -> super::vals::Page60lock1lockBl { - let val = (self.0 >> 4usize) & 0x03; - super::vals::Page60lock1lockBl::from_bits(val as u8) - } - #[doc = "Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers."] - #[inline(always)] - pub fn set_lock_bl(&mut self, val: super::vals::Page60lock1lockBl) { - self.0 = (self.0 & !(0x03 << 4usize)) | (((val.to_bits() as u32) & 0x03) << 4usize); - } - #[doc = "Redundant copy of bits 7:0"] - #[inline(always)] - pub const fn r1(&self) -> u8 { - let val = (self.0 >> 8usize) & 0xff; - val as u8 - } - #[doc = "Redundant copy of bits 7:0"] - #[inline(always)] - pub fn set_r1(&mut self, val: u8) { - self.0 = (self.0 & !(0xff << 8usize)) | (((val as u32) & 0xff) << 8usize); - } - #[doc = "Redundant copy of bits 7:0"] - #[inline(always)] - pub const fn r2(&self) -> u8 { - let val = (self.0 >> 16usize) & 0xff; - val as u8 - } - #[doc = "Redundant copy of bits 7:0"] - #[inline(always)] - pub fn set_r2(&mut self, val: u8) { - self.0 = (self.0 & !(0xff << 16usize)) | (((val as u32) & 0xff) << 16usize); - } -} -impl Default for Page60lock1 { - #[inline(always)] - fn default() -> Page60lock1 { - Page60lock1(0) - } -} -#[doc = "Lock configuration LSBs for page 61 (rows 0xf40 through 0xf7f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions."] -#[repr(transparent)] -#[derive(Copy, Clone, Eq, PartialEq)] -pub struct Page61lock0(pub u32); -impl Page61lock0 { - #[doc = "Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required."] - #[inline(always)] - pub const fn key_w(&self) -> u8 { - let val = (self.0 >> 0usize) & 0x07; - val as u8 - } - #[doc = "Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required."] - #[inline(always)] - pub fn set_key_w(&mut self, val: u8) { - self.0 = (self.0 & !(0x07 << 0usize)) | (((val as u32) & 0x07) << 0usize); - } - #[doc = "Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required."] - #[inline(always)] - pub const fn key_r(&self) -> u8 { - let val = (self.0 >> 3usize) & 0x07; - val as u8 - } - #[doc = "Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required."] - #[inline(always)] - pub fn set_key_r(&mut self, val: u8) { - self.0 = (self.0 & !(0x07 << 3usize)) | (((val as u32) & 0x07) << 3usize); - } - #[doc = "State when at least one key is registered for this page and no matching key has been entered."] - #[inline(always)] - pub const fn no_key_state(&self) -> super::vals::Page61lock0noKeyState { - let val = (self.0 >> 6usize) & 0x01; - super::vals::Page61lock0noKeyState::from_bits(val as u8) - } - #[doc = "State when at least one key is registered for this page and no matching key has been entered."] - #[inline(always)] - pub fn set_no_key_state(&mut self, val: super::vals::Page61lock0noKeyState) { - self.0 = (self.0 & !(0x01 << 6usize)) | (((val.to_bits() as u32) & 0x01) << 6usize); - } - #[doc = "Redundant copy of bits 7:0"] - #[inline(always)] - pub const fn r1(&self) -> u8 { - let val = (self.0 >> 8usize) & 0xff; - val as u8 - } - #[doc = "Redundant copy of bits 7:0"] - #[inline(always)] - pub fn set_r1(&mut self, val: u8) { - self.0 = (self.0 & !(0xff << 8usize)) | (((val as u32) & 0xff) << 8usize); - } - #[doc = "Redundant copy of bits 7:0"] - #[inline(always)] - pub const fn r2(&self) -> u8 { - let val = (self.0 >> 16usize) & 0xff; - val as u8 - } - #[doc = "Redundant copy of bits 7:0"] - #[inline(always)] - pub fn set_r2(&mut self, val: u8) { - self.0 = (self.0 & !(0xff << 16usize)) | (((val as u32) & 0xff) << 16usize); - } -} -impl Default for Page61lock0 { - #[inline(always)] - fn default() -> Page61lock0 { - Page61lock0(0) - } -} -#[doc = "Lock configuration MSBs for page 61 (rows 0xf40 through 0xf7f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions."] -#[repr(transparent)] -#[derive(Copy, Clone, Eq, PartialEq)] -pub struct Page61lock1(pub u32); -impl Page61lock1 { - #[doc = "Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers."] - #[inline(always)] - pub const fn lock_s(&self) -> super::vals::Page61lock1lockS { - let val = (self.0 >> 0usize) & 0x03; - super::vals::Page61lock1lockS::from_bits(val as u8) - } - #[doc = "Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers."] - #[inline(always)] - pub fn set_lock_s(&mut self, val: super::vals::Page61lock1lockS) { - self.0 = (self.0 & !(0x03 << 0usize)) | (((val.to_bits() as u32) & 0x03) << 0usize); - } - #[doc = "Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API."] - #[inline(always)] - pub const fn lock_ns(&self) -> super::vals::Page61lock1lockNs { - let val = (self.0 >> 2usize) & 0x03; - super::vals::Page61lock1lockNs::from_bits(val as u8) - } - #[doc = "Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API."] - #[inline(always)] - pub fn set_lock_ns(&mut self, val: super::vals::Page61lock1lockNs) { - self.0 = (self.0 & !(0x03 << 2usize)) | (((val.to_bits() as u32) & 0x03) << 2usize); - } - #[doc = "Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers."] - #[inline(always)] - pub const fn lock_bl(&self) -> super::vals::Page61lock1lockBl { - let val = (self.0 >> 4usize) & 0x03; - super::vals::Page61lock1lockBl::from_bits(val as u8) - } - #[doc = "Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers."] - #[inline(always)] - pub fn set_lock_bl(&mut self, val: super::vals::Page61lock1lockBl) { - self.0 = (self.0 & !(0x03 << 4usize)) | (((val.to_bits() as u32) & 0x03) << 4usize); - } - #[doc = "Redundant copy of bits 7:0"] - #[inline(always)] - pub const fn r1(&self) -> u8 { - let val = (self.0 >> 8usize) & 0xff; - val as u8 - } - #[doc = "Redundant copy of bits 7:0"] - #[inline(always)] - pub fn set_r1(&mut self, val: u8) { - self.0 = (self.0 & !(0xff << 8usize)) | (((val as u32) & 0xff) << 8usize); - } - #[doc = "Redundant copy of bits 7:0"] - #[inline(always)] - pub const fn r2(&self) -> u8 { - let val = (self.0 >> 16usize) & 0xff; - val as u8 - } - #[doc = "Redundant copy of bits 7:0"] - #[inline(always)] - pub fn set_r2(&mut self, val: u8) { - self.0 = (self.0 & !(0xff << 16usize)) | (((val as u32) & 0xff) << 16usize); - } -} -impl Default for Page61lock1 { - #[inline(always)] - fn default() -> Page61lock1 { - Page61lock1(0) - } -} -#[doc = "Lock configuration LSBs for page 62 (rows 0xf80 through 0xfbf). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions."] -#[repr(transparent)] -#[derive(Copy, Clone, Eq, PartialEq)] -pub struct Page62lock0(pub u32); -impl Page62lock0 { - #[doc = "Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required."] - #[inline(always)] - pub const fn key_w(&self) -> u8 { - let val = (self.0 >> 0usize) & 0x07; - val as u8 - } - #[doc = "Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required."] - #[inline(always)] - pub fn set_key_w(&mut self, val: u8) { - self.0 = (self.0 & !(0x07 << 0usize)) | (((val as u32) & 0x07) << 0usize); - } - #[doc = "Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required."] - #[inline(always)] - pub const fn key_r(&self) -> u8 { - let val = (self.0 >> 3usize) & 0x07; - val as u8 - } - #[doc = "Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required."] - #[inline(always)] - pub fn set_key_r(&mut self, val: u8) { - self.0 = (self.0 & !(0x07 << 3usize)) | (((val as u32) & 0x07) << 3usize); - } - #[doc = "State when at least one key is registered for this page and no matching key has been entered."] - #[inline(always)] - pub const fn no_key_state(&self) -> super::vals::Page62lock0noKeyState { - let val = (self.0 >> 6usize) & 0x01; - super::vals::Page62lock0noKeyState::from_bits(val as u8) - } - #[doc = "State when at least one key is registered for this page and no matching key has been entered."] - #[inline(always)] - pub fn set_no_key_state(&mut self, val: super::vals::Page62lock0noKeyState) { - self.0 = (self.0 & !(0x01 << 6usize)) | (((val.to_bits() as u32) & 0x01) << 6usize); - } - #[doc = "Redundant copy of bits 7:0"] - #[inline(always)] - pub const fn r1(&self) -> u8 { - let val = (self.0 >> 8usize) & 0xff; - val as u8 - } - #[doc = "Redundant copy of bits 7:0"] - #[inline(always)] - pub fn set_r1(&mut self, val: u8) { - self.0 = (self.0 & !(0xff << 8usize)) | (((val as u32) & 0xff) << 8usize); - } - #[doc = "Redundant copy of bits 7:0"] - #[inline(always)] - pub const fn r2(&self) -> u8 { - let val = (self.0 >> 16usize) & 0xff; - val as u8 - } - #[doc = "Redundant copy of bits 7:0"] - #[inline(always)] - pub fn set_r2(&mut self, val: u8) { - self.0 = (self.0 & !(0xff << 16usize)) | (((val as u32) & 0xff) << 16usize); - } -} -impl Default for Page62lock0 { - #[inline(always)] - fn default() -> Page62lock0 { - Page62lock0(0) - } -} -#[doc = "Lock configuration MSBs for page 62 (rows 0xf80 through 0xfbf). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions."] -#[repr(transparent)] -#[derive(Copy, Clone, Eq, PartialEq)] -pub struct Page62lock1(pub u32); -impl Page62lock1 { - #[doc = "Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers."] - #[inline(always)] - pub const fn lock_s(&self) -> super::vals::Page62lock1lockS { - let val = (self.0 >> 0usize) & 0x03; - super::vals::Page62lock1lockS::from_bits(val as u8) - } - #[doc = "Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers."] - #[inline(always)] - pub fn set_lock_s(&mut self, val: super::vals::Page62lock1lockS) { - self.0 = (self.0 & !(0x03 << 0usize)) | (((val.to_bits() as u32) & 0x03) << 0usize); - } - #[doc = "Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API."] - #[inline(always)] - pub const fn lock_ns(&self) -> super::vals::Page62lock1lockNs { - let val = (self.0 >> 2usize) & 0x03; - super::vals::Page62lock1lockNs::from_bits(val as u8) - } - #[doc = "Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API."] - #[inline(always)] - pub fn set_lock_ns(&mut self, val: super::vals::Page62lock1lockNs) { - self.0 = (self.0 & !(0x03 << 2usize)) | (((val.to_bits() as u32) & 0x03) << 2usize); - } - #[doc = "Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers."] - #[inline(always)] - pub const fn lock_bl(&self) -> super::vals::Page62lock1lockBl { - let val = (self.0 >> 4usize) & 0x03; - super::vals::Page62lock1lockBl::from_bits(val as u8) - } - #[doc = "Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers."] - #[inline(always)] - pub fn set_lock_bl(&mut self, val: super::vals::Page62lock1lockBl) { - self.0 = (self.0 & !(0x03 << 4usize)) | (((val.to_bits() as u32) & 0x03) << 4usize); - } - #[doc = "Redundant copy of bits 7:0"] - #[inline(always)] - pub const fn r1(&self) -> u8 { - let val = (self.0 >> 8usize) & 0xff; - val as u8 - } - #[doc = "Redundant copy of bits 7:0"] - #[inline(always)] - pub fn set_r1(&mut self, val: u8) { - self.0 = (self.0 & !(0xff << 8usize)) | (((val as u32) & 0xff) << 8usize); - } - #[doc = "Redundant copy of bits 7:0"] - #[inline(always)] - pub const fn r2(&self) -> u8 { - let val = (self.0 >> 16usize) & 0xff; - val as u8 - } - #[doc = "Redundant copy of bits 7:0"] - #[inline(always)] - pub fn set_r2(&mut self, val: u8) { - self.0 = (self.0 & !(0xff << 16usize)) | (((val as u32) & 0xff) << 16usize); - } -} -impl Default for Page62lock1 { - #[inline(always)] - fn default() -> Page62lock1 { - Page62lock1(0) - } -} -#[doc = "Lock configuration LSBs for page 63 (rows 0xfc0 through 0xfff). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions."] -#[repr(transparent)] -#[derive(Copy, Clone, Eq, PartialEq)] -pub struct Page63lock0(pub u32); -impl Page63lock0 { - #[doc = "Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required."] - #[inline(always)] - pub const fn key_w(&self) -> u8 { - let val = (self.0 >> 0usize) & 0x07; - val as u8 - } - #[doc = "Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required."] - #[inline(always)] - pub fn set_key_w(&mut self, val: u8) { - self.0 = (self.0 & !(0x07 << 0usize)) | (((val as u32) & 0x07) << 0usize); - } - #[doc = "Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required."] - #[inline(always)] - pub const fn key_r(&self) -> u8 { - let val = (self.0 >> 3usize) & 0x07; - val as u8 - } - #[doc = "Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required."] - #[inline(always)] - pub fn set_key_r(&mut self, val: u8) { - self.0 = (self.0 & !(0x07 << 3usize)) | (((val as u32) & 0x07) << 3usize); - } - #[doc = "State when at least one key is registered for this page and no matching key has been entered."] - #[inline(always)] - pub const fn no_key_state(&self) -> super::vals::Page63lock0noKeyState { - let val = (self.0 >> 6usize) & 0x01; - super::vals::Page63lock0noKeyState::from_bits(val as u8) - } - #[doc = "State when at least one key is registered for this page and no matching key has been entered."] - #[inline(always)] - pub fn set_no_key_state(&mut self, val: super::vals::Page63lock0noKeyState) { - self.0 = (self.0 & !(0x01 << 6usize)) | (((val.to_bits() as u32) & 0x01) << 6usize); - } - #[doc = "Decommission for RMA of a suspected faulty device. This re-enables the factory test JTAG interface, and makes pages 3 through 61 of the OTP permanently inaccessible."] - #[inline(always)] - pub const fn rma(&self) -> bool { - let val = (self.0 >> 7usize) & 0x01; - val != 0 - } - #[doc = "Decommission for RMA of a suspected faulty device. This re-enables the factory test JTAG interface, and makes pages 3 through 61 of the OTP permanently inaccessible."] - #[inline(always)] - pub fn set_rma(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 7usize)) | (((val as u32) & 0x01) << 7usize); - } - #[doc = "Redundant copy of bits 7:0"] - #[inline(always)] - pub const fn r1(&self) -> u8 { - let val = (self.0 >> 8usize) & 0xff; - val as u8 - } - #[doc = "Redundant copy of bits 7:0"] - #[inline(always)] - pub fn set_r1(&mut self, val: u8) { - self.0 = (self.0 & !(0xff << 8usize)) | (((val as u32) & 0xff) << 8usize); - } - #[doc = "Redundant copy of bits 7:0"] - #[inline(always)] - pub const fn r2(&self) -> u8 { - let val = (self.0 >> 16usize) & 0xff; - val as u8 - } - #[doc = "Redundant copy of bits 7:0"] - #[inline(always)] - pub fn set_r2(&mut self, val: u8) { - self.0 = (self.0 & !(0xff << 16usize)) | (((val as u32) & 0xff) << 16usize); - } -} -impl Default for Page63lock0 { - #[inline(always)] - fn default() -> Page63lock0 { - Page63lock0(0) - } -} -#[doc = "Lock configuration MSBs for page 63 (rows 0xfc0 through 0xfff). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions."] -#[repr(transparent)] -#[derive(Copy, Clone, Eq, PartialEq)] -pub struct Page63lock1(pub u32); -impl Page63lock1 { - #[doc = "Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers."] - #[inline(always)] - pub const fn lock_s(&self) -> super::vals::Page63lock1lockS { - let val = (self.0 >> 0usize) & 0x03; - super::vals::Page63lock1lockS::from_bits(val as u8) - } - #[doc = "Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers."] - #[inline(always)] - pub fn set_lock_s(&mut self, val: super::vals::Page63lock1lockS) { - self.0 = (self.0 & !(0x03 << 0usize)) | (((val.to_bits() as u32) & 0x03) << 0usize); - } - #[doc = "Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API."] - #[inline(always)] - pub const fn lock_ns(&self) -> super::vals::Page63lock1lockNs { - let val = (self.0 >> 2usize) & 0x03; - super::vals::Page63lock1lockNs::from_bits(val as u8) - } - #[doc = "Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API."] - #[inline(always)] - pub fn set_lock_ns(&mut self, val: super::vals::Page63lock1lockNs) { - self.0 = (self.0 & !(0x03 << 2usize)) | (((val.to_bits() as u32) & 0x03) << 2usize); - } - #[doc = "Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers."] - #[inline(always)] - pub const fn lock_bl(&self) -> super::vals::Page63lock1lockBl { - let val = (self.0 >> 4usize) & 0x03; - super::vals::Page63lock1lockBl::from_bits(val as u8) - } - #[doc = "Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers."] - #[inline(always)] - pub fn set_lock_bl(&mut self, val: super::vals::Page63lock1lockBl) { - self.0 = (self.0 & !(0x03 << 4usize)) | (((val.to_bits() as u32) & 0x03) << 4usize); - } - #[doc = "Redundant copy of bits 7:0"] - #[inline(always)] - pub const fn r1(&self) -> u8 { - let val = (self.0 >> 8usize) & 0xff; - val as u8 - } - #[doc = "Redundant copy of bits 7:0"] - #[inline(always)] - pub fn set_r1(&mut self, val: u8) { - self.0 = (self.0 & !(0xff << 8usize)) | (((val as u32) & 0xff) << 8usize); - } - #[doc = "Redundant copy of bits 7:0"] - #[inline(always)] - pub const fn r2(&self) -> u8 { - let val = (self.0 >> 16usize) & 0xff; - val as u8 - } - #[doc = "Redundant copy of bits 7:0"] - #[inline(always)] - pub fn set_r2(&mut self, val: u8) { - self.0 = (self.0 & !(0xff << 16usize)) | (((val as u32) & 0xff) << 16usize); - } -} -impl Default for Page63lock1 { - #[inline(always)] - fn default() -> Page63lock1 { - Page63lock1(0) - } -} -#[doc = "Lock configuration LSBs for page 6 (rows 0x180 through 0x1bf). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions."] -#[repr(transparent)] -#[derive(Copy, Clone, Eq, PartialEq)] -pub struct Page6lock0(pub u32); -impl Page6lock0 { - #[doc = "Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required."] - #[inline(always)] - pub const fn key_w(&self) -> u8 { - let val = (self.0 >> 0usize) & 0x07; - val as u8 - } - #[doc = "Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required."] - #[inline(always)] - pub fn set_key_w(&mut self, val: u8) { - self.0 = (self.0 & !(0x07 << 0usize)) | (((val as u32) & 0x07) << 0usize); - } - #[doc = "Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required."] - #[inline(always)] - pub const fn key_r(&self) -> u8 { - let val = (self.0 >> 3usize) & 0x07; - val as u8 - } - #[doc = "Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required."] - #[inline(always)] - pub fn set_key_r(&mut self, val: u8) { - self.0 = (self.0 & !(0x07 << 3usize)) | (((val as u32) & 0x07) << 3usize); - } - #[doc = "State when at least one key is registered for this page and no matching key has been entered."] - #[inline(always)] - pub const fn no_key_state(&self) -> super::vals::Page6lock0noKeyState { - let val = (self.0 >> 6usize) & 0x01; - super::vals::Page6lock0noKeyState::from_bits(val as u8) - } - #[doc = "State when at least one key is registered for this page and no matching key has been entered."] - #[inline(always)] - pub fn set_no_key_state(&mut self, val: super::vals::Page6lock0noKeyState) { - self.0 = (self.0 & !(0x01 << 6usize)) | (((val.to_bits() as u32) & 0x01) << 6usize); - } - #[doc = "Redundant copy of bits 7:0"] - #[inline(always)] - pub const fn r1(&self) -> u8 { - let val = (self.0 >> 8usize) & 0xff; - val as u8 - } - #[doc = "Redundant copy of bits 7:0"] - #[inline(always)] - pub fn set_r1(&mut self, val: u8) { - self.0 = (self.0 & !(0xff << 8usize)) | (((val as u32) & 0xff) << 8usize); - } - #[doc = "Redundant copy of bits 7:0"] - #[inline(always)] - pub const fn r2(&self) -> u8 { - let val = (self.0 >> 16usize) & 0xff; - val as u8 - } - #[doc = "Redundant copy of bits 7:0"] - #[inline(always)] - pub fn set_r2(&mut self, val: u8) { - self.0 = (self.0 & !(0xff << 16usize)) | (((val as u32) & 0xff) << 16usize); - } -} -impl Default for Page6lock0 { - #[inline(always)] - fn default() -> Page6lock0 { - Page6lock0(0) - } -} -#[doc = "Lock configuration MSBs for page 6 (rows 0x180 through 0x1bf). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions."] -#[repr(transparent)] -#[derive(Copy, Clone, Eq, PartialEq)] -pub struct Page6lock1(pub u32); -impl Page6lock1 { - #[doc = "Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers."] - #[inline(always)] - pub const fn lock_s(&self) -> super::vals::Page6lock1lockS { - let val = (self.0 >> 0usize) & 0x03; - super::vals::Page6lock1lockS::from_bits(val as u8) - } - #[doc = "Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers."] - #[inline(always)] - pub fn set_lock_s(&mut self, val: super::vals::Page6lock1lockS) { - self.0 = (self.0 & !(0x03 << 0usize)) | (((val.to_bits() as u32) & 0x03) << 0usize); - } - #[doc = "Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API."] - #[inline(always)] - pub const fn lock_ns(&self) -> super::vals::Page6lock1lockNs { - let val = (self.0 >> 2usize) & 0x03; - super::vals::Page6lock1lockNs::from_bits(val as u8) - } - #[doc = "Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API."] - #[inline(always)] - pub fn set_lock_ns(&mut self, val: super::vals::Page6lock1lockNs) { - self.0 = (self.0 & !(0x03 << 2usize)) | (((val.to_bits() as u32) & 0x03) << 2usize); - } - #[doc = "Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers."] - #[inline(always)] - pub const fn lock_bl(&self) -> super::vals::Page6lock1lockBl { - let val = (self.0 >> 4usize) & 0x03; - super::vals::Page6lock1lockBl::from_bits(val as u8) - } - #[doc = "Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers."] - #[inline(always)] - pub fn set_lock_bl(&mut self, val: super::vals::Page6lock1lockBl) { - self.0 = (self.0 & !(0x03 << 4usize)) | (((val.to_bits() as u32) & 0x03) << 4usize); - } - #[doc = "Redundant copy of bits 7:0"] - #[inline(always)] - pub const fn r1(&self) -> u8 { - let val = (self.0 >> 8usize) & 0xff; - val as u8 - } - #[doc = "Redundant copy of bits 7:0"] - #[inline(always)] - pub fn set_r1(&mut self, val: u8) { - self.0 = (self.0 & !(0xff << 8usize)) | (((val as u32) & 0xff) << 8usize); - } - #[doc = "Redundant copy of bits 7:0"] - #[inline(always)] - pub const fn r2(&self) -> u8 { - let val = (self.0 >> 16usize) & 0xff; - val as u8 - } - #[doc = "Redundant copy of bits 7:0"] - #[inline(always)] - pub fn set_r2(&mut self, val: u8) { - self.0 = (self.0 & !(0xff << 16usize)) | (((val as u32) & 0xff) << 16usize); - } -} -impl Default for Page6lock1 { - #[inline(always)] - fn default() -> Page6lock1 { - Page6lock1(0) - } -} -#[doc = "Lock configuration LSBs for page 7 (rows 0x1c0 through 0x1ff). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions."] -#[repr(transparent)] -#[derive(Copy, Clone, Eq, PartialEq)] -pub struct Page7lock0(pub u32); -impl Page7lock0 { - #[doc = "Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required."] - #[inline(always)] - pub const fn key_w(&self) -> u8 { - let val = (self.0 >> 0usize) & 0x07; - val as u8 - } - #[doc = "Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required."] - #[inline(always)] - pub fn set_key_w(&mut self, val: u8) { - self.0 = (self.0 & !(0x07 << 0usize)) | (((val as u32) & 0x07) << 0usize); - } - #[doc = "Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required."] - #[inline(always)] - pub const fn key_r(&self) -> u8 { - let val = (self.0 >> 3usize) & 0x07; - val as u8 - } - #[doc = "Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required."] - #[inline(always)] - pub fn set_key_r(&mut self, val: u8) { - self.0 = (self.0 & !(0x07 << 3usize)) | (((val as u32) & 0x07) << 3usize); - } - #[doc = "State when at least one key is registered for this page and no matching key has been entered."] - #[inline(always)] - pub const fn no_key_state(&self) -> super::vals::Page7lock0noKeyState { - let val = (self.0 >> 6usize) & 0x01; - super::vals::Page7lock0noKeyState::from_bits(val as u8) - } - #[doc = "State when at least one key is registered for this page and no matching key has been entered."] - #[inline(always)] - pub fn set_no_key_state(&mut self, val: super::vals::Page7lock0noKeyState) { - self.0 = (self.0 & !(0x01 << 6usize)) | (((val.to_bits() as u32) & 0x01) << 6usize); - } - #[doc = "Redundant copy of bits 7:0"] - #[inline(always)] - pub const fn r1(&self) -> u8 { - let val = (self.0 >> 8usize) & 0xff; - val as u8 - } - #[doc = "Redundant copy of bits 7:0"] - #[inline(always)] - pub fn set_r1(&mut self, val: u8) { - self.0 = (self.0 & !(0xff << 8usize)) | (((val as u32) & 0xff) << 8usize); - } - #[doc = "Redundant copy of bits 7:0"] - #[inline(always)] - pub const fn r2(&self) -> u8 { - let val = (self.0 >> 16usize) & 0xff; - val as u8 - } - #[doc = "Redundant copy of bits 7:0"] - #[inline(always)] - pub fn set_r2(&mut self, val: u8) { - self.0 = (self.0 & !(0xff << 16usize)) | (((val as u32) & 0xff) << 16usize); - } -} -impl Default for Page7lock0 { - #[inline(always)] - fn default() -> Page7lock0 { - Page7lock0(0) - } -} -#[doc = "Lock configuration MSBs for page 7 (rows 0x1c0 through 0x1ff). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions."] -#[repr(transparent)] -#[derive(Copy, Clone, Eq, PartialEq)] -pub struct Page7lock1(pub u32); -impl Page7lock1 { - #[doc = "Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers."] - #[inline(always)] - pub const fn lock_s(&self) -> super::vals::Page7lock1lockS { - let val = (self.0 >> 0usize) & 0x03; - super::vals::Page7lock1lockS::from_bits(val as u8) - } - #[doc = "Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers."] - #[inline(always)] - pub fn set_lock_s(&mut self, val: super::vals::Page7lock1lockS) { - self.0 = (self.0 & !(0x03 << 0usize)) | (((val.to_bits() as u32) & 0x03) << 0usize); - } - #[doc = "Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API."] - #[inline(always)] - pub const fn lock_ns(&self) -> super::vals::Page7lock1lockNs { - let val = (self.0 >> 2usize) & 0x03; - super::vals::Page7lock1lockNs::from_bits(val as u8) - } - #[doc = "Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API."] - #[inline(always)] - pub fn set_lock_ns(&mut self, val: super::vals::Page7lock1lockNs) { - self.0 = (self.0 & !(0x03 << 2usize)) | (((val.to_bits() as u32) & 0x03) << 2usize); - } - #[doc = "Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers."] - #[inline(always)] - pub const fn lock_bl(&self) -> super::vals::Page7lock1lockBl { - let val = (self.0 >> 4usize) & 0x03; - super::vals::Page7lock1lockBl::from_bits(val as u8) - } - #[doc = "Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers."] - #[inline(always)] - pub fn set_lock_bl(&mut self, val: super::vals::Page7lock1lockBl) { - self.0 = (self.0 & !(0x03 << 4usize)) | (((val.to_bits() as u32) & 0x03) << 4usize); - } - #[doc = "Redundant copy of bits 7:0"] - #[inline(always)] - pub const fn r1(&self) -> u8 { - let val = (self.0 >> 8usize) & 0xff; - val as u8 - } - #[doc = "Redundant copy of bits 7:0"] - #[inline(always)] - pub fn set_r1(&mut self, val: u8) { - self.0 = (self.0 & !(0xff << 8usize)) | (((val as u32) & 0xff) << 8usize); - } - #[doc = "Redundant copy of bits 7:0"] - #[inline(always)] - pub const fn r2(&self) -> u8 { - let val = (self.0 >> 16usize) & 0xff; - val as u8 - } - #[doc = "Redundant copy of bits 7:0"] - #[inline(always)] - pub fn set_r2(&mut self, val: u8) { - self.0 = (self.0 & !(0xff << 16usize)) | (((val as u32) & 0xff) << 16usize); - } -} -impl Default for Page7lock1 { - #[inline(always)] - fn default() -> Page7lock1 { - Page7lock1(0) - } -} -#[doc = "Lock configuration LSBs for page 8 (rows 0x200 through 0x23f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions."] -#[repr(transparent)] -#[derive(Copy, Clone, Eq, PartialEq)] -pub struct Page8lock0(pub u32); -impl Page8lock0 { - #[doc = "Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required."] - #[inline(always)] - pub const fn key_w(&self) -> u8 { - let val = (self.0 >> 0usize) & 0x07; - val as u8 - } - #[doc = "Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required."] - #[inline(always)] - pub fn set_key_w(&mut self, val: u8) { - self.0 = (self.0 & !(0x07 << 0usize)) | (((val as u32) & 0x07) << 0usize); - } - #[doc = "Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required."] - #[inline(always)] - pub const fn key_r(&self) -> u8 { - let val = (self.0 >> 3usize) & 0x07; - val as u8 - } - #[doc = "Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required."] - #[inline(always)] - pub fn set_key_r(&mut self, val: u8) { - self.0 = (self.0 & !(0x07 << 3usize)) | (((val as u32) & 0x07) << 3usize); - } - #[doc = "State when at least one key is registered for this page and no matching key has been entered."] - #[inline(always)] - pub const fn no_key_state(&self) -> super::vals::Page8lock0noKeyState { - let val = (self.0 >> 6usize) & 0x01; - super::vals::Page8lock0noKeyState::from_bits(val as u8) - } - #[doc = "State when at least one key is registered for this page and no matching key has been entered."] - #[inline(always)] - pub fn set_no_key_state(&mut self, val: super::vals::Page8lock0noKeyState) { - self.0 = (self.0 & !(0x01 << 6usize)) | (((val.to_bits() as u32) & 0x01) << 6usize); - } - #[doc = "Redundant copy of bits 7:0"] - #[inline(always)] - pub const fn r1(&self) -> u8 { - let val = (self.0 >> 8usize) & 0xff; - val as u8 - } - #[doc = "Redundant copy of bits 7:0"] - #[inline(always)] - pub fn set_r1(&mut self, val: u8) { - self.0 = (self.0 & !(0xff << 8usize)) | (((val as u32) & 0xff) << 8usize); - } - #[doc = "Redundant copy of bits 7:0"] - #[inline(always)] - pub const fn r2(&self) -> u8 { - let val = (self.0 >> 16usize) & 0xff; - val as u8 - } - #[doc = "Redundant copy of bits 7:0"] - #[inline(always)] - pub fn set_r2(&mut self, val: u8) { - self.0 = (self.0 & !(0xff << 16usize)) | (((val as u32) & 0xff) << 16usize); - } -} -impl Default for Page8lock0 { - #[inline(always)] - fn default() -> Page8lock0 { - Page8lock0(0) - } -} -#[doc = "Lock configuration MSBs for page 8 (rows 0x200 through 0x23f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions."] -#[repr(transparent)] -#[derive(Copy, Clone, Eq, PartialEq)] -pub struct Page8lock1(pub u32); -impl Page8lock1 { - #[doc = "Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers."] - #[inline(always)] - pub const fn lock_s(&self) -> super::vals::Page8lock1lockS { - let val = (self.0 >> 0usize) & 0x03; - super::vals::Page8lock1lockS::from_bits(val as u8) - } - #[doc = "Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers."] - #[inline(always)] - pub fn set_lock_s(&mut self, val: super::vals::Page8lock1lockS) { - self.0 = (self.0 & !(0x03 << 0usize)) | (((val.to_bits() as u32) & 0x03) << 0usize); - } - #[doc = "Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API."] - #[inline(always)] - pub const fn lock_ns(&self) -> super::vals::Page8lock1lockNs { - let val = (self.0 >> 2usize) & 0x03; - super::vals::Page8lock1lockNs::from_bits(val as u8) - } - #[doc = "Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API."] - #[inline(always)] - pub fn set_lock_ns(&mut self, val: super::vals::Page8lock1lockNs) { - self.0 = (self.0 & !(0x03 << 2usize)) | (((val.to_bits() as u32) & 0x03) << 2usize); - } - #[doc = "Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers."] - #[inline(always)] - pub const fn lock_bl(&self) -> super::vals::Page8lock1lockBl { - let val = (self.0 >> 4usize) & 0x03; - super::vals::Page8lock1lockBl::from_bits(val as u8) - } - #[doc = "Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers."] - #[inline(always)] - pub fn set_lock_bl(&mut self, val: super::vals::Page8lock1lockBl) { - self.0 = (self.0 & !(0x03 << 4usize)) | (((val.to_bits() as u32) & 0x03) << 4usize); - } - #[doc = "Redundant copy of bits 7:0"] - #[inline(always)] - pub const fn r1(&self) -> u8 { - let val = (self.0 >> 8usize) & 0xff; - val as u8 - } - #[doc = "Redundant copy of bits 7:0"] - #[inline(always)] - pub fn set_r1(&mut self, val: u8) { - self.0 = (self.0 & !(0xff << 8usize)) | (((val as u32) & 0xff) << 8usize); - } - #[doc = "Redundant copy of bits 7:0"] - #[inline(always)] - pub const fn r2(&self) -> u8 { - let val = (self.0 >> 16usize) & 0xff; - val as u8 - } - #[doc = "Redundant copy of bits 7:0"] - #[inline(always)] - pub fn set_r2(&mut self, val: u8) { - self.0 = (self.0 & !(0xff << 16usize)) | (((val as u32) & 0xff) << 16usize); - } -} -impl Default for Page8lock1 { - #[inline(always)] - fn default() -> Page8lock1 { - Page8lock1(0) - } -} -#[doc = "Lock configuration LSBs for page 9 (rows 0x240 through 0x27f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions."] -#[repr(transparent)] -#[derive(Copy, Clone, Eq, PartialEq)] -pub struct Page9lock0(pub u32); -impl Page9lock0 { - #[doc = "Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required."] - #[inline(always)] - pub const fn key_w(&self) -> u8 { - let val = (self.0 >> 0usize) & 0x07; - val as u8 - } - #[doc = "Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required."] - #[inline(always)] - pub fn set_key_w(&mut self, val: u8) { - self.0 = (self.0 & !(0x07 << 0usize)) | (((val as u32) & 0x07) << 0usize); - } - #[doc = "Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required."] - #[inline(always)] - pub const fn key_r(&self) -> u8 { - let val = (self.0 >> 3usize) & 0x07; - val as u8 - } - #[doc = "Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required."] - #[inline(always)] - pub fn set_key_r(&mut self, val: u8) { - self.0 = (self.0 & !(0x07 << 3usize)) | (((val as u32) & 0x07) << 3usize); - } - #[doc = "State when at least one key is registered for this page and no matching key has been entered."] - #[inline(always)] - pub const fn no_key_state(&self) -> super::vals::Page9lock0noKeyState { - let val = (self.0 >> 6usize) & 0x01; - super::vals::Page9lock0noKeyState::from_bits(val as u8) - } - #[doc = "State when at least one key is registered for this page and no matching key has been entered."] - #[inline(always)] - pub fn set_no_key_state(&mut self, val: super::vals::Page9lock0noKeyState) { - self.0 = (self.0 & !(0x01 << 6usize)) | (((val.to_bits() as u32) & 0x01) << 6usize); - } - #[doc = "Redundant copy of bits 7:0"] - #[inline(always)] - pub const fn r1(&self) -> u8 { - let val = (self.0 >> 8usize) & 0xff; - val as u8 - } - #[doc = "Redundant copy of bits 7:0"] - #[inline(always)] - pub fn set_r1(&mut self, val: u8) { - self.0 = (self.0 & !(0xff << 8usize)) | (((val as u32) & 0xff) << 8usize); - } - #[doc = "Redundant copy of bits 7:0"] - #[inline(always)] - pub const fn r2(&self) -> u8 { - let val = (self.0 >> 16usize) & 0xff; - val as u8 - } - #[doc = "Redundant copy of bits 7:0"] - #[inline(always)] - pub fn set_r2(&mut self, val: u8) { - self.0 = (self.0 & !(0xff << 16usize)) | (((val as u32) & 0xff) << 16usize); - } -} -impl Default for Page9lock0 { - #[inline(always)] - fn default() -> Page9lock0 { - Page9lock0(0) - } -} -#[doc = "Lock configuration MSBs for page 9 (rows 0x240 through 0x27f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions."] +#[doc = "Lock configuration MSBs for page 63 (rows 0xfc0 through 0xfff). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions."] #[repr(transparent)] #[derive(Copy, Clone, Eq, PartialEq)] -pub struct Page9lock1(pub u32); -impl Page9lock1 { +pub struct PageLock1(pub u32); +impl PageLock1 { #[doc = "Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers."] #[inline(always)] - pub const fn lock_s(&self) -> super::vals::Page9lock1lockS { + pub const fn lock_s(&self) -> super::vals::PageLock { let val = (self.0 >> 0usize) & 0x03; - super::vals::Page9lock1lockS::from_bits(val as u8) + super::vals::PageLock::from_bits(val as u8) } #[doc = "Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers."] #[inline(always)] - pub fn set_lock_s(&mut self, val: super::vals::Page9lock1lockS) { + pub fn set_lock_s(&mut self, val: super::vals::PageLock) { self.0 = (self.0 & !(0x03 << 0usize)) | (((val.to_bits() as u32) & 0x03) << 0usize); } #[doc = "Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API."] #[inline(always)] - pub const fn lock_ns(&self) -> super::vals::Page9lock1lockNs { + pub const fn lock_ns(&self) -> super::vals::PageLock { let val = (self.0 >> 2usize) & 0x03; - super::vals::Page9lock1lockNs::from_bits(val as u8) + super::vals::PageLock::from_bits(val as u8) } #[doc = "Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API."] #[inline(always)] - pub fn set_lock_ns(&mut self, val: super::vals::Page9lock1lockNs) { + pub fn set_lock_ns(&mut self, val: super::vals::PageLock) { self.0 = (self.0 & !(0x03 << 2usize)) | (((val.to_bits() as u32) & 0x03) << 2usize); } #[doc = "Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers."] #[inline(always)] - pub const fn lock_bl(&self) -> super::vals::Page9lock1lockBl { + pub const fn lock_bl(&self) -> super::vals::PageLock { let val = (self.0 >> 4usize) & 0x03; - super::vals::Page9lock1lockBl::from_bits(val as u8) + super::vals::PageLock::from_bits(val as u8) } #[doc = "Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers."] #[inline(always)] - pub fn set_lock_bl(&mut self, val: super::vals::Page9lock1lockBl) { + pub fn set_lock_bl(&mut self, val: super::vals::PageLock) { self.0 = (self.0 & !(0x03 << 4usize)) | (((val.to_bits() as u32) & 0x03) << 4usize); } #[doc = "Redundant copy of bits 7:0"] @@ -9423,10 +766,10 @@ impl Page9lock1 { self.0 = (self.0 & !(0xff << 16usize)) | (((val as u32) & 0xff) << 16usize); } } -impl Default for Page9lock1 { +impl Default for PageLock1 { #[inline(always)] - fn default() -> Page9lock1 { - Page9lock1(0) + fn default() -> PageLock1 { + PageLock1(0) } } #[doc = "USB boot specific feature flags (RBIT-3)"] diff --git a/src/rp235x/otp_data_raw/vals.rs b/src/rp235x/otp_data_raw/vals.rs index c6337e79..0f87b5f1 100644 --- a/src/rp235x/otp_data_raw/vals.rs +++ b/src/rp235x/otp_data_raw/vals.rs @@ -1,7 +1,7 @@ #[repr(u8)] #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] pub enum Cs0size { - NONE = 0, + NONE = 0x0, _8K = 0x01, _16K = 0x02, _32K = 0x03, @@ -44,7 +44,7 @@ impl From for u8 { #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] pub struct Cs1size(pub u16); impl Cs1size { - pub const NONE: Self = Self(0); + pub const NONE: Self = Self(0x0); pub const _8K: Self = Self(0x01); pub const _16K: Self = Self(0x02); pub const _32K: Self = Self(0x03); @@ -80,8097 +80,9 @@ impl From for u16 { } #[repr(u8)] #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] -pub enum Page0lock0noKeyState { - READ_ONLY = 0, - INACCESSIBLE = 0x01, -} -impl Page0lock0noKeyState { - #[inline(always)] - pub const fn from_bits(val: u8) -> Page0lock0noKeyState { - unsafe { core::mem::transmute(val & 0x01) } - } - #[inline(always)] - pub const fn to_bits(self) -> u8 { - unsafe { core::mem::transmute(self) } - } -} -impl From for Page0lock0noKeyState { - #[inline(always)] - fn from(val: u8) -> Page0lock0noKeyState { - Page0lock0noKeyState::from_bits(val) - } -} -impl From for u8 { - #[inline(always)] - fn from(val: Page0lock0noKeyState) -> u8 { - Page0lock0noKeyState::to_bits(val) - } -} -#[repr(u8)] -#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] -pub enum Page0lock1lockBl { - #[doc = "Bootloader permits user reads and writes to this page"] - READ_WRITE = 0, - #[doc = "Bootloader permits user reads of this page"] - READ_ONLY = 0x01, - #[doc = "Do not use. Behaves the same as INACCESSIBLE"] - RESERVED = 0x02, - #[doc = "Bootloader does not permit user access to this page"] - INACCESSIBLE = 0x03, -} -impl Page0lock1lockBl { - #[inline(always)] - pub const fn from_bits(val: u8) -> Page0lock1lockBl { - unsafe { core::mem::transmute(val & 0x03) } - } - #[inline(always)] - pub const fn to_bits(self) -> u8 { - unsafe { core::mem::transmute(self) } - } -} -impl From for Page0lock1lockBl { - #[inline(always)] - fn from(val: u8) -> Page0lock1lockBl { - Page0lock1lockBl::from_bits(val) - } -} -impl From for u8 { - #[inline(always)] - fn from(val: Page0lock1lockBl) -> u8 { - Page0lock1lockBl::to_bits(val) - } -} -#[repr(u8)] -#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] -pub enum Page0lock1lockNs { - #[doc = "Page can be read by Non-secure software, and Secure software may permit Non-secure writes."] - READ_WRITE = 0, - #[doc = "Page can be read by Non-secure software"] - READ_ONLY = 0x01, - #[doc = "Do not use. Behaves the same as INACCESSIBLE."] - RESERVED = 0x02, - #[doc = "Page can not be accessed by Non-secure software."] - INACCESSIBLE = 0x03, -} -impl Page0lock1lockNs { - #[inline(always)] - pub const fn from_bits(val: u8) -> Page0lock1lockNs { - unsafe { core::mem::transmute(val & 0x03) } - } - #[inline(always)] - pub const fn to_bits(self) -> u8 { - unsafe { core::mem::transmute(self) } - } -} -impl From for Page0lock1lockNs { - #[inline(always)] - fn from(val: u8) -> Page0lock1lockNs { - Page0lock1lockNs::from_bits(val) - } -} -impl From for u8 { - #[inline(always)] - fn from(val: Page0lock1lockNs) -> u8 { - Page0lock1lockNs::to_bits(val) - } -} -#[repr(u8)] -#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] -pub enum Page0lock1lockS { - #[doc = "Page is fully accessible by Secure software."] - READ_WRITE = 0, - #[doc = "Page can be read by Secure software, but can not be written."] - READ_ONLY = 0x01, - #[doc = "Do not use. Behaves the same as INACCESSIBLE."] - RESERVED = 0x02, - #[doc = "Page can not be accessed by Secure software."] - INACCESSIBLE = 0x03, -} -impl Page0lock1lockS { - #[inline(always)] - pub const fn from_bits(val: u8) -> Page0lock1lockS { - unsafe { core::mem::transmute(val & 0x03) } - } - #[inline(always)] - pub const fn to_bits(self) -> u8 { - unsafe { core::mem::transmute(self) } - } -} -impl From for Page0lock1lockS { - #[inline(always)] - fn from(val: u8) -> Page0lock1lockS { - Page0lock1lockS::from_bits(val) - } -} -impl From for u8 { - #[inline(always)] - fn from(val: Page0lock1lockS) -> u8 { - Page0lock1lockS::to_bits(val) - } -} -#[repr(u8)] -#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] -pub enum Page10lock0noKeyState { - READ_ONLY = 0, - INACCESSIBLE = 0x01, -} -impl Page10lock0noKeyState { - #[inline(always)] - pub const fn from_bits(val: u8) -> Page10lock0noKeyState { - unsafe { core::mem::transmute(val & 0x01) } - } - #[inline(always)] - pub const fn to_bits(self) -> u8 { - unsafe { core::mem::transmute(self) } - } -} -impl From for Page10lock0noKeyState { - #[inline(always)] - fn from(val: u8) -> Page10lock0noKeyState { - Page10lock0noKeyState::from_bits(val) - } -} -impl From for u8 { - #[inline(always)] - fn from(val: Page10lock0noKeyState) -> u8 { - Page10lock0noKeyState::to_bits(val) - } -} -#[repr(u8)] -#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] -pub enum Page10lock1lockBl { - #[doc = "Bootloader permits user reads and writes to this page"] - READ_WRITE = 0, - #[doc = "Bootloader permits user reads of this page"] - READ_ONLY = 0x01, - #[doc = "Do not use. Behaves the same as INACCESSIBLE"] - RESERVED = 0x02, - #[doc = "Bootloader does not permit user access to this page"] - INACCESSIBLE = 0x03, -} -impl Page10lock1lockBl { - #[inline(always)] - pub const fn from_bits(val: u8) -> Page10lock1lockBl { - unsafe { core::mem::transmute(val & 0x03) } - } - #[inline(always)] - pub const fn to_bits(self) -> u8 { - unsafe { core::mem::transmute(self) } - } -} -impl From for Page10lock1lockBl { - #[inline(always)] - fn from(val: u8) -> Page10lock1lockBl { - Page10lock1lockBl::from_bits(val) - } -} -impl From for u8 { - #[inline(always)] - fn from(val: Page10lock1lockBl) -> u8 { - Page10lock1lockBl::to_bits(val) - } -} -#[repr(u8)] -#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] -pub enum Page10lock1lockNs { - #[doc = "Page can be read by Non-secure software, and Secure software may permit Non-secure writes."] - READ_WRITE = 0, - #[doc = "Page can be read by Non-secure software"] - READ_ONLY = 0x01, - #[doc = "Do not use. Behaves the same as INACCESSIBLE."] - RESERVED = 0x02, - #[doc = "Page can not be accessed by Non-secure software."] - INACCESSIBLE = 0x03, -} -impl Page10lock1lockNs { - #[inline(always)] - pub const fn from_bits(val: u8) -> Page10lock1lockNs { - unsafe { core::mem::transmute(val & 0x03) } - } - #[inline(always)] - pub const fn to_bits(self) -> u8 { - unsafe { core::mem::transmute(self) } - } -} -impl From for Page10lock1lockNs { - #[inline(always)] - fn from(val: u8) -> Page10lock1lockNs { - Page10lock1lockNs::from_bits(val) - } -} -impl From for u8 { - #[inline(always)] - fn from(val: Page10lock1lockNs) -> u8 { - Page10lock1lockNs::to_bits(val) - } -} -#[repr(u8)] -#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] -pub enum Page10lock1lockS { - #[doc = "Page is fully accessible by Secure software."] - READ_WRITE = 0, - #[doc = "Page can be read by Secure software, but can not be written."] - READ_ONLY = 0x01, - #[doc = "Do not use. Behaves the same as INACCESSIBLE."] - RESERVED = 0x02, - #[doc = "Page can not be accessed by Secure software."] - INACCESSIBLE = 0x03, -} -impl Page10lock1lockS { - #[inline(always)] - pub const fn from_bits(val: u8) -> Page10lock1lockS { - unsafe { core::mem::transmute(val & 0x03) } - } - #[inline(always)] - pub const fn to_bits(self) -> u8 { - unsafe { core::mem::transmute(self) } - } -} -impl From for Page10lock1lockS { - #[inline(always)] - fn from(val: u8) -> Page10lock1lockS { - Page10lock1lockS::from_bits(val) - } -} -impl From for u8 { - #[inline(always)] - fn from(val: Page10lock1lockS) -> u8 { - Page10lock1lockS::to_bits(val) - } -} -#[repr(u8)] -#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] -pub enum Page11lock0noKeyState { - READ_ONLY = 0, - INACCESSIBLE = 0x01, -} -impl Page11lock0noKeyState { - #[inline(always)] - pub const fn from_bits(val: u8) -> Page11lock0noKeyState { - unsafe { core::mem::transmute(val & 0x01) } - } - #[inline(always)] - pub const fn to_bits(self) -> u8 { - unsafe { core::mem::transmute(self) } - } -} -impl From for Page11lock0noKeyState { - #[inline(always)] - fn from(val: u8) -> Page11lock0noKeyState { - Page11lock0noKeyState::from_bits(val) - } -} -impl From for u8 { - #[inline(always)] - fn from(val: Page11lock0noKeyState) -> u8 { - Page11lock0noKeyState::to_bits(val) - } -} -#[repr(u8)] -#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] -pub enum Page11lock1lockBl { - #[doc = "Bootloader permits user reads and writes to this page"] - READ_WRITE = 0, - #[doc = "Bootloader permits user reads of this page"] - READ_ONLY = 0x01, - #[doc = "Do not use. Behaves the same as INACCESSIBLE"] - RESERVED = 0x02, - #[doc = "Bootloader does not permit user access to this page"] - INACCESSIBLE = 0x03, -} -impl Page11lock1lockBl { - #[inline(always)] - pub const fn from_bits(val: u8) -> Page11lock1lockBl { - unsafe { core::mem::transmute(val & 0x03) } - } - #[inline(always)] - pub const fn to_bits(self) -> u8 { - unsafe { core::mem::transmute(self) } - } -} -impl From for Page11lock1lockBl { - #[inline(always)] - fn from(val: u8) -> Page11lock1lockBl { - Page11lock1lockBl::from_bits(val) - } -} -impl From for u8 { - #[inline(always)] - fn from(val: Page11lock1lockBl) -> u8 { - Page11lock1lockBl::to_bits(val) - } -} -#[repr(u8)] -#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] -pub enum Page11lock1lockNs { - #[doc = "Page can be read by Non-secure software, and Secure software may permit Non-secure writes."] - READ_WRITE = 0, - #[doc = "Page can be read by Non-secure software"] - READ_ONLY = 0x01, - #[doc = "Do not use. Behaves the same as INACCESSIBLE."] - RESERVED = 0x02, - #[doc = "Page can not be accessed by Non-secure software."] - INACCESSIBLE = 0x03, -} -impl Page11lock1lockNs { - #[inline(always)] - pub const fn from_bits(val: u8) -> Page11lock1lockNs { - unsafe { core::mem::transmute(val & 0x03) } - } - #[inline(always)] - pub const fn to_bits(self) -> u8 { - unsafe { core::mem::transmute(self) } - } -} -impl From for Page11lock1lockNs { - #[inline(always)] - fn from(val: u8) -> Page11lock1lockNs { - Page11lock1lockNs::from_bits(val) - } -} -impl From for u8 { - #[inline(always)] - fn from(val: Page11lock1lockNs) -> u8 { - Page11lock1lockNs::to_bits(val) - } -} -#[repr(u8)] -#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] -pub enum Page11lock1lockS { - #[doc = "Page is fully accessible by Secure software."] - READ_WRITE = 0, - #[doc = "Page can be read by Secure software, but can not be written."] - READ_ONLY = 0x01, - #[doc = "Do not use. Behaves the same as INACCESSIBLE."] - RESERVED = 0x02, - #[doc = "Page can not be accessed by Secure software."] - INACCESSIBLE = 0x03, -} -impl Page11lock1lockS { - #[inline(always)] - pub const fn from_bits(val: u8) -> Page11lock1lockS { - unsafe { core::mem::transmute(val & 0x03) } - } - #[inline(always)] - pub const fn to_bits(self) -> u8 { - unsafe { core::mem::transmute(self) } - } -} -impl From for Page11lock1lockS { - #[inline(always)] - fn from(val: u8) -> Page11lock1lockS { - Page11lock1lockS::from_bits(val) - } -} -impl From for u8 { - #[inline(always)] - fn from(val: Page11lock1lockS) -> u8 { - Page11lock1lockS::to_bits(val) - } -} -#[repr(u8)] -#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] -pub enum Page12lock0noKeyState { - READ_ONLY = 0, - INACCESSIBLE = 0x01, -} -impl Page12lock0noKeyState { - #[inline(always)] - pub const fn from_bits(val: u8) -> Page12lock0noKeyState { - unsafe { core::mem::transmute(val & 0x01) } - } - #[inline(always)] - pub const fn to_bits(self) -> u8 { - unsafe { core::mem::transmute(self) } - } -} -impl From for Page12lock0noKeyState { - #[inline(always)] - fn from(val: u8) -> Page12lock0noKeyState { - Page12lock0noKeyState::from_bits(val) - } -} -impl From for u8 { - #[inline(always)] - fn from(val: Page12lock0noKeyState) -> u8 { - Page12lock0noKeyState::to_bits(val) - } -} -#[repr(u8)] -#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] -pub enum Page12lock1lockBl { - #[doc = "Bootloader permits user reads and writes to this page"] - READ_WRITE = 0, - #[doc = "Bootloader permits user reads of this page"] - READ_ONLY = 0x01, - #[doc = "Do not use. Behaves the same as INACCESSIBLE"] - RESERVED = 0x02, - #[doc = "Bootloader does not permit user access to this page"] - INACCESSIBLE = 0x03, -} -impl Page12lock1lockBl { - #[inline(always)] - pub const fn from_bits(val: u8) -> Page12lock1lockBl { - unsafe { core::mem::transmute(val & 0x03) } - } - #[inline(always)] - pub const fn to_bits(self) -> u8 { - unsafe { core::mem::transmute(self) } - } -} -impl From for Page12lock1lockBl { - #[inline(always)] - fn from(val: u8) -> Page12lock1lockBl { - Page12lock1lockBl::from_bits(val) - } -} -impl From for u8 { - #[inline(always)] - fn from(val: Page12lock1lockBl) -> u8 { - Page12lock1lockBl::to_bits(val) - } -} -#[repr(u8)] -#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] -pub enum Page12lock1lockNs { - #[doc = "Page can be read by Non-secure software, and Secure software may permit Non-secure writes."] - READ_WRITE = 0, - #[doc = "Page can be read by Non-secure software"] - READ_ONLY = 0x01, - #[doc = "Do not use. Behaves the same as INACCESSIBLE."] - RESERVED = 0x02, - #[doc = "Page can not be accessed by Non-secure software."] - INACCESSIBLE = 0x03, -} -impl Page12lock1lockNs { - #[inline(always)] - pub const fn from_bits(val: u8) -> Page12lock1lockNs { - unsafe { core::mem::transmute(val & 0x03) } - } - #[inline(always)] - pub const fn to_bits(self) -> u8 { - unsafe { core::mem::transmute(self) } - } -} -impl From for Page12lock1lockNs { - #[inline(always)] - fn from(val: u8) -> Page12lock1lockNs { - Page12lock1lockNs::from_bits(val) - } -} -impl From for u8 { - #[inline(always)] - fn from(val: Page12lock1lockNs) -> u8 { - Page12lock1lockNs::to_bits(val) - } -} -#[repr(u8)] -#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] -pub enum Page12lock1lockS { - #[doc = "Page is fully accessible by Secure software."] - READ_WRITE = 0, - #[doc = "Page can be read by Secure software, but can not be written."] - READ_ONLY = 0x01, - #[doc = "Do not use. Behaves the same as INACCESSIBLE."] - RESERVED = 0x02, - #[doc = "Page can not be accessed by Secure software."] - INACCESSIBLE = 0x03, -} -impl Page12lock1lockS { - #[inline(always)] - pub const fn from_bits(val: u8) -> Page12lock1lockS { - unsafe { core::mem::transmute(val & 0x03) } - } - #[inline(always)] - pub const fn to_bits(self) -> u8 { - unsafe { core::mem::transmute(self) } - } -} -impl From for Page12lock1lockS { - #[inline(always)] - fn from(val: u8) -> Page12lock1lockS { - Page12lock1lockS::from_bits(val) - } -} -impl From for u8 { - #[inline(always)] - fn from(val: Page12lock1lockS) -> u8 { - Page12lock1lockS::to_bits(val) - } -} -#[repr(u8)] -#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] -pub enum Page13lock0noKeyState { - READ_ONLY = 0, - INACCESSIBLE = 0x01, -} -impl Page13lock0noKeyState { - #[inline(always)] - pub const fn from_bits(val: u8) -> Page13lock0noKeyState { - unsafe { core::mem::transmute(val & 0x01) } - } - #[inline(always)] - pub const fn to_bits(self) -> u8 { - unsafe { core::mem::transmute(self) } - } -} -impl From for Page13lock0noKeyState { - #[inline(always)] - fn from(val: u8) -> Page13lock0noKeyState { - Page13lock0noKeyState::from_bits(val) - } -} -impl From for u8 { - #[inline(always)] - fn from(val: Page13lock0noKeyState) -> u8 { - Page13lock0noKeyState::to_bits(val) - } -} -#[repr(u8)] -#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] -pub enum Page13lock1lockBl { - #[doc = "Bootloader permits user reads and writes to this page"] - READ_WRITE = 0, - #[doc = "Bootloader permits user reads of this page"] - READ_ONLY = 0x01, - #[doc = "Do not use. Behaves the same as INACCESSIBLE"] - RESERVED = 0x02, - #[doc = "Bootloader does not permit user access to this page"] - INACCESSIBLE = 0x03, -} -impl Page13lock1lockBl { - #[inline(always)] - pub const fn from_bits(val: u8) -> Page13lock1lockBl { - unsafe { core::mem::transmute(val & 0x03) } - } - #[inline(always)] - pub const fn to_bits(self) -> u8 { - unsafe { core::mem::transmute(self) } - } -} -impl From for Page13lock1lockBl { - #[inline(always)] - fn from(val: u8) -> Page13lock1lockBl { - Page13lock1lockBl::from_bits(val) - } -} -impl From for u8 { - #[inline(always)] - fn from(val: Page13lock1lockBl) -> u8 { - Page13lock1lockBl::to_bits(val) - } -} -#[repr(u8)] -#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] -pub enum Page13lock1lockNs { - #[doc = "Page can be read by Non-secure software, and Secure software may permit Non-secure writes."] - READ_WRITE = 0, - #[doc = "Page can be read by Non-secure software"] - READ_ONLY = 0x01, - #[doc = "Do not use. Behaves the same as INACCESSIBLE."] - RESERVED = 0x02, - #[doc = "Page can not be accessed by Non-secure software."] - INACCESSIBLE = 0x03, -} -impl Page13lock1lockNs { - #[inline(always)] - pub const fn from_bits(val: u8) -> Page13lock1lockNs { - unsafe { core::mem::transmute(val & 0x03) } - } - #[inline(always)] - pub const fn to_bits(self) -> u8 { - unsafe { core::mem::transmute(self) } - } -} -impl From for Page13lock1lockNs { - #[inline(always)] - fn from(val: u8) -> Page13lock1lockNs { - Page13lock1lockNs::from_bits(val) - } -} -impl From for u8 { - #[inline(always)] - fn from(val: Page13lock1lockNs) -> u8 { - Page13lock1lockNs::to_bits(val) - } -} -#[repr(u8)] -#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] -pub enum Page13lock1lockS { - #[doc = "Page is fully accessible by Secure software."] - READ_WRITE = 0, - #[doc = "Page can be read by Secure software, but can not be written."] - READ_ONLY = 0x01, - #[doc = "Do not use. Behaves the same as INACCESSIBLE."] - RESERVED = 0x02, - #[doc = "Page can not be accessed by Secure software."] - INACCESSIBLE = 0x03, -} -impl Page13lock1lockS { - #[inline(always)] - pub const fn from_bits(val: u8) -> Page13lock1lockS { - unsafe { core::mem::transmute(val & 0x03) } - } - #[inline(always)] - pub const fn to_bits(self) -> u8 { - unsafe { core::mem::transmute(self) } - } -} -impl From for Page13lock1lockS { - #[inline(always)] - fn from(val: u8) -> Page13lock1lockS { - Page13lock1lockS::from_bits(val) - } -} -impl From for u8 { - #[inline(always)] - fn from(val: Page13lock1lockS) -> u8 { - Page13lock1lockS::to_bits(val) - } -} -#[repr(u8)] -#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] -pub enum Page14lock0noKeyState { - READ_ONLY = 0, - INACCESSIBLE = 0x01, -} -impl Page14lock0noKeyState { - #[inline(always)] - pub const fn from_bits(val: u8) -> Page14lock0noKeyState { - unsafe { core::mem::transmute(val & 0x01) } - } - #[inline(always)] - pub const fn to_bits(self) -> u8 { - unsafe { core::mem::transmute(self) } - } -} -impl From for Page14lock0noKeyState { - #[inline(always)] - fn from(val: u8) -> Page14lock0noKeyState { - Page14lock0noKeyState::from_bits(val) - } -} -impl From for u8 { - #[inline(always)] - fn from(val: Page14lock0noKeyState) -> u8 { - Page14lock0noKeyState::to_bits(val) - } -} -#[repr(u8)] -#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] -pub enum Page14lock1lockBl { - #[doc = "Bootloader permits user reads and writes to this page"] - READ_WRITE = 0, - #[doc = "Bootloader permits user reads of this page"] - READ_ONLY = 0x01, - #[doc = "Do not use. Behaves the same as INACCESSIBLE"] - RESERVED = 0x02, - #[doc = "Bootloader does not permit user access to this page"] - INACCESSIBLE = 0x03, -} -impl Page14lock1lockBl { - #[inline(always)] - pub const fn from_bits(val: u8) -> Page14lock1lockBl { - unsafe { core::mem::transmute(val & 0x03) } - } - #[inline(always)] - pub const fn to_bits(self) -> u8 { - unsafe { core::mem::transmute(self) } - } -} -impl From for Page14lock1lockBl { - #[inline(always)] - fn from(val: u8) -> Page14lock1lockBl { - Page14lock1lockBl::from_bits(val) - } -} -impl From for u8 { - #[inline(always)] - fn from(val: Page14lock1lockBl) -> u8 { - Page14lock1lockBl::to_bits(val) - } -} -#[repr(u8)] -#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] -pub enum Page14lock1lockNs { - #[doc = "Page can be read by Non-secure software, and Secure software may permit Non-secure writes."] - READ_WRITE = 0, - #[doc = "Page can be read by Non-secure software"] - READ_ONLY = 0x01, - #[doc = "Do not use. Behaves the same as INACCESSIBLE."] - RESERVED = 0x02, - #[doc = "Page can not be accessed by Non-secure software."] - INACCESSIBLE = 0x03, -} -impl Page14lock1lockNs { - #[inline(always)] - pub const fn from_bits(val: u8) -> Page14lock1lockNs { - unsafe { core::mem::transmute(val & 0x03) } - } - #[inline(always)] - pub const fn to_bits(self) -> u8 { - unsafe { core::mem::transmute(self) } - } -} -impl From for Page14lock1lockNs { - #[inline(always)] - fn from(val: u8) -> Page14lock1lockNs { - Page14lock1lockNs::from_bits(val) - } -} -impl From for u8 { - #[inline(always)] - fn from(val: Page14lock1lockNs) -> u8 { - Page14lock1lockNs::to_bits(val) - } -} -#[repr(u8)] -#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] -pub enum Page14lock1lockS { - #[doc = "Page is fully accessible by Secure software."] - READ_WRITE = 0, - #[doc = "Page can be read by Secure software, but can not be written."] - READ_ONLY = 0x01, - #[doc = "Do not use. Behaves the same as INACCESSIBLE."] - RESERVED = 0x02, - #[doc = "Page can not be accessed by Secure software."] - INACCESSIBLE = 0x03, -} -impl Page14lock1lockS { - #[inline(always)] - pub const fn from_bits(val: u8) -> Page14lock1lockS { - unsafe { core::mem::transmute(val & 0x03) } - } - #[inline(always)] - pub const fn to_bits(self) -> u8 { - unsafe { core::mem::transmute(self) } - } -} -impl From for Page14lock1lockS { - #[inline(always)] - fn from(val: u8) -> Page14lock1lockS { - Page14lock1lockS::from_bits(val) - } -} -impl From for u8 { - #[inline(always)] - fn from(val: Page14lock1lockS) -> u8 { - Page14lock1lockS::to_bits(val) - } -} -#[repr(u8)] -#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] -pub enum Page15lock0noKeyState { - READ_ONLY = 0, - INACCESSIBLE = 0x01, -} -impl Page15lock0noKeyState { - #[inline(always)] - pub const fn from_bits(val: u8) -> Page15lock0noKeyState { - unsafe { core::mem::transmute(val & 0x01) } - } - #[inline(always)] - pub const fn to_bits(self) -> u8 { - unsafe { core::mem::transmute(self) } - } -} -impl From for Page15lock0noKeyState { - #[inline(always)] - fn from(val: u8) -> Page15lock0noKeyState { - Page15lock0noKeyState::from_bits(val) - } -} -impl From for u8 { - #[inline(always)] - fn from(val: Page15lock0noKeyState) -> u8 { - Page15lock0noKeyState::to_bits(val) - } -} -#[repr(u8)] -#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] -pub enum Page15lock1lockBl { - #[doc = "Bootloader permits user reads and writes to this page"] - READ_WRITE = 0, - #[doc = "Bootloader permits user reads of this page"] - READ_ONLY = 0x01, - #[doc = "Do not use. Behaves the same as INACCESSIBLE"] - RESERVED = 0x02, - #[doc = "Bootloader does not permit user access to this page"] - INACCESSIBLE = 0x03, -} -impl Page15lock1lockBl { - #[inline(always)] - pub const fn from_bits(val: u8) -> Page15lock1lockBl { - unsafe { core::mem::transmute(val & 0x03) } - } - #[inline(always)] - pub const fn to_bits(self) -> u8 { - unsafe { core::mem::transmute(self) } - } -} -impl From for Page15lock1lockBl { - #[inline(always)] - fn from(val: u8) -> Page15lock1lockBl { - Page15lock1lockBl::from_bits(val) - } -} -impl From for u8 { - #[inline(always)] - fn from(val: Page15lock1lockBl) -> u8 { - Page15lock1lockBl::to_bits(val) - } -} -#[repr(u8)] -#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] -pub enum Page15lock1lockNs { - #[doc = "Page can be read by Non-secure software, and Secure software may permit Non-secure writes."] - READ_WRITE = 0, - #[doc = "Page can be read by Non-secure software"] - READ_ONLY = 0x01, - #[doc = "Do not use. Behaves the same as INACCESSIBLE."] - RESERVED = 0x02, - #[doc = "Page can not be accessed by Non-secure software."] - INACCESSIBLE = 0x03, -} -impl Page15lock1lockNs { - #[inline(always)] - pub const fn from_bits(val: u8) -> Page15lock1lockNs { - unsafe { core::mem::transmute(val & 0x03) } - } - #[inline(always)] - pub const fn to_bits(self) -> u8 { - unsafe { core::mem::transmute(self) } - } -} -impl From for Page15lock1lockNs { - #[inline(always)] - fn from(val: u8) -> Page15lock1lockNs { - Page15lock1lockNs::from_bits(val) - } -} -impl From for u8 { - #[inline(always)] - fn from(val: Page15lock1lockNs) -> u8 { - Page15lock1lockNs::to_bits(val) - } -} -#[repr(u8)] -#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] -pub enum Page15lock1lockS { - #[doc = "Page is fully accessible by Secure software."] - READ_WRITE = 0, - #[doc = "Page can be read by Secure software, but can not be written."] - READ_ONLY = 0x01, - #[doc = "Do not use. Behaves the same as INACCESSIBLE."] - RESERVED = 0x02, - #[doc = "Page can not be accessed by Secure software."] - INACCESSIBLE = 0x03, -} -impl Page15lock1lockS { - #[inline(always)] - pub const fn from_bits(val: u8) -> Page15lock1lockS { - unsafe { core::mem::transmute(val & 0x03) } - } - #[inline(always)] - pub const fn to_bits(self) -> u8 { - unsafe { core::mem::transmute(self) } - } -} -impl From for Page15lock1lockS { - #[inline(always)] - fn from(val: u8) -> Page15lock1lockS { - Page15lock1lockS::from_bits(val) - } -} -impl From for u8 { - #[inline(always)] - fn from(val: Page15lock1lockS) -> u8 { - Page15lock1lockS::to_bits(val) - } -} -#[repr(u8)] -#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] -pub enum Page16lock0noKeyState { - READ_ONLY = 0, - INACCESSIBLE = 0x01, -} -impl Page16lock0noKeyState { - #[inline(always)] - pub const fn from_bits(val: u8) -> Page16lock0noKeyState { - unsafe { core::mem::transmute(val & 0x01) } - } - #[inline(always)] - pub const fn to_bits(self) -> u8 { - unsafe { core::mem::transmute(self) } - } -} -impl From for Page16lock0noKeyState { - #[inline(always)] - fn from(val: u8) -> Page16lock0noKeyState { - Page16lock0noKeyState::from_bits(val) - } -} -impl From for u8 { - #[inline(always)] - fn from(val: Page16lock0noKeyState) -> u8 { - Page16lock0noKeyState::to_bits(val) - } -} -#[repr(u8)] -#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] -pub enum Page16lock1lockBl { - #[doc = "Bootloader permits user reads and writes to this page"] - READ_WRITE = 0, - #[doc = "Bootloader permits user reads of this page"] - READ_ONLY = 0x01, - #[doc = "Do not use. Behaves the same as INACCESSIBLE"] - RESERVED = 0x02, - #[doc = "Bootloader does not permit user access to this page"] - INACCESSIBLE = 0x03, -} -impl Page16lock1lockBl { - #[inline(always)] - pub const fn from_bits(val: u8) -> Page16lock1lockBl { - unsafe { core::mem::transmute(val & 0x03) } - } - #[inline(always)] - pub const fn to_bits(self) -> u8 { - unsafe { core::mem::transmute(self) } - } -} -impl From for Page16lock1lockBl { - #[inline(always)] - fn from(val: u8) -> Page16lock1lockBl { - Page16lock1lockBl::from_bits(val) - } -} -impl From for u8 { - #[inline(always)] - fn from(val: Page16lock1lockBl) -> u8 { - Page16lock1lockBl::to_bits(val) - } -} -#[repr(u8)] -#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] -pub enum Page16lock1lockNs { - #[doc = "Page can be read by Non-secure software, and Secure software may permit Non-secure writes."] - READ_WRITE = 0, - #[doc = "Page can be read by Non-secure software"] - READ_ONLY = 0x01, - #[doc = "Do not use. Behaves the same as INACCESSIBLE."] - RESERVED = 0x02, - #[doc = "Page can not be accessed by Non-secure software."] - INACCESSIBLE = 0x03, -} -impl Page16lock1lockNs { - #[inline(always)] - pub const fn from_bits(val: u8) -> Page16lock1lockNs { - unsafe { core::mem::transmute(val & 0x03) } - } - #[inline(always)] - pub const fn to_bits(self) -> u8 { - unsafe { core::mem::transmute(self) } - } -} -impl From for Page16lock1lockNs { - #[inline(always)] - fn from(val: u8) -> Page16lock1lockNs { - Page16lock1lockNs::from_bits(val) - } -} -impl From for u8 { - #[inline(always)] - fn from(val: Page16lock1lockNs) -> u8 { - Page16lock1lockNs::to_bits(val) - } -} -#[repr(u8)] -#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] -pub enum Page16lock1lockS { - #[doc = "Page is fully accessible by Secure software."] - READ_WRITE = 0, - #[doc = "Page can be read by Secure software, but can not be written."] - READ_ONLY = 0x01, - #[doc = "Do not use. Behaves the same as INACCESSIBLE."] - RESERVED = 0x02, - #[doc = "Page can not be accessed by Secure software."] - INACCESSIBLE = 0x03, -} -impl Page16lock1lockS { - #[inline(always)] - pub const fn from_bits(val: u8) -> Page16lock1lockS { - unsafe { core::mem::transmute(val & 0x03) } - } - #[inline(always)] - pub const fn to_bits(self) -> u8 { - unsafe { core::mem::transmute(self) } - } -} -impl From for Page16lock1lockS { - #[inline(always)] - fn from(val: u8) -> Page16lock1lockS { - Page16lock1lockS::from_bits(val) - } -} -impl From for u8 { - #[inline(always)] - fn from(val: Page16lock1lockS) -> u8 { - Page16lock1lockS::to_bits(val) - } -} -#[repr(u8)] -#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] -pub enum Page17lock0noKeyState { - READ_ONLY = 0, - INACCESSIBLE = 0x01, -} -impl Page17lock0noKeyState { - #[inline(always)] - pub const fn from_bits(val: u8) -> Page17lock0noKeyState { - unsafe { core::mem::transmute(val & 0x01) } - } - #[inline(always)] - pub const fn to_bits(self) -> u8 { - unsafe { core::mem::transmute(self) } - } -} -impl From for Page17lock0noKeyState { - #[inline(always)] - fn from(val: u8) -> Page17lock0noKeyState { - Page17lock0noKeyState::from_bits(val) - } -} -impl From for u8 { - #[inline(always)] - fn from(val: Page17lock0noKeyState) -> u8 { - Page17lock0noKeyState::to_bits(val) - } -} -#[repr(u8)] -#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] -pub enum Page17lock1lockBl { - #[doc = "Bootloader permits user reads and writes to this page"] - READ_WRITE = 0, - #[doc = "Bootloader permits user reads of this page"] - READ_ONLY = 0x01, - #[doc = "Do not use. Behaves the same as INACCESSIBLE"] - RESERVED = 0x02, - #[doc = "Bootloader does not permit user access to this page"] - INACCESSIBLE = 0x03, -} -impl Page17lock1lockBl { - #[inline(always)] - pub const fn from_bits(val: u8) -> Page17lock1lockBl { - unsafe { core::mem::transmute(val & 0x03) } - } - #[inline(always)] - pub const fn to_bits(self) -> u8 { - unsafe { core::mem::transmute(self) } - } -} -impl From for Page17lock1lockBl { - #[inline(always)] - fn from(val: u8) -> Page17lock1lockBl { - Page17lock1lockBl::from_bits(val) - } -} -impl From for u8 { - #[inline(always)] - fn from(val: Page17lock1lockBl) -> u8 { - Page17lock1lockBl::to_bits(val) - } -} -#[repr(u8)] -#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] -pub enum Page17lock1lockNs { - #[doc = "Page can be read by Non-secure software, and Secure software may permit Non-secure writes."] - READ_WRITE = 0, - #[doc = "Page can be read by Non-secure software"] - READ_ONLY = 0x01, - #[doc = "Do not use. Behaves the same as INACCESSIBLE."] - RESERVED = 0x02, - #[doc = "Page can not be accessed by Non-secure software."] - INACCESSIBLE = 0x03, -} -impl Page17lock1lockNs { - #[inline(always)] - pub const fn from_bits(val: u8) -> Page17lock1lockNs { - unsafe { core::mem::transmute(val & 0x03) } - } - #[inline(always)] - pub const fn to_bits(self) -> u8 { - unsafe { core::mem::transmute(self) } - } -} -impl From for Page17lock1lockNs { - #[inline(always)] - fn from(val: u8) -> Page17lock1lockNs { - Page17lock1lockNs::from_bits(val) - } -} -impl From for u8 { - #[inline(always)] - fn from(val: Page17lock1lockNs) -> u8 { - Page17lock1lockNs::to_bits(val) - } -} -#[repr(u8)] -#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] -pub enum Page17lock1lockS { - #[doc = "Page is fully accessible by Secure software."] - READ_WRITE = 0, - #[doc = "Page can be read by Secure software, but can not be written."] - READ_ONLY = 0x01, - #[doc = "Do not use. Behaves the same as INACCESSIBLE."] - RESERVED = 0x02, - #[doc = "Page can not be accessed by Secure software."] - INACCESSIBLE = 0x03, -} -impl Page17lock1lockS { - #[inline(always)] - pub const fn from_bits(val: u8) -> Page17lock1lockS { - unsafe { core::mem::transmute(val & 0x03) } - } - #[inline(always)] - pub const fn to_bits(self) -> u8 { - unsafe { core::mem::transmute(self) } - } -} -impl From for Page17lock1lockS { - #[inline(always)] - fn from(val: u8) -> Page17lock1lockS { - Page17lock1lockS::from_bits(val) - } -} -impl From for u8 { - #[inline(always)] - fn from(val: Page17lock1lockS) -> u8 { - Page17lock1lockS::to_bits(val) - } -} -#[repr(u8)] -#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] -pub enum Page18lock0noKeyState { - READ_ONLY = 0, - INACCESSIBLE = 0x01, -} -impl Page18lock0noKeyState { - #[inline(always)] - pub const fn from_bits(val: u8) -> Page18lock0noKeyState { - unsafe { core::mem::transmute(val & 0x01) } - } - #[inline(always)] - pub const fn to_bits(self) -> u8 { - unsafe { core::mem::transmute(self) } - } -} -impl From for Page18lock0noKeyState { - #[inline(always)] - fn from(val: u8) -> Page18lock0noKeyState { - Page18lock0noKeyState::from_bits(val) - } -} -impl From for u8 { - #[inline(always)] - fn from(val: Page18lock0noKeyState) -> u8 { - Page18lock0noKeyState::to_bits(val) - } -} -#[repr(u8)] -#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] -pub enum Page18lock1lockBl { - #[doc = "Bootloader permits user reads and writes to this page"] - READ_WRITE = 0, - #[doc = "Bootloader permits user reads of this page"] - READ_ONLY = 0x01, - #[doc = "Do not use. Behaves the same as INACCESSIBLE"] - RESERVED = 0x02, - #[doc = "Bootloader does not permit user access to this page"] - INACCESSIBLE = 0x03, -} -impl Page18lock1lockBl { - #[inline(always)] - pub const fn from_bits(val: u8) -> Page18lock1lockBl { - unsafe { core::mem::transmute(val & 0x03) } - } - #[inline(always)] - pub const fn to_bits(self) -> u8 { - unsafe { core::mem::transmute(self) } - } -} -impl From for Page18lock1lockBl { - #[inline(always)] - fn from(val: u8) -> Page18lock1lockBl { - Page18lock1lockBl::from_bits(val) - } -} -impl From for u8 { - #[inline(always)] - fn from(val: Page18lock1lockBl) -> u8 { - Page18lock1lockBl::to_bits(val) - } -} -#[repr(u8)] -#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] -pub enum Page18lock1lockNs { - #[doc = "Page can be read by Non-secure software, and Secure software may permit Non-secure writes."] - READ_WRITE = 0, - #[doc = "Page can be read by Non-secure software"] - READ_ONLY = 0x01, - #[doc = "Do not use. Behaves the same as INACCESSIBLE."] - RESERVED = 0x02, - #[doc = "Page can not be accessed by Non-secure software."] - INACCESSIBLE = 0x03, -} -impl Page18lock1lockNs { - #[inline(always)] - pub const fn from_bits(val: u8) -> Page18lock1lockNs { - unsafe { core::mem::transmute(val & 0x03) } - } - #[inline(always)] - pub const fn to_bits(self) -> u8 { - unsafe { core::mem::transmute(self) } - } -} -impl From for Page18lock1lockNs { - #[inline(always)] - fn from(val: u8) -> Page18lock1lockNs { - Page18lock1lockNs::from_bits(val) - } -} -impl From for u8 { - #[inline(always)] - fn from(val: Page18lock1lockNs) -> u8 { - Page18lock1lockNs::to_bits(val) - } -} -#[repr(u8)] -#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] -pub enum Page18lock1lockS { - #[doc = "Page is fully accessible by Secure software."] - READ_WRITE = 0, - #[doc = "Page can be read by Secure software, but can not be written."] - READ_ONLY = 0x01, - #[doc = "Do not use. Behaves the same as INACCESSIBLE."] - RESERVED = 0x02, - #[doc = "Page can not be accessed by Secure software."] - INACCESSIBLE = 0x03, -} -impl Page18lock1lockS { - #[inline(always)] - pub const fn from_bits(val: u8) -> Page18lock1lockS { - unsafe { core::mem::transmute(val & 0x03) } - } - #[inline(always)] - pub const fn to_bits(self) -> u8 { - unsafe { core::mem::transmute(self) } - } -} -impl From for Page18lock1lockS { - #[inline(always)] - fn from(val: u8) -> Page18lock1lockS { - Page18lock1lockS::from_bits(val) - } -} -impl From for u8 { - #[inline(always)] - fn from(val: Page18lock1lockS) -> u8 { - Page18lock1lockS::to_bits(val) - } -} -#[repr(u8)] -#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] -pub enum Page19lock0noKeyState { - READ_ONLY = 0, - INACCESSIBLE = 0x01, -} -impl Page19lock0noKeyState { - #[inline(always)] - pub const fn from_bits(val: u8) -> Page19lock0noKeyState { - unsafe { core::mem::transmute(val & 0x01) } - } - #[inline(always)] - pub const fn to_bits(self) -> u8 { - unsafe { core::mem::transmute(self) } - } -} -impl From for Page19lock0noKeyState { - #[inline(always)] - fn from(val: u8) -> Page19lock0noKeyState { - Page19lock0noKeyState::from_bits(val) - } -} -impl From for u8 { - #[inline(always)] - fn from(val: Page19lock0noKeyState) -> u8 { - Page19lock0noKeyState::to_bits(val) - } -} -#[repr(u8)] -#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] -pub enum Page19lock1lockBl { - #[doc = "Bootloader permits user reads and writes to this page"] - READ_WRITE = 0, - #[doc = "Bootloader permits user reads of this page"] - READ_ONLY = 0x01, - #[doc = "Do not use. Behaves the same as INACCESSIBLE"] - RESERVED = 0x02, - #[doc = "Bootloader does not permit user access to this page"] - INACCESSIBLE = 0x03, -} -impl Page19lock1lockBl { - #[inline(always)] - pub const fn from_bits(val: u8) -> Page19lock1lockBl { - unsafe { core::mem::transmute(val & 0x03) } - } - #[inline(always)] - pub const fn to_bits(self) -> u8 { - unsafe { core::mem::transmute(self) } - } -} -impl From for Page19lock1lockBl { - #[inline(always)] - fn from(val: u8) -> Page19lock1lockBl { - Page19lock1lockBl::from_bits(val) - } -} -impl From for u8 { - #[inline(always)] - fn from(val: Page19lock1lockBl) -> u8 { - Page19lock1lockBl::to_bits(val) - } -} -#[repr(u8)] -#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] -pub enum Page19lock1lockNs { - #[doc = "Page can be read by Non-secure software, and Secure software may permit Non-secure writes."] - READ_WRITE = 0, - #[doc = "Page can be read by Non-secure software"] - READ_ONLY = 0x01, - #[doc = "Do not use. Behaves the same as INACCESSIBLE."] - RESERVED = 0x02, - #[doc = "Page can not be accessed by Non-secure software."] - INACCESSIBLE = 0x03, -} -impl Page19lock1lockNs { - #[inline(always)] - pub const fn from_bits(val: u8) -> Page19lock1lockNs { - unsafe { core::mem::transmute(val & 0x03) } - } - #[inline(always)] - pub const fn to_bits(self) -> u8 { - unsafe { core::mem::transmute(self) } - } -} -impl From for Page19lock1lockNs { - #[inline(always)] - fn from(val: u8) -> Page19lock1lockNs { - Page19lock1lockNs::from_bits(val) - } -} -impl From for u8 { - #[inline(always)] - fn from(val: Page19lock1lockNs) -> u8 { - Page19lock1lockNs::to_bits(val) - } -} -#[repr(u8)] -#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] -pub enum Page19lock1lockS { - #[doc = "Page is fully accessible by Secure software."] - READ_WRITE = 0, - #[doc = "Page can be read by Secure software, but can not be written."] - READ_ONLY = 0x01, - #[doc = "Do not use. Behaves the same as INACCESSIBLE."] - RESERVED = 0x02, - #[doc = "Page can not be accessed by Secure software."] - INACCESSIBLE = 0x03, -} -impl Page19lock1lockS { - #[inline(always)] - pub const fn from_bits(val: u8) -> Page19lock1lockS { - unsafe { core::mem::transmute(val & 0x03) } - } - #[inline(always)] - pub const fn to_bits(self) -> u8 { - unsafe { core::mem::transmute(self) } - } -} -impl From for Page19lock1lockS { - #[inline(always)] - fn from(val: u8) -> Page19lock1lockS { - Page19lock1lockS::from_bits(val) - } -} -impl From for u8 { - #[inline(always)] - fn from(val: Page19lock1lockS) -> u8 { - Page19lock1lockS::to_bits(val) - } -} -#[repr(u8)] -#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] -pub enum Page1lock0noKeyState { - READ_ONLY = 0, - INACCESSIBLE = 0x01, -} -impl Page1lock0noKeyState { - #[inline(always)] - pub const fn from_bits(val: u8) -> Page1lock0noKeyState { - unsafe { core::mem::transmute(val & 0x01) } - } - #[inline(always)] - pub const fn to_bits(self) -> u8 { - unsafe { core::mem::transmute(self) } - } -} -impl From for Page1lock0noKeyState { - #[inline(always)] - fn from(val: u8) -> Page1lock0noKeyState { - Page1lock0noKeyState::from_bits(val) - } -} -impl From for u8 { - #[inline(always)] - fn from(val: Page1lock0noKeyState) -> u8 { - Page1lock0noKeyState::to_bits(val) - } -} -#[repr(u8)] -#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] -pub enum Page1lock1lockBl { - #[doc = "Bootloader permits user reads and writes to this page"] - READ_WRITE = 0, - #[doc = "Bootloader permits user reads of this page"] - READ_ONLY = 0x01, - #[doc = "Do not use. Behaves the same as INACCESSIBLE"] - RESERVED = 0x02, - #[doc = "Bootloader does not permit user access to this page"] - INACCESSIBLE = 0x03, -} -impl Page1lock1lockBl { - #[inline(always)] - pub const fn from_bits(val: u8) -> Page1lock1lockBl { - unsafe { core::mem::transmute(val & 0x03) } - } - #[inline(always)] - pub const fn to_bits(self) -> u8 { - unsafe { core::mem::transmute(self) } - } -} -impl From for Page1lock1lockBl { - #[inline(always)] - fn from(val: u8) -> Page1lock1lockBl { - Page1lock1lockBl::from_bits(val) - } -} -impl From for u8 { - #[inline(always)] - fn from(val: Page1lock1lockBl) -> u8 { - Page1lock1lockBl::to_bits(val) - } -} -#[repr(u8)] -#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] -pub enum Page1lock1lockNs { - #[doc = "Page can be read by Non-secure software, and Secure software may permit Non-secure writes."] - READ_WRITE = 0, - #[doc = "Page can be read by Non-secure software"] - READ_ONLY = 0x01, - #[doc = "Do not use. Behaves the same as INACCESSIBLE."] - RESERVED = 0x02, - #[doc = "Page can not be accessed by Non-secure software."] - INACCESSIBLE = 0x03, -} -impl Page1lock1lockNs { - #[inline(always)] - pub const fn from_bits(val: u8) -> Page1lock1lockNs { - unsafe { core::mem::transmute(val & 0x03) } - } - #[inline(always)] - pub const fn to_bits(self) -> u8 { - unsafe { core::mem::transmute(self) } - } -} -impl From for Page1lock1lockNs { - #[inline(always)] - fn from(val: u8) -> Page1lock1lockNs { - Page1lock1lockNs::from_bits(val) - } -} -impl From for u8 { - #[inline(always)] - fn from(val: Page1lock1lockNs) -> u8 { - Page1lock1lockNs::to_bits(val) - } -} -#[repr(u8)] -#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] -pub enum Page1lock1lockS { - #[doc = "Page is fully accessible by Secure software."] - READ_WRITE = 0, - #[doc = "Page can be read by Secure software, but can not be written."] - READ_ONLY = 0x01, - #[doc = "Do not use. Behaves the same as INACCESSIBLE."] - RESERVED = 0x02, - #[doc = "Page can not be accessed by Secure software."] - INACCESSIBLE = 0x03, -} -impl Page1lock1lockS { - #[inline(always)] - pub const fn from_bits(val: u8) -> Page1lock1lockS { - unsafe { core::mem::transmute(val & 0x03) } - } - #[inline(always)] - pub const fn to_bits(self) -> u8 { - unsafe { core::mem::transmute(self) } - } -} -impl From for Page1lock1lockS { - #[inline(always)] - fn from(val: u8) -> Page1lock1lockS { - Page1lock1lockS::from_bits(val) - } -} -impl From for u8 { - #[inline(always)] - fn from(val: Page1lock1lockS) -> u8 { - Page1lock1lockS::to_bits(val) - } -} -#[repr(u8)] -#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] -pub enum Page20lock0noKeyState { - READ_ONLY = 0, - INACCESSIBLE = 0x01, -} -impl Page20lock0noKeyState { - #[inline(always)] - pub const fn from_bits(val: u8) -> Page20lock0noKeyState { - unsafe { core::mem::transmute(val & 0x01) } - } - #[inline(always)] - pub const fn to_bits(self) -> u8 { - unsafe { core::mem::transmute(self) } - } -} -impl From for Page20lock0noKeyState { - #[inline(always)] - fn from(val: u8) -> Page20lock0noKeyState { - Page20lock0noKeyState::from_bits(val) - } -} -impl From for u8 { - #[inline(always)] - fn from(val: Page20lock0noKeyState) -> u8 { - Page20lock0noKeyState::to_bits(val) - } -} -#[repr(u8)] -#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] -pub enum Page20lock1lockBl { - #[doc = "Bootloader permits user reads and writes to this page"] - READ_WRITE = 0, - #[doc = "Bootloader permits user reads of this page"] - READ_ONLY = 0x01, - #[doc = "Do not use. Behaves the same as INACCESSIBLE"] - RESERVED = 0x02, - #[doc = "Bootloader does not permit user access to this page"] - INACCESSIBLE = 0x03, -} -impl Page20lock1lockBl { - #[inline(always)] - pub const fn from_bits(val: u8) -> Page20lock1lockBl { - unsafe { core::mem::transmute(val & 0x03) } - } - #[inline(always)] - pub const fn to_bits(self) -> u8 { - unsafe { core::mem::transmute(self) } - } -} -impl From for Page20lock1lockBl { - #[inline(always)] - fn from(val: u8) -> Page20lock1lockBl { - Page20lock1lockBl::from_bits(val) - } -} -impl From for u8 { - #[inline(always)] - fn from(val: Page20lock1lockBl) -> u8 { - Page20lock1lockBl::to_bits(val) - } -} -#[repr(u8)] -#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] -pub enum Page20lock1lockNs { - #[doc = "Page can be read by Non-secure software, and Secure software may permit Non-secure writes."] - READ_WRITE = 0, - #[doc = "Page can be read by Non-secure software"] - READ_ONLY = 0x01, - #[doc = "Do not use. Behaves the same as INACCESSIBLE."] - RESERVED = 0x02, - #[doc = "Page can not be accessed by Non-secure software."] - INACCESSIBLE = 0x03, -} -impl Page20lock1lockNs { - #[inline(always)] - pub const fn from_bits(val: u8) -> Page20lock1lockNs { - unsafe { core::mem::transmute(val & 0x03) } - } - #[inline(always)] - pub const fn to_bits(self) -> u8 { - unsafe { core::mem::transmute(self) } - } -} -impl From for Page20lock1lockNs { - #[inline(always)] - fn from(val: u8) -> Page20lock1lockNs { - Page20lock1lockNs::from_bits(val) - } -} -impl From for u8 { - #[inline(always)] - fn from(val: Page20lock1lockNs) -> u8 { - Page20lock1lockNs::to_bits(val) - } -} -#[repr(u8)] -#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] -pub enum Page20lock1lockS { - #[doc = "Page is fully accessible by Secure software."] - READ_WRITE = 0, - #[doc = "Page can be read by Secure software, but can not be written."] - READ_ONLY = 0x01, - #[doc = "Do not use. Behaves the same as INACCESSIBLE."] - RESERVED = 0x02, - #[doc = "Page can not be accessed by Secure software."] - INACCESSIBLE = 0x03, -} -impl Page20lock1lockS { - #[inline(always)] - pub const fn from_bits(val: u8) -> Page20lock1lockS { - unsafe { core::mem::transmute(val & 0x03) } - } - #[inline(always)] - pub const fn to_bits(self) -> u8 { - unsafe { core::mem::transmute(self) } - } -} -impl From for Page20lock1lockS { - #[inline(always)] - fn from(val: u8) -> Page20lock1lockS { - Page20lock1lockS::from_bits(val) - } -} -impl From for u8 { - #[inline(always)] - fn from(val: Page20lock1lockS) -> u8 { - Page20lock1lockS::to_bits(val) - } -} -#[repr(u8)] -#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] -pub enum Page21lock0noKeyState { - READ_ONLY = 0, - INACCESSIBLE = 0x01, -} -impl Page21lock0noKeyState { - #[inline(always)] - pub const fn from_bits(val: u8) -> Page21lock0noKeyState { - unsafe { core::mem::transmute(val & 0x01) } - } - #[inline(always)] - pub const fn to_bits(self) -> u8 { - unsafe { core::mem::transmute(self) } - } -} -impl From for Page21lock0noKeyState { - #[inline(always)] - fn from(val: u8) -> Page21lock0noKeyState { - Page21lock0noKeyState::from_bits(val) - } -} -impl From for u8 { - #[inline(always)] - fn from(val: Page21lock0noKeyState) -> u8 { - Page21lock0noKeyState::to_bits(val) - } -} -#[repr(u8)] -#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] -pub enum Page21lock1lockBl { - #[doc = "Bootloader permits user reads and writes to this page"] - READ_WRITE = 0, - #[doc = "Bootloader permits user reads of this page"] - READ_ONLY = 0x01, - #[doc = "Do not use. Behaves the same as INACCESSIBLE"] - RESERVED = 0x02, - #[doc = "Bootloader does not permit user access to this page"] - INACCESSIBLE = 0x03, -} -impl Page21lock1lockBl { - #[inline(always)] - pub const fn from_bits(val: u8) -> Page21lock1lockBl { - unsafe { core::mem::transmute(val & 0x03) } - } - #[inline(always)] - pub const fn to_bits(self) -> u8 { - unsafe { core::mem::transmute(self) } - } -} -impl From for Page21lock1lockBl { - #[inline(always)] - fn from(val: u8) -> Page21lock1lockBl { - Page21lock1lockBl::from_bits(val) - } -} -impl From for u8 { - #[inline(always)] - fn from(val: Page21lock1lockBl) -> u8 { - Page21lock1lockBl::to_bits(val) - } -} -#[repr(u8)] -#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] -pub enum Page21lock1lockNs { - #[doc = "Page can be read by Non-secure software, and Secure software may permit Non-secure writes."] - READ_WRITE = 0, - #[doc = "Page can be read by Non-secure software"] - READ_ONLY = 0x01, - #[doc = "Do not use. Behaves the same as INACCESSIBLE."] - RESERVED = 0x02, - #[doc = "Page can not be accessed by Non-secure software."] - INACCESSIBLE = 0x03, -} -impl Page21lock1lockNs { - #[inline(always)] - pub const fn from_bits(val: u8) -> Page21lock1lockNs { - unsafe { core::mem::transmute(val & 0x03) } - } - #[inline(always)] - pub const fn to_bits(self) -> u8 { - unsafe { core::mem::transmute(self) } - } -} -impl From for Page21lock1lockNs { - #[inline(always)] - fn from(val: u8) -> Page21lock1lockNs { - Page21lock1lockNs::from_bits(val) - } -} -impl From for u8 { - #[inline(always)] - fn from(val: Page21lock1lockNs) -> u8 { - Page21lock1lockNs::to_bits(val) - } -} -#[repr(u8)] -#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] -pub enum Page21lock1lockS { - #[doc = "Page is fully accessible by Secure software."] - READ_WRITE = 0, - #[doc = "Page can be read by Secure software, but can not be written."] - READ_ONLY = 0x01, - #[doc = "Do not use. Behaves the same as INACCESSIBLE."] - RESERVED = 0x02, - #[doc = "Page can not be accessed by Secure software."] - INACCESSIBLE = 0x03, -} -impl Page21lock1lockS { - #[inline(always)] - pub const fn from_bits(val: u8) -> Page21lock1lockS { - unsafe { core::mem::transmute(val & 0x03) } - } - #[inline(always)] - pub const fn to_bits(self) -> u8 { - unsafe { core::mem::transmute(self) } - } -} -impl From for Page21lock1lockS { - #[inline(always)] - fn from(val: u8) -> Page21lock1lockS { - Page21lock1lockS::from_bits(val) - } -} -impl From for u8 { - #[inline(always)] - fn from(val: Page21lock1lockS) -> u8 { - Page21lock1lockS::to_bits(val) - } -} -#[repr(u8)] -#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] -pub enum Page22lock0noKeyState { - READ_ONLY = 0, - INACCESSIBLE = 0x01, -} -impl Page22lock0noKeyState { - #[inline(always)] - pub const fn from_bits(val: u8) -> Page22lock0noKeyState { - unsafe { core::mem::transmute(val & 0x01) } - } - #[inline(always)] - pub const fn to_bits(self) -> u8 { - unsafe { core::mem::transmute(self) } - } -} -impl From for Page22lock0noKeyState { - #[inline(always)] - fn from(val: u8) -> Page22lock0noKeyState { - Page22lock0noKeyState::from_bits(val) - } -} -impl From for u8 { - #[inline(always)] - fn from(val: Page22lock0noKeyState) -> u8 { - Page22lock0noKeyState::to_bits(val) - } -} -#[repr(u8)] -#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] -pub enum Page22lock1lockBl { - #[doc = "Bootloader permits user reads and writes to this page"] - READ_WRITE = 0, - #[doc = "Bootloader permits user reads of this page"] - READ_ONLY = 0x01, - #[doc = "Do not use. Behaves the same as INACCESSIBLE"] - RESERVED = 0x02, - #[doc = "Bootloader does not permit user access to this page"] - INACCESSIBLE = 0x03, -} -impl Page22lock1lockBl { - #[inline(always)] - pub const fn from_bits(val: u8) -> Page22lock1lockBl { - unsafe { core::mem::transmute(val & 0x03) } - } - #[inline(always)] - pub const fn to_bits(self) -> u8 { - unsafe { core::mem::transmute(self) } - } -} -impl From for Page22lock1lockBl { - #[inline(always)] - fn from(val: u8) -> Page22lock1lockBl { - Page22lock1lockBl::from_bits(val) - } -} -impl From for u8 { - #[inline(always)] - fn from(val: Page22lock1lockBl) -> u8 { - Page22lock1lockBl::to_bits(val) - } -} -#[repr(u8)] -#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] -pub enum Page22lock1lockNs { - #[doc = "Page can be read by Non-secure software, and Secure software may permit Non-secure writes."] - READ_WRITE = 0, - #[doc = "Page can be read by Non-secure software"] - READ_ONLY = 0x01, - #[doc = "Do not use. Behaves the same as INACCESSIBLE."] - RESERVED = 0x02, - #[doc = "Page can not be accessed by Non-secure software."] - INACCESSIBLE = 0x03, -} -impl Page22lock1lockNs { - #[inline(always)] - pub const fn from_bits(val: u8) -> Page22lock1lockNs { - unsafe { core::mem::transmute(val & 0x03) } - } - #[inline(always)] - pub const fn to_bits(self) -> u8 { - unsafe { core::mem::transmute(self) } - } -} -impl From for Page22lock1lockNs { - #[inline(always)] - fn from(val: u8) -> Page22lock1lockNs { - Page22lock1lockNs::from_bits(val) - } -} -impl From for u8 { - #[inline(always)] - fn from(val: Page22lock1lockNs) -> u8 { - Page22lock1lockNs::to_bits(val) - } -} -#[repr(u8)] -#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] -pub enum Page22lock1lockS { - #[doc = "Page is fully accessible by Secure software."] - READ_WRITE = 0, - #[doc = "Page can be read by Secure software, but can not be written."] - READ_ONLY = 0x01, - #[doc = "Do not use. Behaves the same as INACCESSIBLE."] - RESERVED = 0x02, - #[doc = "Page can not be accessed by Secure software."] - INACCESSIBLE = 0x03, -} -impl Page22lock1lockS { - #[inline(always)] - pub const fn from_bits(val: u8) -> Page22lock1lockS { - unsafe { core::mem::transmute(val & 0x03) } - } - #[inline(always)] - pub const fn to_bits(self) -> u8 { - unsafe { core::mem::transmute(self) } - } -} -impl From for Page22lock1lockS { - #[inline(always)] - fn from(val: u8) -> Page22lock1lockS { - Page22lock1lockS::from_bits(val) - } -} -impl From for u8 { - #[inline(always)] - fn from(val: Page22lock1lockS) -> u8 { - Page22lock1lockS::to_bits(val) - } -} -#[repr(u8)] -#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] -pub enum Page23lock0noKeyState { - READ_ONLY = 0, - INACCESSIBLE = 0x01, -} -impl Page23lock0noKeyState { - #[inline(always)] - pub const fn from_bits(val: u8) -> Page23lock0noKeyState { - unsafe { core::mem::transmute(val & 0x01) } - } - #[inline(always)] - pub const fn to_bits(self) -> u8 { - unsafe { core::mem::transmute(self) } - } -} -impl From for Page23lock0noKeyState { - #[inline(always)] - fn from(val: u8) -> Page23lock0noKeyState { - Page23lock0noKeyState::from_bits(val) - } -} -impl From for u8 { - #[inline(always)] - fn from(val: Page23lock0noKeyState) -> u8 { - Page23lock0noKeyState::to_bits(val) - } -} -#[repr(u8)] -#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] -pub enum Page23lock1lockBl { - #[doc = "Bootloader permits user reads and writes to this page"] - READ_WRITE = 0, - #[doc = "Bootloader permits user reads of this page"] - READ_ONLY = 0x01, - #[doc = "Do not use. Behaves the same as INACCESSIBLE"] - RESERVED = 0x02, - #[doc = "Bootloader does not permit user access to this page"] - INACCESSIBLE = 0x03, -} -impl Page23lock1lockBl { - #[inline(always)] - pub const fn from_bits(val: u8) -> Page23lock1lockBl { - unsafe { core::mem::transmute(val & 0x03) } - } - #[inline(always)] - pub const fn to_bits(self) -> u8 { - unsafe { core::mem::transmute(self) } - } -} -impl From for Page23lock1lockBl { - #[inline(always)] - fn from(val: u8) -> Page23lock1lockBl { - Page23lock1lockBl::from_bits(val) - } -} -impl From for u8 { - #[inline(always)] - fn from(val: Page23lock1lockBl) -> u8 { - Page23lock1lockBl::to_bits(val) - } -} -#[repr(u8)] -#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] -pub enum Page23lock1lockNs { - #[doc = "Page can be read by Non-secure software, and Secure software may permit Non-secure writes."] - READ_WRITE = 0, - #[doc = "Page can be read by Non-secure software"] - READ_ONLY = 0x01, - #[doc = "Do not use. Behaves the same as INACCESSIBLE."] - RESERVED = 0x02, - #[doc = "Page can not be accessed by Non-secure software."] - INACCESSIBLE = 0x03, -} -impl Page23lock1lockNs { - #[inline(always)] - pub const fn from_bits(val: u8) -> Page23lock1lockNs { - unsafe { core::mem::transmute(val & 0x03) } - } - #[inline(always)] - pub const fn to_bits(self) -> u8 { - unsafe { core::mem::transmute(self) } - } -} -impl From for Page23lock1lockNs { - #[inline(always)] - fn from(val: u8) -> Page23lock1lockNs { - Page23lock1lockNs::from_bits(val) - } -} -impl From for u8 { - #[inline(always)] - fn from(val: Page23lock1lockNs) -> u8 { - Page23lock1lockNs::to_bits(val) - } -} -#[repr(u8)] -#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] -pub enum Page23lock1lockS { - #[doc = "Page is fully accessible by Secure software."] - READ_WRITE = 0, - #[doc = "Page can be read by Secure software, but can not be written."] - READ_ONLY = 0x01, - #[doc = "Do not use. Behaves the same as INACCESSIBLE."] - RESERVED = 0x02, - #[doc = "Page can not be accessed by Secure software."] - INACCESSIBLE = 0x03, -} -impl Page23lock1lockS { - #[inline(always)] - pub const fn from_bits(val: u8) -> Page23lock1lockS { - unsafe { core::mem::transmute(val & 0x03) } - } - #[inline(always)] - pub const fn to_bits(self) -> u8 { - unsafe { core::mem::transmute(self) } - } -} -impl From for Page23lock1lockS { - #[inline(always)] - fn from(val: u8) -> Page23lock1lockS { - Page23lock1lockS::from_bits(val) - } -} -impl From for u8 { - #[inline(always)] - fn from(val: Page23lock1lockS) -> u8 { - Page23lock1lockS::to_bits(val) - } -} -#[repr(u8)] -#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] -pub enum Page24lock0noKeyState { - READ_ONLY = 0, - INACCESSIBLE = 0x01, -} -impl Page24lock0noKeyState { - #[inline(always)] - pub const fn from_bits(val: u8) -> Page24lock0noKeyState { - unsafe { core::mem::transmute(val & 0x01) } - } - #[inline(always)] - pub const fn to_bits(self) -> u8 { - unsafe { core::mem::transmute(self) } - } -} -impl From for Page24lock0noKeyState { - #[inline(always)] - fn from(val: u8) -> Page24lock0noKeyState { - Page24lock0noKeyState::from_bits(val) - } -} -impl From for u8 { - #[inline(always)] - fn from(val: Page24lock0noKeyState) -> u8 { - Page24lock0noKeyState::to_bits(val) - } -} -#[repr(u8)] -#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] -pub enum Page24lock1lockBl { - #[doc = "Bootloader permits user reads and writes to this page"] - READ_WRITE = 0, - #[doc = "Bootloader permits user reads of this page"] - READ_ONLY = 0x01, - #[doc = "Do not use. Behaves the same as INACCESSIBLE"] - RESERVED = 0x02, - #[doc = "Bootloader does not permit user access to this page"] - INACCESSIBLE = 0x03, -} -impl Page24lock1lockBl { - #[inline(always)] - pub const fn from_bits(val: u8) -> Page24lock1lockBl { - unsafe { core::mem::transmute(val & 0x03) } - } - #[inline(always)] - pub const fn to_bits(self) -> u8 { - unsafe { core::mem::transmute(self) } - } -} -impl From for Page24lock1lockBl { - #[inline(always)] - fn from(val: u8) -> Page24lock1lockBl { - Page24lock1lockBl::from_bits(val) - } -} -impl From for u8 { - #[inline(always)] - fn from(val: Page24lock1lockBl) -> u8 { - Page24lock1lockBl::to_bits(val) - } -} -#[repr(u8)] -#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] -pub enum Page24lock1lockNs { - #[doc = "Page can be read by Non-secure software, and Secure software may permit Non-secure writes."] - READ_WRITE = 0, - #[doc = "Page can be read by Non-secure software"] - READ_ONLY = 0x01, - #[doc = "Do not use. Behaves the same as INACCESSIBLE."] - RESERVED = 0x02, - #[doc = "Page can not be accessed by Non-secure software."] - INACCESSIBLE = 0x03, -} -impl Page24lock1lockNs { - #[inline(always)] - pub const fn from_bits(val: u8) -> Page24lock1lockNs { - unsafe { core::mem::transmute(val & 0x03) } - } - #[inline(always)] - pub const fn to_bits(self) -> u8 { - unsafe { core::mem::transmute(self) } - } -} -impl From for Page24lock1lockNs { - #[inline(always)] - fn from(val: u8) -> Page24lock1lockNs { - Page24lock1lockNs::from_bits(val) - } -} -impl From for u8 { - #[inline(always)] - fn from(val: Page24lock1lockNs) -> u8 { - Page24lock1lockNs::to_bits(val) - } -} -#[repr(u8)] -#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] -pub enum Page24lock1lockS { - #[doc = "Page is fully accessible by Secure software."] - READ_WRITE = 0, - #[doc = "Page can be read by Secure software, but can not be written."] - READ_ONLY = 0x01, - #[doc = "Do not use. Behaves the same as INACCESSIBLE."] - RESERVED = 0x02, - #[doc = "Page can not be accessed by Secure software."] - INACCESSIBLE = 0x03, -} -impl Page24lock1lockS { - #[inline(always)] - pub const fn from_bits(val: u8) -> Page24lock1lockS { - unsafe { core::mem::transmute(val & 0x03) } - } - #[inline(always)] - pub const fn to_bits(self) -> u8 { - unsafe { core::mem::transmute(self) } - } -} -impl From for Page24lock1lockS { - #[inline(always)] - fn from(val: u8) -> Page24lock1lockS { - Page24lock1lockS::from_bits(val) - } -} -impl From for u8 { - #[inline(always)] - fn from(val: Page24lock1lockS) -> u8 { - Page24lock1lockS::to_bits(val) - } -} -#[repr(u8)] -#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] -pub enum Page25lock0noKeyState { - READ_ONLY = 0, - INACCESSIBLE = 0x01, -} -impl Page25lock0noKeyState { - #[inline(always)] - pub const fn from_bits(val: u8) -> Page25lock0noKeyState { - unsafe { core::mem::transmute(val & 0x01) } - } - #[inline(always)] - pub const fn to_bits(self) -> u8 { - unsafe { core::mem::transmute(self) } - } -} -impl From for Page25lock0noKeyState { - #[inline(always)] - fn from(val: u8) -> Page25lock0noKeyState { - Page25lock0noKeyState::from_bits(val) - } -} -impl From for u8 { - #[inline(always)] - fn from(val: Page25lock0noKeyState) -> u8 { - Page25lock0noKeyState::to_bits(val) - } -} -#[repr(u8)] -#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] -pub enum Page25lock1lockBl { - #[doc = "Bootloader permits user reads and writes to this page"] - READ_WRITE = 0, - #[doc = "Bootloader permits user reads of this page"] - READ_ONLY = 0x01, - #[doc = "Do not use. Behaves the same as INACCESSIBLE"] - RESERVED = 0x02, - #[doc = "Bootloader does not permit user access to this page"] - INACCESSIBLE = 0x03, -} -impl Page25lock1lockBl { - #[inline(always)] - pub const fn from_bits(val: u8) -> Page25lock1lockBl { - unsafe { core::mem::transmute(val & 0x03) } - } - #[inline(always)] - pub const fn to_bits(self) -> u8 { - unsafe { core::mem::transmute(self) } - } -} -impl From for Page25lock1lockBl { - #[inline(always)] - fn from(val: u8) -> Page25lock1lockBl { - Page25lock1lockBl::from_bits(val) - } -} -impl From for u8 { - #[inline(always)] - fn from(val: Page25lock1lockBl) -> u8 { - Page25lock1lockBl::to_bits(val) - } -} -#[repr(u8)] -#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] -pub enum Page25lock1lockNs { - #[doc = "Page can be read by Non-secure software, and Secure software may permit Non-secure writes."] - READ_WRITE = 0, - #[doc = "Page can be read by Non-secure software"] - READ_ONLY = 0x01, - #[doc = "Do not use. Behaves the same as INACCESSIBLE."] - RESERVED = 0x02, - #[doc = "Page can not be accessed by Non-secure software."] - INACCESSIBLE = 0x03, -} -impl Page25lock1lockNs { - #[inline(always)] - pub const fn from_bits(val: u8) -> Page25lock1lockNs { - unsafe { core::mem::transmute(val & 0x03) } - } - #[inline(always)] - pub const fn to_bits(self) -> u8 { - unsafe { core::mem::transmute(self) } - } -} -impl From for Page25lock1lockNs { - #[inline(always)] - fn from(val: u8) -> Page25lock1lockNs { - Page25lock1lockNs::from_bits(val) - } -} -impl From for u8 { - #[inline(always)] - fn from(val: Page25lock1lockNs) -> u8 { - Page25lock1lockNs::to_bits(val) - } -} -#[repr(u8)] -#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] -pub enum Page25lock1lockS { - #[doc = "Page is fully accessible by Secure software."] - READ_WRITE = 0, - #[doc = "Page can be read by Secure software, but can not be written."] - READ_ONLY = 0x01, - #[doc = "Do not use. Behaves the same as INACCESSIBLE."] - RESERVED = 0x02, - #[doc = "Page can not be accessed by Secure software."] - INACCESSIBLE = 0x03, -} -impl Page25lock1lockS { - #[inline(always)] - pub const fn from_bits(val: u8) -> Page25lock1lockS { - unsafe { core::mem::transmute(val & 0x03) } - } - #[inline(always)] - pub const fn to_bits(self) -> u8 { - unsafe { core::mem::transmute(self) } - } -} -impl From for Page25lock1lockS { - #[inline(always)] - fn from(val: u8) -> Page25lock1lockS { - Page25lock1lockS::from_bits(val) - } -} -impl From for u8 { - #[inline(always)] - fn from(val: Page25lock1lockS) -> u8 { - Page25lock1lockS::to_bits(val) - } -} -#[repr(u8)] -#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] -pub enum Page26lock0noKeyState { - READ_ONLY = 0, - INACCESSIBLE = 0x01, -} -impl Page26lock0noKeyState { - #[inline(always)] - pub const fn from_bits(val: u8) -> Page26lock0noKeyState { - unsafe { core::mem::transmute(val & 0x01) } - } - #[inline(always)] - pub const fn to_bits(self) -> u8 { - unsafe { core::mem::transmute(self) } - } -} -impl From for Page26lock0noKeyState { - #[inline(always)] - fn from(val: u8) -> Page26lock0noKeyState { - Page26lock0noKeyState::from_bits(val) - } -} -impl From for u8 { - #[inline(always)] - fn from(val: Page26lock0noKeyState) -> u8 { - Page26lock0noKeyState::to_bits(val) - } -} -#[repr(u8)] -#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] -pub enum Page26lock1lockBl { - #[doc = "Bootloader permits user reads and writes to this page"] - READ_WRITE = 0, - #[doc = "Bootloader permits user reads of this page"] - READ_ONLY = 0x01, - #[doc = "Do not use. Behaves the same as INACCESSIBLE"] - RESERVED = 0x02, - #[doc = "Bootloader does not permit user access to this page"] - INACCESSIBLE = 0x03, -} -impl Page26lock1lockBl { - #[inline(always)] - pub const fn from_bits(val: u8) -> Page26lock1lockBl { - unsafe { core::mem::transmute(val & 0x03) } - } - #[inline(always)] - pub const fn to_bits(self) -> u8 { - unsafe { core::mem::transmute(self) } - } -} -impl From for Page26lock1lockBl { - #[inline(always)] - fn from(val: u8) -> Page26lock1lockBl { - Page26lock1lockBl::from_bits(val) - } -} -impl From for u8 { - #[inline(always)] - fn from(val: Page26lock1lockBl) -> u8 { - Page26lock1lockBl::to_bits(val) - } -} -#[repr(u8)] -#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] -pub enum Page26lock1lockNs { - #[doc = "Page can be read by Non-secure software, and Secure software may permit Non-secure writes."] - READ_WRITE = 0, - #[doc = "Page can be read by Non-secure software"] - READ_ONLY = 0x01, - #[doc = "Do not use. Behaves the same as INACCESSIBLE."] - RESERVED = 0x02, - #[doc = "Page can not be accessed by Non-secure software."] - INACCESSIBLE = 0x03, -} -impl Page26lock1lockNs { - #[inline(always)] - pub const fn from_bits(val: u8) -> Page26lock1lockNs { - unsafe { core::mem::transmute(val & 0x03) } - } - #[inline(always)] - pub const fn to_bits(self) -> u8 { - unsafe { core::mem::transmute(self) } - } -} -impl From for Page26lock1lockNs { - #[inline(always)] - fn from(val: u8) -> Page26lock1lockNs { - Page26lock1lockNs::from_bits(val) - } -} -impl From for u8 { - #[inline(always)] - fn from(val: Page26lock1lockNs) -> u8 { - Page26lock1lockNs::to_bits(val) - } -} -#[repr(u8)] -#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] -pub enum Page26lock1lockS { - #[doc = "Page is fully accessible by Secure software."] - READ_WRITE = 0, - #[doc = "Page can be read by Secure software, but can not be written."] - READ_ONLY = 0x01, - #[doc = "Do not use. Behaves the same as INACCESSIBLE."] - RESERVED = 0x02, - #[doc = "Page can not be accessed by Secure software."] - INACCESSIBLE = 0x03, -} -impl Page26lock1lockS { - #[inline(always)] - pub const fn from_bits(val: u8) -> Page26lock1lockS { - unsafe { core::mem::transmute(val & 0x03) } - } - #[inline(always)] - pub const fn to_bits(self) -> u8 { - unsafe { core::mem::transmute(self) } - } -} -impl From for Page26lock1lockS { - #[inline(always)] - fn from(val: u8) -> Page26lock1lockS { - Page26lock1lockS::from_bits(val) - } -} -impl From for u8 { - #[inline(always)] - fn from(val: Page26lock1lockS) -> u8 { - Page26lock1lockS::to_bits(val) - } -} -#[repr(u8)] -#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] -pub enum Page27lock0noKeyState { - READ_ONLY = 0, - INACCESSIBLE = 0x01, -} -impl Page27lock0noKeyState { - #[inline(always)] - pub const fn from_bits(val: u8) -> Page27lock0noKeyState { - unsafe { core::mem::transmute(val & 0x01) } - } - #[inline(always)] - pub const fn to_bits(self) -> u8 { - unsafe { core::mem::transmute(self) } - } -} -impl From for Page27lock0noKeyState { - #[inline(always)] - fn from(val: u8) -> Page27lock0noKeyState { - Page27lock0noKeyState::from_bits(val) - } -} -impl From for u8 { - #[inline(always)] - fn from(val: Page27lock0noKeyState) -> u8 { - Page27lock0noKeyState::to_bits(val) - } -} -#[repr(u8)] -#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] -pub enum Page27lock1lockBl { - #[doc = "Bootloader permits user reads and writes to this page"] - READ_WRITE = 0, - #[doc = "Bootloader permits user reads of this page"] - READ_ONLY = 0x01, - #[doc = "Do not use. Behaves the same as INACCESSIBLE"] - RESERVED = 0x02, - #[doc = "Bootloader does not permit user access to this page"] - INACCESSIBLE = 0x03, -} -impl Page27lock1lockBl { - #[inline(always)] - pub const fn from_bits(val: u8) -> Page27lock1lockBl { - unsafe { core::mem::transmute(val & 0x03) } - } - #[inline(always)] - pub const fn to_bits(self) -> u8 { - unsafe { core::mem::transmute(self) } - } -} -impl From for Page27lock1lockBl { - #[inline(always)] - fn from(val: u8) -> Page27lock1lockBl { - Page27lock1lockBl::from_bits(val) - } -} -impl From for u8 { - #[inline(always)] - fn from(val: Page27lock1lockBl) -> u8 { - Page27lock1lockBl::to_bits(val) - } -} -#[repr(u8)] -#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] -pub enum Page27lock1lockNs { - #[doc = "Page can be read by Non-secure software, and Secure software may permit Non-secure writes."] - READ_WRITE = 0, - #[doc = "Page can be read by Non-secure software"] - READ_ONLY = 0x01, - #[doc = "Do not use. Behaves the same as INACCESSIBLE."] - RESERVED = 0x02, - #[doc = "Page can not be accessed by Non-secure software."] - INACCESSIBLE = 0x03, -} -impl Page27lock1lockNs { - #[inline(always)] - pub const fn from_bits(val: u8) -> Page27lock1lockNs { - unsafe { core::mem::transmute(val & 0x03) } - } - #[inline(always)] - pub const fn to_bits(self) -> u8 { - unsafe { core::mem::transmute(self) } - } -} -impl From for Page27lock1lockNs { - #[inline(always)] - fn from(val: u8) -> Page27lock1lockNs { - Page27lock1lockNs::from_bits(val) - } -} -impl From for u8 { - #[inline(always)] - fn from(val: Page27lock1lockNs) -> u8 { - Page27lock1lockNs::to_bits(val) - } -} -#[repr(u8)] -#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] -pub enum Page27lock1lockS { - #[doc = "Page is fully accessible by Secure software."] - READ_WRITE = 0, - #[doc = "Page can be read by Secure software, but can not be written."] - READ_ONLY = 0x01, - #[doc = "Do not use. Behaves the same as INACCESSIBLE."] - RESERVED = 0x02, - #[doc = "Page can not be accessed by Secure software."] - INACCESSIBLE = 0x03, -} -impl Page27lock1lockS { - #[inline(always)] - pub const fn from_bits(val: u8) -> Page27lock1lockS { - unsafe { core::mem::transmute(val & 0x03) } - } - #[inline(always)] - pub const fn to_bits(self) -> u8 { - unsafe { core::mem::transmute(self) } - } -} -impl From for Page27lock1lockS { - #[inline(always)] - fn from(val: u8) -> Page27lock1lockS { - Page27lock1lockS::from_bits(val) - } -} -impl From for u8 { - #[inline(always)] - fn from(val: Page27lock1lockS) -> u8 { - Page27lock1lockS::to_bits(val) - } -} -#[repr(u8)] -#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] -pub enum Page28lock0noKeyState { - READ_ONLY = 0, - INACCESSIBLE = 0x01, -} -impl Page28lock0noKeyState { - #[inline(always)] - pub const fn from_bits(val: u8) -> Page28lock0noKeyState { - unsafe { core::mem::transmute(val & 0x01) } - } - #[inline(always)] - pub const fn to_bits(self) -> u8 { - unsafe { core::mem::transmute(self) } - } -} -impl From for Page28lock0noKeyState { - #[inline(always)] - fn from(val: u8) -> Page28lock0noKeyState { - Page28lock0noKeyState::from_bits(val) - } -} -impl From for u8 { - #[inline(always)] - fn from(val: Page28lock0noKeyState) -> u8 { - Page28lock0noKeyState::to_bits(val) - } -} -#[repr(u8)] -#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] -pub enum Page28lock1lockBl { - #[doc = "Bootloader permits user reads and writes to this page"] - READ_WRITE = 0, - #[doc = "Bootloader permits user reads of this page"] - READ_ONLY = 0x01, - #[doc = "Do not use. Behaves the same as INACCESSIBLE"] - RESERVED = 0x02, - #[doc = "Bootloader does not permit user access to this page"] - INACCESSIBLE = 0x03, -} -impl Page28lock1lockBl { - #[inline(always)] - pub const fn from_bits(val: u8) -> Page28lock1lockBl { - unsafe { core::mem::transmute(val & 0x03) } - } - #[inline(always)] - pub const fn to_bits(self) -> u8 { - unsafe { core::mem::transmute(self) } - } -} -impl From for Page28lock1lockBl { - #[inline(always)] - fn from(val: u8) -> Page28lock1lockBl { - Page28lock1lockBl::from_bits(val) - } -} -impl From for u8 { - #[inline(always)] - fn from(val: Page28lock1lockBl) -> u8 { - Page28lock1lockBl::to_bits(val) - } -} -#[repr(u8)] -#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] -pub enum Page28lock1lockNs { - #[doc = "Page can be read by Non-secure software, and Secure software may permit Non-secure writes."] - READ_WRITE = 0, - #[doc = "Page can be read by Non-secure software"] - READ_ONLY = 0x01, - #[doc = "Do not use. Behaves the same as INACCESSIBLE."] - RESERVED = 0x02, - #[doc = "Page can not be accessed by Non-secure software."] - INACCESSIBLE = 0x03, -} -impl Page28lock1lockNs { - #[inline(always)] - pub const fn from_bits(val: u8) -> Page28lock1lockNs { - unsafe { core::mem::transmute(val & 0x03) } - } - #[inline(always)] - pub const fn to_bits(self) -> u8 { - unsafe { core::mem::transmute(self) } - } -} -impl From for Page28lock1lockNs { - #[inline(always)] - fn from(val: u8) -> Page28lock1lockNs { - Page28lock1lockNs::from_bits(val) - } -} -impl From for u8 { - #[inline(always)] - fn from(val: Page28lock1lockNs) -> u8 { - Page28lock1lockNs::to_bits(val) - } -} -#[repr(u8)] -#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] -pub enum Page28lock1lockS { - #[doc = "Page is fully accessible by Secure software."] - READ_WRITE = 0, - #[doc = "Page can be read by Secure software, but can not be written."] - READ_ONLY = 0x01, - #[doc = "Do not use. Behaves the same as INACCESSIBLE."] - RESERVED = 0x02, - #[doc = "Page can not be accessed by Secure software."] - INACCESSIBLE = 0x03, -} -impl Page28lock1lockS { - #[inline(always)] - pub const fn from_bits(val: u8) -> Page28lock1lockS { - unsafe { core::mem::transmute(val & 0x03) } - } - #[inline(always)] - pub const fn to_bits(self) -> u8 { - unsafe { core::mem::transmute(self) } - } -} -impl From for Page28lock1lockS { - #[inline(always)] - fn from(val: u8) -> Page28lock1lockS { - Page28lock1lockS::from_bits(val) - } -} -impl From for u8 { - #[inline(always)] - fn from(val: Page28lock1lockS) -> u8 { - Page28lock1lockS::to_bits(val) - } -} -#[repr(u8)] -#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] -pub enum Page29lock0noKeyState { - READ_ONLY = 0, - INACCESSIBLE = 0x01, -} -impl Page29lock0noKeyState { - #[inline(always)] - pub const fn from_bits(val: u8) -> Page29lock0noKeyState { - unsafe { core::mem::transmute(val & 0x01) } - } - #[inline(always)] - pub const fn to_bits(self) -> u8 { - unsafe { core::mem::transmute(self) } - } -} -impl From for Page29lock0noKeyState { - #[inline(always)] - fn from(val: u8) -> Page29lock0noKeyState { - Page29lock0noKeyState::from_bits(val) - } -} -impl From for u8 { - #[inline(always)] - fn from(val: Page29lock0noKeyState) -> u8 { - Page29lock0noKeyState::to_bits(val) - } -} -#[repr(u8)] -#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] -pub enum Page29lock1lockBl { - #[doc = "Bootloader permits user reads and writes to this page"] - READ_WRITE = 0, - #[doc = "Bootloader permits user reads of this page"] - READ_ONLY = 0x01, - #[doc = "Do not use. Behaves the same as INACCESSIBLE"] - RESERVED = 0x02, - #[doc = "Bootloader does not permit user access to this page"] - INACCESSIBLE = 0x03, -} -impl Page29lock1lockBl { - #[inline(always)] - pub const fn from_bits(val: u8) -> Page29lock1lockBl { - unsafe { core::mem::transmute(val & 0x03) } - } - #[inline(always)] - pub const fn to_bits(self) -> u8 { - unsafe { core::mem::transmute(self) } - } -} -impl From for Page29lock1lockBl { - #[inline(always)] - fn from(val: u8) -> Page29lock1lockBl { - Page29lock1lockBl::from_bits(val) - } -} -impl From for u8 { - #[inline(always)] - fn from(val: Page29lock1lockBl) -> u8 { - Page29lock1lockBl::to_bits(val) - } -} -#[repr(u8)] -#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] -pub enum Page29lock1lockNs { - #[doc = "Page can be read by Non-secure software, and Secure software may permit Non-secure writes."] - READ_WRITE = 0, - #[doc = "Page can be read by Non-secure software"] - READ_ONLY = 0x01, - #[doc = "Do not use. Behaves the same as INACCESSIBLE."] - RESERVED = 0x02, - #[doc = "Page can not be accessed by Non-secure software."] - INACCESSIBLE = 0x03, -} -impl Page29lock1lockNs { - #[inline(always)] - pub const fn from_bits(val: u8) -> Page29lock1lockNs { - unsafe { core::mem::transmute(val & 0x03) } - } - #[inline(always)] - pub const fn to_bits(self) -> u8 { - unsafe { core::mem::transmute(self) } - } -} -impl From for Page29lock1lockNs { - #[inline(always)] - fn from(val: u8) -> Page29lock1lockNs { - Page29lock1lockNs::from_bits(val) - } -} -impl From for u8 { - #[inline(always)] - fn from(val: Page29lock1lockNs) -> u8 { - Page29lock1lockNs::to_bits(val) - } -} -#[repr(u8)] -#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] -pub enum Page29lock1lockS { - #[doc = "Page is fully accessible by Secure software."] - READ_WRITE = 0, - #[doc = "Page can be read by Secure software, but can not be written."] - READ_ONLY = 0x01, - #[doc = "Do not use. Behaves the same as INACCESSIBLE."] - RESERVED = 0x02, - #[doc = "Page can not be accessed by Secure software."] - INACCESSIBLE = 0x03, -} -impl Page29lock1lockS { - #[inline(always)] - pub const fn from_bits(val: u8) -> Page29lock1lockS { - unsafe { core::mem::transmute(val & 0x03) } - } - #[inline(always)] - pub const fn to_bits(self) -> u8 { - unsafe { core::mem::transmute(self) } - } -} -impl From for Page29lock1lockS { - #[inline(always)] - fn from(val: u8) -> Page29lock1lockS { - Page29lock1lockS::from_bits(val) - } -} -impl From for u8 { - #[inline(always)] - fn from(val: Page29lock1lockS) -> u8 { - Page29lock1lockS::to_bits(val) - } -} -#[repr(u8)] -#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] -pub enum Page2lock0noKeyState { - READ_ONLY = 0, - INACCESSIBLE = 0x01, -} -impl Page2lock0noKeyState { - #[inline(always)] - pub const fn from_bits(val: u8) -> Page2lock0noKeyState { - unsafe { core::mem::transmute(val & 0x01) } - } - #[inline(always)] - pub const fn to_bits(self) -> u8 { - unsafe { core::mem::transmute(self) } - } -} -impl From for Page2lock0noKeyState { - #[inline(always)] - fn from(val: u8) -> Page2lock0noKeyState { - Page2lock0noKeyState::from_bits(val) - } -} -impl From for u8 { - #[inline(always)] - fn from(val: Page2lock0noKeyState) -> u8 { - Page2lock0noKeyState::to_bits(val) - } -} -#[repr(u8)] -#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] -pub enum Page2lock1lockBl { - #[doc = "Bootloader permits user reads and writes to this page"] - READ_WRITE = 0, - #[doc = "Bootloader permits user reads of this page"] - READ_ONLY = 0x01, - #[doc = "Do not use. Behaves the same as INACCESSIBLE"] - RESERVED = 0x02, - #[doc = "Bootloader does not permit user access to this page"] - INACCESSIBLE = 0x03, -} -impl Page2lock1lockBl { - #[inline(always)] - pub const fn from_bits(val: u8) -> Page2lock1lockBl { - unsafe { core::mem::transmute(val & 0x03) } - } - #[inline(always)] - pub const fn to_bits(self) -> u8 { - unsafe { core::mem::transmute(self) } - } -} -impl From for Page2lock1lockBl { - #[inline(always)] - fn from(val: u8) -> Page2lock1lockBl { - Page2lock1lockBl::from_bits(val) - } -} -impl From for u8 { - #[inline(always)] - fn from(val: Page2lock1lockBl) -> u8 { - Page2lock1lockBl::to_bits(val) - } -} -#[repr(u8)] -#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] -pub enum Page2lock1lockNs { - #[doc = "Page can be read by Non-secure software, and Secure software may permit Non-secure writes."] - READ_WRITE = 0, - #[doc = "Page can be read by Non-secure software"] - READ_ONLY = 0x01, - #[doc = "Do not use. Behaves the same as INACCESSIBLE."] - RESERVED = 0x02, - #[doc = "Page can not be accessed by Non-secure software."] - INACCESSIBLE = 0x03, -} -impl Page2lock1lockNs { - #[inline(always)] - pub const fn from_bits(val: u8) -> Page2lock1lockNs { - unsafe { core::mem::transmute(val & 0x03) } - } - #[inline(always)] - pub const fn to_bits(self) -> u8 { - unsafe { core::mem::transmute(self) } - } -} -impl From for Page2lock1lockNs { - #[inline(always)] - fn from(val: u8) -> Page2lock1lockNs { - Page2lock1lockNs::from_bits(val) - } -} -impl From for u8 { - #[inline(always)] - fn from(val: Page2lock1lockNs) -> u8 { - Page2lock1lockNs::to_bits(val) - } -} -#[repr(u8)] -#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] -pub enum Page2lock1lockS { - #[doc = "Page is fully accessible by Secure software."] - READ_WRITE = 0, - #[doc = "Page can be read by Secure software, but can not be written."] - READ_ONLY = 0x01, - #[doc = "Do not use. Behaves the same as INACCESSIBLE."] - RESERVED = 0x02, - #[doc = "Page can not be accessed by Secure software."] - INACCESSIBLE = 0x03, -} -impl Page2lock1lockS { - #[inline(always)] - pub const fn from_bits(val: u8) -> Page2lock1lockS { - unsafe { core::mem::transmute(val & 0x03) } - } - #[inline(always)] - pub const fn to_bits(self) -> u8 { - unsafe { core::mem::transmute(self) } - } -} -impl From for Page2lock1lockS { - #[inline(always)] - fn from(val: u8) -> Page2lock1lockS { - Page2lock1lockS::from_bits(val) - } -} -impl From for u8 { - #[inline(always)] - fn from(val: Page2lock1lockS) -> u8 { - Page2lock1lockS::to_bits(val) - } -} -#[repr(u8)] -#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] -pub enum Page30lock0noKeyState { - READ_ONLY = 0, - INACCESSIBLE = 0x01, -} -impl Page30lock0noKeyState { - #[inline(always)] - pub const fn from_bits(val: u8) -> Page30lock0noKeyState { - unsafe { core::mem::transmute(val & 0x01) } - } - #[inline(always)] - pub const fn to_bits(self) -> u8 { - unsafe { core::mem::transmute(self) } - } -} -impl From for Page30lock0noKeyState { - #[inline(always)] - fn from(val: u8) -> Page30lock0noKeyState { - Page30lock0noKeyState::from_bits(val) - } -} -impl From for u8 { - #[inline(always)] - fn from(val: Page30lock0noKeyState) -> u8 { - Page30lock0noKeyState::to_bits(val) - } -} -#[repr(u8)] -#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] -pub enum Page30lock1lockBl { - #[doc = "Bootloader permits user reads and writes to this page"] - READ_WRITE = 0, - #[doc = "Bootloader permits user reads of this page"] - READ_ONLY = 0x01, - #[doc = "Do not use. Behaves the same as INACCESSIBLE"] - RESERVED = 0x02, - #[doc = "Bootloader does not permit user access to this page"] - INACCESSIBLE = 0x03, -} -impl Page30lock1lockBl { - #[inline(always)] - pub const fn from_bits(val: u8) -> Page30lock1lockBl { - unsafe { core::mem::transmute(val & 0x03) } - } - #[inline(always)] - pub const fn to_bits(self) -> u8 { - unsafe { core::mem::transmute(self) } - } -} -impl From for Page30lock1lockBl { - #[inline(always)] - fn from(val: u8) -> Page30lock1lockBl { - Page30lock1lockBl::from_bits(val) - } -} -impl From for u8 { - #[inline(always)] - fn from(val: Page30lock1lockBl) -> u8 { - Page30lock1lockBl::to_bits(val) - } -} -#[repr(u8)] -#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] -pub enum Page30lock1lockNs { - #[doc = "Page can be read by Non-secure software, and Secure software may permit Non-secure writes."] - READ_WRITE = 0, - #[doc = "Page can be read by Non-secure software"] - READ_ONLY = 0x01, - #[doc = "Do not use. Behaves the same as INACCESSIBLE."] - RESERVED = 0x02, - #[doc = "Page can not be accessed by Non-secure software."] - INACCESSIBLE = 0x03, -} -impl Page30lock1lockNs { - #[inline(always)] - pub const fn from_bits(val: u8) -> Page30lock1lockNs { - unsafe { core::mem::transmute(val & 0x03) } - } - #[inline(always)] - pub const fn to_bits(self) -> u8 { - unsafe { core::mem::transmute(self) } - } -} -impl From for Page30lock1lockNs { - #[inline(always)] - fn from(val: u8) -> Page30lock1lockNs { - Page30lock1lockNs::from_bits(val) - } -} -impl From for u8 { - #[inline(always)] - fn from(val: Page30lock1lockNs) -> u8 { - Page30lock1lockNs::to_bits(val) - } -} -#[repr(u8)] -#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] -pub enum Page30lock1lockS { - #[doc = "Page is fully accessible by Secure software."] - READ_WRITE = 0, - #[doc = "Page can be read by Secure software, but can not be written."] - READ_ONLY = 0x01, - #[doc = "Do not use. Behaves the same as INACCESSIBLE."] - RESERVED = 0x02, - #[doc = "Page can not be accessed by Secure software."] - INACCESSIBLE = 0x03, -} -impl Page30lock1lockS { - #[inline(always)] - pub const fn from_bits(val: u8) -> Page30lock1lockS { - unsafe { core::mem::transmute(val & 0x03) } - } - #[inline(always)] - pub const fn to_bits(self) -> u8 { - unsafe { core::mem::transmute(self) } - } -} -impl From for Page30lock1lockS { - #[inline(always)] - fn from(val: u8) -> Page30lock1lockS { - Page30lock1lockS::from_bits(val) - } -} -impl From for u8 { - #[inline(always)] - fn from(val: Page30lock1lockS) -> u8 { - Page30lock1lockS::to_bits(val) - } -} -#[repr(u8)] -#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] -pub enum Page31lock0noKeyState { - READ_ONLY = 0, - INACCESSIBLE = 0x01, -} -impl Page31lock0noKeyState { - #[inline(always)] - pub const fn from_bits(val: u8) -> Page31lock0noKeyState { - unsafe { core::mem::transmute(val & 0x01) } - } - #[inline(always)] - pub const fn to_bits(self) -> u8 { - unsafe { core::mem::transmute(self) } - } -} -impl From for Page31lock0noKeyState { - #[inline(always)] - fn from(val: u8) -> Page31lock0noKeyState { - Page31lock0noKeyState::from_bits(val) - } -} -impl From for u8 { - #[inline(always)] - fn from(val: Page31lock0noKeyState) -> u8 { - Page31lock0noKeyState::to_bits(val) - } -} -#[repr(u8)] -#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] -pub enum Page31lock1lockBl { - #[doc = "Bootloader permits user reads and writes to this page"] - READ_WRITE = 0, - #[doc = "Bootloader permits user reads of this page"] - READ_ONLY = 0x01, - #[doc = "Do not use. Behaves the same as INACCESSIBLE"] - RESERVED = 0x02, - #[doc = "Bootloader does not permit user access to this page"] - INACCESSIBLE = 0x03, -} -impl Page31lock1lockBl { - #[inline(always)] - pub const fn from_bits(val: u8) -> Page31lock1lockBl { - unsafe { core::mem::transmute(val & 0x03) } - } - #[inline(always)] - pub const fn to_bits(self) -> u8 { - unsafe { core::mem::transmute(self) } - } -} -impl From for Page31lock1lockBl { - #[inline(always)] - fn from(val: u8) -> Page31lock1lockBl { - Page31lock1lockBl::from_bits(val) - } -} -impl From for u8 { - #[inline(always)] - fn from(val: Page31lock1lockBl) -> u8 { - Page31lock1lockBl::to_bits(val) - } -} -#[repr(u8)] -#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] -pub enum Page31lock1lockNs { - #[doc = "Page can be read by Non-secure software, and Secure software may permit Non-secure writes."] - READ_WRITE = 0, - #[doc = "Page can be read by Non-secure software"] - READ_ONLY = 0x01, - #[doc = "Do not use. Behaves the same as INACCESSIBLE."] - RESERVED = 0x02, - #[doc = "Page can not be accessed by Non-secure software."] - INACCESSIBLE = 0x03, -} -impl Page31lock1lockNs { - #[inline(always)] - pub const fn from_bits(val: u8) -> Page31lock1lockNs { - unsafe { core::mem::transmute(val & 0x03) } - } - #[inline(always)] - pub const fn to_bits(self) -> u8 { - unsafe { core::mem::transmute(self) } - } -} -impl From for Page31lock1lockNs { - #[inline(always)] - fn from(val: u8) -> Page31lock1lockNs { - Page31lock1lockNs::from_bits(val) - } -} -impl From for u8 { - #[inline(always)] - fn from(val: Page31lock1lockNs) -> u8 { - Page31lock1lockNs::to_bits(val) - } -} -#[repr(u8)] -#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] -pub enum Page31lock1lockS { - #[doc = "Page is fully accessible by Secure software."] - READ_WRITE = 0, - #[doc = "Page can be read by Secure software, but can not be written."] - READ_ONLY = 0x01, - #[doc = "Do not use. Behaves the same as INACCESSIBLE."] - RESERVED = 0x02, - #[doc = "Page can not be accessed by Secure software."] - INACCESSIBLE = 0x03, -} -impl Page31lock1lockS { - #[inline(always)] - pub const fn from_bits(val: u8) -> Page31lock1lockS { - unsafe { core::mem::transmute(val & 0x03) } - } - #[inline(always)] - pub const fn to_bits(self) -> u8 { - unsafe { core::mem::transmute(self) } - } -} -impl From for Page31lock1lockS { - #[inline(always)] - fn from(val: u8) -> Page31lock1lockS { - Page31lock1lockS::from_bits(val) - } -} -impl From for u8 { - #[inline(always)] - fn from(val: Page31lock1lockS) -> u8 { - Page31lock1lockS::to_bits(val) - } -} -#[repr(u8)] -#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] -pub enum Page32lock0noKeyState { - READ_ONLY = 0, - INACCESSIBLE = 0x01, -} -impl Page32lock0noKeyState { - #[inline(always)] - pub const fn from_bits(val: u8) -> Page32lock0noKeyState { - unsafe { core::mem::transmute(val & 0x01) } - } - #[inline(always)] - pub const fn to_bits(self) -> u8 { - unsafe { core::mem::transmute(self) } - } -} -impl From for Page32lock0noKeyState { - #[inline(always)] - fn from(val: u8) -> Page32lock0noKeyState { - Page32lock0noKeyState::from_bits(val) - } -} -impl From for u8 { - #[inline(always)] - fn from(val: Page32lock0noKeyState) -> u8 { - Page32lock0noKeyState::to_bits(val) - } -} -#[repr(u8)] -#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] -pub enum Page32lock1lockBl { - #[doc = "Bootloader permits user reads and writes to this page"] - READ_WRITE = 0, - #[doc = "Bootloader permits user reads of this page"] - READ_ONLY = 0x01, - #[doc = "Do not use. Behaves the same as INACCESSIBLE"] - RESERVED = 0x02, - #[doc = "Bootloader does not permit user access to this page"] - INACCESSIBLE = 0x03, -} -impl Page32lock1lockBl { - #[inline(always)] - pub const fn from_bits(val: u8) -> Page32lock1lockBl { - unsafe { core::mem::transmute(val & 0x03) } - } - #[inline(always)] - pub const fn to_bits(self) -> u8 { - unsafe { core::mem::transmute(self) } - } -} -impl From for Page32lock1lockBl { - #[inline(always)] - fn from(val: u8) -> Page32lock1lockBl { - Page32lock1lockBl::from_bits(val) - } -} -impl From for u8 { - #[inline(always)] - fn from(val: Page32lock1lockBl) -> u8 { - Page32lock1lockBl::to_bits(val) - } -} -#[repr(u8)] -#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] -pub enum Page32lock1lockNs { - #[doc = "Page can be read by Non-secure software, and Secure software may permit Non-secure writes."] - READ_WRITE = 0, - #[doc = "Page can be read by Non-secure software"] - READ_ONLY = 0x01, - #[doc = "Do not use. Behaves the same as INACCESSIBLE."] - RESERVED = 0x02, - #[doc = "Page can not be accessed by Non-secure software."] - INACCESSIBLE = 0x03, -} -impl Page32lock1lockNs { - #[inline(always)] - pub const fn from_bits(val: u8) -> Page32lock1lockNs { - unsafe { core::mem::transmute(val & 0x03) } - } - #[inline(always)] - pub const fn to_bits(self) -> u8 { - unsafe { core::mem::transmute(self) } - } -} -impl From for Page32lock1lockNs { - #[inline(always)] - fn from(val: u8) -> Page32lock1lockNs { - Page32lock1lockNs::from_bits(val) - } -} -impl From for u8 { - #[inline(always)] - fn from(val: Page32lock1lockNs) -> u8 { - Page32lock1lockNs::to_bits(val) - } -} -#[repr(u8)] -#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] -pub enum Page32lock1lockS { - #[doc = "Page is fully accessible by Secure software."] - READ_WRITE = 0, - #[doc = "Page can be read by Secure software, but can not be written."] - READ_ONLY = 0x01, - #[doc = "Do not use. Behaves the same as INACCESSIBLE."] - RESERVED = 0x02, - #[doc = "Page can not be accessed by Secure software."] - INACCESSIBLE = 0x03, -} -impl Page32lock1lockS { - #[inline(always)] - pub const fn from_bits(val: u8) -> Page32lock1lockS { - unsafe { core::mem::transmute(val & 0x03) } - } - #[inline(always)] - pub const fn to_bits(self) -> u8 { - unsafe { core::mem::transmute(self) } - } -} -impl From for Page32lock1lockS { - #[inline(always)] - fn from(val: u8) -> Page32lock1lockS { - Page32lock1lockS::from_bits(val) - } -} -impl From for u8 { - #[inline(always)] - fn from(val: Page32lock1lockS) -> u8 { - Page32lock1lockS::to_bits(val) - } -} -#[repr(u8)] -#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] -pub enum Page33lock0noKeyState { - READ_ONLY = 0, - INACCESSIBLE = 0x01, -} -impl Page33lock0noKeyState { - #[inline(always)] - pub const fn from_bits(val: u8) -> Page33lock0noKeyState { - unsafe { core::mem::transmute(val & 0x01) } - } - #[inline(always)] - pub const fn to_bits(self) -> u8 { - unsafe { core::mem::transmute(self) } - } -} -impl From for Page33lock0noKeyState { - #[inline(always)] - fn from(val: u8) -> Page33lock0noKeyState { - Page33lock0noKeyState::from_bits(val) - } -} -impl From for u8 { - #[inline(always)] - fn from(val: Page33lock0noKeyState) -> u8 { - Page33lock0noKeyState::to_bits(val) - } -} -#[repr(u8)] -#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] -pub enum Page33lock1lockBl { - #[doc = "Bootloader permits user reads and writes to this page"] - READ_WRITE = 0, - #[doc = "Bootloader permits user reads of this page"] - READ_ONLY = 0x01, - #[doc = "Do not use. Behaves the same as INACCESSIBLE"] - RESERVED = 0x02, - #[doc = "Bootloader does not permit user access to this page"] - INACCESSIBLE = 0x03, -} -impl Page33lock1lockBl { - #[inline(always)] - pub const fn from_bits(val: u8) -> Page33lock1lockBl { - unsafe { core::mem::transmute(val & 0x03) } - } - #[inline(always)] - pub const fn to_bits(self) -> u8 { - unsafe { core::mem::transmute(self) } - } -} -impl From for Page33lock1lockBl { - #[inline(always)] - fn from(val: u8) -> Page33lock1lockBl { - Page33lock1lockBl::from_bits(val) - } -} -impl From for u8 { - #[inline(always)] - fn from(val: Page33lock1lockBl) -> u8 { - Page33lock1lockBl::to_bits(val) - } -} -#[repr(u8)] -#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] -pub enum Page33lock1lockNs { - #[doc = "Page can be read by Non-secure software, and Secure software may permit Non-secure writes."] - READ_WRITE = 0, - #[doc = "Page can be read by Non-secure software"] - READ_ONLY = 0x01, - #[doc = "Do not use. Behaves the same as INACCESSIBLE."] - RESERVED = 0x02, - #[doc = "Page can not be accessed by Non-secure software."] - INACCESSIBLE = 0x03, -} -impl Page33lock1lockNs { - #[inline(always)] - pub const fn from_bits(val: u8) -> Page33lock1lockNs { - unsafe { core::mem::transmute(val & 0x03) } - } - #[inline(always)] - pub const fn to_bits(self) -> u8 { - unsafe { core::mem::transmute(self) } - } -} -impl From for Page33lock1lockNs { - #[inline(always)] - fn from(val: u8) -> Page33lock1lockNs { - Page33lock1lockNs::from_bits(val) - } -} -impl From for u8 { - #[inline(always)] - fn from(val: Page33lock1lockNs) -> u8 { - Page33lock1lockNs::to_bits(val) - } -} -#[repr(u8)] -#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] -pub enum Page33lock1lockS { - #[doc = "Page is fully accessible by Secure software."] - READ_WRITE = 0, - #[doc = "Page can be read by Secure software, but can not be written."] - READ_ONLY = 0x01, - #[doc = "Do not use. Behaves the same as INACCESSIBLE."] - RESERVED = 0x02, - #[doc = "Page can not be accessed by Secure software."] - INACCESSIBLE = 0x03, -} -impl Page33lock1lockS { - #[inline(always)] - pub const fn from_bits(val: u8) -> Page33lock1lockS { - unsafe { core::mem::transmute(val & 0x03) } - } - #[inline(always)] - pub const fn to_bits(self) -> u8 { - unsafe { core::mem::transmute(self) } - } -} -impl From for Page33lock1lockS { - #[inline(always)] - fn from(val: u8) -> Page33lock1lockS { - Page33lock1lockS::from_bits(val) - } -} -impl From for u8 { - #[inline(always)] - fn from(val: Page33lock1lockS) -> u8 { - Page33lock1lockS::to_bits(val) - } -} -#[repr(u8)] -#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] -pub enum Page34lock0noKeyState { - READ_ONLY = 0, - INACCESSIBLE = 0x01, -} -impl Page34lock0noKeyState { - #[inline(always)] - pub const fn from_bits(val: u8) -> Page34lock0noKeyState { - unsafe { core::mem::transmute(val & 0x01) } - } - #[inline(always)] - pub const fn to_bits(self) -> u8 { - unsafe { core::mem::transmute(self) } - } -} -impl From for Page34lock0noKeyState { - #[inline(always)] - fn from(val: u8) -> Page34lock0noKeyState { - Page34lock0noKeyState::from_bits(val) - } -} -impl From for u8 { - #[inline(always)] - fn from(val: Page34lock0noKeyState) -> u8 { - Page34lock0noKeyState::to_bits(val) - } -} -#[repr(u8)] -#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] -pub enum Page34lock1lockBl { - #[doc = "Bootloader permits user reads and writes to this page"] - READ_WRITE = 0, - #[doc = "Bootloader permits user reads of this page"] - READ_ONLY = 0x01, - #[doc = "Do not use. Behaves the same as INACCESSIBLE"] - RESERVED = 0x02, - #[doc = "Bootloader does not permit user access to this page"] - INACCESSIBLE = 0x03, -} -impl Page34lock1lockBl { - #[inline(always)] - pub const fn from_bits(val: u8) -> Page34lock1lockBl { - unsafe { core::mem::transmute(val & 0x03) } - } - #[inline(always)] - pub const fn to_bits(self) -> u8 { - unsafe { core::mem::transmute(self) } - } -} -impl From for Page34lock1lockBl { - #[inline(always)] - fn from(val: u8) -> Page34lock1lockBl { - Page34lock1lockBl::from_bits(val) - } -} -impl From for u8 { - #[inline(always)] - fn from(val: Page34lock1lockBl) -> u8 { - Page34lock1lockBl::to_bits(val) - } -} -#[repr(u8)] -#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] -pub enum Page34lock1lockNs { - #[doc = "Page can be read by Non-secure software, and Secure software may permit Non-secure writes."] - READ_WRITE = 0, - #[doc = "Page can be read by Non-secure software"] - READ_ONLY = 0x01, - #[doc = "Do not use. Behaves the same as INACCESSIBLE."] - RESERVED = 0x02, - #[doc = "Page can not be accessed by Non-secure software."] - INACCESSIBLE = 0x03, -} -impl Page34lock1lockNs { - #[inline(always)] - pub const fn from_bits(val: u8) -> Page34lock1lockNs { - unsafe { core::mem::transmute(val & 0x03) } - } - #[inline(always)] - pub const fn to_bits(self) -> u8 { - unsafe { core::mem::transmute(self) } - } -} -impl From for Page34lock1lockNs { - #[inline(always)] - fn from(val: u8) -> Page34lock1lockNs { - Page34lock1lockNs::from_bits(val) - } -} -impl From for u8 { - #[inline(always)] - fn from(val: Page34lock1lockNs) -> u8 { - Page34lock1lockNs::to_bits(val) - } -} -#[repr(u8)] -#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] -pub enum Page34lock1lockS { - #[doc = "Page is fully accessible by Secure software."] - READ_WRITE = 0, - #[doc = "Page can be read by Secure software, but can not be written."] - READ_ONLY = 0x01, - #[doc = "Do not use. Behaves the same as INACCESSIBLE."] - RESERVED = 0x02, - #[doc = "Page can not be accessed by Secure software."] - INACCESSIBLE = 0x03, -} -impl Page34lock1lockS { - #[inline(always)] - pub const fn from_bits(val: u8) -> Page34lock1lockS { - unsafe { core::mem::transmute(val & 0x03) } - } - #[inline(always)] - pub const fn to_bits(self) -> u8 { - unsafe { core::mem::transmute(self) } - } -} -impl From for Page34lock1lockS { - #[inline(always)] - fn from(val: u8) -> Page34lock1lockS { - Page34lock1lockS::from_bits(val) - } -} -impl From for u8 { - #[inline(always)] - fn from(val: Page34lock1lockS) -> u8 { - Page34lock1lockS::to_bits(val) - } -} -#[repr(u8)] -#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] -pub enum Page35lock0noKeyState { - READ_ONLY = 0, - INACCESSIBLE = 0x01, -} -impl Page35lock0noKeyState { - #[inline(always)] - pub const fn from_bits(val: u8) -> Page35lock0noKeyState { - unsafe { core::mem::transmute(val & 0x01) } - } - #[inline(always)] - pub const fn to_bits(self) -> u8 { - unsafe { core::mem::transmute(self) } - } -} -impl From for Page35lock0noKeyState { - #[inline(always)] - fn from(val: u8) -> Page35lock0noKeyState { - Page35lock0noKeyState::from_bits(val) - } -} -impl From for u8 { - #[inline(always)] - fn from(val: Page35lock0noKeyState) -> u8 { - Page35lock0noKeyState::to_bits(val) - } -} -#[repr(u8)] -#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] -pub enum Page35lock1lockBl { - #[doc = "Bootloader permits user reads and writes to this page"] - READ_WRITE = 0, - #[doc = "Bootloader permits user reads of this page"] - READ_ONLY = 0x01, - #[doc = "Do not use. Behaves the same as INACCESSIBLE"] - RESERVED = 0x02, - #[doc = "Bootloader does not permit user access to this page"] - INACCESSIBLE = 0x03, -} -impl Page35lock1lockBl { - #[inline(always)] - pub const fn from_bits(val: u8) -> Page35lock1lockBl { - unsafe { core::mem::transmute(val & 0x03) } - } - #[inline(always)] - pub const fn to_bits(self) -> u8 { - unsafe { core::mem::transmute(self) } - } -} -impl From for Page35lock1lockBl { - #[inline(always)] - fn from(val: u8) -> Page35lock1lockBl { - Page35lock1lockBl::from_bits(val) - } -} -impl From for u8 { - #[inline(always)] - fn from(val: Page35lock1lockBl) -> u8 { - Page35lock1lockBl::to_bits(val) - } -} -#[repr(u8)] -#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] -pub enum Page35lock1lockNs { - #[doc = "Page can be read by Non-secure software, and Secure software may permit Non-secure writes."] - READ_WRITE = 0, - #[doc = "Page can be read by Non-secure software"] - READ_ONLY = 0x01, - #[doc = "Do not use. Behaves the same as INACCESSIBLE."] - RESERVED = 0x02, - #[doc = "Page can not be accessed by Non-secure software."] - INACCESSIBLE = 0x03, -} -impl Page35lock1lockNs { - #[inline(always)] - pub const fn from_bits(val: u8) -> Page35lock1lockNs { - unsafe { core::mem::transmute(val & 0x03) } - } - #[inline(always)] - pub const fn to_bits(self) -> u8 { - unsafe { core::mem::transmute(self) } - } -} -impl From for Page35lock1lockNs { - #[inline(always)] - fn from(val: u8) -> Page35lock1lockNs { - Page35lock1lockNs::from_bits(val) - } -} -impl From for u8 { - #[inline(always)] - fn from(val: Page35lock1lockNs) -> u8 { - Page35lock1lockNs::to_bits(val) - } -} -#[repr(u8)] -#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] -pub enum Page35lock1lockS { - #[doc = "Page is fully accessible by Secure software."] - READ_WRITE = 0, - #[doc = "Page can be read by Secure software, but can not be written."] - READ_ONLY = 0x01, - #[doc = "Do not use. Behaves the same as INACCESSIBLE."] - RESERVED = 0x02, - #[doc = "Page can not be accessed by Secure software."] - INACCESSIBLE = 0x03, -} -impl Page35lock1lockS { - #[inline(always)] - pub const fn from_bits(val: u8) -> Page35lock1lockS { - unsafe { core::mem::transmute(val & 0x03) } - } - #[inline(always)] - pub const fn to_bits(self) -> u8 { - unsafe { core::mem::transmute(self) } - } -} -impl From for Page35lock1lockS { - #[inline(always)] - fn from(val: u8) -> Page35lock1lockS { - Page35lock1lockS::from_bits(val) - } -} -impl From for u8 { - #[inline(always)] - fn from(val: Page35lock1lockS) -> u8 { - Page35lock1lockS::to_bits(val) - } -} -#[repr(u8)] -#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] -pub enum Page36lock0noKeyState { - READ_ONLY = 0, - INACCESSIBLE = 0x01, -} -impl Page36lock0noKeyState { - #[inline(always)] - pub const fn from_bits(val: u8) -> Page36lock0noKeyState { - unsafe { core::mem::transmute(val & 0x01) } - } - #[inline(always)] - pub const fn to_bits(self) -> u8 { - unsafe { core::mem::transmute(self) } - } -} -impl From for Page36lock0noKeyState { - #[inline(always)] - fn from(val: u8) -> Page36lock0noKeyState { - Page36lock0noKeyState::from_bits(val) - } -} -impl From for u8 { - #[inline(always)] - fn from(val: Page36lock0noKeyState) -> u8 { - Page36lock0noKeyState::to_bits(val) - } -} -#[repr(u8)] -#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] -pub enum Page36lock1lockBl { - #[doc = "Bootloader permits user reads and writes to this page"] - READ_WRITE = 0, - #[doc = "Bootloader permits user reads of this page"] - READ_ONLY = 0x01, - #[doc = "Do not use. Behaves the same as INACCESSIBLE"] - RESERVED = 0x02, - #[doc = "Bootloader does not permit user access to this page"] - INACCESSIBLE = 0x03, -} -impl Page36lock1lockBl { - #[inline(always)] - pub const fn from_bits(val: u8) -> Page36lock1lockBl { - unsafe { core::mem::transmute(val & 0x03) } - } - #[inline(always)] - pub const fn to_bits(self) -> u8 { - unsafe { core::mem::transmute(self) } - } -} -impl From for Page36lock1lockBl { - #[inline(always)] - fn from(val: u8) -> Page36lock1lockBl { - Page36lock1lockBl::from_bits(val) - } -} -impl From for u8 { - #[inline(always)] - fn from(val: Page36lock1lockBl) -> u8 { - Page36lock1lockBl::to_bits(val) - } -} -#[repr(u8)] -#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] -pub enum Page36lock1lockNs { - #[doc = "Page can be read by Non-secure software, and Secure software may permit Non-secure writes."] - READ_WRITE = 0, - #[doc = "Page can be read by Non-secure software"] - READ_ONLY = 0x01, - #[doc = "Do not use. Behaves the same as INACCESSIBLE."] - RESERVED = 0x02, - #[doc = "Page can not be accessed by Non-secure software."] - INACCESSIBLE = 0x03, -} -impl Page36lock1lockNs { - #[inline(always)] - pub const fn from_bits(val: u8) -> Page36lock1lockNs { - unsafe { core::mem::transmute(val & 0x03) } - } - #[inline(always)] - pub const fn to_bits(self) -> u8 { - unsafe { core::mem::transmute(self) } - } -} -impl From for Page36lock1lockNs { - #[inline(always)] - fn from(val: u8) -> Page36lock1lockNs { - Page36lock1lockNs::from_bits(val) - } -} -impl From for u8 { - #[inline(always)] - fn from(val: Page36lock1lockNs) -> u8 { - Page36lock1lockNs::to_bits(val) - } -} -#[repr(u8)] -#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] -pub enum Page36lock1lockS { - #[doc = "Page is fully accessible by Secure software."] - READ_WRITE = 0, - #[doc = "Page can be read by Secure software, but can not be written."] - READ_ONLY = 0x01, - #[doc = "Do not use. Behaves the same as INACCESSIBLE."] - RESERVED = 0x02, - #[doc = "Page can not be accessed by Secure software."] - INACCESSIBLE = 0x03, -} -impl Page36lock1lockS { - #[inline(always)] - pub const fn from_bits(val: u8) -> Page36lock1lockS { - unsafe { core::mem::transmute(val & 0x03) } - } - #[inline(always)] - pub const fn to_bits(self) -> u8 { - unsafe { core::mem::transmute(self) } - } -} -impl From for Page36lock1lockS { - #[inline(always)] - fn from(val: u8) -> Page36lock1lockS { - Page36lock1lockS::from_bits(val) - } -} -impl From for u8 { - #[inline(always)] - fn from(val: Page36lock1lockS) -> u8 { - Page36lock1lockS::to_bits(val) - } -} -#[repr(u8)] -#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] -pub enum Page37lock0noKeyState { - READ_ONLY = 0, - INACCESSIBLE = 0x01, -} -impl Page37lock0noKeyState { - #[inline(always)] - pub const fn from_bits(val: u8) -> Page37lock0noKeyState { - unsafe { core::mem::transmute(val & 0x01) } - } - #[inline(always)] - pub const fn to_bits(self) -> u8 { - unsafe { core::mem::transmute(self) } - } -} -impl From for Page37lock0noKeyState { - #[inline(always)] - fn from(val: u8) -> Page37lock0noKeyState { - Page37lock0noKeyState::from_bits(val) - } -} -impl From for u8 { - #[inline(always)] - fn from(val: Page37lock0noKeyState) -> u8 { - Page37lock0noKeyState::to_bits(val) - } -} -#[repr(u8)] -#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] -pub enum Page37lock1lockBl { - #[doc = "Bootloader permits user reads and writes to this page"] - READ_WRITE = 0, - #[doc = "Bootloader permits user reads of this page"] - READ_ONLY = 0x01, - #[doc = "Do not use. Behaves the same as INACCESSIBLE"] - RESERVED = 0x02, - #[doc = "Bootloader does not permit user access to this page"] - INACCESSIBLE = 0x03, -} -impl Page37lock1lockBl { - #[inline(always)] - pub const fn from_bits(val: u8) -> Page37lock1lockBl { - unsafe { core::mem::transmute(val & 0x03) } - } - #[inline(always)] - pub const fn to_bits(self) -> u8 { - unsafe { core::mem::transmute(self) } - } -} -impl From for Page37lock1lockBl { - #[inline(always)] - fn from(val: u8) -> Page37lock1lockBl { - Page37lock1lockBl::from_bits(val) - } -} -impl From for u8 { - #[inline(always)] - fn from(val: Page37lock1lockBl) -> u8 { - Page37lock1lockBl::to_bits(val) - } -} -#[repr(u8)] -#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] -pub enum Page37lock1lockNs { - #[doc = "Page can be read by Non-secure software, and Secure software may permit Non-secure writes."] - READ_WRITE = 0, - #[doc = "Page can be read by Non-secure software"] - READ_ONLY = 0x01, - #[doc = "Do not use. Behaves the same as INACCESSIBLE."] - RESERVED = 0x02, - #[doc = "Page can not be accessed by Non-secure software."] - INACCESSIBLE = 0x03, -} -impl Page37lock1lockNs { - #[inline(always)] - pub const fn from_bits(val: u8) -> Page37lock1lockNs { - unsafe { core::mem::transmute(val & 0x03) } - } - #[inline(always)] - pub const fn to_bits(self) -> u8 { - unsafe { core::mem::transmute(self) } - } -} -impl From for Page37lock1lockNs { - #[inline(always)] - fn from(val: u8) -> Page37lock1lockNs { - Page37lock1lockNs::from_bits(val) - } -} -impl From for u8 { - #[inline(always)] - fn from(val: Page37lock1lockNs) -> u8 { - Page37lock1lockNs::to_bits(val) - } -} -#[repr(u8)] -#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] -pub enum Page37lock1lockS { - #[doc = "Page is fully accessible by Secure software."] - READ_WRITE = 0, - #[doc = "Page can be read by Secure software, but can not be written."] - READ_ONLY = 0x01, - #[doc = "Do not use. Behaves the same as INACCESSIBLE."] - RESERVED = 0x02, - #[doc = "Page can not be accessed by Secure software."] - INACCESSIBLE = 0x03, -} -impl Page37lock1lockS { - #[inline(always)] - pub const fn from_bits(val: u8) -> Page37lock1lockS { - unsafe { core::mem::transmute(val & 0x03) } - } - #[inline(always)] - pub const fn to_bits(self) -> u8 { - unsafe { core::mem::transmute(self) } - } -} -impl From for Page37lock1lockS { - #[inline(always)] - fn from(val: u8) -> Page37lock1lockS { - Page37lock1lockS::from_bits(val) - } -} -impl From for u8 { - #[inline(always)] - fn from(val: Page37lock1lockS) -> u8 { - Page37lock1lockS::to_bits(val) - } -} -#[repr(u8)] -#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] -pub enum Page38lock0noKeyState { - READ_ONLY = 0, - INACCESSIBLE = 0x01, -} -impl Page38lock0noKeyState { - #[inline(always)] - pub const fn from_bits(val: u8) -> Page38lock0noKeyState { - unsafe { core::mem::transmute(val & 0x01) } - } - #[inline(always)] - pub const fn to_bits(self) -> u8 { - unsafe { core::mem::transmute(self) } - } -} -impl From for Page38lock0noKeyState { - #[inline(always)] - fn from(val: u8) -> Page38lock0noKeyState { - Page38lock0noKeyState::from_bits(val) - } -} -impl From for u8 { - #[inline(always)] - fn from(val: Page38lock0noKeyState) -> u8 { - Page38lock0noKeyState::to_bits(val) - } -} -#[repr(u8)] -#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] -pub enum Page38lock1lockBl { - #[doc = "Bootloader permits user reads and writes to this page"] - READ_WRITE = 0, - #[doc = "Bootloader permits user reads of this page"] - READ_ONLY = 0x01, - #[doc = "Do not use. Behaves the same as INACCESSIBLE"] - RESERVED = 0x02, - #[doc = "Bootloader does not permit user access to this page"] - INACCESSIBLE = 0x03, -} -impl Page38lock1lockBl { - #[inline(always)] - pub const fn from_bits(val: u8) -> Page38lock1lockBl { - unsafe { core::mem::transmute(val & 0x03) } - } - #[inline(always)] - pub const fn to_bits(self) -> u8 { - unsafe { core::mem::transmute(self) } - } -} -impl From for Page38lock1lockBl { - #[inline(always)] - fn from(val: u8) -> Page38lock1lockBl { - Page38lock1lockBl::from_bits(val) - } -} -impl From for u8 { - #[inline(always)] - fn from(val: Page38lock1lockBl) -> u8 { - Page38lock1lockBl::to_bits(val) - } -} -#[repr(u8)] -#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] -pub enum Page38lock1lockNs { - #[doc = "Page can be read by Non-secure software, and Secure software may permit Non-secure writes."] - READ_WRITE = 0, - #[doc = "Page can be read by Non-secure software"] - READ_ONLY = 0x01, - #[doc = "Do not use. Behaves the same as INACCESSIBLE."] - RESERVED = 0x02, - #[doc = "Page can not be accessed by Non-secure software."] - INACCESSIBLE = 0x03, -} -impl Page38lock1lockNs { - #[inline(always)] - pub const fn from_bits(val: u8) -> Page38lock1lockNs { - unsafe { core::mem::transmute(val & 0x03) } - } - #[inline(always)] - pub const fn to_bits(self) -> u8 { - unsafe { core::mem::transmute(self) } - } -} -impl From for Page38lock1lockNs { - #[inline(always)] - fn from(val: u8) -> Page38lock1lockNs { - Page38lock1lockNs::from_bits(val) - } -} -impl From for u8 { - #[inline(always)] - fn from(val: Page38lock1lockNs) -> u8 { - Page38lock1lockNs::to_bits(val) - } -} -#[repr(u8)] -#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] -pub enum Page38lock1lockS { - #[doc = "Page is fully accessible by Secure software."] - READ_WRITE = 0, - #[doc = "Page can be read by Secure software, but can not be written."] - READ_ONLY = 0x01, - #[doc = "Do not use. Behaves the same as INACCESSIBLE."] - RESERVED = 0x02, - #[doc = "Page can not be accessed by Secure software."] - INACCESSIBLE = 0x03, -} -impl Page38lock1lockS { - #[inline(always)] - pub const fn from_bits(val: u8) -> Page38lock1lockS { - unsafe { core::mem::transmute(val & 0x03) } - } - #[inline(always)] - pub const fn to_bits(self) -> u8 { - unsafe { core::mem::transmute(self) } - } -} -impl From for Page38lock1lockS { - #[inline(always)] - fn from(val: u8) -> Page38lock1lockS { - Page38lock1lockS::from_bits(val) - } -} -impl From for u8 { - #[inline(always)] - fn from(val: Page38lock1lockS) -> u8 { - Page38lock1lockS::to_bits(val) - } -} -#[repr(u8)] -#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] -pub enum Page39lock0noKeyState { - READ_ONLY = 0, - INACCESSIBLE = 0x01, -} -impl Page39lock0noKeyState { - #[inline(always)] - pub const fn from_bits(val: u8) -> Page39lock0noKeyState { - unsafe { core::mem::transmute(val & 0x01) } - } - #[inline(always)] - pub const fn to_bits(self) -> u8 { - unsafe { core::mem::transmute(self) } - } -} -impl From for Page39lock0noKeyState { - #[inline(always)] - fn from(val: u8) -> Page39lock0noKeyState { - Page39lock0noKeyState::from_bits(val) - } -} -impl From for u8 { - #[inline(always)] - fn from(val: Page39lock0noKeyState) -> u8 { - Page39lock0noKeyState::to_bits(val) - } -} -#[repr(u8)] -#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] -pub enum Page39lock1lockBl { - #[doc = "Bootloader permits user reads and writes to this page"] - READ_WRITE = 0, - #[doc = "Bootloader permits user reads of this page"] - READ_ONLY = 0x01, - #[doc = "Do not use. Behaves the same as INACCESSIBLE"] - RESERVED = 0x02, - #[doc = "Bootloader does not permit user access to this page"] - INACCESSIBLE = 0x03, -} -impl Page39lock1lockBl { - #[inline(always)] - pub const fn from_bits(val: u8) -> Page39lock1lockBl { - unsafe { core::mem::transmute(val & 0x03) } - } - #[inline(always)] - pub const fn to_bits(self) -> u8 { - unsafe { core::mem::transmute(self) } - } -} -impl From for Page39lock1lockBl { - #[inline(always)] - fn from(val: u8) -> Page39lock1lockBl { - Page39lock1lockBl::from_bits(val) - } -} -impl From for u8 { - #[inline(always)] - fn from(val: Page39lock1lockBl) -> u8 { - Page39lock1lockBl::to_bits(val) - } -} -#[repr(u8)] -#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] -pub enum Page39lock1lockNs { - #[doc = "Page can be read by Non-secure software, and Secure software may permit Non-secure writes."] - READ_WRITE = 0, - #[doc = "Page can be read by Non-secure software"] - READ_ONLY = 0x01, - #[doc = "Do not use. Behaves the same as INACCESSIBLE."] - RESERVED = 0x02, - #[doc = "Page can not be accessed by Non-secure software."] - INACCESSIBLE = 0x03, -} -impl Page39lock1lockNs { - #[inline(always)] - pub const fn from_bits(val: u8) -> Page39lock1lockNs { - unsafe { core::mem::transmute(val & 0x03) } - } - #[inline(always)] - pub const fn to_bits(self) -> u8 { - unsafe { core::mem::transmute(self) } - } -} -impl From for Page39lock1lockNs { - #[inline(always)] - fn from(val: u8) -> Page39lock1lockNs { - Page39lock1lockNs::from_bits(val) - } -} -impl From for u8 { - #[inline(always)] - fn from(val: Page39lock1lockNs) -> u8 { - Page39lock1lockNs::to_bits(val) - } -} -#[repr(u8)] -#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] -pub enum Page39lock1lockS { - #[doc = "Page is fully accessible by Secure software."] - READ_WRITE = 0, - #[doc = "Page can be read by Secure software, but can not be written."] - READ_ONLY = 0x01, - #[doc = "Do not use. Behaves the same as INACCESSIBLE."] - RESERVED = 0x02, - #[doc = "Page can not be accessed by Secure software."] - INACCESSIBLE = 0x03, -} -impl Page39lock1lockS { - #[inline(always)] - pub const fn from_bits(val: u8) -> Page39lock1lockS { - unsafe { core::mem::transmute(val & 0x03) } - } - #[inline(always)] - pub const fn to_bits(self) -> u8 { - unsafe { core::mem::transmute(self) } - } -} -impl From for Page39lock1lockS { - #[inline(always)] - fn from(val: u8) -> Page39lock1lockS { - Page39lock1lockS::from_bits(val) - } -} -impl From for u8 { - #[inline(always)] - fn from(val: Page39lock1lockS) -> u8 { - Page39lock1lockS::to_bits(val) - } -} -#[repr(u8)] -#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] -pub enum Page3lock0noKeyState { - READ_ONLY = 0, - INACCESSIBLE = 0x01, -} -impl Page3lock0noKeyState { - #[inline(always)] - pub const fn from_bits(val: u8) -> Page3lock0noKeyState { - unsafe { core::mem::transmute(val & 0x01) } - } - #[inline(always)] - pub const fn to_bits(self) -> u8 { - unsafe { core::mem::transmute(self) } - } -} -impl From for Page3lock0noKeyState { - #[inline(always)] - fn from(val: u8) -> Page3lock0noKeyState { - Page3lock0noKeyState::from_bits(val) - } -} -impl From for u8 { - #[inline(always)] - fn from(val: Page3lock0noKeyState) -> u8 { - Page3lock0noKeyState::to_bits(val) - } -} -#[repr(u8)] -#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] -pub enum Page3lock1lockBl { - #[doc = "Bootloader permits user reads and writes to this page"] - READ_WRITE = 0, - #[doc = "Bootloader permits user reads of this page"] - READ_ONLY = 0x01, - #[doc = "Do not use. Behaves the same as INACCESSIBLE"] - RESERVED = 0x02, - #[doc = "Bootloader does not permit user access to this page"] - INACCESSIBLE = 0x03, -} -impl Page3lock1lockBl { - #[inline(always)] - pub const fn from_bits(val: u8) -> Page3lock1lockBl { - unsafe { core::mem::transmute(val & 0x03) } - } - #[inline(always)] - pub const fn to_bits(self) -> u8 { - unsafe { core::mem::transmute(self) } - } -} -impl From for Page3lock1lockBl { - #[inline(always)] - fn from(val: u8) -> Page3lock1lockBl { - Page3lock1lockBl::from_bits(val) - } -} -impl From for u8 { - #[inline(always)] - fn from(val: Page3lock1lockBl) -> u8 { - Page3lock1lockBl::to_bits(val) - } -} -#[repr(u8)] -#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] -pub enum Page3lock1lockNs { - #[doc = "Page can be read by Non-secure software, and Secure software may permit Non-secure writes."] - READ_WRITE = 0, - #[doc = "Page can be read by Non-secure software"] - READ_ONLY = 0x01, - #[doc = "Do not use. Behaves the same as INACCESSIBLE."] - RESERVED = 0x02, - #[doc = "Page can not be accessed by Non-secure software."] - INACCESSIBLE = 0x03, -} -impl Page3lock1lockNs { - #[inline(always)] - pub const fn from_bits(val: u8) -> Page3lock1lockNs { - unsafe { core::mem::transmute(val & 0x03) } - } - #[inline(always)] - pub const fn to_bits(self) -> u8 { - unsafe { core::mem::transmute(self) } - } -} -impl From for Page3lock1lockNs { - #[inline(always)] - fn from(val: u8) -> Page3lock1lockNs { - Page3lock1lockNs::from_bits(val) - } -} -impl From for u8 { - #[inline(always)] - fn from(val: Page3lock1lockNs) -> u8 { - Page3lock1lockNs::to_bits(val) - } -} -#[repr(u8)] -#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] -pub enum Page3lock1lockS { - #[doc = "Page is fully accessible by Secure software."] - READ_WRITE = 0, - #[doc = "Page can be read by Secure software, but can not be written."] - READ_ONLY = 0x01, - #[doc = "Do not use. Behaves the same as INACCESSIBLE."] - RESERVED = 0x02, - #[doc = "Page can not be accessed by Secure software."] - INACCESSIBLE = 0x03, -} -impl Page3lock1lockS { - #[inline(always)] - pub const fn from_bits(val: u8) -> Page3lock1lockS { - unsafe { core::mem::transmute(val & 0x03) } - } - #[inline(always)] - pub const fn to_bits(self) -> u8 { - unsafe { core::mem::transmute(self) } - } -} -impl From for Page3lock1lockS { - #[inline(always)] - fn from(val: u8) -> Page3lock1lockS { - Page3lock1lockS::from_bits(val) - } -} -impl From for u8 { - #[inline(always)] - fn from(val: Page3lock1lockS) -> u8 { - Page3lock1lockS::to_bits(val) - } -} -#[repr(u8)] -#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] -pub enum Page40lock0noKeyState { - READ_ONLY = 0, - INACCESSIBLE = 0x01, -} -impl Page40lock0noKeyState { - #[inline(always)] - pub const fn from_bits(val: u8) -> Page40lock0noKeyState { - unsafe { core::mem::transmute(val & 0x01) } - } - #[inline(always)] - pub const fn to_bits(self) -> u8 { - unsafe { core::mem::transmute(self) } - } -} -impl From for Page40lock0noKeyState { - #[inline(always)] - fn from(val: u8) -> Page40lock0noKeyState { - Page40lock0noKeyState::from_bits(val) - } -} -impl From for u8 { - #[inline(always)] - fn from(val: Page40lock0noKeyState) -> u8 { - Page40lock0noKeyState::to_bits(val) - } -} -#[repr(u8)] -#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] -pub enum Page40lock1lockBl { - #[doc = "Bootloader permits user reads and writes to this page"] - READ_WRITE = 0, - #[doc = "Bootloader permits user reads of this page"] - READ_ONLY = 0x01, - #[doc = "Do not use. Behaves the same as INACCESSIBLE"] - RESERVED = 0x02, - #[doc = "Bootloader does not permit user access to this page"] - INACCESSIBLE = 0x03, -} -impl Page40lock1lockBl { - #[inline(always)] - pub const fn from_bits(val: u8) -> Page40lock1lockBl { - unsafe { core::mem::transmute(val & 0x03) } - } - #[inline(always)] - pub const fn to_bits(self) -> u8 { - unsafe { core::mem::transmute(self) } - } -} -impl From for Page40lock1lockBl { - #[inline(always)] - fn from(val: u8) -> Page40lock1lockBl { - Page40lock1lockBl::from_bits(val) - } -} -impl From for u8 { - #[inline(always)] - fn from(val: Page40lock1lockBl) -> u8 { - Page40lock1lockBl::to_bits(val) - } -} -#[repr(u8)] -#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] -pub enum Page40lock1lockNs { - #[doc = "Page can be read by Non-secure software, and Secure software may permit Non-secure writes."] - READ_WRITE = 0, - #[doc = "Page can be read by Non-secure software"] - READ_ONLY = 0x01, - #[doc = "Do not use. Behaves the same as INACCESSIBLE."] - RESERVED = 0x02, - #[doc = "Page can not be accessed by Non-secure software."] - INACCESSIBLE = 0x03, -} -impl Page40lock1lockNs { - #[inline(always)] - pub const fn from_bits(val: u8) -> Page40lock1lockNs { - unsafe { core::mem::transmute(val & 0x03) } - } - #[inline(always)] - pub const fn to_bits(self) -> u8 { - unsafe { core::mem::transmute(self) } - } -} -impl From for Page40lock1lockNs { - #[inline(always)] - fn from(val: u8) -> Page40lock1lockNs { - Page40lock1lockNs::from_bits(val) - } -} -impl From for u8 { - #[inline(always)] - fn from(val: Page40lock1lockNs) -> u8 { - Page40lock1lockNs::to_bits(val) - } -} -#[repr(u8)] -#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] -pub enum Page40lock1lockS { - #[doc = "Page is fully accessible by Secure software."] - READ_WRITE = 0, - #[doc = "Page can be read by Secure software, but can not be written."] - READ_ONLY = 0x01, - #[doc = "Do not use. Behaves the same as INACCESSIBLE."] - RESERVED = 0x02, - #[doc = "Page can not be accessed by Secure software."] - INACCESSIBLE = 0x03, -} -impl Page40lock1lockS { - #[inline(always)] - pub const fn from_bits(val: u8) -> Page40lock1lockS { - unsafe { core::mem::transmute(val & 0x03) } - } - #[inline(always)] - pub const fn to_bits(self) -> u8 { - unsafe { core::mem::transmute(self) } - } -} -impl From for Page40lock1lockS { - #[inline(always)] - fn from(val: u8) -> Page40lock1lockS { - Page40lock1lockS::from_bits(val) - } -} -impl From for u8 { - #[inline(always)] - fn from(val: Page40lock1lockS) -> u8 { - Page40lock1lockS::to_bits(val) - } -} -#[repr(u8)] -#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] -pub enum Page41lock0noKeyState { - READ_ONLY = 0, - INACCESSIBLE = 0x01, -} -impl Page41lock0noKeyState { - #[inline(always)] - pub const fn from_bits(val: u8) -> Page41lock0noKeyState { - unsafe { core::mem::transmute(val & 0x01) } - } - #[inline(always)] - pub const fn to_bits(self) -> u8 { - unsafe { core::mem::transmute(self) } - } -} -impl From for Page41lock0noKeyState { - #[inline(always)] - fn from(val: u8) -> Page41lock0noKeyState { - Page41lock0noKeyState::from_bits(val) - } -} -impl From for u8 { - #[inline(always)] - fn from(val: Page41lock0noKeyState) -> u8 { - Page41lock0noKeyState::to_bits(val) - } -} -#[repr(u8)] -#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] -pub enum Page41lock1lockBl { - #[doc = "Bootloader permits user reads and writes to this page"] - READ_WRITE = 0, - #[doc = "Bootloader permits user reads of this page"] - READ_ONLY = 0x01, - #[doc = "Do not use. Behaves the same as INACCESSIBLE"] - RESERVED = 0x02, - #[doc = "Bootloader does not permit user access to this page"] - INACCESSIBLE = 0x03, -} -impl Page41lock1lockBl { - #[inline(always)] - pub const fn from_bits(val: u8) -> Page41lock1lockBl { - unsafe { core::mem::transmute(val & 0x03) } - } - #[inline(always)] - pub const fn to_bits(self) -> u8 { - unsafe { core::mem::transmute(self) } - } -} -impl From for Page41lock1lockBl { - #[inline(always)] - fn from(val: u8) -> Page41lock1lockBl { - Page41lock1lockBl::from_bits(val) - } -} -impl From for u8 { - #[inline(always)] - fn from(val: Page41lock1lockBl) -> u8 { - Page41lock1lockBl::to_bits(val) - } -} -#[repr(u8)] -#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] -pub enum Page41lock1lockNs { - #[doc = "Page can be read by Non-secure software, and Secure software may permit Non-secure writes."] - READ_WRITE = 0, - #[doc = "Page can be read by Non-secure software"] - READ_ONLY = 0x01, - #[doc = "Do not use. Behaves the same as INACCESSIBLE."] - RESERVED = 0x02, - #[doc = "Page can not be accessed by Non-secure software."] - INACCESSIBLE = 0x03, -} -impl Page41lock1lockNs { - #[inline(always)] - pub const fn from_bits(val: u8) -> Page41lock1lockNs { - unsafe { core::mem::transmute(val & 0x03) } - } - #[inline(always)] - pub const fn to_bits(self) -> u8 { - unsafe { core::mem::transmute(self) } - } -} -impl From for Page41lock1lockNs { - #[inline(always)] - fn from(val: u8) -> Page41lock1lockNs { - Page41lock1lockNs::from_bits(val) - } -} -impl From for u8 { - #[inline(always)] - fn from(val: Page41lock1lockNs) -> u8 { - Page41lock1lockNs::to_bits(val) - } -} -#[repr(u8)] -#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] -pub enum Page41lock1lockS { - #[doc = "Page is fully accessible by Secure software."] - READ_WRITE = 0, - #[doc = "Page can be read by Secure software, but can not be written."] - READ_ONLY = 0x01, - #[doc = "Do not use. Behaves the same as INACCESSIBLE."] - RESERVED = 0x02, - #[doc = "Page can not be accessed by Secure software."] - INACCESSIBLE = 0x03, -} -impl Page41lock1lockS { - #[inline(always)] - pub const fn from_bits(val: u8) -> Page41lock1lockS { - unsafe { core::mem::transmute(val & 0x03) } - } - #[inline(always)] - pub const fn to_bits(self) -> u8 { - unsafe { core::mem::transmute(self) } - } -} -impl From for Page41lock1lockS { - #[inline(always)] - fn from(val: u8) -> Page41lock1lockS { - Page41lock1lockS::from_bits(val) - } -} -impl From for u8 { - #[inline(always)] - fn from(val: Page41lock1lockS) -> u8 { - Page41lock1lockS::to_bits(val) - } -} -#[repr(u8)] -#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] -pub enum Page42lock0noKeyState { - READ_ONLY = 0, - INACCESSIBLE = 0x01, -} -impl Page42lock0noKeyState { - #[inline(always)] - pub const fn from_bits(val: u8) -> Page42lock0noKeyState { - unsafe { core::mem::transmute(val & 0x01) } - } - #[inline(always)] - pub const fn to_bits(self) -> u8 { - unsafe { core::mem::transmute(self) } - } -} -impl From for Page42lock0noKeyState { - #[inline(always)] - fn from(val: u8) -> Page42lock0noKeyState { - Page42lock0noKeyState::from_bits(val) - } -} -impl From for u8 { - #[inline(always)] - fn from(val: Page42lock0noKeyState) -> u8 { - Page42lock0noKeyState::to_bits(val) - } -} -#[repr(u8)] -#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] -pub enum Page42lock1lockBl { - #[doc = "Bootloader permits user reads and writes to this page"] - READ_WRITE = 0, - #[doc = "Bootloader permits user reads of this page"] - READ_ONLY = 0x01, - #[doc = "Do not use. Behaves the same as INACCESSIBLE"] - RESERVED = 0x02, - #[doc = "Bootloader does not permit user access to this page"] - INACCESSIBLE = 0x03, -} -impl Page42lock1lockBl { - #[inline(always)] - pub const fn from_bits(val: u8) -> Page42lock1lockBl { - unsafe { core::mem::transmute(val & 0x03) } - } - #[inline(always)] - pub const fn to_bits(self) -> u8 { - unsafe { core::mem::transmute(self) } - } -} -impl From for Page42lock1lockBl { - #[inline(always)] - fn from(val: u8) -> Page42lock1lockBl { - Page42lock1lockBl::from_bits(val) - } -} -impl From for u8 { - #[inline(always)] - fn from(val: Page42lock1lockBl) -> u8 { - Page42lock1lockBl::to_bits(val) - } -} -#[repr(u8)] -#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] -pub enum Page42lock1lockNs { - #[doc = "Page can be read by Non-secure software, and Secure software may permit Non-secure writes."] - READ_WRITE = 0, - #[doc = "Page can be read by Non-secure software"] - READ_ONLY = 0x01, - #[doc = "Do not use. Behaves the same as INACCESSIBLE."] - RESERVED = 0x02, - #[doc = "Page can not be accessed by Non-secure software."] - INACCESSIBLE = 0x03, -} -impl Page42lock1lockNs { - #[inline(always)] - pub const fn from_bits(val: u8) -> Page42lock1lockNs { - unsafe { core::mem::transmute(val & 0x03) } - } - #[inline(always)] - pub const fn to_bits(self) -> u8 { - unsafe { core::mem::transmute(self) } - } -} -impl From for Page42lock1lockNs { - #[inline(always)] - fn from(val: u8) -> Page42lock1lockNs { - Page42lock1lockNs::from_bits(val) - } -} -impl From for u8 { - #[inline(always)] - fn from(val: Page42lock1lockNs) -> u8 { - Page42lock1lockNs::to_bits(val) - } -} -#[repr(u8)] -#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] -pub enum Page42lock1lockS { - #[doc = "Page is fully accessible by Secure software."] - READ_WRITE = 0, - #[doc = "Page can be read by Secure software, but can not be written."] - READ_ONLY = 0x01, - #[doc = "Do not use. Behaves the same as INACCESSIBLE."] - RESERVED = 0x02, - #[doc = "Page can not be accessed by Secure software."] - INACCESSIBLE = 0x03, -} -impl Page42lock1lockS { - #[inline(always)] - pub const fn from_bits(val: u8) -> Page42lock1lockS { - unsafe { core::mem::transmute(val & 0x03) } - } - #[inline(always)] - pub const fn to_bits(self) -> u8 { - unsafe { core::mem::transmute(self) } - } -} -impl From for Page42lock1lockS { - #[inline(always)] - fn from(val: u8) -> Page42lock1lockS { - Page42lock1lockS::from_bits(val) - } -} -impl From for u8 { - #[inline(always)] - fn from(val: Page42lock1lockS) -> u8 { - Page42lock1lockS::to_bits(val) - } -} -#[repr(u8)] -#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] -pub enum Page43lock0noKeyState { - READ_ONLY = 0, - INACCESSIBLE = 0x01, -} -impl Page43lock0noKeyState { - #[inline(always)] - pub const fn from_bits(val: u8) -> Page43lock0noKeyState { - unsafe { core::mem::transmute(val & 0x01) } - } - #[inline(always)] - pub const fn to_bits(self) -> u8 { - unsafe { core::mem::transmute(self) } - } -} -impl From for Page43lock0noKeyState { - #[inline(always)] - fn from(val: u8) -> Page43lock0noKeyState { - Page43lock0noKeyState::from_bits(val) - } -} -impl From for u8 { - #[inline(always)] - fn from(val: Page43lock0noKeyState) -> u8 { - Page43lock0noKeyState::to_bits(val) - } -} -#[repr(u8)] -#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] -pub enum Page43lock1lockBl { - #[doc = "Bootloader permits user reads and writes to this page"] - READ_WRITE = 0, - #[doc = "Bootloader permits user reads of this page"] - READ_ONLY = 0x01, - #[doc = "Do not use. Behaves the same as INACCESSIBLE"] - RESERVED = 0x02, - #[doc = "Bootloader does not permit user access to this page"] - INACCESSIBLE = 0x03, -} -impl Page43lock1lockBl { - #[inline(always)] - pub const fn from_bits(val: u8) -> Page43lock1lockBl { - unsafe { core::mem::transmute(val & 0x03) } - } - #[inline(always)] - pub const fn to_bits(self) -> u8 { - unsafe { core::mem::transmute(self) } - } -} -impl From for Page43lock1lockBl { - #[inline(always)] - fn from(val: u8) -> Page43lock1lockBl { - Page43lock1lockBl::from_bits(val) - } -} -impl From for u8 { - #[inline(always)] - fn from(val: Page43lock1lockBl) -> u8 { - Page43lock1lockBl::to_bits(val) - } -} -#[repr(u8)] -#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] -pub enum Page43lock1lockNs { - #[doc = "Page can be read by Non-secure software, and Secure software may permit Non-secure writes."] - READ_WRITE = 0, - #[doc = "Page can be read by Non-secure software"] - READ_ONLY = 0x01, - #[doc = "Do not use. Behaves the same as INACCESSIBLE."] - RESERVED = 0x02, - #[doc = "Page can not be accessed by Non-secure software."] - INACCESSIBLE = 0x03, -} -impl Page43lock1lockNs { - #[inline(always)] - pub const fn from_bits(val: u8) -> Page43lock1lockNs { - unsafe { core::mem::transmute(val & 0x03) } - } - #[inline(always)] - pub const fn to_bits(self) -> u8 { - unsafe { core::mem::transmute(self) } - } -} -impl From for Page43lock1lockNs { - #[inline(always)] - fn from(val: u8) -> Page43lock1lockNs { - Page43lock1lockNs::from_bits(val) - } -} -impl From for u8 { - #[inline(always)] - fn from(val: Page43lock1lockNs) -> u8 { - Page43lock1lockNs::to_bits(val) - } -} -#[repr(u8)] -#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] -pub enum Page43lock1lockS { - #[doc = "Page is fully accessible by Secure software."] - READ_WRITE = 0, - #[doc = "Page can be read by Secure software, but can not be written."] - READ_ONLY = 0x01, - #[doc = "Do not use. Behaves the same as INACCESSIBLE."] - RESERVED = 0x02, - #[doc = "Page can not be accessed by Secure software."] - INACCESSIBLE = 0x03, -} -impl Page43lock1lockS { - #[inline(always)] - pub const fn from_bits(val: u8) -> Page43lock1lockS { - unsafe { core::mem::transmute(val & 0x03) } - } - #[inline(always)] - pub const fn to_bits(self) -> u8 { - unsafe { core::mem::transmute(self) } - } -} -impl From for Page43lock1lockS { - #[inline(always)] - fn from(val: u8) -> Page43lock1lockS { - Page43lock1lockS::from_bits(val) - } -} -impl From for u8 { - #[inline(always)] - fn from(val: Page43lock1lockS) -> u8 { - Page43lock1lockS::to_bits(val) - } -} -#[repr(u8)] -#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] -pub enum Page44lock0noKeyState { - READ_ONLY = 0, - INACCESSIBLE = 0x01, -} -impl Page44lock0noKeyState { - #[inline(always)] - pub const fn from_bits(val: u8) -> Page44lock0noKeyState { - unsafe { core::mem::transmute(val & 0x01) } - } - #[inline(always)] - pub const fn to_bits(self) -> u8 { - unsafe { core::mem::transmute(self) } - } -} -impl From for Page44lock0noKeyState { - #[inline(always)] - fn from(val: u8) -> Page44lock0noKeyState { - Page44lock0noKeyState::from_bits(val) - } -} -impl From for u8 { - #[inline(always)] - fn from(val: Page44lock0noKeyState) -> u8 { - Page44lock0noKeyState::to_bits(val) - } -} -#[repr(u8)] -#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] -pub enum Page44lock1lockBl { - #[doc = "Bootloader permits user reads and writes to this page"] - READ_WRITE = 0, - #[doc = "Bootloader permits user reads of this page"] - READ_ONLY = 0x01, - #[doc = "Do not use. Behaves the same as INACCESSIBLE"] - RESERVED = 0x02, - #[doc = "Bootloader does not permit user access to this page"] - INACCESSIBLE = 0x03, -} -impl Page44lock1lockBl { - #[inline(always)] - pub const fn from_bits(val: u8) -> Page44lock1lockBl { - unsafe { core::mem::transmute(val & 0x03) } - } - #[inline(always)] - pub const fn to_bits(self) -> u8 { - unsafe { core::mem::transmute(self) } - } -} -impl From for Page44lock1lockBl { - #[inline(always)] - fn from(val: u8) -> Page44lock1lockBl { - Page44lock1lockBl::from_bits(val) - } -} -impl From for u8 { - #[inline(always)] - fn from(val: Page44lock1lockBl) -> u8 { - Page44lock1lockBl::to_bits(val) - } -} -#[repr(u8)] -#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] -pub enum Page44lock1lockNs { - #[doc = "Page can be read by Non-secure software, and Secure software may permit Non-secure writes."] - READ_WRITE = 0, - #[doc = "Page can be read by Non-secure software"] - READ_ONLY = 0x01, - #[doc = "Do not use. Behaves the same as INACCESSIBLE."] - RESERVED = 0x02, - #[doc = "Page can not be accessed by Non-secure software."] - INACCESSIBLE = 0x03, -} -impl Page44lock1lockNs { - #[inline(always)] - pub const fn from_bits(val: u8) -> Page44lock1lockNs { - unsafe { core::mem::transmute(val & 0x03) } - } - #[inline(always)] - pub const fn to_bits(self) -> u8 { - unsafe { core::mem::transmute(self) } - } -} -impl From for Page44lock1lockNs { - #[inline(always)] - fn from(val: u8) -> Page44lock1lockNs { - Page44lock1lockNs::from_bits(val) - } -} -impl From for u8 { - #[inline(always)] - fn from(val: Page44lock1lockNs) -> u8 { - Page44lock1lockNs::to_bits(val) - } -} -#[repr(u8)] -#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] -pub enum Page44lock1lockS { - #[doc = "Page is fully accessible by Secure software."] - READ_WRITE = 0, - #[doc = "Page can be read by Secure software, but can not be written."] - READ_ONLY = 0x01, - #[doc = "Do not use. Behaves the same as INACCESSIBLE."] - RESERVED = 0x02, - #[doc = "Page can not be accessed by Secure software."] - INACCESSIBLE = 0x03, -} -impl Page44lock1lockS { - #[inline(always)] - pub const fn from_bits(val: u8) -> Page44lock1lockS { - unsafe { core::mem::transmute(val & 0x03) } - } - #[inline(always)] - pub const fn to_bits(self) -> u8 { - unsafe { core::mem::transmute(self) } - } -} -impl From for Page44lock1lockS { - #[inline(always)] - fn from(val: u8) -> Page44lock1lockS { - Page44lock1lockS::from_bits(val) - } -} -impl From for u8 { - #[inline(always)] - fn from(val: Page44lock1lockS) -> u8 { - Page44lock1lockS::to_bits(val) - } -} -#[repr(u8)] -#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] -pub enum Page45lock0noKeyState { - READ_ONLY = 0, - INACCESSIBLE = 0x01, -} -impl Page45lock0noKeyState { - #[inline(always)] - pub const fn from_bits(val: u8) -> Page45lock0noKeyState { - unsafe { core::mem::transmute(val & 0x01) } - } - #[inline(always)] - pub const fn to_bits(self) -> u8 { - unsafe { core::mem::transmute(self) } - } -} -impl From for Page45lock0noKeyState { - #[inline(always)] - fn from(val: u8) -> Page45lock0noKeyState { - Page45lock0noKeyState::from_bits(val) - } -} -impl From for u8 { - #[inline(always)] - fn from(val: Page45lock0noKeyState) -> u8 { - Page45lock0noKeyState::to_bits(val) - } -} -#[repr(u8)] -#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] -pub enum Page45lock1lockBl { - #[doc = "Bootloader permits user reads and writes to this page"] - READ_WRITE = 0, - #[doc = "Bootloader permits user reads of this page"] - READ_ONLY = 0x01, - #[doc = "Do not use. Behaves the same as INACCESSIBLE"] - RESERVED = 0x02, - #[doc = "Bootloader does not permit user access to this page"] - INACCESSIBLE = 0x03, -} -impl Page45lock1lockBl { - #[inline(always)] - pub const fn from_bits(val: u8) -> Page45lock1lockBl { - unsafe { core::mem::transmute(val & 0x03) } - } - #[inline(always)] - pub const fn to_bits(self) -> u8 { - unsafe { core::mem::transmute(self) } - } -} -impl From for Page45lock1lockBl { - #[inline(always)] - fn from(val: u8) -> Page45lock1lockBl { - Page45lock1lockBl::from_bits(val) - } -} -impl From for u8 { - #[inline(always)] - fn from(val: Page45lock1lockBl) -> u8 { - Page45lock1lockBl::to_bits(val) - } -} -#[repr(u8)] -#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] -pub enum Page45lock1lockNs { - #[doc = "Page can be read by Non-secure software, and Secure software may permit Non-secure writes."] - READ_WRITE = 0, - #[doc = "Page can be read by Non-secure software"] - READ_ONLY = 0x01, - #[doc = "Do not use. Behaves the same as INACCESSIBLE."] - RESERVED = 0x02, - #[doc = "Page can not be accessed by Non-secure software."] - INACCESSIBLE = 0x03, -} -impl Page45lock1lockNs { - #[inline(always)] - pub const fn from_bits(val: u8) -> Page45lock1lockNs { - unsafe { core::mem::transmute(val & 0x03) } - } - #[inline(always)] - pub const fn to_bits(self) -> u8 { - unsafe { core::mem::transmute(self) } - } -} -impl From for Page45lock1lockNs { - #[inline(always)] - fn from(val: u8) -> Page45lock1lockNs { - Page45lock1lockNs::from_bits(val) - } -} -impl From for u8 { - #[inline(always)] - fn from(val: Page45lock1lockNs) -> u8 { - Page45lock1lockNs::to_bits(val) - } -} -#[repr(u8)] -#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] -pub enum Page45lock1lockS { - #[doc = "Page is fully accessible by Secure software."] - READ_WRITE = 0, - #[doc = "Page can be read by Secure software, but can not be written."] - READ_ONLY = 0x01, - #[doc = "Do not use. Behaves the same as INACCESSIBLE."] - RESERVED = 0x02, - #[doc = "Page can not be accessed by Secure software."] - INACCESSIBLE = 0x03, -} -impl Page45lock1lockS { - #[inline(always)] - pub const fn from_bits(val: u8) -> Page45lock1lockS { - unsafe { core::mem::transmute(val & 0x03) } - } - #[inline(always)] - pub const fn to_bits(self) -> u8 { - unsafe { core::mem::transmute(self) } - } -} -impl From for Page45lock1lockS { - #[inline(always)] - fn from(val: u8) -> Page45lock1lockS { - Page45lock1lockS::from_bits(val) - } -} -impl From for u8 { - #[inline(always)] - fn from(val: Page45lock1lockS) -> u8 { - Page45lock1lockS::to_bits(val) - } -} -#[repr(u8)] -#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] -pub enum Page46lock0noKeyState { - READ_ONLY = 0, - INACCESSIBLE = 0x01, -} -impl Page46lock0noKeyState { - #[inline(always)] - pub const fn from_bits(val: u8) -> Page46lock0noKeyState { - unsafe { core::mem::transmute(val & 0x01) } - } - #[inline(always)] - pub const fn to_bits(self) -> u8 { - unsafe { core::mem::transmute(self) } - } -} -impl From for Page46lock0noKeyState { - #[inline(always)] - fn from(val: u8) -> Page46lock0noKeyState { - Page46lock0noKeyState::from_bits(val) - } -} -impl From for u8 { - #[inline(always)] - fn from(val: Page46lock0noKeyState) -> u8 { - Page46lock0noKeyState::to_bits(val) - } -} -#[repr(u8)] -#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] -pub enum Page46lock1lockBl { - #[doc = "Bootloader permits user reads and writes to this page"] - READ_WRITE = 0, - #[doc = "Bootloader permits user reads of this page"] - READ_ONLY = 0x01, - #[doc = "Do not use. Behaves the same as INACCESSIBLE"] - RESERVED = 0x02, - #[doc = "Bootloader does not permit user access to this page"] - INACCESSIBLE = 0x03, -} -impl Page46lock1lockBl { - #[inline(always)] - pub const fn from_bits(val: u8) -> Page46lock1lockBl { - unsafe { core::mem::transmute(val & 0x03) } - } - #[inline(always)] - pub const fn to_bits(self) -> u8 { - unsafe { core::mem::transmute(self) } - } -} -impl From for Page46lock1lockBl { - #[inline(always)] - fn from(val: u8) -> Page46lock1lockBl { - Page46lock1lockBl::from_bits(val) - } -} -impl From for u8 { - #[inline(always)] - fn from(val: Page46lock1lockBl) -> u8 { - Page46lock1lockBl::to_bits(val) - } -} -#[repr(u8)] -#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] -pub enum Page46lock1lockNs { - #[doc = "Page can be read by Non-secure software, and Secure software may permit Non-secure writes."] - READ_WRITE = 0, - #[doc = "Page can be read by Non-secure software"] - READ_ONLY = 0x01, - #[doc = "Do not use. Behaves the same as INACCESSIBLE."] - RESERVED = 0x02, - #[doc = "Page can not be accessed by Non-secure software."] - INACCESSIBLE = 0x03, -} -impl Page46lock1lockNs { - #[inline(always)] - pub const fn from_bits(val: u8) -> Page46lock1lockNs { - unsafe { core::mem::transmute(val & 0x03) } - } - #[inline(always)] - pub const fn to_bits(self) -> u8 { - unsafe { core::mem::transmute(self) } - } -} -impl From for Page46lock1lockNs { - #[inline(always)] - fn from(val: u8) -> Page46lock1lockNs { - Page46lock1lockNs::from_bits(val) - } -} -impl From for u8 { - #[inline(always)] - fn from(val: Page46lock1lockNs) -> u8 { - Page46lock1lockNs::to_bits(val) - } -} -#[repr(u8)] -#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] -pub enum Page46lock1lockS { - #[doc = "Page is fully accessible by Secure software."] - READ_WRITE = 0, - #[doc = "Page can be read by Secure software, but can not be written."] - READ_ONLY = 0x01, - #[doc = "Do not use. Behaves the same as INACCESSIBLE."] - RESERVED = 0x02, - #[doc = "Page can not be accessed by Secure software."] - INACCESSIBLE = 0x03, -} -impl Page46lock1lockS { - #[inline(always)] - pub const fn from_bits(val: u8) -> Page46lock1lockS { - unsafe { core::mem::transmute(val & 0x03) } - } - #[inline(always)] - pub const fn to_bits(self) -> u8 { - unsafe { core::mem::transmute(self) } - } -} -impl From for Page46lock1lockS { - #[inline(always)] - fn from(val: u8) -> Page46lock1lockS { - Page46lock1lockS::from_bits(val) - } -} -impl From for u8 { - #[inline(always)] - fn from(val: Page46lock1lockS) -> u8 { - Page46lock1lockS::to_bits(val) - } -} -#[repr(u8)] -#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] -pub enum Page47lock0noKeyState { - READ_ONLY = 0, - INACCESSIBLE = 0x01, -} -impl Page47lock0noKeyState { - #[inline(always)] - pub const fn from_bits(val: u8) -> Page47lock0noKeyState { - unsafe { core::mem::transmute(val & 0x01) } - } - #[inline(always)] - pub const fn to_bits(self) -> u8 { - unsafe { core::mem::transmute(self) } - } -} -impl From for Page47lock0noKeyState { - #[inline(always)] - fn from(val: u8) -> Page47lock0noKeyState { - Page47lock0noKeyState::from_bits(val) - } -} -impl From for u8 { - #[inline(always)] - fn from(val: Page47lock0noKeyState) -> u8 { - Page47lock0noKeyState::to_bits(val) - } -} -#[repr(u8)] -#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] -pub enum Page47lock1lockBl { - #[doc = "Bootloader permits user reads and writes to this page"] - READ_WRITE = 0, - #[doc = "Bootloader permits user reads of this page"] - READ_ONLY = 0x01, - #[doc = "Do not use. Behaves the same as INACCESSIBLE"] - RESERVED = 0x02, - #[doc = "Bootloader does not permit user access to this page"] - INACCESSIBLE = 0x03, -} -impl Page47lock1lockBl { - #[inline(always)] - pub const fn from_bits(val: u8) -> Page47lock1lockBl { - unsafe { core::mem::transmute(val & 0x03) } - } - #[inline(always)] - pub const fn to_bits(self) -> u8 { - unsafe { core::mem::transmute(self) } - } -} -impl From for Page47lock1lockBl { - #[inline(always)] - fn from(val: u8) -> Page47lock1lockBl { - Page47lock1lockBl::from_bits(val) - } -} -impl From for u8 { - #[inline(always)] - fn from(val: Page47lock1lockBl) -> u8 { - Page47lock1lockBl::to_bits(val) - } -} -#[repr(u8)] -#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] -pub enum Page47lock1lockNs { - #[doc = "Page can be read by Non-secure software, and Secure software may permit Non-secure writes."] - READ_WRITE = 0, - #[doc = "Page can be read by Non-secure software"] - READ_ONLY = 0x01, - #[doc = "Do not use. Behaves the same as INACCESSIBLE."] - RESERVED = 0x02, - #[doc = "Page can not be accessed by Non-secure software."] - INACCESSIBLE = 0x03, -} -impl Page47lock1lockNs { - #[inline(always)] - pub const fn from_bits(val: u8) -> Page47lock1lockNs { - unsafe { core::mem::transmute(val & 0x03) } - } - #[inline(always)] - pub const fn to_bits(self) -> u8 { - unsafe { core::mem::transmute(self) } - } -} -impl From for Page47lock1lockNs { - #[inline(always)] - fn from(val: u8) -> Page47lock1lockNs { - Page47lock1lockNs::from_bits(val) - } -} -impl From for u8 { - #[inline(always)] - fn from(val: Page47lock1lockNs) -> u8 { - Page47lock1lockNs::to_bits(val) - } -} -#[repr(u8)] -#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] -pub enum Page47lock1lockS { - #[doc = "Page is fully accessible by Secure software."] - READ_WRITE = 0, - #[doc = "Page can be read by Secure software, but can not be written."] - READ_ONLY = 0x01, - #[doc = "Do not use. Behaves the same as INACCESSIBLE."] - RESERVED = 0x02, - #[doc = "Page can not be accessed by Secure software."] - INACCESSIBLE = 0x03, -} -impl Page47lock1lockS { - #[inline(always)] - pub const fn from_bits(val: u8) -> Page47lock1lockS { - unsafe { core::mem::transmute(val & 0x03) } - } - #[inline(always)] - pub const fn to_bits(self) -> u8 { - unsafe { core::mem::transmute(self) } - } -} -impl From for Page47lock1lockS { - #[inline(always)] - fn from(val: u8) -> Page47lock1lockS { - Page47lock1lockS::from_bits(val) - } -} -impl From for u8 { - #[inline(always)] - fn from(val: Page47lock1lockS) -> u8 { - Page47lock1lockS::to_bits(val) - } -} -#[repr(u8)] -#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] -pub enum Page48lock0noKeyState { - READ_ONLY = 0, - INACCESSIBLE = 0x01, -} -impl Page48lock0noKeyState { - #[inline(always)] - pub const fn from_bits(val: u8) -> Page48lock0noKeyState { - unsafe { core::mem::transmute(val & 0x01) } - } - #[inline(always)] - pub const fn to_bits(self) -> u8 { - unsafe { core::mem::transmute(self) } - } -} -impl From for Page48lock0noKeyState { - #[inline(always)] - fn from(val: u8) -> Page48lock0noKeyState { - Page48lock0noKeyState::from_bits(val) - } -} -impl From for u8 { - #[inline(always)] - fn from(val: Page48lock0noKeyState) -> u8 { - Page48lock0noKeyState::to_bits(val) - } -} -#[repr(u8)] -#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] -pub enum Page48lock1lockBl { - #[doc = "Bootloader permits user reads and writes to this page"] - READ_WRITE = 0, - #[doc = "Bootloader permits user reads of this page"] - READ_ONLY = 0x01, - #[doc = "Do not use. Behaves the same as INACCESSIBLE"] - RESERVED = 0x02, - #[doc = "Bootloader does not permit user access to this page"] - INACCESSIBLE = 0x03, -} -impl Page48lock1lockBl { - #[inline(always)] - pub const fn from_bits(val: u8) -> Page48lock1lockBl { - unsafe { core::mem::transmute(val & 0x03) } - } - #[inline(always)] - pub const fn to_bits(self) -> u8 { - unsafe { core::mem::transmute(self) } - } -} -impl From for Page48lock1lockBl { - #[inline(always)] - fn from(val: u8) -> Page48lock1lockBl { - Page48lock1lockBl::from_bits(val) - } -} -impl From for u8 { - #[inline(always)] - fn from(val: Page48lock1lockBl) -> u8 { - Page48lock1lockBl::to_bits(val) - } -} -#[repr(u8)] -#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] -pub enum Page48lock1lockNs { - #[doc = "Page can be read by Non-secure software, and Secure software may permit Non-secure writes."] - READ_WRITE = 0, - #[doc = "Page can be read by Non-secure software"] - READ_ONLY = 0x01, - #[doc = "Do not use. Behaves the same as INACCESSIBLE."] - RESERVED = 0x02, - #[doc = "Page can not be accessed by Non-secure software."] - INACCESSIBLE = 0x03, -} -impl Page48lock1lockNs { - #[inline(always)] - pub const fn from_bits(val: u8) -> Page48lock1lockNs { - unsafe { core::mem::transmute(val & 0x03) } - } - #[inline(always)] - pub const fn to_bits(self) -> u8 { - unsafe { core::mem::transmute(self) } - } -} -impl From for Page48lock1lockNs { - #[inline(always)] - fn from(val: u8) -> Page48lock1lockNs { - Page48lock1lockNs::from_bits(val) - } -} -impl From for u8 { - #[inline(always)] - fn from(val: Page48lock1lockNs) -> u8 { - Page48lock1lockNs::to_bits(val) - } -} -#[repr(u8)] -#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] -pub enum Page48lock1lockS { - #[doc = "Page is fully accessible by Secure software."] - READ_WRITE = 0, - #[doc = "Page can be read by Secure software, but can not be written."] - READ_ONLY = 0x01, - #[doc = "Do not use. Behaves the same as INACCESSIBLE."] - RESERVED = 0x02, - #[doc = "Page can not be accessed by Secure software."] - INACCESSIBLE = 0x03, -} -impl Page48lock1lockS { - #[inline(always)] - pub const fn from_bits(val: u8) -> Page48lock1lockS { - unsafe { core::mem::transmute(val & 0x03) } - } - #[inline(always)] - pub const fn to_bits(self) -> u8 { - unsafe { core::mem::transmute(self) } - } -} -impl From for Page48lock1lockS { - #[inline(always)] - fn from(val: u8) -> Page48lock1lockS { - Page48lock1lockS::from_bits(val) - } -} -impl From for u8 { - #[inline(always)] - fn from(val: Page48lock1lockS) -> u8 { - Page48lock1lockS::to_bits(val) - } -} -#[repr(u8)] -#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] -pub enum Page49lock0noKeyState { - READ_ONLY = 0, - INACCESSIBLE = 0x01, -} -impl Page49lock0noKeyState { - #[inline(always)] - pub const fn from_bits(val: u8) -> Page49lock0noKeyState { - unsafe { core::mem::transmute(val & 0x01) } - } - #[inline(always)] - pub const fn to_bits(self) -> u8 { - unsafe { core::mem::transmute(self) } - } -} -impl From for Page49lock0noKeyState { - #[inline(always)] - fn from(val: u8) -> Page49lock0noKeyState { - Page49lock0noKeyState::from_bits(val) - } -} -impl From for u8 { - #[inline(always)] - fn from(val: Page49lock0noKeyState) -> u8 { - Page49lock0noKeyState::to_bits(val) - } -} -#[repr(u8)] -#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] -pub enum Page49lock1lockBl { - #[doc = "Bootloader permits user reads and writes to this page"] - READ_WRITE = 0, - #[doc = "Bootloader permits user reads of this page"] - READ_ONLY = 0x01, - #[doc = "Do not use. Behaves the same as INACCESSIBLE"] - RESERVED = 0x02, - #[doc = "Bootloader does not permit user access to this page"] - INACCESSIBLE = 0x03, -} -impl Page49lock1lockBl { - #[inline(always)] - pub const fn from_bits(val: u8) -> Page49lock1lockBl { - unsafe { core::mem::transmute(val & 0x03) } - } - #[inline(always)] - pub const fn to_bits(self) -> u8 { - unsafe { core::mem::transmute(self) } - } -} -impl From for Page49lock1lockBl { - #[inline(always)] - fn from(val: u8) -> Page49lock1lockBl { - Page49lock1lockBl::from_bits(val) - } -} -impl From for u8 { - #[inline(always)] - fn from(val: Page49lock1lockBl) -> u8 { - Page49lock1lockBl::to_bits(val) - } -} -#[repr(u8)] -#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] -pub enum Page49lock1lockNs { - #[doc = "Page can be read by Non-secure software, and Secure software may permit Non-secure writes."] - READ_WRITE = 0, - #[doc = "Page can be read by Non-secure software"] - READ_ONLY = 0x01, - #[doc = "Do not use. Behaves the same as INACCESSIBLE."] - RESERVED = 0x02, - #[doc = "Page can not be accessed by Non-secure software."] - INACCESSIBLE = 0x03, -} -impl Page49lock1lockNs { - #[inline(always)] - pub const fn from_bits(val: u8) -> Page49lock1lockNs { - unsafe { core::mem::transmute(val & 0x03) } - } - #[inline(always)] - pub const fn to_bits(self) -> u8 { - unsafe { core::mem::transmute(self) } - } -} -impl From for Page49lock1lockNs { - #[inline(always)] - fn from(val: u8) -> Page49lock1lockNs { - Page49lock1lockNs::from_bits(val) - } -} -impl From for u8 { - #[inline(always)] - fn from(val: Page49lock1lockNs) -> u8 { - Page49lock1lockNs::to_bits(val) - } -} -#[repr(u8)] -#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] -pub enum Page49lock1lockS { - #[doc = "Page is fully accessible by Secure software."] - READ_WRITE = 0, - #[doc = "Page can be read by Secure software, but can not be written."] - READ_ONLY = 0x01, - #[doc = "Do not use. Behaves the same as INACCESSIBLE."] - RESERVED = 0x02, - #[doc = "Page can not be accessed by Secure software."] - INACCESSIBLE = 0x03, -} -impl Page49lock1lockS { - #[inline(always)] - pub const fn from_bits(val: u8) -> Page49lock1lockS { - unsafe { core::mem::transmute(val & 0x03) } - } - #[inline(always)] - pub const fn to_bits(self) -> u8 { - unsafe { core::mem::transmute(self) } - } -} -impl From for Page49lock1lockS { - #[inline(always)] - fn from(val: u8) -> Page49lock1lockS { - Page49lock1lockS::from_bits(val) - } -} -impl From for u8 { - #[inline(always)] - fn from(val: Page49lock1lockS) -> u8 { - Page49lock1lockS::to_bits(val) - } -} -#[repr(u8)] -#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] -pub enum Page4lock0noKeyState { - READ_ONLY = 0, - INACCESSIBLE = 0x01, -} -impl Page4lock0noKeyState { - #[inline(always)] - pub const fn from_bits(val: u8) -> Page4lock0noKeyState { - unsafe { core::mem::transmute(val & 0x01) } - } - #[inline(always)] - pub const fn to_bits(self) -> u8 { - unsafe { core::mem::transmute(self) } - } -} -impl From for Page4lock0noKeyState { - #[inline(always)] - fn from(val: u8) -> Page4lock0noKeyState { - Page4lock0noKeyState::from_bits(val) - } -} -impl From for u8 { - #[inline(always)] - fn from(val: Page4lock0noKeyState) -> u8 { - Page4lock0noKeyState::to_bits(val) - } -} -#[repr(u8)] -#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] -pub enum Page4lock1lockBl { - #[doc = "Bootloader permits user reads and writes to this page"] - READ_WRITE = 0, - #[doc = "Bootloader permits user reads of this page"] - READ_ONLY = 0x01, - #[doc = "Do not use. Behaves the same as INACCESSIBLE"] - RESERVED = 0x02, - #[doc = "Bootloader does not permit user access to this page"] - INACCESSIBLE = 0x03, -} -impl Page4lock1lockBl { - #[inline(always)] - pub const fn from_bits(val: u8) -> Page4lock1lockBl { - unsafe { core::mem::transmute(val & 0x03) } - } - #[inline(always)] - pub const fn to_bits(self) -> u8 { - unsafe { core::mem::transmute(self) } - } -} -impl From for Page4lock1lockBl { - #[inline(always)] - fn from(val: u8) -> Page4lock1lockBl { - Page4lock1lockBl::from_bits(val) - } -} -impl From for u8 { - #[inline(always)] - fn from(val: Page4lock1lockBl) -> u8 { - Page4lock1lockBl::to_bits(val) - } -} -#[repr(u8)] -#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] -pub enum Page4lock1lockNs { - #[doc = "Page can be read by Non-secure software, and Secure software may permit Non-secure writes."] - READ_WRITE = 0, - #[doc = "Page can be read by Non-secure software"] - READ_ONLY = 0x01, - #[doc = "Do not use. Behaves the same as INACCESSIBLE."] - RESERVED = 0x02, - #[doc = "Page can not be accessed by Non-secure software."] - INACCESSIBLE = 0x03, -} -impl Page4lock1lockNs { - #[inline(always)] - pub const fn from_bits(val: u8) -> Page4lock1lockNs { - unsafe { core::mem::transmute(val & 0x03) } - } - #[inline(always)] - pub const fn to_bits(self) -> u8 { - unsafe { core::mem::transmute(self) } - } -} -impl From for Page4lock1lockNs { - #[inline(always)] - fn from(val: u8) -> Page4lock1lockNs { - Page4lock1lockNs::from_bits(val) - } -} -impl From for u8 { - #[inline(always)] - fn from(val: Page4lock1lockNs) -> u8 { - Page4lock1lockNs::to_bits(val) - } -} -#[repr(u8)] -#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] -pub enum Page4lock1lockS { - #[doc = "Page is fully accessible by Secure software."] - READ_WRITE = 0, - #[doc = "Page can be read by Secure software, but can not be written."] - READ_ONLY = 0x01, - #[doc = "Do not use. Behaves the same as INACCESSIBLE."] - RESERVED = 0x02, - #[doc = "Page can not be accessed by Secure software."] - INACCESSIBLE = 0x03, -} -impl Page4lock1lockS { - #[inline(always)] - pub const fn from_bits(val: u8) -> Page4lock1lockS { - unsafe { core::mem::transmute(val & 0x03) } - } - #[inline(always)] - pub const fn to_bits(self) -> u8 { - unsafe { core::mem::transmute(self) } - } -} -impl From for Page4lock1lockS { - #[inline(always)] - fn from(val: u8) -> Page4lock1lockS { - Page4lock1lockS::from_bits(val) - } -} -impl From for u8 { - #[inline(always)] - fn from(val: Page4lock1lockS) -> u8 { - Page4lock1lockS::to_bits(val) - } -} -#[repr(u8)] -#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] -pub enum Page50lock0noKeyState { - READ_ONLY = 0, - INACCESSIBLE = 0x01, -} -impl Page50lock0noKeyState { - #[inline(always)] - pub const fn from_bits(val: u8) -> Page50lock0noKeyState { - unsafe { core::mem::transmute(val & 0x01) } - } - #[inline(always)] - pub const fn to_bits(self) -> u8 { - unsafe { core::mem::transmute(self) } - } -} -impl From for Page50lock0noKeyState { - #[inline(always)] - fn from(val: u8) -> Page50lock0noKeyState { - Page50lock0noKeyState::from_bits(val) - } -} -impl From for u8 { - #[inline(always)] - fn from(val: Page50lock0noKeyState) -> u8 { - Page50lock0noKeyState::to_bits(val) - } -} -#[repr(u8)] -#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] -pub enum Page50lock1lockBl { - #[doc = "Bootloader permits user reads and writes to this page"] - READ_WRITE = 0, - #[doc = "Bootloader permits user reads of this page"] - READ_ONLY = 0x01, - #[doc = "Do not use. Behaves the same as INACCESSIBLE"] - RESERVED = 0x02, - #[doc = "Bootloader does not permit user access to this page"] - INACCESSIBLE = 0x03, -} -impl Page50lock1lockBl { - #[inline(always)] - pub const fn from_bits(val: u8) -> Page50lock1lockBl { - unsafe { core::mem::transmute(val & 0x03) } - } - #[inline(always)] - pub const fn to_bits(self) -> u8 { - unsafe { core::mem::transmute(self) } - } -} -impl From for Page50lock1lockBl { - #[inline(always)] - fn from(val: u8) -> Page50lock1lockBl { - Page50lock1lockBl::from_bits(val) - } -} -impl From for u8 { - #[inline(always)] - fn from(val: Page50lock1lockBl) -> u8 { - Page50lock1lockBl::to_bits(val) - } -} -#[repr(u8)] -#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] -pub enum Page50lock1lockNs { - #[doc = "Page can be read by Non-secure software, and Secure software may permit Non-secure writes."] - READ_WRITE = 0, - #[doc = "Page can be read by Non-secure software"] - READ_ONLY = 0x01, - #[doc = "Do not use. Behaves the same as INACCESSIBLE."] - RESERVED = 0x02, - #[doc = "Page can not be accessed by Non-secure software."] - INACCESSIBLE = 0x03, -} -impl Page50lock1lockNs { - #[inline(always)] - pub const fn from_bits(val: u8) -> Page50lock1lockNs { - unsafe { core::mem::transmute(val & 0x03) } - } - #[inline(always)] - pub const fn to_bits(self) -> u8 { - unsafe { core::mem::transmute(self) } - } -} -impl From for Page50lock1lockNs { - #[inline(always)] - fn from(val: u8) -> Page50lock1lockNs { - Page50lock1lockNs::from_bits(val) - } -} -impl From for u8 { - #[inline(always)] - fn from(val: Page50lock1lockNs) -> u8 { - Page50lock1lockNs::to_bits(val) - } -} -#[repr(u8)] -#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] -pub enum Page50lock1lockS { - #[doc = "Page is fully accessible by Secure software."] - READ_WRITE = 0, - #[doc = "Page can be read by Secure software, but can not be written."] - READ_ONLY = 0x01, - #[doc = "Do not use. Behaves the same as INACCESSIBLE."] - RESERVED = 0x02, - #[doc = "Page can not be accessed by Secure software."] - INACCESSIBLE = 0x03, -} -impl Page50lock1lockS { - #[inline(always)] - pub const fn from_bits(val: u8) -> Page50lock1lockS { - unsafe { core::mem::transmute(val & 0x03) } - } - #[inline(always)] - pub const fn to_bits(self) -> u8 { - unsafe { core::mem::transmute(self) } - } -} -impl From for Page50lock1lockS { - #[inline(always)] - fn from(val: u8) -> Page50lock1lockS { - Page50lock1lockS::from_bits(val) - } -} -impl From for u8 { - #[inline(always)] - fn from(val: Page50lock1lockS) -> u8 { - Page50lock1lockS::to_bits(val) - } -} -#[repr(u8)] -#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] -pub enum Page51lock0noKeyState { - READ_ONLY = 0, - INACCESSIBLE = 0x01, -} -impl Page51lock0noKeyState { - #[inline(always)] - pub const fn from_bits(val: u8) -> Page51lock0noKeyState { - unsafe { core::mem::transmute(val & 0x01) } - } - #[inline(always)] - pub const fn to_bits(self) -> u8 { - unsafe { core::mem::transmute(self) } - } -} -impl From for Page51lock0noKeyState { - #[inline(always)] - fn from(val: u8) -> Page51lock0noKeyState { - Page51lock0noKeyState::from_bits(val) - } -} -impl From for u8 { - #[inline(always)] - fn from(val: Page51lock0noKeyState) -> u8 { - Page51lock0noKeyState::to_bits(val) - } -} -#[repr(u8)] -#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] -pub enum Page51lock1lockBl { - #[doc = "Bootloader permits user reads and writes to this page"] - READ_WRITE = 0, - #[doc = "Bootloader permits user reads of this page"] - READ_ONLY = 0x01, - #[doc = "Do not use. Behaves the same as INACCESSIBLE"] - RESERVED = 0x02, - #[doc = "Bootloader does not permit user access to this page"] - INACCESSIBLE = 0x03, -} -impl Page51lock1lockBl { - #[inline(always)] - pub const fn from_bits(val: u8) -> Page51lock1lockBl { - unsafe { core::mem::transmute(val & 0x03) } - } - #[inline(always)] - pub const fn to_bits(self) -> u8 { - unsafe { core::mem::transmute(self) } - } -} -impl From for Page51lock1lockBl { - #[inline(always)] - fn from(val: u8) -> Page51lock1lockBl { - Page51lock1lockBl::from_bits(val) - } -} -impl From for u8 { - #[inline(always)] - fn from(val: Page51lock1lockBl) -> u8 { - Page51lock1lockBl::to_bits(val) - } -} -#[repr(u8)] -#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] -pub enum Page51lock1lockNs { - #[doc = "Page can be read by Non-secure software, and Secure software may permit Non-secure writes."] - READ_WRITE = 0, - #[doc = "Page can be read by Non-secure software"] - READ_ONLY = 0x01, - #[doc = "Do not use. Behaves the same as INACCESSIBLE."] - RESERVED = 0x02, - #[doc = "Page can not be accessed by Non-secure software."] - INACCESSIBLE = 0x03, -} -impl Page51lock1lockNs { - #[inline(always)] - pub const fn from_bits(val: u8) -> Page51lock1lockNs { - unsafe { core::mem::transmute(val & 0x03) } - } - #[inline(always)] - pub const fn to_bits(self) -> u8 { - unsafe { core::mem::transmute(self) } - } -} -impl From for Page51lock1lockNs { - #[inline(always)] - fn from(val: u8) -> Page51lock1lockNs { - Page51lock1lockNs::from_bits(val) - } -} -impl From for u8 { - #[inline(always)] - fn from(val: Page51lock1lockNs) -> u8 { - Page51lock1lockNs::to_bits(val) - } -} -#[repr(u8)] -#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] -pub enum Page51lock1lockS { - #[doc = "Page is fully accessible by Secure software."] - READ_WRITE = 0, - #[doc = "Page can be read by Secure software, but can not be written."] - READ_ONLY = 0x01, - #[doc = "Do not use. Behaves the same as INACCESSIBLE."] - RESERVED = 0x02, - #[doc = "Page can not be accessed by Secure software."] - INACCESSIBLE = 0x03, -} -impl Page51lock1lockS { - #[inline(always)] - pub const fn from_bits(val: u8) -> Page51lock1lockS { - unsafe { core::mem::transmute(val & 0x03) } - } - #[inline(always)] - pub const fn to_bits(self) -> u8 { - unsafe { core::mem::transmute(self) } - } -} -impl From for Page51lock1lockS { - #[inline(always)] - fn from(val: u8) -> Page51lock1lockS { - Page51lock1lockS::from_bits(val) - } -} -impl From for u8 { - #[inline(always)] - fn from(val: Page51lock1lockS) -> u8 { - Page51lock1lockS::to_bits(val) - } -} -#[repr(u8)] -#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] -pub enum Page52lock0noKeyState { - READ_ONLY = 0, - INACCESSIBLE = 0x01, -} -impl Page52lock0noKeyState { - #[inline(always)] - pub const fn from_bits(val: u8) -> Page52lock0noKeyState { - unsafe { core::mem::transmute(val & 0x01) } - } - #[inline(always)] - pub const fn to_bits(self) -> u8 { - unsafe { core::mem::transmute(self) } - } -} -impl From for Page52lock0noKeyState { - #[inline(always)] - fn from(val: u8) -> Page52lock0noKeyState { - Page52lock0noKeyState::from_bits(val) - } -} -impl From for u8 { - #[inline(always)] - fn from(val: Page52lock0noKeyState) -> u8 { - Page52lock0noKeyState::to_bits(val) - } -} -#[repr(u8)] -#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] -pub enum Page52lock1lockBl { - #[doc = "Bootloader permits user reads and writes to this page"] - READ_WRITE = 0, - #[doc = "Bootloader permits user reads of this page"] - READ_ONLY = 0x01, - #[doc = "Do not use. Behaves the same as INACCESSIBLE"] - RESERVED = 0x02, - #[doc = "Bootloader does not permit user access to this page"] - INACCESSIBLE = 0x03, -} -impl Page52lock1lockBl { - #[inline(always)] - pub const fn from_bits(val: u8) -> Page52lock1lockBl { - unsafe { core::mem::transmute(val & 0x03) } - } - #[inline(always)] - pub const fn to_bits(self) -> u8 { - unsafe { core::mem::transmute(self) } - } -} -impl From for Page52lock1lockBl { - #[inline(always)] - fn from(val: u8) -> Page52lock1lockBl { - Page52lock1lockBl::from_bits(val) - } -} -impl From for u8 { - #[inline(always)] - fn from(val: Page52lock1lockBl) -> u8 { - Page52lock1lockBl::to_bits(val) - } -} -#[repr(u8)] -#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] -pub enum Page52lock1lockNs { - #[doc = "Page can be read by Non-secure software, and Secure software may permit Non-secure writes."] - READ_WRITE = 0, - #[doc = "Page can be read by Non-secure software"] - READ_ONLY = 0x01, - #[doc = "Do not use. Behaves the same as INACCESSIBLE."] - RESERVED = 0x02, - #[doc = "Page can not be accessed by Non-secure software."] - INACCESSIBLE = 0x03, -} -impl Page52lock1lockNs { - #[inline(always)] - pub const fn from_bits(val: u8) -> Page52lock1lockNs { - unsafe { core::mem::transmute(val & 0x03) } - } - #[inline(always)] - pub const fn to_bits(self) -> u8 { - unsafe { core::mem::transmute(self) } - } -} -impl From for Page52lock1lockNs { - #[inline(always)] - fn from(val: u8) -> Page52lock1lockNs { - Page52lock1lockNs::from_bits(val) - } -} -impl From for u8 { - #[inline(always)] - fn from(val: Page52lock1lockNs) -> u8 { - Page52lock1lockNs::to_bits(val) - } -} -#[repr(u8)] -#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] -pub enum Page52lock1lockS { - #[doc = "Page is fully accessible by Secure software."] - READ_WRITE = 0, - #[doc = "Page can be read by Secure software, but can not be written."] - READ_ONLY = 0x01, - #[doc = "Do not use. Behaves the same as INACCESSIBLE."] - RESERVED = 0x02, - #[doc = "Page can not be accessed by Secure software."] - INACCESSIBLE = 0x03, -} -impl Page52lock1lockS { - #[inline(always)] - pub const fn from_bits(val: u8) -> Page52lock1lockS { - unsafe { core::mem::transmute(val & 0x03) } - } - #[inline(always)] - pub const fn to_bits(self) -> u8 { - unsafe { core::mem::transmute(self) } - } -} -impl From for Page52lock1lockS { - #[inline(always)] - fn from(val: u8) -> Page52lock1lockS { - Page52lock1lockS::from_bits(val) - } -} -impl From for u8 { - #[inline(always)] - fn from(val: Page52lock1lockS) -> u8 { - Page52lock1lockS::to_bits(val) - } -} -#[repr(u8)] -#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] -pub enum Page53lock0noKeyState { - READ_ONLY = 0, - INACCESSIBLE = 0x01, -} -impl Page53lock0noKeyState { - #[inline(always)] - pub const fn from_bits(val: u8) -> Page53lock0noKeyState { - unsafe { core::mem::transmute(val & 0x01) } - } - #[inline(always)] - pub const fn to_bits(self) -> u8 { - unsafe { core::mem::transmute(self) } - } -} -impl From for Page53lock0noKeyState { - #[inline(always)] - fn from(val: u8) -> Page53lock0noKeyState { - Page53lock0noKeyState::from_bits(val) - } -} -impl From for u8 { - #[inline(always)] - fn from(val: Page53lock0noKeyState) -> u8 { - Page53lock0noKeyState::to_bits(val) - } -} -#[repr(u8)] -#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] -pub enum Page53lock1lockBl { - #[doc = "Bootloader permits user reads and writes to this page"] - READ_WRITE = 0, - #[doc = "Bootloader permits user reads of this page"] - READ_ONLY = 0x01, - #[doc = "Do not use. Behaves the same as INACCESSIBLE"] - RESERVED = 0x02, - #[doc = "Bootloader does not permit user access to this page"] - INACCESSIBLE = 0x03, -} -impl Page53lock1lockBl { - #[inline(always)] - pub const fn from_bits(val: u8) -> Page53lock1lockBl { - unsafe { core::mem::transmute(val & 0x03) } - } - #[inline(always)] - pub const fn to_bits(self) -> u8 { - unsafe { core::mem::transmute(self) } - } -} -impl From for Page53lock1lockBl { - #[inline(always)] - fn from(val: u8) -> Page53lock1lockBl { - Page53lock1lockBl::from_bits(val) - } -} -impl From for u8 { - #[inline(always)] - fn from(val: Page53lock1lockBl) -> u8 { - Page53lock1lockBl::to_bits(val) - } -} -#[repr(u8)] -#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] -pub enum Page53lock1lockNs { - #[doc = "Page can be read by Non-secure software, and Secure software may permit Non-secure writes."] - READ_WRITE = 0, - #[doc = "Page can be read by Non-secure software"] - READ_ONLY = 0x01, - #[doc = "Do not use. Behaves the same as INACCESSIBLE."] - RESERVED = 0x02, - #[doc = "Page can not be accessed by Non-secure software."] - INACCESSIBLE = 0x03, -} -impl Page53lock1lockNs { - #[inline(always)] - pub const fn from_bits(val: u8) -> Page53lock1lockNs { - unsafe { core::mem::transmute(val & 0x03) } - } - #[inline(always)] - pub const fn to_bits(self) -> u8 { - unsafe { core::mem::transmute(self) } - } -} -impl From for Page53lock1lockNs { - #[inline(always)] - fn from(val: u8) -> Page53lock1lockNs { - Page53lock1lockNs::from_bits(val) - } -} -impl From for u8 { - #[inline(always)] - fn from(val: Page53lock1lockNs) -> u8 { - Page53lock1lockNs::to_bits(val) - } -} -#[repr(u8)] -#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] -pub enum Page53lock1lockS { - #[doc = "Page is fully accessible by Secure software."] - READ_WRITE = 0, - #[doc = "Page can be read by Secure software, but can not be written."] - READ_ONLY = 0x01, - #[doc = "Do not use. Behaves the same as INACCESSIBLE."] - RESERVED = 0x02, - #[doc = "Page can not be accessed by Secure software."] - INACCESSIBLE = 0x03, -} -impl Page53lock1lockS { - #[inline(always)] - pub const fn from_bits(val: u8) -> Page53lock1lockS { - unsafe { core::mem::transmute(val & 0x03) } - } - #[inline(always)] - pub const fn to_bits(self) -> u8 { - unsafe { core::mem::transmute(self) } - } -} -impl From for Page53lock1lockS { - #[inline(always)] - fn from(val: u8) -> Page53lock1lockS { - Page53lock1lockS::from_bits(val) - } -} -impl From for u8 { - #[inline(always)] - fn from(val: Page53lock1lockS) -> u8 { - Page53lock1lockS::to_bits(val) - } -} -#[repr(u8)] -#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] -pub enum Page54lock0noKeyState { - READ_ONLY = 0, - INACCESSIBLE = 0x01, -} -impl Page54lock0noKeyState { - #[inline(always)] - pub const fn from_bits(val: u8) -> Page54lock0noKeyState { - unsafe { core::mem::transmute(val & 0x01) } - } - #[inline(always)] - pub const fn to_bits(self) -> u8 { - unsafe { core::mem::transmute(self) } - } -} -impl From for Page54lock0noKeyState { - #[inline(always)] - fn from(val: u8) -> Page54lock0noKeyState { - Page54lock0noKeyState::from_bits(val) - } -} -impl From for u8 { - #[inline(always)] - fn from(val: Page54lock0noKeyState) -> u8 { - Page54lock0noKeyState::to_bits(val) - } -} -#[repr(u8)] -#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] -pub enum Page54lock1lockBl { - #[doc = "Bootloader permits user reads and writes to this page"] - READ_WRITE = 0, - #[doc = "Bootloader permits user reads of this page"] - READ_ONLY = 0x01, - #[doc = "Do not use. Behaves the same as INACCESSIBLE"] - RESERVED = 0x02, - #[doc = "Bootloader does not permit user access to this page"] - INACCESSIBLE = 0x03, -} -impl Page54lock1lockBl { - #[inline(always)] - pub const fn from_bits(val: u8) -> Page54lock1lockBl { - unsafe { core::mem::transmute(val & 0x03) } - } - #[inline(always)] - pub const fn to_bits(self) -> u8 { - unsafe { core::mem::transmute(self) } - } -} -impl From for Page54lock1lockBl { - #[inline(always)] - fn from(val: u8) -> Page54lock1lockBl { - Page54lock1lockBl::from_bits(val) - } -} -impl From for u8 { - #[inline(always)] - fn from(val: Page54lock1lockBl) -> u8 { - Page54lock1lockBl::to_bits(val) - } -} -#[repr(u8)] -#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] -pub enum Page54lock1lockNs { - #[doc = "Page can be read by Non-secure software, and Secure software may permit Non-secure writes."] - READ_WRITE = 0, - #[doc = "Page can be read by Non-secure software"] - READ_ONLY = 0x01, - #[doc = "Do not use. Behaves the same as INACCESSIBLE."] - RESERVED = 0x02, - #[doc = "Page can not be accessed by Non-secure software."] - INACCESSIBLE = 0x03, -} -impl Page54lock1lockNs { - #[inline(always)] - pub const fn from_bits(val: u8) -> Page54lock1lockNs { - unsafe { core::mem::transmute(val & 0x03) } - } - #[inline(always)] - pub const fn to_bits(self) -> u8 { - unsafe { core::mem::transmute(self) } - } -} -impl From for Page54lock1lockNs { - #[inline(always)] - fn from(val: u8) -> Page54lock1lockNs { - Page54lock1lockNs::from_bits(val) - } -} -impl From for u8 { - #[inline(always)] - fn from(val: Page54lock1lockNs) -> u8 { - Page54lock1lockNs::to_bits(val) - } -} -#[repr(u8)] -#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] -pub enum Page54lock1lockS { - #[doc = "Page is fully accessible by Secure software."] - READ_WRITE = 0, - #[doc = "Page can be read by Secure software, but can not be written."] - READ_ONLY = 0x01, - #[doc = "Do not use. Behaves the same as INACCESSIBLE."] - RESERVED = 0x02, - #[doc = "Page can not be accessed by Secure software."] - INACCESSIBLE = 0x03, -} -impl Page54lock1lockS { - #[inline(always)] - pub const fn from_bits(val: u8) -> Page54lock1lockS { - unsafe { core::mem::transmute(val & 0x03) } - } - #[inline(always)] - pub const fn to_bits(self) -> u8 { - unsafe { core::mem::transmute(self) } - } -} -impl From for Page54lock1lockS { - #[inline(always)] - fn from(val: u8) -> Page54lock1lockS { - Page54lock1lockS::from_bits(val) - } -} -impl From for u8 { - #[inline(always)] - fn from(val: Page54lock1lockS) -> u8 { - Page54lock1lockS::to_bits(val) - } -} -#[repr(u8)] -#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] -pub enum Page55lock0noKeyState { - READ_ONLY = 0, - INACCESSIBLE = 0x01, -} -impl Page55lock0noKeyState { - #[inline(always)] - pub const fn from_bits(val: u8) -> Page55lock0noKeyState { - unsafe { core::mem::transmute(val & 0x01) } - } - #[inline(always)] - pub const fn to_bits(self) -> u8 { - unsafe { core::mem::transmute(self) } - } -} -impl From for Page55lock0noKeyState { - #[inline(always)] - fn from(val: u8) -> Page55lock0noKeyState { - Page55lock0noKeyState::from_bits(val) - } -} -impl From for u8 { - #[inline(always)] - fn from(val: Page55lock0noKeyState) -> u8 { - Page55lock0noKeyState::to_bits(val) - } -} -#[repr(u8)] -#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] -pub enum Page55lock1lockBl { - #[doc = "Bootloader permits user reads and writes to this page"] - READ_WRITE = 0, - #[doc = "Bootloader permits user reads of this page"] - READ_ONLY = 0x01, - #[doc = "Do not use. Behaves the same as INACCESSIBLE"] - RESERVED = 0x02, - #[doc = "Bootloader does not permit user access to this page"] - INACCESSIBLE = 0x03, -} -impl Page55lock1lockBl { - #[inline(always)] - pub const fn from_bits(val: u8) -> Page55lock1lockBl { - unsafe { core::mem::transmute(val & 0x03) } - } - #[inline(always)] - pub const fn to_bits(self) -> u8 { - unsafe { core::mem::transmute(self) } - } -} -impl From for Page55lock1lockBl { - #[inline(always)] - fn from(val: u8) -> Page55lock1lockBl { - Page55lock1lockBl::from_bits(val) - } -} -impl From for u8 { - #[inline(always)] - fn from(val: Page55lock1lockBl) -> u8 { - Page55lock1lockBl::to_bits(val) - } -} -#[repr(u8)] -#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] -pub enum Page55lock1lockNs { - #[doc = "Page can be read by Non-secure software, and Secure software may permit Non-secure writes."] - READ_WRITE = 0, - #[doc = "Page can be read by Non-secure software"] - READ_ONLY = 0x01, - #[doc = "Do not use. Behaves the same as INACCESSIBLE."] - RESERVED = 0x02, - #[doc = "Page can not be accessed by Non-secure software."] - INACCESSIBLE = 0x03, -} -impl Page55lock1lockNs { - #[inline(always)] - pub const fn from_bits(val: u8) -> Page55lock1lockNs { - unsafe { core::mem::transmute(val & 0x03) } - } - #[inline(always)] - pub const fn to_bits(self) -> u8 { - unsafe { core::mem::transmute(self) } - } -} -impl From for Page55lock1lockNs { - #[inline(always)] - fn from(val: u8) -> Page55lock1lockNs { - Page55lock1lockNs::from_bits(val) - } -} -impl From for u8 { - #[inline(always)] - fn from(val: Page55lock1lockNs) -> u8 { - Page55lock1lockNs::to_bits(val) - } -} -#[repr(u8)] -#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] -pub enum Page55lock1lockS { - #[doc = "Page is fully accessible by Secure software."] - READ_WRITE = 0, - #[doc = "Page can be read by Secure software, but can not be written."] - READ_ONLY = 0x01, - #[doc = "Do not use. Behaves the same as INACCESSIBLE."] - RESERVED = 0x02, - #[doc = "Page can not be accessed by Secure software."] - INACCESSIBLE = 0x03, -} -impl Page55lock1lockS { - #[inline(always)] - pub const fn from_bits(val: u8) -> Page55lock1lockS { - unsafe { core::mem::transmute(val & 0x03) } - } - #[inline(always)] - pub const fn to_bits(self) -> u8 { - unsafe { core::mem::transmute(self) } - } -} -impl From for Page55lock1lockS { - #[inline(always)] - fn from(val: u8) -> Page55lock1lockS { - Page55lock1lockS::from_bits(val) - } -} -impl From for u8 { - #[inline(always)] - fn from(val: Page55lock1lockS) -> u8 { - Page55lock1lockS::to_bits(val) - } -} -#[repr(u8)] -#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] -pub enum Page56lock0noKeyState { - READ_ONLY = 0, - INACCESSIBLE = 0x01, -} -impl Page56lock0noKeyState { - #[inline(always)] - pub const fn from_bits(val: u8) -> Page56lock0noKeyState { - unsafe { core::mem::transmute(val & 0x01) } - } - #[inline(always)] - pub const fn to_bits(self) -> u8 { - unsafe { core::mem::transmute(self) } - } -} -impl From for Page56lock0noKeyState { - #[inline(always)] - fn from(val: u8) -> Page56lock0noKeyState { - Page56lock0noKeyState::from_bits(val) - } -} -impl From for u8 { - #[inline(always)] - fn from(val: Page56lock0noKeyState) -> u8 { - Page56lock0noKeyState::to_bits(val) - } -} -#[repr(u8)] -#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] -pub enum Page56lock1lockBl { - #[doc = "Bootloader permits user reads and writes to this page"] - READ_WRITE = 0, - #[doc = "Bootloader permits user reads of this page"] - READ_ONLY = 0x01, - #[doc = "Do not use. Behaves the same as INACCESSIBLE"] - RESERVED = 0x02, - #[doc = "Bootloader does not permit user access to this page"] - INACCESSIBLE = 0x03, -} -impl Page56lock1lockBl { - #[inline(always)] - pub const fn from_bits(val: u8) -> Page56lock1lockBl { - unsafe { core::mem::transmute(val & 0x03) } - } - #[inline(always)] - pub const fn to_bits(self) -> u8 { - unsafe { core::mem::transmute(self) } - } -} -impl From for Page56lock1lockBl { - #[inline(always)] - fn from(val: u8) -> Page56lock1lockBl { - Page56lock1lockBl::from_bits(val) - } -} -impl From for u8 { - #[inline(always)] - fn from(val: Page56lock1lockBl) -> u8 { - Page56lock1lockBl::to_bits(val) - } -} -#[repr(u8)] -#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] -pub enum Page56lock1lockNs { - #[doc = "Page can be read by Non-secure software, and Secure software may permit Non-secure writes."] - READ_WRITE = 0, - #[doc = "Page can be read by Non-secure software"] - READ_ONLY = 0x01, - #[doc = "Do not use. Behaves the same as INACCESSIBLE."] - RESERVED = 0x02, - #[doc = "Page can not be accessed by Non-secure software."] - INACCESSIBLE = 0x03, -} -impl Page56lock1lockNs { - #[inline(always)] - pub const fn from_bits(val: u8) -> Page56lock1lockNs { - unsafe { core::mem::transmute(val & 0x03) } - } - #[inline(always)] - pub const fn to_bits(self) -> u8 { - unsafe { core::mem::transmute(self) } - } -} -impl From for Page56lock1lockNs { - #[inline(always)] - fn from(val: u8) -> Page56lock1lockNs { - Page56lock1lockNs::from_bits(val) - } -} -impl From for u8 { - #[inline(always)] - fn from(val: Page56lock1lockNs) -> u8 { - Page56lock1lockNs::to_bits(val) - } -} -#[repr(u8)] -#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] -pub enum Page56lock1lockS { - #[doc = "Page is fully accessible by Secure software."] - READ_WRITE = 0, - #[doc = "Page can be read by Secure software, but can not be written."] - READ_ONLY = 0x01, - #[doc = "Do not use. Behaves the same as INACCESSIBLE."] - RESERVED = 0x02, - #[doc = "Page can not be accessed by Secure software."] - INACCESSIBLE = 0x03, -} -impl Page56lock1lockS { - #[inline(always)] - pub const fn from_bits(val: u8) -> Page56lock1lockS { - unsafe { core::mem::transmute(val & 0x03) } - } - #[inline(always)] - pub const fn to_bits(self) -> u8 { - unsafe { core::mem::transmute(self) } - } -} -impl From for Page56lock1lockS { - #[inline(always)] - fn from(val: u8) -> Page56lock1lockS { - Page56lock1lockS::from_bits(val) - } -} -impl From for u8 { - #[inline(always)] - fn from(val: Page56lock1lockS) -> u8 { - Page56lock1lockS::to_bits(val) - } -} -#[repr(u8)] -#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] -pub enum Page57lock0noKeyState { - READ_ONLY = 0, - INACCESSIBLE = 0x01, -} -impl Page57lock0noKeyState { - #[inline(always)] - pub const fn from_bits(val: u8) -> Page57lock0noKeyState { - unsafe { core::mem::transmute(val & 0x01) } - } - #[inline(always)] - pub const fn to_bits(self) -> u8 { - unsafe { core::mem::transmute(self) } - } -} -impl From for Page57lock0noKeyState { - #[inline(always)] - fn from(val: u8) -> Page57lock0noKeyState { - Page57lock0noKeyState::from_bits(val) - } -} -impl From for u8 { - #[inline(always)] - fn from(val: Page57lock0noKeyState) -> u8 { - Page57lock0noKeyState::to_bits(val) - } -} -#[repr(u8)] -#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] -pub enum Page57lock1lockBl { - #[doc = "Bootloader permits user reads and writes to this page"] - READ_WRITE = 0, - #[doc = "Bootloader permits user reads of this page"] - READ_ONLY = 0x01, - #[doc = "Do not use. Behaves the same as INACCESSIBLE"] - RESERVED = 0x02, - #[doc = "Bootloader does not permit user access to this page"] - INACCESSIBLE = 0x03, -} -impl Page57lock1lockBl { - #[inline(always)] - pub const fn from_bits(val: u8) -> Page57lock1lockBl { - unsafe { core::mem::transmute(val & 0x03) } - } - #[inline(always)] - pub const fn to_bits(self) -> u8 { - unsafe { core::mem::transmute(self) } - } -} -impl From for Page57lock1lockBl { - #[inline(always)] - fn from(val: u8) -> Page57lock1lockBl { - Page57lock1lockBl::from_bits(val) - } -} -impl From for u8 { - #[inline(always)] - fn from(val: Page57lock1lockBl) -> u8 { - Page57lock1lockBl::to_bits(val) - } -} -#[repr(u8)] -#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] -pub enum Page57lock1lockNs { - #[doc = "Page can be read by Non-secure software, and Secure software may permit Non-secure writes."] - READ_WRITE = 0, - #[doc = "Page can be read by Non-secure software"] - READ_ONLY = 0x01, - #[doc = "Do not use. Behaves the same as INACCESSIBLE."] - RESERVED = 0x02, - #[doc = "Page can not be accessed by Non-secure software."] - INACCESSIBLE = 0x03, -} -impl Page57lock1lockNs { - #[inline(always)] - pub const fn from_bits(val: u8) -> Page57lock1lockNs { - unsafe { core::mem::transmute(val & 0x03) } - } - #[inline(always)] - pub const fn to_bits(self) -> u8 { - unsafe { core::mem::transmute(self) } - } -} -impl From for Page57lock1lockNs { - #[inline(always)] - fn from(val: u8) -> Page57lock1lockNs { - Page57lock1lockNs::from_bits(val) - } -} -impl From for u8 { - #[inline(always)] - fn from(val: Page57lock1lockNs) -> u8 { - Page57lock1lockNs::to_bits(val) - } -} -#[repr(u8)] -#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] -pub enum Page57lock1lockS { - #[doc = "Page is fully accessible by Secure software."] - READ_WRITE = 0, - #[doc = "Page can be read by Secure software, but can not be written."] - READ_ONLY = 0x01, - #[doc = "Do not use. Behaves the same as INACCESSIBLE."] - RESERVED = 0x02, - #[doc = "Page can not be accessed by Secure software."] - INACCESSIBLE = 0x03, -} -impl Page57lock1lockS { - #[inline(always)] - pub const fn from_bits(val: u8) -> Page57lock1lockS { - unsafe { core::mem::transmute(val & 0x03) } - } - #[inline(always)] - pub const fn to_bits(self) -> u8 { - unsafe { core::mem::transmute(self) } - } -} -impl From for Page57lock1lockS { - #[inline(always)] - fn from(val: u8) -> Page57lock1lockS { - Page57lock1lockS::from_bits(val) - } -} -impl From for u8 { - #[inline(always)] - fn from(val: Page57lock1lockS) -> u8 { - Page57lock1lockS::to_bits(val) - } -} -#[repr(u8)] -#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] -pub enum Page58lock0noKeyState { - READ_ONLY = 0, - INACCESSIBLE = 0x01, -} -impl Page58lock0noKeyState { - #[inline(always)] - pub const fn from_bits(val: u8) -> Page58lock0noKeyState { - unsafe { core::mem::transmute(val & 0x01) } - } - #[inline(always)] - pub const fn to_bits(self) -> u8 { - unsafe { core::mem::transmute(self) } - } -} -impl From for Page58lock0noKeyState { - #[inline(always)] - fn from(val: u8) -> Page58lock0noKeyState { - Page58lock0noKeyState::from_bits(val) - } -} -impl From for u8 { - #[inline(always)] - fn from(val: Page58lock0noKeyState) -> u8 { - Page58lock0noKeyState::to_bits(val) - } -} -#[repr(u8)] -#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] -pub enum Page58lock1lockBl { - #[doc = "Bootloader permits user reads and writes to this page"] - READ_WRITE = 0, - #[doc = "Bootloader permits user reads of this page"] - READ_ONLY = 0x01, - #[doc = "Do not use. Behaves the same as INACCESSIBLE"] - RESERVED = 0x02, - #[doc = "Bootloader does not permit user access to this page"] - INACCESSIBLE = 0x03, -} -impl Page58lock1lockBl { - #[inline(always)] - pub const fn from_bits(val: u8) -> Page58lock1lockBl { - unsafe { core::mem::transmute(val & 0x03) } - } - #[inline(always)] - pub const fn to_bits(self) -> u8 { - unsafe { core::mem::transmute(self) } - } -} -impl From for Page58lock1lockBl { - #[inline(always)] - fn from(val: u8) -> Page58lock1lockBl { - Page58lock1lockBl::from_bits(val) - } -} -impl From for u8 { - #[inline(always)] - fn from(val: Page58lock1lockBl) -> u8 { - Page58lock1lockBl::to_bits(val) - } -} -#[repr(u8)] -#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] -pub enum Page58lock1lockNs { - #[doc = "Page can be read by Non-secure software, and Secure software may permit Non-secure writes."] - READ_WRITE = 0, - #[doc = "Page can be read by Non-secure software"] - READ_ONLY = 0x01, - #[doc = "Do not use. Behaves the same as INACCESSIBLE."] - RESERVED = 0x02, - #[doc = "Page can not be accessed by Non-secure software."] - INACCESSIBLE = 0x03, -} -impl Page58lock1lockNs { - #[inline(always)] - pub const fn from_bits(val: u8) -> Page58lock1lockNs { - unsafe { core::mem::transmute(val & 0x03) } - } - #[inline(always)] - pub const fn to_bits(self) -> u8 { - unsafe { core::mem::transmute(self) } - } -} -impl From for Page58lock1lockNs { - #[inline(always)] - fn from(val: u8) -> Page58lock1lockNs { - Page58lock1lockNs::from_bits(val) - } -} -impl From for u8 { - #[inline(always)] - fn from(val: Page58lock1lockNs) -> u8 { - Page58lock1lockNs::to_bits(val) - } -} -#[repr(u8)] -#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] -pub enum Page58lock1lockS { - #[doc = "Page is fully accessible by Secure software."] - READ_WRITE = 0, - #[doc = "Page can be read by Secure software, but can not be written."] - READ_ONLY = 0x01, - #[doc = "Do not use. Behaves the same as INACCESSIBLE."] - RESERVED = 0x02, - #[doc = "Page can not be accessed by Secure software."] - INACCESSIBLE = 0x03, -} -impl Page58lock1lockS { - #[inline(always)] - pub const fn from_bits(val: u8) -> Page58lock1lockS { - unsafe { core::mem::transmute(val & 0x03) } - } - #[inline(always)] - pub const fn to_bits(self) -> u8 { - unsafe { core::mem::transmute(self) } - } -} -impl From for Page58lock1lockS { - #[inline(always)] - fn from(val: u8) -> Page58lock1lockS { - Page58lock1lockS::from_bits(val) - } -} -impl From for u8 { - #[inline(always)] - fn from(val: Page58lock1lockS) -> u8 { - Page58lock1lockS::to_bits(val) - } -} -#[repr(u8)] -#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] -pub enum Page59lock0noKeyState { - READ_ONLY = 0, - INACCESSIBLE = 0x01, -} -impl Page59lock0noKeyState { - #[inline(always)] - pub const fn from_bits(val: u8) -> Page59lock0noKeyState { - unsafe { core::mem::transmute(val & 0x01) } - } - #[inline(always)] - pub const fn to_bits(self) -> u8 { - unsafe { core::mem::transmute(self) } - } -} -impl From for Page59lock0noKeyState { - #[inline(always)] - fn from(val: u8) -> Page59lock0noKeyState { - Page59lock0noKeyState::from_bits(val) - } -} -impl From for u8 { - #[inline(always)] - fn from(val: Page59lock0noKeyState) -> u8 { - Page59lock0noKeyState::to_bits(val) - } -} -#[repr(u8)] -#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] -pub enum Page59lock1lockBl { - #[doc = "Bootloader permits user reads and writes to this page"] - READ_WRITE = 0, - #[doc = "Bootloader permits user reads of this page"] - READ_ONLY = 0x01, - #[doc = "Do not use. Behaves the same as INACCESSIBLE"] - RESERVED = 0x02, - #[doc = "Bootloader does not permit user access to this page"] - INACCESSIBLE = 0x03, -} -impl Page59lock1lockBl { - #[inline(always)] - pub const fn from_bits(val: u8) -> Page59lock1lockBl { - unsafe { core::mem::transmute(val & 0x03) } - } - #[inline(always)] - pub const fn to_bits(self) -> u8 { - unsafe { core::mem::transmute(self) } - } -} -impl From for Page59lock1lockBl { - #[inline(always)] - fn from(val: u8) -> Page59lock1lockBl { - Page59lock1lockBl::from_bits(val) - } -} -impl From for u8 { - #[inline(always)] - fn from(val: Page59lock1lockBl) -> u8 { - Page59lock1lockBl::to_bits(val) - } -} -#[repr(u8)] -#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] -pub enum Page59lock1lockNs { - #[doc = "Page can be read by Non-secure software, and Secure software may permit Non-secure writes."] - READ_WRITE = 0, - #[doc = "Page can be read by Non-secure software"] - READ_ONLY = 0x01, - #[doc = "Do not use. Behaves the same as INACCESSIBLE."] - RESERVED = 0x02, - #[doc = "Page can not be accessed by Non-secure software."] - INACCESSIBLE = 0x03, -} -impl Page59lock1lockNs { - #[inline(always)] - pub const fn from_bits(val: u8) -> Page59lock1lockNs { - unsafe { core::mem::transmute(val & 0x03) } - } - #[inline(always)] - pub const fn to_bits(self) -> u8 { - unsafe { core::mem::transmute(self) } - } -} -impl From for Page59lock1lockNs { - #[inline(always)] - fn from(val: u8) -> Page59lock1lockNs { - Page59lock1lockNs::from_bits(val) - } -} -impl From for u8 { - #[inline(always)] - fn from(val: Page59lock1lockNs) -> u8 { - Page59lock1lockNs::to_bits(val) - } -} -#[repr(u8)] -#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] -pub enum Page59lock1lockS { - #[doc = "Page is fully accessible by Secure software."] - READ_WRITE = 0, - #[doc = "Page can be read by Secure software, but can not be written."] - READ_ONLY = 0x01, - #[doc = "Do not use. Behaves the same as INACCESSIBLE."] - RESERVED = 0x02, - #[doc = "Page can not be accessed by Secure software."] - INACCESSIBLE = 0x03, -} -impl Page59lock1lockS { - #[inline(always)] - pub const fn from_bits(val: u8) -> Page59lock1lockS { - unsafe { core::mem::transmute(val & 0x03) } - } - #[inline(always)] - pub const fn to_bits(self) -> u8 { - unsafe { core::mem::transmute(self) } - } -} -impl From for Page59lock1lockS { - #[inline(always)] - fn from(val: u8) -> Page59lock1lockS { - Page59lock1lockS::from_bits(val) - } -} -impl From for u8 { - #[inline(always)] - fn from(val: Page59lock1lockS) -> u8 { - Page59lock1lockS::to_bits(val) - } -} -#[repr(u8)] -#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] -pub enum Page5lock0noKeyState { - READ_ONLY = 0, - INACCESSIBLE = 0x01, -} -impl Page5lock0noKeyState { - #[inline(always)] - pub const fn from_bits(val: u8) -> Page5lock0noKeyState { - unsafe { core::mem::transmute(val & 0x01) } - } - #[inline(always)] - pub const fn to_bits(self) -> u8 { - unsafe { core::mem::transmute(self) } - } -} -impl From for Page5lock0noKeyState { - #[inline(always)] - fn from(val: u8) -> Page5lock0noKeyState { - Page5lock0noKeyState::from_bits(val) - } -} -impl From for u8 { - #[inline(always)] - fn from(val: Page5lock0noKeyState) -> u8 { - Page5lock0noKeyState::to_bits(val) - } -} -#[repr(u8)] -#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] -pub enum Page5lock1lockBl { - #[doc = "Bootloader permits user reads and writes to this page"] - READ_WRITE = 0, - #[doc = "Bootloader permits user reads of this page"] - READ_ONLY = 0x01, - #[doc = "Do not use. Behaves the same as INACCESSIBLE"] - RESERVED = 0x02, - #[doc = "Bootloader does not permit user access to this page"] - INACCESSIBLE = 0x03, -} -impl Page5lock1lockBl { - #[inline(always)] - pub const fn from_bits(val: u8) -> Page5lock1lockBl { - unsafe { core::mem::transmute(val & 0x03) } - } - #[inline(always)] - pub const fn to_bits(self) -> u8 { - unsafe { core::mem::transmute(self) } - } -} -impl From for Page5lock1lockBl { - #[inline(always)] - fn from(val: u8) -> Page5lock1lockBl { - Page5lock1lockBl::from_bits(val) - } -} -impl From for u8 { - #[inline(always)] - fn from(val: Page5lock1lockBl) -> u8 { - Page5lock1lockBl::to_bits(val) - } -} -#[repr(u8)] -#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] -pub enum Page5lock1lockNs { - #[doc = "Page can be read by Non-secure software, and Secure software may permit Non-secure writes."] - READ_WRITE = 0, - #[doc = "Page can be read by Non-secure software"] - READ_ONLY = 0x01, - #[doc = "Do not use. Behaves the same as INACCESSIBLE."] - RESERVED = 0x02, - #[doc = "Page can not be accessed by Non-secure software."] - INACCESSIBLE = 0x03, -} -impl Page5lock1lockNs { - #[inline(always)] - pub const fn from_bits(val: u8) -> Page5lock1lockNs { - unsafe { core::mem::transmute(val & 0x03) } - } - #[inline(always)] - pub const fn to_bits(self) -> u8 { - unsafe { core::mem::transmute(self) } - } -} -impl From for Page5lock1lockNs { - #[inline(always)] - fn from(val: u8) -> Page5lock1lockNs { - Page5lock1lockNs::from_bits(val) - } -} -impl From for u8 { - #[inline(always)] - fn from(val: Page5lock1lockNs) -> u8 { - Page5lock1lockNs::to_bits(val) - } -} -#[repr(u8)] -#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] -pub enum Page5lock1lockS { - #[doc = "Page is fully accessible by Secure software."] - READ_WRITE = 0, - #[doc = "Page can be read by Secure software, but can not be written."] - READ_ONLY = 0x01, - #[doc = "Do not use. Behaves the same as INACCESSIBLE."] - RESERVED = 0x02, - #[doc = "Page can not be accessed by Secure software."] - INACCESSIBLE = 0x03, -} -impl Page5lock1lockS { - #[inline(always)] - pub const fn from_bits(val: u8) -> Page5lock1lockS { - unsafe { core::mem::transmute(val & 0x03) } - } - #[inline(always)] - pub const fn to_bits(self) -> u8 { - unsafe { core::mem::transmute(self) } - } -} -impl From for Page5lock1lockS { - #[inline(always)] - fn from(val: u8) -> Page5lock1lockS { - Page5lock1lockS::from_bits(val) - } -} -impl From for u8 { - #[inline(always)] - fn from(val: Page5lock1lockS) -> u8 { - Page5lock1lockS::to_bits(val) - } -} -#[repr(u8)] -#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] -pub enum Page60lock0noKeyState { - READ_ONLY = 0, - INACCESSIBLE = 0x01, -} -impl Page60lock0noKeyState { - #[inline(always)] - pub const fn from_bits(val: u8) -> Page60lock0noKeyState { - unsafe { core::mem::transmute(val & 0x01) } - } - #[inline(always)] - pub const fn to_bits(self) -> u8 { - unsafe { core::mem::transmute(self) } - } -} -impl From for Page60lock0noKeyState { - #[inline(always)] - fn from(val: u8) -> Page60lock0noKeyState { - Page60lock0noKeyState::from_bits(val) - } -} -impl From for u8 { - #[inline(always)] - fn from(val: Page60lock0noKeyState) -> u8 { - Page60lock0noKeyState::to_bits(val) - } -} -#[repr(u8)] -#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] -pub enum Page60lock1lockBl { - #[doc = "Bootloader permits user reads and writes to this page"] - READ_WRITE = 0, - #[doc = "Bootloader permits user reads of this page"] - READ_ONLY = 0x01, - #[doc = "Do not use. Behaves the same as INACCESSIBLE"] - RESERVED = 0x02, - #[doc = "Bootloader does not permit user access to this page"] - INACCESSIBLE = 0x03, -} -impl Page60lock1lockBl { - #[inline(always)] - pub const fn from_bits(val: u8) -> Page60lock1lockBl { - unsafe { core::mem::transmute(val & 0x03) } - } - #[inline(always)] - pub const fn to_bits(self) -> u8 { - unsafe { core::mem::transmute(self) } - } -} -impl From for Page60lock1lockBl { - #[inline(always)] - fn from(val: u8) -> Page60lock1lockBl { - Page60lock1lockBl::from_bits(val) - } -} -impl From for u8 { - #[inline(always)] - fn from(val: Page60lock1lockBl) -> u8 { - Page60lock1lockBl::to_bits(val) - } -} -#[repr(u8)] -#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] -pub enum Page60lock1lockNs { - #[doc = "Page can be read by Non-secure software, and Secure software may permit Non-secure writes."] - READ_WRITE = 0, - #[doc = "Page can be read by Non-secure software"] - READ_ONLY = 0x01, - #[doc = "Do not use. Behaves the same as INACCESSIBLE."] - RESERVED = 0x02, - #[doc = "Page can not be accessed by Non-secure software."] - INACCESSIBLE = 0x03, -} -impl Page60lock1lockNs { - #[inline(always)] - pub const fn from_bits(val: u8) -> Page60lock1lockNs { - unsafe { core::mem::transmute(val & 0x03) } - } - #[inline(always)] - pub const fn to_bits(self) -> u8 { - unsafe { core::mem::transmute(self) } - } -} -impl From for Page60lock1lockNs { - #[inline(always)] - fn from(val: u8) -> Page60lock1lockNs { - Page60lock1lockNs::from_bits(val) - } -} -impl From for u8 { - #[inline(always)] - fn from(val: Page60lock1lockNs) -> u8 { - Page60lock1lockNs::to_bits(val) - } -} -#[repr(u8)] -#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] -pub enum Page60lock1lockS { - #[doc = "Page is fully accessible by Secure software."] - READ_WRITE = 0, - #[doc = "Page can be read by Secure software, but can not be written."] - READ_ONLY = 0x01, - #[doc = "Do not use. Behaves the same as INACCESSIBLE."] - RESERVED = 0x02, - #[doc = "Page can not be accessed by Secure software."] - INACCESSIBLE = 0x03, -} -impl Page60lock1lockS { - #[inline(always)] - pub const fn from_bits(val: u8) -> Page60lock1lockS { - unsafe { core::mem::transmute(val & 0x03) } - } - #[inline(always)] - pub const fn to_bits(self) -> u8 { - unsafe { core::mem::transmute(self) } - } -} -impl From for Page60lock1lockS { - #[inline(always)] - fn from(val: u8) -> Page60lock1lockS { - Page60lock1lockS::from_bits(val) - } -} -impl From for u8 { - #[inline(always)] - fn from(val: Page60lock1lockS) -> u8 { - Page60lock1lockS::to_bits(val) - } -} -#[repr(u8)] -#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] -pub enum Page61lock0noKeyState { - READ_ONLY = 0, - INACCESSIBLE = 0x01, -} -impl Page61lock0noKeyState { - #[inline(always)] - pub const fn from_bits(val: u8) -> Page61lock0noKeyState { - unsafe { core::mem::transmute(val & 0x01) } - } - #[inline(always)] - pub const fn to_bits(self) -> u8 { - unsafe { core::mem::transmute(self) } - } -} -impl From for Page61lock0noKeyState { - #[inline(always)] - fn from(val: u8) -> Page61lock0noKeyState { - Page61lock0noKeyState::from_bits(val) - } -} -impl From for u8 { - #[inline(always)] - fn from(val: Page61lock0noKeyState) -> u8 { - Page61lock0noKeyState::to_bits(val) - } -} -#[repr(u8)] -#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] -pub enum Page61lock1lockBl { - #[doc = "Bootloader permits user reads and writes to this page"] - READ_WRITE = 0, - #[doc = "Bootloader permits user reads of this page"] - READ_ONLY = 0x01, - #[doc = "Do not use. Behaves the same as INACCESSIBLE"] - RESERVED = 0x02, - #[doc = "Bootloader does not permit user access to this page"] - INACCESSIBLE = 0x03, -} -impl Page61lock1lockBl { - #[inline(always)] - pub const fn from_bits(val: u8) -> Page61lock1lockBl { - unsafe { core::mem::transmute(val & 0x03) } - } - #[inline(always)] - pub const fn to_bits(self) -> u8 { - unsafe { core::mem::transmute(self) } - } -} -impl From for Page61lock1lockBl { - #[inline(always)] - fn from(val: u8) -> Page61lock1lockBl { - Page61lock1lockBl::from_bits(val) - } -} -impl From for u8 { - #[inline(always)] - fn from(val: Page61lock1lockBl) -> u8 { - Page61lock1lockBl::to_bits(val) - } -} -#[repr(u8)] -#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] -pub enum Page61lock1lockNs { - #[doc = "Page can be read by Non-secure software, and Secure software may permit Non-secure writes."] - READ_WRITE = 0, - #[doc = "Page can be read by Non-secure software"] - READ_ONLY = 0x01, - #[doc = "Do not use. Behaves the same as INACCESSIBLE."] - RESERVED = 0x02, - #[doc = "Page can not be accessed by Non-secure software."] - INACCESSIBLE = 0x03, -} -impl Page61lock1lockNs { - #[inline(always)] - pub const fn from_bits(val: u8) -> Page61lock1lockNs { - unsafe { core::mem::transmute(val & 0x03) } - } - #[inline(always)] - pub const fn to_bits(self) -> u8 { - unsafe { core::mem::transmute(self) } - } -} -impl From for Page61lock1lockNs { - #[inline(always)] - fn from(val: u8) -> Page61lock1lockNs { - Page61lock1lockNs::from_bits(val) - } -} -impl From for u8 { - #[inline(always)] - fn from(val: Page61lock1lockNs) -> u8 { - Page61lock1lockNs::to_bits(val) - } -} -#[repr(u8)] -#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] -pub enum Page61lock1lockS { - #[doc = "Page is fully accessible by Secure software."] - READ_WRITE = 0, - #[doc = "Page can be read by Secure software, but can not be written."] - READ_ONLY = 0x01, - #[doc = "Do not use. Behaves the same as INACCESSIBLE."] - RESERVED = 0x02, - #[doc = "Page can not be accessed by Secure software."] - INACCESSIBLE = 0x03, -} -impl Page61lock1lockS { - #[inline(always)] - pub const fn from_bits(val: u8) -> Page61lock1lockS { - unsafe { core::mem::transmute(val & 0x03) } - } - #[inline(always)] - pub const fn to_bits(self) -> u8 { - unsafe { core::mem::transmute(self) } - } -} -impl From for Page61lock1lockS { - #[inline(always)] - fn from(val: u8) -> Page61lock1lockS { - Page61lock1lockS::from_bits(val) - } -} -impl From for u8 { - #[inline(always)] - fn from(val: Page61lock1lockS) -> u8 { - Page61lock1lockS::to_bits(val) - } -} -#[repr(u8)] -#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] -pub enum Page62lock0noKeyState { - READ_ONLY = 0, - INACCESSIBLE = 0x01, -} -impl Page62lock0noKeyState { - #[inline(always)] - pub const fn from_bits(val: u8) -> Page62lock0noKeyState { - unsafe { core::mem::transmute(val & 0x01) } - } - #[inline(always)] - pub const fn to_bits(self) -> u8 { - unsafe { core::mem::transmute(self) } - } -} -impl From for Page62lock0noKeyState { - #[inline(always)] - fn from(val: u8) -> Page62lock0noKeyState { - Page62lock0noKeyState::from_bits(val) - } -} -impl From for u8 { - #[inline(always)] - fn from(val: Page62lock0noKeyState) -> u8 { - Page62lock0noKeyState::to_bits(val) - } -} -#[repr(u8)] -#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] -pub enum Page62lock1lockBl { - #[doc = "Bootloader permits user reads and writes to this page"] - READ_WRITE = 0, - #[doc = "Bootloader permits user reads of this page"] - READ_ONLY = 0x01, - #[doc = "Do not use. Behaves the same as INACCESSIBLE"] - RESERVED = 0x02, - #[doc = "Bootloader does not permit user access to this page"] - INACCESSIBLE = 0x03, -} -impl Page62lock1lockBl { - #[inline(always)] - pub const fn from_bits(val: u8) -> Page62lock1lockBl { - unsafe { core::mem::transmute(val & 0x03) } - } - #[inline(always)] - pub const fn to_bits(self) -> u8 { - unsafe { core::mem::transmute(self) } - } -} -impl From for Page62lock1lockBl { - #[inline(always)] - fn from(val: u8) -> Page62lock1lockBl { - Page62lock1lockBl::from_bits(val) - } -} -impl From for u8 { - #[inline(always)] - fn from(val: Page62lock1lockBl) -> u8 { - Page62lock1lockBl::to_bits(val) - } -} -#[repr(u8)] -#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] -pub enum Page62lock1lockNs { - #[doc = "Page can be read by Non-secure software, and Secure software may permit Non-secure writes."] - READ_WRITE = 0, - #[doc = "Page can be read by Non-secure software"] - READ_ONLY = 0x01, - #[doc = "Do not use. Behaves the same as INACCESSIBLE."] - RESERVED = 0x02, - #[doc = "Page can not be accessed by Non-secure software."] - INACCESSIBLE = 0x03, -} -impl Page62lock1lockNs { - #[inline(always)] - pub const fn from_bits(val: u8) -> Page62lock1lockNs { - unsafe { core::mem::transmute(val & 0x03) } - } - #[inline(always)] - pub const fn to_bits(self) -> u8 { - unsafe { core::mem::transmute(self) } - } -} -impl From for Page62lock1lockNs { - #[inline(always)] - fn from(val: u8) -> Page62lock1lockNs { - Page62lock1lockNs::from_bits(val) - } -} -impl From for u8 { - #[inline(always)] - fn from(val: Page62lock1lockNs) -> u8 { - Page62lock1lockNs::to_bits(val) - } -} -#[repr(u8)] -#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] -pub enum Page62lock1lockS { - #[doc = "Page is fully accessible by Secure software."] - READ_WRITE = 0, - #[doc = "Page can be read by Secure software, but can not be written."] - READ_ONLY = 0x01, - #[doc = "Do not use. Behaves the same as INACCESSIBLE."] - RESERVED = 0x02, - #[doc = "Page can not be accessed by Secure software."] - INACCESSIBLE = 0x03, -} -impl Page62lock1lockS { - #[inline(always)] - pub const fn from_bits(val: u8) -> Page62lock1lockS { - unsafe { core::mem::transmute(val & 0x03) } - } - #[inline(always)] - pub const fn to_bits(self) -> u8 { - unsafe { core::mem::transmute(self) } - } -} -impl From for Page62lock1lockS { - #[inline(always)] - fn from(val: u8) -> Page62lock1lockS { - Page62lock1lockS::from_bits(val) - } -} -impl From for u8 { - #[inline(always)] - fn from(val: Page62lock1lockS) -> u8 { - Page62lock1lockS::to_bits(val) - } -} -#[repr(u8)] -#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] -pub enum Page63lock0noKeyState { - READ_ONLY = 0, - INACCESSIBLE = 0x01, -} -impl Page63lock0noKeyState { - #[inline(always)] - pub const fn from_bits(val: u8) -> Page63lock0noKeyState { - unsafe { core::mem::transmute(val & 0x01) } - } - #[inline(always)] - pub const fn to_bits(self) -> u8 { - unsafe { core::mem::transmute(self) } - } -} -impl From for Page63lock0noKeyState { - #[inline(always)] - fn from(val: u8) -> Page63lock0noKeyState { - Page63lock0noKeyState::from_bits(val) - } -} -impl From for u8 { - #[inline(always)] - fn from(val: Page63lock0noKeyState) -> u8 { - Page63lock0noKeyState::to_bits(val) - } -} -#[repr(u8)] -#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] -pub enum Page63lock1lockBl { - #[doc = "Bootloader permits user reads and writes to this page"] - READ_WRITE = 0, - #[doc = "Bootloader permits user reads of this page"] - READ_ONLY = 0x01, - #[doc = "Do not use. Behaves the same as INACCESSIBLE"] - RESERVED = 0x02, - #[doc = "Bootloader does not permit user access to this page"] - INACCESSIBLE = 0x03, -} -impl Page63lock1lockBl { - #[inline(always)] - pub const fn from_bits(val: u8) -> Page63lock1lockBl { - unsafe { core::mem::transmute(val & 0x03) } - } - #[inline(always)] - pub const fn to_bits(self) -> u8 { - unsafe { core::mem::transmute(self) } - } -} -impl From for Page63lock1lockBl { - #[inline(always)] - fn from(val: u8) -> Page63lock1lockBl { - Page63lock1lockBl::from_bits(val) - } -} -impl From for u8 { - #[inline(always)] - fn from(val: Page63lock1lockBl) -> u8 { - Page63lock1lockBl::to_bits(val) - } -} -#[repr(u8)] -#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] -pub enum Page63lock1lockNs { - #[doc = "Page can be read by Non-secure software, and Secure software may permit Non-secure writes."] - READ_WRITE = 0, - #[doc = "Page can be read by Non-secure software"] - READ_ONLY = 0x01, - #[doc = "Do not use. Behaves the same as INACCESSIBLE."] - RESERVED = 0x02, - #[doc = "Page can not be accessed by Non-secure software."] - INACCESSIBLE = 0x03, -} -impl Page63lock1lockNs { - #[inline(always)] - pub const fn from_bits(val: u8) -> Page63lock1lockNs { - unsafe { core::mem::transmute(val & 0x03) } - } - #[inline(always)] - pub const fn to_bits(self) -> u8 { - unsafe { core::mem::transmute(self) } - } -} -impl From for Page63lock1lockNs { - #[inline(always)] - fn from(val: u8) -> Page63lock1lockNs { - Page63lock1lockNs::from_bits(val) - } -} -impl From for u8 { - #[inline(always)] - fn from(val: Page63lock1lockNs) -> u8 { - Page63lock1lockNs::to_bits(val) - } -} -#[repr(u8)] -#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] -pub enum Page63lock1lockS { - #[doc = "Page is fully accessible by Secure software."] - READ_WRITE = 0, - #[doc = "Page can be read by Secure software, but can not be written."] - READ_ONLY = 0x01, - #[doc = "Do not use. Behaves the same as INACCESSIBLE."] - RESERVED = 0x02, - #[doc = "Page can not be accessed by Secure software."] - INACCESSIBLE = 0x03, -} -impl Page63lock1lockS { - #[inline(always)] - pub const fn from_bits(val: u8) -> Page63lock1lockS { - unsafe { core::mem::transmute(val & 0x03) } - } - #[inline(always)] - pub const fn to_bits(self) -> u8 { - unsafe { core::mem::transmute(self) } - } -} -impl From for Page63lock1lockS { - #[inline(always)] - fn from(val: u8) -> Page63lock1lockS { - Page63lock1lockS::from_bits(val) - } -} -impl From for u8 { - #[inline(always)] - fn from(val: Page63lock1lockS) -> u8 { - Page63lock1lockS::to_bits(val) - } -} -#[repr(u8)] -#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] -pub enum Page6lock0noKeyState { - READ_ONLY = 0, - INACCESSIBLE = 0x01, -} -impl Page6lock0noKeyState { - #[inline(always)] - pub const fn from_bits(val: u8) -> Page6lock0noKeyState { - unsafe { core::mem::transmute(val & 0x01) } - } - #[inline(always)] - pub const fn to_bits(self) -> u8 { - unsafe { core::mem::transmute(self) } - } -} -impl From for Page6lock0noKeyState { - #[inline(always)] - fn from(val: u8) -> Page6lock0noKeyState { - Page6lock0noKeyState::from_bits(val) - } -} -impl From for u8 { - #[inline(always)] - fn from(val: Page6lock0noKeyState) -> u8 { - Page6lock0noKeyState::to_bits(val) - } -} -#[repr(u8)] -#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] -pub enum Page6lock1lockBl { - #[doc = "Bootloader permits user reads and writes to this page"] - READ_WRITE = 0, - #[doc = "Bootloader permits user reads of this page"] - READ_ONLY = 0x01, - #[doc = "Do not use. Behaves the same as INACCESSIBLE"] - RESERVED = 0x02, - #[doc = "Bootloader does not permit user access to this page"] - INACCESSIBLE = 0x03, -} -impl Page6lock1lockBl { - #[inline(always)] - pub const fn from_bits(val: u8) -> Page6lock1lockBl { - unsafe { core::mem::transmute(val & 0x03) } - } - #[inline(always)] - pub const fn to_bits(self) -> u8 { - unsafe { core::mem::transmute(self) } - } -} -impl From for Page6lock1lockBl { - #[inline(always)] - fn from(val: u8) -> Page6lock1lockBl { - Page6lock1lockBl::from_bits(val) - } -} -impl From for u8 { - #[inline(always)] - fn from(val: Page6lock1lockBl) -> u8 { - Page6lock1lockBl::to_bits(val) - } -} -#[repr(u8)] -#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] -pub enum Page6lock1lockNs { - #[doc = "Page can be read by Non-secure software, and Secure software may permit Non-secure writes."] - READ_WRITE = 0, - #[doc = "Page can be read by Non-secure software"] - READ_ONLY = 0x01, - #[doc = "Do not use. Behaves the same as INACCESSIBLE."] - RESERVED = 0x02, - #[doc = "Page can not be accessed by Non-secure software."] - INACCESSIBLE = 0x03, -} -impl Page6lock1lockNs { - #[inline(always)] - pub const fn from_bits(val: u8) -> Page6lock1lockNs { - unsafe { core::mem::transmute(val & 0x03) } - } - #[inline(always)] - pub const fn to_bits(self) -> u8 { - unsafe { core::mem::transmute(self) } - } -} -impl From for Page6lock1lockNs { - #[inline(always)] - fn from(val: u8) -> Page6lock1lockNs { - Page6lock1lockNs::from_bits(val) - } -} -impl From for u8 { - #[inline(always)] - fn from(val: Page6lock1lockNs) -> u8 { - Page6lock1lockNs::to_bits(val) - } -} -#[repr(u8)] -#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] -pub enum Page6lock1lockS { - #[doc = "Page is fully accessible by Secure software."] - READ_WRITE = 0, - #[doc = "Page can be read by Secure software, but can not be written."] - READ_ONLY = 0x01, - #[doc = "Do not use. Behaves the same as INACCESSIBLE."] - RESERVED = 0x02, - #[doc = "Page can not be accessed by Secure software."] - INACCESSIBLE = 0x03, -} -impl Page6lock1lockS { - #[inline(always)] - pub const fn from_bits(val: u8) -> Page6lock1lockS { - unsafe { core::mem::transmute(val & 0x03) } - } - #[inline(always)] - pub const fn to_bits(self) -> u8 { - unsafe { core::mem::transmute(self) } - } -} -impl From for Page6lock1lockS { - #[inline(always)] - fn from(val: u8) -> Page6lock1lockS { - Page6lock1lockS::from_bits(val) - } -} -impl From for u8 { - #[inline(always)] - fn from(val: Page6lock1lockS) -> u8 { - Page6lock1lockS::to_bits(val) - } -} -#[repr(u8)] -#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] -pub enum Page7lock0noKeyState { - READ_ONLY = 0, - INACCESSIBLE = 0x01, -} -impl Page7lock0noKeyState { - #[inline(always)] - pub const fn from_bits(val: u8) -> Page7lock0noKeyState { - unsafe { core::mem::transmute(val & 0x01) } - } - #[inline(always)] - pub const fn to_bits(self) -> u8 { - unsafe { core::mem::transmute(self) } - } -} -impl From for Page7lock0noKeyState { - #[inline(always)] - fn from(val: u8) -> Page7lock0noKeyState { - Page7lock0noKeyState::from_bits(val) - } -} -impl From for u8 { - #[inline(always)] - fn from(val: Page7lock0noKeyState) -> u8 { - Page7lock0noKeyState::to_bits(val) - } -} -#[repr(u8)] -#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] -pub enum Page7lock1lockBl { - #[doc = "Bootloader permits user reads and writes to this page"] - READ_WRITE = 0, - #[doc = "Bootloader permits user reads of this page"] - READ_ONLY = 0x01, - #[doc = "Do not use. Behaves the same as INACCESSIBLE"] - RESERVED = 0x02, - #[doc = "Bootloader does not permit user access to this page"] - INACCESSIBLE = 0x03, -} -impl Page7lock1lockBl { - #[inline(always)] - pub const fn from_bits(val: u8) -> Page7lock1lockBl { - unsafe { core::mem::transmute(val & 0x03) } - } - #[inline(always)] - pub const fn to_bits(self) -> u8 { - unsafe { core::mem::transmute(self) } - } -} -impl From for Page7lock1lockBl { - #[inline(always)] - fn from(val: u8) -> Page7lock1lockBl { - Page7lock1lockBl::from_bits(val) - } -} -impl From for u8 { - #[inline(always)] - fn from(val: Page7lock1lockBl) -> u8 { - Page7lock1lockBl::to_bits(val) - } -} -#[repr(u8)] -#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] -pub enum Page7lock1lockNs { - #[doc = "Page can be read by Non-secure software, and Secure software may permit Non-secure writes."] - READ_WRITE = 0, - #[doc = "Page can be read by Non-secure software"] - READ_ONLY = 0x01, - #[doc = "Do not use. Behaves the same as INACCESSIBLE."] - RESERVED = 0x02, - #[doc = "Page can not be accessed by Non-secure software."] - INACCESSIBLE = 0x03, -} -impl Page7lock1lockNs { - #[inline(always)] - pub const fn from_bits(val: u8) -> Page7lock1lockNs { - unsafe { core::mem::transmute(val & 0x03) } - } - #[inline(always)] - pub const fn to_bits(self) -> u8 { - unsafe { core::mem::transmute(self) } - } -} -impl From for Page7lock1lockNs { - #[inline(always)] - fn from(val: u8) -> Page7lock1lockNs { - Page7lock1lockNs::from_bits(val) - } -} -impl From for u8 { - #[inline(always)] - fn from(val: Page7lock1lockNs) -> u8 { - Page7lock1lockNs::to_bits(val) - } -} -#[repr(u8)] -#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] -pub enum Page7lock1lockS { - #[doc = "Page is fully accessible by Secure software."] - READ_WRITE = 0, - #[doc = "Page can be read by Secure software, but can not be written."] - READ_ONLY = 0x01, - #[doc = "Do not use. Behaves the same as INACCESSIBLE."] - RESERVED = 0x02, - #[doc = "Page can not be accessed by Secure software."] - INACCESSIBLE = 0x03, -} -impl Page7lock1lockS { - #[inline(always)] - pub const fn from_bits(val: u8) -> Page7lock1lockS { - unsafe { core::mem::transmute(val & 0x03) } - } - #[inline(always)] - pub const fn to_bits(self) -> u8 { - unsafe { core::mem::transmute(self) } - } -} -impl From for Page7lock1lockS { - #[inline(always)] - fn from(val: u8) -> Page7lock1lockS { - Page7lock1lockS::from_bits(val) - } -} -impl From for u8 { - #[inline(always)] - fn from(val: Page7lock1lockS) -> u8 { - Page7lock1lockS::to_bits(val) - } -} -#[repr(u8)] -#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] -pub enum Page8lock0noKeyState { - READ_ONLY = 0, - INACCESSIBLE = 0x01, -} -impl Page8lock0noKeyState { - #[inline(always)] - pub const fn from_bits(val: u8) -> Page8lock0noKeyState { - unsafe { core::mem::transmute(val & 0x01) } - } - #[inline(always)] - pub const fn to_bits(self) -> u8 { - unsafe { core::mem::transmute(self) } - } -} -impl From for Page8lock0noKeyState { - #[inline(always)] - fn from(val: u8) -> Page8lock0noKeyState { - Page8lock0noKeyState::from_bits(val) - } -} -impl From for u8 { - #[inline(always)] - fn from(val: Page8lock0noKeyState) -> u8 { - Page8lock0noKeyState::to_bits(val) - } -} -#[repr(u8)] -#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] -pub enum Page8lock1lockBl { +pub enum PageLock { #[doc = "Bootloader permits user reads and writes to this page"] - READ_WRITE = 0, + READ_WRITE = 0x0, #[doc = "Bootloader permits user reads of this page"] READ_ONLY = 0x01, #[doc = "Do not use. Behaves the same as INACCESSIBLE"] @@ -8178,77 +90,9 @@ pub enum Page8lock1lockBl { #[doc = "Bootloader does not permit user access to this page"] INACCESSIBLE = 0x03, } -impl Page8lock1lockBl { - #[inline(always)] - pub const fn from_bits(val: u8) -> Page8lock1lockBl { - unsafe { core::mem::transmute(val & 0x03) } - } - #[inline(always)] - pub const fn to_bits(self) -> u8 { - unsafe { core::mem::transmute(self) } - } -} -impl From for Page8lock1lockBl { - #[inline(always)] - fn from(val: u8) -> Page8lock1lockBl { - Page8lock1lockBl::from_bits(val) - } -} -impl From for u8 { - #[inline(always)] - fn from(val: Page8lock1lockBl) -> u8 { - Page8lock1lockBl::to_bits(val) - } -} -#[repr(u8)] -#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] -pub enum Page8lock1lockNs { - #[doc = "Page can be read by Non-secure software, and Secure software may permit Non-secure writes."] - READ_WRITE = 0, - #[doc = "Page can be read by Non-secure software"] - READ_ONLY = 0x01, - #[doc = "Do not use. Behaves the same as INACCESSIBLE."] - RESERVED = 0x02, - #[doc = "Page can not be accessed by Non-secure software."] - INACCESSIBLE = 0x03, -} -impl Page8lock1lockNs { - #[inline(always)] - pub const fn from_bits(val: u8) -> Page8lock1lockNs { - unsafe { core::mem::transmute(val & 0x03) } - } - #[inline(always)] - pub const fn to_bits(self) -> u8 { - unsafe { core::mem::transmute(self) } - } -} -impl From for Page8lock1lockNs { - #[inline(always)] - fn from(val: u8) -> Page8lock1lockNs { - Page8lock1lockNs::from_bits(val) - } -} -impl From for u8 { - #[inline(always)] - fn from(val: Page8lock1lockNs) -> u8 { - Page8lock1lockNs::to_bits(val) - } -} -#[repr(u8)] -#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] -pub enum Page8lock1lockS { - #[doc = "Page is fully accessible by Secure software."] - READ_WRITE = 0, - #[doc = "Page can be read by Secure software, but can not be written."] - READ_ONLY = 0x01, - #[doc = "Do not use. Behaves the same as INACCESSIBLE."] - RESERVED = 0x02, - #[doc = "Page can not be accessed by Secure software."] - INACCESSIBLE = 0x03, -} -impl Page8lock1lockS { +impl PageLock { #[inline(always)] - pub const fn from_bits(val: u8) -> Page8lock1lockS { + pub const fn from_bits(val: u8) -> PageLock { unsafe { core::mem::transmute(val & 0x03) } } #[inline(always)] @@ -8256,27 +100,27 @@ impl Page8lock1lockS { unsafe { core::mem::transmute(self) } } } -impl From for Page8lock1lockS { +impl From for PageLock { #[inline(always)] - fn from(val: u8) -> Page8lock1lockS { - Page8lock1lockS::from_bits(val) + fn from(val: u8) -> PageLock { + PageLock::from_bits(val) } } -impl From for u8 { +impl From for u8 { #[inline(always)] - fn from(val: Page8lock1lockS) -> u8 { - Page8lock1lockS::to_bits(val) + fn from(val: PageLock) -> u8 { + PageLock::to_bits(val) } } #[repr(u8)] #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] -pub enum Page9lock0noKeyState { - READ_ONLY = 0, +pub enum PageLockNoKeyState { + READ_ONLY = 0x0, INACCESSIBLE = 0x01, } -impl Page9lock0noKeyState { +impl PageLockNoKeyState { #[inline(always)] - pub const fn from_bits(val: u8) -> Page9lock0noKeyState { + pub const fn from_bits(val: u8) -> PageLockNoKeyState { unsafe { core::mem::transmute(val & 0x01) } } #[inline(always)] @@ -8284,125 +128,23 @@ impl Page9lock0noKeyState { unsafe { core::mem::transmute(self) } } } -impl From for Page9lock0noKeyState { - #[inline(always)] - fn from(val: u8) -> Page9lock0noKeyState { - Page9lock0noKeyState::from_bits(val) - } -} -impl From for u8 { - #[inline(always)] - fn from(val: Page9lock0noKeyState) -> u8 { - Page9lock0noKeyState::to_bits(val) - } -} -#[repr(u8)] -#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] -pub enum Page9lock1lockBl { - #[doc = "Bootloader permits user reads and writes to this page"] - READ_WRITE = 0, - #[doc = "Bootloader permits user reads of this page"] - READ_ONLY = 0x01, - #[doc = "Do not use. Behaves the same as INACCESSIBLE"] - RESERVED = 0x02, - #[doc = "Bootloader does not permit user access to this page"] - INACCESSIBLE = 0x03, -} -impl Page9lock1lockBl { - #[inline(always)] - pub const fn from_bits(val: u8) -> Page9lock1lockBl { - unsafe { core::mem::transmute(val & 0x03) } - } - #[inline(always)] - pub const fn to_bits(self) -> u8 { - unsafe { core::mem::transmute(self) } - } -} -impl From for Page9lock1lockBl { - #[inline(always)] - fn from(val: u8) -> Page9lock1lockBl { - Page9lock1lockBl::from_bits(val) - } -} -impl From for u8 { - #[inline(always)] - fn from(val: Page9lock1lockBl) -> u8 { - Page9lock1lockBl::to_bits(val) - } -} -#[repr(u8)] -#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] -pub enum Page9lock1lockNs { - #[doc = "Page can be read by Non-secure software, and Secure software may permit Non-secure writes."] - READ_WRITE = 0, - #[doc = "Page can be read by Non-secure software"] - READ_ONLY = 0x01, - #[doc = "Do not use. Behaves the same as INACCESSIBLE."] - RESERVED = 0x02, - #[doc = "Page can not be accessed by Non-secure software."] - INACCESSIBLE = 0x03, -} -impl Page9lock1lockNs { - #[inline(always)] - pub const fn from_bits(val: u8) -> Page9lock1lockNs { - unsafe { core::mem::transmute(val & 0x03) } - } - #[inline(always)] - pub const fn to_bits(self) -> u8 { - unsafe { core::mem::transmute(self) } - } -} -impl From for Page9lock1lockNs { - #[inline(always)] - fn from(val: u8) -> Page9lock1lockNs { - Page9lock1lockNs::from_bits(val) - } -} -impl From for u8 { - #[inline(always)] - fn from(val: Page9lock1lockNs) -> u8 { - Page9lock1lockNs::to_bits(val) - } -} -#[repr(u8)] -#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] -pub enum Page9lock1lockS { - #[doc = "Page is fully accessible by Secure software."] - READ_WRITE = 0, - #[doc = "Page can be read by Secure software, but can not be written."] - READ_ONLY = 0x01, - #[doc = "Do not use. Behaves the same as INACCESSIBLE."] - RESERVED = 0x02, - #[doc = "Page can not be accessed by Secure software."] - INACCESSIBLE = 0x03, -} -impl Page9lock1lockS { - #[inline(always)] - pub const fn from_bits(val: u8) -> Page9lock1lockS { - unsafe { core::mem::transmute(val & 0x03) } - } - #[inline(always)] - pub const fn to_bits(self) -> u8 { - unsafe { core::mem::transmute(self) } - } -} -impl From for Page9lock1lockS { +impl From for PageLockNoKeyState { #[inline(always)] - fn from(val: u8) -> Page9lock1lockS { - Page9lock1lockS::from_bits(val) + fn from(val: u8) -> PageLockNoKeyState { + PageLockNoKeyState::from_bits(val) } } -impl From for u8 { +impl From for u8 { #[inline(always)] - fn from(val: Page9lock1lockS) -> u8 { - Page9lock1lockS::to_bits(val) + fn from(val: PageLockNoKeyState) -> u8 { + PageLockNoKeyState::to_bits(val) } } #[repr(transparent)] #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] pub struct Range(pub u16); impl Range { - pub const _1_15MHZ: Self = Self(0); + pub const _1_15MHZ: Self = Self(0x0); pub const _10_30MHZ: Self = Self(0x01); pub const _25_60MHZ: Self = Self(0x02); pub const _40_100MHZ: Self = Self(0x03); @@ -8431,7 +173,7 @@ impl From for u16 { #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] pub struct UsbWhiteLabelAddr(pub u32); impl UsbWhiteLabelAddr { - pub const INDEX_USB_DEVICE_VID_VALUE: Self = Self(0); + pub const INDEX_USB_DEVICE_VID_VALUE: Self = Self(0x0); pub const INDEX_USB_DEVICE_PID_VALUE: Self = Self(0x01); pub const INDEX_USB_DEVICE_BCD_DEVICE_VALUE: Self = Self(0x02); pub const INDEX_USB_DEVICE_LANG_ID_VALUE: Self = Self(0x03); diff --git a/src/rp235x/pads.rs b/src/rp235x/pads.rs index 27767a6f..4156ca18 100644 --- a/src/rp235x/pads.rs +++ b/src/rp235x/pads.rs @@ -18,12 +18,12 @@ impl Pads { pub const fn voltage_select( self, ) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(0usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x0usize) as _) } } #[inline(always)] pub const fn gpio(self, n: usize) -> crate::common::Reg { assert!(n < 50usize); - unsafe { crate::common::Reg::from_ptr(self.ptr.add(4usize + n * 4usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x04usize + n * 4usize) as _) } } } pub mod regs; diff --git a/src/rp235x/pads/vals.rs b/src/rp235x/pads/vals.rs index f9e7d6c3..110c4b00 100644 --- a/src/rp235x/pads/vals.rs +++ b/src/rp235x/pads/vals.rs @@ -1,7 +1,7 @@ #[repr(u8)] #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] pub enum Drive { - _2MA = 0, + _2MA = 0x0, _4MA = 0x01, _8MA = 0x02, _12MA = 0x03, @@ -32,7 +32,7 @@ impl From for u8 { #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] pub enum VoltageSelect { #[doc = "Set voltage to 3.3V (DVDD >= 2V5)"] - _3V3 = 0, + _3V3 = 0x0, #[doc = "Set voltage to 1.8V (DVDD <= 1V8)"] _1V8 = 0x01, } diff --git a/src/rp235x/pio.rs b/src/rp235x/pio.rs index 8f8cb9c2..ce1e4dd4 100644 --- a/src/rp235x/pio.rs +++ b/src/rp235x/pio.rs @@ -13,20 +13,20 @@ impl Irq { pub const fn as_ptr(&self) -> *mut () { self.ptr as _ } - #[doc = "Interrupt Enable for irq1"] + #[doc = "Interrupt Enable for irq0"] #[inline(always)] pub const fn inte(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(0usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x0usize) as _) } } - #[doc = "Interrupt Force for irq1"] + #[doc = "Interrupt Force for irq0"] #[inline(always)] pub const fn intf(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(4usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x04usize) as _) } } - #[doc = "Interrupt status after masking & forcing for irq1"] + #[doc = "Interrupt status after masking & forcing for irq0"] #[inline(always)] pub const fn ints(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(8usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x08usize) as _) } } } #[doc = "Programmable IO block"] @@ -48,64 +48,64 @@ impl Pio { #[doc = "PIO control register"] #[inline(always)] pub const fn ctrl(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(0usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x0usize) as _) } } #[doc = "FIFO status register"] #[inline(always)] pub const fn fstat(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(4usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x04usize) as _) } } #[doc = "FIFO debug register"] #[inline(always)] pub const fn fdebug(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(8usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x08usize) as _) } } #[doc = "FIFO levels"] #[inline(always)] pub const fn flevel(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(12usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x0cusize) as _) } } #[doc = "Direct write access to the TX FIFO for this state machine. Each write pushes one word to the FIFO. Attempting to write to a full FIFO has no effect on the FIFO state or contents, and sets the sticky FDEBUG_TXOVER error flag for this FIFO."] #[inline(always)] pub const fn txf(self, n: usize) -> crate::common::Reg { assert!(n < 4usize); - unsafe { crate::common::Reg::from_ptr(self.ptr.add(16usize + n * 4usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x10usize + n * 4usize) as _) } } #[doc = "Direct read access to the RX FIFO for this state machine. Each read pops one word from the FIFO. Attempting to read from an empty FIFO has no effect on the FIFO state, and sets the sticky FDEBUG_RXUNDER error flag for this FIFO. The data returned to the system on a read from an empty FIFO is undefined."] #[inline(always)] pub const fn rxf(self, n: usize) -> crate::common::Reg { assert!(n < 4usize); - unsafe { crate::common::Reg::from_ptr(self.ptr.add(32usize + n * 4usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x20usize + n * 4usize) as _) } } #[doc = "State machine IRQ flags register. Write 1 to clear. There are eight state machine IRQ flags, which can be set, cleared, and waited on by the state machines. There's no fixed association between flags and state machines -- any state machine can use any flag. Any of the eight flags can be used for timing synchronisation between state machines, using IRQ and WAIT instructions. Any combination of the eight flags can also routed out to either of the two system-level interrupt requests, alongside FIFO status interrupts -- see e.g. IRQ0_INTE."] #[inline(always)] pub const fn irq(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(48usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x30usize) as _) } } #[doc = "Writing a 1 to each of these bits will forcibly assert the corresponding IRQ. Note this is different to the INTF register: writing here affects PIO internal state. INTF just asserts the processor-facing IRQ signal for testing ISRs, and is not visible to the state machines."] #[inline(always)] pub const fn irq_force(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(52usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x34usize) as _) } } #[doc = "There is a 2-flipflop synchronizer on each GPIO input, which protects PIO logic from metastabilities. This increases input delay, and for fast synchronous IO (e.g. SPI) these synchronizers may need to be bypassed. Each bit in this register corresponds to one GPIO. 0 -> input is synchronized (default) 1 -> synchronizer is bypassed If in doubt, leave this register as all zeroes."] #[inline(always)] pub const fn input_sync_bypass(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(56usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x38usize) as _) } } #[doc = "Read to sample the pad output values PIO is currently driving to the GPIOs. On RP2040 there are 30 GPIOs, so the two most significant bits are hardwired to 0."] #[inline(always)] pub const fn dbg_padout(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(60usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x3cusize) as _) } } #[doc = "Read to sample the pad output enables (direction) PIO is currently driving to the GPIOs. On RP2040 there are 30 GPIOs, so the two most significant bits are hardwired to 0."] #[inline(always)] pub const fn dbg_padoe(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(64usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x40usize) as _) } } #[doc = "The PIO hardware has some free parameters that may vary between chip products. These should be provided in the chip datasheet, but are also exposed here."] #[inline(always)] pub const fn dbg_cfginfo(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(68usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x44usize) as _) } } #[doc = "Write-only access to instruction memory location 0"] #[inline(always)] @@ -114,107 +114,54 @@ impl Pio { n: usize, ) -> crate::common::Reg { assert!(n < 32usize); - unsafe { crate::common::Reg::from_ptr(self.ptr.add(72usize + n * 4usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x48usize + n * 4usize) as _) } } #[inline(always)] pub const fn sm(self, n: usize) -> StateMachine { assert!(n < 4usize); - unsafe { StateMachine::from_ptr(self.ptr.add(200usize + n * 24usize) as _) } + unsafe { StateMachine::from_ptr(self.ptr.add(0xc8usize + n * 24usize) as _) } } - #[doc = "Direct read/write access to entry 0 of SM0's RX FIFO, if SHIFTCTRL_FJOIN_RX_PUT xor SHIFTCTRL_FJOIN_RX_GET is set."] #[inline(always)] - pub const fn rxf0_putget0(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(296usize) as _) } - } - #[doc = "Direct read/write access to entry 1 of SM0's RX FIFO, if SHIFTCTRL_FJOIN_RX_PUT xor SHIFTCTRL_FJOIN_RX_GET is set."] - #[inline(always)] - pub const fn rxf0_putget1(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(300usize) as _) } - } - #[doc = "Direct read/write access to entry 2 of SM0's RX FIFO, if SHIFTCTRL_FJOIN_RX_PUT xor SHIFTCTRL_FJOIN_RX_GET is set."] - #[inline(always)] - pub const fn rxf0_putget2(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(304usize) as _) } + pub const fn rxf_putget(self, n: usize) -> RxfPutGet { + assert!(n < 4usize); + unsafe { RxfPutGet::from_ptr(self.ptr.add(0x0128usize + n * 16usize) as _) } } - #[doc = "Direct read/write access to entry 3 of SM0's RX FIFO, if SHIFTCTRL_FJOIN_RX_PUT xor SHIFTCTRL_FJOIN_RX_GET is set."] + #[doc = "Relocate GPIO 0 (from PIO's point of view) in the system GPIO numbering, to access more than 32 GPIOs from PIO. Only the values 0 and 16 are supported (only bit 4 is writable)."] #[inline(always)] - pub const fn rxf0_putget3(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(308usize) as _) } + pub const fn gpiobase(self) -> crate::common::Reg { + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x0168usize) as _) } } - #[doc = "Direct read/write access to entry 0 of SM1's RX FIFO, if SHIFTCTRL_FJOIN_RX_PUT xor SHIFTCTRL_FJOIN_RX_GET is set."] + #[doc = "Raw Interrupts"] #[inline(always)] - pub const fn rxf1_putget0(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(312usize) as _) } + pub const fn intr(self) -> crate::common::Reg { + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x016cusize) as _) } } - #[doc = "Direct read/write access to entry 1 of SM1's RX FIFO, if SHIFTCTRL_FJOIN_RX_PUT xor SHIFTCTRL_FJOIN_RX_GET is set."] #[inline(always)] - pub const fn rxf1_putget1(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(316usize) as _) } + pub const fn irqs(self, n: usize) -> Irq { + assert!(n < 2usize); + unsafe { Irq::from_ptr(self.ptr.add(0x0170usize + n * 12usize) as _) } } - #[doc = "Direct read/write access to entry 2 of SM1's RX FIFO, if SHIFTCTRL_FJOIN_RX_PUT xor SHIFTCTRL_FJOIN_RX_GET is set."] +} +#[derive(Copy, Clone, Eq, PartialEq)] +pub struct RxfPutGet { + ptr: *mut u8, +} +unsafe impl Send for RxfPutGet {} +unsafe impl Sync for RxfPutGet {} +impl RxfPutGet { #[inline(always)] - pub const fn rxf1_putget2(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(320usize) as _) } + pub const unsafe fn from_ptr(ptr: *mut ()) -> Self { + Self { ptr: ptr as _ } } - #[doc = "Direct read/write access to entry 3 of SM1's RX FIFO, if SHIFTCTRL_FJOIN_RX_PUT xor SHIFTCTRL_FJOIN_RX_GET is set."] #[inline(always)] - pub const fn rxf1_putget3(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(324usize) as _) } + pub const fn as_ptr(&self) -> *mut () { + self.ptr as _ } #[doc = "Direct read/write access to entry 0 of SM2's RX FIFO, if SHIFTCTRL_FJOIN_RX_PUT xor SHIFTCTRL_FJOIN_RX_GET is set."] #[inline(always)] - pub const fn rxf2_putget0(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(328usize) as _) } - } - #[doc = "Direct read/write access to entry 1 of SM2's RX FIFO, if SHIFTCTRL_FJOIN_RX_PUT xor SHIFTCTRL_FJOIN_RX_GET is set."] - #[inline(always)] - pub const fn rxf2_putget1(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(332usize) as _) } - } - #[doc = "Direct read/write access to entry 2 of SM2's RX FIFO, if SHIFTCTRL_FJOIN_RX_PUT xor SHIFTCTRL_FJOIN_RX_GET is set."] - #[inline(always)] - pub const fn rxf2_putget2(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(336usize) as _) } - } - #[doc = "Direct read/write access to entry 3 of SM2's RX FIFO, if SHIFTCTRL_FJOIN_RX_PUT xor SHIFTCTRL_FJOIN_RX_GET is set."] - #[inline(always)] - pub const fn rxf2_putget3(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(340usize) as _) } - } - #[doc = "Direct read/write access to entry 0 of SM3's RX FIFO, if SHIFTCTRL_FJOIN_RX_PUT xor SHIFTCTRL_FJOIN_RX_GET is set."] - #[inline(always)] - pub const fn rxf3_putget0(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(344usize) as _) } - } - #[doc = "Direct read/write access to entry 1 of SM3's RX FIFO, if SHIFTCTRL_FJOIN_RX_PUT xor SHIFTCTRL_FJOIN_RX_GET is set."] - #[inline(always)] - pub const fn rxf3_putget1(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(348usize) as _) } - } - #[doc = "Direct read/write access to entry 2 of SM3's RX FIFO, if SHIFTCTRL_FJOIN_RX_PUT xor SHIFTCTRL_FJOIN_RX_GET is set."] - #[inline(always)] - pub const fn rxf3_putget2(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(352usize) as _) } - } - #[doc = "Direct read/write access to entry 3 of SM3's RX FIFO, if SHIFTCTRL_FJOIN_RX_PUT xor SHIFTCTRL_FJOIN_RX_GET is set."] - #[inline(always)] - pub const fn rxf3_putget3(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(356usize) as _) } - } - #[doc = "Relocate GPIO 0 (from PIO's point of view) in the system GPIO numbering, to access more than 32 GPIOs from PIO. Only the values 0 and 16 are supported (only bit 4 is writable)."] - #[inline(always)] - pub const fn gpiobase(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(360usize) as _) } - } - #[doc = "Raw Interrupts"] - #[inline(always)] - pub const fn intr(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(364usize) as _) } - } - #[inline(always)] - pub const fn irqs(self, n: usize) -> Irq { - assert!(n < 2usize); - unsafe { Irq::from_ptr(self.ptr.add(368usize + n * 12usize) as _) } + pub const fn putget(self, n: usize) -> crate::common::Reg { + assert!(n < 4usize); + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x0usize + n * 4usize) as _) } } } #[derive(Copy, Clone, Eq, PartialEq)] @@ -235,32 +182,32 @@ impl StateMachine { #[doc = "Clock divisor register for state machine 3 Frequency = clock freq / (CLKDIV_INT + CLKDIV_FRAC / 256)"] #[inline(always)] pub const fn clkdiv(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(0usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x0usize) as _) } } #[doc = "Execution/behavioural settings for state machine 3"] #[inline(always)] pub const fn execctrl(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(4usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x04usize) as _) } } #[doc = "Control behaviour of the input/output shift registers for state machine 3"] #[inline(always)] pub const fn shiftctrl(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(8usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x08usize) as _) } } #[doc = "Current instruction address of state machine 3"] #[inline(always)] pub const fn addr(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(12usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x0cusize) as _) } } #[doc = "Read to see the instruction currently addressed by state machine 3's program counter Write to execute an instruction immediately (including jumps) and then resume execution."] #[inline(always)] pub const fn instr(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(16usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x10usize) as _) } } #[doc = "State machine pin control"] #[inline(always)] pub const fn pinctrl(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(20usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x14usize) as _) } } } pub mod regs; diff --git a/src/rp235x/pio/regs.rs b/src/rp235x/pio/regs.rs index 20515750..8e2da831 100644 --- a/src/rp235x/pio/regs.rs +++ b/src/rp235x/pio/regs.rs @@ -371,7 +371,7 @@ impl Default for Gpiobase { Gpiobase(0) } } -#[doc = "Write-only access to instruction memory location 2"] +#[doc = "Write-only access to instruction memory location 24"] #[repr(transparent)] #[derive(Copy, Clone, Eq, PartialEq)] pub struct InstrMem(pub u32); @@ -392,7 +392,7 @@ impl Default for InstrMem { InstrMem(0) } } -#[doc = "Interrupt Force for irq0"] +#[doc = "Raw Interrupts"] #[repr(transparent)] #[derive(Copy, Clone, Eq, PartialEq)] pub struct Intr(pub u32); @@ -590,7 +590,7 @@ impl Default for IrqForce { IrqForce(0) } } -#[doc = "Current instruction address of state machine 2"] +#[doc = "Current instruction address of state machine 1"] #[repr(transparent)] #[derive(Copy, Clone, Eq, PartialEq)] pub struct SmAddr(pub u32); @@ -645,7 +645,7 @@ impl Default for SmClkdiv { SmClkdiv(0) } } -#[doc = "Execution/behavioural settings for state machine 2"] +#[doc = "Execution/behavioural settings for state machine 0"] #[repr(transparent)] #[derive(Copy, Clone, Eq, PartialEq)] pub struct SmExecctrl(pub u32); @@ -778,7 +778,7 @@ impl Default for SmExecctrl { SmExecctrl(0) } } -#[doc = "Read to see the instruction currently addressed by state machine 1's program counter Write to execute an instruction immediately (including jumps) and then resume execution."] +#[doc = "Read to see the instruction currently addressed by state machine 2's program counter Write to execute an instruction immediately (including jumps) and then resume execution."] #[repr(transparent)] #[derive(Copy, Clone, Eq, PartialEq)] pub struct SmInstr(pub u32); @@ -888,7 +888,7 @@ impl Default for SmPinctrl { SmPinctrl(0) } } -#[doc = "Control behaviour of the input/output shift registers for state machine 3"] +#[doc = "Control behaviour of the input/output shift registers for state machine 0"] #[repr(transparent)] #[derive(Copy, Clone, Eq, PartialEq)] pub struct SmShiftctrl(pub u32); diff --git a/src/rp235x/pio/vals.rs b/src/rp235x/pio/vals.rs index 9f61b3b2..4ab01ba9 100644 --- a/src/rp235x/pio/vals.rs +++ b/src/rp235x/pio/vals.rs @@ -3,7 +3,7 @@ pub struct ExecctrlStatusN(pub u8); impl ExecctrlStatusN { #[doc = "Index 0-7 of an IRQ flag in this PIO block"] - pub const IRQ: Self = Self(0); + pub const IRQ: Self = Self(0x0); #[doc = "Index 0-7 of an IRQ flag in the next lower-numbered PIO block"] pub const IRQ_PREVPIO: Self = Self(0x08); #[doc = "Index 0-7 of an IRQ flag in the next higher-numbered PIO block"] @@ -33,7 +33,7 @@ impl From for u8 { #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] pub enum ExecctrlStatusSel { #[doc = "All-ones if TX FIFO level < N, otherwise all-zeroes"] - TXLEVEL = 0, + TXLEVEL = 0x0, #[doc = "All-ones if RX FIFO level < N, otherwise all-zeroes"] RXLEVEL = 0x01, #[doc = "All-ones if the indexed IRQ flag is raised, otherwise all-zeroes"] @@ -66,7 +66,7 @@ impl From for u8 { #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] pub enum Version { #[doc = "Version 0 (RP2040)"] - V0 = 0, + V0 = 0x0, #[doc = "Version 1 (RP2350)"] V1 = 0x01, _RESERVED_2 = 0x02, diff --git a/src/rp235x/pll.rs b/src/rp235x/pll.rs index db4207bc..26a466b8 100644 --- a/src/rp235x/pll.rs +++ b/src/rp235x/pll.rs @@ -16,42 +16,42 @@ impl Pll { #[doc = "Control and Status GENERAL CONSTRAINTS: Reference clock frequency min=5MHz, max=800MHz Feedback divider min=16, max=320 VCO frequency min=750MHz, max=1600MHz"] #[inline(always)] pub const fn cs(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(0usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x0usize) as _) } } #[doc = "Controls the PLL power modes."] #[inline(always)] pub const fn pwr(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(4usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x04usize) as _) } } #[doc = "Feedback divisor (note: this PLL does not support fractional division)"] #[inline(always)] pub const fn fbdiv_int(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(8usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x08usize) as _) } } #[doc = "Controls the PLL post dividers for the primary output (note: this PLL does not have a secondary output) the primary output is driven from VCO divided by postdiv1*postdiv2"] #[inline(always)] pub const fn prim(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(12usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x0cusize) as _) } } #[doc = "Raw Interrupts"] #[inline(always)] pub const fn intr(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(16usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x10usize) as _) } } #[doc = "Interrupt Enable"] #[inline(always)] pub const fn inte(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(20usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x14usize) as _) } } #[doc = "Interrupt Force"] #[inline(always)] pub const fn intf(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(24usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x18usize) as _) } } #[doc = "Interrupt status after masking & forcing"] #[inline(always)] pub const fn ints(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(28usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x1cusize) as _) } } } pub mod regs; diff --git a/src/rp235x/powman.rs b/src/rp235x/powman.rs index e321669a..0188f701 100644 --- a/src/rp235x/powman.rs +++ b/src/rp235x/powman.rs @@ -17,314 +17,252 @@ impl Powman { #[doc = "Indicates a bad password has been used"] #[inline(always)] pub const fn badpasswd(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(0usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x0usize) as _) } } #[doc = "Voltage Regulator Control"] #[inline(always)] pub const fn vreg_ctrl(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(4usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x04usize) as _) } } #[doc = "Voltage Regulator Status"] #[inline(always)] pub const fn vreg_sts(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(8usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x08usize) as _) } } #[doc = "Voltage Regulator Settings"] #[inline(always)] pub const fn vreg(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(12usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x0cusize) as _) } } #[doc = "Voltage Regulator Low Power Entry Settings"] #[inline(always)] pub const fn vreg_lp_entry(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(16usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x10usize) as _) } } #[doc = "Voltage Regulator Low Power Exit Settings"] #[inline(always)] pub const fn vreg_lp_exit(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(20usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x14usize) as _) } } #[doc = "Brown-out Detection Control"] #[inline(always)] pub const fn bod_ctrl(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(24usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x18usize) as _) } } #[doc = "Brown-out Detection Settings"] #[inline(always)] pub const fn bod(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(28usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x1cusize) as _) } } #[doc = "Brown-out Detection Low Power Entry Settings"] #[inline(always)] pub const fn bod_lp_entry(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(32usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x20usize) as _) } } #[doc = "Brown-out Detection Low Power Exit Settings"] #[inline(always)] pub const fn bod_lp_exit(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(36usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x24usize) as _) } } #[doc = "Low power oscillator control register."] #[inline(always)] pub const fn lposc(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(40usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x28usize) as _) } } #[doc = "Chip reset control and status"] #[inline(always)] pub const fn chip_reset(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(44usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x2cusize) as _) } } #[doc = "Allows a watchdog reset to reset the internal state of powman in addition to the power-on state machine (PSM). Note that powman ignores watchdog resets that do not select at least the CLOCKS stage or earlier stages in the PSM. If using these bits, it's recommended to set PSM_WDSEL to all-ones in addition to the desired bits in this register. Failing to select CLOCKS or earlier will result in the POWMAN_WDSEL register having no effect."] #[inline(always)] pub const fn wdsel(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(48usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x30usize) as _) } } #[doc = "For configuration of the power sequencer Writes are ignored while POWMAN_STATE_CHANGING=1"] #[inline(always)] pub const fn seq_cfg(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(52usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x34usize) as _) } } #[doc = "This register controls the power state of the 4 power domains. The current power state is indicated in POWMAN_STATE_CURRENT which is read-only. To change the state, write to POWMAN_STATE_REQ. The coding of POWMAN_STATE_CURRENT & POWMAN_STATE_REQ corresponds to the power states defined in the datasheet: bit 3 = SWCORE bit 2 = XIP cache bit 1 = SRAM0 bit 0 = SRAM1 0 = powered up 1 = powered down When POWMAN_STATE_REQ is written, the POWMAN_STATE_WAITING flag is set while the Power Manager determines what is required. If an invalid transition is requested the Power Manager will still register the request in POWMAN_STATE_REQ but will also set the POWMAN_BAD_REQ flag. It will then implement the power-up requests and ignore the power down requests. To do nothing would risk entering an unrecoverable lock-up state. Invalid requests are: any combination of power up and power down requests any request that results in swcore boing powered and xip unpowered If the request is to power down the switched-core domain then POWMAN_STATE_WAITING stays active until the processors halt. During this time the POWMAN_STATE_REQ field can be re-written to change or cancel the request. When the power state transition begins the POWMAN_STATE_WAITING_flag is cleared, the POWMAN_STATE_CHANGING flag is set and POWMAN register writes are ignored until the transition completes."] #[inline(always)] pub const fn state(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(56usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x38usize) as _) } } #[inline(always)] pub const fn pow_fastdiv(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(60usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x3cusize) as _) } } #[doc = "power state machine delays"] #[inline(always)] pub const fn pow_delay(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(64usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x40usize) as _) } } #[doc = "Configures a gpio as a power mode aware control output"] #[inline(always)] - pub const fn ext_ctrl0(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(68usize) as _) } + pub const fn ext_ctrl0(self) -> crate::common::Reg { + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x44usize) as _) } } #[doc = "Configures a gpio as a power mode aware control output"] #[inline(always)] - pub const fn ext_ctrl1(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(72usize) as _) } + pub const fn ext_ctrl1(self) -> crate::common::Reg { + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x48usize) as _) } } #[doc = "Select a GPIO to use as a time reference, the source can be used to drive the low power clock at 32kHz, or to provide a 1ms tick to the timer, or provide a 1Hz tick to the timer. The tick selection is controlled by the POWMAN_TIMER register."] #[inline(always)] pub const fn ext_time_ref(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(76usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x4cusize) as _) } } #[doc = "Informs the AON Timer of the integer component of the clock frequency when running off the LPOSC."] #[inline(always)] pub const fn lposc_freq_khz_int( self, ) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(80usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x50usize) as _) } } #[doc = "Informs the AON Timer of the fractional component of the clock frequency when running off the LPOSC."] #[inline(always)] pub const fn lposc_freq_khz_frac( self, ) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(84usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x54usize) as _) } } #[doc = "Informs the AON Timer of the integer component of the clock frequency when running off the XOSC."] #[inline(always)] pub const fn xosc_freq_khz_int( self, ) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(88usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x58usize) as _) } } #[doc = "Informs the AON Timer of the fractional component of the clock frequency when running off the XOSC."] #[inline(always)] pub const fn xosc_freq_khz_frac( self, ) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(92usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x5cusize) as _) } } #[inline(always)] pub const fn set_time_63to48( self, ) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(96usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x60usize) as _) } } #[inline(always)] pub const fn set_time_47to32( self, ) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(100usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x64usize) as _) } } #[inline(always)] pub const fn set_time_31to16( self, ) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(104usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x68usize) as _) } } #[inline(always)] pub const fn set_time_15to0(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(108usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x6cusize) as _) } } #[inline(always)] pub const fn read_time_upper(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(112usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x70usize) as _) } } #[inline(always)] pub const fn read_time_lower(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(116usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x74usize) as _) } } #[inline(always)] pub const fn alarm_time_63to48( self, ) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(120usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x78usize) as _) } } #[inline(always)] pub const fn alarm_time_47to32( self, ) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(124usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x7cusize) as _) } } #[inline(always)] pub const fn alarm_time_31to16( self, ) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(128usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x80usize) as _) } } #[inline(always)] pub const fn alarm_time_15to0( self, ) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(132usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x84usize) as _) } } #[inline(always)] pub const fn timer(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(136usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x88usize) as _) } } #[doc = "4 GPIO powerup events can be configured to wake the chip up from a low power state. The pwrups are level/edge sensitive and can be set to trigger on a high/rising or low/falling event The number of gpios available depends on the package option. An invalid selection will be ignored source = 0 selects gpio0 . . source = 47 selects gpio47 source = 48 selects qspi_ss source = 49 selects qspi_sd0 source = 50 selects qspi_sd1 source = 51 selects qspi_sd2 source = 52 selects qspi_sd3 source = 53 selects qspi_sclk level = 0 triggers the pwrup when the source is low level = 1 triggers the pwrup when the source is high"] #[inline(always)] - pub const fn pwrup0(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(140usize) as _) } - } - #[doc = "4 GPIO powerup events can be configured to wake the chip up from a low power state. The pwrups are level/edge sensitive and can be set to trigger on a high/rising or low/falling event The number of gpios available depends on the package option. An invalid selection will be ignored source = 0 selects gpio0 . . source = 47 selects gpio47 source = 48 selects qspi_ss source = 49 selects qspi_sd0 source = 50 selects qspi_sd1 source = 51 selects qspi_sd2 source = 52 selects qspi_sd3 source = 53 selects qspi_sclk level = 0 triggers the pwrup when the source is low level = 1 triggers the pwrup when the source is high"] - #[inline(always)] - pub const fn pwrup1(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(144usize) as _) } - } - #[doc = "4 GPIO powerup events can be configured to wake the chip up from a low power state. The pwrups are level/edge sensitive and can be set to trigger on a high/rising or low/falling event The number of gpios available depends on the package option. An invalid selection will be ignored source = 0 selects gpio0 . . source = 47 selects gpio47 source = 48 selects qspi_ss source = 49 selects qspi_sd0 source = 50 selects qspi_sd1 source = 51 selects qspi_sd2 source = 52 selects qspi_sd3 source = 53 selects qspi_sclk level = 0 triggers the pwrup when the source is low level = 1 triggers the pwrup when the source is high"] - #[inline(always)] - pub const fn pwrup2(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(148usize) as _) } - } - #[doc = "4 GPIO powerup events can be configured to wake the chip up from a low power state. The pwrups are level/edge sensitive and can be set to trigger on a high/rising or low/falling event The number of gpios available depends on the package option. An invalid selection will be ignored source = 0 selects gpio0 . . source = 47 selects gpio47 source = 48 selects qspi_ss source = 49 selects qspi_sd0 source = 50 selects qspi_sd1 source = 51 selects qspi_sd2 source = 52 selects qspi_sd3 source = 53 selects qspi_sclk level = 0 triggers the pwrup when the source is low level = 1 triggers the pwrup when the source is high"] - #[inline(always)] - pub const fn pwrup3(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(152usize) as _) } + pub const fn pwrup(self, n: usize) -> crate::common::Reg { + assert!(n < 4usize); + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x8cusize + n * 4usize) as _) } } #[doc = "Indicates current powerup request state pwrup events can be cleared by removing the enable from the pwrup register. The alarm pwrup req can be cleared by clearing timer.alarm_enab 0 = chip reset, for the source of the last reset see POWMAN_CHIP_RESET 1 = pwrup0 2 = pwrup1 3 = pwrup2 4 = pwrup3 5 = coresight_pwrup 6 = alarm_pwrup"] #[inline(always)] pub const fn current_pwrup_req( self, ) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(156usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x9cusize) as _) } } #[doc = "Indicates which pwrup source triggered the last switched-core power up 0 = chip reset, for the source of the last reset see POWMAN_CHIP_RESET 1 = pwrup0 2 = pwrup1 3 = pwrup2 4 = pwrup3 5 = coresight_pwrup 6 = alarm_pwrup"] #[inline(always)] pub const fn last_swcore_pwrup( self, ) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(160usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0xa0usize) as _) } } #[inline(always)] pub const fn dbg_pwrcfg(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(164usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0xa4usize) as _) } } #[doc = "Tell the bootrom to ignore the BOOT0..3 registers following the next RSM reset (e.g. the next core power down/up). If an early boot stage has soft-locked some OTP pages in order to protect their contents from later stages, there is a risk that Secure code running at a later stage can unlock the pages by powering the core up and down. This register can be used to ensure that the bootloader runs as normal on the next power up, preventing Secure code at a later stage from accessing OTP in its unlocked state. Should be used in conjunction with the OTP BOOTDIS register."] #[inline(always)] pub const fn bootdis(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(168usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0xa8usize) as _) } } #[inline(always)] pub const fn dbgconfig(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(172usize) as _) } - } - #[doc = "Scratch register. Information persists in low power mode"] - #[inline(always)] - pub const fn scratch0(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(176usize) as _) } - } - #[doc = "Scratch register. Information persists in low power mode"] - #[inline(always)] - pub const fn scratch1(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(180usize) as _) } - } - #[doc = "Scratch register. Information persists in low power mode"] - #[inline(always)] - pub const fn scratch2(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(184usize) as _) } - } - #[doc = "Scratch register. Information persists in low power mode"] - #[inline(always)] - pub const fn scratch3(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(188usize) as _) } - } - #[doc = "Scratch register. Information persists in low power mode"] - #[inline(always)] - pub const fn scratch4(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(192usize) as _) } - } - #[doc = "Scratch register. Information persists in low power mode"] - #[inline(always)] - pub const fn scratch5(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(196usize) as _) } - } - #[doc = "Scratch register. Information persists in low power mode"] - #[inline(always)] - pub const fn scratch6(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(200usize) as _) } - } - #[doc = "Scratch register. Information persists in low power mode"] - #[inline(always)] - pub const fn scratch7(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(204usize) as _) } - } - #[doc = "Scratch register. Information persists in low power mode"] - #[inline(always)] - pub const fn boot0(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(208usize) as _) } - } - #[doc = "Scratch register. Information persists in low power mode"] - #[inline(always)] - pub const fn boot1(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(212usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0xacusize) as _) } } #[doc = "Scratch register. Information persists in low power mode"] #[inline(always)] - pub const fn boot2(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(216usize) as _) } + pub const fn scratch(self, n: usize) -> crate::common::Reg { + assert!(n < 8usize); + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0xb0usize + n * 4usize) as _) } } #[doc = "Scratch register. Information persists in low power mode"] #[inline(always)] - pub const fn boot3(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(220usize) as _) } + pub const fn boot(self, n: usize) -> crate::common::Reg { + assert!(n < 4usize); + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0xd0usize + n * 4usize) as _) } } #[doc = "Raw Interrupts"] #[inline(always)] - pub const fn intr(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(224usize) as _) } + pub const fn intr(self) -> crate::common::Reg { + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0xe0usize) as _) } } #[doc = "Interrupt Enable"] #[inline(always)] - pub const fn inte(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(228usize) as _) } + pub const fn inte(self) -> crate::common::Reg { + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0xe4usize) as _) } } #[doc = "Interrupt Force"] #[inline(always)] - pub const fn intf(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(232usize) as _) } + pub const fn intf(self) -> crate::common::Reg { + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0xe8usize) as _) } } #[doc = "Interrupt status after masking & forcing"] #[inline(always)] - pub const fn ints(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(236usize) as _) } + pub const fn ints(self) -> crate::common::Reg { + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0xecusize) as _) } } } pub mod regs; diff --git a/src/rp235x/powman/regs.rs b/src/rp235x/powman/regs.rs index 059ae24a..243b16d3 100644 --- a/src/rp235x/powman/regs.rs +++ b/src/rp235x/powman/regs.rs @@ -500,8 +500,8 @@ impl Default for Dbgconfig { #[doc = "Configures a gpio as a power mode aware control output"] #[repr(transparent)] #[derive(Copy, Clone, Eq, PartialEq)] -pub struct ExtCtrl0(pub u32); -impl ExtCtrl0 { +pub struct ExtCtrl(pub u32); +impl ExtCtrl { #[doc = "selects from gpio 0->30 set to 31 to disable this feature"] #[inline(always)] pub const fn gpio_select(&self) -> u8 { @@ -554,73 +554,10 @@ impl ExtCtrl0 { self.0 = (self.0 & !(0x01 << 14usize)) | (((val as u32) & 0x01) << 14usize); } } -impl Default for ExtCtrl0 { +impl Default for ExtCtrl { #[inline(always)] - fn default() -> ExtCtrl0 { - ExtCtrl0(0) - } -} -#[doc = "Configures a gpio as a power mode aware control output"] -#[repr(transparent)] -#[derive(Copy, Clone, Eq, PartialEq)] -pub struct ExtCtrl1(pub u32); -impl ExtCtrl1 { - #[doc = "selects from gpio 0->30 set to 31 to disable this feature"] - #[inline(always)] - pub const fn gpio_select(&self) -> u8 { - let val = (self.0 >> 0usize) & 0x3f; - val as u8 - } - #[doc = "selects from gpio 0->30 set to 31 to disable this feature"] - #[inline(always)] - pub fn set_gpio_select(&mut self, val: u8) { - self.0 = (self.0 & !(0x3f << 0usize)) | (((val as u32) & 0x3f) << 0usize); - } - #[inline(always)] - pub const fn init(&self) -> bool { - let val = (self.0 >> 8usize) & 0x01; - val != 0 - } - #[inline(always)] - pub fn set_init(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 8usize)) | (((val as u32) & 0x01) << 8usize); - } - #[inline(always)] - pub const fn init_state(&self) -> bool { - let val = (self.0 >> 12usize) & 0x01; - val != 0 - } - #[inline(always)] - pub fn set_init_state(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 12usize)) | (((val as u32) & 0x01) << 12usize); - } - #[doc = "output level when entering the low power state"] - #[inline(always)] - pub const fn lp_entry_state(&self) -> bool { - let val = (self.0 >> 13usize) & 0x01; - val != 0 - } - #[doc = "output level when entering the low power state"] - #[inline(always)] - pub fn set_lp_entry_state(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 13usize)) | (((val as u32) & 0x01) << 13usize); - } - #[doc = "output level when exiting the low power state"] - #[inline(always)] - pub const fn lp_exit_state(&self) -> bool { - let val = (self.0 >> 14usize) & 0x01; - val != 0 - } - #[doc = "output level when exiting the low power state"] - #[inline(always)] - pub fn set_lp_exit_state(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 14usize)) | (((val as u32) & 0x01) << 14usize); - } -} -impl Default for ExtCtrl1 { - #[inline(always)] - fn default() -> ExtCtrl1 { - ExtCtrl1(0) + fn default() -> ExtCtrl { + ExtCtrl(0) } } #[doc = "Select a GPIO to use as a time reference, the source can be used to drive the low power clock at 32kHz, or to provide a 1ms tick to the timer, or provide a 1Hz tick to the timer. The tick selection is controlled by the POWMAN_TIMER register."] @@ -660,8 +597,8 @@ impl Default for ExtTimeRef { #[doc = "Interrupt Enable"] #[repr(transparent)] #[derive(Copy, Clone, Eq, PartialEq)] -pub struct Inte(pub u32); -impl Inte { +pub struct Int(pub u32); +impl Int { #[inline(always)] pub const fn vreg_output_low(&self) -> bool { let val = (self.0 >> 0usize) & 0x01; @@ -703,166 +640,10 @@ impl Inte { self.0 = (self.0 & !(0x01 << 3usize)) | (((val as u32) & 0x01) << 3usize); } } -impl Default for Inte { - #[inline(always)] - fn default() -> Inte { - Inte(0) - } -} -#[doc = "Interrupt Force"] -#[repr(transparent)] -#[derive(Copy, Clone, Eq, PartialEq)] -pub struct Intf(pub u32); -impl Intf { - #[inline(always)] - pub const fn vreg_output_low(&self) -> bool { - let val = (self.0 >> 0usize) & 0x01; - val != 0 - } - #[inline(always)] - pub fn set_vreg_output_low(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize); - } - #[inline(always)] - pub const fn timer(&self) -> bool { - let val = (self.0 >> 1usize) & 0x01; - val != 0 - } - #[inline(always)] - pub fn set_timer(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize); - } - #[doc = "Source is state.req_ignored"] - #[inline(always)] - pub const fn state_req_ignored(&self) -> bool { - let val = (self.0 >> 2usize) & 0x01; - val != 0 - } - #[doc = "Source is state.req_ignored"] - #[inline(always)] - pub fn set_state_req_ignored(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 2usize)) | (((val as u32) & 0x01) << 2usize); - } - #[doc = "Source is state.pwrup_while_waiting"] +impl Default for Int { #[inline(always)] - pub const fn pwrup_while_waiting(&self) -> bool { - let val = (self.0 >> 3usize) & 0x01; - val != 0 - } - #[doc = "Source is state.pwrup_while_waiting"] - #[inline(always)] - pub fn set_pwrup_while_waiting(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 3usize)) | (((val as u32) & 0x01) << 3usize); - } -} -impl Default for Intf { - #[inline(always)] - fn default() -> Intf { - Intf(0) - } -} -#[doc = "Raw Interrupts"] -#[repr(transparent)] -#[derive(Copy, Clone, Eq, PartialEq)] -pub struct Intr(pub u32); -impl Intr { - #[inline(always)] - pub const fn vreg_output_low(&self) -> bool { - let val = (self.0 >> 0usize) & 0x01; - val != 0 - } - #[inline(always)] - pub fn set_vreg_output_low(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize); - } - #[inline(always)] - pub const fn timer(&self) -> bool { - let val = (self.0 >> 1usize) & 0x01; - val != 0 - } - #[inline(always)] - pub fn set_timer(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize); - } - #[doc = "Source is state.req_ignored"] - #[inline(always)] - pub const fn state_req_ignored(&self) -> bool { - let val = (self.0 >> 2usize) & 0x01; - val != 0 - } - #[doc = "Source is state.req_ignored"] - #[inline(always)] - pub fn set_state_req_ignored(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 2usize)) | (((val as u32) & 0x01) << 2usize); - } - #[doc = "Source is state.pwrup_while_waiting"] - #[inline(always)] - pub const fn pwrup_while_waiting(&self) -> bool { - let val = (self.0 >> 3usize) & 0x01; - val != 0 - } - #[doc = "Source is state.pwrup_while_waiting"] - #[inline(always)] - pub fn set_pwrup_while_waiting(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 3usize)) | (((val as u32) & 0x01) << 3usize); - } -} -impl Default for Intr { - #[inline(always)] - fn default() -> Intr { - Intr(0) - } -} -#[doc = "Interrupt status after masking & forcing"] -#[repr(transparent)] -#[derive(Copy, Clone, Eq, PartialEq)] -pub struct Ints(pub u32); -impl Ints { - #[inline(always)] - pub const fn vreg_output_low(&self) -> bool { - let val = (self.0 >> 0usize) & 0x01; - val != 0 - } - #[inline(always)] - pub fn set_vreg_output_low(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize); - } - #[inline(always)] - pub const fn timer(&self) -> bool { - let val = (self.0 >> 1usize) & 0x01; - val != 0 - } - #[inline(always)] - pub fn set_timer(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize); - } - #[doc = "Source is state.req_ignored"] - #[inline(always)] - pub const fn state_req_ignored(&self) -> bool { - let val = (self.0 >> 2usize) & 0x01; - val != 0 - } - #[doc = "Source is state.req_ignored"] - #[inline(always)] - pub fn set_state_req_ignored(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 2usize)) | (((val as u32) & 0x01) << 2usize); - } - #[doc = "Source is state.pwrup_while_waiting"] - #[inline(always)] - pub const fn pwrup_while_waiting(&self) -> bool { - let val = (self.0 >> 3usize) & 0x01; - val != 0 - } - #[doc = "Source is state.pwrup_while_waiting"] - #[inline(always)] - pub fn set_pwrup_while_waiting(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 3usize)) | (((val as u32) & 0x01) << 3usize); - } -} -impl Default for Ints { - #[inline(always)] - fn default() -> Ints { - Ints(0) + fn default() -> Int { + Int(0) } } #[doc = "Indicates which pwrup source triggered the last switched-core power up 0 = chip reset, for the source of the last reset see POWMAN_CHIP_RESET 1 = pwrup0 2 = pwrup1 3 = pwrup2 4 = pwrup3 5 = coresight_pwrup 6 = alarm_pwrup"] @@ -1036,230 +817,8 @@ impl Default for PowFastdiv { #[doc = "4 GPIO powerup events can be configured to wake the chip up from a low power state. The pwrups are level/edge sensitive and can be set to trigger on a high/rising or low/falling event The number of gpios available depends on the package option. An invalid selection will be ignored source = 0 selects gpio0 . . source = 47 selects gpio47 source = 48 selects qspi_ss source = 49 selects qspi_sd0 source = 50 selects qspi_sd1 source = 51 selects qspi_sd2 source = 52 selects qspi_sd3 source = 53 selects qspi_sclk level = 0 triggers the pwrup when the source is low level = 1 triggers the pwrup when the source is high"] #[repr(transparent)] #[derive(Copy, Clone, Eq, PartialEq)] -pub struct Pwrup0(pub u32); -impl Pwrup0 { - #[inline(always)] - pub const fn source(&self) -> u8 { - let val = (self.0 >> 0usize) & 0x3f; - val as u8 - } - #[inline(always)] - pub fn set_source(&mut self, val: u8) { - self.0 = (self.0 & !(0x3f << 0usize)) | (((val as u32) & 0x3f) << 0usize); - } - #[doc = "Set to 1 to enable the wakeup source. Set to 0 to disable the wakeup source and clear a pending wakeup event. If using edge detect a latched edge needs to be cleared by writing 1 to the status register also."] - #[inline(always)] - pub const fn enable(&self) -> bool { - let val = (self.0 >> 6usize) & 0x01; - val != 0 - } - #[doc = "Set to 1 to enable the wakeup source. Set to 0 to disable the wakeup source and clear a pending wakeup event. If using edge detect a latched edge needs to be cleared by writing 1 to the status register also."] - #[inline(always)] - pub fn set_enable(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 6usize)) | (((val as u32) & 0x01) << 6usize); - } - #[inline(always)] - pub const fn direction(&self) -> super::vals::Pwrup0direction { - let val = (self.0 >> 7usize) & 0x01; - super::vals::Pwrup0direction::from_bits(val as u8) - } - #[inline(always)] - pub fn set_direction(&mut self, val: super::vals::Pwrup0direction) { - self.0 = (self.0 & !(0x01 << 7usize)) | (((val.to_bits() as u32) & 0x01) << 7usize); - } - #[doc = "Edge or level detect. Edge will detect a 0 to 1 transition (or 1 to 0 transition). Level will detect a 1 or 0. Both types of event get latched into the current_pwrup_req register."] - #[inline(always)] - pub const fn mode(&self) -> super::vals::Pwrup0mode { - let val = (self.0 >> 8usize) & 0x01; - super::vals::Pwrup0mode::from_bits(val as u8) - } - #[doc = "Edge or level detect. Edge will detect a 0 to 1 transition (or 1 to 0 transition). Level will detect a 1 or 0. Both types of event get latched into the current_pwrup_req register."] - #[inline(always)] - pub fn set_mode(&mut self, val: super::vals::Pwrup0mode) { - self.0 = (self.0 & !(0x01 << 8usize)) | (((val.to_bits() as u32) & 0x01) << 8usize); - } - #[doc = "Status of gpio wakeup. Write to 1 to clear a latched edge detect."] - #[inline(always)] - pub const fn status(&self) -> bool { - let val = (self.0 >> 9usize) & 0x01; - val != 0 - } - #[doc = "Status of gpio wakeup. Write to 1 to clear a latched edge detect."] - #[inline(always)] - pub fn set_status(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 9usize)) | (((val as u32) & 0x01) << 9usize); - } - #[doc = "Value of selected gpio pin (only if enable == 1)"] - #[inline(always)] - pub const fn raw_status(&self) -> bool { - let val = (self.0 >> 10usize) & 0x01; - val != 0 - } - #[doc = "Value of selected gpio pin (only if enable == 1)"] - #[inline(always)] - pub fn set_raw_status(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 10usize)) | (((val as u32) & 0x01) << 10usize); - } -} -impl Default for Pwrup0 { - #[inline(always)] - fn default() -> Pwrup0 { - Pwrup0(0) - } -} -#[doc = "4 GPIO powerup events can be configured to wake the chip up from a low power state. The pwrups are level/edge sensitive and can be set to trigger on a high/rising or low/falling event The number of gpios available depends on the package option. An invalid selection will be ignored source = 0 selects gpio0 . . source = 47 selects gpio47 source = 48 selects qspi_ss source = 49 selects qspi_sd0 source = 50 selects qspi_sd1 source = 51 selects qspi_sd2 source = 52 selects qspi_sd3 source = 53 selects qspi_sclk level = 0 triggers the pwrup when the source is low level = 1 triggers the pwrup when the source is high"] -#[repr(transparent)] -#[derive(Copy, Clone, Eq, PartialEq)] -pub struct Pwrup1(pub u32); -impl Pwrup1 { - #[inline(always)] - pub const fn source(&self) -> u8 { - let val = (self.0 >> 0usize) & 0x3f; - val as u8 - } - #[inline(always)] - pub fn set_source(&mut self, val: u8) { - self.0 = (self.0 & !(0x3f << 0usize)) | (((val as u32) & 0x3f) << 0usize); - } - #[doc = "Set to 1 to enable the wakeup source. Set to 0 to disable the wakeup source and clear a pending wakeup event. If using edge detect a latched edge needs to be cleared by writing 1 to the status register also."] - #[inline(always)] - pub const fn enable(&self) -> bool { - let val = (self.0 >> 6usize) & 0x01; - val != 0 - } - #[doc = "Set to 1 to enable the wakeup source. Set to 0 to disable the wakeup source and clear a pending wakeup event. If using edge detect a latched edge needs to be cleared by writing 1 to the status register also."] - #[inline(always)] - pub fn set_enable(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 6usize)) | (((val as u32) & 0x01) << 6usize); - } - #[inline(always)] - pub const fn direction(&self) -> super::vals::Pwrup1direction { - let val = (self.0 >> 7usize) & 0x01; - super::vals::Pwrup1direction::from_bits(val as u8) - } - #[inline(always)] - pub fn set_direction(&mut self, val: super::vals::Pwrup1direction) { - self.0 = (self.0 & !(0x01 << 7usize)) | (((val.to_bits() as u32) & 0x01) << 7usize); - } - #[doc = "Edge or level detect. Edge will detect a 0 to 1 transition (or 1 to 0 transition). Level will detect a 1 or 0. Both types of event get latched into the current_pwrup_req register."] - #[inline(always)] - pub const fn mode(&self) -> super::vals::Pwrup1mode { - let val = (self.0 >> 8usize) & 0x01; - super::vals::Pwrup1mode::from_bits(val as u8) - } - #[doc = "Edge or level detect. Edge will detect a 0 to 1 transition (or 1 to 0 transition). Level will detect a 1 or 0. Both types of event get latched into the current_pwrup_req register."] - #[inline(always)] - pub fn set_mode(&mut self, val: super::vals::Pwrup1mode) { - self.0 = (self.0 & !(0x01 << 8usize)) | (((val.to_bits() as u32) & 0x01) << 8usize); - } - #[doc = "Status of gpio wakeup. Write to 1 to clear a latched edge detect."] - #[inline(always)] - pub const fn status(&self) -> bool { - let val = (self.0 >> 9usize) & 0x01; - val != 0 - } - #[doc = "Status of gpio wakeup. Write to 1 to clear a latched edge detect."] - #[inline(always)] - pub fn set_status(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 9usize)) | (((val as u32) & 0x01) << 9usize); - } - #[doc = "Value of selected gpio pin (only if enable == 1)"] - #[inline(always)] - pub const fn raw_status(&self) -> bool { - let val = (self.0 >> 10usize) & 0x01; - val != 0 - } - #[doc = "Value of selected gpio pin (only if enable == 1)"] - #[inline(always)] - pub fn set_raw_status(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 10usize)) | (((val as u32) & 0x01) << 10usize); - } -} -impl Default for Pwrup1 { - #[inline(always)] - fn default() -> Pwrup1 { - Pwrup1(0) - } -} -#[doc = "4 GPIO powerup events can be configured to wake the chip up from a low power state. The pwrups are level/edge sensitive and can be set to trigger on a high/rising or low/falling event The number of gpios available depends on the package option. An invalid selection will be ignored source = 0 selects gpio0 . . source = 47 selects gpio47 source = 48 selects qspi_ss source = 49 selects qspi_sd0 source = 50 selects qspi_sd1 source = 51 selects qspi_sd2 source = 52 selects qspi_sd3 source = 53 selects qspi_sclk level = 0 triggers the pwrup when the source is low level = 1 triggers the pwrup when the source is high"] -#[repr(transparent)] -#[derive(Copy, Clone, Eq, PartialEq)] -pub struct Pwrup2(pub u32); -impl Pwrup2 { - #[inline(always)] - pub const fn source(&self) -> u8 { - let val = (self.0 >> 0usize) & 0x3f; - val as u8 - } - #[inline(always)] - pub fn set_source(&mut self, val: u8) { - self.0 = (self.0 & !(0x3f << 0usize)) | (((val as u32) & 0x3f) << 0usize); - } - #[doc = "Set to 1 to enable the wakeup source. Set to 0 to disable the wakeup source and clear a pending wakeup event. If using edge detect a latched edge needs to be cleared by writing 1 to the status register also."] - #[inline(always)] - pub const fn enable(&self) -> bool { - let val = (self.0 >> 6usize) & 0x01; - val != 0 - } - #[doc = "Set to 1 to enable the wakeup source. Set to 0 to disable the wakeup source and clear a pending wakeup event. If using edge detect a latched edge needs to be cleared by writing 1 to the status register also."] - #[inline(always)] - pub fn set_enable(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 6usize)) | (((val as u32) & 0x01) << 6usize); - } - #[inline(always)] - pub const fn direction(&self) -> super::vals::Pwrup2direction { - let val = (self.0 >> 7usize) & 0x01; - super::vals::Pwrup2direction::from_bits(val as u8) - } - #[inline(always)] - pub fn set_direction(&mut self, val: super::vals::Pwrup2direction) { - self.0 = (self.0 & !(0x01 << 7usize)) | (((val.to_bits() as u32) & 0x01) << 7usize); - } - #[doc = "Edge or level detect. Edge will detect a 0 to 1 transition (or 1 to 0 transition). Level will detect a 1 or 0. Both types of event get latched into the current_pwrup_req register."] - #[inline(always)] - pub const fn mode(&self) -> super::vals::Pwrup2mode { - let val = (self.0 >> 8usize) & 0x01; - super::vals::Pwrup2mode::from_bits(val as u8) - } - #[doc = "Edge or level detect. Edge will detect a 0 to 1 transition (or 1 to 0 transition). Level will detect a 1 or 0. Both types of event get latched into the current_pwrup_req register."] - #[inline(always)] - pub fn set_mode(&mut self, val: super::vals::Pwrup2mode) { - self.0 = (self.0 & !(0x01 << 8usize)) | (((val.to_bits() as u32) & 0x01) << 8usize); - } - #[doc = "Status of gpio wakeup. Write to 1 to clear a latched edge detect."] - #[inline(always)] - pub const fn status(&self) -> bool { - let val = (self.0 >> 9usize) & 0x01; - val != 0 - } - #[doc = "Status of gpio wakeup. Write to 1 to clear a latched edge detect."] - #[inline(always)] - pub fn set_status(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 9usize)) | (((val as u32) & 0x01) << 9usize); - } - #[doc = "Value of selected gpio pin (only if enable == 1)"] - #[inline(always)] - pub const fn raw_status(&self) -> bool { - let val = (self.0 >> 10usize) & 0x01; - val != 0 - } - #[doc = "Value of selected gpio pin (only if enable == 1)"] - #[inline(always)] - pub fn set_raw_status(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 10usize)) | (((val as u32) & 0x01) << 10usize); - } -} -impl Default for Pwrup2 { - #[inline(always)] - fn default() -> Pwrup2 { - Pwrup2(0) - } -} -#[doc = "4 GPIO powerup events can be configured to wake the chip up from a low power state. The pwrups are level/edge sensitive and can be set to trigger on a high/rising or low/falling event The number of gpios available depends on the package option. An invalid selection will be ignored source = 0 selects gpio0 . . source = 47 selects gpio47 source = 48 selects qspi_ss source = 49 selects qspi_sd0 source = 50 selects qspi_sd1 source = 51 selects qspi_sd2 source = 52 selects qspi_sd3 source = 53 selects qspi_sclk level = 0 triggers the pwrup when the source is low level = 1 triggers the pwrup when the source is high"] -#[repr(transparent)] -#[derive(Copy, Clone, Eq, PartialEq)] -pub struct Pwrup3(pub u32); -impl Pwrup3 { +pub struct Pwrup(pub u32); +impl Pwrup { #[inline(always)] pub const fn source(&self) -> u8 { let val = (self.0 >> 0usize) & 0x3f; @@ -1281,23 +840,23 @@ impl Pwrup3 { self.0 = (self.0 & !(0x01 << 6usize)) | (((val as u32) & 0x01) << 6usize); } #[inline(always)] - pub const fn direction(&self) -> super::vals::Pwrup3direction { + pub const fn direction(&self) -> super::vals::Direction { let val = (self.0 >> 7usize) & 0x01; - super::vals::Pwrup3direction::from_bits(val as u8) + super::vals::Direction::from_bits(val as u8) } #[inline(always)] - pub fn set_direction(&mut self, val: super::vals::Pwrup3direction) { + pub fn set_direction(&mut self, val: super::vals::Direction) { self.0 = (self.0 & !(0x01 << 7usize)) | (((val.to_bits() as u32) & 0x01) << 7usize); } #[doc = "Edge or level detect. Edge will detect a 0 to 1 transition (or 1 to 0 transition). Level will detect a 1 or 0. Both types of event get latched into the current_pwrup_req register."] #[inline(always)] - pub const fn mode(&self) -> super::vals::Pwrup3mode { + pub const fn mode(&self) -> super::vals::Mode { let val = (self.0 >> 8usize) & 0x01; - super::vals::Pwrup3mode::from_bits(val as u8) + super::vals::Mode::from_bits(val as u8) } #[doc = "Edge or level detect. Edge will detect a 0 to 1 transition (or 1 to 0 transition). Level will detect a 1 or 0. Both types of event get latched into the current_pwrup_req register."] #[inline(always)] - pub fn set_mode(&mut self, val: super::vals::Pwrup3mode) { + pub fn set_mode(&mut self, val: super::vals::Mode) { self.0 = (self.0 & !(0x01 << 8usize)) | (((val.to_bits() as u32) & 0x01) << 8usize); } #[doc = "Status of gpio wakeup. Write to 1 to clear a latched edge detect."] @@ -1323,10 +882,10 @@ impl Pwrup3 { self.0 = (self.0 & !(0x01 << 10usize)) | (((val as u32) & 0x01) << 10usize); } } -impl Default for Pwrup3 { +impl Default for Pwrup { #[inline(always)] - fn default() -> Pwrup3 { - Pwrup3(0) + fn default() -> Pwrup { + Pwrup(0) } } #[doc = "For configuration of the power sequencer Writes are ignored while POWMAN_STATE_CHANGING=1"] diff --git a/src/rp235x/powman/vals.rs b/src/rp235x/powman/vals.rs index 22a4e0ce..9196dbe6 100644 --- a/src/rp235x/powman/vals.rs +++ b/src/rp235x/powman/vals.rs @@ -1,12 +1,12 @@ #[repr(u8)] #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] -pub enum Pwrup0direction { - LOW_FALLING = 0, +pub enum Direction { + LOW_FALLING = 0x0, HIGH_RISING = 0x01, } -impl Pwrup0direction { +impl Direction { #[inline(always)] - pub const fn from_bits(val: u8) -> Pwrup0direction { + pub const fn from_bits(val: u8) -> Direction { unsafe { core::mem::transmute(val & 0x01) } } #[inline(always)] @@ -14,27 +14,27 @@ impl Pwrup0direction { unsafe { core::mem::transmute(self) } } } -impl From for Pwrup0direction { +impl From for Direction { #[inline(always)] - fn from(val: u8) -> Pwrup0direction { - Pwrup0direction::from_bits(val) + fn from(val: u8) -> Direction { + Direction::from_bits(val) } } -impl From for u8 { +impl From for u8 { #[inline(always)] - fn from(val: Pwrup0direction) -> u8 { - Pwrup0direction::to_bits(val) + fn from(val: Direction) -> u8 { + Direction::to_bits(val) } } #[repr(u8)] #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] -pub enum Pwrup0mode { - LEVEL = 0, +pub enum Mode { + LEVEL = 0x0, EDGE = 0x01, } -impl Pwrup0mode { +impl Mode { #[inline(always)] - pub const fn from_bits(val: u8) -> Pwrup0mode { + pub const fn from_bits(val: u8) -> Mode { unsafe { core::mem::transmute(val & 0x01) } } #[inline(always)] @@ -42,183 +42,15 @@ impl Pwrup0mode { unsafe { core::mem::transmute(self) } } } -impl From for Pwrup0mode { +impl From for Mode { #[inline(always)] - fn from(val: u8) -> Pwrup0mode { - Pwrup0mode::from_bits(val) + fn from(val: u8) -> Mode { + Mode::from_bits(val) } } -impl From for u8 { +impl From for u8 { #[inline(always)] - fn from(val: Pwrup0mode) -> u8 { - Pwrup0mode::to_bits(val) - } -} -#[repr(u8)] -#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] -pub enum Pwrup1direction { - LOW_FALLING = 0, - HIGH_RISING = 0x01, -} -impl Pwrup1direction { - #[inline(always)] - pub const fn from_bits(val: u8) -> Pwrup1direction { - unsafe { core::mem::transmute(val & 0x01) } - } - #[inline(always)] - pub const fn to_bits(self) -> u8 { - unsafe { core::mem::transmute(self) } - } -} -impl From for Pwrup1direction { - #[inline(always)] - fn from(val: u8) -> Pwrup1direction { - Pwrup1direction::from_bits(val) - } -} -impl From for u8 { - #[inline(always)] - fn from(val: Pwrup1direction) -> u8 { - Pwrup1direction::to_bits(val) - } -} -#[repr(u8)] -#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] -pub enum Pwrup1mode { - LEVEL = 0, - EDGE = 0x01, -} -impl Pwrup1mode { - #[inline(always)] - pub const fn from_bits(val: u8) -> Pwrup1mode { - unsafe { core::mem::transmute(val & 0x01) } - } - #[inline(always)] - pub const fn to_bits(self) -> u8 { - unsafe { core::mem::transmute(self) } - } -} -impl From for Pwrup1mode { - #[inline(always)] - fn from(val: u8) -> Pwrup1mode { - Pwrup1mode::from_bits(val) - } -} -impl From for u8 { - #[inline(always)] - fn from(val: Pwrup1mode) -> u8 { - Pwrup1mode::to_bits(val) - } -} -#[repr(u8)] -#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] -pub enum Pwrup2direction { - LOW_FALLING = 0, - HIGH_RISING = 0x01, -} -impl Pwrup2direction { - #[inline(always)] - pub const fn from_bits(val: u8) -> Pwrup2direction { - unsafe { core::mem::transmute(val & 0x01) } - } - #[inline(always)] - pub const fn to_bits(self) -> u8 { - unsafe { core::mem::transmute(self) } - } -} -impl From for Pwrup2direction { - #[inline(always)] - fn from(val: u8) -> Pwrup2direction { - Pwrup2direction::from_bits(val) - } -} -impl From for u8 { - #[inline(always)] - fn from(val: Pwrup2direction) -> u8 { - Pwrup2direction::to_bits(val) - } -} -#[repr(u8)] -#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] -pub enum Pwrup2mode { - LEVEL = 0, - EDGE = 0x01, -} -impl Pwrup2mode { - #[inline(always)] - pub const fn from_bits(val: u8) -> Pwrup2mode { - unsafe { core::mem::transmute(val & 0x01) } - } - #[inline(always)] - pub const fn to_bits(self) -> u8 { - unsafe { core::mem::transmute(self) } - } -} -impl From for Pwrup2mode { - #[inline(always)] - fn from(val: u8) -> Pwrup2mode { - Pwrup2mode::from_bits(val) - } -} -impl From for u8 { - #[inline(always)] - fn from(val: Pwrup2mode) -> u8 { - Pwrup2mode::to_bits(val) - } -} -#[repr(u8)] -#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] -pub enum Pwrup3direction { - LOW_FALLING = 0, - HIGH_RISING = 0x01, -} -impl Pwrup3direction { - #[inline(always)] - pub const fn from_bits(val: u8) -> Pwrup3direction { - unsafe { core::mem::transmute(val & 0x01) } - } - #[inline(always)] - pub const fn to_bits(self) -> u8 { - unsafe { core::mem::transmute(self) } - } -} -impl From for Pwrup3direction { - #[inline(always)] - fn from(val: u8) -> Pwrup3direction { - Pwrup3direction::from_bits(val) - } -} -impl From for u8 { - #[inline(always)] - fn from(val: Pwrup3direction) -> u8 { - Pwrup3direction::to_bits(val) - } -} -#[repr(u8)] -#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] -pub enum Pwrup3mode { - LEVEL = 0, - EDGE = 0x01, -} -impl Pwrup3mode { - #[inline(always)] - pub const fn from_bits(val: u8) -> Pwrup3mode { - unsafe { core::mem::transmute(val & 0x01) } - } - #[inline(always)] - pub const fn to_bits(self) -> u8 { - unsafe { core::mem::transmute(self) } - } -} -impl From for Pwrup3mode { - #[inline(always)] - fn from(val: u8) -> Pwrup3mode { - Pwrup3mode::from_bits(val) - } -} -impl From for u8 { - #[inline(always)] - fn from(val: Pwrup3mode) -> u8 { - Pwrup3mode::to_bits(val) + fn from(val: Mode) -> u8 { + Mode::to_bits(val) } } diff --git a/src/rp235x/psm.rs b/src/rp235x/psm.rs index 17805bc3..0634e610 100644 --- a/src/rp235x/psm.rs +++ b/src/rp235x/psm.rs @@ -16,22 +16,22 @@ impl Psm { #[doc = "Force block out of reset (i.e. power it on)"] #[inline(always)] pub const fn frce_on(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(0usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x0usize) as _) } } #[doc = "Force into reset (i.e. power it off)"] #[inline(always)] pub const fn frce_off(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(4usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x04usize) as _) } } #[doc = "Set to 1 if the watchdog should reset this"] #[inline(always)] pub const fn wdsel(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(8usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x08usize) as _) } } #[doc = "Is the subsystem ready?"] #[inline(always)] pub const fn done(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(12usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x0cusize) as _) } } } pub mod regs; diff --git a/src/rp235x/pwm.rs b/src/rp235x/pwm.rs index 12164a7d..0df6f1df 100644 --- a/src/rp235x/pwm.rs +++ b/src/rp235x/pwm.rs @@ -16,27 +16,27 @@ impl Channel { #[doc = "Control and status register"] #[inline(always)] pub const fn csr(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(0usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x0usize) as _) } } #[doc = "INT and FRAC form a fixed-point fractional number. Counting rate is system clock frequency divided by this number. Fractional division uses simple 1st-order sigma-delta."] #[inline(always)] pub const fn div(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(4usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x04usize) as _) } } #[doc = "Direct access to the PWM counter"] #[inline(always)] pub const fn ctr(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(8usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x08usize) as _) } } #[doc = "Counter compare values"] #[inline(always)] pub const fn cc(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(12usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x0cusize) as _) } } #[doc = "Counter wrap value"] #[inline(always)] pub const fn top(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(16usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x10usize) as _) } } } #[doc = "Simple PWM"] @@ -58,47 +58,47 @@ impl Pwm { #[inline(always)] pub const fn ch(self, n: usize) -> Channel { assert!(n < 12usize); - unsafe { Channel::from_ptr(self.ptr.add(0usize + n * 20usize) as _) } + unsafe { Channel::from_ptr(self.ptr.add(0x0usize + n * 20usize) as _) } } #[doc = "This register aliases the CSR_EN bits for all channels. Writing to this register allows multiple channels to be enabled or disabled simultaneously, so they can run in perfect sync. For each channel, there is only one physical EN register bit, which can be accessed through here or CHx_CSR."] #[inline(always)] pub const fn en(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(240usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0xf0usize) as _) } } #[doc = "Raw Interrupts"] #[inline(always)] pub const fn intr(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(244usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0xf4usize) as _) } } #[doc = "Interrupt Enable for irq0"] #[inline(always)] pub const fn irq0_inte(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(248usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0xf8usize) as _) } } #[doc = "Interrupt Force for irq0"] #[inline(always)] pub const fn irq0_intf(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(252usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0xfcusize) as _) } } #[doc = "Interrupt status after masking & forcing for irq0"] #[inline(always)] pub const fn irq0_ints(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(256usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x0100usize) as _) } } #[doc = "Interrupt Enable for irq1"] #[inline(always)] pub const fn irq1_inte(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(260usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x0104usize) as _) } } #[doc = "Interrupt Force for irq1"] #[inline(always)] pub const fn irq1_intf(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(264usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x0108usize) as _) } } #[doc = "Interrupt status after masking & forcing for irq1"] #[inline(always)] pub const fn irq1_ints(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(268usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x010cusize) as _) } } } pub mod regs; diff --git a/src/rp235x/pwm/vals.rs b/src/rp235x/pwm/vals.rs index cd8bad90..56a7f6d3 100644 --- a/src/rp235x/pwm/vals.rs +++ b/src/rp235x/pwm/vals.rs @@ -2,7 +2,7 @@ #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] pub enum Ch10csrDivmode { #[doc = "Free-running counting at rate dictated by fractional divider"] - DIV = 0, + DIV = 0x0, #[doc = "Fractional divider operation is gated by the PWM B pin."] LEVEL = 0x01, #[doc = "Counter advances with each rising edge of the PWM B pin."] @@ -36,7 +36,7 @@ impl From for u8 { #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] pub enum Ch11csrDivmode { #[doc = "Free-running counting at rate dictated by fractional divider"] - DIV = 0, + DIV = 0x0, #[doc = "Fractional divider operation is gated by the PWM B pin."] LEVEL = 0x01, #[doc = "Counter advances with each rising edge of the PWM B pin."] @@ -70,7 +70,7 @@ impl From for u8 { #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] pub enum Divmode { #[doc = "Free-running counting at rate dictated by fractional divider"] - DIV = 0, + DIV = 0x0, #[doc = "Fractional divider operation is gated by the PWM B pin."] LEVEL = 0x01, #[doc = "Counter advances with each rising edge of the PWM B pin."] diff --git a/src/rp235x/qmi.rs b/src/rp235x/qmi.rs index c1730113..4d925664 100644 --- a/src/rp235x/qmi.rs +++ b/src/rp235x/qmi.rs @@ -1,11 +1,10 @@ -#[doc = "QSPI Memory Interface. Provides a memory-mapped interface to up to two SPI/DSPI/QSPI flash or PSRAM devices. Also provides a serial interface for programming and configuration of the external device."] #[derive(Copy, Clone, Eq, PartialEq)] -pub struct Qmi { +pub struct Mem { ptr: *mut u8, } -unsafe impl Send for Qmi {} -unsafe impl Sync for Qmi {} -impl Qmi { +unsafe impl Send for Mem {} +unsafe impl Sync for Mem {} +impl Mem { #[inline(always)] pub const unsafe fn from_ptr(ptr: *mut ()) -> Self { Self { ptr: ptr as _ } @@ -14,110 +13,73 @@ impl Qmi { pub const fn as_ptr(&self) -> *mut () { self.ptr as _ } - #[doc = "Control and status for direct serial mode Direct serial mode allows the processor to send and receive raw serial frames, for programming, configuration and control of the external memory devices. Only SPI mode 0 (CPOL=0 CPHA=0) is supported."] - #[inline(always)] - pub const fn direct_csr(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(0usize) as _) } - } - #[doc = "Transmit FIFO for direct mode"] - #[inline(always)] - pub const fn direct_tx(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(4usize) as _) } - } - #[doc = "Receive FIFO for direct mode"] - #[inline(always)] - pub const fn direct_rx(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(8usize) as _) } - } - #[doc = "Timing configuration register for memory address window 0."] - #[inline(always)] - pub const fn m0_timing(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(12usize) as _) } - } - #[doc = "Read transfer format configuration for memory address window 0. Configure the bus width of each transfer phase individually, and configure the length or presence of the command prefix, command suffix and dummy/turnaround transfer phases. Only 24-bit addresses are supported. The reset value of the M0_RFMT register is configured to support a basic 03h serial read transfer with no additional configuration."] - #[inline(always)] - pub const fn m0_rfmt(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(16usize) as _) } - } - #[doc = "Command constants used for reads from memory address window 0. The reset value of the M0_RCMD register is configured to support a basic 03h serial read transfer with no additional configuration."] - #[inline(always)] - pub const fn m0_rcmd(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(20usize) as _) } - } - #[doc = "Write transfer format configuration for memory address window 0. Configure the bus width of each transfer phase individually, and configure the length or presence of the command prefix, command suffix and dummy/turnaround transfer phases. Only 24-bit addresses are supported. The reset value of the M0_WFMT register is configured to support a basic 02h serial write transfer. However, writes to this window must first be enabled via the XIP_CTRL_WRITABLE_M0 bit, as XIP memory is read-only by default."] - #[inline(always)] - pub const fn m0_wfmt(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(24usize) as _) } - } - #[doc = "Command constants used for writes to memory address window 0. The reset value of the M0_WCMD register is configured to support a basic 02h serial write transfer with no additional configuration."] - #[inline(always)] - pub const fn m0_wcmd(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(28usize) as _) } - } #[doc = "Timing configuration register for memory address window 1."] #[inline(always)] - pub const fn m1_timing(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(32usize) as _) } + pub const fn timing(self) -> crate::common::Reg { + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x0usize) as _) } } #[doc = "Read transfer format configuration for memory address window 1. Configure the bus width of each transfer phase individually, and configure the length or presence of the command prefix, command suffix and dummy/turnaround transfer phases. Only 24-bit addresses are supported. The reset value of the M1_RFMT register is configured to support a basic 03h serial read transfer with no additional configuration."] #[inline(always)] - pub const fn m1_rfmt(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(36usize) as _) } + pub const fn rfmt(self) -> crate::common::Reg { + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x04usize) as _) } } #[doc = "Command constants used for reads from memory address window 1. The reset value of the M1_RCMD register is configured to support a basic 03h serial read transfer with no additional configuration."] #[inline(always)] - pub const fn m1_rcmd(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(40usize) as _) } + pub const fn rcmd(self) -> crate::common::Reg { + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x08usize) as _) } } #[doc = "Write transfer format configuration for memory address window 1. Configure the bus width of each transfer phase individually, and configure the length or presence of the command prefix, command suffix and dummy/turnaround transfer phases. Only 24-bit addresses are supported. The reset value of the M1_WFMT register is configured to support a basic 02h serial write transfer. However, writes to this window must first be enabled via the XIP_CTRL_WRITABLE_M1 bit, as XIP memory is read-only by default."] #[inline(always)] - pub const fn m1_wfmt(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(44usize) as _) } + pub const fn wfmt(self) -> crate::common::Reg { + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x0cusize) as _) } } #[doc = "Command constants used for writes to memory address window 1. The reset value of the M1_WCMD register is configured to support a basic 02h serial write transfer with no additional configuration."] #[inline(always)] - pub const fn m1_wcmd(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(48usize) as _) } + pub const fn wcmd(self) -> crate::common::Reg { + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x10usize) as _) } } - #[doc = "Configure address translation for XIP virtual addresses 0x000000 through 0x3fffff (a 4 MiB window starting at +0 MiB). Address translation allows a program image to be executed in place at multiple physical flash addresses (for example, a double-buffered flash image for over-the-air updates), without the overhead of position-independent code. At reset, the address translation registers are initialised to an identity mapping, so that they can be ignored if address translation is not required. Note that the XIP cache is fully virtually addressed, so a cache flush is required after changing the address translation."] - #[inline(always)] - pub const fn atrans0(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(52usize) as _) } - } - #[doc = "Configure address translation for XIP virtual addresses 0x400000 through 0x7fffff (a 4 MiB window starting at +4 MiB). Address translation allows a program image to be executed in place at multiple physical flash addresses (for example, a double-buffered flash image for over-the-air updates), without the overhead of position-independent code. At reset, the address translation registers are initialised to an identity mapping, so that they can be ignored if address translation is not required. Note that the XIP cache is fully virtually addressed, so a cache flush is required after changing the address translation."] +} +#[doc = "QSPI Memory Interface. Provides a memory-mapped interface to up to two SPI/DSPI/QSPI flash or PSRAM devices. Also provides a serial interface for programming and configuration of the external device."] +#[derive(Copy, Clone, Eq, PartialEq)] +pub struct Qmi { + ptr: *mut u8, +} +unsafe impl Send for Qmi {} +unsafe impl Sync for Qmi {} +impl Qmi { #[inline(always)] - pub const fn atrans1(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(56usize) as _) } + pub const unsafe fn from_ptr(ptr: *mut ()) -> Self { + Self { ptr: ptr as _ } } - #[doc = "Configure address translation for XIP virtual addresses 0x800000 through 0xbfffff (a 4 MiB window starting at +8 MiB). Address translation allows a program image to be executed in place at multiple physical flash addresses (for example, a double-buffered flash image for over-the-air updates), without the overhead of position-independent code. At reset, the address translation registers are initialised to an identity mapping, so that they can be ignored if address translation is not required. Note that the XIP cache is fully virtually addressed, so a cache flush is required after changing the address translation."] #[inline(always)] - pub const fn atrans2(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(60usize) as _) } + pub const fn as_ptr(&self) -> *mut () { + self.ptr as _ } - #[doc = "Configure address translation for XIP virtual addresses 0xc00000 through 0xffffff (a 4 MiB window starting at +12 MiB). Address translation allows a program image to be executed in place at multiple physical flash addresses (for example, a double-buffered flash image for over-the-air updates), without the overhead of position-independent code. At reset, the address translation registers are initialised to an identity mapping, so that they can be ignored if address translation is not required. Note that the XIP cache is fully virtually addressed, so a cache flush is required after changing the address translation."] + #[doc = "Control and status for direct serial mode Direct serial mode allows the processor to send and receive raw serial frames, for programming, configuration and control of the external memory devices. Only SPI mode 0 (CPOL=0 CPHA=0) is supported."] #[inline(always)] - pub const fn atrans3(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(64usize) as _) } + pub const fn direct_csr(self) -> crate::common::Reg { + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x0usize) as _) } } - #[doc = "Configure address translation for XIP virtual addresses 0x1000000 through 0x13fffff (a 4 MiB window starting at +16 MiB). Address translation allows a program image to be executed in place at multiple physical flash addresses (for example, a double-buffered flash image for over-the-air updates), without the overhead of position-independent code. At reset, the address translation registers are initialised to an identity mapping, so that they can be ignored if address translation is not required. Note that the XIP cache is fully virtually addressed, so a cache flush is required after changing the address translation."] + #[doc = "Transmit FIFO for direct mode"] #[inline(always)] - pub const fn atrans4(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(68usize) as _) } + pub const fn direct_tx(self) -> crate::common::Reg { + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x04usize) as _) } } - #[doc = "Configure address translation for XIP virtual addresses 0x1400000 through 0x17fffff (a 4 MiB window starting at +20 MiB). Address translation allows a program image to be executed in place at multiple physical flash addresses (for example, a double-buffered flash image for over-the-air updates), without the overhead of position-independent code. At reset, the address translation registers are initialised to an identity mapping, so that they can be ignored if address translation is not required. Note that the XIP cache is fully virtually addressed, so a cache flush is required after changing the address translation."] + #[doc = "Receive FIFO for direct mode"] #[inline(always)] - pub const fn atrans5(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(72usize) as _) } + pub const fn direct_rx(self) -> crate::common::Reg { + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x08usize) as _) } } - #[doc = "Configure address translation for XIP virtual addresses 0x1800000 through 0x1bfffff (a 4 MiB window starting at +24 MiB). Address translation allows a program image to be executed in place at multiple physical flash addresses (for example, a double-buffered flash image for over-the-air updates), without the overhead of position-independent code. At reset, the address translation registers are initialised to an identity mapping, so that they can be ignored if address translation is not required. Note that the XIP cache is fully virtually addressed, so a cache flush is required after changing the address translation."] #[inline(always)] - pub const fn atrans6(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(76usize) as _) } + pub const fn mem(self, n: usize) -> Mem { + assert!(n < 2usize); + unsafe { Mem::from_ptr(self.ptr.add(0x0cusize + n * 20usize) as _) } } - #[doc = "Configure address translation for XIP virtual addresses 0x1c00000 through 0x1ffffff (a 4 MiB window starting at +28 MiB). Address translation allows a program image to be executed in place at multiple physical flash addresses (for example, a double-buffered flash image for over-the-air updates), without the overhead of position-independent code. At reset, the address translation registers are initialised to an identity mapping, so that they can be ignored if address translation is not required. Note that the XIP cache is fully virtually addressed, so a cache flush is required after changing the address translation."] + #[doc = "Configure address translation for XIP virtual addresses 0x000000 through 0x3fffff (a 4 MiB window starting at +0 MiB). Address translation allows a program image to be executed in place at multiple physical flash addresses (for example, a double-buffered flash image for over-the-air updates), without the overhead of position-independent code. At reset, the address translation registers are initialised to an identity mapping, so that they can be ignored if address translation is not required. Note that the XIP cache is fully virtually addressed, so a cache flush is required after changing the address translation."] #[inline(always)] - pub const fn atrans7(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(80usize) as _) } + pub const fn atrans(self, n: usize) -> crate::common::Reg { + assert!(n < 8usize); + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x34usize + n * 4usize) as _) } } } pub mod regs; diff --git a/src/rp235x/qmi/regs.rs b/src/rp235x/qmi/regs.rs index db508fe6..465fd8e3 100644 --- a/src/rp235x/qmi/regs.rs +++ b/src/rp235x/qmi/regs.rs @@ -1,212 +1,8 @@ -#[doc = "Configure address translation for XIP virtual addresses 0x000000 through 0x3fffff (a 4 MiB window starting at +0 MiB). Address translation allows a program image to be executed in place at multiple physical flash addresses (for example, a double-buffered flash image for over-the-air updates), without the overhead of position-independent code. At reset, the address translation registers are initialised to an identity mapping, so that they can be ignored if address translation is not required. Note that the XIP cache is fully virtually addressed, so a cache flush is required after changing the address translation."] -#[repr(transparent)] -#[derive(Copy, Clone, Eq, PartialEq)] -pub struct Atrans0(pub u32); -impl Atrans0 { - #[doc = "Physical address base for this virtual address range, in units of 4 kiB (one flash sector). Taking a 24-bit virtual address, firstly bits 23:22 (the two MSBs) are masked to zero, and then BASE is added to bits 23:12 (the upper 12 bits) to form the physical address. Translation wraps on a 16 MiB boundary."] - #[inline(always)] - pub const fn base(&self) -> u16 { - let val = (self.0 >> 0usize) & 0x0fff; - val as u16 - } - #[doc = "Physical address base for this virtual address range, in units of 4 kiB (one flash sector). Taking a 24-bit virtual address, firstly bits 23:22 (the two MSBs) are masked to zero, and then BASE is added to bits 23:12 (the upper 12 bits) to form the physical address. Translation wraps on a 16 MiB boundary."] - #[inline(always)] - pub fn set_base(&mut self, val: u16) { - self.0 = (self.0 & !(0x0fff << 0usize)) | (((val as u32) & 0x0fff) << 0usize); - } - #[doc = "Translation aperture size for this virtual address range, in units of 4 kiB (one flash sector). Bits 21:12 of the virtual address are compared to SIZE. Offsets greater than SIZE return a bus error, and do not cause a QSPI access."] - #[inline(always)] - pub const fn size(&self) -> u16 { - let val = (self.0 >> 16usize) & 0x07ff; - val as u16 - } - #[doc = "Translation aperture size for this virtual address range, in units of 4 kiB (one flash sector). Bits 21:12 of the virtual address are compared to SIZE. Offsets greater than SIZE return a bus error, and do not cause a QSPI access."] - #[inline(always)] - pub fn set_size(&mut self, val: u16) { - self.0 = (self.0 & !(0x07ff << 16usize)) | (((val as u32) & 0x07ff) << 16usize); - } -} -impl Default for Atrans0 { - #[inline(always)] - fn default() -> Atrans0 { - Atrans0(0) - } -} -#[doc = "Configure address translation for XIP virtual addresses 0x400000 through 0x7fffff (a 4 MiB window starting at +4 MiB). Address translation allows a program image to be executed in place at multiple physical flash addresses (for example, a double-buffered flash image for over-the-air updates), without the overhead of position-independent code. At reset, the address translation registers are initialised to an identity mapping, so that they can be ignored if address translation is not required. Note that the XIP cache is fully virtually addressed, so a cache flush is required after changing the address translation."] -#[repr(transparent)] -#[derive(Copy, Clone, Eq, PartialEq)] -pub struct Atrans1(pub u32); -impl Atrans1 { - #[doc = "Physical address base for this virtual address range, in units of 4 kiB (one flash sector). Taking a 24-bit virtual address, firstly bits 23:22 (the two MSBs) are masked to zero, and then BASE is added to bits 23:12 (the upper 12 bits) to form the physical address. Translation wraps on a 16 MiB boundary."] - #[inline(always)] - pub const fn base(&self) -> u16 { - let val = (self.0 >> 0usize) & 0x0fff; - val as u16 - } - #[doc = "Physical address base for this virtual address range, in units of 4 kiB (one flash sector). Taking a 24-bit virtual address, firstly bits 23:22 (the two MSBs) are masked to zero, and then BASE is added to bits 23:12 (the upper 12 bits) to form the physical address. Translation wraps on a 16 MiB boundary."] - #[inline(always)] - pub fn set_base(&mut self, val: u16) { - self.0 = (self.0 & !(0x0fff << 0usize)) | (((val as u32) & 0x0fff) << 0usize); - } - #[doc = "Translation aperture size for this virtual address range, in units of 4 kiB (one flash sector). Bits 21:12 of the virtual address are compared to SIZE. Offsets greater than SIZE return a bus error, and do not cause a QSPI access."] - #[inline(always)] - pub const fn size(&self) -> u16 { - let val = (self.0 >> 16usize) & 0x07ff; - val as u16 - } - #[doc = "Translation aperture size for this virtual address range, in units of 4 kiB (one flash sector). Bits 21:12 of the virtual address are compared to SIZE. Offsets greater than SIZE return a bus error, and do not cause a QSPI access."] - #[inline(always)] - pub fn set_size(&mut self, val: u16) { - self.0 = (self.0 & !(0x07ff << 16usize)) | (((val as u32) & 0x07ff) << 16usize); - } -} -impl Default for Atrans1 { - #[inline(always)] - fn default() -> Atrans1 { - Atrans1(0) - } -} -#[doc = "Configure address translation for XIP virtual addresses 0x800000 through 0xbfffff (a 4 MiB window starting at +8 MiB). Address translation allows a program image to be executed in place at multiple physical flash addresses (for example, a double-buffered flash image for over-the-air updates), without the overhead of position-independent code. At reset, the address translation registers are initialised to an identity mapping, so that they can be ignored if address translation is not required. Note that the XIP cache is fully virtually addressed, so a cache flush is required after changing the address translation."] -#[repr(transparent)] -#[derive(Copy, Clone, Eq, PartialEq)] -pub struct Atrans2(pub u32); -impl Atrans2 { - #[doc = "Physical address base for this virtual address range, in units of 4 kiB (one flash sector). Taking a 24-bit virtual address, firstly bits 23:22 (the two MSBs) are masked to zero, and then BASE is added to bits 23:12 (the upper 12 bits) to form the physical address. Translation wraps on a 16 MiB boundary."] - #[inline(always)] - pub const fn base(&self) -> u16 { - let val = (self.0 >> 0usize) & 0x0fff; - val as u16 - } - #[doc = "Physical address base for this virtual address range, in units of 4 kiB (one flash sector). Taking a 24-bit virtual address, firstly bits 23:22 (the two MSBs) are masked to zero, and then BASE is added to bits 23:12 (the upper 12 bits) to form the physical address. Translation wraps on a 16 MiB boundary."] - #[inline(always)] - pub fn set_base(&mut self, val: u16) { - self.0 = (self.0 & !(0x0fff << 0usize)) | (((val as u32) & 0x0fff) << 0usize); - } - #[doc = "Translation aperture size for this virtual address range, in units of 4 kiB (one flash sector). Bits 21:12 of the virtual address are compared to SIZE. Offsets greater than SIZE return a bus error, and do not cause a QSPI access."] - #[inline(always)] - pub const fn size(&self) -> u16 { - let val = (self.0 >> 16usize) & 0x07ff; - val as u16 - } - #[doc = "Translation aperture size for this virtual address range, in units of 4 kiB (one flash sector). Bits 21:12 of the virtual address are compared to SIZE. Offsets greater than SIZE return a bus error, and do not cause a QSPI access."] - #[inline(always)] - pub fn set_size(&mut self, val: u16) { - self.0 = (self.0 & !(0x07ff << 16usize)) | (((val as u32) & 0x07ff) << 16usize); - } -} -impl Default for Atrans2 { - #[inline(always)] - fn default() -> Atrans2 { - Atrans2(0) - } -} -#[doc = "Configure address translation for XIP virtual addresses 0xc00000 through 0xffffff (a 4 MiB window starting at +12 MiB). Address translation allows a program image to be executed in place at multiple physical flash addresses (for example, a double-buffered flash image for over-the-air updates), without the overhead of position-independent code. At reset, the address translation registers are initialised to an identity mapping, so that they can be ignored if address translation is not required. Note that the XIP cache is fully virtually addressed, so a cache flush is required after changing the address translation."] -#[repr(transparent)] -#[derive(Copy, Clone, Eq, PartialEq)] -pub struct Atrans3(pub u32); -impl Atrans3 { - #[doc = "Physical address base for this virtual address range, in units of 4 kiB (one flash sector). Taking a 24-bit virtual address, firstly bits 23:22 (the two MSBs) are masked to zero, and then BASE is added to bits 23:12 (the upper 12 bits) to form the physical address. Translation wraps on a 16 MiB boundary."] - #[inline(always)] - pub const fn base(&self) -> u16 { - let val = (self.0 >> 0usize) & 0x0fff; - val as u16 - } - #[doc = "Physical address base for this virtual address range, in units of 4 kiB (one flash sector). Taking a 24-bit virtual address, firstly bits 23:22 (the two MSBs) are masked to zero, and then BASE is added to bits 23:12 (the upper 12 bits) to form the physical address. Translation wraps on a 16 MiB boundary."] - #[inline(always)] - pub fn set_base(&mut self, val: u16) { - self.0 = (self.0 & !(0x0fff << 0usize)) | (((val as u32) & 0x0fff) << 0usize); - } - #[doc = "Translation aperture size for this virtual address range, in units of 4 kiB (one flash sector). Bits 21:12 of the virtual address are compared to SIZE. Offsets greater than SIZE return a bus error, and do not cause a QSPI access."] - #[inline(always)] - pub const fn size(&self) -> u16 { - let val = (self.0 >> 16usize) & 0x07ff; - val as u16 - } - #[doc = "Translation aperture size for this virtual address range, in units of 4 kiB (one flash sector). Bits 21:12 of the virtual address are compared to SIZE. Offsets greater than SIZE return a bus error, and do not cause a QSPI access."] - #[inline(always)] - pub fn set_size(&mut self, val: u16) { - self.0 = (self.0 & !(0x07ff << 16usize)) | (((val as u32) & 0x07ff) << 16usize); - } -} -impl Default for Atrans3 { - #[inline(always)] - fn default() -> Atrans3 { - Atrans3(0) - } -} #[doc = "Configure address translation for XIP virtual addresses 0x1000000 through 0x13fffff (a 4 MiB window starting at +16 MiB). Address translation allows a program image to be executed in place at multiple physical flash addresses (for example, a double-buffered flash image for over-the-air updates), without the overhead of position-independent code. At reset, the address translation registers are initialised to an identity mapping, so that they can be ignored if address translation is not required. Note that the XIP cache is fully virtually addressed, so a cache flush is required after changing the address translation."] #[repr(transparent)] #[derive(Copy, Clone, Eq, PartialEq)] -pub struct Atrans4(pub u32); -impl Atrans4 { - #[doc = "Physical address base for this virtual address range, in units of 4 kiB (one flash sector). Taking a 24-bit virtual address, firstly bits 23:22 (the two MSBs) are masked to zero, and then BASE is added to bits 23:12 (the upper 12 bits) to form the physical address. Translation wraps on a 16 MiB boundary."] - #[inline(always)] - pub const fn base(&self) -> u16 { - let val = (self.0 >> 0usize) & 0x0fff; - val as u16 - } - #[doc = "Physical address base for this virtual address range, in units of 4 kiB (one flash sector). Taking a 24-bit virtual address, firstly bits 23:22 (the two MSBs) are masked to zero, and then BASE is added to bits 23:12 (the upper 12 bits) to form the physical address. Translation wraps on a 16 MiB boundary."] - #[inline(always)] - pub fn set_base(&mut self, val: u16) { - self.0 = (self.0 & !(0x0fff << 0usize)) | (((val as u32) & 0x0fff) << 0usize); - } - #[doc = "Translation aperture size for this virtual address range, in units of 4 kiB (one flash sector). Bits 21:12 of the virtual address are compared to SIZE. Offsets greater than SIZE return a bus error, and do not cause a QSPI access."] - #[inline(always)] - pub const fn size(&self) -> u16 { - let val = (self.0 >> 16usize) & 0x07ff; - val as u16 - } - #[doc = "Translation aperture size for this virtual address range, in units of 4 kiB (one flash sector). Bits 21:12 of the virtual address are compared to SIZE. Offsets greater than SIZE return a bus error, and do not cause a QSPI access."] - #[inline(always)] - pub fn set_size(&mut self, val: u16) { - self.0 = (self.0 & !(0x07ff << 16usize)) | (((val as u32) & 0x07ff) << 16usize); - } -} -impl Default for Atrans4 { - #[inline(always)] - fn default() -> Atrans4 { - Atrans4(0) - } -} -#[doc = "Configure address translation for XIP virtual addresses 0x1400000 through 0x17fffff (a 4 MiB window starting at +20 MiB). Address translation allows a program image to be executed in place at multiple physical flash addresses (for example, a double-buffered flash image for over-the-air updates), without the overhead of position-independent code. At reset, the address translation registers are initialised to an identity mapping, so that they can be ignored if address translation is not required. Note that the XIP cache is fully virtually addressed, so a cache flush is required after changing the address translation."] -#[repr(transparent)] -#[derive(Copy, Clone, Eq, PartialEq)] -pub struct Atrans5(pub u32); -impl Atrans5 { - #[doc = "Physical address base for this virtual address range, in units of 4 kiB (one flash sector). Taking a 24-bit virtual address, firstly bits 23:22 (the two MSBs) are masked to zero, and then BASE is added to bits 23:12 (the upper 12 bits) to form the physical address. Translation wraps on a 16 MiB boundary."] - #[inline(always)] - pub const fn base(&self) -> u16 { - let val = (self.0 >> 0usize) & 0x0fff; - val as u16 - } - #[doc = "Physical address base for this virtual address range, in units of 4 kiB (one flash sector). Taking a 24-bit virtual address, firstly bits 23:22 (the two MSBs) are masked to zero, and then BASE is added to bits 23:12 (the upper 12 bits) to form the physical address. Translation wraps on a 16 MiB boundary."] - #[inline(always)] - pub fn set_base(&mut self, val: u16) { - self.0 = (self.0 & !(0x0fff << 0usize)) | (((val as u32) & 0x0fff) << 0usize); - } - #[doc = "Translation aperture size for this virtual address range, in units of 4 kiB (one flash sector). Bits 21:12 of the virtual address are compared to SIZE. Offsets greater than SIZE return a bus error, and do not cause a QSPI access."] - #[inline(always)] - pub const fn size(&self) -> u16 { - let val = (self.0 >> 16usize) & 0x07ff; - val as u16 - } - #[doc = "Translation aperture size for this virtual address range, in units of 4 kiB (one flash sector). Bits 21:12 of the virtual address are compared to SIZE. Offsets greater than SIZE return a bus error, and do not cause a QSPI access."] - #[inline(always)] - pub fn set_size(&mut self, val: u16) { - self.0 = (self.0 & !(0x07ff << 16usize)) | (((val as u32) & 0x07ff) << 16usize); - } -} -impl Default for Atrans5 { - #[inline(always)] - fn default() -> Atrans5 { - Atrans5(0) - } -} -#[doc = "Configure address translation for XIP virtual addresses 0x1800000 through 0x1bfffff (a 4 MiB window starting at +24 MiB). Address translation allows a program image to be executed in place at multiple physical flash addresses (for example, a double-buffered flash image for over-the-air updates), without the overhead of position-independent code. At reset, the address translation registers are initialised to an identity mapping, so that they can be ignored if address translation is not required. Note that the XIP cache is fully virtually addressed, so a cache flush is required after changing the address translation."] -#[repr(transparent)] -#[derive(Copy, Clone, Eq, PartialEq)] -pub struct Atrans6(pub u32); -impl Atrans6 { +pub struct Atrans(pub u32); +impl Atrans { #[doc = "Physical address base for this virtual address range, in units of 4 kiB (one flash sector). Taking a 24-bit virtual address, firstly bits 23:22 (the two MSBs) are masked to zero, and then BASE is added to bits 23:12 (the upper 12 bits) to form the physical address. Translation wraps on a 16 MiB boundary."] #[inline(always)] pub const fn base(&self) -> u16 { @@ -230,44 +26,10 @@ impl Atrans6 { self.0 = (self.0 & !(0x07ff << 16usize)) | (((val as u32) & 0x07ff) << 16usize); } } -impl Default for Atrans6 { +impl Default for Atrans { #[inline(always)] - fn default() -> Atrans6 { - Atrans6(0) - } -} -#[doc = "Configure address translation for XIP virtual addresses 0x1c00000 through 0x1ffffff (a 4 MiB window starting at +28 MiB). Address translation allows a program image to be executed in place at multiple physical flash addresses (for example, a double-buffered flash image for over-the-air updates), without the overhead of position-independent code. At reset, the address translation registers are initialised to an identity mapping, so that they can be ignored if address translation is not required. Note that the XIP cache is fully virtually addressed, so a cache flush is required after changing the address translation."] -#[repr(transparent)] -#[derive(Copy, Clone, Eq, PartialEq)] -pub struct Atrans7(pub u32); -impl Atrans7 { - #[doc = "Physical address base for this virtual address range, in units of 4 kiB (one flash sector). Taking a 24-bit virtual address, firstly bits 23:22 (the two MSBs) are masked to zero, and then BASE is added to bits 23:12 (the upper 12 bits) to form the physical address. Translation wraps on a 16 MiB boundary."] - #[inline(always)] - pub const fn base(&self) -> u16 { - let val = (self.0 >> 0usize) & 0x0fff; - val as u16 - } - #[doc = "Physical address base for this virtual address range, in units of 4 kiB (one flash sector). Taking a 24-bit virtual address, firstly bits 23:22 (the two MSBs) are masked to zero, and then BASE is added to bits 23:12 (the upper 12 bits) to form the physical address. Translation wraps on a 16 MiB boundary."] - #[inline(always)] - pub fn set_base(&mut self, val: u16) { - self.0 = (self.0 & !(0x0fff << 0usize)) | (((val as u32) & 0x0fff) << 0usize); - } - #[doc = "Translation aperture size for this virtual address range, in units of 4 kiB (one flash sector). Bits 21:12 of the virtual address are compared to SIZE. Offsets greater than SIZE return a bus error, and do not cause a QSPI access."] - #[inline(always)] - pub const fn size(&self) -> u16 { - let val = (self.0 >> 16usize) & 0x07ff; - val as u16 - } - #[doc = "Translation aperture size for this virtual address range, in units of 4 kiB (one flash sector). Bits 21:12 of the virtual address are compared to SIZE. Offsets greater than SIZE return a bus error, and do not cause a QSPI access."] - #[inline(always)] - pub fn set_size(&mut self, val: u16) { - self.0 = (self.0 & !(0x07ff << 16usize)) | (((val as u32) & 0x07ff) << 16usize); - } -} -impl Default for Atrans7 { - #[inline(always)] - fn default() -> Atrans7 { - Atrans7(0) + fn default() -> Atrans { + Atrans(0) } } #[doc = "Control and status for direct serial mode Direct serial mode allows the processor to send and receive raw serial frames, for programming, configuration and control of the external memory devices. Only SPI mode 0 (CPOL=0 CPHA=0) is supported."] @@ -526,401 +288,11 @@ impl Default for DirectTx { DirectTx(0) } } -#[doc = "Command constants used for reads from memory address window 0. The reset value of the M0_RCMD register is configured to support a basic 03h serial read transfer with no additional configuration."] -#[repr(transparent)] -#[derive(Copy, Clone, Eq, PartialEq)] -pub struct M0rcmd(pub u32); -impl M0rcmd { - #[doc = "The command prefix bits to prepend on each new transfer, if Mx_RFMT_PREFIX_LEN is nonzero."] - #[inline(always)] - pub const fn prefix(&self) -> u8 { - let val = (self.0 >> 0usize) & 0xff; - val as u8 - } - #[doc = "The command prefix bits to prepend on each new transfer, if Mx_RFMT_PREFIX_LEN is nonzero."] - #[inline(always)] - pub fn set_prefix(&mut self, val: u8) { - self.0 = (self.0 & !(0xff << 0usize)) | (((val as u32) & 0xff) << 0usize); - } - #[doc = "The command suffix bits following the address, if Mx_RFMT_SUFFIX_LEN is nonzero."] - #[inline(always)] - pub const fn suffix(&self) -> u8 { - let val = (self.0 >> 8usize) & 0xff; - val as u8 - } - #[doc = "The command suffix bits following the address, if Mx_RFMT_SUFFIX_LEN is nonzero."] - #[inline(always)] - pub fn set_suffix(&mut self, val: u8) { - self.0 = (self.0 & !(0xff << 8usize)) | (((val as u32) & 0xff) << 8usize); - } -} -impl Default for M0rcmd { - #[inline(always)] - fn default() -> M0rcmd { - M0rcmd(0) - } -} -#[doc = "Read transfer format configuration for memory address window 0. Configure the bus width of each transfer phase individually, and configure the length or presence of the command prefix, command suffix and dummy/turnaround transfer phases. Only 24-bit addresses are supported. The reset value of the M0_RFMT register is configured to support a basic 03h serial read transfer with no additional configuration."] -#[repr(transparent)] -#[derive(Copy, Clone, Eq, PartialEq)] -pub struct M0rfmt(pub u32); -impl M0rfmt { - #[doc = "The transfer width used for the command prefix, if any"] - #[inline(always)] - pub const fn prefix_width(&self) -> super::vals::M0rfmtPrefixWidth { - let val = (self.0 >> 0usize) & 0x03; - super::vals::M0rfmtPrefixWidth::from_bits(val as u8) - } - #[doc = "The transfer width used for the command prefix, if any"] - #[inline(always)] - pub fn set_prefix_width(&mut self, val: super::vals::M0rfmtPrefixWidth) { - self.0 = (self.0 & !(0x03 << 0usize)) | (((val.to_bits() as u32) & 0x03) << 0usize); - } - #[doc = "The transfer width used for the address. The address phase always transfers 24 bits in total."] - #[inline(always)] - pub const fn addr_width(&self) -> super::vals::M0rfmtAddrWidth { - let val = (self.0 >> 2usize) & 0x03; - super::vals::M0rfmtAddrWidth::from_bits(val as u8) - } - #[doc = "The transfer width used for the address. The address phase always transfers 24 bits in total."] - #[inline(always)] - pub fn set_addr_width(&mut self, val: super::vals::M0rfmtAddrWidth) { - self.0 = (self.0 & !(0x03 << 2usize)) | (((val.to_bits() as u32) & 0x03) << 2usize); - } - #[doc = "The width used for the post-address command suffix, if any"] - #[inline(always)] - pub const fn suffix_width(&self) -> super::vals::M0rfmtSuffixWidth { - let val = (self.0 >> 4usize) & 0x03; - super::vals::M0rfmtSuffixWidth::from_bits(val as u8) - } - #[doc = "The width used for the post-address command suffix, if any"] - #[inline(always)] - pub fn set_suffix_width(&mut self, val: super::vals::M0rfmtSuffixWidth) { - self.0 = (self.0 & !(0x03 << 4usize)) | (((val.to_bits() as u32) & 0x03) << 4usize); - } - #[doc = "The width used for the dummy phase, if any. If width is single, SD0/MOSI is held asserted low during the dummy phase, and SD1...SD3 are tristated. If width is dual/quad, all IOs are tristated during the dummy phase."] - #[inline(always)] - pub const fn dummy_width(&self) -> super::vals::M0rfmtDummyWidth { - let val = (self.0 >> 6usize) & 0x03; - super::vals::M0rfmtDummyWidth::from_bits(val as u8) - } - #[doc = "The width used for the dummy phase, if any. If width is single, SD0/MOSI is held asserted low during the dummy phase, and SD1...SD3 are tristated. If width is dual/quad, all IOs are tristated during the dummy phase."] - #[inline(always)] - pub fn set_dummy_width(&mut self, val: super::vals::M0rfmtDummyWidth) { - self.0 = (self.0 & !(0x03 << 6usize)) | (((val.to_bits() as u32) & 0x03) << 6usize); - } - #[doc = "The width used for the data transfer"] - #[inline(always)] - pub const fn data_width(&self) -> super::vals::M0rfmtDataWidth { - let val = (self.0 >> 8usize) & 0x03; - super::vals::M0rfmtDataWidth::from_bits(val as u8) - } - #[doc = "The width used for the data transfer"] - #[inline(always)] - pub fn set_data_width(&mut self, val: super::vals::M0rfmtDataWidth) { - self.0 = (self.0 & !(0x03 << 8usize)) | (((val.to_bits() as u32) & 0x03) << 8usize); - } - #[doc = "Length of command prefix, in units of 8 bits. (i.e. 2 cycles for quad width, 4 for dual, 8 for single)"] - #[inline(always)] - pub const fn prefix_len(&self) -> super::vals::M0rfmtPrefixLen { - let val = (self.0 >> 12usize) & 0x01; - super::vals::M0rfmtPrefixLen::from_bits(val as u8) - } - #[doc = "Length of command prefix, in units of 8 bits. (i.e. 2 cycles for quad width, 4 for dual, 8 for single)"] - #[inline(always)] - pub fn set_prefix_len(&mut self, val: super::vals::M0rfmtPrefixLen) { - self.0 = (self.0 & !(0x01 << 12usize)) | (((val.to_bits() as u32) & 0x01) << 12usize); - } - #[doc = "Length of post-address command suffix, in units of 4 bits. (i.e. 1 cycle for quad width, 2 for dual, 4 for single) Only values of 0 and 8 bits are supported."] - #[inline(always)] - pub const fn suffix_len(&self) -> super::vals::M0rfmtSuffixLen { - let val = (self.0 >> 14usize) & 0x03; - super::vals::M0rfmtSuffixLen::from_bits(val as u8) - } - #[doc = "Length of post-address command suffix, in units of 4 bits. (i.e. 1 cycle for quad width, 2 for dual, 4 for single) Only values of 0 and 8 bits are supported."] - #[inline(always)] - pub fn set_suffix_len(&mut self, val: super::vals::M0rfmtSuffixLen) { - self.0 = (self.0 & !(0x03 << 14usize)) | (((val.to_bits() as u32) & 0x03) << 14usize); - } - #[doc = "Length of dummy phase between command suffix and data phase, in units of 4 bits. (i.e. 1 cycle for quad width, 2 for dual, 4 for single)"] - #[inline(always)] - pub const fn dummy_len(&self) -> super::vals::M0rfmtDummyLen { - let val = (self.0 >> 16usize) & 0x07; - super::vals::M0rfmtDummyLen::from_bits(val as u8) - } - #[doc = "Length of dummy phase between command suffix and data phase, in units of 4 bits. (i.e. 1 cycle for quad width, 2 for dual, 4 for single)"] - #[inline(always)] - pub fn set_dummy_len(&mut self, val: super::vals::M0rfmtDummyLen) { - self.0 = (self.0 & !(0x07 << 16usize)) | (((val.to_bits() as u32) & 0x07) << 16usize); - } - #[doc = "Enable double transfer rate (DTR) for read commands: address, suffix and read data phases are active on both edges of SCK. SDO data is launched centre-aligned on each SCK edge, and SDI data is captured on the SCK edge that follows its launch. DTR is implemented by halving the clock rate; SCK has a period of 2 x CLK_DIV throughout the transfer. The prefix and dummy phases are still single transfer rate. If the suffix is quad-width, it must be 0 or 8 bits in length, to ensure an even number of SCK edges."] - #[inline(always)] - pub const fn dtr(&self) -> bool { - let val = (self.0 >> 28usize) & 0x01; - val != 0 - } - #[doc = "Enable double transfer rate (DTR) for read commands: address, suffix and read data phases are active on both edges of SCK. SDO data is launched centre-aligned on each SCK edge, and SDI data is captured on the SCK edge that follows its launch. DTR is implemented by halving the clock rate; SCK has a period of 2 x CLK_DIV throughout the transfer. The prefix and dummy phases are still single transfer rate. If the suffix is quad-width, it must be 0 or 8 bits in length, to ensure an even number of SCK edges."] - #[inline(always)] - pub fn set_dtr(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 28usize)) | (((val as u32) & 0x01) << 28usize); - } -} -impl Default for M0rfmt { - #[inline(always)] - fn default() -> M0rfmt { - M0rfmt(0) - } -} -#[doc = "Timing configuration register for memory address window 0."] -#[repr(transparent)] -#[derive(Copy, Clone, Eq, PartialEq)] -pub struct M0timing(pub u32); -impl M0timing { - #[doc = "Clock divisor. Odd and even divisors are supported. Defines the SCK clock period in units of 1 system clock cycle. Divisors 1..255 are encoded directly, and a divisor of 256 is encoded with a value of CLKDIV=0. The clock divisor can be changed on-the-fly, even when the QMI is currently accessing memory in this address window. All other parameters must only be changed when the QMI is idle. If software is increasing CLKDIV in anticipation of an increase in the system clock frequency, a dummy access to either memory window (and appropriate processor barriers/fences) must be inserted after the Mx_TIMING write to ensure the SCK divisor change is in effect _before_ the system clock is changed."] - #[inline(always)] - pub const fn clkdiv(&self) -> u8 { - let val = (self.0 >> 0usize) & 0xff; - val as u8 - } - #[doc = "Clock divisor. Odd and even divisors are supported. Defines the SCK clock period in units of 1 system clock cycle. Divisors 1..255 are encoded directly, and a divisor of 256 is encoded with a value of CLKDIV=0. The clock divisor can be changed on-the-fly, even when the QMI is currently accessing memory in this address window. All other parameters must only be changed when the QMI is idle. If software is increasing CLKDIV in anticipation of an increase in the system clock frequency, a dummy access to either memory window (and appropriate processor barriers/fences) must be inserted after the Mx_TIMING write to ensure the SCK divisor change is in effect _before_ the system clock is changed."] - #[inline(always)] - pub fn set_clkdiv(&mut self, val: u8) { - self.0 = (self.0 & !(0xff << 0usize)) | (((val as u32) & 0xff) << 0usize); - } - #[doc = "Delay the read data sample timing, in units of one half of a system clock cycle. (Not necessarily half of an SCK cycle.) An RXDELAY of 0 means the sample is captured at the SDI input registers simultaneously with the rising edge of SCK launched from the SCK output register. At higher SCK frequencies, RXDELAY may need to be increased to account for the round trip delay of the pads, and the clock-to-Q delay of the QSPI memory device."] - #[inline(always)] - pub const fn rxdelay(&self) -> u8 { - let val = (self.0 >> 8usize) & 0x07; - val as u8 - } - #[doc = "Delay the read data sample timing, in units of one half of a system clock cycle. (Not necessarily half of an SCK cycle.) An RXDELAY of 0 means the sample is captured at the SDI input registers simultaneously with the rising edge of SCK launched from the SCK output register. At higher SCK frequencies, RXDELAY may need to be increased to account for the round trip delay of the pads, and the clock-to-Q delay of the QSPI memory device."] - #[inline(always)] - pub fn set_rxdelay(&mut self, val: u8) { - self.0 = (self.0 & !(0x07 << 8usize)) | (((val as u32) & 0x07) << 8usize); - } - #[doc = "After this window's chip select is deasserted, it remains deasserted for half an SCK cycle (rounded up to an integer number of system clock cycles), plus MIN_DESELECT additional system clock cycles, before the QMI reasserts either chip select pin. Nonzero values may be required for PSRAM devices which enforce a longer minimum CS deselect time, so that they can perform internal DRAM refresh cycles whilst deselected."] - #[inline(always)] - pub const fn min_deselect(&self) -> u8 { - let val = (self.0 >> 12usize) & 0x1f; - val as u8 - } - #[doc = "After this window's chip select is deasserted, it remains deasserted for half an SCK cycle (rounded up to an integer number of system clock cycles), plus MIN_DESELECT additional system clock cycles, before the QMI reasserts either chip select pin. Nonzero values may be required for PSRAM devices which enforce a longer minimum CS deselect time, so that they can perform internal DRAM refresh cycles whilst deselected."] - #[inline(always)] - pub fn set_min_deselect(&mut self, val: u8) { - self.0 = (self.0 & !(0x1f << 12usize)) | (((val as u32) & 0x1f) << 12usize); - } - #[doc = "Enforce a maximum assertion duration for this window's chip select, in units of 64 system clock cycles. If 0, the QMI is permitted to keep the chip select asserted indefinitely when servicing sequential memory accesses (see COOLDOWN). This feature is required to meet timing constraints of PSRAM devices, which specify a maximum chip select assertion so they can perform DRAM refresh cycles. See also MIN_DESELECT, which can enforce a minimum deselect time. If a memory access is in progress at the time MAX_SELECT is reached, the QMI will wait for the access to complete before deasserting the chip select. This additional time must be accounted for to calculate a safe MAX_SELECT value. In the worst case, this may be a fully-formed serial transfer, including command prefix and address, with a data payload as large as one cache line."] - #[inline(always)] - pub const fn max_select(&self) -> u8 { - let val = (self.0 >> 17usize) & 0x3f; - val as u8 - } - #[doc = "Enforce a maximum assertion duration for this window's chip select, in units of 64 system clock cycles. If 0, the QMI is permitted to keep the chip select asserted indefinitely when servicing sequential memory accesses (see COOLDOWN). This feature is required to meet timing constraints of PSRAM devices, which specify a maximum chip select assertion so they can perform DRAM refresh cycles. See also MIN_DESELECT, which can enforce a minimum deselect time. If a memory access is in progress at the time MAX_SELECT is reached, the QMI will wait for the access to complete before deasserting the chip select. This additional time must be accounted for to calculate a safe MAX_SELECT value. In the worst case, this may be a fully-formed serial transfer, including command prefix and address, with a data payload as large as one cache line."] - #[inline(always)] - pub fn set_max_select(&mut self, val: u8) { - self.0 = (self.0 & !(0x3f << 17usize)) | (((val as u32) & 0x3f) << 17usize); - } - #[doc = "Add up to three additional system clock cycles of active hold between the last falling edge of SCK and the deassertion of this window's chip select. The default hold time is one system clock cycle. Note that flash datasheets usually give chip select active hold time from the last *rising* edge of SCK, and so even zero hold from the last falling edge would be safe. Note that this is a minimum hold time guaranteed by the QMI: the actual chip select active hold may be slightly longer for read transfers with low clock divisors and/or high sample delays. Specifically, if the point two cycles after the last RX data sample is later than the last SCK falling edge, then the hold time is measured from *this* point. Note also that, in case the final SCK pulse is masked to save energy (true for non-DTR reads when COOLDOWN is disabled or PAGE_BREAK is reached), all of QMI's timing logic behaves as though the clock pulse were still present. The SELECT_HOLD time is applied from the point where the last SCK falling edge would be if the clock pulse were not masked."] - #[inline(always)] - pub const fn select_hold(&self) -> u8 { - let val = (self.0 >> 23usize) & 0x03; - val as u8 - } - #[doc = "Add up to three additional system clock cycles of active hold between the last falling edge of SCK and the deassertion of this window's chip select. The default hold time is one system clock cycle. Note that flash datasheets usually give chip select active hold time from the last *rising* edge of SCK, and so even zero hold from the last falling edge would be safe. Note that this is a minimum hold time guaranteed by the QMI: the actual chip select active hold may be slightly longer for read transfers with low clock divisors and/or high sample delays. Specifically, if the point two cycles after the last RX data sample is later than the last SCK falling edge, then the hold time is measured from *this* point. Note also that, in case the final SCK pulse is masked to save energy (true for non-DTR reads when COOLDOWN is disabled or PAGE_BREAK is reached), all of QMI's timing logic behaves as though the clock pulse were still present. The SELECT_HOLD time is applied from the point where the last SCK falling edge would be if the clock pulse were not masked."] - #[inline(always)] - pub fn set_select_hold(&mut self, val: u8) { - self.0 = (self.0 & !(0x03 << 23usize)) | (((val as u32) & 0x03) << 23usize); - } - #[doc = "Add up to one additional system clock cycle of setup between chip select assertion and the first rising edge of SCK. The default setup time is one half SCK period, which is usually sufficient except for very high SCK frequencies with some flash devices."] - #[inline(always)] - pub const fn select_setup(&self) -> bool { - let val = (self.0 >> 25usize) & 0x01; - val != 0 - } - #[doc = "Add up to one additional system clock cycle of setup between chip select assertion and the first rising edge of SCK. The default setup time is one half SCK period, which is usually sufficient except for very high SCK frequencies with some flash devices."] - #[inline(always)] - pub fn set_select_setup(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 25usize)) | (((val as u32) & 0x01) << 25usize); - } - #[doc = "When page break is enabled, chip select will automatically deassert when crossing certain power-of-2-aligned address boundaries. The next access will always begin a new read/write SPI burst, even if the address of the next access follows in sequence with the last access before the page boundary. Some flash and PSRAM devices forbid crossing page boundaries with a single read/write transfer, or restrict the operating frequency for transfers that do cross page a boundary. This option allows the QMI to safely support those devices. This field has no effect when COOLDOWN is disabled."] - #[inline(always)] - pub const fn pagebreak(&self) -> super::vals::M0timingPagebreak { - let val = (self.0 >> 28usize) & 0x03; - super::vals::M0timingPagebreak::from_bits(val as u8) - } - #[doc = "When page break is enabled, chip select will automatically deassert when crossing certain power-of-2-aligned address boundaries. The next access will always begin a new read/write SPI burst, even if the address of the next access follows in sequence with the last access before the page boundary. Some flash and PSRAM devices forbid crossing page boundaries with a single read/write transfer, or restrict the operating frequency for transfers that do cross page a boundary. This option allows the QMI to safely support those devices. This field has no effect when COOLDOWN is disabled."] - #[inline(always)] - pub fn set_pagebreak(&mut self, val: super::vals::M0timingPagebreak) { - self.0 = (self.0 & !(0x03 << 28usize)) | (((val.to_bits() as u32) & 0x03) << 28usize); - } - #[doc = "Chip select cooldown period. When a memory transfer finishes, the chip select remains asserted for 64 x COOLDOWN system clock cycles, plus half an SCK clock period (rounded up for odd SCK divisors). After this cooldown expires, the chip select is always deasserted to save power. If the next memory access arrives within the cooldown period, the QMI may be able to append more SCK cycles to the currently ongoing SPI transfer, rather than starting a new transfer. This reduces access latency and increases bus throughput. Specifically, the next access must be in the same direction (read/write), access the same memory window (chip select 0/1), and follow sequentially the address of the last transfer. If any of these are false, the new access will first deassert the chip select, then begin a new transfer. If COOLDOWN is 0, the address alignment configured by PAGEBREAK has been reached, or the total chip select assertion limit MAX_SELECT has been reached, the cooldown period is skipped, and the chip select will always be deasserted one half SCK period after the transfer finishes."] - #[inline(always)] - pub const fn cooldown(&self) -> u8 { - let val = (self.0 >> 30usize) & 0x03; - val as u8 - } - #[doc = "Chip select cooldown period. When a memory transfer finishes, the chip select remains asserted for 64 x COOLDOWN system clock cycles, plus half an SCK clock period (rounded up for odd SCK divisors). After this cooldown expires, the chip select is always deasserted to save power. If the next memory access arrives within the cooldown period, the QMI may be able to append more SCK cycles to the currently ongoing SPI transfer, rather than starting a new transfer. This reduces access latency and increases bus throughput. Specifically, the next access must be in the same direction (read/write), access the same memory window (chip select 0/1), and follow sequentially the address of the last transfer. If any of these are false, the new access will first deassert the chip select, then begin a new transfer. If COOLDOWN is 0, the address alignment configured by PAGEBREAK has been reached, or the total chip select assertion limit MAX_SELECT has been reached, the cooldown period is skipped, and the chip select will always be deasserted one half SCK period after the transfer finishes."] - #[inline(always)] - pub fn set_cooldown(&mut self, val: u8) { - self.0 = (self.0 & !(0x03 << 30usize)) | (((val as u32) & 0x03) << 30usize); - } -} -impl Default for M0timing { - #[inline(always)] - fn default() -> M0timing { - M0timing(0) - } -} -#[doc = "Command constants used for writes to memory address window 0. The reset value of the M0_WCMD register is configured to support a basic 02h serial write transfer with no additional configuration."] -#[repr(transparent)] -#[derive(Copy, Clone, Eq, PartialEq)] -pub struct M0wcmd(pub u32); -impl M0wcmd { - #[doc = "The command prefix bits to prepend on each new transfer, if Mx_WFMT_PREFIX_LEN is nonzero."] - #[inline(always)] - pub const fn prefix(&self) -> u8 { - let val = (self.0 >> 0usize) & 0xff; - val as u8 - } - #[doc = "The command prefix bits to prepend on each new transfer, if Mx_WFMT_PREFIX_LEN is nonzero."] - #[inline(always)] - pub fn set_prefix(&mut self, val: u8) { - self.0 = (self.0 & !(0xff << 0usize)) | (((val as u32) & 0xff) << 0usize); - } - #[doc = "The command suffix bits following the address, if Mx_WFMT_SUFFIX_LEN is nonzero."] - #[inline(always)] - pub const fn suffix(&self) -> u8 { - let val = (self.0 >> 8usize) & 0xff; - val as u8 - } - #[doc = "The command suffix bits following the address, if Mx_WFMT_SUFFIX_LEN is nonzero."] - #[inline(always)] - pub fn set_suffix(&mut self, val: u8) { - self.0 = (self.0 & !(0xff << 8usize)) | (((val as u32) & 0xff) << 8usize); - } -} -impl Default for M0wcmd { - #[inline(always)] - fn default() -> M0wcmd { - M0wcmd(0) - } -} -#[doc = "Write transfer format configuration for memory address window 0. Configure the bus width of each transfer phase individually, and configure the length or presence of the command prefix, command suffix and dummy/turnaround transfer phases. Only 24-bit addresses are supported. The reset value of the M0_WFMT register is configured to support a basic 02h serial write transfer. However, writes to this window must first be enabled via the XIP_CTRL_WRITABLE_M0 bit, as XIP memory is read-only by default."] -#[repr(transparent)] -#[derive(Copy, Clone, Eq, PartialEq)] -pub struct M0wfmt(pub u32); -impl M0wfmt { - #[doc = "The transfer width used for the command prefix, if any"] - #[inline(always)] - pub const fn prefix_width(&self) -> super::vals::M0wfmtPrefixWidth { - let val = (self.0 >> 0usize) & 0x03; - super::vals::M0wfmtPrefixWidth::from_bits(val as u8) - } - #[doc = "The transfer width used for the command prefix, if any"] - #[inline(always)] - pub fn set_prefix_width(&mut self, val: super::vals::M0wfmtPrefixWidth) { - self.0 = (self.0 & !(0x03 << 0usize)) | (((val.to_bits() as u32) & 0x03) << 0usize); - } - #[doc = "The transfer width used for the address. The address phase always transfers 24 bits in total."] - #[inline(always)] - pub const fn addr_width(&self) -> super::vals::M0wfmtAddrWidth { - let val = (self.0 >> 2usize) & 0x03; - super::vals::M0wfmtAddrWidth::from_bits(val as u8) - } - #[doc = "The transfer width used for the address. The address phase always transfers 24 bits in total."] - #[inline(always)] - pub fn set_addr_width(&mut self, val: super::vals::M0wfmtAddrWidth) { - self.0 = (self.0 & !(0x03 << 2usize)) | (((val.to_bits() as u32) & 0x03) << 2usize); - } - #[doc = "The width used for the post-address command suffix, if any"] - #[inline(always)] - pub const fn suffix_width(&self) -> super::vals::M0wfmtSuffixWidth { - let val = (self.0 >> 4usize) & 0x03; - super::vals::M0wfmtSuffixWidth::from_bits(val as u8) - } - #[doc = "The width used for the post-address command suffix, if any"] - #[inline(always)] - pub fn set_suffix_width(&mut self, val: super::vals::M0wfmtSuffixWidth) { - self.0 = (self.0 & !(0x03 << 4usize)) | (((val.to_bits() as u32) & 0x03) << 4usize); - } - #[doc = "The width used for the dummy phase, if any. If width is single, SD0/MOSI is held asserted low during the dummy phase, and SD1...SD3 are tristated. If width is dual/quad, all IOs are tristated during the dummy phase."] - #[inline(always)] - pub const fn dummy_width(&self) -> super::vals::M0wfmtDummyWidth { - let val = (self.0 >> 6usize) & 0x03; - super::vals::M0wfmtDummyWidth::from_bits(val as u8) - } - #[doc = "The width used for the dummy phase, if any. If width is single, SD0/MOSI is held asserted low during the dummy phase, and SD1...SD3 are tristated. If width is dual/quad, all IOs are tristated during the dummy phase."] - #[inline(always)] - pub fn set_dummy_width(&mut self, val: super::vals::M0wfmtDummyWidth) { - self.0 = (self.0 & !(0x03 << 6usize)) | (((val.to_bits() as u32) & 0x03) << 6usize); - } - #[doc = "The width used for the data transfer"] - #[inline(always)] - pub const fn data_width(&self) -> super::vals::M0wfmtDataWidth { - let val = (self.0 >> 8usize) & 0x03; - super::vals::M0wfmtDataWidth::from_bits(val as u8) - } - #[doc = "The width used for the data transfer"] - #[inline(always)] - pub fn set_data_width(&mut self, val: super::vals::M0wfmtDataWidth) { - self.0 = (self.0 & !(0x03 << 8usize)) | (((val.to_bits() as u32) & 0x03) << 8usize); - } - #[doc = "Length of command prefix, in units of 8 bits. (i.e. 2 cycles for quad width, 4 for dual, 8 for single)"] - #[inline(always)] - pub const fn prefix_len(&self) -> super::vals::M0wfmtPrefixLen { - let val = (self.0 >> 12usize) & 0x01; - super::vals::M0wfmtPrefixLen::from_bits(val as u8) - } - #[doc = "Length of command prefix, in units of 8 bits. (i.e. 2 cycles for quad width, 4 for dual, 8 for single)"] - #[inline(always)] - pub fn set_prefix_len(&mut self, val: super::vals::M0wfmtPrefixLen) { - self.0 = (self.0 & !(0x01 << 12usize)) | (((val.to_bits() as u32) & 0x01) << 12usize); - } - #[doc = "Length of post-address command suffix, in units of 4 bits. (i.e. 1 cycle for quad width, 2 for dual, 4 for single) Only values of 0 and 8 bits are supported."] - #[inline(always)] - pub const fn suffix_len(&self) -> super::vals::M0wfmtSuffixLen { - let val = (self.0 >> 14usize) & 0x03; - super::vals::M0wfmtSuffixLen::from_bits(val as u8) - } - #[doc = "Length of post-address command suffix, in units of 4 bits. (i.e. 1 cycle for quad width, 2 for dual, 4 for single) Only values of 0 and 8 bits are supported."] - #[inline(always)] - pub fn set_suffix_len(&mut self, val: super::vals::M0wfmtSuffixLen) { - self.0 = (self.0 & !(0x03 << 14usize)) | (((val.to_bits() as u32) & 0x03) << 14usize); - } - #[doc = "Length of dummy phase between command suffix and data phase, in units of 4 bits. (i.e. 1 cycle for quad width, 2 for dual, 4 for single)"] - #[inline(always)] - pub const fn dummy_len(&self) -> super::vals::M0wfmtDummyLen { - let val = (self.0 >> 16usize) & 0x07; - super::vals::M0wfmtDummyLen::from_bits(val as u8) - } - #[doc = "Length of dummy phase between command suffix and data phase, in units of 4 bits. (i.e. 1 cycle for quad width, 2 for dual, 4 for single)"] - #[inline(always)] - pub fn set_dummy_len(&mut self, val: super::vals::M0wfmtDummyLen) { - self.0 = (self.0 & !(0x07 << 16usize)) | (((val.to_bits() as u32) & 0x07) << 16usize); - } - #[doc = "Enable double transfer rate (DTR) for write commands: address, suffix and write data phases are active on both edges of SCK. SDO data is launched centre-aligned on each SCK edge, and SDI data is captured on the SCK edge that follows its launch. DTR is implemented by halving the clock rate; SCK has a period of 2 x CLK_DIV throughout the transfer. The prefix and dummy phases are still single transfer rate. If the suffix is quad-width, it must be 0 or 8 bits in length, to ensure an even number of SCK edges."] - #[inline(always)] - pub const fn dtr(&self) -> bool { - let val = (self.0 >> 28usize) & 0x01; - val != 0 - } - #[doc = "Enable double transfer rate (DTR) for write commands: address, suffix and write data phases are active on both edges of SCK. SDO data is launched centre-aligned on each SCK edge, and SDI data is captured on the SCK edge that follows its launch. DTR is implemented by halving the clock rate; SCK has a period of 2 x CLK_DIV throughout the transfer. The prefix and dummy phases are still single transfer rate. If the suffix is quad-width, it must be 0 or 8 bits in length, to ensure an even number of SCK edges."] - #[inline(always)] - pub fn set_dtr(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 28usize)) | (((val as u32) & 0x01) << 28usize); - } -} -impl Default for M0wfmt { - #[inline(always)] - fn default() -> M0wfmt { - M0wfmt(0) - } -} #[doc = "Command constants used for reads from memory address window 1. The reset value of the M1_RCMD register is configured to support a basic 03h serial read transfer with no additional configuration."] #[repr(transparent)] #[derive(Copy, Clone, Eq, PartialEq)] -pub struct M1rcmd(pub u32); -impl M1rcmd { +pub struct Rcmd(pub u32); +impl Rcmd { #[doc = "The command prefix bits to prepend on each new transfer, if Mx_RFMT_PREFIX_LEN is nonzero."] #[inline(always)] pub const fn prefix(&self) -> u8 { @@ -944,103 +316,103 @@ impl M1rcmd { self.0 = (self.0 & !(0xff << 8usize)) | (((val as u32) & 0xff) << 8usize); } } -impl Default for M1rcmd { +impl Default for Rcmd { #[inline(always)] - fn default() -> M1rcmd { - M1rcmd(0) + fn default() -> Rcmd { + Rcmd(0) } } -#[doc = "Read transfer format configuration for memory address window 1. Configure the bus width of each transfer phase individually, and configure the length or presence of the command prefix, command suffix and dummy/turnaround transfer phases. Only 24-bit addresses are supported. The reset value of the M1_RFMT register is configured to support a basic 03h serial read transfer with no additional configuration."] +#[doc = "Read transfer format configuration for memory address window 0. Configure the bus width of each transfer phase individually, and configure the length or presence of the command prefix, command suffix and dummy/turnaround transfer phases. Only 24-bit addresses are supported. The reset value of the M0_RFMT register is configured to support a basic 03h serial read transfer with no additional configuration."] #[repr(transparent)] #[derive(Copy, Clone, Eq, PartialEq)] -pub struct M1rfmt(pub u32); -impl M1rfmt { +pub struct Rfmt(pub u32); +impl Rfmt { #[doc = "The transfer width used for the command prefix, if any"] #[inline(always)] - pub const fn prefix_width(&self) -> super::vals::M1rfmtPrefixWidth { + pub const fn prefix_width(&self) -> super::vals::PrefixWidth { let val = (self.0 >> 0usize) & 0x03; - super::vals::M1rfmtPrefixWidth::from_bits(val as u8) + super::vals::PrefixWidth::from_bits(val as u8) } #[doc = "The transfer width used for the command prefix, if any"] #[inline(always)] - pub fn set_prefix_width(&mut self, val: super::vals::M1rfmtPrefixWidth) { + pub fn set_prefix_width(&mut self, val: super::vals::PrefixWidth) { self.0 = (self.0 & !(0x03 << 0usize)) | (((val.to_bits() as u32) & 0x03) << 0usize); } #[doc = "The transfer width used for the address. The address phase always transfers 24 bits in total."] #[inline(always)] - pub const fn addr_width(&self) -> super::vals::M1rfmtAddrWidth { + pub const fn addr_width(&self) -> super::vals::AddrWidth { let val = (self.0 >> 2usize) & 0x03; - super::vals::M1rfmtAddrWidth::from_bits(val as u8) + super::vals::AddrWidth::from_bits(val as u8) } #[doc = "The transfer width used for the address. The address phase always transfers 24 bits in total."] #[inline(always)] - pub fn set_addr_width(&mut self, val: super::vals::M1rfmtAddrWidth) { + pub fn set_addr_width(&mut self, val: super::vals::AddrWidth) { self.0 = (self.0 & !(0x03 << 2usize)) | (((val.to_bits() as u32) & 0x03) << 2usize); } #[doc = "The width used for the post-address command suffix, if any"] #[inline(always)] - pub const fn suffix_width(&self) -> super::vals::M1rfmtSuffixWidth { + pub const fn suffix_width(&self) -> super::vals::SuffixWidth { let val = (self.0 >> 4usize) & 0x03; - super::vals::M1rfmtSuffixWidth::from_bits(val as u8) + super::vals::SuffixWidth::from_bits(val as u8) } #[doc = "The width used for the post-address command suffix, if any"] #[inline(always)] - pub fn set_suffix_width(&mut self, val: super::vals::M1rfmtSuffixWidth) { + pub fn set_suffix_width(&mut self, val: super::vals::SuffixWidth) { self.0 = (self.0 & !(0x03 << 4usize)) | (((val.to_bits() as u32) & 0x03) << 4usize); } #[doc = "The width used for the dummy phase, if any. If width is single, SD0/MOSI is held asserted low during the dummy phase, and SD1...SD3 are tristated. If width is dual/quad, all IOs are tristated during the dummy phase."] #[inline(always)] - pub const fn dummy_width(&self) -> super::vals::M1rfmtDummyWidth { + pub const fn dummy_width(&self) -> super::vals::DummyWidth { let val = (self.0 >> 6usize) & 0x03; - super::vals::M1rfmtDummyWidth::from_bits(val as u8) + super::vals::DummyWidth::from_bits(val as u8) } #[doc = "The width used for the dummy phase, if any. If width is single, SD0/MOSI is held asserted low during the dummy phase, and SD1...SD3 are tristated. If width is dual/quad, all IOs are tristated during the dummy phase."] #[inline(always)] - pub fn set_dummy_width(&mut self, val: super::vals::M1rfmtDummyWidth) { + pub fn set_dummy_width(&mut self, val: super::vals::DummyWidth) { self.0 = (self.0 & !(0x03 << 6usize)) | (((val.to_bits() as u32) & 0x03) << 6usize); } #[doc = "The width used for the data transfer"] #[inline(always)] - pub const fn data_width(&self) -> super::vals::M1rfmtDataWidth { + pub const fn data_width(&self) -> super::vals::DataWidth { let val = (self.0 >> 8usize) & 0x03; - super::vals::M1rfmtDataWidth::from_bits(val as u8) + super::vals::DataWidth::from_bits(val as u8) } #[doc = "The width used for the data transfer"] #[inline(always)] - pub fn set_data_width(&mut self, val: super::vals::M1rfmtDataWidth) { + pub fn set_data_width(&mut self, val: super::vals::DataWidth) { self.0 = (self.0 & !(0x03 << 8usize)) | (((val.to_bits() as u32) & 0x03) << 8usize); } #[doc = "Length of command prefix, in units of 8 bits. (i.e. 2 cycles for quad width, 4 for dual, 8 for single)"] #[inline(always)] - pub const fn prefix_len(&self) -> super::vals::M1rfmtPrefixLen { + pub const fn prefix_len(&self) -> super::vals::PrefixLen { let val = (self.0 >> 12usize) & 0x01; - super::vals::M1rfmtPrefixLen::from_bits(val as u8) + super::vals::PrefixLen::from_bits(val as u8) } #[doc = "Length of command prefix, in units of 8 bits. (i.e. 2 cycles for quad width, 4 for dual, 8 for single)"] #[inline(always)] - pub fn set_prefix_len(&mut self, val: super::vals::M1rfmtPrefixLen) { + pub fn set_prefix_len(&mut self, val: super::vals::PrefixLen) { self.0 = (self.0 & !(0x01 << 12usize)) | (((val.to_bits() as u32) & 0x01) << 12usize); } #[doc = "Length of post-address command suffix, in units of 4 bits. (i.e. 1 cycle for quad width, 2 for dual, 4 for single) Only values of 0 and 8 bits are supported."] #[inline(always)] - pub const fn suffix_len(&self) -> super::vals::M1rfmtSuffixLen { + pub const fn suffix_len(&self) -> super::vals::SuffixLen { let val = (self.0 >> 14usize) & 0x03; - super::vals::M1rfmtSuffixLen::from_bits(val as u8) + super::vals::SuffixLen::from_bits(val as u8) } #[doc = "Length of post-address command suffix, in units of 4 bits. (i.e. 1 cycle for quad width, 2 for dual, 4 for single) Only values of 0 and 8 bits are supported."] #[inline(always)] - pub fn set_suffix_len(&mut self, val: super::vals::M1rfmtSuffixLen) { + pub fn set_suffix_len(&mut self, val: super::vals::SuffixLen) { self.0 = (self.0 & !(0x03 << 14usize)) | (((val.to_bits() as u32) & 0x03) << 14usize); } #[doc = "Length of dummy phase between command suffix and data phase, in units of 4 bits. (i.e. 1 cycle for quad width, 2 for dual, 4 for single)"] #[inline(always)] - pub const fn dummy_len(&self) -> super::vals::M1rfmtDummyLen { + pub const fn dummy_len(&self) -> super::vals::DummyLen { let val = (self.0 >> 16usize) & 0x07; - super::vals::M1rfmtDummyLen::from_bits(val as u8) + super::vals::DummyLen::from_bits(val as u8) } #[doc = "Length of dummy phase between command suffix and data phase, in units of 4 bits. (i.e. 1 cycle for quad width, 2 for dual, 4 for single)"] #[inline(always)] - pub fn set_dummy_len(&mut self, val: super::vals::M1rfmtDummyLen) { + pub fn set_dummy_len(&mut self, val: super::vals::DummyLen) { self.0 = (self.0 & !(0x07 << 16usize)) | (((val.to_bits() as u32) & 0x07) << 16usize); } #[doc = "Enable double transfer rate (DTR) for read commands: address, suffix and read data phases are active on both edges of SCK. SDO data is launched centre-aligned on each SCK edge, and SDI data is captured on the SCK edge that follows its launch. DTR is implemented by halving the clock rate; SCK has a period of 2 x CLK_DIV throughout the transfer. The prefix and dummy phases are still single transfer rate. If the suffix is quad-width, it must be 0 or 8 bits in length, to ensure an even number of SCK edges."] @@ -1055,17 +427,17 @@ impl M1rfmt { self.0 = (self.0 & !(0x01 << 28usize)) | (((val as u32) & 0x01) << 28usize); } } -impl Default for M1rfmt { +impl Default for Rfmt { #[inline(always)] - fn default() -> M1rfmt { - M1rfmt(0) + fn default() -> Rfmt { + Rfmt(0) } } #[doc = "Timing configuration register for memory address window 1."] #[repr(transparent)] #[derive(Copy, Clone, Eq, PartialEq)] -pub struct M1timing(pub u32); -impl M1timing { +pub struct Timing(pub u32); +impl Timing { #[doc = "Clock divisor. Odd and even divisors are supported. Defines the SCK clock period in units of 1 system clock cycle. Divisors 1..255 are encoded directly, and a divisor of 256 is encoded with a value of CLKDIV=0. The clock divisor can be changed on-the-fly, even when the QMI is currently accessing memory in this address window. All other parameters must only be changed when the QMI is idle. If software is increasing CLKDIV in anticipation of an increase in the system clock frequency, a dummy access to either memory window (and appropriate processor barriers/fences) must be inserted after the Mx_TIMING write to ensure the SCK divisor change is in effect _before_ the system clock is changed."] #[inline(always)] pub const fn clkdiv(&self) -> u8 { @@ -1134,13 +506,13 @@ impl M1timing { } #[doc = "When page break is enabled, chip select will automatically deassert when crossing certain power-of-2-aligned address boundaries. The next access will always begin a new read/write SPI burst, even if the address of the next access follows in sequence with the last access before the page boundary. Some flash and PSRAM devices forbid crossing page boundaries with a single read/write transfer, or restrict the operating frequency for transfers that do cross page a boundary. This option allows the QMI to safely support those devices. This field has no effect when COOLDOWN is disabled."] #[inline(always)] - pub const fn pagebreak(&self) -> super::vals::M1timingPagebreak { + pub const fn pagebreak(&self) -> super::vals::Pagebreak { let val = (self.0 >> 28usize) & 0x03; - super::vals::M1timingPagebreak::from_bits(val as u8) + super::vals::Pagebreak::from_bits(val as u8) } #[doc = "When page break is enabled, chip select will automatically deassert when crossing certain power-of-2-aligned address boundaries. The next access will always begin a new read/write SPI burst, even if the address of the next access follows in sequence with the last access before the page boundary. Some flash and PSRAM devices forbid crossing page boundaries with a single read/write transfer, or restrict the operating frequency for transfers that do cross page a boundary. This option allows the QMI to safely support those devices. This field has no effect when COOLDOWN is disabled."] #[inline(always)] - pub fn set_pagebreak(&mut self, val: super::vals::M1timingPagebreak) { + pub fn set_pagebreak(&mut self, val: super::vals::Pagebreak) { self.0 = (self.0 & !(0x03 << 28usize)) | (((val.to_bits() as u32) & 0x03) << 28usize); } #[doc = "Chip select cooldown period. When a memory transfer finishes, the chip select remains asserted for 64 x COOLDOWN system clock cycles, plus half an SCK clock period (rounded up for odd SCK divisors). After this cooldown expires, the chip select is always deasserted to save power. If the next memory access arrives within the cooldown period, the QMI may be able to append more SCK cycles to the currently ongoing SPI transfer, rather than starting a new transfer. This reduces access latency and increases bus throughput. Specifically, the next access must be in the same direction (read/write), access the same memory window (chip select 0/1), and follow sequentially the address of the last transfer. If any of these are false, the new access will first deassert the chip select, then begin a new transfer. If COOLDOWN is 0, the address alignment configured by PAGEBREAK has been reached, or the total chip select assertion limit MAX_SELECT has been reached, the cooldown period is skipped, and the chip select will always be deasserted one half SCK period after the transfer finishes."] @@ -1155,17 +527,17 @@ impl M1timing { self.0 = (self.0 & !(0x03 << 30usize)) | (((val as u32) & 0x03) << 30usize); } } -impl Default for M1timing { +impl Default for Timing { #[inline(always)] - fn default() -> M1timing { - M1timing(0) + fn default() -> Timing { + Timing(0) } } #[doc = "Command constants used for writes to memory address window 1. The reset value of the M1_WCMD register is configured to support a basic 02h serial write transfer with no additional configuration."] #[repr(transparent)] #[derive(Copy, Clone, Eq, PartialEq)] -pub struct M1wcmd(pub u32); -impl M1wcmd { +pub struct Wcmd(pub u32); +impl Wcmd { #[doc = "The command prefix bits to prepend on each new transfer, if Mx_WFMT_PREFIX_LEN is nonzero."] #[inline(always)] pub const fn prefix(&self) -> u8 { @@ -1189,103 +561,103 @@ impl M1wcmd { self.0 = (self.0 & !(0xff << 8usize)) | (((val as u32) & 0xff) << 8usize); } } -impl Default for M1wcmd { +impl Default for Wcmd { #[inline(always)] - fn default() -> M1wcmd { - M1wcmd(0) + fn default() -> Wcmd { + Wcmd(0) } } #[doc = "Write transfer format configuration for memory address window 1. Configure the bus width of each transfer phase individually, and configure the length or presence of the command prefix, command suffix and dummy/turnaround transfer phases. Only 24-bit addresses are supported. The reset value of the M1_WFMT register is configured to support a basic 02h serial write transfer. However, writes to this window must first be enabled via the XIP_CTRL_WRITABLE_M1 bit, as XIP memory is read-only by default."] #[repr(transparent)] #[derive(Copy, Clone, Eq, PartialEq)] -pub struct M1wfmt(pub u32); -impl M1wfmt { +pub struct Wfmt(pub u32); +impl Wfmt { #[doc = "The transfer width used for the command prefix, if any"] #[inline(always)] - pub const fn prefix_width(&self) -> super::vals::M1wfmtPrefixWidth { + pub const fn prefix_width(&self) -> super::vals::PrefixWidth { let val = (self.0 >> 0usize) & 0x03; - super::vals::M1wfmtPrefixWidth::from_bits(val as u8) + super::vals::PrefixWidth::from_bits(val as u8) } #[doc = "The transfer width used for the command prefix, if any"] #[inline(always)] - pub fn set_prefix_width(&mut self, val: super::vals::M1wfmtPrefixWidth) { + pub fn set_prefix_width(&mut self, val: super::vals::PrefixWidth) { self.0 = (self.0 & !(0x03 << 0usize)) | (((val.to_bits() as u32) & 0x03) << 0usize); } #[doc = "The transfer width used for the address. The address phase always transfers 24 bits in total."] #[inline(always)] - pub const fn addr_width(&self) -> super::vals::M1wfmtAddrWidth { + pub const fn addr_width(&self) -> super::vals::AddrWidth { let val = (self.0 >> 2usize) & 0x03; - super::vals::M1wfmtAddrWidth::from_bits(val as u8) + super::vals::AddrWidth::from_bits(val as u8) } #[doc = "The transfer width used for the address. The address phase always transfers 24 bits in total."] #[inline(always)] - pub fn set_addr_width(&mut self, val: super::vals::M1wfmtAddrWidth) { + pub fn set_addr_width(&mut self, val: super::vals::AddrWidth) { self.0 = (self.0 & !(0x03 << 2usize)) | (((val.to_bits() as u32) & 0x03) << 2usize); } #[doc = "The width used for the post-address command suffix, if any"] #[inline(always)] - pub const fn suffix_width(&self) -> super::vals::M1wfmtSuffixWidth { + pub const fn suffix_width(&self) -> super::vals::SuffixWidth { let val = (self.0 >> 4usize) & 0x03; - super::vals::M1wfmtSuffixWidth::from_bits(val as u8) + super::vals::SuffixWidth::from_bits(val as u8) } #[doc = "The width used for the post-address command suffix, if any"] #[inline(always)] - pub fn set_suffix_width(&mut self, val: super::vals::M1wfmtSuffixWidth) { + pub fn set_suffix_width(&mut self, val: super::vals::SuffixWidth) { self.0 = (self.0 & !(0x03 << 4usize)) | (((val.to_bits() as u32) & 0x03) << 4usize); } #[doc = "The width used for the dummy phase, if any. If width is single, SD0/MOSI is held asserted low during the dummy phase, and SD1...SD3 are tristated. If width is dual/quad, all IOs are tristated during the dummy phase."] #[inline(always)] - pub const fn dummy_width(&self) -> super::vals::M1wfmtDummyWidth { + pub const fn dummy_width(&self) -> super::vals::DummyWidth { let val = (self.0 >> 6usize) & 0x03; - super::vals::M1wfmtDummyWidth::from_bits(val as u8) + super::vals::DummyWidth::from_bits(val as u8) } #[doc = "The width used for the dummy phase, if any. If width is single, SD0/MOSI is held asserted low during the dummy phase, and SD1...SD3 are tristated. If width is dual/quad, all IOs are tristated during the dummy phase."] #[inline(always)] - pub fn set_dummy_width(&mut self, val: super::vals::M1wfmtDummyWidth) { + pub fn set_dummy_width(&mut self, val: super::vals::DummyWidth) { self.0 = (self.0 & !(0x03 << 6usize)) | (((val.to_bits() as u32) & 0x03) << 6usize); } #[doc = "The width used for the data transfer"] #[inline(always)] - pub const fn data_width(&self) -> super::vals::M1wfmtDataWidth { + pub const fn data_width(&self) -> super::vals::DataWidth { let val = (self.0 >> 8usize) & 0x03; - super::vals::M1wfmtDataWidth::from_bits(val as u8) + super::vals::DataWidth::from_bits(val as u8) } #[doc = "The width used for the data transfer"] #[inline(always)] - pub fn set_data_width(&mut self, val: super::vals::M1wfmtDataWidth) { + pub fn set_data_width(&mut self, val: super::vals::DataWidth) { self.0 = (self.0 & !(0x03 << 8usize)) | (((val.to_bits() as u32) & 0x03) << 8usize); } #[doc = "Length of command prefix, in units of 8 bits. (i.e. 2 cycles for quad width, 4 for dual, 8 for single)"] #[inline(always)] - pub const fn prefix_len(&self) -> super::vals::M1wfmtPrefixLen { + pub const fn prefix_len(&self) -> super::vals::PrefixLen { let val = (self.0 >> 12usize) & 0x01; - super::vals::M1wfmtPrefixLen::from_bits(val as u8) + super::vals::PrefixLen::from_bits(val as u8) } #[doc = "Length of command prefix, in units of 8 bits. (i.e. 2 cycles for quad width, 4 for dual, 8 for single)"] #[inline(always)] - pub fn set_prefix_len(&mut self, val: super::vals::M1wfmtPrefixLen) { + pub fn set_prefix_len(&mut self, val: super::vals::PrefixLen) { self.0 = (self.0 & !(0x01 << 12usize)) | (((val.to_bits() as u32) & 0x01) << 12usize); } #[doc = "Length of post-address command suffix, in units of 4 bits. (i.e. 1 cycle for quad width, 2 for dual, 4 for single) Only values of 0 and 8 bits are supported."] #[inline(always)] - pub const fn suffix_len(&self) -> super::vals::M1wfmtSuffixLen { + pub const fn suffix_len(&self) -> super::vals::SuffixLen { let val = (self.0 >> 14usize) & 0x03; - super::vals::M1wfmtSuffixLen::from_bits(val as u8) + super::vals::SuffixLen::from_bits(val as u8) } #[doc = "Length of post-address command suffix, in units of 4 bits. (i.e. 1 cycle for quad width, 2 for dual, 4 for single) Only values of 0 and 8 bits are supported."] #[inline(always)] - pub fn set_suffix_len(&mut self, val: super::vals::M1wfmtSuffixLen) { + pub fn set_suffix_len(&mut self, val: super::vals::SuffixLen) { self.0 = (self.0 & !(0x03 << 14usize)) | (((val.to_bits() as u32) & 0x03) << 14usize); } #[doc = "Length of dummy phase between command suffix and data phase, in units of 4 bits. (i.e. 1 cycle for quad width, 2 for dual, 4 for single)"] #[inline(always)] - pub const fn dummy_len(&self) -> super::vals::M1wfmtDummyLen { + pub const fn dummy_len(&self) -> super::vals::DummyLen { let val = (self.0 >> 16usize) & 0x07; - super::vals::M1wfmtDummyLen::from_bits(val as u8) + super::vals::DummyLen::from_bits(val as u8) } #[doc = "Length of dummy phase between command suffix and data phase, in units of 4 bits. (i.e. 1 cycle for quad width, 2 for dual, 4 for single)"] #[inline(always)] - pub fn set_dummy_len(&mut self, val: super::vals::M1wfmtDummyLen) { + pub fn set_dummy_len(&mut self, val: super::vals::DummyLen) { self.0 = (self.0 & !(0x07 << 16usize)) | (((val.to_bits() as u32) & 0x07) << 16usize); } #[doc = "Enable double transfer rate (DTR) for write commands: address, suffix and write data phases are active on both edges of SCK. SDO data is launched centre-aligned on each SCK edge, and SDI data is captured on the SCK edge that follows its launch. DTR is implemented by halving the clock rate; SCK has a period of 2 x CLK_DIV throughout the transfer. The prefix and dummy phases are still single transfer rate. If the suffix is quad-width, it must be 0 or 8 bits in length, to ensure an even number of SCK edges."] @@ -1300,9 +672,9 @@ impl M1wfmt { self.0 = (self.0 & !(0x01 << 28usize)) | (((val as u32) & 0x01) << 28usize); } } -impl Default for M1wfmt { +impl Default for Wfmt { #[inline(always)] - fn default() -> M1wfmt { - M1wfmt(0) + fn default() -> Wfmt { + Wfmt(0) } } diff --git a/src/rp235x/qmi/vals.rs b/src/rp235x/qmi/vals.rs index 937d94a4..dd4d2e54 100644 --- a/src/rp235x/qmi/vals.rs +++ b/src/rp235x/qmi/vals.rs @@ -1,622 +1,17 @@ #[repr(u8)] #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] -pub enum Iwidth { - #[doc = "Single width"] - S = 0, - #[doc = "Dual width"] - D = 0x01, - #[doc = "Quad width"] - Q = 0x02, - _RESERVED_3 = 0x03, -} -impl Iwidth { - #[inline(always)] - pub const fn from_bits(val: u8) -> Iwidth { - unsafe { core::mem::transmute(val & 0x03) } - } - #[inline(always)] - pub const fn to_bits(self) -> u8 { - unsafe { core::mem::transmute(self) } - } -} -impl From for Iwidth { - #[inline(always)] - fn from(val: u8) -> Iwidth { - Iwidth::from_bits(val) - } -} -impl From for u8 { - #[inline(always)] - fn from(val: Iwidth) -> u8 { - Iwidth::to_bits(val) - } -} -#[repr(u8)] -#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] -pub enum M0rfmtAddrWidth { - #[doc = "Single width"] - S = 0, - #[doc = "Dual width"] - D = 0x01, - #[doc = "Quad width"] - Q = 0x02, - _RESERVED_3 = 0x03, -} -impl M0rfmtAddrWidth { - #[inline(always)] - pub const fn from_bits(val: u8) -> M0rfmtAddrWidth { - unsafe { core::mem::transmute(val & 0x03) } - } - #[inline(always)] - pub const fn to_bits(self) -> u8 { - unsafe { core::mem::transmute(self) } - } -} -impl From for M0rfmtAddrWidth { - #[inline(always)] - fn from(val: u8) -> M0rfmtAddrWidth { - M0rfmtAddrWidth::from_bits(val) - } -} -impl From for u8 { - #[inline(always)] - fn from(val: M0rfmtAddrWidth) -> u8 { - M0rfmtAddrWidth::to_bits(val) - } -} -#[repr(u8)] -#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] -pub enum M0rfmtDataWidth { - #[doc = "Single width"] - S = 0, - #[doc = "Dual width"] - D = 0x01, - #[doc = "Quad width"] - Q = 0x02, - _RESERVED_3 = 0x03, -} -impl M0rfmtDataWidth { - #[inline(always)] - pub const fn from_bits(val: u8) -> M0rfmtDataWidth { - unsafe { core::mem::transmute(val & 0x03) } - } - #[inline(always)] - pub const fn to_bits(self) -> u8 { - unsafe { core::mem::transmute(self) } - } -} -impl From for M0rfmtDataWidth { - #[inline(always)] - fn from(val: u8) -> M0rfmtDataWidth { - M0rfmtDataWidth::from_bits(val) - } -} -impl From for u8 { - #[inline(always)] - fn from(val: M0rfmtDataWidth) -> u8 { - M0rfmtDataWidth::to_bits(val) - } -} -#[repr(u8)] -#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] -pub enum M0rfmtDummyLen { - #[doc = "No dummy phase"] - NONE = 0, - #[doc = "4 dummy bits"] - _4 = 0x01, - #[doc = "8 dummy bits"] - _8 = 0x02, - #[doc = "12 dummy bits"] - _12 = 0x03, - #[doc = "16 dummy bits"] - _16 = 0x04, - #[doc = "20 dummy bits"] - _20 = 0x05, - #[doc = "24 dummy bits"] - _24 = 0x06, - #[doc = "28 dummy bits"] - _28 = 0x07, -} -impl M0rfmtDummyLen { - #[inline(always)] - pub const fn from_bits(val: u8) -> M0rfmtDummyLen { - unsafe { core::mem::transmute(val & 0x07) } - } - #[inline(always)] - pub const fn to_bits(self) -> u8 { - unsafe { core::mem::transmute(self) } - } -} -impl From for M0rfmtDummyLen { - #[inline(always)] - fn from(val: u8) -> M0rfmtDummyLen { - M0rfmtDummyLen::from_bits(val) - } -} -impl From for u8 { - #[inline(always)] - fn from(val: M0rfmtDummyLen) -> u8 { - M0rfmtDummyLen::to_bits(val) - } -} -#[repr(u8)] -#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] -pub enum M0rfmtDummyWidth { - #[doc = "Single width"] - S = 0, - #[doc = "Dual width"] - D = 0x01, - #[doc = "Quad width"] - Q = 0x02, - _RESERVED_3 = 0x03, -} -impl M0rfmtDummyWidth { - #[inline(always)] - pub const fn from_bits(val: u8) -> M0rfmtDummyWidth { - unsafe { core::mem::transmute(val & 0x03) } - } - #[inline(always)] - pub const fn to_bits(self) -> u8 { - unsafe { core::mem::transmute(self) } - } -} -impl From for M0rfmtDummyWidth { - #[inline(always)] - fn from(val: u8) -> M0rfmtDummyWidth { - M0rfmtDummyWidth::from_bits(val) - } -} -impl From for u8 { - #[inline(always)] - fn from(val: M0rfmtDummyWidth) -> u8 { - M0rfmtDummyWidth::to_bits(val) - } -} -#[repr(u8)] -#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] -pub enum M0rfmtPrefixLen { - #[doc = "No prefix"] - NONE = 0, - #[doc = "8-bit prefix"] - _8 = 0x01, -} -impl M0rfmtPrefixLen { - #[inline(always)] - pub const fn from_bits(val: u8) -> M0rfmtPrefixLen { - unsafe { core::mem::transmute(val & 0x01) } - } - #[inline(always)] - pub const fn to_bits(self) -> u8 { - unsafe { core::mem::transmute(self) } - } -} -impl From for M0rfmtPrefixLen { - #[inline(always)] - fn from(val: u8) -> M0rfmtPrefixLen { - M0rfmtPrefixLen::from_bits(val) - } -} -impl From for u8 { - #[inline(always)] - fn from(val: M0rfmtPrefixLen) -> u8 { - M0rfmtPrefixLen::to_bits(val) - } -} -#[repr(u8)] -#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] -pub enum M0rfmtPrefixWidth { - #[doc = "Single width"] - S = 0, - #[doc = "Dual width"] - D = 0x01, - #[doc = "Quad width"] - Q = 0x02, - _RESERVED_3 = 0x03, -} -impl M0rfmtPrefixWidth { - #[inline(always)] - pub const fn from_bits(val: u8) -> M0rfmtPrefixWidth { - unsafe { core::mem::transmute(val & 0x03) } - } - #[inline(always)] - pub const fn to_bits(self) -> u8 { - unsafe { core::mem::transmute(self) } - } -} -impl From for M0rfmtPrefixWidth { - #[inline(always)] - fn from(val: u8) -> M0rfmtPrefixWidth { - M0rfmtPrefixWidth::from_bits(val) - } -} -impl From for u8 { - #[inline(always)] - fn from(val: M0rfmtPrefixWidth) -> u8 { - M0rfmtPrefixWidth::to_bits(val) - } -} -#[repr(u8)] -#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] -pub enum M0rfmtSuffixLen { - #[doc = "No suffix"] - NONE = 0, - _RESERVED_1 = 0x01, - #[doc = "8-bit suffix"] - _8 = 0x02, - _RESERVED_3 = 0x03, -} -impl M0rfmtSuffixLen { - #[inline(always)] - pub const fn from_bits(val: u8) -> M0rfmtSuffixLen { - unsafe { core::mem::transmute(val & 0x03) } - } - #[inline(always)] - pub const fn to_bits(self) -> u8 { - unsafe { core::mem::transmute(self) } - } -} -impl From for M0rfmtSuffixLen { - #[inline(always)] - fn from(val: u8) -> M0rfmtSuffixLen { - M0rfmtSuffixLen::from_bits(val) - } -} -impl From for u8 { - #[inline(always)] - fn from(val: M0rfmtSuffixLen) -> u8 { - M0rfmtSuffixLen::to_bits(val) - } -} -#[repr(u8)] -#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] -pub enum M0rfmtSuffixWidth { - #[doc = "Single width"] - S = 0, - #[doc = "Dual width"] - D = 0x01, - #[doc = "Quad width"] - Q = 0x02, - _RESERVED_3 = 0x03, -} -impl M0rfmtSuffixWidth { - #[inline(always)] - pub const fn from_bits(val: u8) -> M0rfmtSuffixWidth { - unsafe { core::mem::transmute(val & 0x03) } - } - #[inline(always)] - pub const fn to_bits(self) -> u8 { - unsafe { core::mem::transmute(self) } - } -} -impl From for M0rfmtSuffixWidth { - #[inline(always)] - fn from(val: u8) -> M0rfmtSuffixWidth { - M0rfmtSuffixWidth::from_bits(val) - } -} -impl From for u8 { - #[inline(always)] - fn from(val: M0rfmtSuffixWidth) -> u8 { - M0rfmtSuffixWidth::to_bits(val) - } -} -#[repr(u8)] -#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] -pub enum M0timingPagebreak { - #[doc = "No page boundary is enforced"] - NONE = 0, - #[doc = "Break bursts crossing a 256-byte page boundary"] - _256 = 0x01, - #[doc = "Break bursts crossing a 1024-byte quad-page boundary"] - _1024 = 0x02, - #[doc = "Break bursts crossing a 4096-byte sector boundary"] - _4096 = 0x03, -} -impl M0timingPagebreak { - #[inline(always)] - pub const fn from_bits(val: u8) -> M0timingPagebreak { - unsafe { core::mem::transmute(val & 0x03) } - } - #[inline(always)] - pub const fn to_bits(self) -> u8 { - unsafe { core::mem::transmute(self) } - } -} -impl From for M0timingPagebreak { - #[inline(always)] - fn from(val: u8) -> M0timingPagebreak { - M0timingPagebreak::from_bits(val) - } -} -impl From for u8 { - #[inline(always)] - fn from(val: M0timingPagebreak) -> u8 { - M0timingPagebreak::to_bits(val) - } -} -#[repr(u8)] -#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] -pub enum M0wfmtAddrWidth { - #[doc = "Single width"] - S = 0, - #[doc = "Dual width"] - D = 0x01, - #[doc = "Quad width"] - Q = 0x02, - _RESERVED_3 = 0x03, -} -impl M0wfmtAddrWidth { - #[inline(always)] - pub const fn from_bits(val: u8) -> M0wfmtAddrWidth { - unsafe { core::mem::transmute(val & 0x03) } - } - #[inline(always)] - pub const fn to_bits(self) -> u8 { - unsafe { core::mem::transmute(self) } - } -} -impl From for M0wfmtAddrWidth { - #[inline(always)] - fn from(val: u8) -> M0wfmtAddrWidth { - M0wfmtAddrWidth::from_bits(val) - } -} -impl From for u8 { - #[inline(always)] - fn from(val: M0wfmtAddrWidth) -> u8 { - M0wfmtAddrWidth::to_bits(val) - } -} -#[repr(u8)] -#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] -pub enum M0wfmtDataWidth { - #[doc = "Single width"] - S = 0, - #[doc = "Dual width"] - D = 0x01, - #[doc = "Quad width"] - Q = 0x02, - _RESERVED_3 = 0x03, -} -impl M0wfmtDataWidth { - #[inline(always)] - pub const fn from_bits(val: u8) -> M0wfmtDataWidth { - unsafe { core::mem::transmute(val & 0x03) } - } - #[inline(always)] - pub const fn to_bits(self) -> u8 { - unsafe { core::mem::transmute(self) } - } -} -impl From for M0wfmtDataWidth { - #[inline(always)] - fn from(val: u8) -> M0wfmtDataWidth { - M0wfmtDataWidth::from_bits(val) - } -} -impl From for u8 { - #[inline(always)] - fn from(val: M0wfmtDataWidth) -> u8 { - M0wfmtDataWidth::to_bits(val) - } -} -#[repr(u8)] -#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] -pub enum M0wfmtDummyLen { - #[doc = "No dummy phase"] - NONE = 0, - #[doc = "4 dummy bits"] - _4 = 0x01, - #[doc = "8 dummy bits"] - _8 = 0x02, - #[doc = "12 dummy bits"] - _12 = 0x03, - #[doc = "16 dummy bits"] - _16 = 0x04, - #[doc = "20 dummy bits"] - _20 = 0x05, - #[doc = "24 dummy bits"] - _24 = 0x06, - #[doc = "28 dummy bits"] - _28 = 0x07, -} -impl M0wfmtDummyLen { - #[inline(always)] - pub const fn from_bits(val: u8) -> M0wfmtDummyLen { - unsafe { core::mem::transmute(val & 0x07) } - } - #[inline(always)] - pub const fn to_bits(self) -> u8 { - unsafe { core::mem::transmute(self) } - } -} -impl From for M0wfmtDummyLen { - #[inline(always)] - fn from(val: u8) -> M0wfmtDummyLen { - M0wfmtDummyLen::from_bits(val) - } -} -impl From for u8 { - #[inline(always)] - fn from(val: M0wfmtDummyLen) -> u8 { - M0wfmtDummyLen::to_bits(val) - } -} -#[repr(u8)] -#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] -pub enum M0wfmtDummyWidth { - #[doc = "Single width"] - S = 0, - #[doc = "Dual width"] - D = 0x01, - #[doc = "Quad width"] - Q = 0x02, - _RESERVED_3 = 0x03, -} -impl M0wfmtDummyWidth { - #[inline(always)] - pub const fn from_bits(val: u8) -> M0wfmtDummyWidth { - unsafe { core::mem::transmute(val & 0x03) } - } - #[inline(always)] - pub const fn to_bits(self) -> u8 { - unsafe { core::mem::transmute(self) } - } -} -impl From for M0wfmtDummyWidth { - #[inline(always)] - fn from(val: u8) -> M0wfmtDummyWidth { - M0wfmtDummyWidth::from_bits(val) - } -} -impl From for u8 { - #[inline(always)] - fn from(val: M0wfmtDummyWidth) -> u8 { - M0wfmtDummyWidth::to_bits(val) - } -} -#[repr(u8)] -#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] -pub enum M0wfmtPrefixLen { - #[doc = "No prefix"] - NONE = 0, - #[doc = "8-bit prefix"] - _8 = 0x01, -} -impl M0wfmtPrefixLen { - #[inline(always)] - pub const fn from_bits(val: u8) -> M0wfmtPrefixLen { - unsafe { core::mem::transmute(val & 0x01) } - } - #[inline(always)] - pub const fn to_bits(self) -> u8 { - unsafe { core::mem::transmute(self) } - } -} -impl From for M0wfmtPrefixLen { - #[inline(always)] - fn from(val: u8) -> M0wfmtPrefixLen { - M0wfmtPrefixLen::from_bits(val) - } -} -impl From for u8 { - #[inline(always)] - fn from(val: M0wfmtPrefixLen) -> u8 { - M0wfmtPrefixLen::to_bits(val) - } -} -#[repr(u8)] -#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] -pub enum M0wfmtPrefixWidth { - #[doc = "Single width"] - S = 0, - #[doc = "Dual width"] - D = 0x01, - #[doc = "Quad width"] - Q = 0x02, - _RESERVED_3 = 0x03, -} -impl M0wfmtPrefixWidth { - #[inline(always)] - pub const fn from_bits(val: u8) -> M0wfmtPrefixWidth { - unsafe { core::mem::transmute(val & 0x03) } - } - #[inline(always)] - pub const fn to_bits(self) -> u8 { - unsafe { core::mem::transmute(self) } - } -} -impl From for M0wfmtPrefixWidth { - #[inline(always)] - fn from(val: u8) -> M0wfmtPrefixWidth { - M0wfmtPrefixWidth::from_bits(val) - } -} -impl From for u8 { - #[inline(always)] - fn from(val: M0wfmtPrefixWidth) -> u8 { - M0wfmtPrefixWidth::to_bits(val) - } -} -#[repr(u8)] -#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] -pub enum M0wfmtSuffixLen { - #[doc = "No suffix"] - NONE = 0, - _RESERVED_1 = 0x01, - #[doc = "8-bit suffix"] - _8 = 0x02, - _RESERVED_3 = 0x03, -} -impl M0wfmtSuffixLen { - #[inline(always)] - pub const fn from_bits(val: u8) -> M0wfmtSuffixLen { - unsafe { core::mem::transmute(val & 0x03) } - } - #[inline(always)] - pub const fn to_bits(self) -> u8 { - unsafe { core::mem::transmute(self) } - } -} -impl From for M0wfmtSuffixLen { - #[inline(always)] - fn from(val: u8) -> M0wfmtSuffixLen { - M0wfmtSuffixLen::from_bits(val) - } -} -impl From for u8 { - #[inline(always)] - fn from(val: M0wfmtSuffixLen) -> u8 { - M0wfmtSuffixLen::to_bits(val) - } -} -#[repr(u8)] -#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] -pub enum M0wfmtSuffixWidth { - #[doc = "Single width"] - S = 0, - #[doc = "Dual width"] - D = 0x01, - #[doc = "Quad width"] - Q = 0x02, - _RESERVED_3 = 0x03, -} -impl M0wfmtSuffixWidth { - #[inline(always)] - pub const fn from_bits(val: u8) -> M0wfmtSuffixWidth { - unsafe { core::mem::transmute(val & 0x03) } - } - #[inline(always)] - pub const fn to_bits(self) -> u8 { - unsafe { core::mem::transmute(self) } - } -} -impl From for M0wfmtSuffixWidth { - #[inline(always)] - fn from(val: u8) -> M0wfmtSuffixWidth { - M0wfmtSuffixWidth::from_bits(val) - } -} -impl From for u8 { - #[inline(always)] - fn from(val: M0wfmtSuffixWidth) -> u8 { - M0wfmtSuffixWidth::to_bits(val) - } -} -#[repr(u8)] -#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] -pub enum M1rfmtAddrWidth { +pub enum AddrWidth { #[doc = "Single width"] - S = 0, + S = 0x0, #[doc = "Dual width"] D = 0x01, #[doc = "Quad width"] Q = 0x02, _RESERVED_3 = 0x03, } -impl M1rfmtAddrWidth { +impl AddrWidth { #[inline(always)] - pub const fn from_bits(val: u8) -> M1rfmtAddrWidth { + pub const fn from_bits(val: u8) -> AddrWidth { unsafe { core::mem::transmute(val & 0x03) } } #[inline(always)] @@ -624,32 +19,32 @@ impl M1rfmtAddrWidth { unsafe { core::mem::transmute(self) } } } -impl From for M1rfmtAddrWidth { +impl From for AddrWidth { #[inline(always)] - fn from(val: u8) -> M1rfmtAddrWidth { - M1rfmtAddrWidth::from_bits(val) + fn from(val: u8) -> AddrWidth { + AddrWidth::from_bits(val) } } -impl From for u8 { +impl From for u8 { #[inline(always)] - fn from(val: M1rfmtAddrWidth) -> u8 { - M1rfmtAddrWidth::to_bits(val) + fn from(val: AddrWidth) -> u8 { + AddrWidth::to_bits(val) } } #[repr(u8)] #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] -pub enum M1rfmtDataWidth { +pub enum DataWidth { #[doc = "Single width"] - S = 0, + S = 0x0, #[doc = "Dual width"] D = 0x01, #[doc = "Quad width"] Q = 0x02, _RESERVED_3 = 0x03, } -impl M1rfmtDataWidth { +impl DataWidth { #[inline(always)] - pub const fn from_bits(val: u8) -> M1rfmtDataWidth { + pub const fn from_bits(val: u8) -> DataWidth { unsafe { core::mem::transmute(val & 0x03) } } #[inline(always)] @@ -657,23 +52,23 @@ impl M1rfmtDataWidth { unsafe { core::mem::transmute(self) } } } -impl From for M1rfmtDataWidth { +impl From for DataWidth { #[inline(always)] - fn from(val: u8) -> M1rfmtDataWidth { - M1rfmtDataWidth::from_bits(val) + fn from(val: u8) -> DataWidth { + DataWidth::from_bits(val) } } -impl From for u8 { +impl From for u8 { #[inline(always)] - fn from(val: M1rfmtDataWidth) -> u8 { - M1rfmtDataWidth::to_bits(val) + fn from(val: DataWidth) -> u8 { + DataWidth::to_bits(val) } } #[repr(u8)] #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] -pub enum M1rfmtDummyLen { +pub enum DummyLen { #[doc = "No dummy phase"] - NONE = 0, + NONE = 0x0, #[doc = "4 dummy bits"] _4 = 0x01, #[doc = "8 dummy bits"] @@ -689,9 +84,9 @@ pub enum M1rfmtDummyLen { #[doc = "28 dummy bits"] _28 = 0x07, } -impl M1rfmtDummyLen { +impl DummyLen { #[inline(always)] - pub const fn from_bits(val: u8) -> M1rfmtDummyLen { + pub const fn from_bits(val: u8) -> DummyLen { unsafe { core::mem::transmute(val & 0x07) } } #[inline(always)] @@ -699,127 +94,32 @@ impl M1rfmtDummyLen { unsafe { core::mem::transmute(self) } } } -impl From for M1rfmtDummyLen { - #[inline(always)] - fn from(val: u8) -> M1rfmtDummyLen { - M1rfmtDummyLen::from_bits(val) - } -} -impl From for u8 { - #[inline(always)] - fn from(val: M1rfmtDummyLen) -> u8 { - M1rfmtDummyLen::to_bits(val) - } -} -#[repr(u8)] -#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] -pub enum M1rfmtDummyWidth { - #[doc = "Single width"] - S = 0, - #[doc = "Dual width"] - D = 0x01, - #[doc = "Quad width"] - Q = 0x02, - _RESERVED_3 = 0x03, -} -impl M1rfmtDummyWidth { - #[inline(always)] - pub const fn from_bits(val: u8) -> M1rfmtDummyWidth { - unsafe { core::mem::transmute(val & 0x03) } - } - #[inline(always)] - pub const fn to_bits(self) -> u8 { - unsafe { core::mem::transmute(self) } - } -} -impl From for M1rfmtDummyWidth { - #[inline(always)] - fn from(val: u8) -> M1rfmtDummyWidth { - M1rfmtDummyWidth::from_bits(val) - } -} -impl From for u8 { - #[inline(always)] - fn from(val: M1rfmtDummyWidth) -> u8 { - M1rfmtDummyWidth::to_bits(val) - } -} -#[repr(u8)] -#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] -pub enum M1rfmtPrefixLen { - #[doc = "No prefix"] - NONE = 0, - #[doc = "8-bit prefix"] - _8 = 0x01, -} -impl M1rfmtPrefixLen { - #[inline(always)] - pub const fn from_bits(val: u8) -> M1rfmtPrefixLen { - unsafe { core::mem::transmute(val & 0x01) } - } - #[inline(always)] - pub const fn to_bits(self) -> u8 { - unsafe { core::mem::transmute(self) } - } -} -impl From for M1rfmtPrefixLen { +impl From for DummyLen { #[inline(always)] - fn from(val: u8) -> M1rfmtPrefixLen { - M1rfmtPrefixLen::from_bits(val) + fn from(val: u8) -> DummyLen { + DummyLen::from_bits(val) } } -impl From for u8 { +impl From for u8 { #[inline(always)] - fn from(val: M1rfmtPrefixLen) -> u8 { - M1rfmtPrefixLen::to_bits(val) + fn from(val: DummyLen) -> u8 { + DummyLen::to_bits(val) } } #[repr(u8)] #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] -pub enum M1rfmtPrefixWidth { +pub enum DummyWidth { #[doc = "Single width"] - S = 0, + S = 0x0, #[doc = "Dual width"] D = 0x01, #[doc = "Quad width"] Q = 0x02, _RESERVED_3 = 0x03, } -impl M1rfmtPrefixWidth { - #[inline(always)] - pub const fn from_bits(val: u8) -> M1rfmtPrefixWidth { - unsafe { core::mem::transmute(val & 0x03) } - } - #[inline(always)] - pub const fn to_bits(self) -> u8 { - unsafe { core::mem::transmute(self) } - } -} -impl From for M1rfmtPrefixWidth { - #[inline(always)] - fn from(val: u8) -> M1rfmtPrefixWidth { - M1rfmtPrefixWidth::from_bits(val) - } -} -impl From for u8 { - #[inline(always)] - fn from(val: M1rfmtPrefixWidth) -> u8 { - M1rfmtPrefixWidth::to_bits(val) - } -} -#[repr(u8)] -#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] -pub enum M1rfmtSuffixLen { - #[doc = "No suffix"] - NONE = 0, - _RESERVED_1 = 0x01, - #[doc = "8-bit suffix"] - _8 = 0x02, - _RESERVED_3 = 0x03, -} -impl M1rfmtSuffixLen { +impl DummyWidth { #[inline(always)] - pub const fn from_bits(val: u8) -> M1rfmtSuffixLen { + pub const fn from_bits(val: u8) -> DummyWidth { unsafe { core::mem::transmute(val & 0x03) } } #[inline(always)] @@ -827,32 +127,32 @@ impl M1rfmtSuffixLen { unsafe { core::mem::transmute(self) } } } -impl From for M1rfmtSuffixLen { +impl From for DummyWidth { #[inline(always)] - fn from(val: u8) -> M1rfmtSuffixLen { - M1rfmtSuffixLen::from_bits(val) + fn from(val: u8) -> DummyWidth { + DummyWidth::from_bits(val) } } -impl From for u8 { +impl From for u8 { #[inline(always)] - fn from(val: M1rfmtSuffixLen) -> u8 { - M1rfmtSuffixLen::to_bits(val) + fn from(val: DummyWidth) -> u8 { + DummyWidth::to_bits(val) } } #[repr(u8)] #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] -pub enum M1rfmtSuffixWidth { +pub enum Iwidth { #[doc = "Single width"] - S = 0, + S = 0x0, #[doc = "Dual width"] D = 0x01, #[doc = "Quad width"] Q = 0x02, _RESERVED_3 = 0x03, } -impl M1rfmtSuffixWidth { +impl Iwidth { #[inline(always)] - pub const fn from_bits(val: u8) -> M1rfmtSuffixWidth { + pub const fn from_bits(val: u8) -> Iwidth { unsafe { core::mem::transmute(val & 0x03) } } #[inline(always)] @@ -860,23 +160,23 @@ impl M1rfmtSuffixWidth { unsafe { core::mem::transmute(self) } } } -impl From for M1rfmtSuffixWidth { +impl From for Iwidth { #[inline(always)] - fn from(val: u8) -> M1rfmtSuffixWidth { - M1rfmtSuffixWidth::from_bits(val) + fn from(val: u8) -> Iwidth { + Iwidth::from_bits(val) } } -impl From for u8 { +impl From for u8 { #[inline(always)] - fn from(val: M1rfmtSuffixWidth) -> u8 { - M1rfmtSuffixWidth::to_bits(val) + fn from(val: Iwidth) -> u8 { + Iwidth::to_bits(val) } } #[repr(u8)] #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] -pub enum M1timingPagebreak { +pub enum Pagebreak { #[doc = "No page boundary is enforced"] - NONE = 0, + NONE = 0x0, #[doc = "Break bursts crossing a 256-byte page boundary"] _256 = 0x01, #[doc = "Break bursts crossing a 1024-byte quad-page boundary"] @@ -884,150 +184,9 @@ pub enum M1timingPagebreak { #[doc = "Break bursts crossing a 4096-byte sector boundary"] _4096 = 0x03, } -impl M1timingPagebreak { - #[inline(always)] - pub const fn from_bits(val: u8) -> M1timingPagebreak { - unsafe { core::mem::transmute(val & 0x03) } - } - #[inline(always)] - pub const fn to_bits(self) -> u8 { - unsafe { core::mem::transmute(self) } - } -} -impl From for M1timingPagebreak { - #[inline(always)] - fn from(val: u8) -> M1timingPagebreak { - M1timingPagebreak::from_bits(val) - } -} -impl From for u8 { - #[inline(always)] - fn from(val: M1timingPagebreak) -> u8 { - M1timingPagebreak::to_bits(val) - } -} -#[repr(u8)] -#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] -pub enum M1wfmtAddrWidth { - #[doc = "Single width"] - S = 0, - #[doc = "Dual width"] - D = 0x01, - #[doc = "Quad width"] - Q = 0x02, - _RESERVED_3 = 0x03, -} -impl M1wfmtAddrWidth { - #[inline(always)] - pub const fn from_bits(val: u8) -> M1wfmtAddrWidth { - unsafe { core::mem::transmute(val & 0x03) } - } - #[inline(always)] - pub const fn to_bits(self) -> u8 { - unsafe { core::mem::transmute(self) } - } -} -impl From for M1wfmtAddrWidth { - #[inline(always)] - fn from(val: u8) -> M1wfmtAddrWidth { - M1wfmtAddrWidth::from_bits(val) - } -} -impl From for u8 { - #[inline(always)] - fn from(val: M1wfmtAddrWidth) -> u8 { - M1wfmtAddrWidth::to_bits(val) - } -} -#[repr(u8)] -#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] -pub enum M1wfmtDataWidth { - #[doc = "Single width"] - S = 0, - #[doc = "Dual width"] - D = 0x01, - #[doc = "Quad width"] - Q = 0x02, - _RESERVED_3 = 0x03, -} -impl M1wfmtDataWidth { - #[inline(always)] - pub const fn from_bits(val: u8) -> M1wfmtDataWidth { - unsafe { core::mem::transmute(val & 0x03) } - } - #[inline(always)] - pub const fn to_bits(self) -> u8 { - unsafe { core::mem::transmute(self) } - } -} -impl From for M1wfmtDataWidth { - #[inline(always)] - fn from(val: u8) -> M1wfmtDataWidth { - M1wfmtDataWidth::from_bits(val) - } -} -impl From for u8 { - #[inline(always)] - fn from(val: M1wfmtDataWidth) -> u8 { - M1wfmtDataWidth::to_bits(val) - } -} -#[repr(u8)] -#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] -pub enum M1wfmtDummyLen { - #[doc = "No dummy phase"] - NONE = 0, - #[doc = "4 dummy bits"] - _4 = 0x01, - #[doc = "8 dummy bits"] - _8 = 0x02, - #[doc = "12 dummy bits"] - _12 = 0x03, - #[doc = "16 dummy bits"] - _16 = 0x04, - #[doc = "20 dummy bits"] - _20 = 0x05, - #[doc = "24 dummy bits"] - _24 = 0x06, - #[doc = "28 dummy bits"] - _28 = 0x07, -} -impl M1wfmtDummyLen { - #[inline(always)] - pub const fn from_bits(val: u8) -> M1wfmtDummyLen { - unsafe { core::mem::transmute(val & 0x07) } - } - #[inline(always)] - pub const fn to_bits(self) -> u8 { - unsafe { core::mem::transmute(self) } - } -} -impl From for M1wfmtDummyLen { - #[inline(always)] - fn from(val: u8) -> M1wfmtDummyLen { - M1wfmtDummyLen::from_bits(val) - } -} -impl From for u8 { - #[inline(always)] - fn from(val: M1wfmtDummyLen) -> u8 { - M1wfmtDummyLen::to_bits(val) - } -} -#[repr(u8)] -#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] -pub enum M1wfmtDummyWidth { - #[doc = "Single width"] - S = 0, - #[doc = "Dual width"] - D = 0x01, - #[doc = "Quad width"] - Q = 0x02, - _RESERVED_3 = 0x03, -} -impl M1wfmtDummyWidth { +impl Pagebreak { #[inline(always)] - pub const fn from_bits(val: u8) -> M1wfmtDummyWidth { + pub const fn from_bits(val: u8) -> Pagebreak { unsafe { core::mem::transmute(val & 0x03) } } #[inline(always)] @@ -1035,29 +194,29 @@ impl M1wfmtDummyWidth { unsafe { core::mem::transmute(self) } } } -impl From for M1wfmtDummyWidth { +impl From for Pagebreak { #[inline(always)] - fn from(val: u8) -> M1wfmtDummyWidth { - M1wfmtDummyWidth::from_bits(val) + fn from(val: u8) -> Pagebreak { + Pagebreak::from_bits(val) } } -impl From for u8 { +impl From for u8 { #[inline(always)] - fn from(val: M1wfmtDummyWidth) -> u8 { - M1wfmtDummyWidth::to_bits(val) + fn from(val: Pagebreak) -> u8 { + Pagebreak::to_bits(val) } } #[repr(u8)] #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] -pub enum M1wfmtPrefixLen { +pub enum PrefixLen { #[doc = "No prefix"] - NONE = 0, + NONE = 0x0, #[doc = "8-bit prefix"] _8 = 0x01, } -impl M1wfmtPrefixLen { +impl PrefixLen { #[inline(always)] - pub const fn from_bits(val: u8) -> M1wfmtPrefixLen { + pub const fn from_bits(val: u8) -> PrefixLen { unsafe { core::mem::transmute(val & 0x01) } } #[inline(always)] @@ -1065,32 +224,32 @@ impl M1wfmtPrefixLen { unsafe { core::mem::transmute(self) } } } -impl From for M1wfmtPrefixLen { +impl From for PrefixLen { #[inline(always)] - fn from(val: u8) -> M1wfmtPrefixLen { - M1wfmtPrefixLen::from_bits(val) + fn from(val: u8) -> PrefixLen { + PrefixLen::from_bits(val) } } -impl From for u8 { +impl From for u8 { #[inline(always)] - fn from(val: M1wfmtPrefixLen) -> u8 { - M1wfmtPrefixLen::to_bits(val) + fn from(val: PrefixLen) -> u8 { + PrefixLen::to_bits(val) } } #[repr(u8)] #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] -pub enum M1wfmtPrefixWidth { +pub enum PrefixWidth { #[doc = "Single width"] - S = 0, + S = 0x0, #[doc = "Dual width"] D = 0x01, #[doc = "Quad width"] Q = 0x02, _RESERVED_3 = 0x03, } -impl M1wfmtPrefixWidth { +impl PrefixWidth { #[inline(always)] - pub const fn from_bits(val: u8) -> M1wfmtPrefixWidth { + pub const fn from_bits(val: u8) -> PrefixWidth { unsafe { core::mem::transmute(val & 0x03) } } #[inline(always)] @@ -1098,31 +257,31 @@ impl M1wfmtPrefixWidth { unsafe { core::mem::transmute(self) } } } -impl From for M1wfmtPrefixWidth { +impl From for PrefixWidth { #[inline(always)] - fn from(val: u8) -> M1wfmtPrefixWidth { - M1wfmtPrefixWidth::from_bits(val) + fn from(val: u8) -> PrefixWidth { + PrefixWidth::from_bits(val) } } -impl From for u8 { +impl From for u8 { #[inline(always)] - fn from(val: M1wfmtPrefixWidth) -> u8 { - M1wfmtPrefixWidth::to_bits(val) + fn from(val: PrefixWidth) -> u8 { + PrefixWidth::to_bits(val) } } #[repr(u8)] #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] -pub enum M1wfmtSuffixLen { +pub enum SuffixLen { #[doc = "No suffix"] - NONE = 0, + NONE = 0x0, _RESERVED_1 = 0x01, #[doc = "8-bit suffix"] _8 = 0x02, _RESERVED_3 = 0x03, } -impl M1wfmtSuffixLen { +impl SuffixLen { #[inline(always)] - pub const fn from_bits(val: u8) -> M1wfmtSuffixLen { + pub const fn from_bits(val: u8) -> SuffixLen { unsafe { core::mem::transmute(val & 0x03) } } #[inline(always)] @@ -1130,32 +289,32 @@ impl M1wfmtSuffixLen { unsafe { core::mem::transmute(self) } } } -impl From for M1wfmtSuffixLen { +impl From for SuffixLen { #[inline(always)] - fn from(val: u8) -> M1wfmtSuffixLen { - M1wfmtSuffixLen::from_bits(val) + fn from(val: u8) -> SuffixLen { + SuffixLen::from_bits(val) } } -impl From for u8 { +impl From for u8 { #[inline(always)] - fn from(val: M1wfmtSuffixLen) -> u8 { - M1wfmtSuffixLen::to_bits(val) + fn from(val: SuffixLen) -> u8 { + SuffixLen::to_bits(val) } } #[repr(u8)] #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] -pub enum M1wfmtSuffixWidth { +pub enum SuffixWidth { #[doc = "Single width"] - S = 0, + S = 0x0, #[doc = "Dual width"] D = 0x01, #[doc = "Quad width"] Q = 0x02, _RESERVED_3 = 0x03, } -impl M1wfmtSuffixWidth { +impl SuffixWidth { #[inline(always)] - pub const fn from_bits(val: u8) -> M1wfmtSuffixWidth { + pub const fn from_bits(val: u8) -> SuffixWidth { unsafe { core::mem::transmute(val & 0x03) } } #[inline(always)] @@ -1163,15 +322,15 @@ impl M1wfmtSuffixWidth { unsafe { core::mem::transmute(self) } } } -impl From for M1wfmtSuffixWidth { +impl From for SuffixWidth { #[inline(always)] - fn from(val: u8) -> M1wfmtSuffixWidth { - M1wfmtSuffixWidth::from_bits(val) + fn from(val: u8) -> SuffixWidth { + SuffixWidth::from_bits(val) } } -impl From for u8 { +impl From for u8 { #[inline(always)] - fn from(val: M1wfmtSuffixWidth) -> u8 { - M1wfmtSuffixWidth::to_bits(val) + fn from(val: SuffixWidth) -> u8 { + SuffixWidth::to_bits(val) } } diff --git a/src/rp235x/resets.rs b/src/rp235x/resets.rs index 334731d1..ba1afea0 100644 --- a/src/rp235x/resets.rs +++ b/src/rp235x/resets.rs @@ -15,15 +15,15 @@ impl Resets { } #[inline(always)] pub const fn reset(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(0usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x0usize) as _) } } #[inline(always)] pub const fn wdsel(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(4usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x04usize) as _) } } #[inline(always)] pub const fn reset_done(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(8usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x08usize) as _) } } } pub mod regs; diff --git a/src/rp235x/rosc.rs b/src/rp235x/rosc.rs index b3772cec..065d7fac 100644 --- a/src/rp235x/rosc.rs +++ b/src/rp235x/rosc.rs @@ -16,52 +16,52 @@ impl Rosc { #[doc = "Ring Oscillator control"] #[inline(always)] pub const fn ctrl(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(0usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x0usize) as _) } } #[doc = "The FREQA & FREQB registers control the frequency by controlling the drive strength of each stage The drive strength has 4 levels determined by the number of bits set Increasing the number of bits set increases the drive strength and increases the oscillation frequency 0 bits set is the default drive strength 1 bit set doubles the drive strength 2 bits set triples drive strength 3 bits set quadruples drive strength For frequency randomisation set both DS0_RANDOM=1 & DS1_RANDOM=1"] #[inline(always)] pub const fn freqa(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(4usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x04usize) as _) } } #[doc = "For a detailed description see freqa register"] #[inline(always)] pub const fn freqb(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(8usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x08usize) as _) } } #[doc = "Loads a value to the LFSR randomiser"] #[inline(always)] pub const fn random(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(12usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x0cusize) as _) } } #[doc = "Ring Oscillator pause control"] #[inline(always)] pub const fn dormant(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(16usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x10usize) as _) } } #[doc = "Controls the output divider"] #[inline(always)] pub const fn div(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(20usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x14usize) as _) } } #[doc = "Controls the phase shifted output"] #[inline(always)] pub const fn phase(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(24usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x18usize) as _) } } #[doc = "Ring Oscillator Status"] #[inline(always)] pub const fn status(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(28usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x1cusize) as _) } } #[doc = "This just reads the state of the oscillator output so randomness is compromised if the ring oscillator is stopped or run at a harmonic of the bus frequency"] #[inline(always)] pub const fn randombit(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(32usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x20usize) as _) } } #[doc = "A down counter running at the ROSC frequency which counts to zero and stops. To start the counter write a non-zero value. Can be used for short software pauses when setting up time sensitive hardware."] #[inline(always)] pub const fn count(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(36usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x24usize) as _) } } } pub mod regs; diff --git a/src/rp235x/sha256.rs b/src/rp235x/sha256.rs index 5dd83fbd..d5f72d1f 100644 --- a/src/rp235x/sha256.rs +++ b/src/rp235x/sha256.rs @@ -17,52 +17,52 @@ impl Sha256 { #[doc = "Control and status register"] #[inline(always)] pub const fn csr(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(0usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x0usize) as _) } } #[doc = "Write data register"] #[inline(always)] pub const fn wdata(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(4usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x04usize) as _) } } #[doc = "256-bit checksum result. Contents are undefined when CSR_SUM_VLD is 0."] #[inline(always)] pub const fn sum0(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(8usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x08usize) as _) } } #[doc = "256-bit checksum result. Contents are undefined when CSR_SUM_VLD is 0."] #[inline(always)] pub const fn sum1(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(12usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x0cusize) as _) } } #[doc = "256-bit checksum result. Contents are undefined when CSR_SUM_VLD is 0."] #[inline(always)] pub const fn sum2(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(16usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x10usize) as _) } } #[doc = "256-bit checksum result. Contents are undefined when CSR_SUM_VLD is 0."] #[inline(always)] pub const fn sum3(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(20usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x14usize) as _) } } #[doc = "256-bit checksum result. Contents are undefined when CSR_SUM_VLD is 0."] #[inline(always)] pub const fn sum4(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(24usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x18usize) as _) } } #[doc = "256-bit checksum result. Contents are undefined when CSR_SUM_VLD is 0."] #[inline(always)] pub const fn sum5(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(28usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x1cusize) as _) } } #[doc = "256-bit checksum result. Contents are undefined when CSR_SUM_VLD is 0."] #[inline(always)] pub const fn sum6(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(32usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x20usize) as _) } } #[doc = "256-bit checksum result. Contents are undefined when CSR_SUM_VLD is 0."] #[inline(always)] pub const fn sum7(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(36usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x24usize) as _) } } } pub mod regs; diff --git a/src/rp235x/sha256/vals.rs b/src/rp235x/sha256/vals.rs index a35fc835..9b51e9a6 100644 --- a/src/rp235x/sha256/vals.rs +++ b/src/rp235x/sha256/vals.rs @@ -1,7 +1,7 @@ #[repr(u8)] #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] pub enum DmaSize { - _8BIT = 0, + _8BIT = 0x0, _16BIT = 0x01, _32BIT = 0x02, _RESERVED_3 = 0x03, diff --git a/src/rp235x/sio.rs b/src/rp235x/sio.rs index b6b6e921..4b94eb55 100644 --- a/src/rp235x/sio.rs +++ b/src/rp235x/sio.rs @@ -16,17 +16,17 @@ impl Fifo { #[doc = "Status register for inter-core FIFOs (mailboxes). There is one FIFO in the core 0 -> core 1 direction, and one core 1 -> core 0. Both are 32 bits wide and 8 words deep. Core 0 can see the read side of the 1->0 FIFO (RX), and the write side of 0->1 FIFO (TX). Core 1 can see the read side of the 0->1 FIFO (RX), and the write side of 1->0 FIFO (TX). The SIO IRQ for each core is the logical OR of the VLD, WOF and ROE fields of its FIFO_ST register."] #[inline(always)] pub const fn st(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(0usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x0usize) as _) } } #[doc = "Write access to this core's TX FIFO"] #[inline(always)] pub const fn wr(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(4usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x04usize) as _) } } #[doc = "Read access to this core's RX FIFO"] #[inline(always)] pub const fn rd(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(8usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x08usize) as _) } } } #[derive(Copy, Clone, Eq, PartialEq)] @@ -47,22 +47,22 @@ impl Gpio { #[doc = "GPIO0...31 output enable"] #[inline(always)] pub const fn value(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(0usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x0usize) as _) } } #[doc = "GPIO0...31 output enable set"] #[inline(always)] pub const fn value_set(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(8usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x08usize) as _) } } #[doc = "GPIO0...31 output enable clear"] #[inline(always)] pub const fn value_clr(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(16usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x10usize) as _) } } #[doc = "GPIO0...31 output enable XOR"] #[inline(always)] pub const fn value_xor(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(24usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x18usize) as _) } } } #[derive(Copy, Clone, Eq, PartialEq)] @@ -83,82 +83,82 @@ impl Interp { #[doc = "Read/write access to accumulator 0"] #[inline(always)] pub const fn accum0(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(0usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x0usize) as _) } } #[doc = "Read/write access to accumulator 1"] #[inline(always)] pub const fn accum1(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(4usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x04usize) as _) } } #[doc = "Read/write access to BASE0 register."] #[inline(always)] pub const fn base0(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(8usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x08usize) as _) } } #[doc = "Read/write access to BASE1 register."] #[inline(always)] pub const fn base1(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(12usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x0cusize) as _) } } #[doc = "Read/write access to BASE2 register."] #[inline(always)] pub const fn base2(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(16usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x10usize) as _) } } #[doc = "Read LANE0 result, and simultaneously write lane results to both accumulators (POP)."] #[inline(always)] pub const fn pop_lane0(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(20usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x14usize) as _) } } #[doc = "Read LANE1 result, and simultaneously write lane results to both accumulators (POP)."] #[inline(always)] pub const fn pop_lane1(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(24usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x18usize) as _) } } #[doc = "Read FULL result, and simultaneously write lane results to both accumulators (POP)."] #[inline(always)] pub const fn pop_full(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(28usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x1cusize) as _) } } #[doc = "Read LANE0 result, without altering any internal state (PEEK)."] #[inline(always)] pub const fn peek_lane0(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(32usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x20usize) as _) } } #[doc = "Read LANE1 result, without altering any internal state (PEEK)."] #[inline(always)] pub const fn peek_lane1(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(36usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x24usize) as _) } } #[doc = "Read FULL result, without altering any internal state (PEEK)."] #[inline(always)] pub const fn peek_full(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(40usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x28usize) as _) } } #[doc = "Control register for lane 0"] #[inline(always)] - pub const fn ctrl_lane0(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(44usize) as _) } + pub const fn ctrl_lane0(self) -> crate::common::Reg { + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x2cusize) as _) } } #[doc = "Control register for lane 1"] #[inline(always)] - pub const fn ctrl_lane1(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(48usize) as _) } + pub const fn ctrl_lane1(self) -> crate::common::Reg { + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x30usize) as _) } } #[doc = "Values written here are atomically added to ACCUM0 Reading yields lane 0's raw shift and mask value (BASE0 not added)."] #[inline(always)] - pub const fn accum0_add(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(52usize) as _) } + pub const fn accum0_add(self) -> crate::common::Reg { + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x34usize) as _) } } #[doc = "Values written here are atomically added to ACCUM1 Reading yields lane 1's raw shift and mask value (BASE1 not added)."] #[inline(always)] - pub const fn accum1_add(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(56usize) as _) } + pub const fn accum1_add(self) -> crate::common::Reg { + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x38usize) as _) } } #[doc = "On write, the lower 16 bits go to BASE0, upper bits to BASE1 simultaneously. Each half is sign-extended to 32 bits if that lane's SIGNED flag is set."] #[inline(always)] pub const fn base_1and0(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(60usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x3cusize) as _) } } } #[doc = "Single-cycle IO block Provides core-local and inter-core hardware for the two processors, with single-cycle access."] @@ -180,156 +180,156 @@ impl Sio { #[doc = "Processor core identifier"] #[inline(always)] pub const fn cpuid(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(0usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x0usize) as _) } } #[doc = "Input value for GPIO0...31. In the Non-secure SIO, Secure-only GPIOs (as per ACCESSCTRL) appear as zero."] #[inline(always)] pub const fn gpio_in(self, n: usize) -> crate::common::Reg { assert!(n < 2usize); - unsafe { crate::common::Reg::from_ptr(self.ptr.add(4usize + n * 4usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x04usize + n * 4usize) as _) } } #[inline(always)] pub const fn gpio_out(self, n: usize) -> Gpio { assert!(n < 2usize); - unsafe { Gpio::from_ptr(self.ptr.add(16usize + n * 4usize) as _) } + unsafe { Gpio::from_ptr(self.ptr.add(0x10usize + n * 4usize) as _) } } #[inline(always)] pub const fn gpio_oe(self, n: usize) -> Gpio { assert!(n < 2usize); - unsafe { Gpio::from_ptr(self.ptr.add(48usize + n * 4usize) as _) } + unsafe { Gpio::from_ptr(self.ptr.add(0x30usize + n * 4usize) as _) } } #[inline(always)] pub const fn fifo(self) -> Fifo { - unsafe { Fifo::from_ptr(self.ptr.add(80usize) as _) } + unsafe { Fifo::from_ptr(self.ptr.add(0x50usize) as _) } } #[doc = "Spinlock state A bitmap containing the state of all 32 spinlocks (1=locked). Mainly intended for debugging."] #[inline(always)] pub const fn spinlock_st(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(92usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x5cusize) as _) } } #[inline(always)] pub const fn interp(self, n: usize) -> Interp { assert!(n < 2usize); - unsafe { Interp::from_ptr(self.ptr.add(128usize + n * 64usize) as _) } + unsafe { Interp::from_ptr(self.ptr.add(0x80usize + n * 64usize) as _) } } #[doc = "Reading from a spinlock address will: - Return 0 if lock is already locked - Otherwise return nonzero, and simultaneously claim the lock Writing (any value) releases the lock. If core 0 and core 1 attempt to claim the same lock simultaneously, core 0 wins. The value returned on success is 0x1 << lock number."] #[inline(always)] pub const fn spinlock(self, n: usize) -> crate::common::Reg { assert!(n < 32usize); - unsafe { crate::common::Reg::from_ptr(self.ptr.add(256usize + n * 4usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x0100usize + n * 4usize) as _) } } #[doc = "Trigger a doorbell interrupt on the opposite core. Write 1 to a bit to set the corresponding bit in DOORBELL_IN on the opposite core. This raises the opposite core's doorbell interrupt. Read to get the status of the doorbells currently asserted on the opposite core. This is equivalent to that core reading its own DOORBELL_IN status."] #[inline(always)] pub const fn doorbell_out_set( self, ) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(384usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x0180usize) as _) } } #[doc = "Clear doorbells which have been posted to the opposite core. This register is intended for debugging and initialisation purposes. Writing 1 to a bit in DOORBELL_OUT_CLR clears the corresponding bit in DOORBELL_IN on the opposite core. Clearing all bits will cause that core's doorbell interrupt to deassert. Since the usual order of events is for software to send events using DOORBELL_OUT_SET, and acknowledge incoming events by writing to DOORBELL_IN_CLR, this register should be used with caution to avoid race conditions. Reading returns the status of the doorbells currently asserted on the other core, i.e. is equivalent to that core reading its own DOORBELL_IN status."] #[inline(always)] pub const fn doorbell_out_clr( self, ) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(388usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x0184usize) as _) } } #[doc = "Write 1s to trigger doorbell interrupts on this core. Read to get status of doorbells currently asserted on this core."] #[inline(always)] pub const fn doorbell_in_set( self, ) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(392usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x0188usize) as _) } } #[doc = "Check and acknowledge doorbells posted to this core. This core's doorbell interrupt is asserted when any bit in this register is 1. Write 1 to each bit to clear that bit. The doorbell interrupt deasserts once all bits are cleared. Read to get status of doorbells currently asserted on this core."] #[inline(always)] pub const fn doorbell_in_clr( self, ) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(396usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x018cusize) as _) } } #[doc = "Detach certain core-local peripherals from Secure SIO, and attach them to Non-secure SIO, so that Non-secure software can use them. Attempting to access one of these peripherals from the Secure SIO when it is attached to the Non-secure SIO, or vice versa, will generate a bus error. This register is per-core, and is only present on the Secure SIO. Most SIO hardware is duplicated across the Secure and Non-secure SIO, so is not listed in this register."] #[inline(always)] pub const fn peri_nonsec(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(400usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x0190usize) as _) } } #[doc = "Control the assertion of the standard software interrupt (MIP.MSIP) on the RISC-V cores. Unlike the RISC-V timer, this interrupt is not routed to a normal system-level interrupt line, so can not be used by the Arm cores. It is safe for both cores to write to this register on the same cycle. The set/clear effect is accumulated across both cores, and then applied. If a flag is both set and cleared on the same cycle, only the set takes effect."] #[inline(always)] pub const fn riscv_softirq(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(416usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x01a0usize) as _) } } #[doc = "Control register for the RISC-V 64-bit Machine-mode timer. This timer is only present in the Secure SIO, so is only accessible to an Arm core in Secure mode or a RISC-V core in Machine mode. Note whilst this timer follows the RISC-V privileged specification, it is equally usable by the Arm cores. The interrupts are routed to normal system-level interrupt lines as well as to the MIP.MTIP inputs on the RISC-V cores."] #[inline(always)] pub const fn mtime_ctrl(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(420usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x01a4usize) as _) } } #[doc = "Read/write access to the high half of RISC-V Machine-mode timer. This register is shared between both cores. If both cores write on the same cycle, core 1 takes precedence."] #[inline(always)] pub const fn mtime(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(432usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x01b0usize) as _) } } #[doc = "Read/write access to the high half of RISC-V Machine-mode timer. This register is shared between both cores. If both cores write on the same cycle, core 1 takes precedence."] #[inline(always)] pub const fn mtimeh(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(436usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x01b4usize) as _) } } #[doc = "Low half of RISC-V Machine-mode timer comparator. This register is core-local, i.e., each core gets a copy of this register, with the comparison result routed to its own interrupt line. The timer interrupt is asserted whenever MTIME is greater than or equal to MTIMECMP. This comparison is unsigned, and performed on the full 64-bit values."] #[inline(always)] pub const fn mtimecmp(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(440usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x01b8usize) as _) } } #[doc = "High half of RISC-V Machine-mode timer comparator. This register is core-local. The timer interrupt is asserted whenever MTIME is greater than or equal to MTIMECMP. This comparison is unsigned, and performed on the full 64-bit values."] #[inline(always)] pub const fn mtimecmph(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(444usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x01bcusize) as _) } } #[doc = "Control register for TMDS encoder."] #[inline(always)] pub const fn tmds_ctrl(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(448usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x01c0usize) as _) } } #[doc = "Write-only access to the TMDS colour data register."] #[inline(always)] pub const fn tmds_wdata(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(452usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x01c4usize) as _) } } #[doc = "Get the encoding of one pixel's worth of colour data, packed into a 32-bit value (3x10-bit symbols). The PEEK alias does not shift the colour register when read, but still advances the running DC balance state of each encoder. This is useful for pixel doubling."] #[inline(always)] pub const fn tmds_peek_single(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(456usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x01c8usize) as _) } } #[doc = "Get the encoding of one pixel's worth of colour data, packed into a 32-bit value. The packing is 5 chunks of 3 lanes times 2 bits (30 bits total). Each chunk contains two bits of a TMDS symbol per lane. This format is intended for shifting out with the HSTX peripheral on RP2350. The POP alias shifts the colour register when read, as well as advancing the running DC balance state of each encoder."] #[inline(always)] pub const fn tmds_pop_single(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(460usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x01ccusize) as _) } } #[doc = "Get lane 0 of the encoding of two pixels' worth of colour data. Two 10-bit TMDS symbols are packed at the bottom of a 32-bit word. The PEEK alias does not shift the colour register when read, but still advances the lane 0 DC balance state. This is useful if all 3 lanes' worth of encode are to be read at once, rather than processing the entire scanline for one lane before moving to the next lane."] #[inline(always)] pub const fn tmds_peek_double_l0(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(464usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x01d0usize) as _) } } #[doc = "Get lane 0 of the encoding of two pixels' worth of colour data. Two 10-bit TMDS symbols are packed at the bottom of a 32-bit word. The POP alias shifts the colour register when read, according to the values of PIX_SHIFT and PIX2_NOSHIFT."] #[inline(always)] pub const fn tmds_pop_double_l0(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(468usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x01d4usize) as _) } } #[doc = "Get lane 1 of the encoding of two pixels' worth of colour data. Two 10-bit TMDS symbols are packed at the bottom of a 32-bit word. The PEEK alias does not shift the colour register when read, but still advances the lane 1 DC balance state. This is useful if all 3 lanes' worth of encode are to be read at once, rather than processing the entire scanline for one lane before moving to the next lane."] #[inline(always)] pub const fn tmds_peek_double_l1(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(472usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x01d8usize) as _) } } #[doc = "Get lane 1 of the encoding of two pixels' worth of colour data. Two 10-bit TMDS symbols are packed at the bottom of a 32-bit word. The POP alias shifts the colour register when read, according to the values of PIX_SHIFT and PIX2_NOSHIFT."] #[inline(always)] pub const fn tmds_pop_double_l1(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(476usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x01dcusize) as _) } } #[doc = "Get lane 2 of the encoding of two pixels' worth of colour data. Two 10-bit TMDS symbols are packed at the bottom of a 32-bit word. The PEEK alias does not shift the colour register when read, but still advances the lane 2 DC balance state. This is useful if all 3 lanes' worth of encode are to be read at once, rather than processing the entire scanline for one lane before moving to the next lane."] #[inline(always)] pub const fn tmds_peek_double_l2(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(480usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x01e0usize) as _) } } #[doc = "Get lane 2 of the encoding of two pixels' worth of colour data. Two 10-bit TMDS symbols are packed at the bottom of a 32-bit word. The POP alias shifts the colour register when read, according to the values of PIX_SHIFT and PIX2_NOSHIFT."] #[inline(always)] pub const fn tmds_pop_double_l2(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(484usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x01e4usize) as _) } } } pub mod regs; diff --git a/src/rp235x/sio/vals.rs b/src/rp235x/sio/vals.rs index 1ffa3eac..1707ad5f 100644 --- a/src/rp235x/sio/vals.rs +++ b/src/rp235x/sio/vals.rs @@ -2,7 +2,7 @@ #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] pub enum PixShift { #[doc = "Do not shift the colour data register."] - _0 = 0, + _0 = 0x0, #[doc = "Shift the colour data register by 1 bit"] _1 = 0x01, #[doc = "Shift the colour data register by 2 bits"] diff --git a/src/rp235x/spi.rs b/src/rp235x/spi.rs index 0a4f215e..68bcf1ef 100644 --- a/src/rp235x/spi.rs +++ b/src/rp235x/spi.rs @@ -16,92 +16,92 @@ impl Spi { #[doc = "Control register 0, SSPCR0 on page 3-4"] #[inline(always)] pub const fn cr0(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(0usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x0usize) as _) } } #[doc = "Control register 1, SSPCR1 on page 3-5"] #[inline(always)] pub const fn cr1(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(4usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x04usize) as _) } } #[doc = "Data register, SSPDR on page 3-6"] #[inline(always)] pub const fn dr(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(8usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x08usize) as _) } } #[doc = "Status register, SSPSR on page 3-7"] #[inline(always)] pub const fn sr(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(12usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x0cusize) as _) } } #[doc = "Clock prescale register, SSPCPSR on page 3-8"] #[inline(always)] pub const fn cpsr(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(16usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x10usize) as _) } } #[doc = "Interrupt mask set or clear register, SSPIMSC on page 3-9"] #[inline(always)] pub const fn imsc(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(20usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x14usize) as _) } } #[doc = "Raw interrupt status register, SSPRIS on page 3-10"] #[inline(always)] pub const fn ris(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(24usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x18usize) as _) } } #[doc = "Masked interrupt status register, SSPMIS on page 3-11"] #[inline(always)] pub const fn mis(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(28usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x1cusize) as _) } } #[doc = "Interrupt clear register, SSPICR on page 3-11"] #[inline(always)] pub const fn icr(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(32usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x20usize) as _) } } #[doc = "DMA control register, SSPDMACR on page 3-12"] #[inline(always)] pub const fn dmacr(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(36usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x24usize) as _) } } #[doc = "Peripheral identification registers, SSPPeriphID0-3 on page 3-13"] #[inline(always)] pub const fn periphid0(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(4064usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x0fe0usize) as _) } } #[doc = "Peripheral identification registers, SSPPeriphID0-3 on page 3-13"] #[inline(always)] pub const fn periphid1(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(4068usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x0fe4usize) as _) } } #[doc = "Peripheral identification registers, SSPPeriphID0-3 on page 3-13"] #[inline(always)] pub const fn periphid2(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(4072usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x0fe8usize) as _) } } #[doc = "Peripheral identification registers, SSPPeriphID0-3 on page 3-13"] #[inline(always)] pub const fn periphid3(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(4076usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x0fecusize) as _) } } #[doc = "PrimeCell identification registers, SSPPCellID0-3 on page 3-16"] #[inline(always)] pub const fn pcellid0(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(4080usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x0ff0usize) as _) } } #[doc = "PrimeCell identification registers, SSPPCellID0-3 on page 3-16"] #[inline(always)] pub const fn pcellid1(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(4084usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x0ff4usize) as _) } } #[doc = "PrimeCell identification registers, SSPPCellID0-3 on page 3-16"] #[inline(always)] pub const fn pcellid2(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(4088usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x0ff8usize) as _) } } #[doc = "PrimeCell identification registers, SSPPCellID0-3 on page 3-16"] #[inline(always)] pub const fn pcellid3(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(4092usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x0ffcusize) as _) } } } pub mod regs; diff --git a/src/rp235x/syscfg.rs b/src/rp235x/syscfg.rs index e770429c..c79f6c66 100644 --- a/src/rp235x/syscfg.rs +++ b/src/rp235x/syscfg.rs @@ -17,34 +17,34 @@ impl Syscfg { #[doc = "Configuration for processors"] #[inline(always)] pub const fn proc_config(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(0usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x0usize) as _) } } #[doc = "For each bit, if 1, bypass the input synchronizer between that GPIO and the GPIO input register in the SIO. The input synchronizers should generally be unbypassed, to avoid injecting metastabilities into processors. If you're feeling brave, you can bypass to save two cycles of input latency. This register applies to GPIO 0...31."] #[inline(always)] pub const fn proc_in_sync_bypass(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(4usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x04usize) as _) } } #[doc = "For each bit, if 1, bypass the input synchronizer between that GPIO and the GPIO input register in the SIO. The input synchronizers should generally be unbypassed, to avoid injecting metastabilities into processors. If you're feeling brave, you can bypass to save two cycles of input latency. This register applies to GPIO 32...47. USB GPIO 56..57 QSPI GPIO 58..63"] #[inline(always)] pub const fn proc_in_sync_bypass_hi( self, ) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(8usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x08usize) as _) } } #[doc = "Directly control the chip SWD debug port"] #[inline(always)] pub const fn dbgforce(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(12usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x0cusize) as _) } } #[doc = "Control PD pins to memories. Set high to put memories to a low power state. In this state the memories will retain contents but not be accessible Use with caution"] #[inline(always)] pub const fn mempowerdown(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(16usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x10usize) as _) } } #[doc = "Auxiliary system control register"] #[inline(always)] pub const fn auxctrl(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(20usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x14usize) as _) } } } pub mod regs; diff --git a/src/rp235x/sysinfo.rs b/src/rp235x/sysinfo.rs index 5a7dff28..c42124e2 100644 --- a/src/rp235x/sysinfo.rs +++ b/src/rp235x/sysinfo.rs @@ -16,21 +16,21 @@ impl Sysinfo { #[doc = "JEDEC JEP-106 compliant chip identifier."] #[inline(always)] pub const fn chip_id(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(0usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x0usize) as _) } } #[inline(always)] pub const fn package_sel(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(4usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x04usize) as _) } } #[doc = "Platform register. Allows software to know what environment it is running in during pre-production development. Post-production, the PLATFORM is always ASIC, non-SIM."] #[inline(always)] pub const fn platform(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(8usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x08usize) as _) } } #[doc = "Git hash of the chip source. Used to identify chip version."] #[inline(always)] pub const fn gitref_rp2350(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(20usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x14usize) as _) } } } pub mod regs; diff --git a/src/rp235x/tbman.rs b/src/rp235x/tbman.rs index f3d65156..5eca987b 100644 --- a/src/rp235x/tbman.rs +++ b/src/rp235x/tbman.rs @@ -17,7 +17,7 @@ impl Tbman { #[doc = "Indicates the type of platform in use"] #[inline(always)] pub const fn platform(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(0usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x0usize) as _) } } } pub mod regs; diff --git a/src/rp235x/ticks.rs b/src/rp235x/ticks.rs index 98f86780..9cf6851c 100644 --- a/src/rp235x/ticks.rs +++ b/src/rp235x/ticks.rs @@ -16,84 +16,84 @@ impl Ticks { #[doc = "Controls the tick generator"] #[inline(always)] pub const fn proc0_ctrl(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(0usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x0usize) as _) } } #[inline(always)] pub const fn proc0_cycles(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(4usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x04usize) as _) } } #[inline(always)] pub const fn proc0_count(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(8usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x08usize) as _) } } #[doc = "Controls the tick generator"] #[inline(always)] pub const fn proc1_ctrl(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(12usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x0cusize) as _) } } #[inline(always)] pub const fn proc1_cycles(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(16usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x10usize) as _) } } #[inline(always)] pub const fn proc1_count(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(20usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x14usize) as _) } } #[doc = "Controls the tick generator"] #[inline(always)] pub const fn timer0_ctrl(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(24usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x18usize) as _) } } #[inline(always)] pub const fn timer0_cycles(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(28usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x1cusize) as _) } } #[inline(always)] pub const fn timer0_count(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(32usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x20usize) as _) } } #[doc = "Controls the tick generator"] #[inline(always)] pub const fn timer1_ctrl(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(36usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x24usize) as _) } } #[inline(always)] pub const fn timer1_cycles(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(40usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x28usize) as _) } } #[inline(always)] pub const fn timer1_count(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(44usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x2cusize) as _) } } #[doc = "Controls the tick generator"] #[inline(always)] pub const fn watchdog_ctrl(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(48usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x30usize) as _) } } #[inline(always)] pub const fn watchdog_cycles( self, ) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(52usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x34usize) as _) } } #[inline(always)] pub const fn watchdog_count( self, ) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(56usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x38usize) as _) } } #[doc = "Controls the tick generator"] #[inline(always)] pub const fn riscv_ctrl(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(60usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x3cusize) as _) } } #[inline(always)] pub const fn riscv_cycles(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(64usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x40usize) as _) } } #[inline(always)] pub const fn riscv_count(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(68usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x44usize) as _) } } } pub mod regs; diff --git a/src/rp235x/timer.rs b/src/rp235x/timer.rs index 2a795aca..aa740e65 100644 --- a/src/rp235x/timer.rs +++ b/src/rp235x/timer.rs @@ -17,83 +17,83 @@ impl Timer { #[doc = "Write to bits 63:32 of time always write timelw before timehw"] #[inline(always)] pub const fn timehw(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(0usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x0usize) as _) } } #[doc = "Write to bits 31:0 of time writes do not get copied to time until timehw is written"] #[inline(always)] pub const fn timelw(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(4usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x04usize) as _) } } #[doc = "Read from bits 63:32 of time always read timelr before timehr"] #[inline(always)] pub const fn timehr(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(8usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x08usize) as _) } } #[doc = "Read from bits 31:0 of time"] #[inline(always)] pub const fn timelr(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(12usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x0cusize) as _) } } #[doc = "Arm alarm 0, and configure the time it will fire. Once armed, the alarm fires when TIMER_ALARM0 == TIMELR. The alarm will disarm itself once it fires, and can be disarmed early using the ARMED status register."] #[inline(always)] pub const fn alarm(self, n: usize) -> crate::common::Reg { assert!(n < 4usize); - unsafe { crate::common::Reg::from_ptr(self.ptr.add(16usize + n * 4usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x10usize + n * 4usize) as _) } } #[doc = "Indicates the armed/disarmed status of each alarm. A write to the corresponding ALARMx register arms the alarm. Alarms automatically disarm upon firing, but writing ones here will disarm immediately without waiting to fire."] #[inline(always)] pub const fn armed(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(32usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x20usize) as _) } } #[doc = "Raw read from bits 63:32 of time (no side effects)"] #[inline(always)] pub const fn timerawh(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(36usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x24usize) as _) } } #[doc = "Raw read from bits 31:0 of time (no side effects)"] #[inline(always)] pub const fn timerawl(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(40usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x28usize) as _) } } #[doc = "Set bits high to enable pause when the corresponding debug ports are active"] #[inline(always)] pub const fn dbgpause(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(44usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x2cusize) as _) } } #[doc = "Set high to pause the timer"] #[inline(always)] pub const fn pause(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(48usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x30usize) as _) } } #[doc = "Set locked bit to disable write access to timer Once set, cannot be cleared (without a reset)"] #[inline(always)] pub const fn locked(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(52usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x34usize) as _) } } #[doc = "Selects the source for the timer. Defaults to the normal tick configured in the ticks block (typically configured to 1 microsecond). Writing to 1 will ignore the tick and count clk_sys cycles instead."] #[inline(always)] pub const fn source(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(56usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x38usize) as _) } } #[doc = "Raw Interrupts"] #[inline(always)] pub const fn intr(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(60usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x3cusize) as _) } } #[doc = "Interrupt Enable"] #[inline(always)] pub const fn inte(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(64usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x40usize) as _) } } #[doc = "Interrupt Force"] #[inline(always)] pub const fn intf(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(68usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x44usize) as _) } } #[doc = "Interrupt status after masking & forcing"] #[inline(always)] pub const fn ints(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(72usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x48usize) as _) } } } pub mod regs; diff --git a/src/rp235x/timer/vals.rs b/src/rp235x/timer/vals.rs index 0c506c29..beff7839 100644 --- a/src/rp235x/timer/vals.rs +++ b/src/rp235x/timer/vals.rs @@ -1,7 +1,7 @@ #[repr(u8)] #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] pub enum ClkSys { - TICK = 0, + TICK = 0x0, CLK_SYS = 0x01, } impl ClkSys { diff --git a/src/rp235x/trng.rs b/src/rp235x/trng.rs index 08b8ce85..37da8f88 100644 --- a/src/rp235x/trng.rs +++ b/src/rp235x/trng.rs @@ -17,133 +17,133 @@ impl Trng { #[doc = "Interrupt masking."] #[inline(always)] pub const fn rng_imr(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(256usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x0100usize) as _) } } #[doc = "RNG status register. If corresponding RNG_IMR bit is unmasked, an interrupt will be generated."] #[inline(always)] pub const fn rng_isr(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(260usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x0104usize) as _) } } #[doc = "Interrupt/status bit clear Register."] #[inline(always)] pub const fn rng_icr(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(264usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x0108usize) as _) } } #[doc = "Selecting the inverter-chain length."] #[inline(always)] pub const fn trng_config(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(268usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x010cusize) as _) } } #[doc = "192 bit collection indication."] #[inline(always)] pub const fn trng_valid(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(272usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x0110usize) as _) } } #[doc = "RNG collected bits."] #[inline(always)] pub const fn ehr_data0(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(276usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x0114usize) as _) } } #[doc = "RNG collected bits."] #[inline(always)] pub const fn ehr_data1(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(280usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x0118usize) as _) } } #[doc = "RNG collected bits."] #[inline(always)] pub const fn ehr_data2(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(284usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x011cusize) as _) } } #[doc = "RNG collected bits."] #[inline(always)] pub const fn ehr_data3(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(288usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x0120usize) as _) } } #[doc = "RNG collected bits."] #[inline(always)] pub const fn ehr_data4(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(292usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x0124usize) as _) } } #[doc = "RNG collected bits."] #[inline(always)] pub const fn ehr_data5(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(296usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x0128usize) as _) } } #[doc = "Enable signal for the random source."] #[inline(always)] pub const fn rnd_source_enable( self, ) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(300usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x012cusize) as _) } } #[doc = "Counts clocks between sampling of random bit."] #[inline(always)] pub const fn sample_cnt1(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(304usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x0130usize) as _) } } #[doc = "Statistic about Autocorrelation test activations."] #[inline(always)] pub const fn autocorr_statistic( self, ) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(308usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x0134usize) as _) } } #[doc = "Debug register."] #[inline(always)] pub const fn trng_debug_control( self, ) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(312usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x0138usize) as _) } } #[doc = "Generate internal SW reset within the RNG block."] #[inline(always)] pub const fn trng_sw_reset(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(320usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x0140usize) as _) } } #[doc = "Enable the RNG debug mode"] #[inline(always)] pub const fn rng_debug_en_input( self, ) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(436usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x01b4usize) as _) } } #[doc = "RNG Busy indication."] #[inline(always)] pub const fn trng_busy(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(440usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x01b8usize) as _) } } #[doc = "Reset the counter of collected bits in the RNG."] #[inline(always)] pub const fn rst_bits_counter( self, ) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(444usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x01bcusize) as _) } } #[doc = "Displays the version settings of the TRNG."] #[inline(always)] pub const fn rng_version(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(448usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x01c0usize) as _) } } #[doc = "Collected BIST results."] #[inline(always)] pub const fn rng_bist_cntr_0( self, ) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(480usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x01e0usize) as _) } } #[doc = "Collected BIST results."] #[inline(always)] pub const fn rng_bist_cntr_1( self, ) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(484usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x01e4usize) as _) } } #[doc = "Collected BIST results."] #[inline(always)] pub const fn rng_bist_cntr_2( self, ) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(488usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x01e8usize) as _) } } } pub mod regs; diff --git a/src/rp235x/uart.rs b/src/rp235x/uart.rs index 078cce38..d64805b0 100644 --- a/src/rp235x/uart.rs +++ b/src/rp235x/uart.rs @@ -16,112 +16,112 @@ impl Uart { #[doc = "Data Register, UARTDR"] #[inline(always)] pub const fn uartdr(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(0usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x0usize) as _) } } #[doc = "Receive Status Register/Error Clear Register, UARTRSR/UARTECR"] #[inline(always)] pub const fn uartrsr(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(4usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x04usize) as _) } } #[doc = "Flag Register, UARTFR"] #[inline(always)] pub const fn uartfr(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(24usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x18usize) as _) } } #[doc = "IrDA Low-Power Counter Register, UARTILPR"] #[inline(always)] pub const fn uartilpr(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(32usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x20usize) as _) } } #[doc = "Integer Baud Rate Register, UARTIBRD"] #[inline(always)] pub const fn uartibrd(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(36usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x24usize) as _) } } #[doc = "Fractional Baud Rate Register, UARTFBRD"] #[inline(always)] pub const fn uartfbrd(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(40usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x28usize) as _) } } #[doc = "Line Control Register, UARTLCR_H"] #[inline(always)] pub const fn uartlcr_h(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(44usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x2cusize) as _) } } #[doc = "Control Register, UARTCR"] #[inline(always)] pub const fn uartcr(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(48usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x30usize) as _) } } #[doc = "Interrupt FIFO Level Select Register, UARTIFLS"] #[inline(always)] pub const fn uartifls(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(52usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x34usize) as _) } } #[doc = "Interrupt Mask Set/Clear Register, UARTIMSC"] #[inline(always)] pub const fn uartimsc(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(56usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x38usize) as _) } } #[doc = "Raw Interrupt Status Register, UARTRIS"] #[inline(always)] pub const fn uartris(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(60usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x3cusize) as _) } } #[doc = "Masked Interrupt Status Register, UARTMIS"] #[inline(always)] pub const fn uartmis(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(64usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x40usize) as _) } } #[doc = "Interrupt Clear Register, UARTICR"] #[inline(always)] pub const fn uarticr(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(68usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x44usize) as _) } } #[doc = "DMA Control Register, UARTDMACR"] #[inline(always)] pub const fn uartdmacr(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(72usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x48usize) as _) } } #[doc = "UARTPeriphID0 Register"] #[inline(always)] pub const fn uartperiphid0(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(4064usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x0fe0usize) as _) } } #[doc = "UARTPeriphID1 Register"] #[inline(always)] pub const fn uartperiphid1(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(4068usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x0fe4usize) as _) } } #[doc = "UARTPeriphID2 Register"] #[inline(always)] pub const fn uartperiphid2(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(4072usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x0fe8usize) as _) } } #[doc = "UARTPeriphID3 Register"] #[inline(always)] pub const fn uartperiphid3(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(4076usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x0fecusize) as _) } } #[doc = "UARTPCellID0 Register"] #[inline(always)] pub const fn uartpcellid0(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(4080usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x0ff0usize) as _) } } #[doc = "UARTPCellID1 Register"] #[inline(always)] pub const fn uartpcellid1(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(4084usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x0ff4usize) as _) } } #[doc = "UARTPCellID2 Register"] #[inline(always)] pub const fn uartpcellid2(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(4088usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x0ff8usize) as _) } } #[doc = "UARTPCellID3 Register"] #[inline(always)] pub const fn uartpcellid3(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(4092usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x0ffcusize) as _) } } } pub mod regs; diff --git a/src/rp235x/usb.rs b/src/rp235x/usb.rs index 388e7a5f..1ee9ced2 100644 --- a/src/rp235x/usb.rs +++ b/src/rp235x/usb.rs @@ -17,7 +17,7 @@ impl Usb { #[doc = "Device address and endpoint control"] #[inline(always)] pub const fn addr_endp(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(0usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x0usize) as _) } } #[doc = "Interrupt endpoint 1. Only valid for HOST mode."] #[inline(always)] @@ -26,165 +26,165 @@ impl Usb { n: usize, ) -> crate::common::Reg { assert!(n < 15usize); - unsafe { crate::common::Reg::from_ptr(self.ptr.add(4usize + n * 4usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x04usize + n * 4usize) as _) } } #[doc = "Main control register"] #[inline(always)] pub const fn main_ctrl(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(64usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x40usize) as _) } } #[doc = "Set the SOF (Start of Frame) frame number in the host controller. The SOF packet is sent every 1ms and the host will increment the frame number by 1 each time."] #[inline(always)] pub const fn sof_wr(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(68usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x44usize) as _) } } #[doc = "Read the last SOF (Start of Frame) frame number seen. In device mode the last SOF received from the host. In host mode the last SOF sent by the host."] #[inline(always)] pub const fn sof_rd(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(72usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x48usize) as _) } } #[doc = "SIE control register"] #[inline(always)] pub const fn sie_ctrl(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(76usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x4cusize) as _) } } #[doc = "SIE status register"] #[inline(always)] pub const fn sie_status(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(80usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x50usize) as _) } } #[doc = "interrupt endpoint control register"] #[inline(always)] pub const fn int_ep_ctrl(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(84usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x54usize) as _) } } #[doc = "Buffer status register. A bit set here indicates that a buffer has completed on the endpoint (if the buffer interrupt is enabled). It is possible for 2 buffers to be completed, so clearing the buffer status bit may instantly re set it on the next clock cycle."] #[inline(always)] pub const fn buff_status(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(88usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x58usize) as _) } } #[doc = "Which of the double buffers should be handled. Only valid if using an interrupt per buffer (i.e. not per 2 buffers). Not valid for host interrupt endpoint polling because they are only single buffered."] #[inline(always)] pub const fn buff_cpu_should_handle( self, ) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(92usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x5cusize) as _) } } #[doc = "Device only: Can be set to ignore the buffer control register for this endpoint in case you would like to revoke a buffer. A NAK will be sent for every access to the endpoint until this bit is cleared. A corresponding bit in `EP_ABORT_DONE` is set when it is safe to modify the buffer control register."] #[inline(always)] pub const fn ep_abort(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(96usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x60usize) as _) } } #[doc = "Device only: Used in conjunction with `EP_ABORT`. Set once an endpoint is idle so the programmer knows it is safe to modify the buffer control register."] #[inline(always)] pub const fn ep_abort_done(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(100usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x64usize) as _) } } #[doc = "Device: this bit must be set in conjunction with the `STALL` bit in the buffer control register to send a STALL on EP0. The device controller clears these bits when a SETUP packet is received because the USB spec requires that a STALL condition is cleared when a SETUP packet is received."] #[inline(always)] pub const fn ep_stall_arm(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(104usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x68usize) as _) } } #[doc = "Used by the host controller. Sets the wait time in microseconds before trying again if the device replies with a NAK."] #[inline(always)] pub const fn nak_poll(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(108usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x6cusize) as _) } } #[doc = "Device: bits are set when the `IRQ_ON_NAK` or `IRQ_ON_STALL` bits are set. For EP0 this comes from `SIE_CTRL`. For all other endpoints it comes from the endpoint control register."] #[inline(always)] pub const fn ep_status_stall_nak( self, ) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(112usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x70usize) as _) } } #[doc = "Where to connect the USB controller. Should be to_phy by default."] #[inline(always)] pub const fn usb_muxing(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(116usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x74usize) as _) } } #[doc = "Overrides for the power signals in the event that the VBUS signals are not hooked up to GPIO. Set the value of the override and then the override enable to switch over to the override value."] #[inline(always)] pub const fn usb_pwr(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(120usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x78usize) as _) } } #[doc = "This register allows for direct control of the USB phy. Use in conjunction with usbphy_direct_override register to enable each override bit."] #[inline(always)] pub const fn usbphy_direct(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(124usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x7cusize) as _) } } #[doc = "Override enable for each control in usbphy_direct"] #[inline(always)] pub const fn usbphy_direct_override( self, ) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(128usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x80usize) as _) } } #[doc = "Used to adjust trim values of USB phy pull down resistors."] #[inline(always)] pub const fn usbphy_trim(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(132usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x84usize) as _) } } #[doc = "Used for debug only."] #[inline(always)] pub const fn linestate_tuning( self, ) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(136usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x88usize) as _) } } #[doc = "Raw Interrupts"] #[inline(always)] pub const fn intr(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(140usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x8cusize) as _) } } #[doc = "Interrupt Enable"] #[inline(always)] pub const fn inte(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(144usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x90usize) as _) } } #[doc = "Interrupt Force"] #[inline(always)] pub const fn intf(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(148usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x94usize) as _) } } #[doc = "Interrupt status after masking & forcing"] #[inline(always)] pub const fn ints(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(152usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x98usize) as _) } } #[doc = "Device only. Raw value of free-running PHY clock counter @48MHz. Used to calculate time between SOF events."] #[inline(always)] pub const fn sof_timestamp_raw( self, ) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(256usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x0100usize) as _) } } #[doc = "Device only. Value of free-running PHY clock counter @48MHz when last SOF event occurred."] #[inline(always)] pub const fn sof_timestamp_last( self, ) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(260usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x0104usize) as _) } } #[inline(always)] pub const fn sm_state(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(264usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x0108usize) as _) } } #[doc = "TX error count for each endpoint. Write to each field to reset the counter to 0."] #[inline(always)] pub const fn ep_tx_error(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(268usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x010cusize) as _) } } #[doc = "RX error count for each endpoint. Write to each field to reset the counter to 0."] #[inline(always)] pub const fn ep_rx_error(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(272usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x0110usize) as _) } } #[doc = "Watchdog that forces the device state machine to idle and raises an interrupt if the device stays in a state that isn't idle for the configured limit. The counter is reset on every state transition. Set limit while enable is low and then set the enable."] #[inline(always)] pub const fn dev_sm_watchdog( self, ) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(276usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x0114usize) as _) } } } pub mod regs; diff --git a/src/rp235x/usb/regs.rs b/src/rp235x/usb/regs.rs index f24c64a9..31bb4e0d 100644 --- a/src/rp235x/usb/regs.rs +++ b/src/rp235x/usb/regs.rs @@ -32,7 +32,7 @@ impl Default for AddrEndp { AddrEndp(0) } } -#[doc = "Interrupt endpoint 15. Only valid for HOST mode."] +#[doc = "Interrupt endpoint 8. Only valid for HOST mode."] #[repr(transparent)] #[derive(Copy, Clone, Eq, PartialEq)] pub struct AddrEndpX(pub u32); @@ -814,7 +814,7 @@ impl Default for EpTxError { EpTxError(0) } } -#[doc = "Raw Interrupts"] +#[doc = "Interrupt Enable"] #[repr(transparent)] #[derive(Copy, Clone, Eq, PartialEq)] pub struct Int(pub u32); diff --git a/src/rp235x/usb_dpram.rs b/src/rp235x/usb_dpram.rs index ec3eec2a..ca45a368 100644 --- a/src/rp235x/usb_dpram.rs +++ b/src/rp235x/usb_dpram.rs @@ -19,14 +19,14 @@ impl UsbDpram { pub const fn setup_packet_low( self, ) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(0usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x0usize) as _) } } #[doc = "Bytes 4-7 of the setup packet from the host."] #[inline(always)] pub const fn setup_packet_high( self, ) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(4usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x04usize) as _) } } #[inline(always)] pub const fn ep_in_control( @@ -34,7 +34,7 @@ impl UsbDpram { n: usize, ) -> crate::common::Reg { assert!(n < 15usize); - unsafe { crate::common::Reg::from_ptr(self.ptr.add(8usize + n * 8usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x08usize + n * 8usize) as _) } } #[inline(always)] pub const fn ep_out_control( @@ -42,7 +42,7 @@ impl UsbDpram { n: usize, ) -> crate::common::Reg { assert!(n < 15usize); - unsafe { crate::common::Reg::from_ptr(self.ptr.add(12usize + n * 8usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x0cusize + n * 8usize) as _) } } #[doc = "Buffer control for both buffers of an endpoint. Fields ending in a _1 are for buffer 1. Fields ending in a _0 are for buffer 0. Buffer 1 controls are only valid if the endpoint is in double buffered mode."] #[inline(always)] @@ -51,7 +51,7 @@ impl UsbDpram { n: usize, ) -> crate::common::Reg { assert!(n < 16usize); - unsafe { crate::common::Reg::from_ptr(self.ptr.add(128usize + n * 8usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x80usize + n * 8usize) as _) } } #[doc = "Buffer control for both buffers of an endpoint. Fields ending in a _1 are for buffer 1. Fields ending in a _0 are for buffer 0. Buffer 1 controls are only valid if the endpoint is in double buffered mode."] #[inline(always)] @@ -60,7 +60,7 @@ impl UsbDpram { n: usize, ) -> crate::common::Reg { assert!(n < 16usize); - unsafe { crate::common::Reg::from_ptr(self.ptr.add(132usize + n * 8usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x84usize + n * 8usize) as _) } } } pub mod regs; diff --git a/src/rp235x/usb_dpram/vals.rs b/src/rp235x/usb_dpram/vals.rs index d0e39228..c1e350b1 100644 --- a/src/rp235x/usb_dpram/vals.rs +++ b/src/rp235x/usb_dpram/vals.rs @@ -1,7 +1,7 @@ #[repr(u8)] #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] pub enum EpBufferControlDoubleBufferIsoOffset { - _128 = 0, + _128 = 0x0, _256 = 0x01, _512 = 0x02, _1024 = 0x03, @@ -31,7 +31,7 @@ impl From for u8 { #[repr(u8)] #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] pub enum EpControlEndpointType { - CONTROL = 0, + CONTROL = 0x0, ISOCHRONOUS = 0x01, BULK = 0x02, INTERRUPT = 0x03, diff --git a/src/rp235x/watchdog.rs b/src/rp235x/watchdog.rs index 4c60649e..e35bb4b9 100644 --- a/src/rp235x/watchdog.rs +++ b/src/rp235x/watchdog.rs @@ -16,57 +16,57 @@ impl Watchdog { #[doc = "Watchdog control The rst_wdsel register determines which subsystems are reset when the watchdog is triggered. The watchdog can be triggered in software."] #[inline(always)] pub const fn ctrl(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(0usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x0usize) as _) } } #[doc = "Load the watchdog timer. The maximum setting is 0xffffff which corresponds to approximately 16 seconds."] #[inline(always)] pub const fn load(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(4usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x04usize) as _) } } #[doc = "Logs the reason for the last reset. Both bits are zero for the case of a hardware reset. Additionally, as of RP2350, a debugger warm reset of either core (SYSRESETREQ or hartreset) will also clear the watchdog reason register, so that software loaded under the debugger following a watchdog timeout will not continue to see the timeout condition."] #[inline(always)] pub const fn reason(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(8usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x08usize) as _) } } #[doc = "Scratch register. Information persists through soft reset of the chip."] #[inline(always)] pub const fn scratch0(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(12usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x0cusize) as _) } } #[doc = "Scratch register. Information persists through soft reset of the chip."] #[inline(always)] pub const fn scratch1(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(16usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x10usize) as _) } } #[doc = "Scratch register. Information persists through soft reset of the chip."] #[inline(always)] pub const fn scratch2(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(20usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x14usize) as _) } } #[doc = "Scratch register. Information persists through soft reset of the chip."] #[inline(always)] pub const fn scratch3(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(24usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x18usize) as _) } } #[doc = "Scratch register. Information persists through soft reset of the chip."] #[inline(always)] pub const fn scratch4(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(28usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x1cusize) as _) } } #[doc = "Scratch register. Information persists through soft reset of the chip."] #[inline(always)] pub const fn scratch5(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(32usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x20usize) as _) } } #[doc = "Scratch register. Information persists through soft reset of the chip."] #[inline(always)] pub const fn scratch6(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(36usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x24usize) as _) } } #[doc = "Scratch register. Information persists through soft reset of the chip."] #[inline(always)] pub const fn scratch7(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(40usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x28usize) as _) } } } pub mod regs; diff --git a/src/rp235x/xip_aux.rs b/src/rp235x/xip_aux.rs index e81beae5..e0db2678 100644 --- a/src/rp235x/xip_aux.rs +++ b/src/rp235x/xip_aux.rs @@ -17,17 +17,17 @@ impl XipAux { #[doc = "Read the XIP stream FIFO (fast bus access to XIP_CTRL_STREAM_FIFO)"] #[inline(always)] pub const fn stream(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(0usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x0usize) as _) } } #[doc = "Write to the QMI direct-mode TX FIFO (fast bus access to QMI_DIRECT_TX)"] #[inline(always)] pub const fn qmi_direct_tx(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(4usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x04usize) as _) } } #[doc = "Read from the QMI direct-mode RX FIFO (fast bus access to QMI_DIRECT_RX)"] #[inline(always)] pub const fn qmi_direct_rx(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(8usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x08usize) as _) } } } pub mod regs; diff --git a/src/rp235x/xip_aux/vals.rs b/src/rp235x/xip_aux/vals.rs index d49136f2..315c0347 100644 --- a/src/rp235x/xip_aux/vals.rs +++ b/src/rp235x/xip_aux/vals.rs @@ -2,7 +2,7 @@ #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] pub enum Iwidth { #[doc = "Single width"] - S = 0, + S = 0x0, #[doc = "Dual width"] D = 0x01, #[doc = "Quad width"] diff --git a/src/rp235x/xip_ctrl.rs b/src/rp235x/xip_ctrl.rs index bce3a5b3..584b4438 100644 --- a/src/rp235x/xip_ctrl.rs +++ b/src/rp235x/xip_ctrl.rs @@ -17,36 +17,36 @@ impl XipCtrl { #[doc = "Cache control register. Read-only from a Non-secure context."] #[inline(always)] pub const fn ctrl(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(0usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x0usize) as _) } } #[inline(always)] pub const fn stat(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(8usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x08usize) as _) } } #[doc = "Cache Hit counter"] #[inline(always)] pub const fn ctr_hit(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(12usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x0cusize) as _) } } #[doc = "Cache Access counter"] #[inline(always)] pub const fn ctr_acc(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(16usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x10usize) as _) } } #[doc = "FIFO stream address"] #[inline(always)] pub const fn stream_addr(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(20usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x14usize) as _) } } #[doc = "FIFO stream control"] #[inline(always)] pub const fn stream_ctr(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(24usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x18usize) as _) } } #[doc = "FIFO stream data"] #[inline(always)] pub const fn stream_fifo(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(28usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x1cusize) as _) } } } pub mod regs; diff --git a/src/rp235x/xosc.rs b/src/rp235x/xosc.rs index 95054801..f207bcae 100644 --- a/src/rp235x/xosc.rs +++ b/src/rp235x/xosc.rs @@ -17,27 +17,27 @@ impl Xosc { #[doc = "Crystal Oscillator Control"] #[inline(always)] pub const fn ctrl(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(0usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x0usize) as _) } } #[doc = "Crystal Oscillator Status"] #[inline(always)] pub const fn status(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(4usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x04usize) as _) } } #[doc = "Crystal Oscillator pause control"] #[inline(always)] pub const fn dormant(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(8usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x08usize) as _) } } #[doc = "Controls the startup delay"] #[inline(always)] pub const fn startup(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(12usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x0cusize) as _) } } #[doc = "A down counter running at the xosc frequency which counts to zero and stops. Can be used for short software pauses when setting up time sensitive hardware. To start the counter, write a non-zero value. Reads will return 1 while the count is running and 0 when it has finished. Minimum count value is 4. Count values <4 will be treated as count value =4. Note that synchronisation to the register clock domain costs 2 register clock cycles and the counter cannot compensate for that."] #[inline(always)] pub const fn count(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(16usize) as _) } + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x10usize) as _) } } } pub mod regs; diff --git a/src/rp235x/xosc/vals.rs b/src/rp235x/xosc/vals.rs index 06a57082..ae7dc224 100644 --- a/src/rp235x/xosc/vals.rs +++ b/src/rp235x/xosc/vals.rs @@ -84,7 +84,7 @@ impl From for u16 { #[repr(u8)] #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] pub enum StatusFreqRange { - _1_15MHZ = 0, + _1_15MHZ = 0x0, _10_30MHZ = 0x01, _25_60MHZ = 0x02, _40_100MHZ = 0x03, diff --git a/svd/rp2040.yaml b/svd/rp2040.yaml index 30ae58e9..f791ffbf 100644 --- a/svd/rp2040.yaml +++ b/svd/rp2040.yaml @@ -7,14 +7,22 @@ transforms: useless: true # =========== DMA + - !DeleteFieldsets + from: dma::regs::Int[refs]\d* - !MergeEnums from: dma::vals::Ch\d+CtrlTrigTreqSel to: dma::vals::TreqSel - !MergeEnums from: dma::vals::Ch\d+CtrlTrigDataSize to: dma::vals::DataSize + - !MergeEnums + from: dma::vals::Ch\d+TransCountMode + to: dma::vals::TransCountMode - !DeleteEnums from: dma::vals::Ch\d+CtrlTrigRingSize + - !MergeFieldsets + from: dma::regs::Ch\d+TransCount + to: dma::regs::ChTransCount - !MergeFieldsets from: dma::regs::Timer\d+ to: dma::regs::Timer @@ -42,6 +50,10 @@ transforms: blocks: dma::Dma from: timer\d+ to: timer + - !MakeRegisterArray + blocks: dma::Dma + from: (int[refs])\d* + to: $1 # =========== TIMER - !MakeRegisterArray diff --git a/svd/rp235x.yaml b/svd/rp235x.yaml index 25370295..6fd543e0 100644 --- a/svd/rp235x.yaml +++ b/svd/rp235x.yaml @@ -7,14 +7,22 @@ transforms: useless: true # =========== DMA + - !DeleteFieldsets + from: dma::regs::Int[refs]\d* - !MergeEnums from: dma::vals::Ch\d+CtrlTrigTreqSel to: dma::vals::TreqSel - !MergeEnums from: dma::vals::Ch\d+CtrlTrigDataSize to: dma::vals::DataSize + - !MergeEnums + from: dma::vals::Ch\d+TransCountMode + to: dma::vals::TransCountMode - !DeleteEnums from: dma::vals::Ch\d+CtrlTrigRingSize + - !MergeFieldsets + from: dma::regs::Ch\d+TransCount + to: dma::regs::ChTransCount - !MergeFieldsets from: dma::regs::Timer\d+ to: dma::regs::Timer @@ -42,25 +50,46 @@ transforms: blocks: dma::Dma from: timer\d+ to: timer - - # =========== TIMER - !MakeRegisterArray - blocks: timer0::Timer0 - from: alarm\d+ - to: alarm + blocks: dma::Dma + from: (int[refs])\d* + to: $1 - !MergeFieldsets - from: timer0::regs::Int[efrs] - to: timer0::regs::Int + from: dma::regs::Seccfg(Irq|Ch)\d+ + to: dma::regs::Seccfg$1 + - !MakeRegisterArray + blocks: dma::Dma + from: seccfg_(ch|irq)\d* + to: seccfg_$1 + - !DeleteFieldsets + from: dma::regs::Mpu[LB]ar\d+ + - !MakeRegisterArray + blocks: dma::Dma + from: (mpu_[lb]ar)\d+ + to: $1 - !MakeFieldArray - fieldsets: timer0::regs::Int - from: alarm_\d+ - to: alarm + fieldsets: dma::regs::SeccfgMisc + from: timer\d+_(.+) + to: timer_$1 + + # =========== TIMER - !Rename from: timer0::(.*) to: timer::$1 - !Rename from: timer::Timer0 to: timer::Timer + - !MakeRegisterArray + blocks: timer::Timer + from: alarm\d+ + to: alarm + - !MergeFieldsets + from: timer::regs::Int[efrs] + to: timer::regs::Int + - !MakeFieldArray + fieldsets: timer::regs::Int + from: alarm_\d+ + to: alarm # =========== UART - !Rename @@ -147,6 +176,20 @@ transforms: blocks: pio::Pio from: irq\d+ to: irqs + - !MakeBlock + blocks: pio::Pio + from: rxf(\d+)_putget(\d+) + to_outer: rxf${1}_putget + to_inner: putget$2 + to_block: pio::RxfPutGet + - !MakeRegisterArray + blocks: pio::Pio + from: rxf\d+_putget + to: rxf_putget + - !MakeRegisterArray + blocks: pio::RxfPutGet + from: putget\d+ + to: putget # ========= SIO - !MakeBlock @@ -244,6 +287,12 @@ transforms: main: io::Io to: io::Io check: NoCheck + - !DeleteFieldsets + from: io::regs::Irqsummary.* + - !MakeRegisterArray + blocks: io::Io + from: (irqsummary_.*)[01] + to: $1 # =========== PADS - !Rename @@ -387,6 +436,153 @@ transforms: from: ch\d+ to: ch + # =========== ACCESSCTRL + - !MergeFieldsets + from: accessctrl::regs::(Adc\d+|Busctrl|Clocks|CoresightPeriph|CoresightTrace|Dma|Hstx|I2c\d+|IoBank\d+|Otp|PadsBank\d+|PadsQspi|Pio\d+|PllSys|PllUsb|Powman|Pwm|Resets|Rom|Rosc|Rsm|Sha256|Spi\d+|Sram\d+|Syscfg|Sysinfo|Tbman|Ticks|Timer\d+|Trng|Uart\d+|Usbctrl|Watchdog|XipAux|XipCtrl|XipMain|XipQmi|Xosc) + to: accessctrl::regs::Access + - !MakeRegisterArray + blocks: accessctrl::Accessctrl + from: sram\d+ + to: sram + + # =========== BOOTRAM + - !MakeRegisterArray + blocks: bootram::Bootram + from: bootlock\d+ + to: bootlock + + # =========== HSTX + - !MergeFieldsets + from: hstx_ctrl::regs::Bit\d+ + to: hstx_ctrl::regs::Bit + - !MakeRegisterArray + blocks: hstx_ctrl::HstxCtrl + from: bit\d+ + to: bit + + # =========== OTP + - !MergeEnums + from: otp::vals::SwLock\d+(.*) + to: otp::vals::SwLock$1 + - !MergeFieldsets + from: otp::regs::SwLock\d+ + to: otp::regs::SwLock + - !MergeFieldsets + from: otp::regs::Int[erfs] + to: otp::regs::Int + - !MakeRegisterArray + blocks: otp::Otp + from: sw_lock\d+ + to: sw_lock + - !MakeRegisterArray + blocks: otp::Otp + from: crt_key_w\d+ + to: crt_key + - !MakeRegisterArray + blocks: otp::Otp + from: (sbpi_[rw]data)_\d+ + to: $1 + + # =========== OTP_DATA_RAW + - !MergeEnums + from: otp_data_raw::vals::Page\d+Lock1Lock.* + to: otp_data_raw::vals::PageLock + - !MergeEnums + from: otp_data_raw::vals::Page\d+Lock0NoKeyState + to: otp_data_raw::vals::PageLockNoKeyState + - !MergeFieldsets + from: otp_data_raw::regs::Page\d+Lock0 + to: otp_data_raw::regs::PageLock0 + main: otp_data_raw::regs::Page63Lock0 + check: NoCheck + - !MergeFieldsets + from: otp_data_raw::regs::Page\d+Lock1 + to: otp_data_raw::regs::PageLock1 + main: otp_data_raw::regs::Page63Lock1 + check: NoCheck + - !MergeFieldsets + from: otp_data_raw::regs::Key\d+Valid + to: otp_data_raw::regs::KeyValid + - !MakeRegisterArray + blocks: otp_data_raw::OtpDataRaw + from: key\d+_valid + to: key_valid + - !DeleteFieldsets + from: otp_data_raw::regs::(BootKey|Key)\d+ + - !MakeBlock + blocks: otp_data_raw::OtpDataRaw + from: page(\d+)_lock(\d+) + to_outer: page${1}_lock + to_inner: lock$2 + to_block: otp_data_raw::PageLock + - !MakeRegisterArray + blocks: otp_data_raw::OtpDataRaw + from: page\d+_lock + to: page_lock + - !MakeBlock + blocks: otp_data_raw::OtpDataRaw + from: key(\d+)_(\d+) + to_outer: key${1} + to_inner: part$2 + to_block: otp_data_raw::Key + - !MakeRegisterArray + blocks: otp_data_raw::OtpDataRaw + from: key\d+ + to: key + - !MakeBlock + blocks: otp_data_raw::OtpDataRaw + from: bootkey(\d+)_(\d+) + to_outer: bootkey${1} + to_inner: part$2 + to_block: otp_data_raw::BootKey + - !MakeRegisterArray + blocks: otp_data_raw::OtpDataRaw + from: bootkey\d+ + to: bootkey + + + # =========== QMI + - !MergeEnums + from: qmi::vals::M\d+([RW]fmt|Timing)(.*) + to: qmi::vals::$2 + - !MergeFieldsets + from: qmi::regs::Atrans\d+ + to: qmi::regs::Atrans + - !MergeFieldsets + from: qmi::regs::M\d+(.*) + to: qmi::regs::$1 + - !MakeRegisterArray + blocks: qmi::Qmi + from: atrans\d+ + to: atrans + - !MakeBlock + blocks: qmi::Qmi + from: m(\d+)_(.*) + to_outer: mem${1} + to_inner: $2 + to_block: qmi::Mem + - !MakeRegisterArray + blocks: qmi::Qmi + from: mem\d+ + to: mem + + # =========== POWMAN + - !MergeEnums + from: powman::vals::Pwrup\d+(.*) + to: powman::vals::$1 + - !MergeFieldsets + from: powman::regs::ExtCtrl\d+ + to: powman::regs::ExtCtrl + - !MergeFieldsets + from: powman::regs::Pwrup\d+ + to: powman::regs::Pwrup + - !MergeFieldsets + from: powman::regs::Int[fers] + to: powman::regs::Int + - !MakeRegisterArray + blocks: powman::Powman + from: (pwrup|scratch|boot)\d+ + to: $1 # =========== Misc - !MergeEnums @@ -408,5 +604,6 @@ transforms: from: swi_irq::.* - !Delete from: pads_qspi::.* - - !FixRegisterBitSizes # There's some 24-bit regs. This changes them to 32-bit with a 24-bit field. + - !FixRegisterBitSizes # There's some 24-bit regs. This changes them to 32-bit. + create_fieldsets: false - !Sanitize