SPI Master additional features

[Dominaezzz]

The SPI Master is currently not exposing some hardware features.
I'm listing them here to begin with rather than create a barrage of issues.

• Configurable Segmented Transfers (All chips except the base ESP32 support this. It allows to setup multiple transfers at once, rather then send them one by one with the CPU).
• Expose SPI App interrupts (ESP32-S3/C2/C3/C6/H2 SPI supports these things called "app interrupts" which behave just like SoftwareInterrupts, they are very handy for implementing an interrupt based queue)
• Expose the extra LCD features that the S2 has for the SPI hardware.
• Allow using SPI with Dma[Tx|Rx]Buffers that don't have a length. The driver should accept a length in addition to the DMA buffer. (This allows for streaming transfers)

#2494 was created while I was drafting this issue. I think this issue should be separate since that one will be closed once the analysis is done, and this should remain open as a request for the features.

edit: moved a few of these into #2494 to be tackled before 1.0

[bugadani]

Please don't remove needs-attention, the team will do that during/after triage.

[Dominaezzz]

Noted. Sorry about that

[bugadani]

C2/C3/C6/H2 also have APP interrupts.

S2's LCD features can live in a separate driver, most likely.