Design high frequency sample and hold routine

[etemu]

Detach all interrupts, set a low prescaler and sample a single ADC channel with a variable Frequency up to 500khz - for detailed waveform analysis within a specific window.

This is not mandatory but rather an enhancement for educational purposes and advanced analysis of the waveforms.

[etemu]

Setting the prescaler to 16 yields an ADC clock up to 1Mhz but it may have an impact to resolution:

The Atmega168 datasheet eludes to the fact the reason behind using the default 200kHz clock is because it is optimized around the connected voltage source having an output impedance of 10k or less. So, a buffer stage aka impedance converter is needed for a high-Z input from TiVA.