AXIOM-photonSDI-hw.pro

update=2019 January 17, Thursday 17:28:24
version=1
last_client=pcbnew
[general]
version=1
RootSch=
BoardNm=
[cvpcb]
version=1
NetIExt=net
[eeschema]
version=1
LibDir=
[eeschema/libraries]
[schematic_editor]
version=1
PageLayoutDescrFile=
PlotDirectoryName=
SubpartIdSeparator=0
SubpartFirstId=65
NetFmtName=
SpiceAjustPassiveValues=0
LabSize=50
ERC_TestSimilarLabels=1
[pcbnew]
version=1
PageLayoutDescrFile=
LastNetListRead=AXIOM-photonSDI-hw.net
CopperLayerCount=4
BoardThickness=1.6
AllowMicroVias=0
AllowBlindVias=0
RequireCourtyardDefinitions=0
ProhibitOverlappingCourtyards=1
MinTrackWidth=0.127
MinViaDiameter=0.4572
MinViaDrill=0.254
MinMicroViaDiameter=0.2
MinMicroViaDrill=0.09999999999999999
MinHoleToHole=0.25
TrackWidth1=0.15
ViaDiameter1=0.4572
ViaDrill1=0.254
dPairWidth1=0.2
dPairGap1=0.127
dPairViaGap1=0.25
SilkLineWidth=0.15
SilkTextSizeV=1
SilkTextSizeH=1
SilkTextSizeThickness=0.15
SilkTextItalic=0
SilkTextUpright=1
CopperLineWidth=0.2
CopperTextSizeV=1.5
CopperTextSizeH=1.5
CopperTextThickness=0.3
CopperTextItalic=0
CopperTextUpright=1
EdgeCutLineWidth=0.09999999999999999
CourtyardLineWidth=0.05
OthersLineWidth=0.15
OthersTextSizeV=1
OthersTextSizeH=1
OthersTextSizeThickness=0.15
OthersTextItalic=0
OthersTextUpright=1
SolderMaskClearance=0.0635
SolderMaskMinWidth=0.25
SolderPasteClearance=0
SolderPasteRatio=-0
[pcbnew/Netclasses]
[pcbnew/Netclasses/1]
Name=differential
Clearance=0.127
TrackWidth=0.16
ViaDiameter=0.4572
ViaDrill=0.254
uViaDiameter=0.3
uViaDrill=0.1
dPairWidth=0.16
dPairGap=0.127
dPairViaGap=0.25
[pcbnew/Netclasses/2]
Name=power
Clearance=0.127
TrackWidth=0.2
ViaDiameter=0.4572
ViaDrill=0.254
uViaDiameter=0.3
uViaDrill=0.1
dPairWidth=0.2
dPairGap=0.127
dPairViaGap=0.25
[pcbnew/Netclasses/3]
Name=sdi
Clearance=0.2
TrackWidth=0.139
ViaDiameter=0.4572
ViaDrill=0.254
uViaDiameter=0.3
uViaDrill=0.1
dPairWidth=0.2
dPairGap=0.127
dPairViaGap=0.25