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kvm-unit-tests-ca85dda2671e.patch
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kvm-unit-tests-ca85dda2671e.patch
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From 5fbeca5651ed44b4e9a4670e7f8e0efe88442e26 Mon Sep 17 00:00:00 2001
From: Dongli Zhang <[email protected]>
Date: Wed, 20 Jul 2022 17:42:08 -0700
Subject: [PATCH 1/1] kvm-unit-tests-ca85dda2671e
Signed-off-by: Dongli Zhang <[email protected]>
---
x86/pmu.c | 124 ++++++++++++++++++++++++++++++++++++++++++++++++++++++
1 file changed, 124 insertions(+)
diff --git a/x86/pmu.c b/x86/pmu.c
index a46bdbf..91cfe1c 100644
--- a/x86/pmu.c
+++ b/x86/pmu.c
@@ -98,6 +98,18 @@ struct pmu_event {
};
#define PMU_CAP_FW_WRITES (1ULL << 13)
+/*
+ * 在以下设置gp_counter_base:
+ * - x86/pmu.c|751| <<main>> if (rdmsr(MSR_IA32_PERF_CAPABILITIES) & PMU_CAP_FW_WRITES) gp_counter_base = MSR_IA32_PMC0;
+ * - x86/pmu.c|101| <<global>> static u64 gp_counter_base = MSR_IA32_PERFCTR0;
+ *
+ * 关于version 1,
+ * IA32_PMCx MSRs 从 0x0c1开始
+ * IA32_PERFEVTSELx MSRs 从0x186开始
+ *
+ * 当IA_PERF_CAPABILITIES.FW_WRITE[bit 13] == 1的时候:
+ * IA32_PMCx从0x4c1开始
+ */
static u64 gp_counter_base = MSR_IA32_PERFCTR0;
static int num_counters;
@@ -132,8 +144,20 @@ static bool check_irq(void)
return irq_received;
}
+/*
+ * called by:
+ * - x86/pmu.c|143| <<event_to_global_idx>> return cnt->ctr - (is_gp(cnt) ? gp_counter_base :
+ * - x86/pmu.c|149| <<get_counter_event>> if (is_gp(cnt)) {
+ * - x86/pmu.c|187| <<start_event>> if (is_gp(evt))
+ * - x86/pmu.c|211| <<stop_event>> if (is_gp(evt))
+ * - x86/pmu.c|395| <<do_rdpmc_fast>> if (!is_gp(cnt))
+ */
static bool is_gp(pmu_counter_t *evt)
{
+ /*
+ * MSR_CORE_PERF_FIXED_CTR0 = 0x309
+ * MSR_IA32_PMC0 = 0x4c1
+ */
return evt->ctr < MSR_CORE_PERF_FIXED_CTR0 ||
evt->ctr >= MSR_IA32_PMC0;
}
@@ -173,8 +197,34 @@ static void global_disable(pmu_counter_t *cnt)
}
+/*
+ * version 1:
+ *
+ * IA32_PMCx MSRs 从 0x0c1开始
+ * IA32_PERFEVTSELx MSRs 从0x186开始
+ *
+ * 当IA_PERF_CAPABILITIES.FW_WRITE[bit 13] == 1的时候:
+ * IA32_PMCx从0x4c1开始
+ *
+ * version 2:
+ *
+ * IA32_FIXED_CTR0 在 0x309
+ * IA32_FIXED_CTR1 在 0x30a
+ * IA32_FIXED_CTR2 在 0x30b
+ * IA32_FIXED_CTR3 在 0x30c
+ *
+ * IA32_FIXED_CTR_CTRL在0x38d
+ */
static void start_event(pmu_counter_t *evt)
{
+ /*
+ * typedef struct {
+ * uint32_t ctr;
+ * uint32_t config;
+ * uint64_t count;
+ * int idx;
+ * } pmu_counter_t;
+ */
wrmsr(evt->ctr, evt->count);
if (is_gp(evt))
wrmsr(MSR_P6_EVNTSEL0 + event_to_global_idx(evt),
@@ -208,6 +258,14 @@ static void stop_event(pmu_counter_t *evt)
int shift = (evt->ctr - MSR_CORE_PERF_FIXED_CTR0) * 4;
wrmsr(MSR_CORE_PERF_FIXED_CTR_CTRL, ctrl & ~(0xf << shift));
}
+ /*
+ * typedef struct {
+ * uint32_t ctr;
+ * uint32_t config;
+ * uint64_t count;
+ * int idx;
+ * } pmu_counter_t;
+ */
evt->count = rdmsr(evt->ctr);
}
@@ -235,6 +293,18 @@ static bool verify_counter(pmu_counter_t *cnt)
static void check_gp_counter(struct pmu_event *evt)
{
+ /*
+ * typedef struct {
+ * uint32_t ctr;
+ * uint32_t config;
+ * uint64_t count;
+ * int idx;
+ * } pmu_counter_t;
+ *
+ * 在以下设置gp_counter_base:
+ * - x86/pmu.c|751| <<main>> if (rdmsr(MSR_IA32_PERF_CAPABILITIES) & PMU_CAP_FW_WRITES) gp_counter_base = MSR_IA32_PMC0;
+ * - x86/pmu.c|101| <<global>> static u64 gp_counter_base = MSR_IA32_PERFCTR0;
+ */
pmu_counter_t cnt = {
.ctr = gp_counter_base,
.config = EVNTSEL_OS | EVNTSEL_USR | evt->unit_sel,
@@ -252,6 +322,18 @@ static void check_gp_counters(void)
{
int i;
+ /*
+ * 关于ebx.
+ *
+ * Architecture Performance Monitoring Features (0xa/ebx):
+ * core cycle event not available = false
+ * instruction retired event not available = false
+ * reference cycles event not available = false
+ * last-level cache ref event not available = false
+ * last-level cache miss event not avail = false
+ * branch inst retired event not available = false
+ * branch mispred retired event not avail = false
+ */
for (i = 0; i < sizeof(gp_events)/sizeof(gp_events[0]); i++)
if (!(ebx.full & (1 << i)))
check_gp_counter(&gp_events[i]);
@@ -610,8 +692,22 @@ static void check_gp_counters_write_width(void)
* core crystal clock, TSC, or bus clock. Calibrate to the TSC
* frequency to set reasonable expectations.
*/
+/*
+ * called by:
+ * - x86/pmu.c|678| <<main>> set_ref_cycle_expectations();
+ *
+ * 核心思想是计算gp_events[2].min和gp_events[2].max
+ */
static void set_ref_cycle_expectations(void)
{
+ /*
+ * typedef struct {
+ * uint32_t ctr;
+ * uint32_t config;
+ * uint64_t count;
+ * int idx;
+ * } pmu_counter_t;
+ */
pmu_counter_t cnt = {
.ctr = MSR_IA32_PERFCTR0,
.config = EVNTSEL_OS | EVNTSEL_USR | gp_events[2].unit_sel,
@@ -653,6 +749,28 @@ static void set_ref_cycle_expectations(void)
gp_events[2].max = (gp_events[2].max * cnt.count) / tsc_delta;
}
+/*
+ * # cpuid -l 10 -1
+ * Disclaimer: cpuid may not support decoding of all cpuid registers.
+ * CPU:
+ * Architecture Performance Monitoring Features (0xa/eax):
+ * version ID = 0x3 (3)
+ * number of counters per logical processor = 0x4 (4)
+ * bit width of counter = 0x30 (48)
+ * length of EBX bit vector = 0x7 (7)
+ * Architecture Performance Monitoring Features (0xa/ebx):
+ * core cycle event not available = false
+ * instruction retired event not available = false
+ * reference cycles event not available = false
+ * last-level cache ref event not available = false
+ * last-level cache miss event not avail = false
+ * branch inst retired event not available = false
+ * branch mispred retired event not avail = false
+ * Architecture Performance Monitoring Features (0xa/edx):
+ * number of fixed counters = 0x3 (3)
+ * bit width of fixed counters = 0x30 (48)
+ */
+
int main(int ac, char **av)
{
struct cpuid id = cpuid(10);
@@ -675,6 +793,9 @@ int main(int ac, char **av)
return report_summary();
}
+ /*
+ * 核心思想是计算gp_events[2].min和gp_events[2].max
+ */
set_ref_cycle_expectations();
printf("PMU version: %d\n", eax.split.version_id);
@@ -684,6 +805,9 @@ int main(int ac, char **av)
printf("Fixed counters: %d\n", edx.split.num_counters_fixed);
printf("Fixed counter width: %d\n", edx.split.bit_width_fixed);
+ /*
+ * number of counters per logical processor = 0x4 (4)
+ */
num_counters = eax.split.num_counters;
apic_write(APIC_LVTPC, PC_VECTOR);
--
2.17.1