From 0949766ad765c7e1303d6539300f95d6515a2294 Mon Sep 17 00:00:00 2001 From: Andre Weissflog Date: Thu, 2 Jan 2025 16:17:47 +0100 Subject: [PATCH] Z80 code generated decoder structure rework. (#106) --- .gitignore | 2 + CHANGELOG.md | 14 + chips/m6502.h | 3 +- chips/z80.h | 5563 ++++++++++++-------------------------- codegen/README.txt | 16 +- codegen/m6502.template.h | 793 ------ codegen/m6502_gen.py | 44 +- codegen/m6502_gen.sh | 4 + codegen/templ.py | 20 + codegen/z80.template.h | 1155 -------- codegen/z80_desc.yml | 36 +- codegen/z80_gen.py | 302 ++- codegen/z80_gen.sh | 4 + 13 files changed, 2064 insertions(+), 5892 deletions(-) delete mode 100644 codegen/m6502.template.h create mode 100755 codegen/m6502_gen.sh create mode 100644 codegen/templ.py delete mode 100644 codegen/z80.template.h create mode 100755 codegen/z80_gen.sh diff --git a/.gitignore b/.gitignore index 3f19db91..72ad9fc2 100644 --- a/.gitignore +++ b/.gitignore @@ -1,4 +1,6 @@ .vscode/ +.venv/ +__pycache__/ #>fips # this area is managed by fips, do not edit .fips-* diff --git a/CHANGELOG.md b/CHANGELOG.md index 1b1e1aae..4f7ad453 100644 --- a/CHANGELOG.md +++ b/CHANGELOG.md @@ -1,5 +1,19 @@ ## What's New +* **02-Jan-2024**: Integrated some 'structural ideas' from the Zig Z80 emulator into z80.h + (everything backward compatible and no behaviour changes): + - Got rid of lookup tables which mapped opcodes to the first instruction + payload step in the decoder switch-case statement. Instead the first + 512 case-branches in the decoder switch-case directly map to the first + (and for 4-cycle instructions: only) payload step (256 for the main + instruction subset and the next 256 for the ED-prefixed subset). + - Stepping to the next decoder step is now always 'exclusive', instead + of incrementing the current step, an explicit step number is written. + This appears to be a tiny faster. + - The separate input template files for the code generation of the Z80 + and M6502 emulators have been removed, instead the generated code is + now injected into the actual source files (search for `<%` and `%>` markers). + * **24-Dec-2024**: complete UI overhaul: - switched to the Dear ImGui docking branch diff --git a/chips/m6502.h b/chips/m6502.h index 6729986e..8bf1d3dc 100644 --- a/chips/m6502.h +++ b/chips/m6502.h @@ -768,6 +768,7 @@ uint64_t m6502_tick(m6502_t* c, uint64_t pins) { // reads are default, writes are special _RD(); switch (c->IR++) { + // <% decoder /* BRK */ case (0x00<<3)|0: _SA(c->PC);break; case (0x00<<3)|1: if(0==(c->brk_flags&(M6502_BRK_IRQ|M6502_BRK_NMI))){c->PC++;}_SAD(0x0100|c->S--,c->PC>>8);if(0==(c->brk_flags&M6502_BRK_RESET)){_WR();}break; @@ -3072,7 +3073,7 @@ uint64_t m6502_tick(m6502_t* c, uint64_t pins) { case (0xFF<<3)|5: c->AD++;_SD(c->AD);_m6502_sbc(c,c->AD);_WR();break; case (0xFF<<3)|6: _FETCH();break; case (0xFF<<3)|7: assert(false);break; - + // %> } M6510_SET_PORT(pins, c->io_pins); c->PINS = pins; diff --git a/chips/z80.h b/chips/z80.h index 4b34acd9..055d581d 100644 --- a/chips/z80.h +++ b/chips/z80.h @@ -396,10 +396,40 @@ bool z80_opdone(z80_t* cpu); #define _Z80_UNREACHABLE #endif -// values for hlx_idx for mapping HL, IX or IY, used as index into hlx[] -#define _Z80_MAP_HL (0) -#define _Z80_MAP_IX (1) -#define _Z80_MAP_IY (2) +// extra/special decoder steps +// <% extra_step_defines +#define Z80_DDFD_M1_T2 1685 +#define Z80_DDFD_M1_T3 1686 +#define Z80_DDFD_M1_T4 1687 +#define Z80_DDFD_D_T1 1688 +#define Z80_DDFD_D_T2 1689 +#define Z80_DDFD_D_T3 1690 +#define Z80_DDFD_D_T4 1691 +#define Z80_DDFD_D_T5 1692 +#define Z80_DDFD_D_T6 1693 +#define Z80_DDFD_D_T7 1694 +#define Z80_DDFD_D_T8 1695 +#define Z80_DDFD_LDHLN_WR_T1 1696 +#define Z80_DDFD_LDHLN_WR_T2 1697 +#define Z80_DDFD_LDHLN_WR_T3 1698 +#define Z80_DDFD_LDHLN_OVERLAPPED 1699 +#define Z80_CB_M1_T2 1700 +#define Z80_CB_M1_T3 1701 +#define Z80_CB_M1_T4 1702 +#define Z80_ED_M1_T2 1703 +#define Z80_ED_M1_T3 1704 +#define Z80_ED_M1_T4 1705 +#define Z80_M1_T2 1706 +#define Z80_M1_T3 1707 +#define Z80_M1_T4 1708 +#define Z80_CB_STEP 1612 +#define Z80_CBHL_STEP 1613 +#define Z80_DDFDCB_STEP 1621 +#define Z80_INT_IM0_STEP 1636 +#define Z80_INT_IM1_STEP 1642 +#define Z80_INT_IM2_STEP 1655 +#define Z80_NMI_STEP 1674 +// %> uint64_t z80_init(z80_t* cpu) { CHIPS_ASSERT(cpu); @@ -451,6 +481,28 @@ static const uint8_t _z80_szp_flags[256] = { 0xa4,0xa0,0xa0,0xa4,0xa0,0xa4,0xa4,0xa0,0xa8,0xac,0xac,0xa8,0xac,0xa8,0xa8,0xac, }; +// lookup table for (HL)/(IX/IY+d) ops +static const uint8_t _z80_indirect_table[256] = { + // <% indirect_table + 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, + 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, + 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, + 0,0,0,0,1,1,1,0,0,0,0,0,0,0,0,0, + 0,0,0,0,0,0,1,0,0,0,0,0,0,0,1,0, + 0,0,0,0,0,0,1,0,0,0,0,0,0,0,1,0, + 0,0,0,0,0,0,1,0,0,0,0,0,0,0,1,0, + 1,1,1,1,1,1,0,1,0,0,0,0,0,0,1,0, + 0,0,0,0,0,0,1,0,0,0,0,0,0,0,1,0, + 0,0,0,0,0,0,1,0,0,0,0,0,0,0,1,0, + 0,0,0,0,0,0,1,0,0,0,0,0,0,0,1,0, + 0,0,0,0,0,0,1,0,0,0,0,0,0,0,1,0, + 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, + 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, + 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, + 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, + // %> +}; + static inline uint8_t _z80_sz_flags(uint8_t val) { return (val != 0) ? (val & Z80_SF) : Z80_ZF; } @@ -883,806 +935,6 @@ static inline void _z80_ddfdcb_addr(z80_t* cpu, uint64_t pins) { cpu->wz = cpu->addr; } -// special case opstate table slots -#define _Z80_OPSTATE_SLOT_CB (0) -#define _Z80_OPSTATE_SLOT_CBHL (1) -#define _Z80_OPSTATE_SLOT_DDFDCB (2) -#define _Z80_OPSTATE_SLOT_INT_IM0 (3) -#define _Z80_OPSTATE_SLOT_INT_IM1 (4) -#define _Z80_OPSTATE_SLOT_INT_IM2 (5) -#define _Z80_OPSTATE_SLOT_NMI (6) -#define _Z80_OPSTATE_NUM_SPECIAL_OPS (7) - -#define _Z80_OPSTATE_STEP_INDIRECT (5) // see case-branch '6' -#define _Z80_OPSTATE_STEP_INDIRECT_IMM8 (13) // see case-branch '14' - -static const uint16_t _z80_optable[256] = { - 27, // 00: NOP (M:1 T:4 steps:1) - 28, // 01: LD BC,nn (M:3 T:10 steps:7) - 35, // 02: LD (BC),A (M:2 T:7 steps:4) - 39, // 03: INC BC (M:2 T:6 steps:3) - 42, // 04: INC B (M:1 T:4 steps:1) - 43, // 05: DEC B (M:1 T:4 steps:1) - 44, // 06: LD B,n (M:2 T:7 steps:4) - 48, // 07: RLCA (M:1 T:4 steps:1) - 49, // 08: EX AF,AF' (M:1 T:4 steps:1) - 50, // 09: ADD HL,BC (M:2 T:11 steps:8) - 58, // 0A: LD A,(BC) (M:2 T:7 steps:4) - 62, // 0B: DEC BC (M:2 T:6 steps:3) - 65, // 0C: INC C (M:1 T:4 steps:1) - 66, // 0D: DEC C (M:1 T:4 steps:1) - 67, // 0E: LD C,n (M:2 T:7 steps:4) - 71, // 0F: RRCA (M:1 T:4 steps:1) - 72, // 10: DJNZ d (M:4 T:13 steps:10) - 82, // 11: LD DE,nn (M:3 T:10 steps:7) - 89, // 12: LD (DE),A (M:2 T:7 steps:4) - 93, // 13: INC DE (M:2 T:6 steps:3) - 96, // 14: INC D (M:1 T:4 steps:1) - 97, // 15: DEC D (M:1 T:4 steps:1) - 98, // 16: LD D,n (M:2 T:7 steps:4) - 102, // 17: RLA (M:1 T:4 steps:1) - 103, // 18: JR d (M:3 T:12 steps:9) - 112, // 19: ADD HL,DE (M:2 T:11 steps:8) - 120, // 1A: LD A,(DE) (M:2 T:7 steps:4) - 124, // 1B: DEC DE (M:2 T:6 steps:3) - 127, // 1C: INC E (M:1 T:4 steps:1) - 128, // 1D: DEC E (M:1 T:4 steps:1) - 129, // 1E: LD E,n (M:2 T:7 steps:4) - 133, // 1F: RRA (M:1 T:4 steps:1) - 134, // 20: JR NZ,d (M:3 T:12 steps:9) - 143, // 21: LD HL,nn (M:3 T:10 steps:7) - 150, // 22: LD (nn),HL (M:5 T:16 steps:13) - 163, // 23: INC HL (M:2 T:6 steps:3) - 166, // 24: INC H (M:1 T:4 steps:1) - 167, // 25: DEC H (M:1 T:4 steps:1) - 168, // 26: LD H,n (M:2 T:7 steps:4) - 172, // 27: DAA (M:1 T:4 steps:1) - 173, // 28: JR Z,d (M:3 T:12 steps:9) - 182, // 29: ADD HL,HL (M:2 T:11 steps:8) - 190, // 2A: LD HL,(nn) (M:5 T:16 steps:13) - 203, // 2B: DEC HL (M:2 T:6 steps:3) - 206, // 2C: INC L (M:1 T:4 steps:1) - 207, // 2D: DEC L (M:1 T:4 steps:1) - 208, // 2E: LD L,n (M:2 T:7 steps:4) - 212, // 2F: CPL (M:1 T:4 steps:1) - 213, // 30: JR NC,d (M:3 T:12 steps:9) - 222, // 31: LD SP,nn (M:3 T:10 steps:7) - 229, // 32: LD (nn),A (M:4 T:13 steps:10) - 239, // 33: INC SP (M:2 T:6 steps:3) - 242, // 34: INC (HL) (M:3 T:11 steps:8) - 250, // 35: DEC (HL) (M:3 T:11 steps:8) - 258, // 36: LD (HL),n (M:3 T:10 steps:7) - 265, // 37: SCF (M:1 T:4 steps:1) - 266, // 38: JR C,d (M:3 T:12 steps:9) - 275, // 39: ADD HL,SP (M:2 T:11 steps:8) - 283, // 3A: LD A,(nn) (M:4 T:13 steps:10) - 293, // 3B: DEC SP (M:2 T:6 steps:3) - 296, // 3C: INC A (M:1 T:4 steps:1) - 297, // 3D: DEC A (M:1 T:4 steps:1) - 298, // 3E: LD A,n (M:2 T:7 steps:4) - 302, // 3F: CCF (M:1 T:4 steps:1) - 303, // 40: LD B,B (M:1 T:4 steps:1) - 304, // 41: LD B,C (M:1 T:4 steps:1) - 305, // 42: LD B,D (M:1 T:4 steps:1) - 306, // 43: LD B,E (M:1 T:4 steps:1) - 307, // 44: LD B,H (M:1 T:4 steps:1) - 308, // 45: LD B,L (M:1 T:4 steps:1) - 309, // 46: LD B,(HL) (M:2 T:7 steps:4) - 313, // 47: LD B,A (M:1 T:4 steps:1) - 314, // 48: LD C,B (M:1 T:4 steps:1) - 315, // 49: LD C,C (M:1 T:4 steps:1) - 316, // 4A: LD C,D (M:1 T:4 steps:1) - 317, // 4B: LD C,E (M:1 T:4 steps:1) - 318, // 4C: LD C,H (M:1 T:4 steps:1) - 319, // 4D: LD C,L (M:1 T:4 steps:1) - 320, // 4E: LD C,(HL) (M:2 T:7 steps:4) - 324, // 4F: LD C,A (M:1 T:4 steps:1) - 325, // 50: LD D,B (M:1 T:4 steps:1) - 326, // 51: LD D,C (M:1 T:4 steps:1) - 327, // 52: LD D,D (M:1 T:4 steps:1) - 328, // 53: LD D,E (M:1 T:4 steps:1) - 329, // 54: LD D,H (M:1 T:4 steps:1) - 330, // 55: LD D,L (M:1 T:4 steps:1) - 331, // 56: LD D,(HL) (M:2 T:7 steps:4) - 335, // 57: LD D,A (M:1 T:4 steps:1) - 336, // 58: LD E,B (M:1 T:4 steps:1) - 337, // 59: LD E,C (M:1 T:4 steps:1) - 338, // 5A: LD E,D (M:1 T:4 steps:1) - 339, // 5B: LD E,E (M:1 T:4 steps:1) - 340, // 5C: LD E,H (M:1 T:4 steps:1) - 341, // 5D: LD E,L (M:1 T:4 steps:1) - 342, // 5E: LD E,(HL) (M:2 T:7 steps:4) - 346, // 5F: LD E,A (M:1 T:4 steps:1) - 347, // 60: LD H,B (M:1 T:4 steps:1) - 348, // 61: LD H,C (M:1 T:4 steps:1) - 349, // 62: LD H,D (M:1 T:4 steps:1) - 350, // 63: LD H,E (M:1 T:4 steps:1) - 351, // 64: LD H,H (M:1 T:4 steps:1) - 352, // 65: LD H,L (M:1 T:4 steps:1) - 353, // 66: LD H,(HL) (M:2 T:7 steps:4) - 357, // 67: LD H,A (M:1 T:4 steps:1) - 358, // 68: LD L,B (M:1 T:4 steps:1) - 359, // 69: LD L,C (M:1 T:4 steps:1) - 360, // 6A: LD L,D (M:1 T:4 steps:1) - 361, // 6B: LD L,E (M:1 T:4 steps:1) - 362, // 6C: LD L,H (M:1 T:4 steps:1) - 363, // 6D: LD L,L (M:1 T:4 steps:1) - 364, // 6E: LD L,(HL) (M:2 T:7 steps:4) - 368, // 6F: LD L,A (M:1 T:4 steps:1) - 369, // 70: LD (HL),B (M:2 T:7 steps:4) - 373, // 71: LD (HL),C (M:2 T:7 steps:4) - 377, // 72: LD (HL),D (M:2 T:7 steps:4) - 381, // 73: LD (HL),E (M:2 T:7 steps:4) - 385, // 74: LD (HL),H (M:2 T:7 steps:4) - 389, // 75: LD (HL),L (M:2 T:7 steps:4) - 393, // 76: HALT (M:1 T:4 steps:1) - 394, // 77: LD (HL),A (M:2 T:7 steps:4) - 398, // 78: LD A,B (M:1 T:4 steps:1) - 399, // 79: LD A,C (M:1 T:4 steps:1) - 400, // 7A: LD A,D (M:1 T:4 steps:1) - 401, // 7B: LD A,E (M:1 T:4 steps:1) - 402, // 7C: LD A,H (M:1 T:4 steps:1) - 403, // 7D: LD A,L (M:1 T:4 steps:1) - 404, // 7E: LD A,(HL) (M:2 T:7 steps:4) - 408, // 7F: LD A,A (M:1 T:4 steps:1) - 409, // 80: ADD B (M:1 T:4 steps:1) - 410, // 81: ADD C (M:1 T:4 steps:1) - 411, // 82: ADD D (M:1 T:4 steps:1) - 412, // 83: ADD E (M:1 T:4 steps:1) - 413, // 84: ADD H (M:1 T:4 steps:1) - 414, // 85: ADD L (M:1 T:4 steps:1) - 415, // 86: ADD (HL) (M:2 T:7 steps:4) - 419, // 87: ADD A (M:1 T:4 steps:1) - 420, // 88: ADC B (M:1 T:4 steps:1) - 421, // 89: ADC C (M:1 T:4 steps:1) - 422, // 8A: ADC D (M:1 T:4 steps:1) - 423, // 8B: ADC E (M:1 T:4 steps:1) - 424, // 8C: ADC H (M:1 T:4 steps:1) - 425, // 8D: ADC L (M:1 T:4 steps:1) - 426, // 8E: ADC (HL) (M:2 T:7 steps:4) - 430, // 8F: ADC A (M:1 T:4 steps:1) - 431, // 90: SUB B (M:1 T:4 steps:1) - 432, // 91: SUB C (M:1 T:4 steps:1) - 433, // 92: SUB D (M:1 T:4 steps:1) - 434, // 93: SUB E (M:1 T:4 steps:1) - 435, // 94: SUB H (M:1 T:4 steps:1) - 436, // 95: SUB L (M:1 T:4 steps:1) - 437, // 96: SUB (HL) (M:2 T:7 steps:4) - 441, // 97: SUB A (M:1 T:4 steps:1) - 442, // 98: SBC B (M:1 T:4 steps:1) - 443, // 99: SBC C (M:1 T:4 steps:1) - 444, // 9A: SBC D (M:1 T:4 steps:1) - 445, // 9B: SBC E (M:1 T:4 steps:1) - 446, // 9C: SBC H (M:1 T:4 steps:1) - 447, // 9D: SBC L (M:1 T:4 steps:1) - 448, // 9E: SBC (HL) (M:2 T:7 steps:4) - 452, // 9F: SBC A (M:1 T:4 steps:1) - 453, // A0: AND B (M:1 T:4 steps:1) - 454, // A1: AND C (M:1 T:4 steps:1) - 455, // A2: AND D (M:1 T:4 steps:1) - 456, // A3: AND E (M:1 T:4 steps:1) - 457, // A4: AND H (M:1 T:4 steps:1) - 458, // A5: AND L (M:1 T:4 steps:1) - 459, // A6: AND (HL) (M:2 T:7 steps:4) - 463, // A7: AND A (M:1 T:4 steps:1) - 464, // A8: XOR B (M:1 T:4 steps:1) - 465, // A9: XOR C (M:1 T:4 steps:1) - 466, // AA: XOR D (M:1 T:4 steps:1) - 467, // AB: XOR E (M:1 T:4 steps:1) - 468, // AC: XOR H (M:1 T:4 steps:1) - 469, // AD: XOR L (M:1 T:4 steps:1) - 470, // AE: XOR (HL) (M:2 T:7 steps:4) - 474, // AF: XOR A (M:1 T:4 steps:1) - 475, // B0: OR B (M:1 T:4 steps:1) - 476, // B1: OR C (M:1 T:4 steps:1) - 477, // B2: OR D (M:1 T:4 steps:1) - 478, // B3: OR E (M:1 T:4 steps:1) - 479, // B4: OR H (M:1 T:4 steps:1) - 480, // B5: OR L (M:1 T:4 steps:1) - 481, // B6: OR (HL) (M:2 T:7 steps:4) - 485, // B7: OR A (M:1 T:4 steps:1) - 486, // B8: CP B (M:1 T:4 steps:1) - 487, // B9: CP C (M:1 T:4 steps:1) - 488, // BA: CP D (M:1 T:4 steps:1) - 489, // BB: CP E (M:1 T:4 steps:1) - 490, // BC: CP H (M:1 T:4 steps:1) - 491, // BD: CP L (M:1 T:4 steps:1) - 492, // BE: CP (HL) (M:2 T:7 steps:4) - 496, // BF: CP A (M:1 T:4 steps:1) - 497, // C0: RET NZ (M:4 T:11 steps:8) - 505, // C1: POP BC (M:3 T:10 steps:7) - 512, // C2: JP NZ,nn (M:3 T:10 steps:7) - 519, // C3: JP nn (M:3 T:10 steps:7) - 526, // C4: CALL NZ,nn (M:6 T:17 steps:14) - 540, // C5: PUSH BC (M:4 T:11 steps:8) - 548, // C6: ADD n (M:2 T:7 steps:4) - 552, // C7: RST 0h (M:4 T:11 steps:8) - 560, // C8: RET Z (M:4 T:11 steps:8) - 568, // C9: RET (M:3 T:10 steps:7) - 575, // CA: JP Z,nn (M:3 T:10 steps:7) - 582, // CB: CB prefix (M:1 T:4 steps:1) - 583, // CC: CALL Z,nn (M:6 T:17 steps:14) - 597, // CD: CALL nn (M:5 T:17 steps:14) - 611, // CE: ADC n (M:2 T:7 steps:4) - 615, // CF: RST 8h (M:4 T:11 steps:8) - 623, // D0: RET NC (M:4 T:11 steps:8) - 631, // D1: POP DE (M:3 T:10 steps:7) - 638, // D2: JP NC,nn (M:3 T:10 steps:7) - 645, // D3: OUT (n),A (M:3 T:11 steps:8) - 653, // D4: CALL NC,nn (M:6 T:17 steps:14) - 667, // D5: PUSH DE (M:4 T:11 steps:8) - 675, // D6: SUB n (M:2 T:7 steps:4) - 679, // D7: RST 10h (M:4 T:11 steps:8) - 687, // D8: RET C (M:4 T:11 steps:8) - 695, // D9: EXX (M:1 T:4 steps:1) - 696, // DA: JP C,nn (M:3 T:10 steps:7) - 703, // DB: IN A,(n) (M:3 T:11 steps:8) - 711, // DC: CALL C,nn (M:6 T:17 steps:14) - 725, // DD: DD prefix (M:1 T:4 steps:1) - 726, // DE: SBC n (M:2 T:7 steps:4) - 730, // DF: RST 18h (M:4 T:11 steps:8) - 738, // E0: RET PO (M:4 T:11 steps:8) - 746, // E1: POP HL (M:3 T:10 steps:7) - 753, // E2: JP PO,nn (M:3 T:10 steps:7) - 760, // E3: EX (SP),HL (M:5 T:19 steps:16) - 776, // E4: CALL PO,nn (M:6 T:17 steps:14) - 790, // E5: PUSH HL (M:4 T:11 steps:8) - 798, // E6: AND n (M:2 T:7 steps:4) - 802, // E7: RST 20h (M:4 T:11 steps:8) - 810, // E8: RET PE (M:4 T:11 steps:8) - 818, // E9: JP HL (M:1 T:4 steps:1) - 819, // EA: JP PE,nn (M:3 T:10 steps:7) - 826, // EB: EX DE,HL (M:1 T:4 steps:1) - 827, // EC: CALL PE,nn (M:6 T:17 steps:14) - 841, // ED: ED prefix (M:1 T:4 steps:1) - 842, // EE: XOR n (M:2 T:7 steps:4) - 846, // EF: RST 28h (M:4 T:11 steps:8) - 854, // F0: RET P (M:4 T:11 steps:8) - 862, // F1: POP AF (M:3 T:10 steps:7) - 869, // F2: JP P,nn (M:3 T:10 steps:7) - 876, // F3: DI (M:1 T:4 steps:1) - 877, // F4: CALL P,nn (M:6 T:17 steps:14) - 891, // F5: PUSH AF (M:4 T:11 steps:8) - 899, // F6: OR n (M:2 T:7 steps:4) - 903, // F7: RST 30h (M:4 T:11 steps:8) - 911, // F8: RET M (M:4 T:11 steps:8) - 919, // F9: LD SP,HL (M:2 T:6 steps:3) - 922, // FA: JP M,nn (M:3 T:10 steps:7) - 929, // FB: EI (M:1 T:4 steps:1) - 930, // FC: CALL M,nn (M:6 T:17 steps:14) - 944, // FD: FD prefix (M:1 T:4 steps:1) - 945, // FE: CP n (M:2 T:7 steps:4) - 949, // FF: RST 38h (M:4 T:11 steps:8) - }; - -static const uint16_t _z80_ddfd_optable[256] = { - 27, // 00: NOP (M:1 T:4 steps:1) - 28, // 01: LD BC,nn (M:3 T:10 steps:7) - 35, // 02: LD (BC),A (M:2 T:7 steps:4) - 39, // 03: INC BC (M:2 T:6 steps:3) - 42, // 04: INC B (M:1 T:4 steps:1) - 43, // 05: DEC B (M:1 T:4 steps:1) - 44, // 06: LD B,n (M:2 T:7 steps:4) - 48, // 07: RLCA (M:1 T:4 steps:1) - 49, // 08: EX AF,AF' (M:1 T:4 steps:1) - 50, // 09: ADD HL,BC (M:2 T:11 steps:8) - 58, // 0A: LD A,(BC) (M:2 T:7 steps:4) - 62, // 0B: DEC BC (M:2 T:6 steps:3) - 65, // 0C: INC C (M:1 T:4 steps:1) - 66, // 0D: DEC C (M:1 T:4 steps:1) - 67, // 0E: LD C,n (M:2 T:7 steps:4) - 71, // 0F: RRCA (M:1 T:4 steps:1) - 72, // 10: DJNZ d (M:4 T:13 steps:10) - 82, // 11: LD DE,nn (M:3 T:10 steps:7) - 89, // 12: LD (DE),A (M:2 T:7 steps:4) - 93, // 13: INC DE (M:2 T:6 steps:3) - 96, // 14: INC D (M:1 T:4 steps:1) - 97, // 15: DEC D (M:1 T:4 steps:1) - 98, // 16: LD D,n (M:2 T:7 steps:4) - 102, // 17: RLA (M:1 T:4 steps:1) - 103, // 18: JR d (M:3 T:12 steps:9) - 112, // 19: ADD HL,DE (M:2 T:11 steps:8) - 120, // 1A: LD A,(DE) (M:2 T:7 steps:4) - 124, // 1B: DEC DE (M:2 T:6 steps:3) - 127, // 1C: INC E (M:1 T:4 steps:1) - 128, // 1D: DEC E (M:1 T:4 steps:1) - 129, // 1E: LD E,n (M:2 T:7 steps:4) - 133, // 1F: RRA (M:1 T:4 steps:1) - 134, // 20: JR NZ,d (M:3 T:12 steps:9) - 143, // 21: LD HL,nn (M:3 T:10 steps:7) - 150, // 22: LD (nn),HL (M:5 T:16 steps:13) - 163, // 23: INC HL (M:2 T:6 steps:3) - 166, // 24: INC H (M:1 T:4 steps:1) - 167, // 25: DEC H (M:1 T:4 steps:1) - 168, // 26: LD H,n (M:2 T:7 steps:4) - 172, // 27: DAA (M:1 T:4 steps:1) - 173, // 28: JR Z,d (M:3 T:12 steps:9) - 182, // 29: ADD HL,HL (M:2 T:11 steps:8) - 190, // 2A: LD HL,(nn) (M:5 T:16 steps:13) - 203, // 2B: DEC HL (M:2 T:6 steps:3) - 206, // 2C: INC L (M:1 T:4 steps:1) - 207, // 2D: DEC L (M:1 T:4 steps:1) - 208, // 2E: LD L,n (M:2 T:7 steps:4) - 212, // 2F: CPL (M:1 T:4 steps:1) - 213, // 30: JR NC,d (M:3 T:12 steps:9) - 222, // 31: LD SP,nn (M:3 T:10 steps:7) - 229, // 32: LD (nn),A (M:4 T:13 steps:10) - 239, // 33: INC SP (M:2 T:6 steps:3) - _Z80_OPSTATE_STEP_INDIRECT, // 34: INC (HL) (M:3 T:11 steps:8) - _Z80_OPSTATE_STEP_INDIRECT, // 35: DEC (HL) (M:3 T:11 steps:8) - _Z80_OPSTATE_STEP_INDIRECT_IMM8, // 36: LD (HL),n (M:3 T:10 steps:7) - 265, // 37: SCF (M:1 T:4 steps:1) - 266, // 38: JR C,d (M:3 T:12 steps:9) - 275, // 39: ADD HL,SP (M:2 T:11 steps:8) - 283, // 3A: LD A,(nn) (M:4 T:13 steps:10) - 293, // 3B: DEC SP (M:2 T:6 steps:3) - 296, // 3C: INC A (M:1 T:4 steps:1) - 297, // 3D: DEC A (M:1 T:4 steps:1) - 298, // 3E: LD A,n (M:2 T:7 steps:4) - 302, // 3F: CCF (M:1 T:4 steps:1) - 303, // 40: LD B,B (M:1 T:4 steps:1) - 304, // 41: LD B,C (M:1 T:4 steps:1) - 305, // 42: LD B,D (M:1 T:4 steps:1) - 306, // 43: LD B,E (M:1 T:4 steps:1) - 307, // 44: LD B,H (M:1 T:4 steps:1) - 308, // 45: LD B,L (M:1 T:4 steps:1) - _Z80_OPSTATE_STEP_INDIRECT, // 46: LD B,(HL) (M:2 T:7 steps:4) - 313, // 47: LD B,A (M:1 T:4 steps:1) - 314, // 48: LD C,B (M:1 T:4 steps:1) - 315, // 49: LD C,C (M:1 T:4 steps:1) - 316, // 4A: LD C,D (M:1 T:4 steps:1) - 317, // 4B: LD C,E (M:1 T:4 steps:1) - 318, // 4C: LD C,H (M:1 T:4 steps:1) - 319, // 4D: LD C,L (M:1 T:4 steps:1) - _Z80_OPSTATE_STEP_INDIRECT, // 4E: LD C,(HL) (M:2 T:7 steps:4) - 324, // 4F: LD C,A (M:1 T:4 steps:1) - 325, // 50: LD D,B (M:1 T:4 steps:1) - 326, // 51: LD D,C (M:1 T:4 steps:1) - 327, // 52: LD D,D (M:1 T:4 steps:1) - 328, // 53: LD D,E (M:1 T:4 steps:1) - 329, // 54: LD D,H (M:1 T:4 steps:1) - 330, // 55: LD D,L (M:1 T:4 steps:1) - _Z80_OPSTATE_STEP_INDIRECT, // 56: LD D,(HL) (M:2 T:7 steps:4) - 335, // 57: LD D,A (M:1 T:4 steps:1) - 336, // 58: LD E,B (M:1 T:4 steps:1) - 337, // 59: LD E,C (M:1 T:4 steps:1) - 338, // 5A: LD E,D (M:1 T:4 steps:1) - 339, // 5B: LD E,E (M:1 T:4 steps:1) - 340, // 5C: LD E,H (M:1 T:4 steps:1) - 341, // 5D: LD E,L (M:1 T:4 steps:1) - _Z80_OPSTATE_STEP_INDIRECT, // 5E: LD E,(HL) (M:2 T:7 steps:4) - 346, // 5F: LD E,A (M:1 T:4 steps:1) - 347, // 60: LD H,B (M:1 T:4 steps:1) - 348, // 61: LD H,C (M:1 T:4 steps:1) - 349, // 62: LD H,D (M:1 T:4 steps:1) - 350, // 63: LD H,E (M:1 T:4 steps:1) - 351, // 64: LD H,H (M:1 T:4 steps:1) - 352, // 65: LD H,L (M:1 T:4 steps:1) - _Z80_OPSTATE_STEP_INDIRECT, // 66: LD H,(HL) (M:2 T:7 steps:4) - 357, // 67: LD H,A (M:1 T:4 steps:1) - 358, // 68: LD L,B (M:1 T:4 steps:1) - 359, // 69: LD L,C (M:1 T:4 steps:1) - 360, // 6A: LD L,D (M:1 T:4 steps:1) - 361, // 6B: LD L,E (M:1 T:4 steps:1) - 362, // 6C: LD L,H (M:1 T:4 steps:1) - 363, // 6D: LD L,L (M:1 T:4 steps:1) - _Z80_OPSTATE_STEP_INDIRECT, // 6E: LD L,(HL) (M:2 T:7 steps:4) - 368, // 6F: LD L,A (M:1 T:4 steps:1) - _Z80_OPSTATE_STEP_INDIRECT, // 70: LD (HL),B (M:2 T:7 steps:4) - _Z80_OPSTATE_STEP_INDIRECT, // 71: LD (HL),C (M:2 T:7 steps:4) - _Z80_OPSTATE_STEP_INDIRECT, // 72: LD (HL),D (M:2 T:7 steps:4) - _Z80_OPSTATE_STEP_INDIRECT, // 73: LD (HL),E (M:2 T:7 steps:4) - _Z80_OPSTATE_STEP_INDIRECT, // 74: LD (HL),H (M:2 T:7 steps:4) - _Z80_OPSTATE_STEP_INDIRECT, // 75: LD (HL),L (M:2 T:7 steps:4) - 393, // 76: HALT (M:1 T:4 steps:1) - _Z80_OPSTATE_STEP_INDIRECT, // 77: LD (HL),A (M:2 T:7 steps:4) - 398, // 78: LD A,B (M:1 T:4 steps:1) - 399, // 79: LD A,C (M:1 T:4 steps:1) - 400, // 7A: LD A,D (M:1 T:4 steps:1) - 401, // 7B: LD A,E (M:1 T:4 steps:1) - 402, // 7C: LD A,H (M:1 T:4 steps:1) - 403, // 7D: LD A,L (M:1 T:4 steps:1) - _Z80_OPSTATE_STEP_INDIRECT, // 7E: LD A,(HL) (M:2 T:7 steps:4) - 408, // 7F: LD A,A (M:1 T:4 steps:1) - 409, // 80: ADD B (M:1 T:4 steps:1) - 410, // 81: ADD C (M:1 T:4 steps:1) - 411, // 82: ADD D (M:1 T:4 steps:1) - 412, // 83: ADD E (M:1 T:4 steps:1) - 413, // 84: ADD H (M:1 T:4 steps:1) - 414, // 85: ADD L (M:1 T:4 steps:1) - _Z80_OPSTATE_STEP_INDIRECT, // 86: ADD (HL) (M:2 T:7 steps:4) - 419, // 87: ADD A (M:1 T:4 steps:1) - 420, // 88: ADC B (M:1 T:4 steps:1) - 421, // 89: ADC C (M:1 T:4 steps:1) - 422, // 8A: ADC D (M:1 T:4 steps:1) - 423, // 8B: ADC E (M:1 T:4 steps:1) - 424, // 8C: ADC H (M:1 T:4 steps:1) - 425, // 8D: ADC L (M:1 T:4 steps:1) - _Z80_OPSTATE_STEP_INDIRECT, // 8E: ADC (HL) (M:2 T:7 steps:4) - 430, // 8F: ADC A (M:1 T:4 steps:1) - 431, // 90: SUB B (M:1 T:4 steps:1) - 432, // 91: SUB C (M:1 T:4 steps:1) - 433, // 92: SUB D (M:1 T:4 steps:1) - 434, // 93: SUB E (M:1 T:4 steps:1) - 435, // 94: SUB H (M:1 T:4 steps:1) - 436, // 95: SUB L (M:1 T:4 steps:1) - _Z80_OPSTATE_STEP_INDIRECT, // 96: SUB (HL) (M:2 T:7 steps:4) - 441, // 97: SUB A (M:1 T:4 steps:1) - 442, // 98: SBC B (M:1 T:4 steps:1) - 443, // 99: SBC C (M:1 T:4 steps:1) - 444, // 9A: SBC D (M:1 T:4 steps:1) - 445, // 9B: SBC E (M:1 T:4 steps:1) - 446, // 9C: SBC H (M:1 T:4 steps:1) - 447, // 9D: SBC L (M:1 T:4 steps:1) - _Z80_OPSTATE_STEP_INDIRECT, // 9E: SBC (HL) (M:2 T:7 steps:4) - 452, // 9F: SBC A (M:1 T:4 steps:1) - 453, // A0: AND B (M:1 T:4 steps:1) - 454, // A1: AND C (M:1 T:4 steps:1) - 455, // A2: AND D (M:1 T:4 steps:1) - 456, // A3: AND E (M:1 T:4 steps:1) - 457, // A4: AND H (M:1 T:4 steps:1) - 458, // A5: AND L (M:1 T:4 steps:1) - _Z80_OPSTATE_STEP_INDIRECT, // A6: AND (HL) (M:2 T:7 steps:4) - 463, // A7: AND A (M:1 T:4 steps:1) - 464, // A8: XOR B (M:1 T:4 steps:1) - 465, // A9: XOR C (M:1 T:4 steps:1) - 466, // AA: XOR D (M:1 T:4 steps:1) - 467, // AB: XOR E (M:1 T:4 steps:1) - 468, // AC: XOR H (M:1 T:4 steps:1) - 469, // AD: XOR L (M:1 T:4 steps:1) - _Z80_OPSTATE_STEP_INDIRECT, // AE: XOR (HL) (M:2 T:7 steps:4) - 474, // AF: XOR A (M:1 T:4 steps:1) - 475, // B0: OR B (M:1 T:4 steps:1) - 476, // B1: OR C (M:1 T:4 steps:1) - 477, // B2: OR D (M:1 T:4 steps:1) - 478, // B3: OR E (M:1 T:4 steps:1) - 479, // B4: OR H (M:1 T:4 steps:1) - 480, // B5: OR L (M:1 T:4 steps:1) - _Z80_OPSTATE_STEP_INDIRECT, // B6: OR (HL) (M:2 T:7 steps:4) - 485, // B7: OR A (M:1 T:4 steps:1) - 486, // B8: CP B (M:1 T:4 steps:1) - 487, // B9: CP C (M:1 T:4 steps:1) - 488, // BA: CP D (M:1 T:4 steps:1) - 489, // BB: CP E (M:1 T:4 steps:1) - 490, // BC: CP H (M:1 T:4 steps:1) - 491, // BD: CP L (M:1 T:4 steps:1) - _Z80_OPSTATE_STEP_INDIRECT, // BE: CP (HL) (M:2 T:7 steps:4) - 496, // BF: CP A (M:1 T:4 steps:1) - 497, // C0: RET NZ (M:4 T:11 steps:8) - 505, // C1: POP BC (M:3 T:10 steps:7) - 512, // C2: JP NZ,nn (M:3 T:10 steps:7) - 519, // C3: JP nn (M:3 T:10 steps:7) - 526, // C4: CALL NZ,nn (M:6 T:17 steps:14) - 540, // C5: PUSH BC (M:4 T:11 steps:8) - 548, // C6: ADD n (M:2 T:7 steps:4) - 552, // C7: RST 0h (M:4 T:11 steps:8) - 560, // C8: RET Z (M:4 T:11 steps:8) - 568, // C9: RET (M:3 T:10 steps:7) - 575, // CA: JP Z,nn (M:3 T:10 steps:7) - 582, // CB: CB prefix (M:1 T:4 steps:1) - 583, // CC: CALL Z,nn (M:6 T:17 steps:14) - 597, // CD: CALL nn (M:5 T:17 steps:14) - 611, // CE: ADC n (M:2 T:7 steps:4) - 615, // CF: RST 8h (M:4 T:11 steps:8) - 623, // D0: RET NC (M:4 T:11 steps:8) - 631, // D1: POP DE (M:3 T:10 steps:7) - 638, // D2: JP NC,nn (M:3 T:10 steps:7) - 645, // D3: OUT (n),A (M:3 T:11 steps:8) - 653, // D4: CALL NC,nn (M:6 T:17 steps:14) - 667, // D5: PUSH DE (M:4 T:11 steps:8) - 675, // D6: SUB n (M:2 T:7 steps:4) - 679, // D7: RST 10h (M:4 T:11 steps:8) - 687, // D8: RET C (M:4 T:11 steps:8) - 695, // D9: EXX (M:1 T:4 steps:1) - 696, // DA: JP C,nn (M:3 T:10 steps:7) - 703, // DB: IN A,(n) (M:3 T:11 steps:8) - 711, // DC: CALL C,nn (M:6 T:17 steps:14) - 725, // DD: DD prefix (M:1 T:4 steps:1) - 726, // DE: SBC n (M:2 T:7 steps:4) - 730, // DF: RST 18h (M:4 T:11 steps:8) - 738, // E0: RET PO (M:4 T:11 steps:8) - 746, // E1: POP HL (M:3 T:10 steps:7) - 753, // E2: JP PO,nn (M:3 T:10 steps:7) - 760, // E3: EX (SP),HL (M:5 T:19 steps:16) - 776, // E4: CALL PO,nn (M:6 T:17 steps:14) - 790, // E5: PUSH HL (M:4 T:11 steps:8) - 798, // E6: AND n (M:2 T:7 steps:4) - 802, // E7: RST 20h (M:4 T:11 steps:8) - 810, // E8: RET PE (M:4 T:11 steps:8) - 818, // E9: JP HL (M:1 T:4 steps:1) - 819, // EA: JP PE,nn (M:3 T:10 steps:7) - 826, // EB: EX DE,HL (M:1 T:4 steps:1) - 827, // EC: CALL PE,nn (M:6 T:17 steps:14) - 841, // ED: ED prefix (M:1 T:4 steps:1) - 842, // EE: XOR n (M:2 T:7 steps:4) - 846, // EF: RST 28h (M:4 T:11 steps:8) - 854, // F0: RET P (M:4 T:11 steps:8) - 862, // F1: POP AF (M:3 T:10 steps:7) - 869, // F2: JP P,nn (M:3 T:10 steps:7) - 876, // F3: DI (M:1 T:4 steps:1) - 877, // F4: CALL P,nn (M:6 T:17 steps:14) - 891, // F5: PUSH AF (M:4 T:11 steps:8) - 899, // F6: OR n (M:2 T:7 steps:4) - 903, // F7: RST 30h (M:4 T:11 steps:8) - 911, // F8: RET M (M:4 T:11 steps:8) - 919, // F9: LD SP,HL (M:2 T:6 steps:3) - 922, // FA: JP M,nn (M:3 T:10 steps:7) - 929, // FB: EI (M:1 T:4 steps:1) - 930, // FC: CALL M,nn (M:6 T:17 steps:14) - 944, // FD: FD prefix (M:1 T:4 steps:1) - 945, // FE: CP n (M:2 T:7 steps:4) - 949, // FF: RST 38h (M:4 T:11 steps:8) - }; - -static const uint16_t _z80_ed_optable[256] = { - 957, // 00: ED NOP (M:1 T:4 steps:1) - 957, // 01: ED NOP (M:1 T:4 steps:1) - 957, // 02: ED NOP (M:1 T:4 steps:1) - 957, // 03: ED NOP (M:1 T:4 steps:1) - 957, // 04: ED NOP (M:1 T:4 steps:1) - 957, // 05: ED NOP (M:1 T:4 steps:1) - 957, // 06: ED NOP (M:1 T:4 steps:1) - 957, // 07: ED NOP (M:1 T:4 steps:1) - 957, // 08: ED NOP (M:1 T:4 steps:1) - 957, // 09: ED NOP (M:1 T:4 steps:1) - 957, // 0A: ED NOP (M:1 T:4 steps:1) - 957, // 0B: ED NOP (M:1 T:4 steps:1) - 957, // 0C: ED NOP (M:1 T:4 steps:1) - 957, // 0D: ED NOP (M:1 T:4 steps:1) - 957, // 0E: ED NOP (M:1 T:4 steps:1) - 957, // 0F: ED NOP (M:1 T:4 steps:1) - 957, // 10: ED NOP (M:1 T:4 steps:1) - 957, // 11: ED NOP (M:1 T:4 steps:1) - 957, // 12: ED NOP (M:1 T:4 steps:1) - 957, // 13: ED NOP (M:1 T:4 steps:1) - 957, // 14: ED NOP (M:1 T:4 steps:1) - 957, // 15: ED NOP (M:1 T:4 steps:1) - 957, // 16: ED NOP (M:1 T:4 steps:1) - 957, // 17: ED NOP (M:1 T:4 steps:1) - 957, // 18: ED NOP (M:1 T:4 steps:1) - 957, // 19: ED NOP (M:1 T:4 steps:1) - 957, // 1A: ED NOP (M:1 T:4 steps:1) - 957, // 1B: ED NOP (M:1 T:4 steps:1) - 957, // 1C: ED NOP (M:1 T:4 steps:1) - 957, // 1D: ED NOP (M:1 T:4 steps:1) - 957, // 1E: ED NOP (M:1 T:4 steps:1) - 957, // 1F: ED NOP (M:1 T:4 steps:1) - 957, // 20: ED NOP (M:1 T:4 steps:1) - 957, // 21: ED NOP (M:1 T:4 steps:1) - 957, // 22: ED NOP (M:1 T:4 steps:1) - 957, // 23: ED NOP (M:1 T:4 steps:1) - 957, // 24: ED NOP (M:1 T:4 steps:1) - 957, // 25: ED NOP (M:1 T:4 steps:1) - 957, // 26: ED NOP (M:1 T:4 steps:1) - 957, // 27: ED NOP (M:1 T:4 steps:1) - 957, // 28: ED NOP (M:1 T:4 steps:1) - 957, // 29: ED NOP (M:1 T:4 steps:1) - 957, // 2A: ED NOP (M:1 T:4 steps:1) - 957, // 2B: ED NOP (M:1 T:4 steps:1) - 957, // 2C: ED NOP (M:1 T:4 steps:1) - 957, // 2D: ED NOP (M:1 T:4 steps:1) - 957, // 2E: ED NOP (M:1 T:4 steps:1) - 957, // 2F: ED NOP (M:1 T:4 steps:1) - 957, // 30: ED NOP (M:1 T:4 steps:1) - 957, // 31: ED NOP (M:1 T:4 steps:1) - 957, // 32: ED NOP (M:1 T:4 steps:1) - 957, // 33: ED NOP (M:1 T:4 steps:1) - 957, // 34: ED NOP (M:1 T:4 steps:1) - 957, // 35: ED NOP (M:1 T:4 steps:1) - 957, // 36: ED NOP (M:1 T:4 steps:1) - 957, // 37: ED NOP (M:1 T:4 steps:1) - 957, // 38: ED NOP (M:1 T:4 steps:1) - 957, // 39: ED NOP (M:1 T:4 steps:1) - 957, // 3A: ED NOP (M:1 T:4 steps:1) - 957, // 3B: ED NOP (M:1 T:4 steps:1) - 957, // 3C: ED NOP (M:1 T:4 steps:1) - 957, // 3D: ED NOP (M:1 T:4 steps:1) - 957, // 3E: ED NOP (M:1 T:4 steps:1) - 957, // 3F: ED NOP (M:1 T:4 steps:1) - 958, // 40: IN B,(C) (M:2 T:8 steps:5) - 963, // 41: OUT (C),B (M:2 T:8 steps:5) - 968, // 42: SBC HL,BC (M:2 T:11 steps:8) - 976, // 43: LD (nn),BC (M:5 T:16 steps:13) - 989, // 44: NEG (M:1 T:4 steps:1) - 990, // 45: RETN (M:3 T:10 steps:7) - 997, // 46: IM 0 (M:1 T:4 steps:1) - 998, // 47: LD I,A (M:2 T:5 steps:2) - 1000, // 48: IN C,(C) (M:2 T:8 steps:5) - 1005, // 49: OUT (C),C (M:2 T:8 steps:5) - 1010, // 4A: ADC HL,BC (M:2 T:11 steps:8) - 1018, // 4B: LD BC,(nn) (M:5 T:16 steps:13) - 989, // 4C: NEG (M:1 T:4 steps:1) - 1031, // 4D: RETI (M:3 T:10 steps:7) - 1038, // 4E: IM 0 (M:1 T:4 steps:1) - 1039, // 4F: LD R,A (M:2 T:5 steps:2) - 1041, // 50: IN D,(C) (M:2 T:8 steps:5) - 1046, // 51: OUT (C),D (M:2 T:8 steps:5) - 1051, // 52: SBC HL,DE (M:2 T:11 steps:8) - 1059, // 53: LD (nn),DE (M:5 T:16 steps:13) - 989, // 54: NEG (M:1 T:4 steps:1) - 1031, // 55: RETI (M:3 T:10 steps:7) - 1072, // 56: IM 1 (M:1 T:4 steps:1) - 1073, // 57: LD A,I (M:2 T:5 steps:2) - 1075, // 58: IN E,(C) (M:2 T:8 steps:5) - 1080, // 59: OUT (C),E (M:2 T:8 steps:5) - 1085, // 5A: ADC HL,DE (M:2 T:11 steps:8) - 1093, // 5B: LD DE,(nn) (M:5 T:16 steps:13) - 989, // 5C: NEG (M:1 T:4 steps:1) - 1031, // 5D: RETI (M:3 T:10 steps:7) - 1106, // 5E: IM 2 (M:1 T:4 steps:1) - 1107, // 5F: LD A,R (M:2 T:5 steps:2) - 1109, // 60: IN H,(C) (M:2 T:8 steps:5) - 1114, // 61: OUT (C),H (M:2 T:8 steps:5) - 1119, // 62: SBC HL,HL (M:2 T:11 steps:8) - 1127, // 63: LD (nn),HL (M:5 T:16 steps:13) - 989, // 64: NEG (M:1 T:4 steps:1) - 1031, // 65: RETI (M:3 T:10 steps:7) - 1140, // 66: IM 0 (M:1 T:4 steps:1) - 1141, // 67: RRD (M:4 T:14 steps:11) - 1152, // 68: IN L,(C) (M:2 T:8 steps:5) - 1157, // 69: OUT (C),L (M:2 T:8 steps:5) - 1162, // 6A: ADC HL,HL (M:2 T:11 steps:8) - 1170, // 6B: LD HL,(nn) (M:5 T:16 steps:13) - 989, // 6C: NEG (M:1 T:4 steps:1) - 1031, // 6D: RETI (M:3 T:10 steps:7) - 1183, // 6E: IM 0 (M:1 T:4 steps:1) - 1184, // 6F: RLD (M:4 T:14 steps:11) - 1195, // 70: IN (C) (M:2 T:8 steps:5) - 1200, // 71: OUT (C),0 (M:2 T:8 steps:5) - 1205, // 72: SBC HL,SP (M:2 T:11 steps:8) - 1213, // 73: LD (nn),SP (M:5 T:16 steps:13) - 989, // 74: NEG (M:1 T:4 steps:1) - 1031, // 75: RETI (M:3 T:10 steps:7) - 1226, // 76: IM 1 (M:1 T:4 steps:1) - 957, // 77: ED NOP (M:1 T:4 steps:1) - 1227, // 78: IN A,(C) (M:2 T:8 steps:5) - 1232, // 79: OUT (C),A (M:2 T:8 steps:5) - 1237, // 7A: ADC HL,SP (M:2 T:11 steps:8) - 1245, // 7B: LD SP,(nn) (M:5 T:16 steps:13) - 989, // 7C: NEG (M:1 T:4 steps:1) - 1031, // 7D: RETI (M:3 T:10 steps:7) - 1258, // 7E: IM 2 (M:1 T:4 steps:1) - 957, // 7F: ED NOP (M:1 T:4 steps:1) - 957, // 80: ED NOP (M:1 T:4 steps:1) - 957, // 81: ED NOP (M:1 T:4 steps:1) - 957, // 82: ED NOP (M:1 T:4 steps:1) - 957, // 83: ED NOP (M:1 T:4 steps:1) - 957, // 84: ED NOP (M:1 T:4 steps:1) - 957, // 85: ED NOP (M:1 T:4 steps:1) - 957, // 86: ED NOP (M:1 T:4 steps:1) - 957, // 87: ED NOP (M:1 T:4 steps:1) - 957, // 88: ED NOP (M:1 T:4 steps:1) - 957, // 89: ED NOP (M:1 T:4 steps:1) - 957, // 8A: ED NOP (M:1 T:4 steps:1) - 957, // 8B: ED NOP (M:1 T:4 steps:1) - 957, // 8C: ED NOP (M:1 T:4 steps:1) - 957, // 8D: ED NOP (M:1 T:4 steps:1) - 957, // 8E: ED NOP (M:1 T:4 steps:1) - 957, // 8F: ED NOP (M:1 T:4 steps:1) - 957, // 90: ED NOP (M:1 T:4 steps:1) - 957, // 91: ED NOP (M:1 T:4 steps:1) - 957, // 92: ED NOP (M:1 T:4 steps:1) - 957, // 93: ED NOP (M:1 T:4 steps:1) - 957, // 94: ED NOP (M:1 T:4 steps:1) - 957, // 95: ED NOP (M:1 T:4 steps:1) - 957, // 96: ED NOP (M:1 T:4 steps:1) - 957, // 97: ED NOP (M:1 T:4 steps:1) - 957, // 98: ED NOP (M:1 T:4 steps:1) - 957, // 99: ED NOP (M:1 T:4 steps:1) - 957, // 9A: ED NOP (M:1 T:4 steps:1) - 957, // 9B: ED NOP (M:1 T:4 steps:1) - 957, // 9C: ED NOP (M:1 T:4 steps:1) - 957, // 9D: ED NOP (M:1 T:4 steps:1) - 957, // 9E: ED NOP (M:1 T:4 steps:1) - 957, // 9F: ED NOP (M:1 T:4 steps:1) - 1259, // A0: LDI (M:4 T:12 steps:9) - 1268, // A1: CPI (M:3 T:12 steps:9) - 1277, // A2: INI (M:4 T:12 steps:9) - 1286, // A3: OUTI (M:4 T:12 steps:9) - 957, // A4: ED NOP (M:1 T:4 steps:1) - 957, // A5: ED NOP (M:1 T:4 steps:1) - 957, // A6: ED NOP (M:1 T:4 steps:1) - 957, // A7: ED NOP (M:1 T:4 steps:1) - 1295, // A8: LDD (M:4 T:12 steps:9) - 1304, // A9: CPD (M:3 T:12 steps:9) - 1313, // AA: IND (M:4 T:12 steps:9) - 1322, // AB: OUTD (M:4 T:12 steps:9) - 957, // AC: ED NOP (M:1 T:4 steps:1) - 957, // AD: ED NOP (M:1 T:4 steps:1) - 957, // AE: ED NOP (M:1 T:4 steps:1) - 957, // AF: ED NOP (M:1 T:4 steps:1) - 1331, // B0: LDIR (M:5 T:17 steps:14) - 1345, // B1: CPIR (M:4 T:17 steps:14) - 1359, // B2: INIR (M:5 T:17 steps:14) - 1373, // B3: OTIR (M:5 T:17 steps:14) - 957, // B4: ED NOP (M:1 T:4 steps:1) - 957, // B5: ED NOP (M:1 T:4 steps:1) - 957, // B6: ED NOP (M:1 T:4 steps:1) - 957, // B7: ED NOP (M:1 T:4 steps:1) - 1387, // B8: LDDR (M:5 T:17 steps:14) - 1401, // B9: CPDR (M:4 T:17 steps:14) - 1415, // BA: INDR (M:5 T:17 steps:14) - 1429, // BB: OTDR (M:5 T:17 steps:14) - 957, // BC: ED NOP (M:1 T:4 steps:1) - 957, // BD: ED NOP (M:1 T:4 steps:1) - 957, // BE: ED NOP (M:1 T:4 steps:1) - 957, // BF: ED NOP (M:1 T:4 steps:1) - 957, // C0: ED NOP (M:1 T:4 steps:1) - 957, // C1: ED NOP (M:1 T:4 steps:1) - 957, // C2: ED NOP (M:1 T:4 steps:1) - 957, // C3: ED NOP (M:1 T:4 steps:1) - 957, // C4: ED NOP (M:1 T:4 steps:1) - 957, // C5: ED NOP (M:1 T:4 steps:1) - 957, // C6: ED NOP (M:1 T:4 steps:1) - 957, // C7: ED NOP (M:1 T:4 steps:1) - 957, // C8: ED NOP (M:1 T:4 steps:1) - 957, // C9: ED NOP (M:1 T:4 steps:1) - 957, // CA: ED NOP (M:1 T:4 steps:1) - 957, // CB: ED NOP (M:1 T:4 steps:1) - 957, // CC: ED NOP (M:1 T:4 steps:1) - 957, // CD: ED NOP (M:1 T:4 steps:1) - 957, // CE: ED NOP (M:1 T:4 steps:1) - 957, // CF: ED NOP (M:1 T:4 steps:1) - 957, // D0: ED NOP (M:1 T:4 steps:1) - 957, // D1: ED NOP (M:1 T:4 steps:1) - 957, // D2: ED NOP (M:1 T:4 steps:1) - 957, // D3: ED NOP (M:1 T:4 steps:1) - 957, // D4: ED NOP (M:1 T:4 steps:1) - 957, // D5: ED NOP (M:1 T:4 steps:1) - 957, // D6: ED NOP (M:1 T:4 steps:1) - 957, // D7: ED NOP (M:1 T:4 steps:1) - 957, // D8: ED NOP (M:1 T:4 steps:1) - 957, // D9: ED NOP (M:1 T:4 steps:1) - 957, // DA: ED NOP (M:1 T:4 steps:1) - 957, // DB: ED NOP (M:1 T:4 steps:1) - 957, // DC: ED NOP (M:1 T:4 steps:1) - 957, // DD: ED NOP (M:1 T:4 steps:1) - 957, // DE: ED NOP (M:1 T:4 steps:1) - 957, // DF: ED NOP (M:1 T:4 steps:1) - 957, // E0: ED NOP (M:1 T:4 steps:1) - 957, // E1: ED NOP (M:1 T:4 steps:1) - 957, // E2: ED NOP (M:1 T:4 steps:1) - 957, // E3: ED NOP (M:1 T:4 steps:1) - 957, // E4: ED NOP (M:1 T:4 steps:1) - 957, // E5: ED NOP (M:1 T:4 steps:1) - 957, // E6: ED NOP (M:1 T:4 steps:1) - 957, // E7: ED NOP (M:1 T:4 steps:1) - 957, // E8: ED NOP (M:1 T:4 steps:1) - 957, // E9: ED NOP (M:1 T:4 steps:1) - 957, // EA: ED NOP (M:1 T:4 steps:1) - 957, // EB: ED NOP (M:1 T:4 steps:1) - 957, // EC: ED NOP (M:1 T:4 steps:1) - 957, // ED: ED NOP (M:1 T:4 steps:1) - 957, // EE: ED NOP (M:1 T:4 steps:1) - 957, // EF: ED NOP (M:1 T:4 steps:1) - 957, // F0: ED NOP (M:1 T:4 steps:1) - 957, // F1: ED NOP (M:1 T:4 steps:1) - 957, // F2: ED NOP (M:1 T:4 steps:1) - 957, // F3: ED NOP (M:1 T:4 steps:1) - 957, // F4: ED NOP (M:1 T:4 steps:1) - 957, // F5: ED NOP (M:1 T:4 steps:1) - 957, // F6: ED NOP (M:1 T:4 steps:1) - 957, // F7: ED NOP (M:1 T:4 steps:1) - 957, // F8: ED NOP (M:1 T:4 steps:1) - 957, // F9: ED NOP (M:1 T:4 steps:1) - 957, // FA: ED NOP (M:1 T:4 steps:1) - 957, // FB: ED NOP (M:1 T:4 steps:1) - 957, // FC: ED NOP (M:1 T:4 steps:1) - 957, // FD: ED NOP (M:1 T:4 steps:1) - 957, // FE: ED NOP (M:1 T:4 steps:1) - 957, // FF: ED NOP (M:1 T:4 steps:1) - }; - -static const uint16_t _z80_special_optable[_Z80_OPSTATE_NUM_SPECIAL_OPS] = { - 1443, // 00: cb (M:1 T:4 steps:1) - 1444, // 01: cbhl (M:3 T:11 steps:8) - 1452, // 02: ddfdcb (M:6 T:18 steps:15) - 1467, // 03: int_im0 (M:6 T:9 steps:6) - 1473, // 04: int_im1 (M:7 T:16 steps:13) - 1486, // 05: int_im2 (M:9 T:22 steps:19) - 1505, // 06: nmi (M:5 T:14 steps:11) - }; - // initiate refresh cycle static inline uint64_t _z80_refresh(z80_t* cpu, uint64_t pins) { pins = _z80_set_ab_x(pins, cpu->ir, Z80_MREQ|Z80_RFSH); @@ -1696,12 +948,11 @@ static inline uint64_t _z80_fetch(z80_t* cpu, uint64_t pins) { cpu->prefix_active = false; // shortcut no interrupts requested if (cpu->int_bits == 0) { - cpu->step = 0xFFFF; + cpu->step = Z80_M1_T2; return _z80_set_ab_x(pins, cpu->pc++, Z80_M1|Z80_MREQ|Z80_RD); - } - else if (cpu->int_bits & Z80_NMI) { + } else if (cpu->int_bits & Z80_NMI) { // non-maskable interrupt starts with a regular M1 machine cycle - cpu->step = _z80_special_optable[_Z80_OPSTATE_SLOT_NMI]; + cpu->step = Z80_NMI_STEP; cpu->int_bits = 0; if (pins & Z80_HALT) { pins &= ~Z80_HALT; @@ -1709,14 +960,18 @@ static inline uint64_t _z80_fetch(z80_t* cpu, uint64_t pins) { } // NOTE: PC is *not* incremented! return _z80_set_ab_x(pins, cpu->pc, Z80_M1|Z80_MREQ|Z80_RD); - } - else if (cpu->int_bits & Z80_INT) { + } else if (cpu->int_bits & Z80_INT) { if (cpu->iff1) { // maskable interrupts start with a special M1 machine cycle which // doesn't fetch the next opcode, but instead activate the // pins M1|IOQR to request a special byte which is handled differently // depending on interrupt mode - cpu->step = _z80_special_optable[_Z80_OPSTATE_SLOT_INT_IM0 + cpu->im]; + switch (cpu->im) { + case 0: cpu->step = Z80_INT_IM0_STEP; break; + case 1: cpu->step = Z80_INT_IM1_STEP; break; + case 2: cpu->step = Z80_INT_IM2_STEP; break; + default: _Z80_UNREACHABLE; + } cpu->int_bits = 0; if (pins & Z80_HALT) { pins &= ~Z80_HALT; @@ -1724,14 +979,12 @@ static inline uint64_t _z80_fetch(z80_t* cpu, uint64_t pins) { } // NOTE: PC is not incremented, and no pins are activated here return pins; - } - else { + } else { // oops, maskable interrupt requested but disabled - cpu->step = 0xFFFF; + cpu->step = Z80_M1_T2; return _z80_set_ab_x(pins, cpu->pc++, Z80_M1|Z80_MREQ|Z80_RD); } - } - else { + } else { _Z80_UNREACHABLE; return pins; } @@ -1744,35 +997,34 @@ static inline uint64_t _z80_fetch_cb(z80_t* cpu, uint64_t pins) { // execution on the special DDCB/FDCB decoder block which // loads the d-offset first and then the opcode in a // regular memory read machine cycle - cpu->step = _z80_special_optable[_Z80_OPSTATE_SLOT_DDFDCB]; - } - else { + cpu->step = Z80_DDFDCB_STEP; + return pins; + } else { // this is a regular CB-prefixed instruction, continue // execution on a special fetch machine cycle which doesn't // handle DD/FD prefix and then branches either to the // special CB or CBHL decoder block - cpu->step = 21; // => step 22: opcode fetch for CB prefixed instructions - pins = _z80_set_ab_x(pins, cpu->pc++, Z80_M1|Z80_MREQ|Z80_RD); + cpu->step = Z80_CB_M1_T2; // => opcode fetch for CB prefixed instructions + return _z80_set_ab_x(pins, cpu->pc++, Z80_M1|Z80_MREQ|Z80_RD); } - return pins; } static inline uint64_t _z80_fetch_dd(z80_t* cpu, uint64_t pins) { - cpu->step = 2; // => step 3: opcode fetch for DD/FD prefixed instructions + cpu->step = Z80_DDFD_M1_T2; cpu->hlx_idx = 1; cpu->prefix_active = true; return _z80_set_ab_x(pins, cpu->pc++, Z80_M1|Z80_MREQ|Z80_RD); } static inline uint64_t _z80_fetch_fd(z80_t* cpu, uint64_t pins) { - cpu->step = 2; // => step 3: opcode fetch for DD/FD prefixed instructions + cpu->step = Z80_DDFD_M1_T2; cpu->hlx_idx = 2; cpu->prefix_active = true; return _z80_set_ab_x(pins, cpu->pc++, Z80_M1|Z80_MREQ|Z80_RD); } static inline uint64_t _z80_fetch_ed(z80_t* cpu, uint64_t pins) { - cpu->step = 24; // => step 25: opcode fetch for ED prefixed instructions + cpu->step = Z80_ED_M1_T2; cpu->hlx_idx = 0; cpu->prefix_active = true; return _z80_set_ab_x(pins, cpu->pc++, Z80_M1|Z80_MREQ|Z80_RD); @@ -1781,7 +1033,7 @@ static inline uint64_t _z80_fetch_ed(z80_t* cpu, uint64_t pins) { uint64_t z80_prefetch(z80_t* cpu, uint16_t new_pc) { cpu->pc = new_pc; // overlapped M1:T1 of the NOP instruction to initiate opcode fetch at new pc - cpu->step = _z80_optable[0] + 1; + cpu->step = 0; return 0; } @@ -1793,7 +1045,8 @@ uint64_t z80_prefetch(z80_t* cpu, uint16_t new_pc) { #define _gd() _z80_get_db(pins) // high level helper macros -#define _skip(n) cpu->step+=(n); +#define _goto(n) cpu->step=n;goto step_to +#define _fetch() goto fetch_next #define _fetch_dd() pins=_z80_fetch_dd(cpu,pins); #define _fetch_fd() pins=_z80_fetch_fd(cpu,pins); #define _fetch_ed() pins=_z80_fetch_ed(cpu,pins); @@ -1802,7 +1055,7 @@ uint64_t z80_prefetch(z80_t* cpu, uint16_t new_pc) { #define _mwrite(ab,d) _sadx(ab,d,Z80_MREQ|Z80_WR) #define _ioread(ab) _sax(ab,Z80_IORQ|Z80_RD) #define _iowrite(ab,d) _sadx(ab,d,Z80_IORQ|Z80_WR) -#define _wait() {if(pins&Z80_WAIT)goto track_int_bits;} +#define _wait() {if(pins&Z80_WAIT)goto step_to;} #define _cc_nz (!(cpu->f&Z80_ZF)) #define _cc_z (cpu->f&Z80_ZF) #define _cc_nc (!(cpu->f&Z80_CF)) @@ -1815,2950 +1068,1742 @@ uint64_t z80_prefetch(z80_t* cpu, uint16_t new_pc) { uint64_t z80_tick(z80_t* cpu, uint64_t pins) { pins &= ~(Z80_CTRL_PIN_MASK|Z80_RETI); switch (cpu->step) { - //=== shared fetch machine cycle for non-DD/FD-prefixed ops - // M1/T2: load opcode from data bus - case 0: _wait(); cpu->opcode = _gd(); goto step_next; - // M1/T3: refresh cycle - case 1: pins = _z80_refresh(cpu, pins); goto step_next; - // M1/T4: branch to instruction 'payload' - case 2: { - cpu->step = _z80_optable[cpu->opcode]; - // preload effective address for (HL) ops - cpu->addr = cpu->hl; - } goto step_next; + // <% decoder + case 0: _fetch(); // NOP (0) + case 1: _goto(512); // LD BC,nn (0) + case 2: _goto(518); // LD (BC),A (0) + case 3: cpu->bc++;_goto(521); // INC BC (0) + case 4: cpu->b=_z80_inc8(cpu,cpu->b);_fetch(); // INC B (0) + case 5: cpu->b=_z80_dec8(cpu,cpu->b);_fetch(); // DEC B (0) + case 6: _goto(523); // LD B,n (0) + case 7: _z80_rlca(cpu);_fetch(); // RLCA (0) + case 8: _z80_ex_af_af2(cpu);_fetch(); // EX AF,AF' (0) + case 9: _z80_add16(cpu,cpu->bc);_goto(526); // ADD HL,BC (0) + case 10: _goto(533); // LD A,(BC) (0) + case 11: cpu->bc--;_goto(536); // DEC BC (0) + case 12: cpu->c=_z80_inc8(cpu,cpu->c);_fetch(); // INC C (0) + case 13: cpu->c=_z80_dec8(cpu,cpu->c);_fetch(); // DEC C (0) + case 14: _goto(538); // LD C,n (0) + case 15: _z80_rrca(cpu);_fetch(); // RRCA (0) + case 16: _goto(541); // DJNZ d (0) + case 17: _goto(550); // LD DE,nn (0) + case 18: _goto(556); // LD (DE),A (0) + case 19: cpu->de++;_goto(559); // INC DE (0) + case 20: cpu->d=_z80_inc8(cpu,cpu->d);_fetch(); // INC D (0) + case 21: cpu->d=_z80_dec8(cpu,cpu->d);_fetch(); // DEC D (0) + case 22: _goto(561); // LD D,n (0) + case 23: _z80_rla(cpu);_fetch(); // RLA (0) + case 24: _goto(564); // JR d (0) + case 25: _z80_add16(cpu,cpu->de);_goto(572); // ADD HL,DE (0) + case 26: _goto(579); // LD A,(DE) (0) + case 27: cpu->de--;_goto(582); // DEC DE (0) + case 28: cpu->e=_z80_inc8(cpu,cpu->e);_fetch(); // INC E (0) + case 29: cpu->e=_z80_dec8(cpu,cpu->e);_fetch(); // DEC E (0) + case 30: _goto(584); // LD E,n (0) + case 31: _z80_rra(cpu);_fetch(); // RRA (0) + case 32: _goto(587); // JR NZ,d (0) + case 33: _goto(595); // LD HL,nn (0) + case 34: _goto(601); // LD (nn),HL (0) + case 35: cpu->hlx[cpu->hlx_idx].hl++;_goto(613); // INC HL (0) + case 36: cpu->hlx[cpu->hlx_idx].h=_z80_inc8(cpu,cpu->hlx[cpu->hlx_idx].h);_fetch(); // INC H (0) + case 37: cpu->hlx[cpu->hlx_idx].h=_z80_dec8(cpu,cpu->hlx[cpu->hlx_idx].h);_fetch(); // DEC H (0) + case 38: _goto(615); // LD H,n (0) + case 39: _z80_daa(cpu);_fetch(); // DAA (0) + case 40: _goto(618); // JR Z,d (0) + case 41: _z80_add16(cpu,cpu->hlx[cpu->hlx_idx].hl);_goto(626); // ADD HL,HL (0) + case 42: _goto(633); // LD HL,(nn) (0) + case 43: cpu->hlx[cpu->hlx_idx].hl--;_goto(645); // DEC HL (0) + case 44: cpu->hlx[cpu->hlx_idx].l=_z80_inc8(cpu,cpu->hlx[cpu->hlx_idx].l);_fetch(); // INC L (0) + case 45: cpu->hlx[cpu->hlx_idx].l=_z80_dec8(cpu,cpu->hlx[cpu->hlx_idx].l);_fetch(); // DEC L (0) + case 46: _goto(647); // LD L,n (0) + case 47: _z80_cpl(cpu);_fetch(); // CPL (0) + case 48: _goto(650); // JR NC,d (0) + case 49: _goto(658); // LD SP,nn (0) + case 50: _goto(664); // LD (nn),A (0) + case 51: cpu->sp++;_goto(673); // INC SP (0) + case 52: _goto(675); // INC (HL) (0) + case 53: _goto(682); // DEC (HL) (0) + case 54: _goto(689); // LD (HL),n (0) + case 55: _z80_scf(cpu);_fetch(); // SCF (0) + case 56: _goto(695); // JR C,d (0) + case 57: _z80_add16(cpu,cpu->sp);_goto(703); // ADD HL,SP (0) + case 58: _goto(710); // LD A,(nn) (0) + case 59: cpu->sp--;_goto(719); // DEC SP (0) + case 60: cpu->a=_z80_inc8(cpu,cpu->a);_fetch(); // INC A (0) + case 61: cpu->a=_z80_dec8(cpu,cpu->a);_fetch(); // DEC A (0) + case 62: _goto(721); // LD A,n (0) + case 63: _z80_ccf(cpu);_fetch(); // CCF (0) + case 64: cpu->b=cpu->b;_fetch(); // LD B,B (0) + case 65: cpu->b=cpu->c;_fetch(); // LD B,C (0) + case 66: cpu->b=cpu->d;_fetch(); // LD B,D (0) + case 67: cpu->b=cpu->e;_fetch(); // LD B,E (0) + case 68: cpu->b=cpu->hlx[cpu->hlx_idx].h;_fetch(); // LD B,H (0) + case 69: cpu->b=cpu->hlx[cpu->hlx_idx].l;_fetch(); // LD B,L (0) + case 70: _goto(724); // LD B,(HL) (0) + case 71: cpu->b=cpu->a;_fetch(); // LD B,A (0) + case 72: cpu->c=cpu->b;_fetch(); // LD C,B (0) + case 73: cpu->c=cpu->c;_fetch(); // LD C,C (0) + case 74: cpu->c=cpu->d;_fetch(); // LD C,D (0) + case 75: cpu->c=cpu->e;_fetch(); // LD C,E (0) + case 76: cpu->c=cpu->hlx[cpu->hlx_idx].h;_fetch(); // LD C,H (0) + case 77: cpu->c=cpu->hlx[cpu->hlx_idx].l;_fetch(); // LD C,L (0) + case 78: _goto(727); // LD C,(HL) (0) + case 79: cpu->c=cpu->a;_fetch(); // LD C,A (0) + case 80: cpu->d=cpu->b;_fetch(); // LD D,B (0) + case 81: cpu->d=cpu->c;_fetch(); // LD D,C (0) + case 82: cpu->d=cpu->d;_fetch(); // LD D,D (0) + case 83: cpu->d=cpu->e;_fetch(); // LD D,E (0) + case 84: cpu->d=cpu->hlx[cpu->hlx_idx].h;_fetch(); // LD D,H (0) + case 85: cpu->d=cpu->hlx[cpu->hlx_idx].l;_fetch(); // LD D,L (0) + case 86: _goto(730); // LD D,(HL) (0) + case 87: cpu->d=cpu->a;_fetch(); // LD D,A (0) + case 88: cpu->e=cpu->b;_fetch(); // LD E,B (0) + case 89: cpu->e=cpu->c;_fetch(); // LD E,C (0) + case 90: cpu->e=cpu->d;_fetch(); // LD E,D (0) + case 91: cpu->e=cpu->e;_fetch(); // LD E,E (0) + case 92: cpu->e=cpu->hlx[cpu->hlx_idx].h;_fetch(); // LD E,H (0) + case 93: cpu->e=cpu->hlx[cpu->hlx_idx].l;_fetch(); // LD E,L (0) + case 94: _goto(733); // LD E,(HL) (0) + case 95: cpu->e=cpu->a;_fetch(); // LD E,A (0) + case 96: cpu->hlx[cpu->hlx_idx].h=cpu->b;_fetch(); // LD H,B (0) + case 97: cpu->hlx[cpu->hlx_idx].h=cpu->c;_fetch(); // LD H,C (0) + case 98: cpu->hlx[cpu->hlx_idx].h=cpu->d;_fetch(); // LD H,D (0) + case 99: cpu->hlx[cpu->hlx_idx].h=cpu->e;_fetch(); // LD H,E (0) + case 100: cpu->hlx[cpu->hlx_idx].h=cpu->hlx[cpu->hlx_idx].h;_fetch(); // LD H,H (0) + case 101: cpu->hlx[cpu->hlx_idx].h=cpu->hlx[cpu->hlx_idx].l;_fetch(); // LD H,L (0) + case 102: _goto(736); // LD H,(HL) (0) + case 103: cpu->hlx[cpu->hlx_idx].h=cpu->a;_fetch(); // LD H,A (0) + case 104: cpu->hlx[cpu->hlx_idx].l=cpu->b;_fetch(); // LD L,B (0) + case 105: cpu->hlx[cpu->hlx_idx].l=cpu->c;_fetch(); // LD L,C (0) + case 106: cpu->hlx[cpu->hlx_idx].l=cpu->d;_fetch(); // LD L,D (0) + case 107: cpu->hlx[cpu->hlx_idx].l=cpu->e;_fetch(); // LD L,E (0) + case 108: cpu->hlx[cpu->hlx_idx].l=cpu->hlx[cpu->hlx_idx].h;_fetch(); // LD L,H (0) + case 109: cpu->hlx[cpu->hlx_idx].l=cpu->hlx[cpu->hlx_idx].l;_fetch(); // LD L,L (0) + case 110: _goto(739); // LD L,(HL) (0) + case 111: cpu->hlx[cpu->hlx_idx].l=cpu->a;_fetch(); // LD L,A (0) + case 112: _goto(742); // LD (HL),B (0) + case 113: _goto(745); // LD (HL),C (0) + case 114: _goto(748); // LD (HL),D (0) + case 115: _goto(751); // LD (HL),E (0) + case 116: _goto(754); // LD (HL),H (0) + case 117: _goto(757); // LD (HL),L (0) + case 118: pins=_z80_halt(cpu,pins);_fetch(); // HALT (0) + case 119: _goto(760); // LD (HL),A (0) + case 120: cpu->a=cpu->b;_fetch(); // LD A,B (0) + case 121: cpu->a=cpu->c;_fetch(); // LD A,C (0) + case 122: cpu->a=cpu->d;_fetch(); // LD A,D (0) + case 123: cpu->a=cpu->e;_fetch(); // LD A,E (0) + case 124: cpu->a=cpu->hlx[cpu->hlx_idx].h;_fetch(); // LD A,H (0) + case 125: cpu->a=cpu->hlx[cpu->hlx_idx].l;_fetch(); // LD A,L (0) + case 126: _goto(763); // LD A,(HL) (0) + case 127: cpu->a=cpu->a;_fetch(); // LD A,A (0) + case 128: _z80_add8(cpu,cpu->b);_fetch(); // ADD B (0) + case 129: _z80_add8(cpu,cpu->c);_fetch(); // ADD C (0) + case 130: _z80_add8(cpu,cpu->d);_fetch(); // ADD D (0) + case 131: _z80_add8(cpu,cpu->e);_fetch(); // ADD E (0) + case 132: _z80_add8(cpu,cpu->hlx[cpu->hlx_idx].h);_fetch(); // ADD H (0) + case 133: _z80_add8(cpu,cpu->hlx[cpu->hlx_idx].l);_fetch(); // ADD L (0) + case 134: _goto(766); // ADD (HL) (0) + case 135: _z80_add8(cpu,cpu->a);_fetch(); // ADD A (0) + case 136: _z80_adc8(cpu,cpu->b);_fetch(); // ADC B (0) + case 137: _z80_adc8(cpu,cpu->c);_fetch(); // ADC C (0) + case 138: _z80_adc8(cpu,cpu->d);_fetch(); // ADC D (0) + case 139: _z80_adc8(cpu,cpu->e);_fetch(); // ADC E (0) + case 140: _z80_adc8(cpu,cpu->hlx[cpu->hlx_idx].h);_fetch(); // ADC H (0) + case 141: _z80_adc8(cpu,cpu->hlx[cpu->hlx_idx].l);_fetch(); // ADC L (0) + case 142: _goto(769); // ADC (HL) (0) + case 143: _z80_adc8(cpu,cpu->a);_fetch(); // ADC A (0) + case 144: _z80_sub8(cpu,cpu->b);_fetch(); // SUB B (0) + case 145: _z80_sub8(cpu,cpu->c);_fetch(); // SUB C (0) + case 146: _z80_sub8(cpu,cpu->d);_fetch(); // SUB D (0) + case 147: _z80_sub8(cpu,cpu->e);_fetch(); // SUB E (0) + case 148: _z80_sub8(cpu,cpu->hlx[cpu->hlx_idx].h);_fetch(); // SUB H (0) + case 149: _z80_sub8(cpu,cpu->hlx[cpu->hlx_idx].l);_fetch(); // SUB L (0) + case 150: _goto(772); // SUB (HL) (0) + case 151: _z80_sub8(cpu,cpu->a);_fetch(); // SUB A (0) + case 152: _z80_sbc8(cpu,cpu->b);_fetch(); // SBC B (0) + case 153: _z80_sbc8(cpu,cpu->c);_fetch(); // SBC C (0) + case 154: _z80_sbc8(cpu,cpu->d);_fetch(); // SBC D (0) + case 155: _z80_sbc8(cpu,cpu->e);_fetch(); // SBC E (0) + case 156: _z80_sbc8(cpu,cpu->hlx[cpu->hlx_idx].h);_fetch(); // SBC H (0) + case 157: _z80_sbc8(cpu,cpu->hlx[cpu->hlx_idx].l);_fetch(); // SBC L (0) + case 158: _goto(775); // SBC (HL) (0) + case 159: _z80_sbc8(cpu,cpu->a);_fetch(); // SBC A (0) + case 160: _z80_and8(cpu,cpu->b);_fetch(); // AND B (0) + case 161: _z80_and8(cpu,cpu->c);_fetch(); // AND C (0) + case 162: _z80_and8(cpu,cpu->d);_fetch(); // AND D (0) + case 163: _z80_and8(cpu,cpu->e);_fetch(); // AND E (0) + case 164: _z80_and8(cpu,cpu->hlx[cpu->hlx_idx].h);_fetch(); // AND H (0) + case 165: _z80_and8(cpu,cpu->hlx[cpu->hlx_idx].l);_fetch(); // AND L (0) + case 166: _goto(778); // AND (HL) (0) + case 167: _z80_and8(cpu,cpu->a);_fetch(); // AND A (0) + case 168: _z80_xor8(cpu,cpu->b);_fetch(); // XOR B (0) + case 169: _z80_xor8(cpu,cpu->c);_fetch(); // XOR C (0) + case 170: _z80_xor8(cpu,cpu->d);_fetch(); // XOR D (0) + case 171: _z80_xor8(cpu,cpu->e);_fetch(); // XOR E (0) + case 172: _z80_xor8(cpu,cpu->hlx[cpu->hlx_idx].h);_fetch(); // XOR H (0) + case 173: _z80_xor8(cpu,cpu->hlx[cpu->hlx_idx].l);_fetch(); // XOR L (0) + case 174: _goto(781); // XOR (HL) (0) + case 175: _z80_xor8(cpu,cpu->a);_fetch(); // XOR A (0) + case 176: _z80_or8(cpu,cpu->b);_fetch(); // OR B (0) + case 177: _z80_or8(cpu,cpu->c);_fetch(); // OR C (0) + case 178: _z80_or8(cpu,cpu->d);_fetch(); // OR D (0) + case 179: _z80_or8(cpu,cpu->e);_fetch(); // OR E (0) + case 180: _z80_or8(cpu,cpu->hlx[cpu->hlx_idx].h);_fetch(); // OR H (0) + case 181: _z80_or8(cpu,cpu->hlx[cpu->hlx_idx].l);_fetch(); // OR L (0) + case 182: _goto(784); // OR (HL) (0) + case 183: _z80_or8(cpu,cpu->a);_fetch(); // OR A (0) + case 184: _z80_cp8(cpu,cpu->b);_fetch(); // CP B (0) + case 185: _z80_cp8(cpu,cpu->c);_fetch(); // CP C (0) + case 186: _z80_cp8(cpu,cpu->d);_fetch(); // CP D (0) + case 187: _z80_cp8(cpu,cpu->e);_fetch(); // CP E (0) + case 188: _z80_cp8(cpu,cpu->hlx[cpu->hlx_idx].h);_fetch(); // CP H (0) + case 189: _z80_cp8(cpu,cpu->hlx[cpu->hlx_idx].l);_fetch(); // CP L (0) + case 190: _goto(787); // CP (HL) (0) + case 191: _z80_cp8(cpu,cpu->a);_fetch(); // CP A (0) + case 192: if(!_cc_nz){_goto(790+6);};_goto(790); // RET NZ (0) + case 193: _goto(797); // POP BC (0) + case 194: _goto(803); // JP NZ,nn (0) + case 195: _goto(809); // JP nn (0) + case 196: _goto(815); // CALL NZ,nn (0) + case 197: _goto(828); // PUSH BC (0) + case 198: _goto(835); // ADD n (0) + case 199: _goto(838); // RST 0h (0) + case 200: if(!_cc_z){_goto(845+6);};_goto(845); // RET Z (0) + case 201: _goto(852); // RET (0) + case 202: _goto(858); // JP Z,nn (0) + case 203: _fetch_cb();goto step_to; // CB prefix (0) + case 204: _goto(864); // CALL Z,nn (0) + case 205: _goto(877); // CALL nn (0) + case 206: _goto(890); // ADC n (0) + case 207: _goto(893); // RST 8h (0) + case 208: if(!_cc_nc){_goto(900+6);};_goto(900); // RET NC (0) + case 209: _goto(907); // POP DE (0) + case 210: _goto(913); // JP NC,nn (0) + case 211: _goto(919); // OUT (n),A (0) + case 212: _goto(926); // CALL NC,nn (0) + case 213: _goto(939); // PUSH DE (0) + case 214: _goto(946); // SUB n (0) + case 215: _goto(949); // RST 10h (0) + case 216: if(!_cc_c){_goto(956+6);};_goto(956); // RET C (0) + case 217: _z80_exx(cpu);_fetch(); // EXX (0) + case 218: _goto(963); // JP C,nn (0) + case 219: _goto(969); // IN A,(n) (0) + case 220: _goto(976); // CALL C,nn (0) + case 221: _fetch_dd();goto step_to; // DD prefix (0) + case 222: _goto(989); // SBC n (0) + case 223: _goto(992); // RST 18h (0) + case 224: if(!_cc_po){_goto(999+6);};_goto(999); // RET PO (0) + case 225: _goto(1006); // POP HL (0) + case 226: _goto(1012); // JP PO,nn (0) + case 227: _goto(1018); // EX (SP),HL (0) + case 228: _goto(1033); // CALL PO,nn (0) + case 229: _goto(1046); // PUSH HL (0) + case 230: _goto(1053); // AND n (0) + case 231: _goto(1056); // RST 20h (0) + case 232: if(!_cc_pe){_goto(1063+6);};_goto(1063); // RET PE (0) + case 233: cpu->pc=cpu->hlx[cpu->hlx_idx].hl;_fetch(); // JP HL (0) + case 234: _goto(1070); // JP PE,nn (0) + case 235: _z80_ex_de_hl(cpu);_fetch(); // EX DE,HL (0) + case 236: _goto(1076); // CALL PE,nn (0) + case 237: _fetch_ed();goto step_to; // ED prefix (0) + case 238: _goto(1089); // XOR n (0) + case 239: _goto(1092); // RST 28h (0) + case 240: if(!_cc_p){_goto(1099+6);};_goto(1099); // RET P (0) + case 241: _goto(1106); // POP AF (0) + case 242: _goto(1112); // JP P,nn (0) + case 243: cpu->iff1=cpu->iff2=false;_fetch(); // DI (0) + case 244: _goto(1118); // CALL P,nn (0) + case 245: _goto(1131); // PUSH AF (0) + case 246: _goto(1138); // OR n (0) + case 247: _goto(1141); // RST 30h (0) + case 248: if(!_cc_m){_goto(1148+6);};_goto(1148); // RET M (0) + case 249: cpu->sp=cpu->hlx[cpu->hlx_idx].hl;_goto(1155); // LD SP,HL (0) + case 250: _goto(1157); // JP M,nn (0) + case 251: cpu->iff1=cpu->iff2=false;pins=_z80_fetch(cpu,pins);cpu->iff1=cpu->iff2=true;goto step_to; // EI (0) + case 252: _goto(1163); // CALL M,nn (0) + case 253: _fetch_fd();goto step_to; // FD prefix (0) + case 254: _goto(1176); // CP n (0) + case 255: _goto(1179); // RST 38h (0) + case 256: _fetch(); // ED NOP (0) + case 257: _fetch(); // ED NOP (0) + case 258: _fetch(); // ED NOP (0) + case 259: _fetch(); // ED NOP (0) + case 260: _fetch(); // ED NOP (0) + case 261: _fetch(); // ED NOP (0) + case 262: _fetch(); // ED NOP (0) + case 263: _fetch(); // ED NOP (0) + case 264: _fetch(); // ED NOP (0) + case 265: _fetch(); // ED NOP (0) + case 266: _fetch(); // ED NOP (0) + case 267: _fetch(); // ED NOP (0) + case 268: _fetch(); // ED NOP (0) + case 269: _fetch(); // ED NOP (0) + case 270: _fetch(); // ED NOP (0) + case 271: _fetch(); // ED NOP (0) + case 272: _fetch(); // ED NOP (0) + case 273: _fetch(); // ED NOP (0) + case 274: _fetch(); // ED NOP (0) + case 275: _fetch(); // ED NOP (0) + case 276: _fetch(); // ED NOP (0) + case 277: _fetch(); // ED NOP (0) + case 278: _fetch(); // ED NOP (0) + case 279: _fetch(); // ED NOP (0) + case 280: _fetch(); // ED NOP (0) + case 281: _fetch(); // ED NOP (0) + case 282: _fetch(); // ED NOP (0) + case 283: _fetch(); // ED NOP (0) + case 284: _fetch(); // ED NOP (0) + case 285: _fetch(); // ED NOP (0) + case 286: _fetch(); // ED NOP (0) + case 287: _fetch(); // ED NOP (0) + case 288: _fetch(); // ED NOP (0) + case 289: _fetch(); // ED NOP (0) + case 290: _fetch(); // ED NOP (0) + case 291: _fetch(); // ED NOP (0) + case 292: _fetch(); // ED NOP (0) + case 293: _fetch(); // ED NOP (0) + case 294: _fetch(); // ED NOP (0) + case 295: _fetch(); // ED NOP (0) + case 296: _fetch(); // ED NOP (0) + case 297: _fetch(); // ED NOP (0) + case 298: _fetch(); // ED NOP (0) + case 299: _fetch(); // ED NOP (0) + case 300: _fetch(); // ED NOP (0) + case 301: _fetch(); // ED NOP (0) + case 302: _fetch(); // ED NOP (0) + case 303: _fetch(); // ED NOP (0) + case 304: _fetch(); // ED NOP (0) + case 305: _fetch(); // ED NOP (0) + case 306: _fetch(); // ED NOP (0) + case 307: _fetch(); // ED NOP (0) + case 308: _fetch(); // ED NOP (0) + case 309: _fetch(); // ED NOP (0) + case 310: _fetch(); // ED NOP (0) + case 311: _fetch(); // ED NOP (0) + case 312: _fetch(); // ED NOP (0) + case 313: _fetch(); // ED NOP (0) + case 314: _fetch(); // ED NOP (0) + case 315: _fetch(); // ED NOP (0) + case 316: _fetch(); // ED NOP (0) + case 317: _fetch(); // ED NOP (0) + case 318: _fetch(); // ED NOP (0) + case 319: _fetch(); // ED NOP (0) + case 320: _goto(1186); // IN B,(C) (0) + case 321: _goto(1190); // OUT (C),B (0) + case 322: _z80_sbc16(cpu,cpu->bc);_goto(1194); // SBC HL,BC (0) + case 323: _goto(1201); // LD (nn),BC (0) + case 324: _z80_neg8(cpu);_fetch(); // NEG (0) + case 325: _goto(1213); // RETN (0) + case 326: cpu->im=0;_fetch(); // IM 0 (0) + case 327: _goto(1219); // LD I,A (0) + case 328: _goto(1220); // IN C,(C) (0) + case 329: _goto(1224); // OUT (C),C (0) + case 330: _z80_adc16(cpu,cpu->bc);_goto(1228); // ADC HL,BC (0) + case 331: _goto(1235); // LD BC,(nn) (0) + case 332: _z80_neg8(cpu);_fetch(); // NEG (0) + case 333: _goto(1247); // RETI (0) + case 334: cpu->im=0;_fetch(); // IM 0 (0) + case 335: _goto(1253); // LD R,A (0) + case 336: _goto(1254); // IN D,(C) (0) + case 337: _goto(1258); // OUT (C),D (0) + case 338: _z80_sbc16(cpu,cpu->de);_goto(1262); // SBC HL,DE (0) + case 339: _goto(1269); // LD (nn),DE (0) + case 340: _z80_neg8(cpu);_fetch(); // NEG (0) + case 341: _goto(1247); // RETI (0) + case 342: cpu->im=1;_fetch(); // IM 1 (0) + case 343: _goto(1282); // LD A,I (0) + case 344: _goto(1283); // IN E,(C) (0) + case 345: _goto(1287); // OUT (C),E (0) + case 346: _z80_adc16(cpu,cpu->de);_goto(1291); // ADC HL,DE (0) + case 347: _goto(1298); // LD DE,(nn) (0) + case 348: _z80_neg8(cpu);_fetch(); // NEG (0) + case 349: _goto(1247); // RETI (0) + case 350: cpu->im=2;_fetch(); // IM 2 (0) + case 351: _goto(1311); // LD A,R (0) + case 352: _goto(1312); // IN H,(C) (0) + case 353: _goto(1316); // OUT (C),H (0) + case 354: _z80_sbc16(cpu,cpu->hl);_goto(1320); // SBC HL,HL (0) + case 355: _goto(1327); // LD (nn),HL (0) + case 356: _z80_neg8(cpu);_fetch(); // NEG (0) + case 357: _goto(1247); // RETI (0) + case 358: cpu->im=0;_fetch(); // IM 0 (0) + case 359: _goto(1340); // RRD (0) + case 360: _goto(1350); // IN L,(C) (0) + case 361: _goto(1354); // OUT (C),L (0) + case 362: _z80_adc16(cpu,cpu->hl);_goto(1358); // ADC HL,HL (0) + case 363: _goto(1365); // LD HL,(nn) (0) + case 364: _z80_neg8(cpu);_fetch(); // NEG (0) + case 365: _goto(1247); // RETI (0) + case 366: cpu->im=0;_fetch(); // IM 0 (0) + case 367: _goto(1378); // RLD (0) + case 368: _goto(1388); // IN (C) (0) + case 369: _goto(1392); // OUT (C),0 (0) + case 370: _z80_sbc16(cpu,cpu->sp);_goto(1396); // SBC HL,SP (0) + case 371: _goto(1403); // LD (nn),SP (0) + case 372: _z80_neg8(cpu);_fetch(); // NEG (0) + case 373: _goto(1247); // RETI (0) + case 374: cpu->im=1;_fetch(); // IM 1 (0) + case 375: _fetch(); // ED NOP (0) + case 376: _goto(1416); // IN A,(C) (0) + case 377: _goto(1420); // OUT (C),A (0) + case 378: _z80_adc16(cpu,cpu->sp);_goto(1424); // ADC HL,SP (0) + case 379: _goto(1431); // LD SP,(nn) (0) + case 380: _z80_neg8(cpu);_fetch(); // NEG (0) + case 381: _goto(1247); // RETI (0) + case 382: cpu->im=2;_fetch(); // IM 2 (0) + case 383: _fetch(); // ED NOP (0) + case 384: _fetch(); // ED NOP (0) + case 385: _fetch(); // ED NOP (0) + case 386: _fetch(); // ED NOP (0) + case 387: _fetch(); // ED NOP (0) + case 388: _fetch(); // ED NOP (0) + case 389: _fetch(); // ED NOP (0) + case 390: _fetch(); // ED NOP (0) + case 391: _fetch(); // ED NOP (0) + case 392: _fetch(); // ED NOP (0) + case 393: _fetch(); // ED NOP (0) + case 394: _fetch(); // ED NOP (0) + case 395: _fetch(); // ED NOP (0) + case 396: _fetch(); // ED NOP (0) + case 397: _fetch(); // ED NOP (0) + case 398: _fetch(); // ED NOP (0) + case 399: _fetch(); // ED NOP (0) + case 400: _fetch(); // ED NOP (0) + case 401: _fetch(); // ED NOP (0) + case 402: _fetch(); // ED NOP (0) + case 403: _fetch(); // ED NOP (0) + case 404: _fetch(); // ED NOP (0) + case 405: _fetch(); // ED NOP (0) + case 406: _fetch(); // ED NOP (0) + case 407: _fetch(); // ED NOP (0) + case 408: _fetch(); // ED NOP (0) + case 409: _fetch(); // ED NOP (0) + case 410: _fetch(); // ED NOP (0) + case 411: _fetch(); // ED NOP (0) + case 412: _fetch(); // ED NOP (0) + case 413: _fetch(); // ED NOP (0) + case 414: _fetch(); // ED NOP (0) + case 415: _fetch(); // ED NOP (0) + case 416: _goto(1444); // LDI (0) + case 417: _goto(1452); // CPI (0) + case 418: _goto(1460); // INI (0) + case 419: _goto(1468); // OUTI (0) + case 420: _fetch(); // ED NOP (0) + case 421: _fetch(); // ED NOP (0) + case 422: _fetch(); // ED NOP (0) + case 423: _fetch(); // ED NOP (0) + case 424: _goto(1476); // LDD (0) + case 425: _goto(1484); // CPD (0) + case 426: _goto(1492); // IND (0) + case 427: _goto(1500); // OUTD (0) + case 428: _fetch(); // ED NOP (0) + case 429: _fetch(); // ED NOP (0) + case 430: _fetch(); // ED NOP (0) + case 431: _fetch(); // ED NOP (0) + case 432: _goto(1508); // LDIR (0) + case 433: _goto(1521); // CPIR (0) + case 434: _goto(1534); // INIR (0) + case 435: _goto(1547); // OTIR (0) + case 436: _fetch(); // ED NOP (0) + case 437: _fetch(); // ED NOP (0) + case 438: _fetch(); // ED NOP (0) + case 439: _fetch(); // ED NOP (0) + case 440: _goto(1560); // LDDR (0) + case 441: _goto(1573); // CPDR (0) + case 442: _goto(1586); // INDR (0) + case 443: _goto(1599); // OTDR (0) + case 444: _fetch(); // ED NOP (0) + case 445: _fetch(); // ED NOP (0) + case 446: _fetch(); // ED NOP (0) + case 447: _fetch(); // ED NOP (0) + case 448: _fetch(); // ED NOP (0) + case 449: _fetch(); // ED NOP (0) + case 450: _fetch(); // ED NOP (0) + case 451: _fetch(); // ED NOP (0) + case 452: _fetch(); // ED NOP (0) + case 453: _fetch(); // ED NOP (0) + case 454: _fetch(); // ED NOP (0) + case 455: _fetch(); // ED NOP (0) + case 456: _fetch(); // ED NOP (0) + case 457: _fetch(); // ED NOP (0) + case 458: _fetch(); // ED NOP (0) + case 459: _fetch(); // ED NOP (0) + case 460: _fetch(); // ED NOP (0) + case 461: _fetch(); // ED NOP (0) + case 462: _fetch(); // ED NOP (0) + case 463: _fetch(); // ED NOP (0) + case 464: _fetch(); // ED NOP (0) + case 465: _fetch(); // ED NOP (0) + case 466: _fetch(); // ED NOP (0) + case 467: _fetch(); // ED NOP (0) + case 468: _fetch(); // ED NOP (0) + case 469: _fetch(); // ED NOP (0) + case 470: _fetch(); // ED NOP (0) + case 471: _fetch(); // ED NOP (0) + case 472: _fetch(); // ED NOP (0) + case 473: _fetch(); // ED NOP (0) + case 474: _fetch(); // ED NOP (0) + case 475: _fetch(); // ED NOP (0) + case 476: _fetch(); // ED NOP (0) + case 477: _fetch(); // ED NOP (0) + case 478: _fetch(); // ED NOP (0) + case 479: _fetch(); // ED NOP (0) + case 480: _fetch(); // ED NOP (0) + case 481: _fetch(); // ED NOP (0) + case 482: _fetch(); // ED NOP (0) + case 483: _fetch(); // ED NOP (0) + case 484: _fetch(); // ED NOP (0) + case 485: _fetch(); // ED NOP (0) + case 486: _fetch(); // ED NOP (0) + case 487: _fetch(); // ED NOP (0) + case 488: _fetch(); // ED NOP (0) + case 489: _fetch(); // ED NOP (0) + case 490: _fetch(); // ED NOP (0) + case 491: _fetch(); // ED NOP (0) + case 492: _fetch(); // ED NOP (0) + case 493: _fetch(); // ED NOP (0) + case 494: _fetch(); // ED NOP (0) + case 495: _fetch(); // ED NOP (0) + case 496: _fetch(); // ED NOP (0) + case 497: _fetch(); // ED NOP (0) + case 498: _fetch(); // ED NOP (0) + case 499: _fetch(); // ED NOP (0) + case 500: _fetch(); // ED NOP (0) + case 501: _fetch(); // ED NOP (0) + case 502: _fetch(); // ED NOP (0) + case 503: _fetch(); // ED NOP (0) + case 504: _fetch(); // ED NOP (0) + case 505: _fetch(); // ED NOP (0) + case 506: _fetch(); // ED NOP (0) + case 507: _fetch(); // ED NOP (0) + case 508: _fetch(); // ED NOP (0) + case 509: _fetch(); // ED NOP (0) + case 510: _fetch(); // ED NOP (0) + case 511: _fetch(); // ED NOP (0) + case 512: _wait();_mread(cpu->pc++);_goto(513); // LD BC,nn (1) + case 513: cpu->c=_gd();_goto(514); // LD BC,nn (2) + case 514: _goto(515); // LD BC,nn (3) + case 515: _wait();_mread(cpu->pc++);_goto(516); // LD BC,nn (4) + case 516: cpu->b=_gd();_goto(517); // LD BC,nn (5) + case 517: _fetch(); // LD BC,nn (6) + case 518: _wait();_mwrite(cpu->bc,cpu->a);cpu->wzl=cpu->c+1;cpu->wzh=cpu->a;_goto(519); // LD (BC),A (1) + case 519: _goto(520); // LD (BC),A (2) + case 520: _fetch(); // LD (BC),A (3) + case 521: _goto(522); // INC BC (1) + case 522: _fetch(); // INC BC (2) + case 523: _wait();_mread(cpu->pc++);_goto(524); // LD B,n (1) + case 524: cpu->b=_gd();_goto(525); // LD B,n (2) + case 525: _fetch(); // LD B,n (3) + case 526: _goto(527); // ADD HL,BC (1) + case 527: _goto(528); // ADD HL,BC (2) + case 528: _goto(529); // ADD HL,BC (3) + case 529: _goto(530); // ADD HL,BC (4) + case 530: _goto(531); // ADD HL,BC (5) + case 531: _goto(532); // ADD HL,BC (6) + case 532: _fetch(); // ADD HL,BC (7) + case 533: _wait();_mread(cpu->bc);_goto(534); // LD A,(BC) (1) + case 534: cpu->a=_gd();cpu->wz=cpu->bc+1;_goto(535); // LD A,(BC) (2) + case 535: _fetch(); // LD A,(BC) (3) + case 536: _goto(537); // DEC BC (1) + case 537: _fetch(); // DEC BC (2) + case 538: _wait();_mread(cpu->pc++);_goto(539); // LD C,n (1) + case 539: cpu->c=_gd();_goto(540); // LD C,n (2) + case 540: _fetch(); // LD C,n (3) + case 541: _goto(542); // DJNZ d (1) + case 542: _wait();_mread(cpu->pc++);_goto(543); // DJNZ d (2) + case 543: cpu->dlatch=_gd();if(--cpu->b==0){_goto(544+5);};_goto(544); // DJNZ d (3) + case 544: cpu->pc+=(int8_t)cpu->dlatch;cpu->wz=cpu->pc;_goto(545); // DJNZ d (4) + case 545: _goto(546); // DJNZ d (5) + case 546: _goto(547); // DJNZ d (6) + case 547: _goto(548); // DJNZ d (7) + case 548: _goto(549); // DJNZ d (8) + case 549: _fetch(); // DJNZ d (9) + case 550: _wait();_mread(cpu->pc++);_goto(551); // LD DE,nn (1) + case 551: cpu->e=_gd();_goto(552); // LD DE,nn (2) + case 552: _goto(553); // LD DE,nn (3) + case 553: _wait();_mread(cpu->pc++);_goto(554); // LD DE,nn (4) + case 554: cpu->d=_gd();_goto(555); // LD DE,nn (5) + case 555: _fetch(); // LD DE,nn (6) + case 556: _wait();_mwrite(cpu->de,cpu->a);cpu->wzl=cpu->e+1;cpu->wzh=cpu->a;_goto(557); // LD (DE),A (1) + case 557: _goto(558); // LD (DE),A (2) + case 558: _fetch(); // LD (DE),A (3) + case 559: _goto(560); // INC DE (1) + case 560: _fetch(); // INC DE (2) + case 561: _wait();_mread(cpu->pc++);_goto(562); // LD D,n (1) + case 562: cpu->d=_gd();_goto(563); // LD D,n (2) + case 563: _fetch(); // LD D,n (3) + case 564: _wait();_mread(cpu->pc++);_goto(565); // JR d (1) + case 565: cpu->dlatch=_gd();_goto(566); // JR d (2) + case 566: cpu->pc+=(int8_t)cpu->dlatch;cpu->wz=cpu->pc;_goto(567); // JR d (3) + case 567: _goto(568); // JR d (4) + case 568: _goto(569); // JR d (5) + case 569: _goto(570); // JR d (6) + case 570: _goto(571); // JR d (7) + case 571: _fetch(); // JR d (8) + case 572: _goto(573); // ADD HL,DE (1) + case 573: _goto(574); // ADD HL,DE (2) + case 574: _goto(575); // ADD HL,DE (3) + case 575: _goto(576); // ADD HL,DE (4) + case 576: _goto(577); // ADD HL,DE (5) + case 577: _goto(578); // ADD HL,DE (6) + case 578: _fetch(); // ADD HL,DE (7) + case 579: _wait();_mread(cpu->de);_goto(580); // LD A,(DE) (1) + case 580: cpu->a=_gd();cpu->wz=cpu->de+1;_goto(581); // LD A,(DE) (2) + case 581: _fetch(); // LD A,(DE) (3) + case 582: _goto(583); // DEC DE (1) + case 583: _fetch(); // DEC DE (2) + case 584: _wait();_mread(cpu->pc++);_goto(585); // LD E,n (1) + case 585: cpu->e=_gd();_goto(586); // LD E,n (2) + case 586: _fetch(); // LD E,n (3) + case 587: _wait();_mread(cpu->pc++);_goto(588); // JR NZ,d (1) + case 588: cpu->dlatch=_gd();if(!(_cc_nz)){_goto(589+5);};_goto(589); // JR NZ,d (2) + case 589: cpu->pc+=(int8_t)cpu->dlatch;cpu->wz=cpu->pc;_goto(590); // JR NZ,d (3) + case 590: _goto(591); // JR NZ,d (4) + case 591: _goto(592); // JR NZ,d (5) + case 592: _goto(593); // JR NZ,d (6) + case 593: _goto(594); // JR NZ,d (7) + case 594: _fetch(); // JR NZ,d (8) + case 595: _wait();_mread(cpu->pc++);_goto(596); // LD HL,nn (1) + case 596: cpu->hlx[cpu->hlx_idx].l=_gd();_goto(597); // LD HL,nn (2) + case 597: _goto(598); // LD HL,nn (3) + case 598: _wait();_mread(cpu->pc++);_goto(599); // LD HL,nn (4) + case 599: cpu->hlx[cpu->hlx_idx].h=_gd();_goto(600); // LD HL,nn (5) + case 600: _fetch(); // LD HL,nn (6) + case 601: _wait();_mread(cpu->pc++);_goto(602); // LD (nn),HL (1) + case 602: cpu->wzl=_gd();_goto(603); // LD (nn),HL (2) + case 603: _goto(604); // LD (nn),HL (3) + case 604: _wait();_mread(cpu->pc++);_goto(605); // LD (nn),HL (4) + case 605: cpu->wzh=_gd();_goto(606); // LD (nn),HL (5) + case 606: _goto(607); // LD (nn),HL (6) + case 607: _wait();_mwrite(cpu->wz++,cpu->hlx[cpu->hlx_idx].l);_goto(608); // LD (nn),HL (7) + case 608: _goto(609); // LD (nn),HL (8) + case 609: _goto(610); // LD (nn),HL (9) + case 610: _wait();_mwrite(cpu->wz,cpu->hlx[cpu->hlx_idx].h);_goto(611); // LD (nn),HL (10) + case 611: _goto(612); // LD (nn),HL (11) + case 612: _fetch(); // LD (nn),HL (12) + case 613: _goto(614); // INC HL (1) + case 614: _fetch(); // INC HL (2) + case 615: _wait();_mread(cpu->pc++);_goto(616); // LD H,n (1) + case 616: cpu->hlx[cpu->hlx_idx].h=_gd();_goto(617); // LD H,n (2) + case 617: _fetch(); // LD H,n (3) + case 618: _wait();_mread(cpu->pc++);_goto(619); // JR Z,d (1) + case 619: cpu->dlatch=_gd();if(!(_cc_z)){_goto(620+5);};_goto(620); // JR Z,d (2) + case 620: cpu->pc+=(int8_t)cpu->dlatch;cpu->wz=cpu->pc;_goto(621); // JR Z,d (3) + case 621: _goto(622); // JR Z,d (4) + case 622: _goto(623); // JR Z,d (5) + case 623: _goto(624); // JR Z,d (6) + case 624: _goto(625); // JR Z,d (7) + case 625: _fetch(); // JR Z,d (8) + case 626: _goto(627); // ADD HL,HL (1) + case 627: _goto(628); // ADD HL,HL (2) + case 628: _goto(629); // ADD HL,HL (3) + case 629: _goto(630); // ADD HL,HL (4) + case 630: _goto(631); // ADD HL,HL (5) + case 631: _goto(632); // ADD HL,HL (6) + case 632: _fetch(); // ADD HL,HL (7) + case 633: _wait();_mread(cpu->pc++);_goto(634); // LD HL,(nn) (1) + case 634: cpu->wzl=_gd();_goto(635); // LD HL,(nn) (2) + case 635: _goto(636); // LD HL,(nn) (3) + case 636: _wait();_mread(cpu->pc++);_goto(637); // LD HL,(nn) (4) + case 637: cpu->wzh=_gd();_goto(638); // LD HL,(nn) (5) + case 638: _goto(639); // LD HL,(nn) (6) + case 639: _wait();_mread(cpu->wz++);_goto(640); // LD HL,(nn) (7) + case 640: cpu->hlx[cpu->hlx_idx].l=_gd();_goto(641); // LD HL,(nn) (8) + case 641: _goto(642); // LD HL,(nn) (9) + case 642: _wait();_mread(cpu->wz);_goto(643); // LD HL,(nn) (10) + case 643: cpu->hlx[cpu->hlx_idx].h=_gd();_goto(644); // LD HL,(nn) (11) + case 644: _fetch(); // LD HL,(nn) (12) + case 645: _goto(646); // DEC HL (1) + case 646: _fetch(); // DEC HL (2) + case 647: _wait();_mread(cpu->pc++);_goto(648); // LD L,n (1) + case 648: cpu->hlx[cpu->hlx_idx].l=_gd();_goto(649); // LD L,n (2) + case 649: _fetch(); // LD L,n (3) + case 650: _wait();_mread(cpu->pc++);_goto(651); // JR NC,d (1) + case 651: cpu->dlatch=_gd();if(!(_cc_nc)){_goto(652+5);};_goto(652); // JR NC,d (2) + case 652: cpu->pc+=(int8_t)cpu->dlatch;cpu->wz=cpu->pc;_goto(653); // JR NC,d (3) + case 653: _goto(654); // JR NC,d (4) + case 654: _goto(655); // JR NC,d (5) + case 655: _goto(656); // JR NC,d (6) + case 656: _goto(657); // JR NC,d (7) + case 657: _fetch(); // JR NC,d (8) + case 658: _wait();_mread(cpu->pc++);_goto(659); // LD SP,nn (1) + case 659: cpu->spl=_gd();_goto(660); // LD SP,nn (2) + case 660: _goto(661); // LD SP,nn (3) + case 661: _wait();_mread(cpu->pc++);_goto(662); // LD SP,nn (4) + case 662: cpu->sph=_gd();_goto(663); // LD SP,nn (5) + case 663: _fetch(); // LD SP,nn (6) + case 664: _wait();_mread(cpu->pc++);_goto(665); // LD (nn),A (1) + case 665: cpu->wzl=_gd();_goto(666); // LD (nn),A (2) + case 666: _goto(667); // LD (nn),A (3) + case 667: _wait();_mread(cpu->pc++);_goto(668); // LD (nn),A (4) + case 668: cpu->wzh=_gd();_goto(669); // LD (nn),A (5) + case 669: _goto(670); // LD (nn),A (6) + case 670: _wait();_mwrite(cpu->wz++,cpu->a);cpu->wzh=cpu->a;_goto(671); // LD (nn),A (7) + case 671: _goto(672); // LD (nn),A (8) + case 672: _fetch(); // LD (nn),A (9) + case 673: _goto(674); // INC SP (1) + case 674: _fetch(); // INC SP (2) + case 675: _wait();_mread(cpu->addr);_goto(676); // INC (HL) (1) + case 676: cpu->dlatch=_gd();cpu->dlatch=_z80_inc8(cpu,cpu->dlatch);_goto(677); // INC (HL) (2) + case 677: _goto(678); // INC (HL) (3) + case 678: _goto(679); // INC (HL) (4) + case 679: _wait();_mwrite(cpu->addr,cpu->dlatch);_goto(680); // INC (HL) (5) + case 680: _goto(681); // INC (HL) (6) + case 681: _fetch(); // INC (HL) (7) + case 682: _wait();_mread(cpu->addr);_goto(683); // DEC (HL) (1) + case 683: cpu->dlatch=_gd();cpu->dlatch=_z80_dec8(cpu,cpu->dlatch);_goto(684); // DEC (HL) (2) + case 684: _goto(685); // DEC (HL) (3) + case 685: _goto(686); // DEC (HL) (4) + case 686: _wait();_mwrite(cpu->addr,cpu->dlatch);_goto(687); // DEC (HL) (5) + case 687: _goto(688); // DEC (HL) (6) + case 688: _fetch(); // DEC (HL) (7) + case 689: _wait();_mread(cpu->pc++);_goto(690); // LD (HL),n (1) + case 690: cpu->dlatch=_gd();_goto(691); // LD (HL),n (2) + case 691: _goto(692); // LD (HL),n (3) + case 692: _wait();_mwrite(cpu->addr,cpu->dlatch);_goto(693); // LD (HL),n (4) + case 693: _goto(694); // LD (HL),n (5) + case 694: _fetch(); // LD (HL),n (6) + case 695: _wait();_mread(cpu->pc++);_goto(696); // JR C,d (1) + case 696: cpu->dlatch=_gd();if(!(_cc_c)){_goto(697+5);};_goto(697); // JR C,d (2) + case 697: cpu->pc+=(int8_t)cpu->dlatch;cpu->wz=cpu->pc;_goto(698); // JR C,d (3) + case 698: _goto(699); // JR C,d (4) + case 699: _goto(700); // JR C,d (5) + case 700: _goto(701); // JR C,d (6) + case 701: _goto(702); // JR C,d (7) + case 702: _fetch(); // JR C,d (8) + case 703: _goto(704); // ADD HL,SP (1) + case 704: _goto(705); // ADD HL,SP (2) + case 705: _goto(706); // ADD HL,SP (3) + case 706: _goto(707); // ADD HL,SP (4) + case 707: _goto(708); // ADD HL,SP (5) + case 708: _goto(709); // ADD HL,SP (6) + case 709: _fetch(); // ADD HL,SP (7) + case 710: _wait();_mread(cpu->pc++);_goto(711); // LD A,(nn) (1) + case 711: cpu->wzl=_gd();_goto(712); // LD A,(nn) (2) + case 712: _goto(713); // LD A,(nn) (3) + case 713: _wait();_mread(cpu->pc++);_goto(714); // LD A,(nn) (4) + case 714: cpu->wzh=_gd();_goto(715); // LD A,(nn) (5) + case 715: _goto(716); // LD A,(nn) (6) + case 716: _wait();_mread(cpu->wz++);_goto(717); // LD A,(nn) (7) + case 717: cpu->a=_gd();_goto(718); // LD A,(nn) (8) + case 718: _fetch(); // LD A,(nn) (9) + case 719: _goto(720); // DEC SP (1) + case 720: _fetch(); // DEC SP (2) + case 721: _wait();_mread(cpu->pc++);_goto(722); // LD A,n (1) + case 722: cpu->a=_gd();_goto(723); // LD A,n (2) + case 723: _fetch(); // LD A,n (3) + case 724: _wait();_mread(cpu->addr);_goto(725); // LD B,(HL) (1) + case 725: cpu->b=_gd();_goto(726); // LD B,(HL) (2) + case 726: _fetch(); // LD B,(HL) (3) + case 727: _wait();_mread(cpu->addr);_goto(728); // LD C,(HL) (1) + case 728: cpu->c=_gd();_goto(729); // LD C,(HL) (2) + case 729: _fetch(); // LD C,(HL) (3) + case 730: _wait();_mread(cpu->addr);_goto(731); // LD D,(HL) (1) + case 731: cpu->d=_gd();_goto(732); // LD D,(HL) (2) + case 732: _fetch(); // LD D,(HL) (3) + case 733: _wait();_mread(cpu->addr);_goto(734); // LD E,(HL) (1) + case 734: cpu->e=_gd();_goto(735); // LD E,(HL) (2) + case 735: _fetch(); // LD E,(HL) (3) + case 736: _wait();_mread(cpu->addr);_goto(737); // LD H,(HL) (1) + case 737: cpu->h=_gd();_goto(738); // LD H,(HL) (2) + case 738: _fetch(); // LD H,(HL) (3) + case 739: _wait();_mread(cpu->addr);_goto(740); // LD L,(HL) (1) + case 740: cpu->l=_gd();_goto(741); // LD L,(HL) (2) + case 741: _fetch(); // LD L,(HL) (3) + case 742: _wait();_mwrite(cpu->addr,cpu->b);_goto(743); // LD (HL),B (1) + case 743: _goto(744); // LD (HL),B (2) + case 744: _fetch(); // LD (HL),B (3) + case 745: _wait();_mwrite(cpu->addr,cpu->c);_goto(746); // LD (HL),C (1) + case 746: _goto(747); // LD (HL),C (2) + case 747: _fetch(); // LD (HL),C (3) + case 748: _wait();_mwrite(cpu->addr,cpu->d);_goto(749); // LD (HL),D (1) + case 749: _goto(750); // LD (HL),D (2) + case 750: _fetch(); // LD (HL),D (3) + case 751: _wait();_mwrite(cpu->addr,cpu->e);_goto(752); // LD (HL),E (1) + case 752: _goto(753); // LD (HL),E (2) + case 753: _fetch(); // LD (HL),E (3) + case 754: _wait();_mwrite(cpu->addr,cpu->h);_goto(755); // LD (HL),H (1) + case 755: _goto(756); // LD (HL),H (2) + case 756: _fetch(); // LD (HL),H (3) + case 757: _wait();_mwrite(cpu->addr,cpu->l);_goto(758); // LD (HL),L (1) + case 758: _goto(759); // LD (HL),L (2) + case 759: _fetch(); // LD (HL),L (3) + case 760: _wait();_mwrite(cpu->addr,cpu->a);_goto(761); // LD (HL),A (1) + case 761: _goto(762); // LD (HL),A (2) + case 762: _fetch(); // LD (HL),A (3) + case 763: _wait();_mread(cpu->addr);_goto(764); // LD A,(HL) (1) + case 764: cpu->a=_gd();_goto(765); // LD A,(HL) (2) + case 765: _fetch(); // LD A,(HL) (3) + case 766: _wait();_mread(cpu->addr);_goto(767); // ADD (HL) (1) + case 767: cpu->dlatch=_gd();_goto(768); // ADD (HL) (2) + case 768: _z80_add8(cpu,cpu->dlatch);_fetch(); // ADD (HL) (3) + case 769: _wait();_mread(cpu->addr);_goto(770); // ADC (HL) (1) + case 770: cpu->dlatch=_gd();_goto(771); // ADC (HL) (2) + case 771: _z80_adc8(cpu,cpu->dlatch);_fetch(); // ADC (HL) (3) + case 772: _wait();_mread(cpu->addr);_goto(773); // SUB (HL) (1) + case 773: cpu->dlatch=_gd();_goto(774); // SUB (HL) (2) + case 774: _z80_sub8(cpu,cpu->dlatch);_fetch(); // SUB (HL) (3) + case 775: _wait();_mread(cpu->addr);_goto(776); // SBC (HL) (1) + case 776: cpu->dlatch=_gd();_goto(777); // SBC (HL) (2) + case 777: _z80_sbc8(cpu,cpu->dlatch);_fetch(); // SBC (HL) (3) + case 778: _wait();_mread(cpu->addr);_goto(779); // AND (HL) (1) + case 779: cpu->dlatch=_gd();_goto(780); // AND (HL) (2) + case 780: _z80_and8(cpu,cpu->dlatch);_fetch(); // AND (HL) (3) + case 781: _wait();_mread(cpu->addr);_goto(782); // XOR (HL) (1) + case 782: cpu->dlatch=_gd();_goto(783); // XOR (HL) (2) + case 783: _z80_xor8(cpu,cpu->dlatch);_fetch(); // XOR (HL) (3) + case 784: _wait();_mread(cpu->addr);_goto(785); // OR (HL) (1) + case 785: cpu->dlatch=_gd();_goto(786); // OR (HL) (2) + case 786: _z80_or8(cpu,cpu->dlatch);_fetch(); // OR (HL) (3) + case 787: _wait();_mread(cpu->addr);_goto(788); // CP (HL) (1) + case 788: cpu->dlatch=_gd();_goto(789); // CP (HL) (2) + case 789: _z80_cp8(cpu,cpu->dlatch);_fetch(); // CP (HL) (3) + case 790: _goto(791); // RET NZ (1) + case 791: _wait();_mread(cpu->sp++);_goto(792); // RET NZ (2) + case 792: cpu->wzl=_gd();_goto(793); // RET NZ (3) + case 793: _goto(794); // RET NZ (4) + case 794: _wait();_mread(cpu->sp++);_goto(795); // RET NZ (5) + case 795: cpu->wzh=_gd();cpu->pc=cpu->wz;_goto(796); // RET NZ (6) + case 796: _fetch(); // RET NZ (7) + case 797: _wait();_mread(cpu->sp++);_goto(798); // POP BC (1) + case 798: cpu->c=_gd();_goto(799); // POP BC (2) + case 799: _goto(800); // POP BC (3) + case 800: _wait();_mread(cpu->sp++);_goto(801); // POP BC (4) + case 801: cpu->b=_gd();_goto(802); // POP BC (5) + case 802: _fetch(); // POP BC (6) + case 803: _wait();_mread(cpu->pc++);_goto(804); // JP NZ,nn (1) + case 804: cpu->wzl=_gd();_goto(805); // JP NZ,nn (2) + case 805: _goto(806); // JP NZ,nn (3) + case 806: _wait();_mread(cpu->pc++);_goto(807); // JP NZ,nn (4) + case 807: cpu->wzh=_gd();if(_cc_nz){cpu->pc=cpu->wz;};_goto(808); // JP NZ,nn (5) + case 808: _fetch(); // JP NZ,nn (6) + case 809: _wait();_mread(cpu->pc++);_goto(810); // JP nn (1) + case 810: cpu->wzl=_gd();_goto(811); // JP nn (2) + case 811: _goto(812); // JP nn (3) + case 812: _wait();_mread(cpu->pc++);_goto(813); // JP nn (4) + case 813: cpu->wzh=_gd();cpu->pc=cpu->wz;_goto(814); // JP nn (5) + case 814: _fetch(); // JP nn (6) + case 815: _wait();_mread(cpu->pc++);_goto(816); // CALL NZ,nn (1) + case 816: cpu->wzl=_gd();_goto(817); // CALL NZ,nn (2) + case 817: _goto(818); // CALL NZ,nn (3) + case 818: _wait();_mread(cpu->pc++);_goto(819); // CALL NZ,nn (4) + case 819: cpu->wzh=_gd();if (!_cc_nz){_goto(820+7);};_goto(820); // CALL NZ,nn (5) + case 820: _goto(821); // CALL NZ,nn (6) + case 821: _goto(822); // CALL NZ,nn (7) + case 822: _wait();_mwrite(--cpu->sp,cpu->pch);_goto(823); // CALL NZ,nn (8) + case 823: _goto(824); // CALL NZ,nn (9) + case 824: _goto(825); // CALL NZ,nn (10) + case 825: _wait();_mwrite(--cpu->sp,cpu->pcl);cpu->pc=cpu->wz;_goto(826); // CALL NZ,nn (11) + case 826: _goto(827); // CALL NZ,nn (12) + case 827: _fetch(); // CALL NZ,nn (13) + case 828: _goto(829); // PUSH BC (1) + case 829: _wait();_mwrite(--cpu->sp,cpu->b);_goto(830); // PUSH BC (2) + case 830: _goto(831); // PUSH BC (3) + case 831: _goto(832); // PUSH BC (4) + case 832: _wait();_mwrite(--cpu->sp,cpu->c);_goto(833); // PUSH BC (5) + case 833: _goto(834); // PUSH BC (6) + case 834: _fetch(); // PUSH BC (7) + case 835: _wait();_mread(cpu->pc++);_goto(836); // ADD n (1) + case 836: cpu->dlatch=_gd();_goto(837); // ADD n (2) + case 837: _z80_add8(cpu,cpu->dlatch);_fetch(); // ADD n (3) + case 838: _goto(839); // RST 0h (1) + case 839: _wait();_mwrite(--cpu->sp,cpu->pch);_goto(840); // RST 0h (2) + case 840: _goto(841); // RST 0h (3) + case 841: _goto(842); // RST 0h (4) + case 842: _wait();_mwrite(--cpu->sp,cpu->pcl);cpu->wz=0x00;cpu->pc=cpu->wz;_goto(843); // RST 0h (5) + case 843: _goto(844); // RST 0h (6) + case 844: _fetch(); // RST 0h (7) + case 845: _goto(846); // RET Z (1) + case 846: _wait();_mread(cpu->sp++);_goto(847); // RET Z (2) + case 847: cpu->wzl=_gd();_goto(848); // RET Z (3) + case 848: _goto(849); // RET Z (4) + case 849: _wait();_mread(cpu->sp++);_goto(850); // RET Z (5) + case 850: cpu->wzh=_gd();cpu->pc=cpu->wz;_goto(851); // RET Z (6) + case 851: _fetch(); // RET Z (7) + case 852: _wait();_mread(cpu->sp++);_goto(853); // RET (1) + case 853: cpu->wzl=_gd();_goto(854); // RET (2) + case 854: _goto(855); // RET (3) + case 855: _wait();_mread(cpu->sp++);_goto(856); // RET (4) + case 856: cpu->wzh=_gd();cpu->pc=cpu->wz;_goto(857); // RET (5) + case 857: _fetch(); // RET (6) + case 858: _wait();_mread(cpu->pc++);_goto(859); // JP Z,nn (1) + case 859: cpu->wzl=_gd();_goto(860); // JP Z,nn (2) + case 860: _goto(861); // JP Z,nn (3) + case 861: _wait();_mread(cpu->pc++);_goto(862); // JP Z,nn (4) + case 862: cpu->wzh=_gd();if(_cc_z){cpu->pc=cpu->wz;};_goto(863); // JP Z,nn (5) + case 863: _fetch(); // JP Z,nn (6) + case 864: _wait();_mread(cpu->pc++);_goto(865); // CALL Z,nn (1) + case 865: cpu->wzl=_gd();_goto(866); // CALL Z,nn (2) + case 866: _goto(867); // CALL Z,nn (3) + case 867: _wait();_mread(cpu->pc++);_goto(868); // CALL Z,nn (4) + case 868: cpu->wzh=_gd();if (!_cc_z){_goto(869+7);};_goto(869); // CALL Z,nn (5) + case 869: _goto(870); // CALL Z,nn (6) + case 870: _goto(871); // CALL Z,nn (7) + case 871: _wait();_mwrite(--cpu->sp,cpu->pch);_goto(872); // CALL Z,nn (8) + case 872: _goto(873); // CALL Z,nn (9) + case 873: _goto(874); // CALL Z,nn (10) + case 874: _wait();_mwrite(--cpu->sp,cpu->pcl);cpu->pc=cpu->wz;_goto(875); // CALL Z,nn (11) + case 875: _goto(876); // CALL Z,nn (12) + case 876: _fetch(); // CALL Z,nn (13) + case 877: _wait();_mread(cpu->pc++);_goto(878); // CALL nn (1) + case 878: cpu->wzl=_gd();_goto(879); // CALL nn (2) + case 879: _goto(880); // CALL nn (3) + case 880: _wait();_mread(cpu->pc++);_goto(881); // CALL nn (4) + case 881: cpu->wzh=_gd();_goto(882); // CALL nn (5) + case 882: _goto(883); // CALL nn (6) + case 883: _goto(884); // CALL nn (7) + case 884: _wait();_mwrite(--cpu->sp,cpu->pch);_goto(885); // CALL nn (8) + case 885: _goto(886); // CALL nn (9) + case 886: _goto(887); // CALL nn (10) + case 887: _wait();_mwrite(--cpu->sp,cpu->pcl);cpu->pc=cpu->wz;_goto(888); // CALL nn (11) + case 888: _goto(889); // CALL nn (12) + case 889: _fetch(); // CALL nn (13) + case 890: _wait();_mread(cpu->pc++);_goto(891); // ADC n (1) + case 891: cpu->dlatch=_gd();_goto(892); // ADC n (2) + case 892: _z80_adc8(cpu,cpu->dlatch);_fetch(); // ADC n (3) + case 893: _goto(894); // RST 8h (1) + case 894: _wait();_mwrite(--cpu->sp,cpu->pch);_goto(895); // RST 8h (2) + case 895: _goto(896); // RST 8h (3) + case 896: _goto(897); // RST 8h (4) + case 897: _wait();_mwrite(--cpu->sp,cpu->pcl);cpu->wz=0x08;cpu->pc=cpu->wz;_goto(898); // RST 8h (5) + case 898: _goto(899); // RST 8h (6) + case 899: _fetch(); // RST 8h (7) + case 900: _goto(901); // RET NC (1) + case 901: _wait();_mread(cpu->sp++);_goto(902); // RET NC (2) + case 902: cpu->wzl=_gd();_goto(903); // RET NC (3) + case 903: _goto(904); // RET NC (4) + case 904: _wait();_mread(cpu->sp++);_goto(905); // RET NC (5) + case 905: cpu->wzh=_gd();cpu->pc=cpu->wz;_goto(906); // RET NC (6) + case 906: _fetch(); // RET NC (7) + case 907: _wait();_mread(cpu->sp++);_goto(908); // POP DE (1) + case 908: cpu->e=_gd();_goto(909); // POP DE (2) + case 909: _goto(910); // POP DE (3) + case 910: _wait();_mread(cpu->sp++);_goto(911); // POP DE (4) + case 911: cpu->d=_gd();_goto(912); // POP DE (5) + case 912: _fetch(); // POP DE (6) + case 913: _wait();_mread(cpu->pc++);_goto(914); // JP NC,nn (1) + case 914: cpu->wzl=_gd();_goto(915); // JP NC,nn (2) + case 915: _goto(916); // JP NC,nn (3) + case 916: _wait();_mread(cpu->pc++);_goto(917); // JP NC,nn (4) + case 917: cpu->wzh=_gd();if(_cc_nc){cpu->pc=cpu->wz;};_goto(918); // JP NC,nn (5) + case 918: _fetch(); // JP NC,nn (6) + case 919: _wait();_mread(cpu->pc++);_goto(920); // OUT (n),A (1) + case 920: cpu->wzl=_gd();cpu->wzh=cpu->a;_goto(921); // OUT (n),A (2) + case 921: _goto(922); // OUT (n),A (3) + case 922: _iowrite(cpu->wz,cpu->a);_goto(923); // OUT (n),A (4) + case 923: _wait();cpu->wzl++;_goto(924); // OUT (n),A (5) + case 924: _goto(925); // OUT (n),A (6) + case 925: _fetch(); // OUT (n),A (7) + case 926: _wait();_mread(cpu->pc++);_goto(927); // CALL NC,nn (1) + case 927: cpu->wzl=_gd();_goto(928); // CALL NC,nn (2) + case 928: _goto(929); // CALL NC,nn (3) + case 929: _wait();_mread(cpu->pc++);_goto(930); // CALL NC,nn (4) + case 930: cpu->wzh=_gd();if (!_cc_nc){_goto(931+7);};_goto(931); // CALL NC,nn (5) + case 931: _goto(932); // CALL NC,nn (6) + case 932: _goto(933); // CALL NC,nn (7) + case 933: _wait();_mwrite(--cpu->sp,cpu->pch);_goto(934); // CALL NC,nn (8) + case 934: _goto(935); // CALL NC,nn (9) + case 935: _goto(936); // CALL NC,nn (10) + case 936: _wait();_mwrite(--cpu->sp,cpu->pcl);cpu->pc=cpu->wz;_goto(937); // CALL NC,nn (11) + case 937: _goto(938); // CALL NC,nn (12) + case 938: _fetch(); // CALL NC,nn (13) + case 939: _goto(940); // PUSH DE (1) + case 940: _wait();_mwrite(--cpu->sp,cpu->d);_goto(941); // PUSH DE (2) + case 941: _goto(942); // PUSH DE (3) + case 942: _goto(943); // PUSH DE (4) + case 943: _wait();_mwrite(--cpu->sp,cpu->e);_goto(944); // PUSH DE (5) + case 944: _goto(945); // PUSH DE (6) + case 945: _fetch(); // PUSH DE (7) + case 946: _wait();_mread(cpu->pc++);_goto(947); // SUB n (1) + case 947: cpu->dlatch=_gd();_goto(948); // SUB n (2) + case 948: _z80_sub8(cpu,cpu->dlatch);_fetch(); // SUB n (3) + case 949: _goto(950); // RST 10h (1) + case 950: _wait();_mwrite(--cpu->sp,cpu->pch);_goto(951); // RST 10h (2) + case 951: _goto(952); // RST 10h (3) + case 952: _goto(953); // RST 10h (4) + case 953: _wait();_mwrite(--cpu->sp,cpu->pcl);cpu->wz=0x10;cpu->pc=cpu->wz;_goto(954); // RST 10h (5) + case 954: _goto(955); // RST 10h (6) + case 955: _fetch(); // RST 10h (7) + case 956: _goto(957); // RET C (1) + case 957: _wait();_mread(cpu->sp++);_goto(958); // RET C (2) + case 958: cpu->wzl=_gd();_goto(959); // RET C (3) + case 959: _goto(960); // RET C (4) + case 960: _wait();_mread(cpu->sp++);_goto(961); // RET C (5) + case 961: cpu->wzh=_gd();cpu->pc=cpu->wz;_goto(962); // RET C (6) + case 962: _fetch(); // RET C (7) + case 963: _wait();_mread(cpu->pc++);_goto(964); // JP C,nn (1) + case 964: cpu->wzl=_gd();_goto(965); // JP C,nn (2) + case 965: _goto(966); // JP C,nn (3) + case 966: _wait();_mread(cpu->pc++);_goto(967); // JP C,nn (4) + case 967: cpu->wzh=_gd();if(_cc_c){cpu->pc=cpu->wz;};_goto(968); // JP C,nn (5) + case 968: _fetch(); // JP C,nn (6) + case 969: _wait();_mread(cpu->pc++);_goto(970); // IN A,(n) (1) + case 970: cpu->wzl=_gd();cpu->wzh=cpu->a;_goto(971); // IN A,(n) (2) + case 971: _goto(972); // IN A,(n) (3) + case 972: _goto(973); // IN A,(n) (4) + case 973: _wait();_ioread(cpu->wz++);_goto(974); // IN A,(n) (5) + case 974: cpu->a=_gd();_goto(975); // IN A,(n) (6) + case 975: _fetch(); // IN A,(n) (7) + case 976: _wait();_mread(cpu->pc++);_goto(977); // CALL C,nn (1) + case 977: cpu->wzl=_gd();_goto(978); // CALL C,nn (2) + case 978: _goto(979); // CALL C,nn (3) + case 979: _wait();_mread(cpu->pc++);_goto(980); // CALL C,nn (4) + case 980: cpu->wzh=_gd();if (!_cc_c){_goto(981+7);};_goto(981); // CALL C,nn (5) + case 981: _goto(982); // CALL C,nn (6) + case 982: _goto(983); // CALL C,nn (7) + case 983: _wait();_mwrite(--cpu->sp,cpu->pch);_goto(984); // CALL C,nn (8) + case 984: _goto(985); // CALL C,nn (9) + case 985: _goto(986); // CALL C,nn (10) + case 986: _wait();_mwrite(--cpu->sp,cpu->pcl);cpu->pc=cpu->wz;_goto(987); // CALL C,nn (11) + case 987: _goto(988); // CALL C,nn (12) + case 988: _fetch(); // CALL C,nn (13) + case 989: _wait();_mread(cpu->pc++);_goto(990); // SBC n (1) + case 990: cpu->dlatch=_gd();_goto(991); // SBC n (2) + case 991: _z80_sbc8(cpu,cpu->dlatch);_fetch(); // SBC n (3) + case 992: _goto(993); // RST 18h (1) + case 993: _wait();_mwrite(--cpu->sp,cpu->pch);_goto(994); // RST 18h (2) + case 994: _goto(995); // RST 18h (3) + case 995: _goto(996); // RST 18h (4) + case 996: _wait();_mwrite(--cpu->sp,cpu->pcl);cpu->wz=0x18;cpu->pc=cpu->wz;_goto(997); // RST 18h (5) + case 997: _goto(998); // RST 18h (6) + case 998: _fetch(); // RST 18h (7) + case 999: _goto(1000); // RET PO (1) + case 1000: _wait();_mread(cpu->sp++);_goto(1001); // RET PO (2) + case 1001: cpu->wzl=_gd();_goto(1002); // RET PO (3) + case 1002: _goto(1003); // RET PO (4) + case 1003: _wait();_mread(cpu->sp++);_goto(1004); // RET PO (5) + case 1004: cpu->wzh=_gd();cpu->pc=cpu->wz;_goto(1005); // RET PO (6) + case 1005: _fetch(); // RET PO (7) + case 1006: _wait();_mread(cpu->sp++);_goto(1007); // POP HL (1) + case 1007: cpu->hlx[cpu->hlx_idx].l=_gd();_goto(1008); // POP HL (2) + case 1008: _goto(1009); // POP HL (3) + case 1009: _wait();_mread(cpu->sp++);_goto(1010); // POP HL (4) + case 1010: cpu->hlx[cpu->hlx_idx].h=_gd();_goto(1011); // POP HL (5) + case 1011: _fetch(); // POP HL (6) + case 1012: _wait();_mread(cpu->pc++);_goto(1013); // JP PO,nn (1) + case 1013: cpu->wzl=_gd();_goto(1014); // JP PO,nn (2) + case 1014: _goto(1015); // JP PO,nn (3) + case 1015: _wait();_mread(cpu->pc++);_goto(1016); // JP PO,nn (4) + case 1016: cpu->wzh=_gd();if(_cc_po){cpu->pc=cpu->wz;};_goto(1017); // JP PO,nn (5) + case 1017: _fetch(); // JP PO,nn (6) + case 1018: _wait();_mread(cpu->sp);_goto(1019); // EX (SP),HL (1) + case 1019: cpu->wzl=_gd();_goto(1020); // EX (SP),HL (2) + case 1020: _goto(1021); // EX (SP),HL (3) + case 1021: _wait();_mread(cpu->sp+1);_goto(1022); // EX (SP),HL (4) + case 1022: cpu->wzh=_gd();_goto(1023); // EX (SP),HL (5) + case 1023: _goto(1024); // EX (SP),HL (6) + case 1024: _goto(1025); // EX (SP),HL (7) + case 1025: _wait();_mwrite(cpu->sp+1,cpu->hlx[cpu->hlx_idx].h);_goto(1026); // EX (SP),HL (8) + case 1026: _goto(1027); // EX (SP),HL (9) + case 1027: _goto(1028); // EX (SP),HL (10) + case 1028: _wait();_mwrite(cpu->sp,cpu->hlx[cpu->hlx_idx].l);cpu->hlx[cpu->hlx_idx].hl=cpu->wz;_goto(1029); // EX (SP),HL (11) + case 1029: _goto(1030); // EX (SP),HL (12) + case 1030: _goto(1031); // EX (SP),HL (13) + case 1031: _goto(1032); // EX (SP),HL (14) + case 1032: _fetch(); // EX (SP),HL (15) + case 1033: _wait();_mread(cpu->pc++);_goto(1034); // CALL PO,nn (1) + case 1034: cpu->wzl=_gd();_goto(1035); // CALL PO,nn (2) + case 1035: _goto(1036); // CALL PO,nn (3) + case 1036: _wait();_mread(cpu->pc++);_goto(1037); // CALL PO,nn (4) + case 1037: cpu->wzh=_gd();if (!_cc_po){_goto(1038+7);};_goto(1038); // CALL PO,nn (5) + case 1038: _goto(1039); // CALL PO,nn (6) + case 1039: _goto(1040); // CALL PO,nn (7) + case 1040: _wait();_mwrite(--cpu->sp,cpu->pch);_goto(1041); // CALL PO,nn (8) + case 1041: _goto(1042); // CALL PO,nn (9) + case 1042: _goto(1043); // CALL PO,nn (10) + case 1043: _wait();_mwrite(--cpu->sp,cpu->pcl);cpu->pc=cpu->wz;_goto(1044); // CALL PO,nn (11) + case 1044: _goto(1045); // CALL PO,nn (12) + case 1045: _fetch(); // CALL PO,nn (13) + case 1046: _goto(1047); // PUSH HL (1) + case 1047: _wait();_mwrite(--cpu->sp,cpu->hlx[cpu->hlx_idx].h);_goto(1048); // PUSH HL (2) + case 1048: _goto(1049); // PUSH HL (3) + case 1049: _goto(1050); // PUSH HL (4) + case 1050: _wait();_mwrite(--cpu->sp,cpu->hlx[cpu->hlx_idx].l);_goto(1051); // PUSH HL (5) + case 1051: _goto(1052); // PUSH HL (6) + case 1052: _fetch(); // PUSH HL (7) + case 1053: _wait();_mread(cpu->pc++);_goto(1054); // AND n (1) + case 1054: cpu->dlatch=_gd();_goto(1055); // AND n (2) + case 1055: _z80_and8(cpu,cpu->dlatch);_fetch(); // AND n (3) + case 1056: _goto(1057); // RST 20h (1) + case 1057: _wait();_mwrite(--cpu->sp,cpu->pch);_goto(1058); // RST 20h (2) + case 1058: _goto(1059); // RST 20h (3) + case 1059: _goto(1060); // RST 20h (4) + case 1060: _wait();_mwrite(--cpu->sp,cpu->pcl);cpu->wz=0x20;cpu->pc=cpu->wz;_goto(1061); // RST 20h (5) + case 1061: _goto(1062); // RST 20h (6) + case 1062: _fetch(); // RST 20h (7) + case 1063: _goto(1064); // RET PE (1) + case 1064: _wait();_mread(cpu->sp++);_goto(1065); // RET PE (2) + case 1065: cpu->wzl=_gd();_goto(1066); // RET PE (3) + case 1066: _goto(1067); // RET PE (4) + case 1067: _wait();_mread(cpu->sp++);_goto(1068); // RET PE (5) + case 1068: cpu->wzh=_gd();cpu->pc=cpu->wz;_goto(1069); // RET PE (6) + case 1069: _fetch(); // RET PE (7) + case 1070: _wait();_mread(cpu->pc++);_goto(1071); // JP PE,nn (1) + case 1071: cpu->wzl=_gd();_goto(1072); // JP PE,nn (2) + case 1072: _goto(1073); // JP PE,nn (3) + case 1073: _wait();_mread(cpu->pc++);_goto(1074); // JP PE,nn (4) + case 1074: cpu->wzh=_gd();if(_cc_pe){cpu->pc=cpu->wz;};_goto(1075); // JP PE,nn (5) + case 1075: _fetch(); // JP PE,nn (6) + case 1076: _wait();_mread(cpu->pc++);_goto(1077); // CALL PE,nn (1) + case 1077: cpu->wzl=_gd();_goto(1078); // CALL PE,nn (2) + case 1078: _goto(1079); // CALL PE,nn (3) + case 1079: _wait();_mread(cpu->pc++);_goto(1080); // CALL PE,nn (4) + case 1080: cpu->wzh=_gd();if (!_cc_pe){_goto(1081+7);};_goto(1081); // CALL PE,nn (5) + case 1081: _goto(1082); // CALL PE,nn (6) + case 1082: _goto(1083); // CALL PE,nn (7) + case 1083: _wait();_mwrite(--cpu->sp,cpu->pch);_goto(1084); // CALL PE,nn (8) + case 1084: _goto(1085); // CALL PE,nn (9) + case 1085: _goto(1086); // CALL PE,nn (10) + case 1086: _wait();_mwrite(--cpu->sp,cpu->pcl);cpu->pc=cpu->wz;_goto(1087); // CALL PE,nn (11) + case 1087: _goto(1088); // CALL PE,nn (12) + case 1088: _fetch(); // CALL PE,nn (13) + case 1089: _wait();_mread(cpu->pc++);_goto(1090); // XOR n (1) + case 1090: cpu->dlatch=_gd();_goto(1091); // XOR n (2) + case 1091: _z80_xor8(cpu,cpu->dlatch);_fetch(); // XOR n (3) + case 1092: _goto(1093); // RST 28h (1) + case 1093: _wait();_mwrite(--cpu->sp,cpu->pch);_goto(1094); // RST 28h (2) + case 1094: _goto(1095); // RST 28h (3) + case 1095: _goto(1096); // RST 28h (4) + case 1096: _wait();_mwrite(--cpu->sp,cpu->pcl);cpu->wz=0x28;cpu->pc=cpu->wz;_goto(1097); // RST 28h (5) + case 1097: _goto(1098); // RST 28h (6) + case 1098: _fetch(); // RST 28h (7) + case 1099: _goto(1100); // RET P (1) + case 1100: _wait();_mread(cpu->sp++);_goto(1101); // RET P (2) + case 1101: cpu->wzl=_gd();_goto(1102); // RET P (3) + case 1102: _goto(1103); // RET P (4) + case 1103: _wait();_mread(cpu->sp++);_goto(1104); // RET P (5) + case 1104: cpu->wzh=_gd();cpu->pc=cpu->wz;_goto(1105); // RET P (6) + case 1105: _fetch(); // RET P (7) + case 1106: _wait();_mread(cpu->sp++);_goto(1107); // POP AF (1) + case 1107: cpu->f=_gd();_goto(1108); // POP AF (2) + case 1108: _goto(1109); // POP AF (3) + case 1109: _wait();_mread(cpu->sp++);_goto(1110); // POP AF (4) + case 1110: cpu->a=_gd();_goto(1111); // POP AF (5) + case 1111: _fetch(); // POP AF (6) + case 1112: _wait();_mread(cpu->pc++);_goto(1113); // JP P,nn (1) + case 1113: cpu->wzl=_gd();_goto(1114); // JP P,nn (2) + case 1114: _goto(1115); // JP P,nn (3) + case 1115: _wait();_mread(cpu->pc++);_goto(1116); // JP P,nn (4) + case 1116: cpu->wzh=_gd();if(_cc_p){cpu->pc=cpu->wz;};_goto(1117); // JP P,nn (5) + case 1117: _fetch(); // JP P,nn (6) + case 1118: _wait();_mread(cpu->pc++);_goto(1119); // CALL P,nn (1) + case 1119: cpu->wzl=_gd();_goto(1120); // CALL P,nn (2) + case 1120: _goto(1121); // CALL P,nn (3) + case 1121: _wait();_mread(cpu->pc++);_goto(1122); // CALL P,nn (4) + case 1122: cpu->wzh=_gd();if (!_cc_p){_goto(1123+7);};_goto(1123); // CALL P,nn (5) + case 1123: _goto(1124); // CALL P,nn (6) + case 1124: _goto(1125); // CALL P,nn (7) + case 1125: _wait();_mwrite(--cpu->sp,cpu->pch);_goto(1126); // CALL P,nn (8) + case 1126: _goto(1127); // CALL P,nn (9) + case 1127: _goto(1128); // CALL P,nn (10) + case 1128: _wait();_mwrite(--cpu->sp,cpu->pcl);cpu->pc=cpu->wz;_goto(1129); // CALL P,nn (11) + case 1129: _goto(1130); // CALL P,nn (12) + case 1130: _fetch(); // CALL P,nn (13) + case 1131: _goto(1132); // PUSH AF (1) + case 1132: _wait();_mwrite(--cpu->sp,cpu->a);_goto(1133); // PUSH AF (2) + case 1133: _goto(1134); // PUSH AF (3) + case 1134: _goto(1135); // PUSH AF (4) + case 1135: _wait();_mwrite(--cpu->sp,cpu->f);_goto(1136); // PUSH AF (5) + case 1136: _goto(1137); // PUSH AF (6) + case 1137: _fetch(); // PUSH AF (7) + case 1138: _wait();_mread(cpu->pc++);_goto(1139); // OR n (1) + case 1139: cpu->dlatch=_gd();_goto(1140); // OR n (2) + case 1140: _z80_or8(cpu,cpu->dlatch);_fetch(); // OR n (3) + case 1141: _goto(1142); // RST 30h (1) + case 1142: _wait();_mwrite(--cpu->sp,cpu->pch);_goto(1143); // RST 30h (2) + case 1143: _goto(1144); // RST 30h (3) + case 1144: _goto(1145); // RST 30h (4) + case 1145: _wait();_mwrite(--cpu->sp,cpu->pcl);cpu->wz=0x30;cpu->pc=cpu->wz;_goto(1146); // RST 30h (5) + case 1146: _goto(1147); // RST 30h (6) + case 1147: _fetch(); // RST 30h (7) + case 1148: _goto(1149); // RET M (1) + case 1149: _wait();_mread(cpu->sp++);_goto(1150); // RET M (2) + case 1150: cpu->wzl=_gd();_goto(1151); // RET M (3) + case 1151: _goto(1152); // RET M (4) + case 1152: _wait();_mread(cpu->sp++);_goto(1153); // RET M (5) + case 1153: cpu->wzh=_gd();cpu->pc=cpu->wz;_goto(1154); // RET M (6) + case 1154: _fetch(); // RET M (7) + case 1155: _goto(1156); // LD SP,HL (1) + case 1156: _fetch(); // LD SP,HL (2) + case 1157: _wait();_mread(cpu->pc++);_goto(1158); // JP M,nn (1) + case 1158: cpu->wzl=_gd();_goto(1159); // JP M,nn (2) + case 1159: _goto(1160); // JP M,nn (3) + case 1160: _wait();_mread(cpu->pc++);_goto(1161); // JP M,nn (4) + case 1161: cpu->wzh=_gd();if(_cc_m){cpu->pc=cpu->wz;};_goto(1162); // JP M,nn (5) + case 1162: _fetch(); // JP M,nn (6) + case 1163: _wait();_mread(cpu->pc++);_goto(1164); // CALL M,nn (1) + case 1164: cpu->wzl=_gd();_goto(1165); // CALL M,nn (2) + case 1165: _goto(1166); // CALL M,nn (3) + case 1166: _wait();_mread(cpu->pc++);_goto(1167); // CALL M,nn (4) + case 1167: cpu->wzh=_gd();if (!_cc_m){_goto(1168+7);};_goto(1168); // CALL M,nn (5) + case 1168: _goto(1169); // CALL M,nn (6) + case 1169: _goto(1170); // CALL M,nn (7) + case 1170: _wait();_mwrite(--cpu->sp,cpu->pch);_goto(1171); // CALL M,nn (8) + case 1171: _goto(1172); // CALL M,nn (9) + case 1172: _goto(1173); // CALL M,nn (10) + case 1173: _wait();_mwrite(--cpu->sp,cpu->pcl);cpu->pc=cpu->wz;_goto(1174); // CALL M,nn (11) + case 1174: _goto(1175); // CALL M,nn (12) + case 1175: _fetch(); // CALL M,nn (13) + case 1176: _wait();_mread(cpu->pc++);_goto(1177); // CP n (1) + case 1177: cpu->dlatch=_gd();_goto(1178); // CP n (2) + case 1178: _z80_cp8(cpu,cpu->dlatch);_fetch(); // CP n (3) + case 1179: _goto(1180); // RST 38h (1) + case 1180: _wait();_mwrite(--cpu->sp,cpu->pch);_goto(1181); // RST 38h (2) + case 1181: _goto(1182); // RST 38h (3) + case 1182: _goto(1183); // RST 38h (4) + case 1183: _wait();_mwrite(--cpu->sp,cpu->pcl);cpu->wz=0x38;cpu->pc=cpu->wz;_goto(1184); // RST 38h (5) + case 1184: _goto(1185); // RST 38h (6) + case 1185: _fetch(); // RST 38h (7) + case 1186: _goto(1187); // IN B,(C) (1) + case 1187: _wait();_ioread(cpu->bc);_goto(1188); // IN B,(C) (2) + case 1188: cpu->dlatch=_gd();cpu->wz=cpu->bc+1;_goto(1189); // IN B,(C) (3) + case 1189: cpu->b=_z80_in(cpu,cpu->dlatch);_fetch(); // IN B,(C) (4) + case 1190: _iowrite(cpu->bc,cpu->b);_goto(1191); // OUT (C),B (1) + case 1191: _wait();cpu->wz=cpu->bc+1;_goto(1192); // OUT (C),B (2) + case 1192: _goto(1193); // OUT (C),B (3) + case 1193: _fetch(); // OUT (C),B (4) + case 1194: _goto(1195); // SBC HL,BC (1) + case 1195: _goto(1196); // SBC HL,BC (2) + case 1196: _goto(1197); // SBC HL,BC (3) + case 1197: _goto(1198); // SBC HL,BC (4) + case 1198: _goto(1199); // SBC HL,BC (5) + case 1199: _goto(1200); // SBC HL,BC (6) + case 1200: _fetch(); // SBC HL,BC (7) + case 1201: _wait();_mread(cpu->pc++);_goto(1202); // LD (nn),BC (1) + case 1202: cpu->wzl=_gd();_goto(1203); // LD (nn),BC (2) + case 1203: _goto(1204); // LD (nn),BC (3) + case 1204: _wait();_mread(cpu->pc++);_goto(1205); // LD (nn),BC (4) + case 1205: cpu->wzh=_gd();_goto(1206); // LD (nn),BC (5) + case 1206: _goto(1207); // LD (nn),BC (6) + case 1207: _wait();_mwrite(cpu->wz++,cpu->c);_goto(1208); // LD (nn),BC (7) + case 1208: _goto(1209); // LD (nn),BC (8) + case 1209: _goto(1210); // LD (nn),BC (9) + case 1210: _wait();_mwrite(cpu->wz,cpu->b);_goto(1211); // LD (nn),BC (10) + case 1211: _goto(1212); // LD (nn),BC (11) + case 1212: _fetch(); // LD (nn),BC (12) + case 1213: _wait();_mread(cpu->sp++);_goto(1214); // RETN (1) + case 1214: cpu->wzl=_gd();_goto(1215); // RETN (2) + case 1215: _goto(1216); // RETN (3) + case 1216: _wait();_mread(cpu->sp++);_goto(1217); // RETN (4) + case 1217: cpu->wzh=_gd();cpu->pc=cpu->wz;_goto(1218); // RETN (5) + case 1218: pins=_z80_fetch(cpu,pins);cpu->iff1=cpu->iff2;goto step_to; // RETN (6) + case 1219: cpu->i=cpu->a;_fetch(); // LD I,A (1) + case 1220: _goto(1221); // IN C,(C) (1) + case 1221: _wait();_ioread(cpu->bc);_goto(1222); // IN C,(C) (2) + case 1222: cpu->dlatch=_gd();cpu->wz=cpu->bc+1;_goto(1223); // IN C,(C) (3) + case 1223: cpu->c=_z80_in(cpu,cpu->dlatch);_fetch(); // IN C,(C) (4) + case 1224: _iowrite(cpu->bc,cpu->c);_goto(1225); // OUT (C),C (1) + case 1225: _wait();cpu->wz=cpu->bc+1;_goto(1226); // OUT (C),C (2) + case 1226: _goto(1227); // OUT (C),C (3) + case 1227: _fetch(); // OUT (C),C (4) + case 1228: _goto(1229); // ADC HL,BC (1) + case 1229: _goto(1230); // ADC HL,BC (2) + case 1230: _goto(1231); // ADC HL,BC (3) + case 1231: _goto(1232); // ADC HL,BC (4) + case 1232: _goto(1233); // ADC HL,BC (5) + case 1233: _goto(1234); // ADC HL,BC (6) + case 1234: _fetch(); // ADC HL,BC (7) + case 1235: _wait();_mread(cpu->pc++);_goto(1236); // LD BC,(nn) (1) + case 1236: cpu->wzl=_gd();_goto(1237); // LD BC,(nn) (2) + case 1237: _goto(1238); // LD BC,(nn) (3) + case 1238: _wait();_mread(cpu->pc++);_goto(1239); // LD BC,(nn) (4) + case 1239: cpu->wzh=_gd();_goto(1240); // LD BC,(nn) (5) + case 1240: _goto(1241); // LD BC,(nn) (6) + case 1241: _wait();_mread(cpu->wz++);_goto(1242); // LD BC,(nn) (7) + case 1242: cpu->c=_gd();_goto(1243); // LD BC,(nn) (8) + case 1243: _goto(1244); // LD BC,(nn) (9) + case 1244: _wait();_mread(cpu->wz);_goto(1245); // LD BC,(nn) (10) + case 1245: cpu->b=_gd();_goto(1246); // LD BC,(nn) (11) + case 1246: _fetch(); // LD BC,(nn) (12) + case 1247: _wait();_mread(cpu->sp++);_goto(1248); // RETI (1) + case 1248: cpu->wzl=_gd();pins|=Z80_RETI;_goto(1249); // RETI (2) + case 1249: _goto(1250); // RETI (3) + case 1250: _wait();_mread(cpu->sp++);_goto(1251); // RETI (4) + case 1251: cpu->wzh=_gd();cpu->pc=cpu->wz;_goto(1252); // RETI (5) + case 1252: pins=_z80_fetch(cpu,pins);cpu->iff1=cpu->iff2;goto step_to; // RETI (6) + case 1253: cpu->r=cpu->a;_fetch(); // LD R,A (1) + case 1254: _goto(1255); // IN D,(C) (1) + case 1255: _wait();_ioread(cpu->bc);_goto(1256); // IN D,(C) (2) + case 1256: cpu->dlatch=_gd();cpu->wz=cpu->bc+1;_goto(1257); // IN D,(C) (3) + case 1257: cpu->d=_z80_in(cpu,cpu->dlatch);_fetch(); // IN D,(C) (4) + case 1258: _iowrite(cpu->bc,cpu->d);_goto(1259); // OUT (C),D (1) + case 1259: _wait();cpu->wz=cpu->bc+1;_goto(1260); // OUT (C),D (2) + case 1260: _goto(1261); // OUT (C),D (3) + case 1261: _fetch(); // OUT (C),D (4) + case 1262: _goto(1263); // SBC HL,DE (1) + case 1263: _goto(1264); // SBC HL,DE (2) + case 1264: _goto(1265); // SBC HL,DE (3) + case 1265: _goto(1266); // SBC HL,DE (4) + case 1266: _goto(1267); // SBC HL,DE (5) + case 1267: _goto(1268); // SBC HL,DE (6) + case 1268: _fetch(); // SBC HL,DE (7) + case 1269: _wait();_mread(cpu->pc++);_goto(1270); // LD (nn),DE (1) + case 1270: cpu->wzl=_gd();_goto(1271); // LD (nn),DE (2) + case 1271: _goto(1272); // LD (nn),DE (3) + case 1272: _wait();_mread(cpu->pc++);_goto(1273); // LD (nn),DE (4) + case 1273: cpu->wzh=_gd();_goto(1274); // LD (nn),DE (5) + case 1274: _goto(1275); // LD (nn),DE (6) + case 1275: _wait();_mwrite(cpu->wz++,cpu->e);_goto(1276); // LD (nn),DE (7) + case 1276: _goto(1277); // LD (nn),DE (8) + case 1277: _goto(1278); // LD (nn),DE (9) + case 1278: _wait();_mwrite(cpu->wz,cpu->d);_goto(1279); // LD (nn),DE (10) + case 1279: _goto(1280); // LD (nn),DE (11) + case 1280: _fetch(); // LD (nn),DE (12) + case 1281: pins=_z80_fetch(cpu,pins);cpu->iff1=cpu->iff2;goto step_to; // RETI (6) + case 1282: cpu->a=cpu->i;cpu->f=_z80_sziff2_flags(cpu, cpu->i);_fetch(); // LD A,I (1) + case 1283: _goto(1284); // IN E,(C) (1) + case 1284: _wait();_ioread(cpu->bc);_goto(1285); // IN E,(C) (2) + case 1285: cpu->dlatch=_gd();cpu->wz=cpu->bc+1;_goto(1286); // IN E,(C) (3) + case 1286: cpu->e=_z80_in(cpu,cpu->dlatch);_fetch(); // IN E,(C) (4) + case 1287: _iowrite(cpu->bc,cpu->e);_goto(1288); // OUT (C),E (1) + case 1288: _wait();cpu->wz=cpu->bc+1;_goto(1289); // OUT (C),E (2) + case 1289: _goto(1290); // OUT (C),E (3) + case 1290: _fetch(); // OUT (C),E (4) + case 1291: _goto(1292); // ADC HL,DE (1) + case 1292: _goto(1293); // ADC HL,DE (2) + case 1293: _goto(1294); // ADC HL,DE (3) + case 1294: _goto(1295); // ADC HL,DE (4) + case 1295: _goto(1296); // ADC HL,DE (5) + case 1296: _goto(1297); // ADC HL,DE (6) + case 1297: _fetch(); // ADC HL,DE (7) + case 1298: _wait();_mread(cpu->pc++);_goto(1299); // LD DE,(nn) (1) + case 1299: cpu->wzl=_gd();_goto(1300); // LD DE,(nn) (2) + case 1300: _goto(1301); // LD DE,(nn) (3) + case 1301: _wait();_mread(cpu->pc++);_goto(1302); // LD DE,(nn) (4) + case 1302: cpu->wzh=_gd();_goto(1303); // LD DE,(nn) (5) + case 1303: _goto(1304); // LD DE,(nn) (6) + case 1304: _wait();_mread(cpu->wz++);_goto(1305); // LD DE,(nn) (7) + case 1305: cpu->e=_gd();_goto(1306); // LD DE,(nn) (8) + case 1306: _goto(1307); // LD DE,(nn) (9) + case 1307: _wait();_mread(cpu->wz);_goto(1308); // LD DE,(nn) (10) + case 1308: cpu->d=_gd();_goto(1309); // LD DE,(nn) (11) + case 1309: _fetch(); // LD DE,(nn) (12) + case 1310: pins=_z80_fetch(cpu,pins);cpu->iff1=cpu->iff2;goto step_to; // RETI (6) + case 1311: cpu->a=cpu->r;cpu->f=_z80_sziff2_flags(cpu, cpu->r);_fetch(); // LD A,R (1) + case 1312: _goto(1313); // IN H,(C) (1) + case 1313: _wait();_ioread(cpu->bc);_goto(1314); // IN H,(C) (2) + case 1314: cpu->dlatch=_gd();cpu->wz=cpu->bc+1;_goto(1315); // IN H,(C) (3) + case 1315: cpu->h=_z80_in(cpu,cpu->dlatch);_fetch(); // IN H,(C) (4) + case 1316: _iowrite(cpu->bc,cpu->h);_goto(1317); // OUT (C),H (1) + case 1317: _wait();cpu->wz=cpu->bc+1;_goto(1318); // OUT (C),H (2) + case 1318: _goto(1319); // OUT (C),H (3) + case 1319: _fetch(); // OUT (C),H (4) + case 1320: _goto(1321); // SBC HL,HL (1) + case 1321: _goto(1322); // SBC HL,HL (2) + case 1322: _goto(1323); // SBC HL,HL (3) + case 1323: _goto(1324); // SBC HL,HL (4) + case 1324: _goto(1325); // SBC HL,HL (5) + case 1325: _goto(1326); // SBC HL,HL (6) + case 1326: _fetch(); // SBC HL,HL (7) + case 1327: _wait();_mread(cpu->pc++);_goto(1328); // LD (nn),HL (1) + case 1328: cpu->wzl=_gd();_goto(1329); // LD (nn),HL (2) + case 1329: _goto(1330); // LD (nn),HL (3) + case 1330: _wait();_mread(cpu->pc++);_goto(1331); // LD (nn),HL (4) + case 1331: cpu->wzh=_gd();_goto(1332); // LD (nn),HL (5) + case 1332: _goto(1333); // LD (nn),HL (6) + case 1333: _wait();_mwrite(cpu->wz++,cpu->l);_goto(1334); // LD (nn),HL (7) + case 1334: _goto(1335); // LD (nn),HL (8) + case 1335: _goto(1336); // LD (nn),HL (9) + case 1336: _wait();_mwrite(cpu->wz,cpu->h);_goto(1337); // LD (nn),HL (10) + case 1337: _goto(1338); // LD (nn),HL (11) + case 1338: _fetch(); // LD (nn),HL (12) + case 1339: pins=_z80_fetch(cpu,pins);cpu->iff1=cpu->iff2;goto step_to; // RETI (6) + case 1340: _wait();_mread(cpu->hl);_goto(1341); // RRD (1) + case 1341: cpu->dlatch=_gd();_goto(1342); // RRD (2) + case 1342: cpu->dlatch=_z80_rrd(cpu,cpu->dlatch);_goto(1343); // RRD (3) + case 1343: _goto(1344); // RRD (4) + case 1344: _goto(1345); // RRD (5) + case 1345: _goto(1346); // RRD (6) + case 1346: _goto(1347); // RRD (7) + case 1347: _wait();_mwrite(cpu->hl,cpu->dlatch);cpu->wz=cpu->hl+1;_goto(1348); // RRD (8) + case 1348: _goto(1349); // RRD (9) + case 1349: _fetch(); // RRD (10) + case 1350: _goto(1351); // IN L,(C) (1) + case 1351: _wait();_ioread(cpu->bc);_goto(1352); // IN L,(C) (2) + case 1352: cpu->dlatch=_gd();cpu->wz=cpu->bc+1;_goto(1353); // IN L,(C) (3) + case 1353: cpu->l=_z80_in(cpu,cpu->dlatch);_fetch(); // IN L,(C) (4) + case 1354: _iowrite(cpu->bc,cpu->l);_goto(1355); // OUT (C),L (1) + case 1355: _wait();cpu->wz=cpu->bc+1;_goto(1356); // OUT (C),L (2) + case 1356: _goto(1357); // OUT (C),L (3) + case 1357: _fetch(); // OUT (C),L (4) + case 1358: _goto(1359); // ADC HL,HL (1) + case 1359: _goto(1360); // ADC HL,HL (2) + case 1360: _goto(1361); // ADC HL,HL (3) + case 1361: _goto(1362); // ADC HL,HL (4) + case 1362: _goto(1363); // ADC HL,HL (5) + case 1363: _goto(1364); // ADC HL,HL (6) + case 1364: _fetch(); // ADC HL,HL (7) + case 1365: _wait();_mread(cpu->pc++);_goto(1366); // LD HL,(nn) (1) + case 1366: cpu->wzl=_gd();_goto(1367); // LD HL,(nn) (2) + case 1367: _goto(1368); // LD HL,(nn) (3) + case 1368: _wait();_mread(cpu->pc++);_goto(1369); // LD HL,(nn) (4) + case 1369: cpu->wzh=_gd();_goto(1370); // LD HL,(nn) (5) + case 1370: _goto(1371); // LD HL,(nn) (6) + case 1371: _wait();_mread(cpu->wz++);_goto(1372); // LD HL,(nn) (7) + case 1372: cpu->l=_gd();_goto(1373); // LD HL,(nn) (8) + case 1373: _goto(1374); // LD HL,(nn) (9) + case 1374: _wait();_mread(cpu->wz);_goto(1375); // LD HL,(nn) (10) + case 1375: cpu->h=_gd();_goto(1376); // LD HL,(nn) (11) + case 1376: _fetch(); // LD HL,(nn) (12) + case 1377: pins=_z80_fetch(cpu,pins);cpu->iff1=cpu->iff2;goto step_to; // RETI (6) + case 1378: _wait();_mread(cpu->hl);_goto(1379); // RLD (1) + case 1379: cpu->dlatch=_gd();_goto(1380); // RLD (2) + case 1380: cpu->dlatch=_z80_rld(cpu,cpu->dlatch);_goto(1381); // RLD (3) + case 1381: _goto(1382); // RLD (4) + case 1382: _goto(1383); // RLD (5) + case 1383: _goto(1384); // RLD (6) + case 1384: _goto(1385); // RLD (7) + case 1385: _wait();_mwrite(cpu->hl,cpu->dlatch);cpu->wz=cpu->hl+1;_goto(1386); // RLD (8) + case 1386: _goto(1387); // RLD (9) + case 1387: _fetch(); // RLD (10) + case 1388: _goto(1389); // IN (C) (1) + case 1389: _wait();_ioread(cpu->bc);_goto(1390); // IN (C) (2) + case 1390: cpu->dlatch=_gd();cpu->wz=cpu->bc+1;_goto(1391); // IN (C) (3) + case 1391: _z80_in(cpu,cpu->dlatch);_fetch(); // IN (C) (4) + case 1392: _iowrite(cpu->bc,0);_goto(1393); // OUT (C),0 (1) + case 1393: _wait();cpu->wz=cpu->bc+1;_goto(1394); // OUT (C),0 (2) + case 1394: _goto(1395); // OUT (C),0 (3) + case 1395: _fetch(); // OUT (C),0 (4) + case 1396: _goto(1397); // SBC HL,SP (1) + case 1397: _goto(1398); // SBC HL,SP (2) + case 1398: _goto(1399); // SBC HL,SP (3) + case 1399: _goto(1400); // SBC HL,SP (4) + case 1400: _goto(1401); // SBC HL,SP (5) + case 1401: _goto(1402); // SBC HL,SP (6) + case 1402: _fetch(); // SBC HL,SP (7) + case 1403: _wait();_mread(cpu->pc++);_goto(1404); // LD (nn),SP (1) + case 1404: cpu->wzl=_gd();_goto(1405); // LD (nn),SP (2) + case 1405: _goto(1406); // LD (nn),SP (3) + case 1406: _wait();_mread(cpu->pc++);_goto(1407); // LD (nn),SP (4) + case 1407: cpu->wzh=_gd();_goto(1408); // LD (nn),SP (5) + case 1408: _goto(1409); // LD (nn),SP (6) + case 1409: _wait();_mwrite(cpu->wz++,cpu->spl);_goto(1410); // LD (nn),SP (7) + case 1410: _goto(1411); // LD (nn),SP (8) + case 1411: _goto(1412); // LD (nn),SP (9) + case 1412: _wait();_mwrite(cpu->wz,cpu->sph);_goto(1413); // LD (nn),SP (10) + case 1413: _goto(1414); // LD (nn),SP (11) + case 1414: _fetch(); // LD (nn),SP (12) + case 1415: pins=_z80_fetch(cpu,pins);cpu->iff1=cpu->iff2;goto step_to; // RETI (6) + case 1416: _goto(1417); // IN A,(C) (1) + case 1417: _wait();_ioread(cpu->bc);_goto(1418); // IN A,(C) (2) + case 1418: cpu->dlatch=_gd();cpu->wz=cpu->bc+1;_goto(1419); // IN A,(C) (3) + case 1419: cpu->a=_z80_in(cpu,cpu->dlatch);_fetch(); // IN A,(C) (4) + case 1420: _iowrite(cpu->bc,cpu->a);_goto(1421); // OUT (C),A (1) + case 1421: _wait();cpu->wz=cpu->bc+1;_goto(1422); // OUT (C),A (2) + case 1422: _goto(1423); // OUT (C),A (3) + case 1423: _fetch(); // OUT (C),A (4) + case 1424: _goto(1425); // ADC HL,SP (1) + case 1425: _goto(1426); // ADC HL,SP (2) + case 1426: _goto(1427); // ADC HL,SP (3) + case 1427: _goto(1428); // ADC HL,SP (4) + case 1428: _goto(1429); // ADC HL,SP (5) + case 1429: _goto(1430); // ADC HL,SP (6) + case 1430: _fetch(); // ADC HL,SP (7) + case 1431: _wait();_mread(cpu->pc++);_goto(1432); // LD SP,(nn) (1) + case 1432: cpu->wzl=_gd();_goto(1433); // LD SP,(nn) (2) + case 1433: _goto(1434); // LD SP,(nn) (3) + case 1434: _wait();_mread(cpu->pc++);_goto(1435); // LD SP,(nn) (4) + case 1435: cpu->wzh=_gd();_goto(1436); // LD SP,(nn) (5) + case 1436: _goto(1437); // LD SP,(nn) (6) + case 1437: _wait();_mread(cpu->wz++);_goto(1438); // LD SP,(nn) (7) + case 1438: cpu->spl=_gd();_goto(1439); // LD SP,(nn) (8) + case 1439: _goto(1440); // LD SP,(nn) (9) + case 1440: _wait();_mread(cpu->wz);_goto(1441); // LD SP,(nn) (10) + case 1441: cpu->sph=_gd();_goto(1442); // LD SP,(nn) (11) + case 1442: _fetch(); // LD SP,(nn) (12) + case 1443: pins=_z80_fetch(cpu,pins);cpu->iff1=cpu->iff2;goto step_to; // RETI (6) + case 1444: _wait();_mread(cpu->hl++);_goto(1445); // LDI (1) + case 1445: cpu->dlatch=_gd();_goto(1446); // LDI (2) + case 1446: _goto(1447); // LDI (3) + case 1447: _wait();_mwrite(cpu->de++,cpu->dlatch);_goto(1448); // LDI (4) + case 1448: _goto(1449); // LDI (5) + case 1449: _z80_ldi_ldd(cpu,cpu->dlatch);_goto(1450); // LDI (6) + case 1450: _goto(1451); // LDI (7) + case 1451: _fetch(); // LDI (8) + case 1452: _wait();_mread(cpu->hl++);_goto(1453); // CPI (1) + case 1453: cpu->dlatch=_gd();_goto(1454); // CPI (2) + case 1454: cpu->wz++;_z80_cpi_cpd(cpu,cpu->dlatch);_goto(1455); // CPI (3) + case 1455: _goto(1456); // CPI (4) + case 1456: _goto(1457); // CPI (5) + case 1457: _goto(1458); // CPI (6) + case 1458: _goto(1459); // CPI (7) + case 1459: _fetch(); // CPI (8) + case 1460: _goto(1461); // INI (1) + case 1461: _goto(1462); // INI (2) + case 1462: _wait();_ioread(cpu->bc);_goto(1463); // INI (3) + case 1463: cpu->dlatch=_gd();cpu->wz=cpu->bc+1;cpu->b--;;_goto(1464); // INI (4) + case 1464: _goto(1465); // INI (5) + case 1465: _wait();_mwrite(cpu->hl++,cpu->dlatch);_z80_ini_ind(cpu,cpu->dlatch,cpu->c+1);_goto(1466); // INI (6) + case 1466: _goto(1467); // INI (7) + case 1467: _fetch(); // INI (8) + case 1468: _goto(1469); // OUTI (1) + case 1469: _wait();_mread(cpu->hl++);_goto(1470); // OUTI (2) + case 1470: cpu->dlatch=_gd();cpu->b--;_goto(1471); // OUTI (3) + case 1471: _goto(1472); // OUTI (4) + case 1472: _iowrite(cpu->bc,cpu->dlatch);_goto(1473); // OUTI (5) + case 1473: _wait();cpu->wz=cpu->bc+1;_z80_outi_outd(cpu,cpu->dlatch);_goto(1474); // OUTI (6) + case 1474: _goto(1475); // OUTI (7) + case 1475: _fetch(); // OUTI (8) + case 1476: _wait();_mread(cpu->hl--);_goto(1477); // LDD (1) + case 1477: cpu->dlatch=_gd();_goto(1478); // LDD (2) + case 1478: _goto(1479); // LDD (3) + case 1479: _wait();_mwrite(cpu->de--,cpu->dlatch);_goto(1480); // LDD (4) + case 1480: _goto(1481); // LDD (5) + case 1481: _z80_ldi_ldd(cpu,cpu->dlatch);_goto(1482); // LDD (6) + case 1482: _goto(1483); // LDD (7) + case 1483: _fetch(); // LDD (8) + case 1484: _wait();_mread(cpu->hl--);_goto(1485); // CPD (1) + case 1485: cpu->dlatch=_gd();_goto(1486); // CPD (2) + case 1486: cpu->wz--;_z80_cpi_cpd(cpu,cpu->dlatch);_goto(1487); // CPD (3) + case 1487: _goto(1488); // CPD (4) + case 1488: _goto(1489); // CPD (5) + case 1489: _goto(1490); // CPD (6) + case 1490: _goto(1491); // CPD (7) + case 1491: _fetch(); // CPD (8) + case 1492: _goto(1493); // IND (1) + case 1493: _goto(1494); // IND (2) + case 1494: _wait();_ioread(cpu->bc);_goto(1495); // IND (3) + case 1495: cpu->dlatch=_gd();cpu->wz=cpu->bc-1;cpu->b--;;_goto(1496); // IND (4) + case 1496: _goto(1497); // IND (5) + case 1497: _wait();_mwrite(cpu->hl--,cpu->dlatch);_z80_ini_ind(cpu,cpu->dlatch,cpu->c-1);_goto(1498); // IND (6) + case 1498: _goto(1499); // IND (7) + case 1499: _fetch(); // IND (8) + case 1500: _goto(1501); // OUTD (1) + case 1501: _wait();_mread(cpu->hl--);_goto(1502); // OUTD (2) + case 1502: cpu->dlatch=_gd();cpu->b--;_goto(1503); // OUTD (3) + case 1503: _goto(1504); // OUTD (4) + case 1504: _iowrite(cpu->bc,cpu->dlatch);_goto(1505); // OUTD (5) + case 1505: _wait();cpu->wz=cpu->bc-1;_z80_outi_outd(cpu,cpu->dlatch);_goto(1506); // OUTD (6) + case 1506: _goto(1507); // OUTD (7) + case 1507: _fetch(); // OUTD (8) + case 1508: _wait();_mread(cpu->hl++);_goto(1509); // LDIR (1) + case 1509: cpu->dlatch=_gd();_goto(1510); // LDIR (2) + case 1510: _goto(1511); // LDIR (3) + case 1511: _wait();_mwrite(cpu->de++,cpu->dlatch);_goto(1512); // LDIR (4) + case 1512: _goto(1513); // LDIR (5) + case 1513: if(!_z80_ldi_ldd(cpu,cpu->dlatch)){_goto(1514+5);};_goto(1514); // LDIR (6) + case 1514: _goto(1515); // LDIR (7) + case 1515: cpu->wz=--cpu->pc;--cpu->pc;;_goto(1516); // LDIR (8) + case 1516: _goto(1517); // LDIR (9) + case 1517: _goto(1518); // LDIR (10) + case 1518: _goto(1519); // LDIR (11) + case 1519: _goto(1520); // LDIR (12) + case 1520: _fetch(); // LDIR (13) + case 1521: _wait();_mread(cpu->hl++);_goto(1522); // CPIR (1) + case 1522: cpu->dlatch=_gd();_goto(1523); // CPIR (2) + case 1523: cpu->wz++;if(!_z80_cpi_cpd(cpu,cpu->dlatch)){_goto(1524+5);};_goto(1524); // CPIR (3) + case 1524: _goto(1525); // CPIR (4) + case 1525: _goto(1526); // CPIR (5) + case 1526: _goto(1527); // CPIR (6) + case 1527: _goto(1528); // CPIR (7) + case 1528: cpu->wz=--cpu->pc;--cpu->pc;_goto(1529); // CPIR (8) + case 1529: _goto(1530); // CPIR (9) + case 1530: _goto(1531); // CPIR (10) + case 1531: _goto(1532); // CPIR (11) + case 1532: _goto(1533); // CPIR (12) + case 1533: _fetch(); // CPIR (13) + case 1534: _goto(1535); // INIR (1) + case 1535: _goto(1536); // INIR (2) + case 1536: _wait();_ioread(cpu->bc);_goto(1537); // INIR (3) + case 1537: cpu->dlatch=_gd();cpu->wz=cpu->bc+1;cpu->b--;;_goto(1538); // INIR (4) + case 1538: _goto(1539); // INIR (5) + case 1539: _wait();_mwrite(cpu->hl++,cpu->dlatch);if (!_z80_ini_ind(cpu,cpu->dlatch,cpu->c+1)){_goto(1540+5);};_goto(1540); // INIR (6) + case 1540: _goto(1541); // INIR (7) + case 1541: cpu->wz=--cpu->pc;--cpu->pc;_goto(1542); // INIR (8) + case 1542: _goto(1543); // INIR (9) + case 1543: _goto(1544); // INIR (10) + case 1544: _goto(1545); // INIR (11) + case 1545: _goto(1546); // INIR (12) + case 1546: _fetch(); // INIR (13) + case 1547: _goto(1548); // OTIR (1) + case 1548: _wait();_mread(cpu->hl++);_goto(1549); // OTIR (2) + case 1549: cpu->dlatch=_gd();cpu->b--;_goto(1550); // OTIR (3) + case 1550: _goto(1551); // OTIR (4) + case 1551: _iowrite(cpu->bc,cpu->dlatch);_goto(1552); // OTIR (5) + case 1552: _wait();cpu->wz=cpu->bc+1;if(!_z80_outi_outd(cpu,cpu->dlatch)){_goto(1553+5);};_goto(1553); // OTIR (6) + case 1553: _goto(1554); // OTIR (7) + case 1554: cpu->wz=--cpu->pc;--cpu->pc;_goto(1555); // OTIR (8) + case 1555: _goto(1556); // OTIR (9) + case 1556: _goto(1557); // OTIR (10) + case 1557: _goto(1558); // OTIR (11) + case 1558: _goto(1559); // OTIR (12) + case 1559: _fetch(); // OTIR (13) + case 1560: _wait();_mread(cpu->hl--);_goto(1561); // LDDR (1) + case 1561: cpu->dlatch=_gd();_goto(1562); // LDDR (2) + case 1562: _goto(1563); // LDDR (3) + case 1563: _wait();_mwrite(cpu->de--,cpu->dlatch);_goto(1564); // LDDR (4) + case 1564: _goto(1565); // LDDR (5) + case 1565: if(!_z80_ldi_ldd(cpu,cpu->dlatch)){_goto(1566+5);};_goto(1566); // LDDR (6) + case 1566: _goto(1567); // LDDR (7) + case 1567: cpu->wz=--cpu->pc;--cpu->pc;;_goto(1568); // LDDR (8) + case 1568: _goto(1569); // LDDR (9) + case 1569: _goto(1570); // LDDR (10) + case 1570: _goto(1571); // LDDR (11) + case 1571: _goto(1572); // LDDR (12) + case 1572: _fetch(); // LDDR (13) + case 1573: _wait();_mread(cpu->hl--);_goto(1574); // CPDR (1) + case 1574: cpu->dlatch=_gd();_goto(1575); // CPDR (2) + case 1575: cpu->wz--;if(!_z80_cpi_cpd(cpu,cpu->dlatch)){_goto(1576+5);};_goto(1576); // CPDR (3) + case 1576: _goto(1577); // CPDR (4) + case 1577: _goto(1578); // CPDR (5) + case 1578: _goto(1579); // CPDR (6) + case 1579: _goto(1580); // CPDR (7) + case 1580: cpu->wz=--cpu->pc;--cpu->pc;_goto(1581); // CPDR (8) + case 1581: _goto(1582); // CPDR (9) + case 1582: _goto(1583); // CPDR (10) + case 1583: _goto(1584); // CPDR (11) + case 1584: _goto(1585); // CPDR (12) + case 1585: _fetch(); // CPDR (13) + case 1586: _goto(1587); // INDR (1) + case 1587: _goto(1588); // INDR (2) + case 1588: _wait();_ioread(cpu->bc);_goto(1589); // INDR (3) + case 1589: cpu->dlatch=_gd();cpu->wz=cpu->bc-1;cpu->b--;;_goto(1590); // INDR (4) + case 1590: _goto(1591); // INDR (5) + case 1591: _wait();_mwrite(cpu->hl--,cpu->dlatch);if (!_z80_ini_ind(cpu,cpu->dlatch,cpu->c-1)){_goto(1592+5);};_goto(1592); // INDR (6) + case 1592: _goto(1593); // INDR (7) + case 1593: cpu->wz=--cpu->pc;--cpu->pc;_goto(1594); // INDR (8) + case 1594: _goto(1595); // INDR (9) + case 1595: _goto(1596); // INDR (10) + case 1596: _goto(1597); // INDR (11) + case 1597: _goto(1598); // INDR (12) + case 1598: _fetch(); // INDR (13) + case 1599: _goto(1600); // OTDR (1) + case 1600: _wait();_mread(cpu->hl--);_goto(1601); // OTDR (2) + case 1601: cpu->dlatch=_gd();cpu->b--;_goto(1602); // OTDR (3) + case 1602: _goto(1603); // OTDR (4) + case 1603: _iowrite(cpu->bc,cpu->dlatch);_goto(1604); // OTDR (5) + case 1604: _wait();cpu->wz=cpu->bc-1;if(!_z80_outi_outd(cpu,cpu->dlatch)){_goto(1605+5);};_goto(1605); // OTDR (6) + case 1605: _goto(1606); // OTDR (7) + case 1606: cpu->wz=--cpu->pc;--cpu->pc;_goto(1607); // OTDR (8) + case 1607: _goto(1608); // OTDR (9) + case 1608: _goto(1609); // OTDR (10) + case 1609: _goto(1610); // OTDR (11) + case 1610: _goto(1611); // OTDR (12) + case 1611: _fetch(); // OTDR (13) + case 1612: {uint8_t z=cpu->opcode&7;_z80_cb_action(cpu,z,z);};_fetch(); // cb (0) + case 1613: _goto(1614); // cbhl (0) + case 1614: _wait();_mread(cpu->hl);_goto(1615); // cbhl (1) + case 1615: cpu->dlatch=_gd();if(!_z80_cb_action(cpu,6,6)){_goto(1616+3);};_goto(1616); // cbhl (2) + case 1616: _goto(1617); // cbhl (3) + case 1617: _goto(1618); // cbhl (4) + case 1618: _wait();_mwrite(cpu->hl,cpu->dlatch);_goto(1619); // cbhl (5) + case 1619: _goto(1620); // cbhl (6) + case 1620: _fetch(); // cbhl (7) + case 1621: _wait();_mread(cpu->pc++);_goto(1622); // ddfdcb (0) + case 1622: _z80_ddfdcb_addr(cpu,pins);_goto(1623); // ddfdcb (1) + case 1623: _goto(1624); // ddfdcb (2) + case 1624: _wait();_mread(cpu->pc++);_goto(1625); // ddfdcb (3) + case 1625: cpu->opcode=_gd();_goto(1626); // ddfdcb (4) + case 1626: _goto(1627); // ddfdcb (5) + case 1627: _goto(1628); // ddfdcb (6) + case 1628: _goto(1629); // ddfdcb (7) + case 1629: _wait();_mread(cpu->addr);_goto(1630); // ddfdcb (8) + case 1630: cpu->dlatch=_gd();if(!_z80_cb_action(cpu,6,cpu->opcode&7)){_goto(1631+3);};_goto(1631); // ddfdcb (9) + case 1631: _goto(1632); // ddfdcb (10) + case 1632: _goto(1633); // ddfdcb (11) + case 1633: _wait();_mwrite(cpu->addr,cpu->dlatch);_goto(1634); // ddfdcb (12) + case 1634: _goto(1635); // ddfdcb (13) + case 1635: _fetch(); // ddfdcb (14) + case 1636: cpu->iff1=cpu->iff2=false;_goto(1637); // int_im0 (0) + case 1637: pins|=(Z80_M1|Z80_IORQ);_goto(1638); // int_im0 (1) + case 1638: _wait();cpu->opcode=_z80_get_db(pins);_goto(1639); // int_im0 (2) + case 1639: pins=_z80_refresh(cpu,pins);_goto(1640); // int_im0 (3) + case 1640: cpu->addr=cpu->hl;_goto(cpu->opcode);_goto(1641); // int_im0 (4) + case 1641: _fetch(); // int_im0 (5) + case 1642: cpu->iff1=cpu->iff2=false;_goto(1643); // int_im1 (0) + case 1643: pins|=(Z80_M1|Z80_IORQ);_goto(1644); // int_im1 (1) + case 1644: _wait();_goto(1645); // int_im1 (2) + case 1645: pins=_z80_refresh(cpu,pins);_goto(1646); // int_im1 (3) + case 1646: _goto(1647); // int_im1 (4) + case 1647: _goto(1648); // int_im1 (5) + case 1648: _goto(1649); // int_im1 (6) + case 1649: _wait();_mwrite(--cpu->sp,cpu->pch);_goto(1650); // int_im1 (7) + case 1650: _goto(1651); // int_im1 (8) + case 1651: _goto(1652); // int_im1 (9) + case 1652: _wait();_mwrite(--cpu->sp,cpu->pcl);cpu->wz=cpu->pc=0x0038;_goto(1653); // int_im1 (10) + case 1653: _goto(1654); // int_im1 (11) + case 1654: _fetch(); // int_im1 (12) + case 1655: cpu->iff1=cpu->iff2=false;_goto(1656); // int_im2 (0) + case 1656: pins|=(Z80_M1|Z80_IORQ);_goto(1657); // int_im2 (1) + case 1657: _wait();cpu->dlatch=_z80_get_db(pins);_goto(1658); // int_im2 (2) + case 1658: pins=_z80_refresh(cpu,pins);_goto(1659); // int_im2 (3) + case 1659: _goto(1660); // int_im2 (4) + case 1660: _goto(1661); // int_im2 (5) + case 1661: _goto(1662); // int_im2 (6) + case 1662: _wait();_mwrite(--cpu->sp,cpu->pch);_goto(1663); // int_im2 (7) + case 1663: _goto(1664); // int_im2 (8) + case 1664: _goto(1665); // int_im2 (9) + case 1665: _wait();_mwrite(--cpu->sp,cpu->pcl);cpu->wzl=cpu->dlatch;cpu->wzh=cpu->i;_goto(1666); // int_im2 (10) + case 1666: _goto(1667); // int_im2 (11) + case 1667: _goto(1668); // int_im2 (12) + case 1668: _wait();_mread(cpu->wz++);_goto(1669); // int_im2 (13) + case 1669: cpu->dlatch=_gd();_goto(1670); // int_im2 (14) + case 1670: _goto(1671); // int_im2 (15) + case 1671: _wait();_mread(cpu->wz);_goto(1672); // int_im2 (16) + case 1672: cpu->wzh=_gd();cpu->wzl=cpu->dlatch;cpu->pc=cpu->wz;_goto(1673); // int_im2 (17) + case 1673: _fetch(); // int_im2 (18) + case 1674: _wait();cpu->iff1=false;_goto(1675); // nmi (0) + case 1675: pins=_z80_refresh(cpu,pins);_goto(1676); // nmi (1) + case 1676: _goto(1677); // nmi (2) + case 1677: _goto(1678); // nmi (3) + case 1678: _goto(1679); // nmi (4) + case 1679: _wait();_mwrite(--cpu->sp,cpu->pch);_goto(1680); // nmi (5) + case 1680: _goto(1681); // nmi (6) + case 1681: _goto(1682); // nmi (7) + case 1682: _wait();_mwrite(--cpu->sp,cpu->pcl);cpu->wz=cpu->pc=0x0066;_goto(1683); // nmi (8) + case 1683: _goto(1684); // nmi (9) + case 1684: _fetch(); // nmi (10) + // %> //=== shared fetch machine cycle for DD/FD-prefixed ops - // M1/T2: load opcode from data bus - case 3: _wait(); cpu->opcode = _gd(); goto step_next; - // M1/T3: refresh cycle - case 4: pins = _z80_refresh(cpu, pins); goto step_next; - // M1/T4: branch to instruction 'payload' - case 5: { - cpu->step = _z80_ddfd_optable[cpu->opcode]; + case Z80_DDFD_M1_T2: _wait(); cpu->opcode = _gd(); _goto(Z80_DDFD_M1_T3); + case Z80_DDFD_M1_T3: pins = _z80_refresh(cpu, pins); _goto(Z80_DDFD_M1_T4); + case Z80_DDFD_M1_T4: cpu->addr = cpu->hlx[cpu->hlx_idx].hl; - } goto step_next; + _goto(_z80_indirect_table[cpu->opcode] ? Z80_DDFD_D_T1 : cpu->opcode); //=== optional d-loading cycle for (IX+d), (IY+d) - //--- mread - case 6: goto step_next; - case 7: _wait();_mread(cpu->pc++); goto step_next; - case 8: cpu->addr += (int8_t)_gd(); cpu->wz = cpu->addr; goto step_next; - //--- filler ticks - case 9: goto step_next; - case 10: goto step_next; - case 11: goto step_next; - case 12: goto step_next; - case 13: { - // branch to actual instruction - cpu->step = _z80_optable[cpu->opcode]; - } goto step_next; - //=== special case d-loading cycle for (IX+d),n where the immediate load - // is hidden in the d-cycle load - //--- mread for d offset - case 14: goto step_next; - case 15: _wait();_mread(cpu->pc++); goto step_next; - case 16: cpu->addr += (int8_t)_gd(); cpu->wz = cpu->addr; goto step_next; - //--- mread for n - case 17: goto step_next; - case 18: _wait();_mread(cpu->pc++); goto step_next; - case 19: cpu->dlatch=_gd(); goto step_next; - //--- filler tick - case 20: goto step_next; - case 21: { - // branch to ld (hl),n and skip the original mread cycle for loading 'n' - cpu->step = _z80_optable[cpu->opcode] + 3; - } goto step_next; + case Z80_DDFD_D_T1: _goto(Z80_DDFD_D_T2); + case Z80_DDFD_D_T2: _wait(); _mread(cpu->pc++); _goto(Z80_DDFD_D_T3); + case Z80_DDFD_D_T3: cpu->addr += (int8_t)_gd(); cpu->wz = cpu->addr; _goto(Z80_DDFD_D_T4); + //--- special case LD (IX/IY+d),n or filler ticks + case Z80_DDFD_D_T4: _goto(Z80_DDFD_D_T5); + case Z80_DDFD_D_T5: if (cpu->opcode == 0x36) { _wait();_mread(cpu->pc++); }; _goto(Z80_DDFD_D_T6); + case Z80_DDFD_D_T6: if (cpu->opcode == 0x36) { cpu->dlatch = _gd(); }; _goto(Z80_DDFD_D_T7); + case Z80_DDFD_D_T7: _goto(Z80_DDFD_D_T8); + case Z80_DDFD_D_T8: _goto((cpu->opcode==0x36) ? Z80_DDFD_LDHLN_WR_T1 : cpu->opcode); + //--- special case LD (IX/IY+d),n write mcycle + case Z80_DDFD_LDHLN_WR_T1: _goto(Z80_DDFD_LDHLN_WR_T2); + case Z80_DDFD_LDHLN_WR_T2: _wait(); _mwrite(cpu->addr,cpu->dlatch); _goto(Z80_DDFD_LDHLN_WR_T3); + case Z80_DDFD_LDHLN_WR_T3: _goto(Z80_DDFD_LDHLN_OVERLAPPED); + case Z80_DDFD_LDHLN_OVERLAPPED: _fetch(); //=== special opcode fetch machine cycle for CB-prefixed instructions - case 22: _wait(); cpu->opcode = _gd(); goto step_next; - case 23: pins = _z80_refresh(cpu, pins); goto step_next; - case 24: { + case Z80_CB_M1_T2: _wait(); cpu->opcode = _gd(); _goto(Z80_CB_M1_T3); + case Z80_CB_M1_T3: pins = _z80_refresh(cpu, pins); _goto(Z80_CB_M1_T4); + case Z80_CB_M1_T4: if ((cpu->opcode & 7) == 6) { // this is a (HL) instruction cpu->addr = cpu->hl; - cpu->step = _z80_special_optable[_Z80_OPSTATE_SLOT_CBHL]; + _goto(Z80_CBHL_STEP); } else { - cpu->step = _z80_special_optable[_Z80_OPSTATE_SLOT_CB]; + _goto(Z80_CB_STEP); } - } goto step_next; //=== special opcode fetch machine cycle for ED-prefixed instructions - // M1/T2: load opcode from data bus - case 25: _wait(); cpu->opcode = _gd(); goto step_next; - // M1/T3: refresh cycle - case 26: pins = _z80_refresh(cpu, pins); goto step_next; - // M1/T4: branch to instruction 'payload' - case 27: cpu->step = _z80_ed_optable[cpu->opcode]; goto step_next; - //=== from here on code-generated - - // 00: NOP (M:1 T:4) - // -- overlapped - case 28: goto fetch_next; - - // 01: LD BC,nn (M:3 T:10) - // -- mread - case 29: goto step_next; - case 30: _wait();_mread(cpu->pc++);goto step_next; - case 31: cpu->c=_gd();goto step_next; - // -- mread - case 32: goto step_next; - case 33: _wait();_mread(cpu->pc++);goto step_next; - case 34: cpu->b=_gd();goto step_next; - // -- overlapped - case 35: goto fetch_next; - - // 02: LD (BC),A (M:2 T:7) - // -- mwrite - case 36: goto step_next; - case 37: _wait();_mwrite(cpu->bc,cpu->a);cpu->wzl=cpu->c+1;cpu->wzh=cpu->a;goto step_next; - case 38: goto step_next; - // -- overlapped - case 39: goto fetch_next; - - // 03: INC BC (M:2 T:6) - // -- generic - case 40: cpu->bc++;goto step_next; - case 41: goto step_next; - // -- overlapped - case 42: goto fetch_next; - - // 04: INC B (M:1 T:4) - // -- overlapped - case 43: cpu->b=_z80_inc8(cpu,cpu->b);goto fetch_next; - - // 05: DEC B (M:1 T:4) - // -- overlapped - case 44: cpu->b=_z80_dec8(cpu,cpu->b);goto fetch_next; - - // 06: LD B,n (M:2 T:7) - // -- mread - case 45: goto step_next; - case 46: _wait();_mread(cpu->pc++);goto step_next; - case 47: cpu->b=_gd();goto step_next; - // -- overlapped - case 48: goto fetch_next; - - // 07: RLCA (M:1 T:4) - // -- overlapped - case 49: _z80_rlca(cpu);goto fetch_next; - - // 08: EX AF,AF' (M:1 T:4) - // -- overlapped - case 50: _z80_ex_af_af2(cpu);goto fetch_next; - - // 09: ADD HL,BC (M:2 T:11) - // -- generic - case 51: _z80_add16(cpu,cpu->bc);goto step_next; - case 52: goto step_next; - case 53: goto step_next; - case 54: goto step_next; - case 55: goto step_next; - case 56: goto step_next; - case 57: goto step_next; - // -- overlapped - case 58: goto fetch_next; - - // 0A: LD A,(BC) (M:2 T:7) - // -- mread - case 59: goto step_next; - case 60: _wait();_mread(cpu->bc);goto step_next; - case 61: cpu->a=_gd();cpu->wz=cpu->bc+1;goto step_next; - // -- overlapped - case 62: goto fetch_next; - - // 0B: DEC BC (M:2 T:6) - // -- generic - case 63: cpu->bc--;goto step_next; - case 64: goto step_next; - // -- overlapped - case 65: goto fetch_next; - - // 0C: INC C (M:1 T:4) - // -- overlapped - case 66: cpu->c=_z80_inc8(cpu,cpu->c);goto fetch_next; - - // 0D: DEC C (M:1 T:4) - // -- overlapped - case 67: cpu->c=_z80_dec8(cpu,cpu->c);goto fetch_next; - - // 0E: LD C,n (M:2 T:7) - // -- mread - case 68: goto step_next; - case 69: _wait();_mread(cpu->pc++);goto step_next; - case 70: cpu->c=_gd();goto step_next; - // -- overlapped - case 71: goto fetch_next; - - // 0F: RRCA (M:1 T:4) - // -- overlapped - case 72: _z80_rrca(cpu);goto fetch_next; - - // 10: DJNZ d (M:4 T:13) - // -- generic - case 73: goto step_next; - // -- mread - case 74: goto step_next; - case 75: _wait();_mread(cpu->pc++);goto step_next; - case 76: cpu->dlatch=_gd();if(--cpu->b==0){_skip(5);};goto step_next; - // -- generic - case 77: cpu->pc+=(int8_t)cpu->dlatch;cpu->wz=cpu->pc;goto step_next; - case 78: goto step_next; - case 79: goto step_next; - case 80: goto step_next; - case 81: goto step_next; - // -- overlapped - case 82: goto fetch_next; - - // 11: LD DE,nn (M:3 T:10) - // -- mread - case 83: goto step_next; - case 84: _wait();_mread(cpu->pc++);goto step_next; - case 85: cpu->e=_gd();goto step_next; - // -- mread - case 86: goto step_next; - case 87: _wait();_mread(cpu->pc++);goto step_next; - case 88: cpu->d=_gd();goto step_next; - // -- overlapped - case 89: goto fetch_next; - - // 12: LD (DE),A (M:2 T:7) - // -- mwrite - case 90: goto step_next; - case 91: _wait();_mwrite(cpu->de,cpu->a);cpu->wzl=cpu->e+1;cpu->wzh=cpu->a;goto step_next; - case 92: goto step_next; - // -- overlapped - case 93: goto fetch_next; - - // 13: INC DE (M:2 T:6) - // -- generic - case 94: cpu->de++;goto step_next; - case 95: goto step_next; - // -- overlapped - case 96: goto fetch_next; - - // 14: INC D (M:1 T:4) - // -- overlapped - case 97: cpu->d=_z80_inc8(cpu,cpu->d);goto fetch_next; - - // 15: DEC D (M:1 T:4) - // -- overlapped - case 98: cpu->d=_z80_dec8(cpu,cpu->d);goto fetch_next; - - // 16: LD D,n (M:2 T:7) - // -- mread - case 99: goto step_next; - case 100: _wait();_mread(cpu->pc++);goto step_next; - case 101: cpu->d=_gd();goto step_next; - // -- overlapped - case 102: goto fetch_next; - - // 17: RLA (M:1 T:4) - // -- overlapped - case 103: _z80_rla(cpu);goto fetch_next; - - // 18: JR d (M:3 T:12) - // -- mread - case 104: goto step_next; - case 105: _wait();_mread(cpu->pc++);goto step_next; - case 106: cpu->dlatch=_gd();goto step_next; - // -- generic - case 107: cpu->pc+=(int8_t)cpu->dlatch;cpu->wz=cpu->pc;goto step_next; - case 108: goto step_next; - case 109: goto step_next; - case 110: goto step_next; - case 111: goto step_next; - // -- overlapped - case 112: goto fetch_next; - - // 19: ADD HL,DE (M:2 T:11) - // -- generic - case 113: _z80_add16(cpu,cpu->de);goto step_next; - case 114: goto step_next; - case 115: goto step_next; - case 116: goto step_next; - case 117: goto step_next; - case 118: goto step_next; - case 119: goto step_next; - // -- overlapped - case 120: goto fetch_next; - - // 1A: LD A,(DE) (M:2 T:7) - // -- mread - case 121: goto step_next; - case 122: _wait();_mread(cpu->de);goto step_next; - case 123: cpu->a=_gd();cpu->wz=cpu->de+1;goto step_next; - // -- overlapped - case 124: goto fetch_next; - - // 1B: DEC DE (M:2 T:6) - // -- generic - case 125: cpu->de--;goto step_next; - case 126: goto step_next; - // -- overlapped - case 127: goto fetch_next; - - // 1C: INC E (M:1 T:4) - // -- overlapped - case 128: cpu->e=_z80_inc8(cpu,cpu->e);goto fetch_next; - - // 1D: DEC E (M:1 T:4) - // -- overlapped - case 129: cpu->e=_z80_dec8(cpu,cpu->e);goto fetch_next; - - // 1E: LD E,n (M:2 T:7) - // -- mread - case 130: goto step_next; - case 131: _wait();_mread(cpu->pc++);goto step_next; - case 132: cpu->e=_gd();goto step_next; - // -- overlapped - case 133: goto fetch_next; - - // 1F: RRA (M:1 T:4) - // -- overlapped - case 134: _z80_rra(cpu);goto fetch_next; - - // 20: JR NZ,d (M:3 T:12) - // -- mread - case 135: goto step_next; - case 136: _wait();_mread(cpu->pc++);goto step_next; - case 137: cpu->dlatch=_gd();if(!(_cc_nz)){_skip(5);};goto step_next; - // -- generic - case 138: cpu->pc+=(int8_t)cpu->dlatch;cpu->wz=cpu->pc;goto step_next; - case 139: goto step_next; - case 140: goto step_next; - case 141: goto step_next; - case 142: goto step_next; - // -- overlapped - case 143: goto fetch_next; - - // 21: LD HL,nn (M:3 T:10) - // -- mread - case 144: goto step_next; - case 145: _wait();_mread(cpu->pc++);goto step_next; - case 146: cpu->hlx[cpu->hlx_idx].l=_gd();goto step_next; - // -- mread - case 147: goto step_next; - case 148: _wait();_mread(cpu->pc++);goto step_next; - case 149: cpu->hlx[cpu->hlx_idx].h=_gd();goto step_next; - // -- overlapped - case 150: goto fetch_next; - - // 22: LD (nn),HL (M:5 T:16) - // -- mread - case 151: goto step_next; - case 152: _wait();_mread(cpu->pc++);goto step_next; - case 153: cpu->wzl=_gd();goto step_next; - // -- mread - case 154: goto step_next; - case 155: _wait();_mread(cpu->pc++);goto step_next; - case 156: cpu->wzh=_gd();goto step_next; - // -- mwrite - case 157: goto step_next; - case 158: _wait();_mwrite(cpu->wz++,cpu->hlx[cpu->hlx_idx].l);goto step_next; - case 159: goto step_next; - // -- mwrite - case 160: goto step_next; - case 161: _wait();_mwrite(cpu->wz,cpu->hlx[cpu->hlx_idx].h);goto step_next; - case 162: goto step_next; - // -- overlapped - case 163: goto fetch_next; - - // 23: INC HL (M:2 T:6) - // -- generic - case 164: cpu->hlx[cpu->hlx_idx].hl++;goto step_next; - case 165: goto step_next; - // -- overlapped - case 166: goto fetch_next; - - // 24: INC H (M:1 T:4) - // -- overlapped - case 167: cpu->hlx[cpu->hlx_idx].h=_z80_inc8(cpu,cpu->hlx[cpu->hlx_idx].h);goto fetch_next; - - // 25: DEC H (M:1 T:4) - // -- overlapped - case 168: cpu->hlx[cpu->hlx_idx].h=_z80_dec8(cpu,cpu->hlx[cpu->hlx_idx].h);goto fetch_next; - - // 26: LD H,n (M:2 T:7) - // -- mread - case 169: goto step_next; - case 170: _wait();_mread(cpu->pc++);goto step_next; - case 171: cpu->hlx[cpu->hlx_idx].h=_gd();goto step_next; - // -- overlapped - case 172: goto fetch_next; - - // 27: DAA (M:1 T:4) - // -- overlapped - case 173: _z80_daa(cpu);goto fetch_next; - - // 28: JR Z,d (M:3 T:12) - // -- mread - case 174: goto step_next; - case 175: _wait();_mread(cpu->pc++);goto step_next; - case 176: cpu->dlatch=_gd();if(!(_cc_z)){_skip(5);};goto step_next; - // -- generic - case 177: cpu->pc+=(int8_t)cpu->dlatch;cpu->wz=cpu->pc;goto step_next; - case 178: goto step_next; - case 179: goto step_next; - case 180: goto step_next; - case 181: goto step_next; - // -- overlapped - case 182: goto fetch_next; - - // 29: ADD HL,HL (M:2 T:11) - // -- generic - case 183: _z80_add16(cpu,cpu->hlx[cpu->hlx_idx].hl);goto step_next; - case 184: goto step_next; - case 185: goto step_next; - case 186: goto step_next; - case 187: goto step_next; - case 188: goto step_next; - case 189: goto step_next; - // -- overlapped - case 190: goto fetch_next; - - // 2A: LD HL,(nn) (M:5 T:16) - // -- mread - case 191: goto step_next; - case 192: _wait();_mread(cpu->pc++);goto step_next; - case 193: cpu->wzl=_gd();goto step_next; - // -- mread - case 194: goto step_next; - case 195: _wait();_mread(cpu->pc++);goto step_next; - case 196: cpu->wzh=_gd();goto step_next; - // -- mread - case 197: goto step_next; - case 198: _wait();_mread(cpu->wz++);goto step_next; - case 199: cpu->hlx[cpu->hlx_idx].l=_gd();goto step_next; - // -- mread - case 200: goto step_next; - case 201: _wait();_mread(cpu->wz);goto step_next; - case 202: cpu->hlx[cpu->hlx_idx].h=_gd();goto step_next; - // -- overlapped - case 203: goto fetch_next; - - // 2B: DEC HL (M:2 T:6) - // -- generic - case 204: cpu->hlx[cpu->hlx_idx].hl--;goto step_next; - case 205: goto step_next; - // -- overlapped - case 206: goto fetch_next; - - // 2C: INC L (M:1 T:4) - // -- overlapped - case 207: cpu->hlx[cpu->hlx_idx].l=_z80_inc8(cpu,cpu->hlx[cpu->hlx_idx].l);goto fetch_next; - - // 2D: DEC L (M:1 T:4) - // -- overlapped - case 208: cpu->hlx[cpu->hlx_idx].l=_z80_dec8(cpu,cpu->hlx[cpu->hlx_idx].l);goto fetch_next; - - // 2E: LD L,n (M:2 T:7) - // -- mread - case 209: goto step_next; - case 210: _wait();_mread(cpu->pc++);goto step_next; - case 211: cpu->hlx[cpu->hlx_idx].l=_gd();goto step_next; - // -- overlapped - case 212: goto fetch_next; - - // 2F: CPL (M:1 T:4) - // -- overlapped - case 213: _z80_cpl(cpu);goto fetch_next; - - // 30: JR NC,d (M:3 T:12) - // -- mread - case 214: goto step_next; - case 215: _wait();_mread(cpu->pc++);goto step_next; - case 216: cpu->dlatch=_gd();if(!(_cc_nc)){_skip(5);};goto step_next; - // -- generic - case 217: cpu->pc+=(int8_t)cpu->dlatch;cpu->wz=cpu->pc;goto step_next; - case 218: goto step_next; - case 219: goto step_next; - case 220: goto step_next; - case 221: goto step_next; - // -- overlapped - case 222: goto fetch_next; - - // 31: LD SP,nn (M:3 T:10) - // -- mread - case 223: goto step_next; - case 224: _wait();_mread(cpu->pc++);goto step_next; - case 225: cpu->spl=_gd();goto step_next; - // -- mread - case 226: goto step_next; - case 227: _wait();_mread(cpu->pc++);goto step_next; - case 228: cpu->sph=_gd();goto step_next; - // -- overlapped - case 229: goto fetch_next; - - // 32: LD (nn),A (M:4 T:13) - // -- mread - case 230: goto step_next; - case 231: _wait();_mread(cpu->pc++);goto step_next; - case 232: cpu->wzl=_gd();goto step_next; - // -- mread - case 233: goto step_next; - case 234: _wait();_mread(cpu->pc++);goto step_next; - case 235: cpu->wzh=_gd();goto step_next; - // -- mwrite - case 236: goto step_next; - case 237: _wait();_mwrite(cpu->wz++,cpu->a);cpu->wzh=cpu->a;goto step_next; - case 238: goto step_next; - // -- overlapped - case 239: goto fetch_next; - - // 33: INC SP (M:2 T:6) - // -- generic - case 240: cpu->sp++;goto step_next; - case 241: goto step_next; - // -- overlapped - case 242: goto fetch_next; - - // 34: INC (HL) (M:3 T:11) - // -- mread - case 243: goto step_next; - case 244: _wait();_mread(cpu->addr);goto step_next; - case 245: cpu->dlatch=_gd();cpu->dlatch=_z80_inc8(cpu,cpu->dlatch);goto step_next; - case 246: goto step_next; - // -- mwrite - case 247: goto step_next; - case 248: _wait();_mwrite(cpu->addr,cpu->dlatch);goto step_next; - case 249: goto step_next; - // -- overlapped - case 250: goto fetch_next; - - // 35: DEC (HL) (M:3 T:11) - // -- mread - case 251: goto step_next; - case 252: _wait();_mread(cpu->addr);goto step_next; - case 253: cpu->dlatch=_gd();cpu->dlatch=_z80_dec8(cpu,cpu->dlatch);goto step_next; - case 254: goto step_next; - // -- mwrite - case 255: goto step_next; - case 256: _wait();_mwrite(cpu->addr,cpu->dlatch);goto step_next; - case 257: goto step_next; - // -- overlapped - case 258: goto fetch_next; - - // 36: LD (HL),n (M:3 T:10) - // -- mread - case 259: goto step_next; - case 260: _wait();_mread(cpu->pc++);goto step_next; - case 261: cpu->dlatch=_gd();goto step_next; - // -- mwrite - case 262: goto step_next; - case 263: _wait();_mwrite(cpu->addr,cpu->dlatch);goto step_next; - case 264: goto step_next; - // -- overlapped - case 265: goto fetch_next; - - // 37: SCF (M:1 T:4) - // -- overlapped - case 266: _z80_scf(cpu);goto fetch_next; - - // 38: JR C,d (M:3 T:12) - // -- mread - case 267: goto step_next; - case 268: _wait();_mread(cpu->pc++);goto step_next; - case 269: cpu->dlatch=_gd();if(!(_cc_c)){_skip(5);};goto step_next; - // -- generic - case 270: cpu->pc+=(int8_t)cpu->dlatch;cpu->wz=cpu->pc;goto step_next; - case 271: goto step_next; - case 272: goto step_next; - case 273: goto step_next; - case 274: goto step_next; - // -- overlapped - case 275: goto fetch_next; - - // 39: ADD HL,SP (M:2 T:11) - // -- generic - case 276: _z80_add16(cpu,cpu->sp);goto step_next; - case 277: goto step_next; - case 278: goto step_next; - case 279: goto step_next; - case 280: goto step_next; - case 281: goto step_next; - case 282: goto step_next; - // -- overlapped - case 283: goto fetch_next; - - // 3A: LD A,(nn) (M:4 T:13) - // -- mread - case 284: goto step_next; - case 285: _wait();_mread(cpu->pc++);goto step_next; - case 286: cpu->wzl=_gd();goto step_next; - // -- mread - case 287: goto step_next; - case 288: _wait();_mread(cpu->pc++);goto step_next; - case 289: cpu->wzh=_gd();goto step_next; - // -- mread - case 290: goto step_next; - case 291: _wait();_mread(cpu->wz++);goto step_next; - case 292: cpu->a=_gd();goto step_next; - // -- overlapped - case 293: goto fetch_next; - - // 3B: DEC SP (M:2 T:6) - // -- generic - case 294: cpu->sp--;goto step_next; - case 295: goto step_next; - // -- overlapped - case 296: goto fetch_next; - - // 3C: INC A (M:1 T:4) - // -- overlapped - case 297: cpu->a=_z80_inc8(cpu,cpu->a);goto fetch_next; - - // 3D: DEC A (M:1 T:4) - // -- overlapped - case 298: cpu->a=_z80_dec8(cpu,cpu->a);goto fetch_next; - - // 3E: LD A,n (M:2 T:7) - // -- mread - case 299: goto step_next; - case 300: _wait();_mread(cpu->pc++);goto step_next; - case 301: cpu->a=_gd();goto step_next; - // -- overlapped - case 302: goto fetch_next; - - // 3F: CCF (M:1 T:4) - // -- overlapped - case 303: _z80_ccf(cpu);goto fetch_next; - - // 40: LD B,B (M:1 T:4) - // -- overlapped - case 304: cpu->b=cpu->b;goto fetch_next; - - // 41: LD B,C (M:1 T:4) - // -- overlapped - case 305: cpu->b=cpu->c;goto fetch_next; - - // 42: LD B,D (M:1 T:4) - // -- overlapped - case 306: cpu->b=cpu->d;goto fetch_next; - - // 43: LD B,E (M:1 T:4) - // -- overlapped - case 307: cpu->b=cpu->e;goto fetch_next; - - // 44: LD B,H (M:1 T:4) - // -- overlapped - case 308: cpu->b=cpu->hlx[cpu->hlx_idx].h;goto fetch_next; - - // 45: LD B,L (M:1 T:4) - // -- overlapped - case 309: cpu->b=cpu->hlx[cpu->hlx_idx].l;goto fetch_next; - - // 46: LD B,(HL) (M:2 T:7) - // -- mread - case 310: goto step_next; - case 311: _wait();_mread(cpu->addr);goto step_next; - case 312: cpu->b=_gd();goto step_next; - // -- overlapped - case 313: goto fetch_next; - - // 47: LD B,A (M:1 T:4) - // -- overlapped - case 314: cpu->b=cpu->a;goto fetch_next; - - // 48: LD C,B (M:1 T:4) - // -- overlapped - case 315: cpu->c=cpu->b;goto fetch_next; - - // 49: LD C,C (M:1 T:4) - // -- overlapped - case 316: cpu->c=cpu->c;goto fetch_next; - - // 4A: LD C,D (M:1 T:4) - // -- overlapped - case 317: cpu->c=cpu->d;goto fetch_next; - - // 4B: LD C,E (M:1 T:4) - // -- overlapped - case 318: cpu->c=cpu->e;goto fetch_next; - - // 4C: LD C,H (M:1 T:4) - // -- overlapped - case 319: cpu->c=cpu->hlx[cpu->hlx_idx].h;goto fetch_next; - - // 4D: LD C,L (M:1 T:4) - // -- overlapped - case 320: cpu->c=cpu->hlx[cpu->hlx_idx].l;goto fetch_next; - - // 4E: LD C,(HL) (M:2 T:7) - // -- mread - case 321: goto step_next; - case 322: _wait();_mread(cpu->addr);goto step_next; - case 323: cpu->c=_gd();goto step_next; - // -- overlapped - case 324: goto fetch_next; - - // 4F: LD C,A (M:1 T:4) - // -- overlapped - case 325: cpu->c=cpu->a;goto fetch_next; - - // 50: LD D,B (M:1 T:4) - // -- overlapped - case 326: cpu->d=cpu->b;goto fetch_next; - - // 51: LD D,C (M:1 T:4) - // -- overlapped - case 327: cpu->d=cpu->c;goto fetch_next; - - // 52: LD D,D (M:1 T:4) - // -- overlapped - case 328: cpu->d=cpu->d;goto fetch_next; - - // 53: LD D,E (M:1 T:4) - // -- overlapped - case 329: cpu->d=cpu->e;goto fetch_next; - - // 54: LD D,H (M:1 T:4) - // -- overlapped - case 330: cpu->d=cpu->hlx[cpu->hlx_idx].h;goto fetch_next; - - // 55: LD D,L (M:1 T:4) - // -- overlapped - case 331: cpu->d=cpu->hlx[cpu->hlx_idx].l;goto fetch_next; - - // 56: LD D,(HL) (M:2 T:7) - // -- mread - case 332: goto step_next; - case 333: _wait();_mread(cpu->addr);goto step_next; - case 334: cpu->d=_gd();goto step_next; - // -- overlapped - case 335: goto fetch_next; - - // 57: LD D,A (M:1 T:4) - // -- overlapped - case 336: cpu->d=cpu->a;goto fetch_next; - - // 58: LD E,B (M:1 T:4) - // -- overlapped - case 337: cpu->e=cpu->b;goto fetch_next; - - // 59: LD E,C (M:1 T:4) - // -- overlapped - case 338: cpu->e=cpu->c;goto fetch_next; - - // 5A: LD E,D (M:1 T:4) - // -- overlapped - case 339: cpu->e=cpu->d;goto fetch_next; - - // 5B: LD E,E (M:1 T:4) - // -- overlapped - case 340: cpu->e=cpu->e;goto fetch_next; - - // 5C: LD E,H (M:1 T:4) - // -- overlapped - case 341: cpu->e=cpu->hlx[cpu->hlx_idx].h;goto fetch_next; - - // 5D: LD E,L (M:1 T:4) - // -- overlapped - case 342: cpu->e=cpu->hlx[cpu->hlx_idx].l;goto fetch_next; - - // 5E: LD E,(HL) (M:2 T:7) - // -- mread - case 343: goto step_next; - case 344: _wait();_mread(cpu->addr);goto step_next; - case 345: cpu->e=_gd();goto step_next; - // -- overlapped - case 346: goto fetch_next; - - // 5F: LD E,A (M:1 T:4) - // -- overlapped - case 347: cpu->e=cpu->a;goto fetch_next; - - // 60: LD H,B (M:1 T:4) - // -- overlapped - case 348: cpu->hlx[cpu->hlx_idx].h=cpu->b;goto fetch_next; - - // 61: LD H,C (M:1 T:4) - // -- overlapped - case 349: cpu->hlx[cpu->hlx_idx].h=cpu->c;goto fetch_next; - - // 62: LD H,D (M:1 T:4) - // -- overlapped - case 350: cpu->hlx[cpu->hlx_idx].h=cpu->d;goto fetch_next; - - // 63: LD H,E (M:1 T:4) - // -- overlapped - case 351: cpu->hlx[cpu->hlx_idx].h=cpu->e;goto fetch_next; - - // 64: LD H,H (M:1 T:4) - // -- overlapped - case 352: cpu->hlx[cpu->hlx_idx].h=cpu->hlx[cpu->hlx_idx].h;goto fetch_next; - - // 65: LD H,L (M:1 T:4) - // -- overlapped - case 353: cpu->hlx[cpu->hlx_idx].h=cpu->hlx[cpu->hlx_idx].l;goto fetch_next; - - // 66: LD H,(HL) (M:2 T:7) - // -- mread - case 354: goto step_next; - case 355: _wait();_mread(cpu->addr);goto step_next; - case 356: cpu->h=_gd();goto step_next; - // -- overlapped - case 357: goto fetch_next; - - // 67: LD H,A (M:1 T:4) - // -- overlapped - case 358: cpu->hlx[cpu->hlx_idx].h=cpu->a;goto fetch_next; - - // 68: LD L,B (M:1 T:4) - // -- overlapped - case 359: cpu->hlx[cpu->hlx_idx].l=cpu->b;goto fetch_next; - - // 69: LD L,C (M:1 T:4) - // -- overlapped - case 360: cpu->hlx[cpu->hlx_idx].l=cpu->c;goto fetch_next; - - // 6A: LD L,D (M:1 T:4) - // -- overlapped - case 361: cpu->hlx[cpu->hlx_idx].l=cpu->d;goto fetch_next; - - // 6B: LD L,E (M:1 T:4) - // -- overlapped - case 362: cpu->hlx[cpu->hlx_idx].l=cpu->e;goto fetch_next; - - // 6C: LD L,H (M:1 T:4) - // -- overlapped - case 363: cpu->hlx[cpu->hlx_idx].l=cpu->hlx[cpu->hlx_idx].h;goto fetch_next; - - // 6D: LD L,L (M:1 T:4) - // -- overlapped - case 364: cpu->hlx[cpu->hlx_idx].l=cpu->hlx[cpu->hlx_idx].l;goto fetch_next; - - // 6E: LD L,(HL) (M:2 T:7) - // -- mread - case 365: goto step_next; - case 366: _wait();_mread(cpu->addr);goto step_next; - case 367: cpu->l=_gd();goto step_next; - // -- overlapped - case 368: goto fetch_next; - - // 6F: LD L,A (M:1 T:4) - // -- overlapped - case 369: cpu->hlx[cpu->hlx_idx].l=cpu->a;goto fetch_next; - - // 70: LD (HL),B (M:2 T:7) - // -- mwrite - case 370: goto step_next; - case 371: _wait();_mwrite(cpu->addr,cpu->b);goto step_next; - case 372: goto step_next; - // -- overlapped - case 373: goto fetch_next; - - // 71: LD (HL),C (M:2 T:7) - // -- mwrite - case 374: goto step_next; - case 375: _wait();_mwrite(cpu->addr,cpu->c);goto step_next; - case 376: goto step_next; - // -- overlapped - case 377: goto fetch_next; - - // 72: LD (HL),D (M:2 T:7) - // -- mwrite - case 378: goto step_next; - case 379: _wait();_mwrite(cpu->addr,cpu->d);goto step_next; - case 380: goto step_next; - // -- overlapped - case 381: goto fetch_next; - - // 73: LD (HL),E (M:2 T:7) - // -- mwrite - case 382: goto step_next; - case 383: _wait();_mwrite(cpu->addr,cpu->e);goto step_next; - case 384: goto step_next; - // -- overlapped - case 385: goto fetch_next; - - // 74: LD (HL),H (M:2 T:7) - // -- mwrite - case 386: goto step_next; - case 387: _wait();_mwrite(cpu->addr,cpu->h);goto step_next; - case 388: goto step_next; - // -- overlapped - case 389: goto fetch_next; - - // 75: LD (HL),L (M:2 T:7) - // -- mwrite - case 390: goto step_next; - case 391: _wait();_mwrite(cpu->addr,cpu->l);goto step_next; - case 392: goto step_next; - // -- overlapped - case 393: goto fetch_next; - - // 76: HALT (M:1 T:4) - // -- overlapped - case 394: pins=_z80_halt(cpu,pins);goto fetch_next; - - // 77: LD (HL),A (M:2 T:7) - // -- mwrite - case 395: goto step_next; - case 396: _wait();_mwrite(cpu->addr,cpu->a);goto step_next; - case 397: goto step_next; - // -- overlapped - case 398: goto fetch_next; - - // 78: LD A,B (M:1 T:4) - // -- overlapped - case 399: cpu->a=cpu->b;goto fetch_next; - - // 79: LD A,C (M:1 T:4) - // -- overlapped - case 400: cpu->a=cpu->c;goto fetch_next; - - // 7A: LD A,D (M:1 T:4) - // -- overlapped - case 401: cpu->a=cpu->d;goto fetch_next; - - // 7B: LD A,E (M:1 T:4) - // -- overlapped - case 402: cpu->a=cpu->e;goto fetch_next; - - // 7C: LD A,H (M:1 T:4) - // -- overlapped - case 403: cpu->a=cpu->hlx[cpu->hlx_idx].h;goto fetch_next; - - // 7D: LD A,L (M:1 T:4) - // -- overlapped - case 404: cpu->a=cpu->hlx[cpu->hlx_idx].l;goto fetch_next; - - // 7E: LD A,(HL) (M:2 T:7) - // -- mread - case 405: goto step_next; - case 406: _wait();_mread(cpu->addr);goto step_next; - case 407: cpu->a=_gd();goto step_next; - // -- overlapped - case 408: goto fetch_next; - - // 7F: LD A,A (M:1 T:4) - // -- overlapped - case 409: cpu->a=cpu->a;goto fetch_next; - - // 80: ADD B (M:1 T:4) - // -- overlapped - case 410: _z80_add8(cpu,cpu->b);goto fetch_next; - - // 81: ADD C (M:1 T:4) - // -- overlapped - case 411: _z80_add8(cpu,cpu->c);goto fetch_next; - - // 82: ADD D (M:1 T:4) - // -- overlapped - case 412: _z80_add8(cpu,cpu->d);goto fetch_next; - - // 83: ADD E (M:1 T:4) - // -- overlapped - case 413: _z80_add8(cpu,cpu->e);goto fetch_next; - - // 84: ADD H (M:1 T:4) - // -- overlapped - case 414: _z80_add8(cpu,cpu->hlx[cpu->hlx_idx].h);goto fetch_next; - - // 85: ADD L (M:1 T:4) - // -- overlapped - case 415: _z80_add8(cpu,cpu->hlx[cpu->hlx_idx].l);goto fetch_next; - - // 86: ADD (HL) (M:2 T:7) - // -- mread - case 416: goto step_next; - case 417: _wait();_mread(cpu->addr);goto step_next; - case 418: cpu->dlatch=_gd();goto step_next; - // -- overlapped - case 419: _z80_add8(cpu,cpu->dlatch);goto fetch_next; - - // 87: ADD A (M:1 T:4) - // -- overlapped - case 420: _z80_add8(cpu,cpu->a);goto fetch_next; - - // 88: ADC B (M:1 T:4) - // -- overlapped - case 421: _z80_adc8(cpu,cpu->b);goto fetch_next; - - // 89: ADC C (M:1 T:4) - // -- overlapped - case 422: _z80_adc8(cpu,cpu->c);goto fetch_next; - - // 8A: ADC D (M:1 T:4) - // -- overlapped - case 423: _z80_adc8(cpu,cpu->d);goto fetch_next; - - // 8B: ADC E (M:1 T:4) - // -- overlapped - case 424: _z80_adc8(cpu,cpu->e);goto fetch_next; - - // 8C: ADC H (M:1 T:4) - // -- overlapped - case 425: _z80_adc8(cpu,cpu->hlx[cpu->hlx_idx].h);goto fetch_next; - - // 8D: ADC L (M:1 T:4) - // -- overlapped - case 426: _z80_adc8(cpu,cpu->hlx[cpu->hlx_idx].l);goto fetch_next; - - // 8E: ADC (HL) (M:2 T:7) - // -- mread - case 427: goto step_next; - case 428: _wait();_mread(cpu->addr);goto step_next; - case 429: cpu->dlatch=_gd();goto step_next; - // -- overlapped - case 430: _z80_adc8(cpu,cpu->dlatch);goto fetch_next; - - // 8F: ADC A (M:1 T:4) - // -- overlapped - case 431: _z80_adc8(cpu,cpu->a);goto fetch_next; - - // 90: SUB B (M:1 T:4) - // -- overlapped - case 432: _z80_sub8(cpu,cpu->b);goto fetch_next; - - // 91: SUB C (M:1 T:4) - // -- overlapped - case 433: _z80_sub8(cpu,cpu->c);goto fetch_next; - - // 92: SUB D (M:1 T:4) - // -- overlapped - case 434: _z80_sub8(cpu,cpu->d);goto fetch_next; - - // 93: SUB E (M:1 T:4) - // -- overlapped - case 435: _z80_sub8(cpu,cpu->e);goto fetch_next; - - // 94: SUB H (M:1 T:4) - // -- overlapped - case 436: _z80_sub8(cpu,cpu->hlx[cpu->hlx_idx].h);goto fetch_next; - - // 95: SUB L (M:1 T:4) - // -- overlapped - case 437: _z80_sub8(cpu,cpu->hlx[cpu->hlx_idx].l);goto fetch_next; - - // 96: SUB (HL) (M:2 T:7) - // -- mread - case 438: goto step_next; - case 439: _wait();_mread(cpu->addr);goto step_next; - case 440: cpu->dlatch=_gd();goto step_next; - // -- overlapped - case 441: _z80_sub8(cpu,cpu->dlatch);goto fetch_next; - - // 97: SUB A (M:1 T:4) - // -- overlapped - case 442: _z80_sub8(cpu,cpu->a);goto fetch_next; - - // 98: SBC B (M:1 T:4) - // -- overlapped - case 443: _z80_sbc8(cpu,cpu->b);goto fetch_next; - - // 99: SBC C (M:1 T:4) - // -- overlapped - case 444: _z80_sbc8(cpu,cpu->c);goto fetch_next; - - // 9A: SBC D (M:1 T:4) - // -- overlapped - case 445: _z80_sbc8(cpu,cpu->d);goto fetch_next; - - // 9B: SBC E (M:1 T:4) - // -- overlapped - case 446: _z80_sbc8(cpu,cpu->e);goto fetch_next; - - // 9C: SBC H (M:1 T:4) - // -- overlapped - case 447: _z80_sbc8(cpu,cpu->hlx[cpu->hlx_idx].h);goto fetch_next; - - // 9D: SBC L (M:1 T:4) - // -- overlapped - case 448: _z80_sbc8(cpu,cpu->hlx[cpu->hlx_idx].l);goto fetch_next; - - // 9E: SBC (HL) (M:2 T:7) - // -- mread - case 449: goto step_next; - case 450: _wait();_mread(cpu->addr);goto step_next; - case 451: cpu->dlatch=_gd();goto step_next; - // -- overlapped - case 452: _z80_sbc8(cpu,cpu->dlatch);goto fetch_next; - - // 9F: SBC A (M:1 T:4) - // -- overlapped - case 453: _z80_sbc8(cpu,cpu->a);goto fetch_next; - - // A0: AND B (M:1 T:4) - // -- overlapped - case 454: _z80_and8(cpu,cpu->b);goto fetch_next; - - // A1: AND C (M:1 T:4) - // -- overlapped - case 455: _z80_and8(cpu,cpu->c);goto fetch_next; - - // A2: AND D (M:1 T:4) - // -- overlapped - case 456: _z80_and8(cpu,cpu->d);goto fetch_next; - - // A3: AND E (M:1 T:4) - // -- overlapped - case 457: _z80_and8(cpu,cpu->e);goto fetch_next; - - // A4: AND H (M:1 T:4) - // -- overlapped - case 458: _z80_and8(cpu,cpu->hlx[cpu->hlx_idx].h);goto fetch_next; - - // A5: AND L (M:1 T:4) - // -- overlapped - case 459: _z80_and8(cpu,cpu->hlx[cpu->hlx_idx].l);goto fetch_next; - - // A6: AND (HL) (M:2 T:7) - // -- mread - case 460: goto step_next; - case 461: _wait();_mread(cpu->addr);goto step_next; - case 462: cpu->dlatch=_gd();goto step_next; - // -- overlapped - case 463: _z80_and8(cpu,cpu->dlatch);goto fetch_next; - - // A7: AND A (M:1 T:4) - // -- overlapped - case 464: _z80_and8(cpu,cpu->a);goto fetch_next; - - // A8: XOR B (M:1 T:4) - // -- overlapped - case 465: _z80_xor8(cpu,cpu->b);goto fetch_next; - - // A9: XOR C (M:1 T:4) - // -- overlapped - case 466: _z80_xor8(cpu,cpu->c);goto fetch_next; - - // AA: XOR D (M:1 T:4) - // -- overlapped - case 467: _z80_xor8(cpu,cpu->d);goto fetch_next; - - // AB: XOR E (M:1 T:4) - // -- overlapped - case 468: _z80_xor8(cpu,cpu->e);goto fetch_next; - - // AC: XOR H (M:1 T:4) - // -- overlapped - case 469: _z80_xor8(cpu,cpu->hlx[cpu->hlx_idx].h);goto fetch_next; - - // AD: XOR L (M:1 T:4) - // -- overlapped - case 470: _z80_xor8(cpu,cpu->hlx[cpu->hlx_idx].l);goto fetch_next; - - // AE: XOR (HL) (M:2 T:7) - // -- mread - case 471: goto step_next; - case 472: _wait();_mread(cpu->addr);goto step_next; - case 473: cpu->dlatch=_gd();goto step_next; - // -- overlapped - case 474: _z80_xor8(cpu,cpu->dlatch);goto fetch_next; - - // AF: XOR A (M:1 T:4) - // -- overlapped - case 475: _z80_xor8(cpu,cpu->a);goto fetch_next; - - // B0: OR B (M:1 T:4) - // -- overlapped - case 476: _z80_or8(cpu,cpu->b);goto fetch_next; - - // B1: OR C (M:1 T:4) - // -- overlapped - case 477: _z80_or8(cpu,cpu->c);goto fetch_next; - - // B2: OR D (M:1 T:4) - // -- overlapped - case 478: _z80_or8(cpu,cpu->d);goto fetch_next; - - // B3: OR E (M:1 T:4) - // -- overlapped - case 479: _z80_or8(cpu,cpu->e);goto fetch_next; - - // B4: OR H (M:1 T:4) - // -- overlapped - case 480: _z80_or8(cpu,cpu->hlx[cpu->hlx_idx].h);goto fetch_next; - - // B5: OR L (M:1 T:4) - // -- overlapped - case 481: _z80_or8(cpu,cpu->hlx[cpu->hlx_idx].l);goto fetch_next; - - // B6: OR (HL) (M:2 T:7) - // -- mread - case 482: goto step_next; - case 483: _wait();_mread(cpu->addr);goto step_next; - case 484: cpu->dlatch=_gd();goto step_next; - // -- overlapped - case 485: _z80_or8(cpu,cpu->dlatch);goto fetch_next; - - // B7: OR A (M:1 T:4) - // -- overlapped - case 486: _z80_or8(cpu,cpu->a);goto fetch_next; - - // B8: CP B (M:1 T:4) - // -- overlapped - case 487: _z80_cp8(cpu,cpu->b);goto fetch_next; - - // B9: CP C (M:1 T:4) - // -- overlapped - case 488: _z80_cp8(cpu,cpu->c);goto fetch_next; - - // BA: CP D (M:1 T:4) - // -- overlapped - case 489: _z80_cp8(cpu,cpu->d);goto fetch_next; - - // BB: CP E (M:1 T:4) - // -- overlapped - case 490: _z80_cp8(cpu,cpu->e);goto fetch_next; - - // BC: CP H (M:1 T:4) - // -- overlapped - case 491: _z80_cp8(cpu,cpu->hlx[cpu->hlx_idx].h);goto fetch_next; - - // BD: CP L (M:1 T:4) - // -- overlapped - case 492: _z80_cp8(cpu,cpu->hlx[cpu->hlx_idx].l);goto fetch_next; - - // BE: CP (HL) (M:2 T:7) - // -- mread - case 493: goto step_next; - case 494: _wait();_mread(cpu->addr);goto step_next; - case 495: cpu->dlatch=_gd();goto step_next; - // -- overlapped - case 496: _z80_cp8(cpu,cpu->dlatch);goto fetch_next; - - // BF: CP A (M:1 T:4) - // -- overlapped - case 497: _z80_cp8(cpu,cpu->a);goto fetch_next; - - // C0: RET NZ (M:4 T:11) - // -- generic - case 498: if(!_cc_nz){_skip(6);};goto step_next; - // -- mread - case 499: goto step_next; - case 500: _wait();_mread(cpu->sp++);goto step_next; - case 501: cpu->wzl=_gd();goto step_next; - // -- mread - case 502: goto step_next; - case 503: _wait();_mread(cpu->sp++);goto step_next; - case 504: cpu->wzh=_gd();cpu->pc=cpu->wz;goto step_next; - // -- overlapped - case 505: goto fetch_next; - - // C1: POP BC (M:3 T:10) - // -- mread - case 506: goto step_next; - case 507: _wait();_mread(cpu->sp++);goto step_next; - case 508: cpu->c=_gd();goto step_next; - // -- mread - case 509: goto step_next; - case 510: _wait();_mread(cpu->sp++);goto step_next; - case 511: cpu->b=_gd();goto step_next; - // -- overlapped - case 512: goto fetch_next; - - // C2: JP NZ,nn (M:3 T:10) - // -- mread - case 513: goto step_next; - case 514: _wait();_mread(cpu->pc++);goto step_next; - case 515: cpu->wzl=_gd();goto step_next; - // -- mread - case 516: goto step_next; - case 517: _wait();_mread(cpu->pc++);goto step_next; - case 518: cpu->wzh=_gd();if(_cc_nz){cpu->pc=cpu->wz;};goto step_next; - // -- overlapped - case 519: goto fetch_next; - - // C3: JP nn (M:3 T:10) - // -- mread - case 520: goto step_next; - case 521: _wait();_mread(cpu->pc++);goto step_next; - case 522: cpu->wzl=_gd();goto step_next; - // -- mread - case 523: goto step_next; - case 524: _wait();_mread(cpu->pc++);goto step_next; - case 525: cpu->wzh=_gd();cpu->pc=cpu->wz;goto step_next; - // -- overlapped - case 526: goto fetch_next; - - // C4: CALL NZ,nn (M:6 T:17) - // -- mread - case 527: goto step_next; - case 528: _wait();_mread(cpu->pc++);goto step_next; - case 529: cpu->wzl=_gd();goto step_next; - // -- mread - case 530: goto step_next; - case 531: _wait();_mread(cpu->pc++);goto step_next; - case 532: cpu->wzh=_gd();if (!_cc_nz){_skip(7);};goto step_next; - // -- generic - case 533: goto step_next; - // -- mwrite - case 534: goto step_next; - case 535: _wait();_mwrite(--cpu->sp,cpu->pch);goto step_next; - case 536: goto step_next; - // -- mwrite - case 537: goto step_next; - case 538: _wait();_mwrite(--cpu->sp,cpu->pcl);cpu->pc=cpu->wz;goto step_next; - case 539: goto step_next; - // -- overlapped - case 540: goto fetch_next; - - // C5: PUSH BC (M:4 T:11) - // -- generic - case 541: goto step_next; - // -- mwrite - case 542: goto step_next; - case 543: _wait();_mwrite(--cpu->sp,cpu->b);goto step_next; - case 544: goto step_next; - // -- mwrite - case 545: goto step_next; - case 546: _wait();_mwrite(--cpu->sp,cpu->c);goto step_next; - case 547: goto step_next; - // -- overlapped - case 548: goto fetch_next; - - // C6: ADD n (M:2 T:7) - // -- mread - case 549: goto step_next; - case 550: _wait();_mread(cpu->pc++);goto step_next; - case 551: cpu->dlatch=_gd();goto step_next; - // -- overlapped - case 552: _z80_add8(cpu,cpu->dlatch);goto fetch_next; - - // C7: RST 0h (M:4 T:11) - // -- generic - case 553: goto step_next; - // -- mwrite - case 554: goto step_next; - case 555: _wait();_mwrite(--cpu->sp,cpu->pch);goto step_next; - case 556: goto step_next; - // -- mwrite - case 557: goto step_next; - case 558: _wait();_mwrite(--cpu->sp,cpu->pcl);cpu->wz=0x00;cpu->pc=cpu->wz;goto step_next; - case 559: goto step_next; - // -- overlapped - case 560: goto fetch_next; - - // C8: RET Z (M:4 T:11) - // -- generic - case 561: if(!_cc_z){_skip(6);};goto step_next; - // -- mread - case 562: goto step_next; - case 563: _wait();_mread(cpu->sp++);goto step_next; - case 564: cpu->wzl=_gd();goto step_next; - // -- mread - case 565: goto step_next; - case 566: _wait();_mread(cpu->sp++);goto step_next; - case 567: cpu->wzh=_gd();cpu->pc=cpu->wz;goto step_next; - // -- overlapped - case 568: goto fetch_next; - - // C9: RET (M:3 T:10) - // -- mread - case 569: goto step_next; - case 570: _wait();_mread(cpu->sp++);goto step_next; - case 571: cpu->wzl=_gd();goto step_next; - // -- mread - case 572: goto step_next; - case 573: _wait();_mread(cpu->sp++);goto step_next; - case 574: cpu->wzh=_gd();cpu->pc=cpu->wz;goto step_next; - // -- overlapped - case 575: goto fetch_next; - - // CA: JP Z,nn (M:3 T:10) - // -- mread - case 576: goto step_next; - case 577: _wait();_mread(cpu->pc++);goto step_next; - case 578: cpu->wzl=_gd();goto step_next; - // -- mread - case 579: goto step_next; - case 580: _wait();_mread(cpu->pc++);goto step_next; - case 581: cpu->wzh=_gd();if(_cc_z){cpu->pc=cpu->wz;};goto step_next; - // -- overlapped - case 582: goto fetch_next; - - // CB: CB prefix (M:1 T:4) - // -- overlapped - case 583: _fetch_cb();goto step_next; - - // CC: CALL Z,nn (M:6 T:17) - // -- mread - case 584: goto step_next; - case 585: _wait();_mread(cpu->pc++);goto step_next; - case 586: cpu->wzl=_gd();goto step_next; - // -- mread - case 587: goto step_next; - case 588: _wait();_mread(cpu->pc++);goto step_next; - case 589: cpu->wzh=_gd();if (!_cc_z){_skip(7);};goto step_next; - // -- generic - case 590: goto step_next; - // -- mwrite - case 591: goto step_next; - case 592: _wait();_mwrite(--cpu->sp,cpu->pch);goto step_next; - case 593: goto step_next; - // -- mwrite - case 594: goto step_next; - case 595: _wait();_mwrite(--cpu->sp,cpu->pcl);cpu->pc=cpu->wz;goto step_next; - case 596: goto step_next; - // -- overlapped - case 597: goto fetch_next; - - // CD: CALL nn (M:5 T:17) - // -- mread - case 598: goto step_next; - case 599: _wait();_mread(cpu->pc++);goto step_next; - case 600: cpu->wzl=_gd();goto step_next; - // -- mread - case 601: goto step_next; - case 602: _wait();_mread(cpu->pc++);goto step_next; - case 603: cpu->wzh=_gd();goto step_next; - case 604: goto step_next; - // -- mwrite - case 605: goto step_next; - case 606: _wait();_mwrite(--cpu->sp,cpu->pch);goto step_next; - case 607: goto step_next; - // -- mwrite - case 608: goto step_next; - case 609: _wait();_mwrite(--cpu->sp,cpu->pcl);cpu->pc=cpu->wz;goto step_next; - case 610: goto step_next; - // -- overlapped - case 611: goto fetch_next; - - // CE: ADC n (M:2 T:7) - // -- mread - case 612: goto step_next; - case 613: _wait();_mread(cpu->pc++);goto step_next; - case 614: cpu->dlatch=_gd();goto step_next; - // -- overlapped - case 615: _z80_adc8(cpu,cpu->dlatch);goto fetch_next; - - // CF: RST 8h (M:4 T:11) - // -- generic - case 616: goto step_next; - // -- mwrite - case 617: goto step_next; - case 618: _wait();_mwrite(--cpu->sp,cpu->pch);goto step_next; - case 619: goto step_next; - // -- mwrite - case 620: goto step_next; - case 621: _wait();_mwrite(--cpu->sp,cpu->pcl);cpu->wz=0x08;cpu->pc=cpu->wz;goto step_next; - case 622: goto step_next; - // -- overlapped - case 623: goto fetch_next; - - // D0: RET NC (M:4 T:11) - // -- generic - case 624: if(!_cc_nc){_skip(6);};goto step_next; - // -- mread - case 625: goto step_next; - case 626: _wait();_mread(cpu->sp++);goto step_next; - case 627: cpu->wzl=_gd();goto step_next; - // -- mread - case 628: goto step_next; - case 629: _wait();_mread(cpu->sp++);goto step_next; - case 630: cpu->wzh=_gd();cpu->pc=cpu->wz;goto step_next; - // -- overlapped - case 631: goto fetch_next; - - // D1: POP DE (M:3 T:10) - // -- mread - case 632: goto step_next; - case 633: _wait();_mread(cpu->sp++);goto step_next; - case 634: cpu->e=_gd();goto step_next; - // -- mread - case 635: goto step_next; - case 636: _wait();_mread(cpu->sp++);goto step_next; - case 637: cpu->d=_gd();goto step_next; - // -- overlapped - case 638: goto fetch_next; - - // D2: JP NC,nn (M:3 T:10) - // -- mread - case 639: goto step_next; - case 640: _wait();_mread(cpu->pc++);goto step_next; - case 641: cpu->wzl=_gd();goto step_next; - // -- mread - case 642: goto step_next; - case 643: _wait();_mread(cpu->pc++);goto step_next; - case 644: cpu->wzh=_gd();if(_cc_nc){cpu->pc=cpu->wz;};goto step_next; - // -- overlapped - case 645: goto fetch_next; - - // D3: OUT (n),A (M:3 T:11) - // -- mread - case 646: goto step_next; - case 647: _wait();_mread(cpu->pc++);goto step_next; - case 648: cpu->wzl=_gd();cpu->wzh=cpu->a;goto step_next; - // -- iowrite - case 649: goto step_next; - case 650: _iowrite(cpu->wz,cpu->a);goto step_next; - case 651: _wait();cpu->wzl++;goto step_next; - case 652: goto step_next; - // -- overlapped - case 653: goto fetch_next; - - // D4: CALL NC,nn (M:6 T:17) - // -- mread - case 654: goto step_next; - case 655: _wait();_mread(cpu->pc++);goto step_next; - case 656: cpu->wzl=_gd();goto step_next; - // -- mread - case 657: goto step_next; - case 658: _wait();_mread(cpu->pc++);goto step_next; - case 659: cpu->wzh=_gd();if (!_cc_nc){_skip(7);};goto step_next; - // -- generic - case 660: goto step_next; - // -- mwrite - case 661: goto step_next; - case 662: _wait();_mwrite(--cpu->sp,cpu->pch);goto step_next; - case 663: goto step_next; - // -- mwrite - case 664: goto step_next; - case 665: _wait();_mwrite(--cpu->sp,cpu->pcl);cpu->pc=cpu->wz;goto step_next; - case 666: goto step_next; - // -- overlapped - case 667: goto fetch_next; - - // D5: PUSH DE (M:4 T:11) - // -- generic - case 668: goto step_next; - // -- mwrite - case 669: goto step_next; - case 670: _wait();_mwrite(--cpu->sp,cpu->d);goto step_next; - case 671: goto step_next; - // -- mwrite - case 672: goto step_next; - case 673: _wait();_mwrite(--cpu->sp,cpu->e);goto step_next; - case 674: goto step_next; - // -- overlapped - case 675: goto fetch_next; - - // D6: SUB n (M:2 T:7) - // -- mread - case 676: goto step_next; - case 677: _wait();_mread(cpu->pc++);goto step_next; - case 678: cpu->dlatch=_gd();goto step_next; - // -- overlapped - case 679: _z80_sub8(cpu,cpu->dlatch);goto fetch_next; - - // D7: RST 10h (M:4 T:11) - // -- generic - case 680: goto step_next; - // -- mwrite - case 681: goto step_next; - case 682: _wait();_mwrite(--cpu->sp,cpu->pch);goto step_next; - case 683: goto step_next; - // -- mwrite - case 684: goto step_next; - case 685: _wait();_mwrite(--cpu->sp,cpu->pcl);cpu->wz=0x10;cpu->pc=cpu->wz;goto step_next; - case 686: goto step_next; - // -- overlapped - case 687: goto fetch_next; - - // D8: RET C (M:4 T:11) - // -- generic - case 688: if(!_cc_c){_skip(6);};goto step_next; - // -- mread - case 689: goto step_next; - case 690: _wait();_mread(cpu->sp++);goto step_next; - case 691: cpu->wzl=_gd();goto step_next; - // -- mread - case 692: goto step_next; - case 693: _wait();_mread(cpu->sp++);goto step_next; - case 694: cpu->wzh=_gd();cpu->pc=cpu->wz;goto step_next; - // -- overlapped - case 695: goto fetch_next; - - // D9: EXX (M:1 T:4) - // -- overlapped - case 696: _z80_exx(cpu);goto fetch_next; - - // DA: JP C,nn (M:3 T:10) - // -- mread - case 697: goto step_next; - case 698: _wait();_mread(cpu->pc++);goto step_next; - case 699: cpu->wzl=_gd();goto step_next; - // -- mread - case 700: goto step_next; - case 701: _wait();_mread(cpu->pc++);goto step_next; - case 702: cpu->wzh=_gd();if(_cc_c){cpu->pc=cpu->wz;};goto step_next; - // -- overlapped - case 703: goto fetch_next; - - // DB: IN A,(n) (M:3 T:11) - // -- mread - case 704: goto step_next; - case 705: _wait();_mread(cpu->pc++);goto step_next; - case 706: cpu->wzl=_gd();cpu->wzh=cpu->a;goto step_next; - // -- ioread - case 707: goto step_next; - case 708: goto step_next; - case 709: _wait();_ioread(cpu->wz++);goto step_next; - case 710: cpu->a=_gd();goto step_next; - // -- overlapped - case 711: goto fetch_next; - - // DC: CALL C,nn (M:6 T:17) - // -- mread - case 712: goto step_next; - case 713: _wait();_mread(cpu->pc++);goto step_next; - case 714: cpu->wzl=_gd();goto step_next; - // -- mread - case 715: goto step_next; - case 716: _wait();_mread(cpu->pc++);goto step_next; - case 717: cpu->wzh=_gd();if (!_cc_c){_skip(7);};goto step_next; - // -- generic - case 718: goto step_next; - // -- mwrite - case 719: goto step_next; - case 720: _wait();_mwrite(--cpu->sp,cpu->pch);goto step_next; - case 721: goto step_next; - // -- mwrite - case 722: goto step_next; - case 723: _wait();_mwrite(--cpu->sp,cpu->pcl);cpu->pc=cpu->wz;goto step_next; - case 724: goto step_next; - // -- overlapped - case 725: goto fetch_next; - - // DD: DD prefix (M:1 T:4) - // -- overlapped - case 726: _fetch_dd();goto step_next; - - // DE: SBC n (M:2 T:7) - // -- mread - case 727: goto step_next; - case 728: _wait();_mread(cpu->pc++);goto step_next; - case 729: cpu->dlatch=_gd();goto step_next; - // -- overlapped - case 730: _z80_sbc8(cpu,cpu->dlatch);goto fetch_next; - - // DF: RST 18h (M:4 T:11) - // -- generic - case 731: goto step_next; - // -- mwrite - case 732: goto step_next; - case 733: _wait();_mwrite(--cpu->sp,cpu->pch);goto step_next; - case 734: goto step_next; - // -- mwrite - case 735: goto step_next; - case 736: _wait();_mwrite(--cpu->sp,cpu->pcl);cpu->wz=0x18;cpu->pc=cpu->wz;goto step_next; - case 737: goto step_next; - // -- overlapped - case 738: goto fetch_next; - - // E0: RET PO (M:4 T:11) - // -- generic - case 739: if(!_cc_po){_skip(6);};goto step_next; - // -- mread - case 740: goto step_next; - case 741: _wait();_mread(cpu->sp++);goto step_next; - case 742: cpu->wzl=_gd();goto step_next; - // -- mread - case 743: goto step_next; - case 744: _wait();_mread(cpu->sp++);goto step_next; - case 745: cpu->wzh=_gd();cpu->pc=cpu->wz;goto step_next; - // -- overlapped - case 746: goto fetch_next; - - // E1: POP HL (M:3 T:10) - // -- mread - case 747: goto step_next; - case 748: _wait();_mread(cpu->sp++);goto step_next; - case 749: cpu->hlx[cpu->hlx_idx].l=_gd();goto step_next; - // -- mread - case 750: goto step_next; - case 751: _wait();_mread(cpu->sp++);goto step_next; - case 752: cpu->hlx[cpu->hlx_idx].h=_gd();goto step_next; - // -- overlapped - case 753: goto fetch_next; - - // E2: JP PO,nn (M:3 T:10) - // -- mread - case 754: goto step_next; - case 755: _wait();_mread(cpu->pc++);goto step_next; - case 756: cpu->wzl=_gd();goto step_next; - // -- mread - case 757: goto step_next; - case 758: _wait();_mread(cpu->pc++);goto step_next; - case 759: cpu->wzh=_gd();if(_cc_po){cpu->pc=cpu->wz;};goto step_next; - // -- overlapped - case 760: goto fetch_next; - - // E3: EX (SP),HL (M:5 T:19) - // -- mread - case 761: goto step_next; - case 762: _wait();_mread(cpu->sp);goto step_next; - case 763: cpu->wzl=_gd();goto step_next; - // -- mread - case 764: goto step_next; - case 765: _wait();_mread(cpu->sp+1);goto step_next; - case 766: cpu->wzh=_gd();goto step_next; - case 767: goto step_next; - // -- mwrite - case 768: goto step_next; - case 769: _wait();_mwrite(cpu->sp+1,cpu->hlx[cpu->hlx_idx].h);goto step_next; - case 770: goto step_next; - // -- mwrite - case 771: goto step_next; - case 772: _wait();_mwrite(cpu->sp,cpu->hlx[cpu->hlx_idx].l);cpu->hlx[cpu->hlx_idx].hl=cpu->wz;goto step_next; - case 773: goto step_next; - case 774: goto step_next; - case 775: goto step_next; - // -- overlapped - case 776: goto fetch_next; - - // E4: CALL PO,nn (M:6 T:17) - // -- mread - case 777: goto step_next; - case 778: _wait();_mread(cpu->pc++);goto step_next; - case 779: cpu->wzl=_gd();goto step_next; - // -- mread - case 780: goto step_next; - case 781: _wait();_mread(cpu->pc++);goto step_next; - case 782: cpu->wzh=_gd();if (!_cc_po){_skip(7);};goto step_next; - // -- generic - case 783: goto step_next; - // -- mwrite - case 784: goto step_next; - case 785: _wait();_mwrite(--cpu->sp,cpu->pch);goto step_next; - case 786: goto step_next; - // -- mwrite - case 787: goto step_next; - case 788: _wait();_mwrite(--cpu->sp,cpu->pcl);cpu->pc=cpu->wz;goto step_next; - case 789: goto step_next; - // -- overlapped - case 790: goto fetch_next; - - // E5: PUSH HL (M:4 T:11) - // -- generic - case 791: goto step_next; - // -- mwrite - case 792: goto step_next; - case 793: _wait();_mwrite(--cpu->sp,cpu->hlx[cpu->hlx_idx].h);goto step_next; - case 794: goto step_next; - // -- mwrite - case 795: goto step_next; - case 796: _wait();_mwrite(--cpu->sp,cpu->hlx[cpu->hlx_idx].l);goto step_next; - case 797: goto step_next; - // -- overlapped - case 798: goto fetch_next; - - // E6: AND n (M:2 T:7) - // -- mread - case 799: goto step_next; - case 800: _wait();_mread(cpu->pc++);goto step_next; - case 801: cpu->dlatch=_gd();goto step_next; - // -- overlapped - case 802: _z80_and8(cpu,cpu->dlatch);goto fetch_next; - - // E7: RST 20h (M:4 T:11) - // -- generic - case 803: goto step_next; - // -- mwrite - case 804: goto step_next; - case 805: _wait();_mwrite(--cpu->sp,cpu->pch);goto step_next; - case 806: goto step_next; - // -- mwrite - case 807: goto step_next; - case 808: _wait();_mwrite(--cpu->sp,cpu->pcl);cpu->wz=0x20;cpu->pc=cpu->wz;goto step_next; - case 809: goto step_next; - // -- overlapped - case 810: goto fetch_next; - - // E8: RET PE (M:4 T:11) - // -- generic - case 811: if(!_cc_pe){_skip(6);};goto step_next; - // -- mread - case 812: goto step_next; - case 813: _wait();_mread(cpu->sp++);goto step_next; - case 814: cpu->wzl=_gd();goto step_next; - // -- mread - case 815: goto step_next; - case 816: _wait();_mread(cpu->sp++);goto step_next; - case 817: cpu->wzh=_gd();cpu->pc=cpu->wz;goto step_next; - // -- overlapped - case 818: goto fetch_next; - - // E9: JP HL (M:1 T:4) - // -- overlapped - case 819: cpu->pc=cpu->hlx[cpu->hlx_idx].hl;goto fetch_next; - - // EA: JP PE,nn (M:3 T:10) - // -- mread - case 820: goto step_next; - case 821: _wait();_mread(cpu->pc++);goto step_next; - case 822: cpu->wzl=_gd();goto step_next; - // -- mread - case 823: goto step_next; - case 824: _wait();_mread(cpu->pc++);goto step_next; - case 825: cpu->wzh=_gd();if(_cc_pe){cpu->pc=cpu->wz;};goto step_next; - // -- overlapped - case 826: goto fetch_next; - - // EB: EX DE,HL (M:1 T:4) - // -- overlapped - case 827: _z80_ex_de_hl(cpu);goto fetch_next; - - // EC: CALL PE,nn (M:6 T:17) - // -- mread - case 828: goto step_next; - case 829: _wait();_mread(cpu->pc++);goto step_next; - case 830: cpu->wzl=_gd();goto step_next; - // -- mread - case 831: goto step_next; - case 832: _wait();_mread(cpu->pc++);goto step_next; - case 833: cpu->wzh=_gd();if (!_cc_pe){_skip(7);};goto step_next; - // -- generic - case 834: goto step_next; - // -- mwrite - case 835: goto step_next; - case 836: _wait();_mwrite(--cpu->sp,cpu->pch);goto step_next; - case 837: goto step_next; - // -- mwrite - case 838: goto step_next; - case 839: _wait();_mwrite(--cpu->sp,cpu->pcl);cpu->pc=cpu->wz;goto step_next; - case 840: goto step_next; - // -- overlapped - case 841: goto fetch_next; - - // ED: ED prefix (M:1 T:4) - // -- overlapped - case 842: _fetch_ed();goto step_next; - - // EE: XOR n (M:2 T:7) - // -- mread - case 843: goto step_next; - case 844: _wait();_mread(cpu->pc++);goto step_next; - case 845: cpu->dlatch=_gd();goto step_next; - // -- overlapped - case 846: _z80_xor8(cpu,cpu->dlatch);goto fetch_next; - - // EF: RST 28h (M:4 T:11) - // -- generic - case 847: goto step_next; - // -- mwrite - case 848: goto step_next; - case 849: _wait();_mwrite(--cpu->sp,cpu->pch);goto step_next; - case 850: goto step_next; - // -- mwrite - case 851: goto step_next; - case 852: _wait();_mwrite(--cpu->sp,cpu->pcl);cpu->wz=0x28;cpu->pc=cpu->wz;goto step_next; - case 853: goto step_next; - // -- overlapped - case 854: goto fetch_next; - - // F0: RET P (M:4 T:11) - // -- generic - case 855: if(!_cc_p){_skip(6);};goto step_next; - // -- mread - case 856: goto step_next; - case 857: _wait();_mread(cpu->sp++);goto step_next; - case 858: cpu->wzl=_gd();goto step_next; - // -- mread - case 859: goto step_next; - case 860: _wait();_mread(cpu->sp++);goto step_next; - case 861: cpu->wzh=_gd();cpu->pc=cpu->wz;goto step_next; - // -- overlapped - case 862: goto fetch_next; - - // F1: POP AF (M:3 T:10) - // -- mread - case 863: goto step_next; - case 864: _wait();_mread(cpu->sp++);goto step_next; - case 865: cpu->f=_gd();goto step_next; - // -- mread - case 866: goto step_next; - case 867: _wait();_mread(cpu->sp++);goto step_next; - case 868: cpu->a=_gd();goto step_next; - // -- overlapped - case 869: goto fetch_next; - - // F2: JP P,nn (M:3 T:10) - // -- mread - case 870: goto step_next; - case 871: _wait();_mread(cpu->pc++);goto step_next; - case 872: cpu->wzl=_gd();goto step_next; - // -- mread - case 873: goto step_next; - case 874: _wait();_mread(cpu->pc++);goto step_next; - case 875: cpu->wzh=_gd();if(_cc_p){cpu->pc=cpu->wz;};goto step_next; - // -- overlapped - case 876: goto fetch_next; - - // F3: DI (M:1 T:4) - // -- overlapped - case 877: cpu->iff1=cpu->iff2=false;goto fetch_next; - - // F4: CALL P,nn (M:6 T:17) - // -- mread - case 878: goto step_next; - case 879: _wait();_mread(cpu->pc++);goto step_next; - case 880: cpu->wzl=_gd();goto step_next; - // -- mread - case 881: goto step_next; - case 882: _wait();_mread(cpu->pc++);goto step_next; - case 883: cpu->wzh=_gd();if (!_cc_p){_skip(7);};goto step_next; - // -- generic - case 884: goto step_next; - // -- mwrite - case 885: goto step_next; - case 886: _wait();_mwrite(--cpu->sp,cpu->pch);goto step_next; - case 887: goto step_next; - // -- mwrite - case 888: goto step_next; - case 889: _wait();_mwrite(--cpu->sp,cpu->pcl);cpu->pc=cpu->wz;goto step_next; - case 890: goto step_next; - // -- overlapped - case 891: goto fetch_next; - - // F5: PUSH AF (M:4 T:11) - // -- generic - case 892: goto step_next; - // -- mwrite - case 893: goto step_next; - case 894: _wait();_mwrite(--cpu->sp,cpu->a);goto step_next; - case 895: goto step_next; - // -- mwrite - case 896: goto step_next; - case 897: _wait();_mwrite(--cpu->sp,cpu->f);goto step_next; - case 898: goto step_next; - // -- overlapped - case 899: goto fetch_next; - - // F6: OR n (M:2 T:7) - // -- mread - case 900: goto step_next; - case 901: _wait();_mread(cpu->pc++);goto step_next; - case 902: cpu->dlatch=_gd();goto step_next; - // -- overlapped - case 903: _z80_or8(cpu,cpu->dlatch);goto fetch_next; - - // F7: RST 30h (M:4 T:11) - // -- generic - case 904: goto step_next; - // -- mwrite - case 905: goto step_next; - case 906: _wait();_mwrite(--cpu->sp,cpu->pch);goto step_next; - case 907: goto step_next; - // -- mwrite - case 908: goto step_next; - case 909: _wait();_mwrite(--cpu->sp,cpu->pcl);cpu->wz=0x30;cpu->pc=cpu->wz;goto step_next; - case 910: goto step_next; - // -- overlapped - case 911: goto fetch_next; - - // F8: RET M (M:4 T:11) - // -- generic - case 912: if(!_cc_m){_skip(6);};goto step_next; - // -- mread - case 913: goto step_next; - case 914: _wait();_mread(cpu->sp++);goto step_next; - case 915: cpu->wzl=_gd();goto step_next; - // -- mread - case 916: goto step_next; - case 917: _wait();_mread(cpu->sp++);goto step_next; - case 918: cpu->wzh=_gd();cpu->pc=cpu->wz;goto step_next; - // -- overlapped - case 919: goto fetch_next; - - // F9: LD SP,HL (M:2 T:6) - // -- generic - case 920: cpu->sp=cpu->hlx[cpu->hlx_idx].hl;goto step_next; - case 921: goto step_next; - // -- overlapped - case 922: goto fetch_next; - - // FA: JP M,nn (M:3 T:10) - // -- mread - case 923: goto step_next; - case 924: _wait();_mread(cpu->pc++);goto step_next; - case 925: cpu->wzl=_gd();goto step_next; - // -- mread - case 926: goto step_next; - case 927: _wait();_mread(cpu->pc++);goto step_next; - case 928: cpu->wzh=_gd();if(_cc_m){cpu->pc=cpu->wz;};goto step_next; - // -- overlapped - case 929: goto fetch_next; - - // FB: EI (M:1 T:4) - // -- overlapped - case 930: cpu->iff1=cpu->iff2=false;pins=_z80_fetch(cpu,pins);cpu->iff1=cpu->iff2=true;goto step_next; - - // FC: CALL M,nn (M:6 T:17) - // -- mread - case 931: goto step_next; - case 932: _wait();_mread(cpu->pc++);goto step_next; - case 933: cpu->wzl=_gd();goto step_next; - // -- mread - case 934: goto step_next; - case 935: _wait();_mread(cpu->pc++);goto step_next; - case 936: cpu->wzh=_gd();if (!_cc_m){_skip(7);};goto step_next; - // -- generic - case 937: goto step_next; - // -- mwrite - case 938: goto step_next; - case 939: _wait();_mwrite(--cpu->sp,cpu->pch);goto step_next; - case 940: goto step_next; - // -- mwrite - case 941: goto step_next; - case 942: _wait();_mwrite(--cpu->sp,cpu->pcl);cpu->pc=cpu->wz;goto step_next; - case 943: goto step_next; - // -- overlapped - case 944: goto fetch_next; - - // FD: FD prefix (M:1 T:4) - // -- overlapped - case 945: _fetch_fd();goto step_next; - - // FE: CP n (M:2 T:7) - // -- mread - case 946: goto step_next; - case 947: _wait();_mread(cpu->pc++);goto step_next; - case 948: cpu->dlatch=_gd();goto step_next; - // -- overlapped - case 949: _z80_cp8(cpu,cpu->dlatch);goto fetch_next; - - // FF: RST 38h (M:4 T:11) - // -- generic - case 950: goto step_next; - // -- mwrite - case 951: goto step_next; - case 952: _wait();_mwrite(--cpu->sp,cpu->pch);goto step_next; - case 953: goto step_next; - // -- mwrite - case 954: goto step_next; - case 955: _wait();_mwrite(--cpu->sp,cpu->pcl);cpu->wz=0x38;cpu->pc=cpu->wz;goto step_next; - case 956: goto step_next; - // -- overlapped - case 957: goto fetch_next; - - // ED 00: ED NOP (M:1 T:4) - // -- overlapped - case 958: goto fetch_next; - - // ED 40: IN B,(C) (M:2 T:8) - // -- ioread - case 959: goto step_next; - case 960: goto step_next; - case 961: _wait();_ioread(cpu->bc);goto step_next; - case 962: cpu->dlatch=_gd();cpu->wz=cpu->bc+1;goto step_next; - // -- overlapped - case 963: cpu->b=_z80_in(cpu,cpu->dlatch);goto fetch_next; - - // ED 41: OUT (C),B (M:2 T:8) - // -- iowrite - case 964: goto step_next; - case 965: _iowrite(cpu->bc,cpu->b);goto step_next; - case 966: _wait();cpu->wz=cpu->bc+1;goto step_next; - case 967: goto step_next; - // -- overlapped - case 968: goto fetch_next; - - // ED 42: SBC HL,BC (M:2 T:11) - // -- generic - case 969: _z80_sbc16(cpu,cpu->bc);goto step_next; - case 970: goto step_next; - case 971: goto step_next; - case 972: goto step_next; - case 973: goto step_next; - case 974: goto step_next; - case 975: goto step_next; - // -- overlapped - case 976: goto fetch_next; - - // ED 43: LD (nn),BC (M:5 T:16) - // -- mread - case 977: goto step_next; - case 978: _wait();_mread(cpu->pc++);goto step_next; - case 979: cpu->wzl=_gd();goto step_next; - // -- mread - case 980: goto step_next; - case 981: _wait();_mread(cpu->pc++);goto step_next; - case 982: cpu->wzh=_gd();goto step_next; - // -- mwrite - case 983: goto step_next; - case 984: _wait();_mwrite(cpu->wz++,cpu->c);goto step_next; - case 985: goto step_next; - // -- mwrite - case 986: goto step_next; - case 987: _wait();_mwrite(cpu->wz,cpu->b);goto step_next; - case 988: goto step_next; - // -- overlapped - case 989: goto fetch_next; - - // ED 44: NEG (M:1 T:4) - // -- overlapped - case 990: _z80_neg8(cpu);goto fetch_next; - - // ED 45: RETN (M:3 T:10) - // -- mread - case 991: goto step_next; - case 992: _wait();_mread(cpu->sp++);goto step_next; - case 993: cpu->wzl=_gd();goto step_next; - // -- mread - case 994: goto step_next; - case 995: _wait();_mread(cpu->sp++);goto step_next; - case 996: cpu->wzh=_gd();cpu->pc=cpu->wz;goto step_next; - // -- overlapped - case 997: pins=_z80_fetch(cpu,pins);cpu->iff1=cpu->iff2;goto step_next; - - // ED 46: IM 0 (M:1 T:4) - // -- overlapped - case 998: cpu->im=0;goto fetch_next; - - // ED 47: LD I,A (M:2 T:5) - // -- generic - case 999: goto step_next; - // -- overlapped - case 1000: cpu->i=cpu->a;goto fetch_next; - - // ED 48: IN C,(C) (M:2 T:8) - // -- ioread - case 1001: goto step_next; - case 1002: goto step_next; - case 1003: _wait();_ioread(cpu->bc);goto step_next; - case 1004: cpu->dlatch=_gd();cpu->wz=cpu->bc+1;goto step_next; - // -- overlapped - case 1005: cpu->c=_z80_in(cpu,cpu->dlatch);goto fetch_next; - - // ED 49: OUT (C),C (M:2 T:8) - // -- iowrite - case 1006: goto step_next; - case 1007: _iowrite(cpu->bc,cpu->c);goto step_next; - case 1008: _wait();cpu->wz=cpu->bc+1;goto step_next; - case 1009: goto step_next; - // -- overlapped - case 1010: goto fetch_next; - - // ED 4A: ADC HL,BC (M:2 T:11) - // -- generic - case 1011: _z80_adc16(cpu,cpu->bc);goto step_next; - case 1012: goto step_next; - case 1013: goto step_next; - case 1014: goto step_next; - case 1015: goto step_next; - case 1016: goto step_next; - case 1017: goto step_next; - // -- overlapped - case 1018: goto fetch_next; - - // ED 4B: LD BC,(nn) (M:5 T:16) - // -- mread - case 1019: goto step_next; - case 1020: _wait();_mread(cpu->pc++);goto step_next; - case 1021: cpu->wzl=_gd();goto step_next; - // -- mread - case 1022: goto step_next; - case 1023: _wait();_mread(cpu->pc++);goto step_next; - case 1024: cpu->wzh=_gd();goto step_next; - // -- mread - case 1025: goto step_next; - case 1026: _wait();_mread(cpu->wz++);goto step_next; - case 1027: cpu->c=_gd();goto step_next; - // -- mread - case 1028: goto step_next; - case 1029: _wait();_mread(cpu->wz);goto step_next; - case 1030: cpu->b=_gd();goto step_next; - // -- overlapped - case 1031: goto fetch_next; - - // ED 4D: RETI (M:3 T:10) - // -- mread - case 1032: goto step_next; - case 1033: _wait();_mread(cpu->sp++);goto step_next; - case 1034: cpu->wzl=_gd();pins|=Z80_RETI;goto step_next; - // -- mread - case 1035: goto step_next; - case 1036: _wait();_mread(cpu->sp++);goto step_next; - case 1037: cpu->wzh=_gd();cpu->pc=cpu->wz;goto step_next; - // -- overlapped - case 1038: pins=_z80_fetch(cpu,pins);cpu->iff1=cpu->iff2;goto step_next; - - // ED 4E: IM 0 (M:1 T:4) - // -- overlapped - case 1039: cpu->im=0;goto fetch_next; - - // ED 4F: LD R,A (M:2 T:5) - // -- generic - case 1040: goto step_next; - // -- overlapped - case 1041: cpu->r=cpu->a;goto fetch_next; - - // ED 50: IN D,(C) (M:2 T:8) - // -- ioread - case 1042: goto step_next; - case 1043: goto step_next; - case 1044: _wait();_ioread(cpu->bc);goto step_next; - case 1045: cpu->dlatch=_gd();cpu->wz=cpu->bc+1;goto step_next; - // -- overlapped - case 1046: cpu->d=_z80_in(cpu,cpu->dlatch);goto fetch_next; - - // ED 51: OUT (C),D (M:2 T:8) - // -- iowrite - case 1047: goto step_next; - case 1048: _iowrite(cpu->bc,cpu->d);goto step_next; - case 1049: _wait();cpu->wz=cpu->bc+1;goto step_next; - case 1050: goto step_next; - // -- overlapped - case 1051: goto fetch_next; - - // ED 52: SBC HL,DE (M:2 T:11) - // -- generic - case 1052: _z80_sbc16(cpu,cpu->de);goto step_next; - case 1053: goto step_next; - case 1054: goto step_next; - case 1055: goto step_next; - case 1056: goto step_next; - case 1057: goto step_next; - case 1058: goto step_next; - // -- overlapped - case 1059: goto fetch_next; - - // ED 53: LD (nn),DE (M:5 T:16) - // -- mread - case 1060: goto step_next; - case 1061: _wait();_mread(cpu->pc++);goto step_next; - case 1062: cpu->wzl=_gd();goto step_next; - // -- mread - case 1063: goto step_next; - case 1064: _wait();_mread(cpu->pc++);goto step_next; - case 1065: cpu->wzh=_gd();goto step_next; - // -- mwrite - case 1066: goto step_next; - case 1067: _wait();_mwrite(cpu->wz++,cpu->e);goto step_next; - case 1068: goto step_next; - // -- mwrite - case 1069: goto step_next; - case 1070: _wait();_mwrite(cpu->wz,cpu->d);goto step_next; - case 1071: goto step_next; - // -- overlapped - case 1072: goto fetch_next; - - // ED 56: IM 1 (M:1 T:4) - // -- overlapped - case 1073: cpu->im=1;goto fetch_next; - - // ED 57: LD A,I (M:2 T:5) - // -- generic - case 1074: goto step_next; - // -- overlapped - case 1075: cpu->a=cpu->i;cpu->f=_z80_sziff2_flags(cpu, cpu->i);goto fetch_next; - - // ED 58: IN E,(C) (M:2 T:8) - // -- ioread - case 1076: goto step_next; - case 1077: goto step_next; - case 1078: _wait();_ioread(cpu->bc);goto step_next; - case 1079: cpu->dlatch=_gd();cpu->wz=cpu->bc+1;goto step_next; - // -- overlapped - case 1080: cpu->e=_z80_in(cpu,cpu->dlatch);goto fetch_next; - - // ED 59: OUT (C),E (M:2 T:8) - // -- iowrite - case 1081: goto step_next; - case 1082: _iowrite(cpu->bc,cpu->e);goto step_next; - case 1083: _wait();cpu->wz=cpu->bc+1;goto step_next; - case 1084: goto step_next; - // -- overlapped - case 1085: goto fetch_next; - - // ED 5A: ADC HL,DE (M:2 T:11) - // -- generic - case 1086: _z80_adc16(cpu,cpu->de);goto step_next; - case 1087: goto step_next; - case 1088: goto step_next; - case 1089: goto step_next; - case 1090: goto step_next; - case 1091: goto step_next; - case 1092: goto step_next; - // -- overlapped - case 1093: goto fetch_next; - - // ED 5B: LD DE,(nn) (M:5 T:16) - // -- mread - case 1094: goto step_next; - case 1095: _wait();_mread(cpu->pc++);goto step_next; - case 1096: cpu->wzl=_gd();goto step_next; - // -- mread - case 1097: goto step_next; - case 1098: _wait();_mread(cpu->pc++);goto step_next; - case 1099: cpu->wzh=_gd();goto step_next; - // -- mread - case 1100: goto step_next; - case 1101: _wait();_mread(cpu->wz++);goto step_next; - case 1102: cpu->e=_gd();goto step_next; - // -- mread - case 1103: goto step_next; - case 1104: _wait();_mread(cpu->wz);goto step_next; - case 1105: cpu->d=_gd();goto step_next; - // -- overlapped - case 1106: goto fetch_next; - - // ED 5E: IM 2 (M:1 T:4) - // -- overlapped - case 1107: cpu->im=2;goto fetch_next; - - // ED 5F: LD A,R (M:2 T:5) - // -- generic - case 1108: goto step_next; - // -- overlapped - case 1109: cpu->a=cpu->r;cpu->f=_z80_sziff2_flags(cpu, cpu->r);goto fetch_next; - - // ED 60: IN H,(C) (M:2 T:8) - // -- ioread - case 1110: goto step_next; - case 1111: goto step_next; - case 1112: _wait();_ioread(cpu->bc);goto step_next; - case 1113: cpu->dlatch=_gd();cpu->wz=cpu->bc+1;goto step_next; - // -- overlapped - case 1114: cpu->h=_z80_in(cpu,cpu->dlatch);goto fetch_next; - - // ED 61: OUT (C),H (M:2 T:8) - // -- iowrite - case 1115: goto step_next; - case 1116: _iowrite(cpu->bc,cpu->h);goto step_next; - case 1117: _wait();cpu->wz=cpu->bc+1;goto step_next; - case 1118: goto step_next; - // -- overlapped - case 1119: goto fetch_next; - - // ED 62: SBC HL,HL (M:2 T:11) - // -- generic - case 1120: _z80_sbc16(cpu,cpu->hl);goto step_next; - case 1121: goto step_next; - case 1122: goto step_next; - case 1123: goto step_next; - case 1124: goto step_next; - case 1125: goto step_next; - case 1126: goto step_next; - // -- overlapped - case 1127: goto fetch_next; - - // ED 63: LD (nn),HL (M:5 T:16) - // -- mread - case 1128: goto step_next; - case 1129: _wait();_mread(cpu->pc++);goto step_next; - case 1130: cpu->wzl=_gd();goto step_next; - // -- mread - case 1131: goto step_next; - case 1132: _wait();_mread(cpu->pc++);goto step_next; - case 1133: cpu->wzh=_gd();goto step_next; - // -- mwrite - case 1134: goto step_next; - case 1135: _wait();_mwrite(cpu->wz++,cpu->l);goto step_next; - case 1136: goto step_next; - // -- mwrite - case 1137: goto step_next; - case 1138: _wait();_mwrite(cpu->wz,cpu->h);goto step_next; - case 1139: goto step_next; - // -- overlapped - case 1140: goto fetch_next; - - // ED 66: IM 0 (M:1 T:4) - // -- overlapped - case 1141: cpu->im=0;goto fetch_next; - - // ED 67: RRD (M:4 T:14) - // -- mread - case 1142: goto step_next; - case 1143: _wait();_mread(cpu->hl);goto step_next; - case 1144: cpu->dlatch=_gd();goto step_next; - // -- generic - case 1145: cpu->dlatch=_z80_rrd(cpu,cpu->dlatch);goto step_next; - case 1146: goto step_next; - case 1147: goto step_next; - case 1148: goto step_next; - // -- mwrite - case 1149: goto step_next; - case 1150: _wait();_mwrite(cpu->hl,cpu->dlatch);cpu->wz=cpu->hl+1;goto step_next; - case 1151: goto step_next; - // -- overlapped - case 1152: goto fetch_next; - - // ED 68: IN L,(C) (M:2 T:8) - // -- ioread - case 1153: goto step_next; - case 1154: goto step_next; - case 1155: _wait();_ioread(cpu->bc);goto step_next; - case 1156: cpu->dlatch=_gd();cpu->wz=cpu->bc+1;goto step_next; - // -- overlapped - case 1157: cpu->l=_z80_in(cpu,cpu->dlatch);goto fetch_next; - - // ED 69: OUT (C),L (M:2 T:8) - // -- iowrite - case 1158: goto step_next; - case 1159: _iowrite(cpu->bc,cpu->l);goto step_next; - case 1160: _wait();cpu->wz=cpu->bc+1;goto step_next; - case 1161: goto step_next; - // -- overlapped - case 1162: goto fetch_next; - - // ED 6A: ADC HL,HL (M:2 T:11) - // -- generic - case 1163: _z80_adc16(cpu,cpu->hl);goto step_next; - case 1164: goto step_next; - case 1165: goto step_next; - case 1166: goto step_next; - case 1167: goto step_next; - case 1168: goto step_next; - case 1169: goto step_next; - // -- overlapped - case 1170: goto fetch_next; - - // ED 6B: LD HL,(nn) (M:5 T:16) - // -- mread - case 1171: goto step_next; - case 1172: _wait();_mread(cpu->pc++);goto step_next; - case 1173: cpu->wzl=_gd();goto step_next; - // -- mread - case 1174: goto step_next; - case 1175: _wait();_mread(cpu->pc++);goto step_next; - case 1176: cpu->wzh=_gd();goto step_next; - // -- mread - case 1177: goto step_next; - case 1178: _wait();_mread(cpu->wz++);goto step_next; - case 1179: cpu->l=_gd();goto step_next; - // -- mread - case 1180: goto step_next; - case 1181: _wait();_mread(cpu->wz);goto step_next; - case 1182: cpu->h=_gd();goto step_next; - // -- overlapped - case 1183: goto fetch_next; - - // ED 6E: IM 0 (M:1 T:4) - // -- overlapped - case 1184: cpu->im=0;goto fetch_next; - - // ED 6F: RLD (M:4 T:14) - // -- mread - case 1185: goto step_next; - case 1186: _wait();_mread(cpu->hl);goto step_next; - case 1187: cpu->dlatch=_gd();goto step_next; - // -- generic - case 1188: cpu->dlatch=_z80_rld(cpu,cpu->dlatch);goto step_next; - case 1189: goto step_next; - case 1190: goto step_next; - case 1191: goto step_next; - // -- mwrite - case 1192: goto step_next; - case 1193: _wait();_mwrite(cpu->hl,cpu->dlatch);cpu->wz=cpu->hl+1;goto step_next; - case 1194: goto step_next; - // -- overlapped - case 1195: goto fetch_next; - - // ED 70: IN (C) (M:2 T:8) - // -- ioread - case 1196: goto step_next; - case 1197: goto step_next; - case 1198: _wait();_ioread(cpu->bc);goto step_next; - case 1199: cpu->dlatch=_gd();cpu->wz=cpu->bc+1;goto step_next; - // -- overlapped - case 1200: _z80_in(cpu,cpu->dlatch);goto fetch_next; - - // ED 71: OUT (C),0 (M:2 T:8) - // -- iowrite - case 1201: goto step_next; - case 1202: _iowrite(cpu->bc,0);goto step_next; - case 1203: _wait();cpu->wz=cpu->bc+1;goto step_next; - case 1204: goto step_next; - // -- overlapped - case 1205: goto fetch_next; - - // ED 72: SBC HL,SP (M:2 T:11) - // -- generic - case 1206: _z80_sbc16(cpu,cpu->sp);goto step_next; - case 1207: goto step_next; - case 1208: goto step_next; - case 1209: goto step_next; - case 1210: goto step_next; - case 1211: goto step_next; - case 1212: goto step_next; - // -- overlapped - case 1213: goto fetch_next; - - // ED 73: LD (nn),SP (M:5 T:16) - // -- mread - case 1214: goto step_next; - case 1215: _wait();_mread(cpu->pc++);goto step_next; - case 1216: cpu->wzl=_gd();goto step_next; - // -- mread - case 1217: goto step_next; - case 1218: _wait();_mread(cpu->pc++);goto step_next; - case 1219: cpu->wzh=_gd();goto step_next; - // -- mwrite - case 1220: goto step_next; - case 1221: _wait();_mwrite(cpu->wz++,cpu->spl);goto step_next; - case 1222: goto step_next; - // -- mwrite - case 1223: goto step_next; - case 1224: _wait();_mwrite(cpu->wz,cpu->sph);goto step_next; - case 1225: goto step_next; - // -- overlapped - case 1226: goto fetch_next; - - // ED 76: IM 1 (M:1 T:4) - // -- overlapped - case 1227: cpu->im=1;goto fetch_next; - - // ED 78: IN A,(C) (M:2 T:8) - // -- ioread - case 1228: goto step_next; - case 1229: goto step_next; - case 1230: _wait();_ioread(cpu->bc);goto step_next; - case 1231: cpu->dlatch=_gd();cpu->wz=cpu->bc+1;goto step_next; - // -- overlapped - case 1232: cpu->a=_z80_in(cpu,cpu->dlatch);goto fetch_next; - - // ED 79: OUT (C),A (M:2 T:8) - // -- iowrite - case 1233: goto step_next; - case 1234: _iowrite(cpu->bc,cpu->a);goto step_next; - case 1235: _wait();cpu->wz=cpu->bc+1;goto step_next; - case 1236: goto step_next; - // -- overlapped - case 1237: goto fetch_next; - - // ED 7A: ADC HL,SP (M:2 T:11) - // -- generic - case 1238: _z80_adc16(cpu,cpu->sp);goto step_next; - case 1239: goto step_next; - case 1240: goto step_next; - case 1241: goto step_next; - case 1242: goto step_next; - case 1243: goto step_next; - case 1244: goto step_next; - // -- overlapped - case 1245: goto fetch_next; - - // ED 7B: LD SP,(nn) (M:5 T:16) - // -- mread - case 1246: goto step_next; - case 1247: _wait();_mread(cpu->pc++);goto step_next; - case 1248: cpu->wzl=_gd();goto step_next; - // -- mread - case 1249: goto step_next; - case 1250: _wait();_mread(cpu->pc++);goto step_next; - case 1251: cpu->wzh=_gd();goto step_next; - // -- mread - case 1252: goto step_next; - case 1253: _wait();_mread(cpu->wz++);goto step_next; - case 1254: cpu->spl=_gd();goto step_next; - // -- mread - case 1255: goto step_next; - case 1256: _wait();_mread(cpu->wz);goto step_next; - case 1257: cpu->sph=_gd();goto step_next; - // -- overlapped - case 1258: goto fetch_next; - - // ED 7E: IM 2 (M:1 T:4) - // -- overlapped - case 1259: cpu->im=2;goto fetch_next; - - // ED A0: LDI (M:4 T:12) - // -- mread - case 1260: goto step_next; - case 1261: _wait();_mread(cpu->hl++);goto step_next; - case 1262: cpu->dlatch=_gd();goto step_next; - // -- mwrite - case 1263: goto step_next; - case 1264: _wait();_mwrite(cpu->de++,cpu->dlatch);goto step_next; - case 1265: goto step_next; - // -- generic - case 1266: _z80_ldi_ldd(cpu,cpu->dlatch);goto step_next; - case 1267: goto step_next; - // -- overlapped - case 1268: goto fetch_next; - - // ED A1: CPI (M:3 T:12) - // -- mread - case 1269: goto step_next; - case 1270: _wait();_mread(cpu->hl++);goto step_next; - case 1271: cpu->dlatch=_gd();goto step_next; - // -- generic - case 1272: cpu->wz++;_z80_cpi_cpd(cpu,cpu->dlatch);goto step_next; - case 1273: goto step_next; - case 1274: goto step_next; - case 1275: goto step_next; - case 1276: goto step_next; - // -- overlapped - case 1277: goto fetch_next; - - // ED A2: INI (M:4 T:12) - // -- generic - case 1278: goto step_next; - // -- ioread - case 1279: goto step_next; - case 1280: goto step_next; - case 1281: _wait();_ioread(cpu->bc);goto step_next; - case 1282: cpu->dlatch=_gd();cpu->wz=cpu->bc+1;cpu->b--;;goto step_next; - // -- mwrite - case 1283: goto step_next; - case 1284: _wait();_mwrite(cpu->hl++,cpu->dlatch);_z80_ini_ind(cpu,cpu->dlatch,cpu->c+1);goto step_next; - case 1285: goto step_next; - // -- overlapped - case 1286: goto fetch_next; - - // ED A3: OUTI (M:4 T:12) - // -- generic - case 1287: goto step_next; - // -- mread - case 1288: goto step_next; - case 1289: _wait();_mread(cpu->hl++);goto step_next; - case 1290: cpu->dlatch=_gd();cpu->b--;goto step_next; - // -- iowrite - case 1291: goto step_next; - case 1292: _iowrite(cpu->bc,cpu->dlatch);goto step_next; - case 1293: _wait();cpu->wz=cpu->bc+1;_z80_outi_outd(cpu,cpu->dlatch);goto step_next; - case 1294: goto step_next; - // -- overlapped - case 1295: goto fetch_next; - - // ED A8: LDD (M:4 T:12) - // -- mread - case 1296: goto step_next; - case 1297: _wait();_mread(cpu->hl--);goto step_next; - case 1298: cpu->dlatch=_gd();goto step_next; - // -- mwrite - case 1299: goto step_next; - case 1300: _wait();_mwrite(cpu->de--,cpu->dlatch);goto step_next; - case 1301: goto step_next; - // -- generic - case 1302: _z80_ldi_ldd(cpu,cpu->dlatch);goto step_next; - case 1303: goto step_next; - // -- overlapped - case 1304: goto fetch_next; - - // ED A9: CPD (M:3 T:12) - // -- mread - case 1305: goto step_next; - case 1306: _wait();_mread(cpu->hl--);goto step_next; - case 1307: cpu->dlatch=_gd();goto step_next; - // -- generic - case 1308: cpu->wz--;_z80_cpi_cpd(cpu,cpu->dlatch);goto step_next; - case 1309: goto step_next; - case 1310: goto step_next; - case 1311: goto step_next; - case 1312: goto step_next; - // -- overlapped - case 1313: goto fetch_next; - - // ED AA: IND (M:4 T:12) - // -- generic - case 1314: goto step_next; - // -- ioread - case 1315: goto step_next; - case 1316: goto step_next; - case 1317: _wait();_ioread(cpu->bc);goto step_next; - case 1318: cpu->dlatch=_gd();cpu->wz=cpu->bc-1;cpu->b--;;goto step_next; - // -- mwrite - case 1319: goto step_next; - case 1320: _wait();_mwrite(cpu->hl--,cpu->dlatch);_z80_ini_ind(cpu,cpu->dlatch,cpu->c-1);goto step_next; - case 1321: goto step_next; - // -- overlapped - case 1322: goto fetch_next; - - // ED AB: OUTD (M:4 T:12) - // -- generic - case 1323: goto step_next; - // -- mread - case 1324: goto step_next; - case 1325: _wait();_mread(cpu->hl--);goto step_next; - case 1326: cpu->dlatch=_gd();cpu->b--;goto step_next; - // -- iowrite - case 1327: goto step_next; - case 1328: _iowrite(cpu->bc,cpu->dlatch);goto step_next; - case 1329: _wait();cpu->wz=cpu->bc-1;_z80_outi_outd(cpu,cpu->dlatch);goto step_next; - case 1330: goto step_next; - // -- overlapped - case 1331: goto fetch_next; - - // ED B0: LDIR (M:5 T:17) - // -- mread - case 1332: goto step_next; - case 1333: _wait();_mread(cpu->hl++);goto step_next; - case 1334: cpu->dlatch=_gd();goto step_next; - // -- mwrite - case 1335: goto step_next; - case 1336: _wait();_mwrite(cpu->de++,cpu->dlatch);goto step_next; - case 1337: goto step_next; - // -- generic - case 1338: if(!_z80_ldi_ldd(cpu,cpu->dlatch)){_skip(5);};goto step_next; - case 1339: goto step_next; - // -- generic - case 1340: cpu->wz=--cpu->pc;--cpu->pc;;goto step_next; - case 1341: goto step_next; - case 1342: goto step_next; - case 1343: goto step_next; - case 1344: goto step_next; - // -- overlapped - case 1345: goto fetch_next; - - // ED B1: CPIR (M:4 T:17) - // -- mread - case 1346: goto step_next; - case 1347: _wait();_mread(cpu->hl++);goto step_next; - case 1348: cpu->dlatch=_gd();goto step_next; - // -- generic - case 1349: cpu->wz++;if(!_z80_cpi_cpd(cpu,cpu->dlatch)){_skip(5);};goto step_next; - case 1350: goto step_next; - case 1351: goto step_next; - case 1352: goto step_next; - case 1353: goto step_next; - // -- generic - case 1354: cpu->wz=--cpu->pc;--cpu->pc;goto step_next; - case 1355: goto step_next; - case 1356: goto step_next; - case 1357: goto step_next; - case 1358: goto step_next; - // -- overlapped - case 1359: goto fetch_next; - - // ED B2: INIR (M:5 T:17) - // -- generic - case 1360: goto step_next; - // -- ioread - case 1361: goto step_next; - case 1362: goto step_next; - case 1363: _wait();_ioread(cpu->bc);goto step_next; - case 1364: cpu->dlatch=_gd();cpu->wz=cpu->bc+1;cpu->b--;;goto step_next; - // -- mwrite - case 1365: goto step_next; - case 1366: _wait();_mwrite(cpu->hl++,cpu->dlatch);if (!_z80_ini_ind(cpu,cpu->dlatch,cpu->c+1)){_skip(5);};goto step_next; - case 1367: goto step_next; - // -- generic - case 1368: cpu->wz=--cpu->pc;--cpu->pc;goto step_next; - case 1369: goto step_next; - case 1370: goto step_next; - case 1371: goto step_next; - case 1372: goto step_next; - // -- overlapped - case 1373: goto fetch_next; - - // ED B3: OTIR (M:5 T:17) - // -- generic - case 1374: goto step_next; - // -- mread - case 1375: goto step_next; - case 1376: _wait();_mread(cpu->hl++);goto step_next; - case 1377: cpu->dlatch=_gd();cpu->b--;goto step_next; - // -- iowrite - case 1378: goto step_next; - case 1379: _iowrite(cpu->bc,cpu->dlatch);goto step_next; - case 1380: _wait();cpu->wz=cpu->bc+1;if(!_z80_outi_outd(cpu,cpu->dlatch)){_skip(5);};goto step_next; - case 1381: goto step_next; - // -- generic - case 1382: cpu->wz=--cpu->pc;--cpu->pc;goto step_next; - case 1383: goto step_next; - case 1384: goto step_next; - case 1385: goto step_next; - case 1386: goto step_next; - // -- overlapped - case 1387: goto fetch_next; - - // ED B8: LDDR (M:5 T:17) - // -- mread - case 1388: goto step_next; - case 1389: _wait();_mread(cpu->hl--);goto step_next; - case 1390: cpu->dlatch=_gd();goto step_next; - // -- mwrite - case 1391: goto step_next; - case 1392: _wait();_mwrite(cpu->de--,cpu->dlatch);goto step_next; - case 1393: goto step_next; - // -- generic - case 1394: if(!_z80_ldi_ldd(cpu,cpu->dlatch)){_skip(5);};goto step_next; - case 1395: goto step_next; - // -- generic - case 1396: cpu->wz=--cpu->pc;--cpu->pc;;goto step_next; - case 1397: goto step_next; - case 1398: goto step_next; - case 1399: goto step_next; - case 1400: goto step_next; - // -- overlapped - case 1401: goto fetch_next; - - // ED B9: CPDR (M:4 T:17) - // -- mread - case 1402: goto step_next; - case 1403: _wait();_mread(cpu->hl--);goto step_next; - case 1404: cpu->dlatch=_gd();goto step_next; - // -- generic - case 1405: cpu->wz--;if(!_z80_cpi_cpd(cpu,cpu->dlatch)){_skip(5);};goto step_next; - case 1406: goto step_next; - case 1407: goto step_next; - case 1408: goto step_next; - case 1409: goto step_next; - // -- generic - case 1410: cpu->wz=--cpu->pc;--cpu->pc;goto step_next; - case 1411: goto step_next; - case 1412: goto step_next; - case 1413: goto step_next; - case 1414: goto step_next; - // -- overlapped - case 1415: goto fetch_next; - - // ED BA: INDR (M:5 T:17) - // -- generic - case 1416: goto step_next; - // -- ioread - case 1417: goto step_next; - case 1418: goto step_next; - case 1419: _wait();_ioread(cpu->bc);goto step_next; - case 1420: cpu->dlatch=_gd();cpu->wz=cpu->bc-1;cpu->b--;;goto step_next; - // -- mwrite - case 1421: goto step_next; - case 1422: _wait();_mwrite(cpu->hl--,cpu->dlatch);if (!_z80_ini_ind(cpu,cpu->dlatch,cpu->c-1)){_skip(5);};goto step_next; - case 1423: goto step_next; - // -- generic - case 1424: cpu->wz=--cpu->pc;--cpu->pc;goto step_next; - case 1425: goto step_next; - case 1426: goto step_next; - case 1427: goto step_next; - case 1428: goto step_next; - // -- overlapped - case 1429: goto fetch_next; - - // ED BB: OTDR (M:5 T:17) - // -- generic - case 1430: goto step_next; - // -- mread - case 1431: goto step_next; - case 1432: _wait();_mread(cpu->hl--);goto step_next; - case 1433: cpu->dlatch=_gd();cpu->b--;goto step_next; - // -- iowrite - case 1434: goto step_next; - case 1435: _iowrite(cpu->bc,cpu->dlatch);goto step_next; - case 1436: _wait();cpu->wz=cpu->bc-1;if(!_z80_outi_outd(cpu,cpu->dlatch)){_skip(5);};goto step_next; - case 1437: goto step_next; - // -- generic - case 1438: cpu->wz=--cpu->pc;--cpu->pc;goto step_next; - case 1439: goto step_next; - case 1440: goto step_next; - case 1441: goto step_next; - case 1442: goto step_next; - // -- overlapped - case 1443: goto fetch_next; - - // CB 00: cb (M:1 T:4) - // -- overlapped - case 1444: {uint8_t z=cpu->opcode&7;_z80_cb_action(cpu,z,z);};goto fetch_next; - - // CB 00: cbhl (M:3 T:11) - // -- mread - case 1445: goto step_next; - case 1446: _wait();_mread(cpu->hl);goto step_next; - case 1447: cpu->dlatch=_gd();if(!_z80_cb_action(cpu,6,6)){_skip(3);};goto step_next; - case 1448: goto step_next; - // -- mwrite - case 1449: goto step_next; - case 1450: _wait();_mwrite(cpu->hl,cpu->dlatch);goto step_next; - case 1451: goto step_next; - // -- overlapped - case 1452: goto fetch_next; - - // CB 00: ddfdcb (M:6 T:18) - // -- generic - case 1453: _wait();_mread(cpu->pc++);goto step_next; - // -- generic - case 1454: _z80_ddfdcb_addr(cpu,pins);goto step_next; - // -- mread - case 1455: goto step_next; - case 1456: _wait();_mread(cpu->pc++);goto step_next; - case 1457: cpu->opcode=_gd();goto step_next; - case 1458: goto step_next; - case 1459: goto step_next; - // -- mread - case 1460: goto step_next; - case 1461: _wait();_mread(cpu->addr);goto step_next; - case 1462: cpu->dlatch=_gd();if(!_z80_cb_action(cpu,6,cpu->opcode&7)){_skip(3);};goto step_next; - case 1463: goto step_next; - // -- mwrite - case 1464: goto step_next; - case 1465: _wait();_mwrite(cpu->addr,cpu->dlatch);goto step_next; - case 1466: goto step_next; - // -- overlapped - case 1467: goto fetch_next; - - // 00: int_im0 (M:6 T:9) - // -- generic - case 1468: cpu->iff1=cpu->iff2=false;goto step_next; - // -- generic - case 1469: pins|=(Z80_M1|Z80_IORQ);goto step_next; - // -- generic - case 1470: _wait();cpu->opcode=_z80_get_db(pins);goto step_next; - // -- generic - case 1471: pins=_z80_refresh(cpu,pins);goto step_next; - // -- generic - case 1472: cpu->step=_z80_optable[cpu->opcode]; cpu->addr=cpu->hl;goto step_next; - // -- overlapped - case 1473: goto fetch_next; - - // 00: int_im1 (M:7 T:16) - // -- generic - case 1474: cpu->iff1=cpu->iff2=false;goto step_next; - // -- generic - case 1475: pins|=(Z80_M1|Z80_IORQ);goto step_next; - // -- generic - case 1476: _wait();goto step_next; - // -- generic - case 1477: pins=_z80_refresh(cpu,pins);goto step_next; - case 1478: goto step_next; - case 1479: goto step_next; - // -- mwrite - case 1480: goto step_next; - case 1481: _wait();_mwrite(--cpu->sp,cpu->pch);goto step_next; - case 1482: goto step_next; - // -- mwrite - case 1483: goto step_next; - case 1484: _wait();_mwrite(--cpu->sp,cpu->pcl);cpu->wz=cpu->pc=0x0038;goto step_next; - case 1485: goto step_next; - // -- overlapped - case 1486: goto fetch_next; - - // 00: int_im2 (M:9 T:22) - // -- generic - case 1487: cpu->iff1=cpu->iff2=false;goto step_next; - // -- generic - case 1488: pins|=(Z80_M1|Z80_IORQ);goto step_next; - // -- generic - case 1489: _wait();cpu->dlatch=_z80_get_db(pins);goto step_next; - // -- generic - case 1490: pins=_z80_refresh(cpu,pins);goto step_next; - case 1491: goto step_next; - case 1492: goto step_next; - // -- mwrite - case 1493: goto step_next; - case 1494: _wait();_mwrite(--cpu->sp,cpu->pch);goto step_next; - case 1495: goto step_next; - // -- mwrite - case 1496: goto step_next; - case 1497: _wait();_mwrite(--cpu->sp,cpu->pcl);cpu->wzl=cpu->dlatch;cpu->wzh=cpu->i;goto step_next; - case 1498: goto step_next; - // -- mread - case 1499: goto step_next; - case 1500: _wait();_mread(cpu->wz++);goto step_next; - case 1501: cpu->dlatch=_gd();goto step_next; - // -- mread - case 1502: goto step_next; - case 1503: _wait();_mread(cpu->wz);goto step_next; - case 1504: cpu->wzh=_gd();cpu->wzl=cpu->dlatch;cpu->pc=cpu->wz;goto step_next; - // -- overlapped - case 1505: goto fetch_next; - - // 00: nmi (M:5 T:14) - // -- generic - case 1506: _wait();cpu->iff1=false;goto step_next; - // -- generic - case 1507: pins=_z80_refresh(cpu,pins);goto step_next; - case 1508: goto step_next; - case 1509: goto step_next; - // -- mwrite - case 1510: goto step_next; - case 1511: _wait();_mwrite(--cpu->sp,cpu->pch);goto step_next; - case 1512: goto step_next; - // -- mwrite - case 1513: goto step_next; - case 1514: _wait();_mwrite(--cpu->sp,cpu->pcl);cpu->wz=cpu->pc=0x0066;goto step_next; - case 1515: goto step_next; - // -- overlapped - case 1516: goto fetch_next; - + case Z80_ED_M1_T2: _wait(); cpu->opcode = _gd(); _goto(Z80_ED_M1_T3); + case Z80_ED_M1_T3: pins = _z80_refresh(cpu, pins); _goto(Z80_ED_M1_T4); + case Z80_ED_M1_T4: _goto(cpu->opcode + 256); + //=== shared fetch machine cycle for non-DD/FD-prefixed ops + case Z80_M1_T2: _wait(); cpu->opcode = _gd(); _goto(Z80_M1_T3); + case Z80_M1_T3: pins = _z80_refresh(cpu, pins); _goto(Z80_M1_T4); + case Z80_M1_T4: cpu->addr = cpu->hl; _goto(cpu->opcode); default: _Z80_UNREACHABLE; } -fetch_next: pins = _z80_fetch(cpu, pins); -step_next: cpu->step += 1; -track_int_bits: { - // track NMI 0 => 1 edge and current INT pin state, this will track the - // relevant interrupt status up to the last instruction cycle and will - // be checked in the first M1 cycle (during _fetch) +fetch_next: + pins = _z80_fetch(cpu, pins); +step_to: { + // track NMI 0 => 1 edge and current INT pin state, this will track the + // relevant interrupt status up to the last instruction cycle and will + // be checked in the first M1 cycle (during _fetch) const uint64_t rising_nmi = (pins ^ cpu->pins) & pins; // NMI 0 => 1 cpu->pins = pins; cpu->int_bits = ((cpu->int_bits | rising_nmi) & Z80_NMI) | (pins & Z80_INT); diff --git a/codegen/README.txt b/codegen/README.txt index e677b16e..53283832 100644 --- a/codegen/README.txt +++ b/codegen/README.txt @@ -1,14 +1,12 @@ This directory contains code-generation python scripts which will generate the z80.h and m6502.h headers. -First install pyyaml: +In a bash compatible shell run: -pip3 install pyyaml - -Then run: - -> python3 z80_gen.py -> python3 m6502_gen.py - -To generate the respective decoder source files in the '../chips' directory. +```sh +./z80_gen.sh +./m6502_gen.sh +``` +This will run Python3 inside a virtual environment and read/write the `chips/z80.h` and +`chips/m6502.h` headers. diff --git a/codegen/m6502.template.h b/codegen/m6502.template.h deleted file mode 100644 index aaee7ad2..00000000 --- a/codegen/m6502.template.h +++ /dev/null @@ -1,793 +0,0 @@ -#pragma once -/*# - # m6502.h - - MOS Technology 6502 / 6510 CPU emulator. - - Project repo: https://github.com/floooh/chips/ - - NOTE: this file is code-generated from m6502.template.h and m6502_gen.py - in the 'codegen' directory. - - Do this: - ~~~C - #define CHIPS_IMPL - ~~~ - before you include this file in *one* C or C++ file to create the - implementation. - - Optionally provide the following macros with your own implementation - ~~~C - CHIPS_ASSERT(c) - ~~~ - - ## Emulated Pins - - *********************************** - * +-----------+ * - * IRQ --->| |---> A0 * - * NMI --->| |... * - * RDY--->| |---> A15 * - * RES--->| | * - * RW <---| | * - * SYNC <---| | * - * | |<--> D0 * - * (P0)<-->| |... * - * ...| |<--> D7 * - * (P5)<-->| | * - * +-----------+ * - *********************************** - - The input/output P0..P5 pins only exist on the m6510. - - If the RDY pin is active (1) the CPU will loop on the next read - access until the pin goes inactive. - - ## Overview - - m6502.h implements a cycle-stepped 6502/6510 CPU emulator, meaning - that the emulation state can be ticked forward in clock cycles instead - of full instructions. - - To initialize the emulator, fill out a m6502_desc_t structure with - initialization parameters and then call m6502_init(). - - ~~~C - typedef struct { - bool bcd_disabled; // set to true if BCD mode is disabled - m6510_in_t in_cb; // only m6510: port IO input callback - m6510_out_t out_cb; // only m6510: port IO output callback - uint8_t m6510_io_pullup; // only m6510: IO port bits that are 1 when reading - uint8_t m6510_io_floating; // only m6510: unconnected IO port pins - void* m6510_user_data; // only m6510: optional in/out callback user data - } m6502_desc_t; - ~~~ - - At the end of m6502_init(), the CPU emulation will be at the start of - RESET state, and the first 7 ticks will execute the reset sequence - (loading the reset vector at address 0xFFFC and continuing execution - there. - - m6502_init() will return a 64-bit pin mask which must be the input argument - to the first call of m6502_tick(). - - To execute instructions, call m6502_tick() in a loop. m6502_tick() takes - a 64-bit pin mask as input, executes one clock tick, and returns - a modified pin mask. - - After executing one tick, the pin mask must be inspected, a memory read - or write operation must be performed, and the modified pin mask must be - used for the next call to m6502_tick(). This 64-bit pin mask is how - the CPU emulation communicates with the outside world. - - The simplest-possible execution loop would look like this: - - ~~~C - // setup 64 kBytes of memory - uint8_t mem[1<<16] = { ... }; - // initialize the CPU - m6502_t cpu; - uint64_t pins = m6502_init(&cpu, &(m6502_desc_t){...}); - while (...) { - // run the CPU emulation for one tick - pins = m6502_tick(&cpu, pins); - // extract 16-bit address from pin mask - const uint16_t addr = M6502_GET_ADDR(pins); - // perform memory access - if (pins & M6502_RW) { - // a memory read - M6502_SET_DATA(pins, mem[addr]); - } - else { - // a memory write - mem[addr] = M6502_GET_DATA(pins); - } - } - ~~~ - - To start a reset sequence, set the M6502_RES bit in the pin mask and - continue calling the m6502_tick() function. At the start of the next - instruction, the CPU will initiate the 7-tick reset sequence. You do NOT - need to clear the M6502_RES bit, this will be cleared when the reset - sequence starts. - - To request an interrupt, set the M6502_IRQ or M6502_NMI bits in the pin - mask and continue calling the tick function. The interrupt sequence - will be initiated at the end of the current or next instruction - (depending on the exact cycle the interrupt pin has been set). - - Unlike the M6502_RES pin, you are also responsible for clearing the - interrupt pins (typically, the interrupt lines are cleared by the chip - which requested the interrupt once the CPU reads a chip's interrupt - status register to check which chip requested the interrupt). - - To find out whether a new instruction is about to start, check if the - M6502_SYNC pin is set. - - To "goto" a random address at any time, a 'prefetch' like this is - necessary (this basically simulates a normal instruction fetch from - address 'next_pc'). This is usually only needed in "trap code" which - intercepts operating system calls, executes some native code to emulate - the operating system call, and then continue execution somewhere else: - - ~~~C - pins = M6502_SYNC; - M6502_SET_ADDR(pins, next_pc); - M6502_SET_DATA(pins, mem[next_pc]); - m6502_set_pc(next_pc); - ~~~~ - - ## Functions - ~~~C - uint64_t m6502_init(m6502_t* cpu, const m6502_desc_t* desc) - ~~~ - Initialize a m6502_t instance, the desc structure provides - initialization attributes: - ~~~C - typedef struct { - bool bcd_disabled; // set to true if BCD mode is disabled - m6510_in_t m6510_in_cb; // m6510 only: optional port IO input callback - m6510_out_t m6510_out_cb; // m6510 only: optional port IO output callback - void* m6510_user_data; // m6510 only: optional callback user data - uint8_t m6510_io_pullup; // m6510 only: IO port bits that are 1 when reading - uint8_t m6510_io_floating; // m6510 only: unconnected IO port pins - } m6502_desc_t; - ~~~ - - To emulate a m6510 you must provide port IO callbacks in m6510_in_cb - and m6510_out_cb, and should initialize the m6510_io_pullup and - m6510_io_floating members to indicate which of the IO pins are - connected or hardwired to a 1-state. - - ~~~C - uint64_t m6502_tick(m6502_t* cpu, uint64_t pins) - ~~~ - Tick the CPU for one clock cycle. The 'pins' argument and return value - is the current state of the CPU pins used to communicate with the - outside world (see the Overview section above for details). - - ~~~C - uint64_t m6510_iorq(m6502_t* cpu, uint64_t pins) - ~~~ - For the 6510, call this function after the tick callback when memory - access to the special addresses 0 and 1 are requested. m6510_iorq() - may call the input/output callback functions provided in m6502_desc_t. - - ~~~C - void m6502_set_x(m6502_t* cpu, uint8_t val) - void m6502_set_xx(m6502_t* cpu, uint16_t val) - uint8_t m6502_x(m6502_t* cpu) - uint16_t m6502_xx(m6502_t* cpu) - ~~~ - Set and get 6502 registers and flags. - - - ## zlib/libpng license - - Copyright (c) 2018 Andre Weissflog - This software is provided 'as-is', without any express or implied warranty. - In no event will the authors be held liable for any damages arising from the - use of this software. - Permission is granted to anyone to use this software for any purpose, - including commercial applications, and to alter it and redistribute it - freely, subject to the following restrictions: - 1. The origin of this software must not be misrepresented; you must not - claim that you wrote the original software. If you use this software in a - product, an acknowledgment in the product documentation would be - appreciated but is not required. - 2. Altered source versions must be plainly marked as such, and must not - be misrepresented as being the original software. - 3. This notice may not be removed or altered from any source - distribution. -#*/ -#include -#include - -#ifdef __cplusplus -extern "C" { -#endif - -// address bus pins -#define M6502_PIN_A0 (0) -#define M6502_PIN_A1 (1) -#define M6502_PIN_A2 (2) -#define M6502_PIN_A3 (3) -#define M6502_PIN_A4 (4) -#define M6502_PIN_A5 (5) -#define M6502_PIN_A6 (6) -#define M6502_PIN_A7 (7) -#define M6502_PIN_A8 (8) -#define M6502_PIN_A9 (9) -#define M6502_PIN_A10 (10) -#define M6502_PIN_A11 (11) -#define M6502_PIN_A12 (12) -#define M6502_PIN_A13 (13) -#define M6502_PIN_A14 (14) -#define M6502_PIN_A15 (15) - -// data bus pins -#define M6502_PIN_D0 (16) -#define M6502_PIN_D1 (17) -#define M6502_PIN_D2 (18) -#define M6502_PIN_D3 (19) -#define M6502_PIN_D4 (20) -#define M6502_PIN_D5 (21) -#define M6502_PIN_D6 (22) -#define M6502_PIN_D7 (23) - -// control pins -#define M6502_PIN_RW (24) // out: memory read or write access -#define M6502_PIN_SYNC (25) // out: start of a new instruction -#define M6502_PIN_IRQ (26) // in: maskable interrupt requested -#define M6502_PIN_NMI (27) // in: non-maskable interrupt requested -#define M6502_PIN_RDY (28) // in: freeze execution at next read cycle -#define M6510_PIN_AEC (29) // in, m6510 only, put bus lines into tristate mode, not implemented -#define M6502_PIN_RES (30) // request RESET - -// m6510 IO port pins -#define M6510_PIN_P0 (32) -#define M6510_PIN_P1 (33) -#define M6510_PIN_P2 (34) -#define M6510_PIN_P3 (35) -#define M6510_PIN_P4 (36) -#define M6510_PIN_P5 (37) - -// pin bit masks -#define M6502_A0 (1ULL<>16)) -/* merge 8-bit data bus value into 64-bit pins */ -#define M6502_SET_DATA(p,d) {p=(((p)&~0xFF0000ULL)|(((d)<<16)&0xFF0000ULL));} -/* copy data bus value from other pin mask */ -#define M6502_COPY_DATA(p0,p1) (((p0)&~0xFF0000ULL)|((p1)&0xFF0000ULL)) -/* return a pin mask with control-pins, address and data bus */ -#define M6502_MAKE_PINS(ctrl, addr, data) ((ctrl)|(((data)<<16)&0xFF0000ULL)|((addr)&0xFFFFULL)) -/* set the port bits on the 64-bit pin mask */ -#define M6510_SET_PORT(p,d) {p=(((p)&~M6510_PORT_BITS)|((((uint64_t)(d))<<32)&M6510_PORT_BITS));} -/* M6510: check for IO port access to address 0 or 1 */ -#define M6510_CHECK_IO(p) (((p)&0xFFFEULL)==0) - -#ifdef __cplusplus -} /* extern "C" */ -#endif - -/*-- IMPLEMENTATION ----------------------------------------------------------*/ -#ifdef CHIPS_IMPL -#include -#ifndef CHIPS_ASSERT - #include - #define CHIPS_ASSERT(c) assert(c) -#endif - -/* register access functions */ -void m6502_set_a(m6502_t* cpu, uint8_t v) { cpu->A = v; } -void m6502_set_x(m6502_t* cpu, uint8_t v) { cpu->X = v; } -void m6502_set_y(m6502_t* cpu, uint8_t v) { cpu->Y = v; } -void m6502_set_s(m6502_t* cpu, uint8_t v) { cpu->S = v; } -void m6502_set_p(m6502_t* cpu, uint8_t v) { cpu->P = v; } -void m6502_set_pc(m6502_t* cpu, uint16_t v) { cpu->PC = v; } -uint8_t m6502_a(m6502_t* cpu) { return cpu->A; } -uint8_t m6502_x(m6502_t* cpu) { return cpu->X; } -uint8_t m6502_y(m6502_t* cpu) { return cpu->Y; } -uint8_t m6502_s(m6502_t* cpu) { return cpu->S; } -uint8_t m6502_p(m6502_t* cpu) { return cpu->P; } -uint16_t m6502_pc(m6502_t* cpu) { return cpu->PC; } - -/* helper macros and functions for code-generated instruction decoder */ -#define _M6502_NZ(p,v) ((p&~(M6502_NF|M6502_ZF))|((v&0xFF)?(v&M6502_NF):M6502_ZF)) - -static inline void _m6502_adc(m6502_t* cpu, uint8_t val) { - if (cpu->bcd_enabled && (cpu->P & M6502_DF)) { - /* decimal mode (credit goes to MAME) */ - uint8_t c = cpu->P & M6502_CF ? 1 : 0; - cpu->P &= ~(M6502_NF|M6502_VF|M6502_ZF|M6502_CF); - uint8_t al = (cpu->A & 0x0F) + (val & 0x0F) + c; - if (al > 9) { - al += 6; - } - uint8_t ah = (cpu->A >> 4) + (val >> 4) + (al > 0x0F); - if (0 == (uint8_t)(cpu->A + val + c)) { - cpu->P |= M6502_ZF; - } - else if (ah & 0x08) { - cpu->P |= M6502_NF; - } - if (~(cpu->A^val) & (cpu->A^(ah<<4)) & 0x80) { - cpu->P |= M6502_VF; - } - if (ah > 9) { - ah += 6; - } - if (ah > 15) { - cpu->P |= M6502_CF; - } - cpu->A = (ah<<4) | (al & 0x0F); - } - else { - /* default mode */ - uint16_t sum = cpu->A + val + (cpu->P & M6502_CF ? 1:0); - cpu->P &= ~(M6502_VF|M6502_CF); - cpu->P = _M6502_NZ(cpu->P,sum); - if (~(cpu->A^val) & (cpu->A^sum) & 0x80) { - cpu->P |= M6502_VF; - } - if (sum & 0xFF00) { - cpu->P |= M6502_CF; - } - cpu->A = sum & 0xFF; - } -} - -static inline void _m6502_sbc(m6502_t* cpu, uint8_t val) { - if (cpu->bcd_enabled && (cpu->P & M6502_DF)) { - /* decimal mode (credit goes to MAME) */ - uint8_t c = cpu->P & M6502_CF ? 0 : 1; - cpu->P &= ~(M6502_NF|M6502_VF|M6502_ZF|M6502_CF); - uint16_t diff = cpu->A - val - c; - uint8_t al = (cpu->A & 0x0F) - (val & 0x0F) - c; - if ((int8_t)al < 0) { - al -= 6; - } - uint8_t ah = (cpu->A>>4) - (val>>4) - ((int8_t)al < 0); - if (0 == (uint8_t)diff) { - cpu->P |= M6502_ZF; - } - else if (diff & 0x80) { - cpu->P |= M6502_NF; - } - if ((cpu->A^val) & (cpu->A^diff) & 0x80) { - cpu->P |= M6502_VF; - } - if (!(diff & 0xFF00)) { - cpu->P |= M6502_CF; - } - if (ah & 0x80) { - ah -= 6; - } - cpu->A = (ah<<4) | (al & 0x0F); - } - else { - /* default mode */ - uint16_t diff = cpu->A - val - (cpu->P & M6502_CF ? 0 : 1); - cpu->P &= ~(M6502_VF|M6502_CF); - cpu->P = _M6502_NZ(cpu->P, (uint8_t)diff); - if ((cpu->A^val) & (cpu->A^diff) & 0x80) { - cpu->P |= M6502_VF; - } - if (!(diff & 0xFF00)) { - cpu->P |= M6502_CF; - } - cpu->A = diff & 0xFF; - } -} - -static inline void _m6502_cmp(m6502_t* cpu, uint8_t r, uint8_t v) { - uint16_t t = r - v; - cpu->P = (_M6502_NZ(cpu->P, (uint8_t)t) & ~M6502_CF) | ((t & 0xFF00) ? 0:M6502_CF); -} - -static inline uint8_t _m6502_asl(m6502_t* cpu, uint8_t v) { - cpu->P = (_M6502_NZ(cpu->P, v<<1) & ~M6502_CF) | ((v & 0x80) ? M6502_CF:0); - return v<<1; -} - -static inline uint8_t _m6502_lsr(m6502_t* cpu, uint8_t v) { - cpu->P = (_M6502_NZ(cpu->P, v>>1) & ~M6502_CF) | ((v & 0x01) ? M6502_CF:0); - return v>>1; -} - -static inline uint8_t _m6502_rol(m6502_t* cpu, uint8_t v) { - bool carry = cpu->P & M6502_CF; - cpu->P &= ~(M6502_NF|M6502_ZF|M6502_CF); - if (v & 0x80) { - cpu->P |= M6502_CF; - } - v <<= 1; - if (carry) { - v |= 1; - } - cpu->P = _M6502_NZ(cpu->P, v); - return v; -} - -static inline uint8_t _m6502_ror(m6502_t* cpu, uint8_t v) { - bool carry = cpu->P & M6502_CF; - cpu->P &= ~(M6502_NF|M6502_ZF|M6502_CF); - if (v & 1) { - cpu->P |= M6502_CF; - } - v >>= 1; - if (carry) { - v |= 0x80; - } - cpu->P = _M6502_NZ(cpu->P, v); - return v; -} - -static inline void _m6502_bit(m6502_t* cpu, uint8_t v) { - uint8_t t = cpu->A & v; - cpu->P &= ~(M6502_NF|M6502_VF|M6502_ZF); - if (!t) { - cpu->P |= M6502_ZF; - } - cpu->P |= v & (M6502_NF|M6502_VF); -} - -static inline void _m6502_arr(m6502_t* cpu) { - /* undocumented, unreliable ARR instruction, but this is tested - by the Wolfgang Lorenz C64 test suite - implementation taken from MAME - */ - if (cpu->bcd_enabled && (cpu->P & M6502_DF)) { - bool c = cpu->P & M6502_CF; - cpu->P &= ~(M6502_NF|M6502_VF|M6502_ZF|M6502_CF); - uint8_t a = cpu->A>>1; - if (c) { - a |= 0x80; - } - cpu->P = _M6502_NZ(cpu->P,a); - if ((a ^ cpu->A) & 0x40) { - cpu->P |= M6502_VF; - } - if ((cpu->A & 0xF) >= 5) { - a = ((a + 6) & 0xF) | (a & 0xF0); - } - if ((cpu->A & 0xF0) >= 0x50) { - a += 0x60; - cpu->P |= M6502_CF; - } - cpu->A = a; - } - else { - bool c = cpu->P & M6502_CF; - cpu->P &= ~(M6502_NF|M6502_VF|M6502_ZF|M6502_CF); - cpu->A >>= 1; - if (c) { - cpu->A |= 0x80; - } - cpu->P = _M6502_NZ(cpu->P,cpu->A); - if (cpu->A & 0x40) { - cpu->P |= M6502_VF|M6502_CF; - } - if (cpu->A & 0x20) { - cpu->P ^= M6502_VF; - } - } -} - -/* undocumented SBX instruction: - AND X register with accumulator and store result in X register, then - subtract byte from X register (without borrow) where the - subtract works like a CMP instruction -*/ -static inline void _m6502_sbx(m6502_t* cpu, uint8_t v) { - uint16_t t = (cpu->A & cpu->X) - v; - cpu->P = _M6502_NZ(cpu->P, t) & ~M6502_CF; - if (!(t & 0xFF00)) { - cpu->P |= M6502_CF; - } - cpu->X = (uint8_t)t; -} -#undef _M6502_NZ - -uint64_t m6502_init(m6502_t* c, const m6502_desc_t* desc) { - CHIPS_ASSERT(c && desc); - memset(c, 0, sizeof(*c)); - c->P = M6502_ZF; - c->bcd_enabled = !desc->bcd_disabled; - c->PINS = M6502_RW | M6502_SYNC | M6502_RES; - c->in_cb = desc->m6510_in_cb; - c->out_cb = desc->m6510_out_cb; - c->user_data = desc->m6510_user_data; - c->io_pullup = desc->m6510_io_pullup; - c->io_floating = desc->m6510_io_floating; - return c->PINS; -} - -/* only call this when accessing address 0 or 1 (M6510_CHECK_IO(pins) evaluates to true) */ -uint64_t m6510_iorq(m6502_t* c, uint64_t pins) { - CHIPS_ASSERT(c->in_cb && c->out_cb); - if ((pins & M6502_A0) == 0) { - /* address 0: access to data direction register */ - if (pins & M6502_RW) { - /* read IO direction bits */ - M6502_SET_DATA(pins, c->io_ddr); - } - else { - /* write IO direction bits and update outside world */ - c->io_ddr = M6502_GET_DATA(pins); - c->io_drive = (c->io_out & c->io_ddr) | (c->io_drive & ~c->io_ddr); - c->out_cb((c->io_out & c->io_ddr) | (c->io_pullup & ~c->io_ddr), c->user_data); - c->io_pins = (c->io_out & c->io_ddr) | (c->io_inp & ~c->io_ddr); - } - } - else { - /* address 1: perform I/O */ - if (pins & M6502_RW) { - /* an input operation */ - c->io_inp = c->in_cb(c->user_data); - uint8_t val = ((c->io_inp | (c->io_floating & c->io_drive)) & ~c->io_ddr) | (c->io_out & c->io_ddr); - M6502_SET_DATA(pins, val); - } - else { - /* an output operation */ - c->io_out = M6502_GET_DATA(pins); - c->io_drive = (c->io_out & c->io_ddr) | (c->io_drive & ~c->io_ddr); - c->out_cb((c->io_out & c->io_ddr) | (c->io_pullup & ~c->io_ddr), c->user_data); - } - c->io_pins = (c->io_out & c->io_ddr) | (c->io_inp & ~c->io_ddr); - } - return pins; -} - -void m6502_snapshot_onsave(m6502_t* snapshot) { - CHIPS_ASSERT(snapshot); - snapshot->in_cb = 0; - snapshot->out_cb = 0; - snapshot->user_data = 0; -} - -void m6502_snapshot_onload(m6502_t* snapshot, m6502_t* sys) { - CHIPS_ASSERT(snapshot && sys); - snapshot->in_cb = sys->in_cb; - snapshot->out_cb = sys->out_cb; - snapshot->user_data = sys->user_data; -} - -/* set 16-bit address in 64-bit pin mask */ -#define _SA(addr) pins=(pins&~0xFFFF)|((addr)&0xFFFFULL) -/* extract 16-bit addess from pin mask */ -#define _GA() ((uint16_t)(pins&0xFFFFULL)) -/* set 16-bit address and 8-bit data in 64-bit pin mask */ -#define _SAD(addr,data) pins=(pins&~0xFFFFFF)|((((data)&0xFF)<<16)&0xFF0000ULL)|((addr)&0xFFFFULL) -/* fetch next opcode byte */ -#define _FETCH() _SA(c->PC);_ON(M6502_SYNC); -/* set 8-bit data in 64-bit pin mask */ -#define _SD(data) pins=((pins&~0xFF0000ULL)|(((data&0xFF)<<16)&0xFF0000ULL)) -/* extract 8-bit data from 64-bit pin mask */ -#define _GD() ((uint8_t)((pins&0xFF0000ULL)>>16)) -/* enable control pins */ -#define _ON(m) pins|=(m) -/* disable control pins */ -#define _OFF(m) pins&=~(m) -/* a memory read tick */ -#define _RD() _ON(M6502_RW); -/* a memory write tick */ -#define _WR() _OFF(M6502_RW); -/* set N and Z flags depending on value */ -#define _NZ(v) c->P=((c->P&~(M6502_NF|M6502_ZF))|((v&0xFF)?(v&M6502_NF):M6502_ZF)) - -#if defined(_MSC_VER) -#pragma warning(push) -#pragma warning(disable:4244) /* conversion from 'uint16_t' to 'uint8_t', possible loss of data */ -#endif - -uint64_t m6502_tick(m6502_t* c, uint64_t pins) { - if (pins & (M6502_SYNC|M6502_IRQ|M6502_NMI|M6502_RDY|M6502_RES)) { - // interrupt detection also works in RDY phases, but only NMI is "sticky" - - // NMI is edge-triggered - if (0 != ((pins & (pins ^ c->PINS)) & M6502_NMI)) { - c->nmi_pip |= 0x100; - } - // IRQ test is level triggered - if ((pins & M6502_IRQ) && (0 == (c->P & M6502_IF))) { - c->irq_pip |= 0x100; - } - - // RDY pin is only checked during read cycles - if ((pins & (M6502_RW|M6502_RDY)) == (M6502_RW|M6502_RDY)) { - M6510_SET_PORT(pins, c->io_pins); - c->PINS = pins; - c->irq_pip <<= 1; - return pins; - } - if (pins & M6502_SYNC) { - // load new instruction into 'instruction register' and restart tick counter - c->IR = _GD()<<3; - _OFF(M6502_SYNC); - - // check IRQ, NMI and RES state - // - IRQ is level-triggered and must be active in the full cycle - // before SYNC - // - NMI is edge-triggered, and the change must have happened in - // any cycle before SYNC - // - RES behaves slightly different than on a real 6502, we go - // into RES state as soon as the pin goes active, from there - // on, behaviour is 'standard' - if (0 != (c->irq_pip & 0x400)) { - c->brk_flags |= M6502_BRK_IRQ; - } - if (0 != (c->nmi_pip & 0xFC00)) { - c->brk_flags |= M6502_BRK_NMI; - } - if (0 != (pins & M6502_RES)) { - c->brk_flags |= M6502_BRK_RESET; - c->io_ddr = 0; - c->io_out = 0; - c->io_inp = 0; - c->io_pins = 0; - } - c->irq_pip &= 0x3FF; - c->nmi_pip &= 0x3FF; - - // if interrupt or reset was requested, force a BRK instruction - if (c->brk_flags) { - c->IR = 0; - c->P &= ~M6502_BF; - pins &= ~M6502_RES; - } - else { - c->PC++; - } - } - } - // reads are default, writes are special - _RD(); - switch (c->IR++) { -$decode_block - } - M6510_SET_PORT(pins, c->io_pins); - c->PINS = pins; - c->irq_pip <<= 1; - c->nmi_pip <<= 1; - return pins; -} -#if defined(_MSC_VER) -#pragma warning(pop) -#endif - -#undef _SA -#undef _SAD -#undef _FETCH -#undef _SD -#undef _GD -#undef _ON -#undef _OFF -#undef _RD -#undef _WR -#undef _NZ -#endif /* CHIPS_IMPL */ diff --git a/codegen/m6502_gen.py b/codegen/m6502_gen.py index a7aaac64..9dfe8134 100644 --- a/codegen/m6502_gen.py +++ b/codegen/m6502_gen.py @@ -2,10 +2,9 @@ # m6502_decoder.py # Generate instruction decoder for m6502.h emulator. #------------------------------------------------------------------------------- -from string import Template +import templ -InpPath = 'm6502.template.h' -OutPath = '../chips/m6502.h' +INOUT_PATH = '../chips/m6502.h' # flag bits CF = (1<<0) @@ -73,7 +72,7 @@ def branch_name(m, v): [[A_IMM,M_R_],[A_IMM,M_R_],[A_IMM,M_R_],[A_IMM,M_R_],[A_IMM,M_R_],[A_IMM,M_R_],[A_IMM,M_R_],[A_IMM,M_R_]], # relative branches [[A_ZPX,M_R_],[A_ZPX,M_R_],[A_ZPX,M_R_],[A_ZPX,M_R_],[A_ZPX,M__W],[A_ZPX,M_R_],[A_ZPX,M_R_],[A_ZPX,M_R_]], [[A____,M___],[A____,M___],[A____,M___],[A____,M___],[A____,M___],[A____,M___],[A____,M___],[A____,M___]], - [[A_ABX,M_R_],[A_ABX,M_R_],[A_ABX,M_R_],[A_ABX,M_R_],[A_ABX,M__W],[A_ABX,M_R_],[A_ABX,M_R_],[A_ABX,M_R_]] + [[A_ABX,M_R_],[A_ABX,M_R_],[A_ABX,M_R_],[A_ABX,M_R_],[A_ABX,M__W],[A_ABX,M_R_],[A_ABX,M_R_],[A_ABX,M_R_]] ], # cc = 01 [ @@ -169,7 +168,7 @@ def invalid_opcode(op): #------------------------------------------------------------------------------- def enc_addr(op, addr_mode, mem_access): if addr_mode == A____: - # no addressing, this still puts the PC on the address bus without + # no addressing, this still puts the PC on the address bus without # incrementing the PC op.t('_SA(c->PC);') elif addr_mode == A_IMM: @@ -238,7 +237,7 @@ def enc_addr(op, addr_mode, mem_access): # jmp is completely handled in instruction decoding pass elif addr_mode == A_JSR: - # jsr is completely handled in instruction decoding + # jsr is completely handled in instruction decoding pass else: # invalid instruction @@ -350,7 +349,7 @@ def i_php(o): def i_plp(o): cmt(o,'PLP') o.t('_SA(0x0100|c->S++);') # read junk byte from current SP - o.t('_SA(0x0100|c->S);') # read actual byte + o.t('_SA(0x0100|c->S);') # read actual byte o.t('c->P=(_GD()|M6502_BF)&~M6502_XF;'); #------------------------------------------------------------------------------- @@ -643,7 +642,7 @@ def x_sha(o): #------------------------------------------------------------------------------- def x_shx(o): # undocumented SHX - # AND X register with the high byte of the target address of the + # AND X register with the high byte of the target address of the # argument + 1. Store the result in memory. # u_cmt(o, 'SHX') @@ -813,16 +812,16 @@ def enc_op(op): else: i_inc(o) elif cc == 3: # undocumented block - if aaa == 0: + if aaa == 0: if bbb == 2: x_anc(o) else: u_slo(o) - elif aaa == 1: + elif aaa == 1: if bbb == 2: x_anc(o) else: u_rla(o) elif aaa == 2: if bbb == 2: x_asr(o) else: u_sre(o) - elif aaa == 3: + elif aaa == 3: if bbb == 2: x_arr(o) else: u_rra(o) elif aaa == 4: @@ -847,14 +846,15 @@ def enc_op(op): o.t('_FETCH();') return o -#------------------------------------------------------------------------------- -# execution starts here -# -for op in range(0, 256): - write_op(enc_op(op)) - -with open(InpPath, 'r') as inf: - templ = Template(inf.read()) - c_src = templ.safe_substitute(decode_block=out_lines) - with open(OutPath, 'w') as outf: - outf.write(c_src) +def write_result(): + with open(INOUT_PATH, 'r') as f: + lines = f.read().splitlines() + lines = templ.replace(lines, 'decoder', out_lines) + out_str = '\n'.join(lines) + '\n' + with open(INOUT_PATH, 'w') as f: + f.write(out_str) + +if __name__ == '__main__': + for op in range(0, 256): + write_op(enc_op(op)) + write_result() diff --git a/codegen/m6502_gen.sh b/codegen/m6502_gen.sh new file mode 100755 index 00000000..1609c487 --- /dev/null +++ b/codegen/m6502_gen.sh @@ -0,0 +1,4 @@ +python3 -m venv .venv +source .venv/bin/activate +python3 -m pip install pyyaml +python3 m6502_gen.py diff --git a/codegen/templ.py b/codegen/templ.py new file mode 100644 index 00000000..0514a341 --- /dev/null +++ b/codegen/templ.py @@ -0,0 +1,20 @@ + +# replace `<% templ_name %>` with templ_str +def replace(src_lines, templ_name, templ_str): + templ_lines = templ_str.splitlines() + res = [] + skip = False + for src_line in src_lines: + if skip: + # skip src lines until template end-marker found + if '%>' in src_line: + skip = False + res.append(src_line) + else: + res.append(src_line) + # check for start of template + if f'<% {templ_name}' in src_line: + skip = True + for templ_line in templ_lines: + res.append(templ_line.rstrip()) + return res diff --git a/codegen/z80.template.h b/codegen/z80.template.h deleted file mode 100644 index 417e8660..00000000 --- a/codegen/z80.template.h +++ /dev/null @@ -1,1155 +0,0 @@ -#pragma once -/*# - # z80.h - - A cycle-stepped Z80 emulator in a C header. - - Do this: - ~~~~C - #define CHIPS_IMPL - ~~~~ - before you include this file in *one* C or C++ file to create the - implementation. - - Optionally provide - ~~~C - #define CHIPS_ASSERT(x) your_own_asset_macro(x) - ~~~ - - ## Emulated Pins - *********************************** - * +-----------+ * - * M1 <---| |---> A0 * - * MREQ <---| |---> A1 * - * IORQ <---| |---> A2 * - * RD <---| |---> .. * - * WR <---| Z80 |---> A15 * - * HALT <---| | * - * WAIT --->| |<--> D0 * - * INT --->| |<--> D1 * - * NMI --->| |<--> ... * - * RFSH <---| |<--> D7 * - * +-----------+ * - *********************************** - - ## Functions - - ~~~C - uint64_t z80_init(z80_t* cpu); - ~~~ - Initializes a new z80_t instance, returns initial pin mask to start - execution at address 0. - - ~~~C - uint64_t z80_reset(z80_t* cpu) - ~~~ - Resets a z80_t instance, returns pin mask to start execution at - address 0. - - ~~~C - uint64_t z80_tick(z80_t* cpu, uint64_t pins) - ~~~ - Step the z80_t instance for one clock cycle. - - ~~~C - uint64_t z80_prefetch(z80_t* cpu, uint16_t new_pc) - ~~~ - Call this function to force execution to start at a specific - PC. Use the returned pin mask as argument into the next z80_tick() call. - - ~~~C - bool z80_opdone(z80_t* cpu) - ~~~ - Helper function to detect whether the z80_t instance has completed - an instruction. - - ## HOWTO - - Initialize a new z80_t instance and start ticking it: - ~~~C - z80_t cpu; - uint64_t pins = z80_init(&cpu); - while (!done) { - pins = z80_tick(&cpu, pins); - } - ~~~ - Since there is no memory attached yet, the CPU will simply run whatever opcode - bytes are present on the data bus (in this case the data bus is zero, so the CPU - just runs throught the same NOP over and over). - - Next, add some memory and inspect and modify the pin mask to handle memory accesses: - ~~~C - uint8_t mem[(1<<16)] = {0}; - z80_t cpu; - uint64_t pins = z80_init(&cpu); - while (!done) { - pins = z80_tick(&cpu, pins); - if (pins & Z80_MREQ) { - const uint16_t addr = Z80_GET_ADDR(pins); - if (pins & Z80_RD) { - uint8_t data = mem[addr]; - Z80_SET_DATA(pins, data); - } - else if (pins & Z80_WR) { - uint8_t data = Z80_GET_DATA(pins); - mem[addr] = data; - } - } - } - ~~~ - The CPU will now run through the whole address space executing NOPs (because the memory is - filled with 0s instead of a valid program). If there would be a valid Z80 program at memory - address 0, this would be executed instead. - - IO requests are handled the same as memory requests, but instead of the MREQ pin, the - IORQ pin must be checked: - ~~~C - uint8_t mem[(1<<16)] = {0}; - z80_t cpu; - uint64_t pins = z80_init(&cpu); - while (!done) { - pins = z80_tick(&cpu, pins); - if (pins & Z80_MREQ) { - const uint16_t addr = Z80_GET_ADDR(pins); - if (pins & Z80_RD) { - uint8_t data = mem[addr]; - Z80_SET_DATA(pins, data); - } - else if (pins & Z80_WR) { - uint8_t data = Z80_GET_DATA(pins); - mem[addr] = data; - } - } - else if (pins & Z80_IORQ) { - const uint16_t port = Z80_GET_ADDR(pins); - if (pins & Z80_RD) { - // handle IO input request at port - ... - } - else if (pins & Z80_WR) { - // handle IO output request at port - ... - } - } - } - ~~~ - - Handle interrupt acknowledge cycles by checking for Z80_IORQ|Z80_M1: - ~~~C - uint8_t mem[(1<<16)] = {0}; - z80_t cpu; - uint64_t pins = z80_init(&cpu); - while (!done) { - pins = z80_tick(&cpu, pins); - if (pins & Z80_MREQ) { - const uint16_t addr = Z80_GET_ADDR(pins); - if (pins & Z80_RD) { - uint8_t data = mem[addr]; - Z80_SET_DATA(pins, data); - } - else if (pins & Z80_WR) { - uint8_t data = Z80_GET_DATA(pins); - mem[addr] = data; - } - } - else if (pins & Z80_IORQ) { - const uint16_t addr = Z80_GET_ADDR(pins); - if (pins & Z80_M1) { - // an interrupt acknowledge cycle, depending on the emulated system, - // put either an instruction byte, or an interrupt vector on the data bus - Z80_SET_DATA(pins, opcode_or_intvec); - } - else if (pins & Z80_RD) { - // handle IO input request at port `addr` - ... - } - else if (pins & Z80_WR) { - // handle IO output request at port `addr` - ... - } - } - } - ~~~ - - To request an interrupt, or inject a wait state just set the respective pin - (Z80_INT, Z80_NMI, Z80_WAIT), don't forget to clear the pin again later (the - details on when those pins are set and cleared depend heavily on the - emulated system). - - !!! note - NOTE: The Z80_RES pin is currently not emulated. Instead call the `z80_reset()` function. - - To emulate a whole computer system, add the per-tick code for the rest of the system to the - basic ticking code above. - - If the emulated system uses the Z80 daisychain interrupt protocol (for instance when using - the Z80 family chips like the PIO or CTC), tick those chips in interrupt priority order and - set the Z80_IEIO pin before the highest priority chip in the daisychain is ticked: - - ~~~C - ... - while (!done) { - pins = z80_tick(&cpu, pins); - ... - // tick Z80 family chips in 'daisychain order': - pins |= Z80_IEIO; - ... - pins = z80ctc_tick(&ctc, pins); - ... - pins = z80pio_tick(&pio, pins); - ... - // the Z80_INT pin will now be set if any of the chips wants to issue an interrupt request - } - ~~~ -#*/ -/* - zlib/libpng license - - Copyright (c) 2021 Andre Weissflog - This software is provided 'as-is', without any express or implied warranty. - In no event will the authors be held liable for any damages arising from the - use of this software. - Permission is granted to anyone to use this software for any purpose, - including commercial applications, and to alter it and redistribute it - freely, subject to the following restrictions: - 1. The origin of this software must not be misrepresented; you must not - claim that you wrote the original software. If you use this software in a - product, an acknowledgment in the product documentation would be - appreciated but is not required. - 2. Altered source versions must be plainly marked as such, and must not - be misrepresented as being the original software. - 3. This notice may not be removed or altered from any source - distribution. -*/ -#include -#include - -#ifdef __cplusplus -extern "C" { -#endif - -// address pins -#define Z80_PIN_A0 (0) -#define Z80_PIN_A1 (1) -#define Z80_PIN_A2 (2) -#define Z80_PIN_A3 (3) -#define Z80_PIN_A4 (4) -#define Z80_PIN_A5 (5) -#define Z80_PIN_A6 (6) -#define Z80_PIN_A7 (7) -#define Z80_PIN_A8 (8) -#define Z80_PIN_A9 (9) -#define Z80_PIN_A10 (10) -#define Z80_PIN_A11 (11) -#define Z80_PIN_A12 (12) -#define Z80_PIN_A13 (13) -#define Z80_PIN_A14 (14) -#define Z80_PIN_A15 (15) - -// data pins -#define Z80_PIN_D0 (16) -#define Z80_PIN_D1 (17) -#define Z80_PIN_D2 (18) -#define Z80_PIN_D3 (19) -#define Z80_PIN_D4 (20) -#define Z80_PIN_D5 (21) -#define Z80_PIN_D6 (22) -#define Z80_PIN_D7 (23) - -// control pins -#define Z80_PIN_M1 (24) // machine cycle 1 -#define Z80_PIN_MREQ (25) // memory request -#define Z80_PIN_IORQ (26) // input/output request -#define Z80_PIN_RD (27) // read -#define Z80_PIN_WR (28) // write -#define Z80_PIN_HALT (29) // halt state -#define Z80_PIN_INT (30) // interrupt request -#define Z80_PIN_RES (31) // reset requested -#define Z80_PIN_NMI (32) // non-maskable interrupt -#define Z80_PIN_WAIT (33) // wait requested -#define Z80_PIN_RFSH (34) // refresh - -// virtual pins (for interrupt daisy chain protocol) -#define Z80_PIN_IEIO (37) // unified daisy chain 'Interrupt Enable In+Out' -#define Z80_PIN_RETI (38) // cpu has decoded a RETI instruction - -// pin bit masks -#define Z80_A0 (1ULL<>16)) -#define Z80_SET_DATA(p,d) {p=((p)&~0xFF0000ULL)|(((d)<<16)&0xFF0000ULL);} - -// status flags -#define Z80_CF (1<<0) // carry -#define Z80_NF (1<<1) // add/subtract -#define Z80_VF (1<<2) // parity/overflow -#define Z80_PF Z80_VF -#define Z80_XF (1<<3) // undocumented bit 3 -#define Z80_HF (1<<4) // half carry -#define Z80_YF (1<<5) // undocumented bit 5 -#define Z80_ZF (1<<6) // zero -#define Z80_SF (1<<7) // sign - -// CPU state -typedef struct { - uint16_t step; // the currently active decoder step - uint16_t addr; // effective address for (HL),(IX+d),(IY+d) - uint8_t dlatch; // temporary store for data bus value - uint8_t opcode; // current opcode - uint8_t hlx_idx; // index into hlx[] for mapping hl to ix or iy (0: hl, 1: ix, 2: iy) - bool prefix_active; // true if any prefix currently active (only needed in z80_opdone()) - uint64_t pins; // last pin state, used for NMI detection - uint64_t int_bits; // track INT and NMI state - union { struct { uint8_t pcl; uint8_t pch; }; uint16_t pc; }; - - // NOTE: These unions are fine in C, but not C++. - union { struct { uint8_t f; uint8_t a; }; uint16_t af; }; - union { struct { uint8_t c; uint8_t b; }; uint16_t bc; }; - union { struct { uint8_t e; uint8_t d; }; uint16_t de; }; - union { - struct { - union { struct { uint8_t l; uint8_t h; }; uint16_t hl; }; - union { struct { uint8_t ixl; uint8_t ixh; }; uint16_t ix; }; - union { struct { uint8_t iyl; uint8_t iyh; }; uint16_t iy; }; - }; - struct { union { struct { uint8_t l; uint8_t h; }; uint16_t hl; }; } hlx[3]; - }; - union { struct { uint8_t wzl; uint8_t wzh; }; uint16_t wz; }; - union { struct { uint8_t spl; uint8_t sph; }; uint16_t sp; }; - union { struct { uint8_t r; uint8_t i; }; uint16_t ir; }; - uint16_t af2, bc2, de2, hl2; // shadow register bank - uint8_t im; - bool iff1, iff2; -} z80_t; - -// initialize a new Z80 instance and return initial pin mask -uint64_t z80_init(z80_t* cpu); -// immediately put Z80 into reset state -uint64_t z80_reset(z80_t* cpu); -// execute one tick, return new pin mask -uint64_t z80_tick(z80_t* cpu, uint64_t pins); -// force execution to continue at address 'new_pc' -uint64_t z80_prefetch(z80_t* cpu, uint16_t new_pc); -// return true when full instruction has finished -bool z80_opdone(z80_t* cpu); - -#ifdef __cplusplus -} // extern C -#endif - -//-- IMPLEMENTATION ------------------------------------------------------------ -#ifdef CHIPS_IMPL -#include // memset -#ifndef CHIPS_ASSERT -#include -#define CHIPS_ASSERT(c) assert(c) -#endif - -#if defined(__GNUC__) -#define _Z80_UNREACHABLE __builtin_unreachable() -#elif defined(_MSC_VER) -#define _Z80_UNREACHABLE __assume(0) -#else -#define _Z80_UNREACHABLE -#endif - -// values for hlx_idx for mapping HL, IX or IY, used as index into hlx[] -#define _Z80_MAP_HL (0) -#define _Z80_MAP_IX (1) -#define _Z80_MAP_IY (2) - -uint64_t z80_init(z80_t* cpu) { - CHIPS_ASSERT(cpu); - // initial state as described in 'The Undocumented Z80 Documented' - memset(cpu, 0, sizeof(z80_t)); - cpu->af = cpu->bc = cpu->de = cpu->hl = 0xFFFF; - cpu->wz = cpu->sp = cpu->ix = cpu->iy = 0xFFFF; - cpu->af2 = cpu->bc2 = cpu->de2 = cpu->hl2 = 0xFFFF; - return z80_prefetch(cpu, 0x0000); -} - -uint64_t z80_reset(z80_t* cpu) { - // reset state as described in 'The Undocumented Z80 Documented' - memset(cpu, 0, sizeof(z80_t)); - cpu->af = cpu->bc = cpu->de = cpu->hl = 0xFFFF; - cpu->wz = cpu->sp = cpu->ix = cpu->iy = 0xFFFF; - cpu->af2 = cpu->bc2 = cpu->de2 = cpu->hl2 = 0xFFFF; - return z80_prefetch(cpu, 0x0000); -} - -bool z80_opdone(z80_t* cpu) { - // because of the overlapped cycle, the result of the previous - // instruction is only available in M1/T2 - return ((cpu->pins & (Z80_M1|Z80_RD)) == (Z80_M1|Z80_RD)) && !cpu->prefix_active; -} - -static inline uint64_t _z80_halt(z80_t* cpu, uint64_t pins) { - cpu->pc--; - return pins | Z80_HALT; -} - -// sign+zero+parity lookup table -static const uint8_t _z80_szp_flags[256] = { - 0x44,0x00,0x00,0x04,0x00,0x04,0x04,0x00,0x08,0x0c,0x0c,0x08,0x0c,0x08,0x08,0x0c, - 0x00,0x04,0x04,0x00,0x04,0x00,0x00,0x04,0x0c,0x08,0x08,0x0c,0x08,0x0c,0x0c,0x08, - 0x20,0x24,0x24,0x20,0x24,0x20,0x20,0x24,0x2c,0x28,0x28,0x2c,0x28,0x2c,0x2c,0x28, - 0x24,0x20,0x20,0x24,0x20,0x24,0x24,0x20,0x28,0x2c,0x2c,0x28,0x2c,0x28,0x28,0x2c, - 0x00,0x04,0x04,0x00,0x04,0x00,0x00,0x04,0x0c,0x08,0x08,0x0c,0x08,0x0c,0x0c,0x08, - 0x04,0x00,0x00,0x04,0x00,0x04,0x04,0x00,0x08,0x0c,0x0c,0x08,0x0c,0x08,0x08,0x0c, - 0x24,0x20,0x20,0x24,0x20,0x24,0x24,0x20,0x28,0x2c,0x2c,0x28,0x2c,0x28,0x28,0x2c, - 0x20,0x24,0x24,0x20,0x24,0x20,0x20,0x24,0x2c,0x28,0x28,0x2c,0x28,0x2c,0x2c,0x28, - 0x80,0x84,0x84,0x80,0x84,0x80,0x80,0x84,0x8c,0x88,0x88,0x8c,0x88,0x8c,0x8c,0x88, - 0x84,0x80,0x80,0x84,0x80,0x84,0x84,0x80,0x88,0x8c,0x8c,0x88,0x8c,0x88,0x88,0x8c, - 0xa4,0xa0,0xa0,0xa4,0xa0,0xa4,0xa4,0xa0,0xa8,0xac,0xac,0xa8,0xac,0xa8,0xa8,0xac, - 0xa0,0xa4,0xa4,0xa0,0xa4,0xa0,0xa0,0xa4,0xac,0xa8,0xa8,0xac,0xa8,0xac,0xac,0xa8, - 0x84,0x80,0x80,0x84,0x80,0x84,0x84,0x80,0x88,0x8c,0x8c,0x88,0x8c,0x88,0x88,0x8c, - 0x80,0x84,0x84,0x80,0x84,0x80,0x80,0x84,0x8c,0x88,0x88,0x8c,0x88,0x8c,0x8c,0x88, - 0xa0,0xa4,0xa4,0xa0,0xa4,0xa0,0xa0,0xa4,0xac,0xa8,0xa8,0xac,0xa8,0xac,0xac,0xa8, - 0xa4,0xa0,0xa0,0xa4,0xa0,0xa4,0xa4,0xa0,0xa8,0xac,0xac,0xa8,0xac,0xa8,0xa8,0xac, -}; - -static inline uint8_t _z80_sz_flags(uint8_t val) { - return (val != 0) ? (val & Z80_SF) : Z80_ZF; -} - -static inline uint8_t _z80_szyxch_flags(uint8_t acc, uint8_t val, uint32_t res) { - return _z80_sz_flags(res) | - (res & (Z80_YF|Z80_XF)) | - ((res >> 8) & Z80_CF) | - ((acc ^ val ^ res) & Z80_HF); -} - -static inline uint8_t _z80_add_flags(uint8_t acc, uint8_t val, uint32_t res) { - return _z80_szyxch_flags(acc, val, res) | ((((val ^ acc ^ 0x80) & (val ^ res)) >> 5) & Z80_VF); -} - -static inline uint8_t _z80_sub_flags(uint8_t acc, uint8_t val, uint32_t res) { - return Z80_NF | _z80_szyxch_flags(acc, val, res) | ((((val ^ acc) & (res ^ acc)) >> 5) & Z80_VF); -} - -static inline uint8_t _z80_cp_flags(uint8_t acc, uint8_t val, uint32_t res) { - return Z80_NF | - _z80_sz_flags(res) | - (val & (Z80_YF|Z80_XF)) | - ((res >> 8) & Z80_CF) | - ((acc ^ val ^ res) & Z80_HF) | - ((((val ^ acc) & (res ^ acc)) >> 5) & Z80_VF); -} - -static inline uint8_t _z80_sziff2_flags(z80_t* cpu, uint8_t val) { - return (cpu->f & Z80_CF) | _z80_sz_flags(val) | (val & (Z80_YF|Z80_XF)) | (cpu->iff2 ? Z80_PF : 0); -} - -static inline void _z80_add8(z80_t* cpu, uint8_t val) { - uint32_t res = cpu->a + val; - cpu->f = _z80_add_flags(cpu->a, val, res); - cpu->a = (uint8_t)res; -} - -static inline void _z80_adc8(z80_t* cpu, uint8_t val) { - uint32_t res = cpu->a + val + (cpu->f & Z80_CF); - cpu->f = _z80_add_flags(cpu->a, val, res); - cpu->a = (uint8_t)res; -} - -static inline void _z80_sub8(z80_t* cpu, uint8_t val) { - uint32_t res = (uint32_t) ((int)cpu->a - (int)val); - cpu->f = _z80_sub_flags(cpu->a, val, res); - cpu->a = (uint8_t)res; -} - -static inline void _z80_sbc8(z80_t* cpu, uint8_t val) { - uint32_t res = (uint32_t) ((int)cpu->a - (int)val - (cpu->f & Z80_CF)); - cpu->f = _z80_sub_flags(cpu->a, val, res); - cpu->a = (uint8_t)res; -} - -static inline void _z80_and8(z80_t* cpu, uint8_t val) { - cpu->a &= val; - cpu->f = _z80_szp_flags[cpu->a] | Z80_HF; -} - -static inline void _z80_xor8(z80_t* cpu, uint8_t val) { - cpu->a ^= val; - cpu->f = _z80_szp_flags[cpu->a]; -} - -static inline void _z80_or8(z80_t* cpu, uint8_t val) { - cpu->a |= val; - cpu->f = _z80_szp_flags[cpu->a]; -} - -static inline void _z80_cp8(z80_t* cpu, uint8_t val) { - uint32_t res = (uint32_t) ((int)cpu->a - (int)val); - cpu->f = _z80_cp_flags(cpu->a, val, res); -} - -static inline void _z80_neg8(z80_t* cpu) { - uint32_t res = (uint32_t) (0 - (int)cpu->a); - cpu->f = _z80_sub_flags(0, cpu->a, res); - cpu->a = (uint8_t)res; -} - -static inline uint8_t _z80_inc8(z80_t* cpu, uint8_t val) { - uint8_t res = val + 1; - uint8_t f = _z80_sz_flags(res) | (res & (Z80_XF|Z80_YF)) | ((res ^ val) & Z80_HF); - if (res == 0x80) { - f |= Z80_VF; - } - cpu->f = f | (cpu->f & Z80_CF); - return res; -} - -static inline uint8_t _z80_dec8(z80_t* cpu, uint8_t val) { - uint8_t res = val - 1; - uint8_t f = Z80_NF | _z80_sz_flags(res) | (res & (Z80_XF|Z80_YF)) | ((res ^ val) & Z80_HF); - if (res == 0x7F) { - f |= Z80_VF; - } - cpu->f = f | (cpu->f & Z80_CF); - return res; -} - -static inline void _z80_ex_de_hl(z80_t* cpu) { - uint16_t tmp = cpu->hl; - cpu->hl = cpu->de; - cpu->de = tmp; -} - -static inline void _z80_ex_af_af2(z80_t* cpu) { - uint16_t tmp = cpu->af2; - cpu->af2 = cpu->af; - cpu->af = tmp; -} - -static inline void _z80_exx(z80_t* cpu) { - uint16_t tmp; - tmp = cpu->bc; cpu->bc = cpu->bc2; cpu->bc2 = tmp; - tmp = cpu->de; cpu->de = cpu->de2; cpu->de2 = tmp; - tmp = cpu->hl; cpu->hl = cpu->hl2; cpu->hl2 = tmp; -} - -static inline void _z80_rlca(z80_t* cpu) { - uint8_t res = (cpu->a << 1) | (cpu->a >> 7); - cpu->f = ((cpu->a >> 7) & Z80_CF) | (cpu->f & (Z80_SF|Z80_ZF|Z80_PF)) | (res & (Z80_YF|Z80_XF)); - cpu->a = res; -} - -static inline void _z80_rrca(z80_t* cpu) { - uint8_t res = (cpu->a >> 1) | (cpu->a << 7); - cpu->f = (cpu->a & Z80_CF) | (cpu->f & (Z80_SF|Z80_ZF|Z80_PF)) | (res & (Z80_YF|Z80_XF)); - cpu->a = res; -} - -static inline void _z80_rla(z80_t* cpu) { - uint8_t res = (cpu->a << 1) | (cpu->f & Z80_CF); - cpu->f = ((cpu->a >> 7) & Z80_CF) | (cpu->f & (Z80_SF|Z80_ZF|Z80_PF)) | (res & (Z80_YF|Z80_XF)); - cpu->a = res; -} - -static inline void _z80_rra(z80_t* cpu) { - uint8_t res = (cpu->a >> 1) | ((cpu->f & Z80_CF) << 7); - cpu->f = (cpu->a & Z80_CF) | (cpu->f & (Z80_SF|Z80_ZF|Z80_PF)) | (res & (Z80_YF|Z80_XF)); - cpu->a = res; -} - -static inline void _z80_daa(z80_t* cpu) { - uint8_t res = cpu->a; - if (cpu->f & Z80_NF) { - if (((cpu->a & 0xF)>0x9) || (cpu->f & Z80_HF)) { - res -= 0x06; - } - if ((cpu->a > 0x99) || (cpu->f & Z80_CF)) { - res -= 0x60; - } - } - else { - if (((cpu->a & 0xF)>0x9) || (cpu->f & Z80_HF)) { - res += 0x06; - } - if ((cpu->a > 0x99) || (cpu->f & Z80_CF)) { - res += 0x60; - } - } - cpu->f &= Z80_CF|Z80_NF; - cpu->f |= (cpu->a > 0x99) ? Z80_CF : 0; - cpu->f |= (cpu->a ^ res) & Z80_HF; - cpu->f |= _z80_szp_flags[res]; - cpu->a = res; -} - -static inline void _z80_cpl(z80_t* cpu) { - cpu->a ^= 0xFF; - cpu->f= (cpu->f & (Z80_SF|Z80_ZF|Z80_PF|Z80_CF)) |Z80_HF|Z80_NF| (cpu->a & (Z80_YF|Z80_XF)); -} - -static inline void _z80_scf(z80_t* cpu) { - cpu->f = (cpu->f & (Z80_SF|Z80_ZF|Z80_PF|Z80_CF)) | Z80_CF | (cpu->a & (Z80_YF|Z80_XF)); -} - -static inline void _z80_ccf(z80_t* cpu) { - cpu->f = ((cpu->f & (Z80_SF|Z80_ZF|Z80_PF|Z80_CF)) | ((cpu->f & Z80_CF)<<4) | (cpu->a & (Z80_YF|Z80_XF))) ^ Z80_CF; -} - -static inline void _z80_add16(z80_t* cpu, uint16_t val) { - const uint16_t acc = cpu->hlx[cpu->hlx_idx].hl; - cpu->wz = acc + 1; - const uint32_t res = acc + val; - cpu->hlx[cpu->hlx_idx].hl = res; - cpu->f = (cpu->f & (Z80_SF|Z80_ZF|Z80_VF)) | - (((acc ^ res ^ val)>>8)&Z80_HF) | - ((res >> 16) & Z80_CF) | - ((res >> 8) & (Z80_YF|Z80_XF)); -} - -static inline void _z80_adc16(z80_t* cpu, uint16_t val) { - // NOTE: adc is ED-prefixed, so they are never rewired to IX/IY - const uint16_t acc = cpu->hl; - cpu->wz = acc + 1; - const uint32_t res = acc + val + (cpu->f & Z80_CF); - cpu->hl = res; - cpu->f = (((val ^ acc ^ 0x8000) & (val ^ res) & 0x8000) >> 13) | - (((acc ^ res ^ val) >>8 ) & Z80_HF) | - ((res >> 16) & Z80_CF) | - ((res >> 8) & (Z80_SF|Z80_YF|Z80_XF)) | - ((res & 0xFFFF) ? 0 : Z80_ZF); -} - -static inline void _z80_sbc16(z80_t* cpu, uint16_t val) { - // NOTE: sbc is ED-prefixed, so they are never rewired to IX/IY - const uint16_t acc = cpu->hl; - cpu->wz = acc + 1; - const uint32_t res = acc - val - (cpu->f & Z80_CF); - cpu->hl = res; - cpu->f = (Z80_NF | (((val ^ acc) & (acc ^ res) & 0x8000) >> 13)) | - (((acc ^ res ^ val) >> 8) & Z80_HF) | - ((res >> 16) & Z80_CF) | - ((res >> 8) & (Z80_SF|Z80_YF|Z80_XF)) | - ((res & 0xFFFF) ? 0 : Z80_ZF); -} - -static inline bool _z80_ldi_ldd(z80_t* cpu, uint8_t val) { - const uint8_t res = cpu->a + val; - cpu->bc -= 1; - cpu->f = (cpu->f & (Z80_SF|Z80_ZF|Z80_CF)) | - ((res & 2) ? Z80_YF : 0) | - ((res & 8) ? Z80_XF : 0) | - (cpu->bc ? Z80_VF : 0); - return cpu->bc != 0; -} - -static inline bool _z80_cpi_cpd(z80_t* cpu, uint8_t val) { - uint32_t res = (uint32_t) ((int)cpu->a - (int)val); - cpu->bc -= 1; - uint8_t f = (cpu->f & Z80_CF)|Z80_NF|_z80_sz_flags(res); - if ((res & 0xF) > ((uint32_t)cpu->a & 0xF)) { - f |= Z80_HF; - res--; - } - if (res & 2) { f |= Z80_YF; } - if (res & 8) { f |= Z80_XF; } - if (cpu->bc) { f |= Z80_VF; } - cpu->f = f; - return (cpu->bc != 0) && !(f & Z80_ZF); -} - -static inline bool _z80_ini_ind(z80_t* cpu, uint8_t val, uint8_t c) { - const uint8_t b = cpu->b; - uint8_t f = _z80_sz_flags(b) | (b & (Z80_XF|Z80_YF)); - if (val & Z80_SF) { f |= Z80_NF; } - uint32_t t = (uint32_t)c + val; - if (t & 0x100) { f |= Z80_HF|Z80_CF; } - f |= _z80_szp_flags[((uint8_t)(t & 7)) ^ b] & Z80_PF; - cpu->f = f; - return (b != 0); -} - -static inline bool _z80_outi_outd(z80_t* cpu, uint8_t val) { - const uint8_t b = cpu->b; - uint8_t f = _z80_sz_flags(b) | (b & (Z80_XF|Z80_YF)); - if (val & Z80_SF) { f |= Z80_NF; } - uint32_t t = (uint32_t)cpu->l + val; - if (t & 0x0100) { f |= Z80_HF|Z80_CF; } - f |= _z80_szp_flags[((uint8_t)(t & 7)) ^ b] & Z80_PF; - cpu->f = f; - return (b != 0); -} - -static inline uint8_t _z80_in(z80_t* cpu, uint8_t val) { - cpu->f = (cpu->f & Z80_CF) | _z80_szp_flags[val]; - return val; -} - -static inline uint8_t _z80_rrd(z80_t* cpu, uint8_t val) { - const uint8_t l = cpu->a & 0x0F; - cpu->a = (cpu->a & 0xF0) | (val & 0x0F); - val = (val >> 4) | (l << 4); - cpu->f = (cpu->f & Z80_CF) | _z80_szp_flags[cpu->a]; - return val; -} - -static inline uint8_t _z80_rld(z80_t* cpu, uint8_t val) { - const uint8_t l = cpu->a & 0x0F; - cpu->a = (cpu->a & 0xF0) | (val >> 4); - val = (val << 4) | l; - cpu->f = (cpu->f & Z80_CF) | _z80_szp_flags[cpu->a]; - return val; -} - -static inline uint8_t _z80_rlc(z80_t* cpu, uint8_t val) { - uint8_t res = (val<<1) | (val>>7); - cpu->f = _z80_szp_flags[res] | ((val>>7) & Z80_CF); - return res; -} - -static inline uint8_t _z80_rrc(z80_t* cpu, uint8_t val) { - uint8_t res = (val>>1) | (val<<7); - cpu->f = _z80_szp_flags[res] | (val & Z80_CF); - return res; -} - -static inline uint8_t _z80_rl(z80_t* cpu, uint8_t val) { - uint8_t res = (val<<1) | (cpu->f & Z80_CF); - cpu->f = _z80_szp_flags[res] | ((val>>7) & Z80_CF); - return res; -} - -static inline uint8_t _z80_rr(z80_t* cpu, uint8_t val) { - uint8_t res = (val>>1) | ((cpu->f & Z80_CF)<<7); - cpu->f = _z80_szp_flags[res] | (val & Z80_CF); - return res; -} - -static inline uint8_t _z80_sla(z80_t* cpu, uint8_t val) { - uint8_t res = val<<1; - cpu->f = _z80_szp_flags[res] | ((val>>7) & Z80_CF); - return res; -} - -static inline uint8_t _z80_sra(z80_t* cpu, uint8_t val) { - uint8_t res = (val>>1) | (val & 0x80); - cpu->f = _z80_szp_flags[res] | (val & Z80_CF); - return res; -} - -static inline uint8_t _z80_sll(z80_t* cpu, uint8_t val) { - uint8_t res = (val<<1) | 1; - cpu->f = _z80_szp_flags[res] | ((val>>7) & Z80_CF); - return res; -} - -static inline uint8_t _z80_srl(z80_t* cpu, uint8_t val) { - uint8_t res = val>>1; - cpu->f = _z80_szp_flags[res] | (val & Z80_CF); - return res; -} - -static inline uint64_t _z80_set_ab(uint64_t pins, uint16_t ab) { - return (pins & ~0xFFFF) | ab; -} - -static inline uint64_t _z80_set_ab_x(uint64_t pins, uint16_t ab, uint64_t x) { - return (pins & ~0xFFFF) | ab | x; -} - -static inline uint64_t _z80_set_ab_db(uint64_t pins, uint16_t ab, uint8_t db) { - return (pins & ~0xFFFFFF) | (db<<16) | ab; -} - -static inline uint64_t _z80_set_ab_db_x(uint64_t pins, uint16_t ab, uint8_t db, uint64_t x) { - return (pins & ~0xFFFFFF) | (db<<16) | ab | x; -} - -static inline uint8_t _z80_get_db(uint64_t pins) { - return (uint8_t)(pins>>16); -} - -// CB-prefix block action -static inline bool _z80_cb_action(z80_t* cpu, uint8_t z0, uint8_t z1) { - const uint8_t x = cpu->opcode>>6; - const uint8_t y = (cpu->opcode>>3)&7; - uint8_t val, res; - switch (z0) { - case 0: val = cpu->b; break; - case 1: val = cpu->c; break; - case 2: val = cpu->d; break; - case 3: val = cpu->e; break; - case 4: val = cpu->h; break; - case 5: val = cpu->l; break; - case 6: val = cpu->dlatch; break; // (HL) - case 7: val = cpu->a; break; - default: _Z80_UNREACHABLE; - } - switch (x) { - case 0: // rot/shift - switch (y) { - case 0: res = _z80_rlc(cpu, val); break; - case 1: res = _z80_rrc(cpu, val); break; - case 2: res = _z80_rl(cpu, val); break; - case 3: res = _z80_rr(cpu, val); break; - case 4: res = _z80_sla(cpu, val); break; - case 5: res = _z80_sra(cpu, val); break; - case 6: res = _z80_sll(cpu, val); break; - case 7: res = _z80_srl(cpu, val); break; - default: _Z80_UNREACHABLE; - } - break; - case 1: // bit - res = val & (1<f = (cpu->f & Z80_CF) | Z80_HF | (res ? (res & Z80_SF) : (Z80_ZF|Z80_PF)); - if (z0 == 6) { - cpu->f |= (cpu->wz >> 8) & (Z80_YF|Z80_XF); - } - else { - cpu->f |= val & (Z80_YF|Z80_XF); - } - break; - case 2: // res - res = val & ~(1 << y); - break; - case 3: // set - res = val | (1 << y); - break; - default: _Z80_UNREACHABLE; - } - // don't write result back for BIT - if (x != 1) { - cpu->dlatch = res; - switch (z1) { - case 0: cpu->b = res; break; - case 1: cpu->c = res; break; - case 2: cpu->d = res; break; - case 3: cpu->e = res; break; - case 4: cpu->h = res; break; - case 5: cpu->l = res; break; - case 6: break; // (HL) - case 7: cpu->a = res; break; - default: _Z80_UNREACHABLE; - } - return true; - } - else { - return false; - } -} - -// compute the effective memory address for DD+CB/FD+CB instructions -static inline void _z80_ddfdcb_addr(z80_t* cpu, uint64_t pins) { - uint8_t d = _z80_get_db(pins); - cpu->addr = cpu->hlx[cpu->hlx_idx].hl + (int8_t)d; - cpu->wz = cpu->addr; -} - -// special case opstate table slots -#define _Z80_OPSTATE_SLOT_CB (0) -#define _Z80_OPSTATE_SLOT_CBHL (1) -#define _Z80_OPSTATE_SLOT_DDFDCB (2) -#define _Z80_OPSTATE_SLOT_INT_IM0 (3) -#define _Z80_OPSTATE_SLOT_INT_IM1 (4) -#define _Z80_OPSTATE_SLOT_INT_IM2 (5) -#define _Z80_OPSTATE_SLOT_NMI (6) -#define _Z80_OPSTATE_NUM_SPECIAL_OPS (7) - -#define _Z80_OPSTATE_STEP_INDIRECT (5) // see case-branch '6' -#define _Z80_OPSTATE_STEP_INDIRECT_IMM8 (13) // see case-branch '14' - -static const uint16_t _z80_optable[256] = { -$optable }; - -static const uint16_t _z80_ddfd_optable[256] = { -$ddfd_optable }; - -static const uint16_t _z80_ed_optable[256] = { -$ed_optable }; - -static const uint16_t _z80_special_optable[_Z80_OPSTATE_NUM_SPECIAL_OPS] = { -$special_optable }; - -// initiate refresh cycle -static inline uint64_t _z80_refresh(z80_t* cpu, uint64_t pins) { - pins = _z80_set_ab_x(pins, cpu->ir, Z80_MREQ|Z80_RFSH); - cpu->r = (cpu->r & 0x80) | ((cpu->r + 1) & 0x7F); - return pins; -} - -// initiate a fetch machine cycle for regular (non-prefixed) instructions, or initiate interrupt handling -static inline uint64_t _z80_fetch(z80_t* cpu, uint64_t pins) { - cpu->hlx_idx = 0; - cpu->prefix_active = false; - // shortcut no interrupts requested - if (cpu->int_bits == 0) { - cpu->step = 0xFFFF; - return _z80_set_ab_x(pins, cpu->pc++, Z80_M1|Z80_MREQ|Z80_RD); - } - else if (cpu->int_bits & Z80_NMI) { - // non-maskable interrupt starts with a regular M1 machine cycle - cpu->step = _z80_special_optable[_Z80_OPSTATE_SLOT_NMI]; - cpu->int_bits = 0; - if (pins & Z80_HALT) { - pins &= ~Z80_HALT; - cpu->pc++; - } - // NOTE: PC is *not* incremented! - return _z80_set_ab_x(pins, cpu->pc, Z80_M1|Z80_MREQ|Z80_RD); - } - else if (cpu->int_bits & Z80_INT) { - if (cpu->iff1) { - // maskable interrupts start with a special M1 machine cycle which - // doesn't fetch the next opcode, but instead activate the - // pins M1|IOQR to request a special byte which is handled differently - // depending on interrupt mode - cpu->step = _z80_special_optable[_Z80_OPSTATE_SLOT_INT_IM0 + cpu->im]; - cpu->int_bits = 0; - if (pins & Z80_HALT) { - pins &= ~Z80_HALT; - cpu->pc++; - } - // NOTE: PC is not incremented, and no pins are activated here - return pins; - } - else { - // oops, maskable interrupt requested but disabled - cpu->step = 0xFFFF; - return _z80_set_ab_x(pins, cpu->pc++, Z80_M1|Z80_MREQ|Z80_RD); - } - } - else { - _Z80_UNREACHABLE; - return pins; - } -} - -static inline uint64_t _z80_fetch_cb(z80_t* cpu, uint64_t pins) { - cpu->prefix_active = true; - if (cpu->hlx_idx > 0) { - // this is a DD+CB / FD+CB instruction, continue - // execution on the special DDCB/FDCB decoder block which - // loads the d-offset first and then the opcode in a - // regular memory read machine cycle - cpu->step = _z80_special_optable[_Z80_OPSTATE_SLOT_DDFDCB]; - } - else { - // this is a regular CB-prefixed instruction, continue - // execution on a special fetch machine cycle which doesn't - // handle DD/FD prefix and then branches either to the - // special CB or CBHL decoder block - cpu->step = 21; // => step 22: opcode fetch for CB prefixed instructions - pins = _z80_set_ab_x(pins, cpu->pc++, Z80_M1|Z80_MREQ|Z80_RD); - } - return pins; -} - -static inline uint64_t _z80_fetch_dd(z80_t* cpu, uint64_t pins) { - cpu->step = 2; // => step 3: opcode fetch for DD/FD prefixed instructions - cpu->hlx_idx = 1; - cpu->prefix_active = true; - return _z80_set_ab_x(pins, cpu->pc++, Z80_M1|Z80_MREQ|Z80_RD); -} - -static inline uint64_t _z80_fetch_fd(z80_t* cpu, uint64_t pins) { - cpu->step = 2; // => step 3: opcode fetch for DD/FD prefixed instructions - cpu->hlx_idx = 2; - cpu->prefix_active = true; - return _z80_set_ab_x(pins, cpu->pc++, Z80_M1|Z80_MREQ|Z80_RD); -} - -static inline uint64_t _z80_fetch_ed(z80_t* cpu, uint64_t pins) { - cpu->step = 24; // => step 25: opcode fetch for ED prefixed instructions - cpu->hlx_idx = 0; - cpu->prefix_active = true; - return _z80_set_ab_x(pins, cpu->pc++, Z80_M1|Z80_MREQ|Z80_RD); -} - -uint64_t z80_prefetch(z80_t* cpu, uint16_t new_pc) { - cpu->pc = new_pc; - // overlapped M1:T1 of the NOP instruction to initiate opcode fetch at new pc - cpu->step = _z80_optable[0] + 1; - return 0; -} - -// pin helper macros -#define _sa(ab) pins=_z80_set_ab(pins,ab) -#define _sax(ab,x) pins=_z80_set_ab_x(pins,ab,x) -#define _sad(ab,d) pins=_z80_set_ab_db(pins,ab,d) -#define _sadx(ab,d,x) pins=_z80_set_ab_db_x(pins,ab,d,x) -#define _gd() _z80_get_db(pins) - -// high level helper macros -#define _skip(n) cpu->step+=(n); -#define _fetch_dd() pins=_z80_fetch_dd(cpu,pins); -#define _fetch_fd() pins=_z80_fetch_fd(cpu,pins); -#define _fetch_ed() pins=_z80_fetch_ed(cpu,pins); -#define _fetch_cb() pins=_z80_fetch_cb(cpu,pins); -#define _mread(ab) _sax(ab,Z80_MREQ|Z80_RD) -#define _mwrite(ab,d) _sadx(ab,d,Z80_MREQ|Z80_WR) -#define _ioread(ab) _sax(ab,Z80_IORQ|Z80_RD) -#define _iowrite(ab,d) _sadx(ab,d,Z80_IORQ|Z80_WR) -#define _wait() {if(pins&Z80_WAIT)goto track_int_bits;} -#define _cc_nz (!(cpu->f&Z80_ZF)) -#define _cc_z (cpu->f&Z80_ZF) -#define _cc_nc (!(cpu->f&Z80_CF)) -#define _cc_c (cpu->f&Z80_CF) -#define _cc_po (!(cpu->f&Z80_PF)) -#define _cc_pe (cpu->f&Z80_PF) -#define _cc_p (!(cpu->f&Z80_SF)) -#define _cc_m (cpu->f&Z80_SF) - -uint64_t z80_tick(z80_t* cpu, uint64_t pins) { - pins &= ~(Z80_CTRL_PIN_MASK|Z80_RETI); - switch (cpu->step) { - //=== shared fetch machine cycle for non-DD/FD-prefixed ops - // M1/T2: load opcode from data bus - case 0: _wait(); cpu->opcode = _gd(); goto step_next; - // M1/T3: refresh cycle - case 1: pins = _z80_refresh(cpu, pins); goto step_next; - // M1/T4: branch to instruction 'payload' - case 2: { - cpu->step = _z80_optable[cpu->opcode]; - // preload effective address for (HL) ops - cpu->addr = cpu->hl; - } goto step_next; - //=== shared fetch machine cycle for DD/FD-prefixed ops - // M1/T2: load opcode from data bus - case 3: _wait(); cpu->opcode = _gd(); goto step_next; - // M1/T3: refresh cycle - case 4: pins = _z80_refresh(cpu, pins); goto step_next; - // M1/T4: branch to instruction 'payload' - case 5: { - cpu->step = _z80_ddfd_optable[cpu->opcode]; - cpu->addr = cpu->hlx[cpu->hlx_idx].hl; - } goto step_next; - //=== optional d-loading cycle for (IX+d), (IY+d) - //--- mread - case 6: goto step_next; - case 7: _wait();_mread(cpu->pc++); goto step_next; - case 8: cpu->addr += (int8_t)_gd(); cpu->wz = cpu->addr; goto step_next; - //--- filler ticks - case 9: goto step_next; - case 10: goto step_next; - case 11: goto step_next; - case 12: goto step_next; - case 13: { - // branch to actual instruction - cpu->step = _z80_optable[cpu->opcode]; - } goto step_next; - //=== special case d-loading cycle for (IX+d),n where the immediate load - // is hidden in the d-cycle load - //--- mread for d offset - case 14: goto step_next; - case 15: _wait();_mread(cpu->pc++); goto step_next; - case 16: cpu->addr += (int8_t)_gd(); cpu->wz = cpu->addr; goto step_next; - //--- mread for n - case 17: goto step_next; - case 18: _wait();_mread(cpu->pc++); goto step_next; - case 19: cpu->dlatch=_gd(); goto step_next; - //--- filler tick - case 20: goto step_next; - case 21: { - // branch to ld (hl),n and skip the original mread cycle for loading 'n' - cpu->step = _z80_optable[cpu->opcode] + 3; - } goto step_next; - //=== special opcode fetch machine cycle for CB-prefixed instructions - case 22: _wait(); cpu->opcode = _gd(); goto step_next; - case 23: pins = _z80_refresh(cpu, pins); goto step_next; - case 24: { - if ((cpu->opcode & 7) == 6) { - // this is a (HL) instruction - cpu->addr = cpu->hl; - cpu->step = _z80_special_optable[_Z80_OPSTATE_SLOT_CBHL]; - } - else { - cpu->step = _z80_special_optable[_Z80_OPSTATE_SLOT_CB]; - } - } goto step_next; - //=== special opcode fetch machine cycle for ED-prefixed instructions - // M1/T2: load opcode from data bus - case 25: _wait(); cpu->opcode = _gd(); goto step_next; - // M1/T3: refresh cycle - case 26: pins = _z80_refresh(cpu, pins); goto step_next; - // M1/T4: branch to instruction 'payload' - case 27: cpu->step = _z80_ed_optable[cpu->opcode]; goto step_next; - //=== from here on code-generated -$decode_block - default: _Z80_UNREACHABLE; - } -fetch_next: pins = _z80_fetch(cpu, pins); -step_next: cpu->step += 1; -track_int_bits: { - // track NMI 0 => 1 edge and current INT pin state, this will track the - // relevant interrupt status up to the last instruction cycle and will - // be checked in the first M1 cycle (during _fetch) - const uint64_t rising_nmi = (pins ^ cpu->pins) & pins; // NMI 0 => 1 - cpu->pins = pins; - cpu->int_bits = ((cpu->int_bits | rising_nmi) & Z80_NMI) | (pins & Z80_INT); - } - return pins; -} - -#undef _sa -#undef _sax -#undef _sad -#undef _sadx -#undef _gd -#undef _skip -#undef _fetch_dd -#undef _fetch_fd -#undef _fetch_ed -#undef _fetch_cb -#undef _mread -#undef _mwrite -#undef _ioread -#undef _iowrite -#undef _wait -#undef _cc_nz -#undef _cc_z -#undef _cc_nc -#undef _cc_c -#undef _cc_po -#undef _cc_pe -#undef _cc_p -#undef _cc_m - -#endif // CHIPS_IMPL diff --git a/codegen/z80_desc.yml b/codegen/z80_desc.yml index 7cd91f69..afb0642d 100644 --- a/codegen/z80_desc.yml +++ b/codegen/z80_desc.yml @@ -52,7 +52,7 @@ DJNZ d: cond: (x == 0) and (y == 2) and (z == 0) mcycles: - { type: generic, tcycles: 1 } - - { type: mread, ab: $PC++, dst: $DLATCH, action: "if(--$B==0){_skip(5);}"} + - { type: mread, ab: $PC++, dst: $DLATCH, action: "if(--$B==0){_goto($NEXTSTEP+5);}"} - { type: generic, tcycles: 5, action: "$PC+=(int8_t)$DLATCH;$WZ=$PC" } JR d: @@ -64,7 +64,7 @@ JR d: JR $CC-4,d: cond: (x == 0) and (y >= 4) and (y <= 7) and (z == 0) mcycles: - - { type: mread, ab: $PC++, dst: $DLATCH, action: "if(!($CC-4)){_skip(5);}" } + - { type: mread, ab: $PC++, dst: $DLATCH, action: "if(!($CC-4)){_goto($NEXTSTEP+5);}" } - { type: generic, tcycles: 5, action: "$PC+=(int8_t)$DLATCH;$WZ=$PC" } # 16-bit load immediate/add @@ -227,7 +227,7 @@ CCF: RET $CC: cond: (x == 3) and (z == 0) mcycles: - - { type: generic, tcycles: 1, action: "if(!$CC){_skip(6);}"} + - { type: generic, tcycles: 1, action: "if(!$CC){_goto($NEXTSTEP+6);}"} - { type: mread, ab: $SP++, dst: $WZL } - { type: mread, ab: $SP++, dst: $WZH, action: "$PC=$WZ" } @@ -323,7 +323,7 @@ CALL $CC,nn: cond: (x == 3) and (z == 4) mcycles: - { type: mread, ab: $PC++, dst: $WZL } - - { type: mread, ab: $PC++, dst: $WZH, action: "if (!$CC){_skip(7);}" } + - { type: mread, ab: $PC++, dst: $WZH, action: "if (!$CC){_goto($NEXTSTEP+7);}" } - { type: generic, tcycles: 1 } - { type: mwrite, ab: --$SP, db: $PCH } - { type: mwrite, ab: --$SP, db: $PCL, action: "$PC=$WZ" } @@ -377,7 +377,7 @@ RST $Y*8: #== ED prefix block ============================================================ ED NOP: prefix: ed - flags: { single: true } + flags: { multiple: true } cond: (x == 0) or (x == 3) or ((x == 1) and (z == 7) and (y >= 6)) or ((x == 2) and ((z > 3) or (y < 4))) mcycles: [] @@ -441,14 +441,14 @@ LD $RP,(nn): NEG: prefix: ed cond: (x == 1) and (z == 4) - flags: { single: true } + flags: { multiple: true } mcycles: - { type: overlapped, action: "_z80_neg8(cpu)"} RETI: prefix: ed cond: (x == 1) and (y != 0) and (z == 5) - flags: { single: true } + flags: { multiple: true } mcycles: # virtual RETI pin must be set as early as possible - { type: mread, ab: $SP++, dst: $WZL, action: "pins|=Z80_RETI" } @@ -537,7 +537,7 @@ LDIR: mcycles: - { type: mread, ab: "cpu->hl++", dst: $DLATCH } - { type: mwrite, ab: "cpu->de++", db: $DLATCH } - - { type: generic, tcycles: 2, action: "if(!_z80_ldi_ldd(cpu,$DLATCH)){_skip(5);}"} + - { type: generic, tcycles: 2, action: "if(!_z80_ldi_ldd(cpu,$DLATCH)){_goto($NEXTSTEP+5);}"} - { type: generic, tcycles: 5, action: "$WZ=--$PC;--$PC;" } LDDR: @@ -546,7 +546,7 @@ LDDR: mcycles: - { type: mread, ab: "cpu->hl--", dst: $DLATCH } - { type: mwrite, ab: "cpu->de--", db: $DLATCH } - - { type: generic, tcycles: 2, action: "if(!_z80_ldi_ldd(cpu,$DLATCH)){_skip(5);}"} + - { type: generic, tcycles: 2, action: "if(!_z80_ldi_ldd(cpu,$DLATCH)){_goto($NEXTSTEP+5);}"} - { type: generic, tcycles: 5, action: "$WZ=--$PC;--$PC;" } CPI: @@ -568,7 +568,7 @@ CPIR: cond: (x == 2) and (y == 6) and (z == 1) mcycles: - { type: mread, ab: "cpu->hl++", dst: $DLATCH } - - { type: generic, tcycles: 5, action: "$WZ++;if(!_z80_cpi_cpd(cpu,$DLATCH)){_skip(5);}"} + - { type: generic, tcycles: 5, action: "$WZ++;if(!_z80_cpi_cpd(cpu,$DLATCH)){_goto($NEXTSTEP+5);}"} - { type: generic, tcycles: 5, action: "$WZ=--$PC;--$PC"} CPDR: @@ -576,7 +576,7 @@ CPDR: cond: (x == 2) and (y == 7) and (z == 1) mcycles: - { type: mread, ab: "cpu->hl--", dst: $DLATCH } - - { type: generic, tcycles: 5, action: "$WZ--;if(!_z80_cpi_cpd(cpu,$DLATCH)){_skip(5);}"} + - { type: generic, tcycles: 5, action: "$WZ--;if(!_z80_cpi_cpd(cpu,$DLATCH)){_goto($NEXTSTEP+5);}"} - { type: generic, tcycles: 5, action: "$WZ=--$PC;--$PC"} INI: @@ -601,7 +601,7 @@ INIR: mcycles: - { type: generic, tcycles: 1 } - { type: ioread, ab: $BC, dst: $DLATCH, action: "$WZ=$BC+1;$B--;" } - - { type: mwrite, ab: "cpu->hl++", db: $DLATCH, action: "if (!_z80_ini_ind(cpu,$DLATCH,$C+1)){_skip(5);}" } + - { type: mwrite, ab: "cpu->hl++", db: $DLATCH, action: "if (!_z80_ini_ind(cpu,$DLATCH,$C+1)){_goto($NEXTSTEP+5);}" } - { type: generic, tcycles: 5, action: "$WZ=--$PC;--$PC"} INDR: @@ -610,7 +610,7 @@ INDR: mcycles: - { type: generic, tcycles: 1 } - { type: ioread, ab: $BC, dst: $DLATCH, action: "$WZ=$BC-1;$B--;" } - - { type: mwrite, ab: "cpu->hl--", db: $DLATCH, action: "if (!_z80_ini_ind(cpu,$DLATCH,$C-1)){_skip(5);}" } + - { type: mwrite, ab: "cpu->hl--", db: $DLATCH, action: "if (!_z80_ini_ind(cpu,$DLATCH,$C-1)){_goto($NEXTSTEP+5);}" } - { type: generic, tcycles: 5, action: "$WZ=--$PC;--$PC"} OUTI: @@ -635,7 +635,7 @@ OTIR: mcycles: - { type: generic, tcycles: 1 } - { type: mread, ab: "cpu->hl++", dst: $DLATCH, action: "$B--" } - - { type: iowrite, ab: $BC, db: $DLATCH, action: "$WZ=$BC+1;if(!_z80_outi_outd(cpu,$DLATCH)){_skip(5);}"} + - { type: iowrite, ab: $BC, db: $DLATCH, action: "$WZ=$BC+1;if(!_z80_outi_outd(cpu,$DLATCH)){_goto($NEXTSTEP+5);}"} - { type: generic, tcycles: 5, action: "$WZ=--$PC;--$PC"} OTDR: @@ -644,7 +644,7 @@ OTDR: mcycles: - { type: generic, tcycles: 1 } - { type: mread, ab: "cpu->hl--", dst: $DLATCH, action: "$B--" } - - { type: iowrite, ab: $BC, db: $DLATCH, action: "$WZ=$BC-1;if(!_z80_outi_outd(cpu,$DLATCH)){_skip(5);}"} + - { type: iowrite, ab: $BC, db: $DLATCH, action: "$WZ=$BC-1;if(!_z80_outi_outd(cpu,$DLATCH)){_goto($NEXTSTEP+5);}"} - { type: generic, tcycles: 5, action: "$WZ=--$PC;--$PC"} #== CB prefix block ============================================================ @@ -657,7 +657,7 @@ cb: cbhl: flags: { special: true } mcycles: - - { type: mread, tcycles: 4, ab: "cpu->hl", dst: $DLATCH, action: "if(!_z80_cb_action(cpu,6,6)){_skip(3);}" } + - { type: mread, tcycles: 4, ab: "cpu->hl", dst: $DLATCH, action: "if(!_z80_cb_action(cpu,6,6)){_goto($NEXTSTEP+3);}" } - { type: mwrite, ab: "cpu->hl", db: $DLATCH } ddfdcb: @@ -669,7 +669,7 @@ ddfdcb: # load opcode - { type: mread, ab: $PC++, tcycles: 5, dst: "cpu->opcode"} # read operand - - { type: mread, ab: $ADDR, tcycles: 4, dst: $DLATCH, action: "if(!_z80_cb_action(cpu,6,cpu->opcode&7)){_skip(3);}" } + - { type: mread, ab: $ADDR, tcycles: 4, dst: $DLATCH, action: "if(!_z80_cb_action(cpu,6,cpu->opcode&7)){_goto($NEXTSTEP+3);}" } # write result back - { type: mwrite, ab: $ADDR, db: $DLATCH } @@ -685,7 +685,7 @@ int_im0: - { type: generic, tcycles: 1, action: "_wait();cpu->opcode=_z80_get_db(pins)" } # combined refresh and branch to loaded instruction cycle - { type: generic, tcycles: 1, action: "pins=_z80_refresh(cpu,pins)" } - - { type: generic, tcycles: 1, action: "cpu->step=_z80_optable[cpu->opcode]; cpu->addr=cpu->hl" } + - { type: generic, tcycles: 1, action: "cpu->addr=cpu->hl;_goto(cpu->opcode)" } int_im1: flags: { special: true } diff --git a/codegen/z80_gen.py b/codegen/z80_gen.py index d6ae1a62..32eb20b5 100644 --- a/codegen/z80_gen.py +++ b/codegen/z80_gen.py @@ -1,10 +1,8 @@ import yaml, copy -from string import Template +import templ -FIRST_DECODER_STEP = 28 DESC_PATH = 'z80_desc.yml' -TEMPL_PATH = 'z80.template.h' -OUT_PATH = '../chips/z80.h' +INOUT_PATH = '../chips/z80.h' TAB_WIDTH = 4 # a machine cycle description @@ -23,29 +21,16 @@ def __init__(self, name, cond, flags): self.flags = flags self.opcode = -1 self.prefix = '' - self.single = False - self.num_cycles = 0 - self.num_steps = 0 - self.decoder_offset = 0 - self.first_op_index = -1 + self.multiple = False + self.multiple_first_op_index = -1 + self.step_index = -1 + self.extra_step_index = -1 self.mcycles = [] -OP_PATTERNS = [] - -OP_INDEX_CB = 512 -OP_INDEX_CBHL = 513 -OP_INDEX_DDFDCB = 514 -OP_INDEX_INT_IM0 = 515 -OP_INDEX_INT_IM1 = 516 -OP_INDEX_INT_IM2 = 517 -OP_INDEX_NMI = 518 +OP_DESCS = [] NUM_SPECIAL_OPS = 7 -# 0..255: core opcodes -# 256..511: ED prefix opcodes -# 512..514: special decoder blocks for CB-prefix -# 515..519: special decoder blocks for interrupt handling OPS = [None for _ in range(0,2*256 + NUM_SPECIAL_OPS)] # a fetch machine cycle is processed as 2 parts because it overlaps @@ -75,8 +60,8 @@ def __init__(self, name, cond, flags): rp2l_map = [ 'cpu->c', 'cpu->e', 'cpu->hlx[cpu->hlx_idx].l', 'cpu->f'] rp2h_map = [ 'cpu->b', 'cpu->d', 'cpu->hlx[cpu->hlx_idx].h', 'cpu->a'] cc_map = [ '_cc_nz', '_cc_z', '_cc_nc', '_cc_c', '_cc_po', '_cc_pe', '_cc_p', '_cc_m' ] -alu_map = [ '_z80_add8(cpu,', - '_z80_adc8(cpu,', +alu_map = [ '_z80_add8(cpu,', + '_z80_adc8(cpu,', '_z80_sub8(cpu,', '_z80_sbc8(cpu,', '_z80_and8(cpu,', @@ -96,22 +81,6 @@ def __init__(self, name, cond, flags): def err(msg: str): raise BaseException(msg) -def unwrap(maybe_value): - if maybe_value is None: - err('Expected valid value, found None') - return maybe_value - -# append a source code line -indent = 0 -out_lines = '' - -def tab(): - return ' ' * TAB_WIDTH * indent - -def l(s) : - global out_lines - out_lines += tab() + s + '\n' - def map_comment(inp, y, z, p, q): return inp\ .replace('$RY', r_comment[y])\ @@ -226,12 +195,20 @@ def parse_opdescs(): op.mcycles.insert(0, MCycle('fetch', FETCH_TCYCLES, {})) if num_overlapped == 0: op.mcycles.append(MCycle('overlapped', OVERLAPPED_FETCH_TCYCLES, {})) - OP_PATTERNS.append(op) + OP_DESCS.append(op) def find_opdesc(name): - for op_desc in OP_PATTERNS: + for op_desc in OP_DESCS: if op_desc.name == name: return op_desc + err(f"opdesc not found for '{name}'") + return None + +def find_op(name): + for op in OPS: + if op.name == name: + return op + err(f"op not found for '{name}'") return None def stampout_mcycle_items(mcycle_items, y, z, p, q): @@ -249,12 +226,14 @@ def stampout_op(prefix, opcode, op_index, op_desc): z = opcode & 7 p = y >> 1 q = y & 1 - if op_desc.first_op_index == -1: - op_desc.first_op_index = op_index + if op_desc.multiple_first_op_index == -1: + op_desc.multiple_first_op_index = op_index op = copy.deepcopy(op_desc) op.name = map_comment(op.name, y, z, p, q) op.prefix = prefix op.opcode = opcode + if flag(op, 'multiple') and op.multiple_first_op_index != op_index: + op.flags['redundant'] = True for mcycle in op.mcycles: mcycle.items = stampout_mcycle_items(mcycle.items, y, z, p, q) OPS[op_index] = op @@ -263,79 +242,102 @@ def expand_optable(): for oprange,prefix in enumerate(['', 'ed']): for opcode in range(0,256): x = opcode >> 6 # type: ignore (generated unused warning, but x is needed in 'eval') - y = (opcode >> 3) & 7 + y = (opcode >> 3) & 7 z = opcode & 7 # type: ignore p = y >> 1 # type: ignore q = y & 1 # type: ignore op_index = oprange * 256 + opcode - for op_desc_index,op_desc in enumerate(OP_PATTERNS): + for op_desc_index,op_desc in enumerate(OP_DESCS): if not flag(op_desc, 'special'): if eval(op_desc.cond_compiled) and op_desc.prefix == prefix: if OPS[op_index] is not None: err(f"Condition collission for opcode {op_desc_index:02X} and '{op_desc.name}'") stampout_op(prefix, opcode, op_index, op_desc) - stampout_op('cb', 0, OP_INDEX_CB, unwrap(find_opdesc('cb'))) - stampout_op('cb', 0, OP_INDEX_CBHL, unwrap(find_opdesc('cbhl'))) - stampout_op('cb', 0, OP_INDEX_DDFDCB, unwrap(find_opdesc('ddfdcb'))) - stampout_op('', 0, OP_INDEX_INT_IM0, unwrap(find_opdesc('int_im0'))) - stampout_op('', 0, OP_INDEX_INT_IM1, unwrap(find_opdesc('int_im1'))) - stampout_op('', 0, OP_INDEX_INT_IM2, unwrap(find_opdesc('int_im2'))) - stampout_op('', 0, OP_INDEX_NMI, unwrap(find_opdesc('nmi'))) - -# compute number of tcycles in an instruction -def compute_tcycles(op): - cycles = 0 - for mcycle in op.mcycles: - cycles += mcycle.tcycles - return cycles + op_index += 1; stampout_op('cb', -1, op_index, find_opdesc('cb')) + op_index += 1; stampout_op('cb', -1, op_index, find_opdesc('cbhl')) + op_index += 1; stampout_op('cb', -1, op_index, find_opdesc('ddfdcb')) + op_index += 1; stampout_op('', -1, op_index, find_opdesc('int_im0')) + op_index += 1; stampout_op('', -1, op_index, find_opdesc('int_im1')) + op_index += 1; stampout_op('', -1, op_index, find_opdesc('int_im2')) + op_index += 1; stampout_op('', -1, op_index, find_opdesc('nmi')) # generate code for one op def gen_decoder(): - global indent indent = 2 - decoder_step = FIRST_DECODER_STEP + cur_step = 0 + cur_extra_step = 512 # main and ed ops + out_lines = '' + out_extra_lines = '' + + def tab(): + return ' ' * TAB_WIDTH * indent + + def l(s): + nonlocal out_lines + out_lines += tab() + s + '\n' + + def lx(s): + nonlocal out_extra_lines + out_extra_lines += tab() + s + '\n' def add(action): - nonlocal decoder_step - nonlocal step - l(f'case {decoder_step:4}: {action}goto step_next;') - decoder_step += 1 - step += 1 - + nonlocal cur_step, cur_extra_step, op_step, op + # NOTE: special ops (interrupt handling etc) are entirely written into the 'extra' decoder block + if op_step == 0 and not flag(op, 'special'): + next_step = cur_extra_step + # check if this is a redundant op which needs to step to a shared payload + if flag(op, 'redundant'): + next_step = OPS[op.multiple_first_op_index].extra_step_index + action = action.replace("$NEXTSTEP", f'{next_step}') + l(f'case {cur_step:4}: {action}_goto({next_step}); // {op.name} ({op_step})') + cur_step += 1 + else: + # do not write a payload for redundant ops + if not flag(op, 'redundant'): + next_step = cur_extra_step + 1 + action = action.replace("$NEXTSTEP", f'{next_step}') + lx(f'case {cur_extra_step:4}: {action}_goto({next_step}); // {op.name} ({op_step})') + cur_extra_step += 1 + op_step += 1 + def add_fetch(action): - nonlocal decoder_step - nonlocal step - l(f'case {decoder_step:4}: {action}goto fetch_next;') - decoder_step += 1 - step += 1 - - for op_index,maybe_op in enumerate(OPS): - op = unwrap(maybe_op) - # ignore duplicate ops if they are flagged as 'single' - if flag(op, 'single') and op.first_op_index != op_index: - continue - - step = 0 - op.num_cycles = compute_tcycles(op) - op.decoder_offset = decoder_step - - l('') - l(f'// {op.prefix.upper()} {op.opcode:02X}: {op.name} (M:{len(op.mcycles)-1} T:{op.num_cycles})') + nonlocal cur_step, cur_extra_step, op_step, op + if op_step == 0 and not flag(op, 'special'): + l(f'case {cur_step:4}: {action}_fetch(); // {op.name} ({op_step})') + cur_step += 1 + else: + lx(f'case {cur_extra_step:4}: {action}_fetch(); // {op.name} ({op_step})') + cur_extra_step += 1 + op_step += 1 + + def add_stepto(action): + nonlocal cur_step, cur_extra_step, op_step, op + if op_step == 0: + l(f'case {cur_step:4}: {action}goto step_to; // {op.name} ({op_step})') + cur_step += 1 + else: + lx(f'case {cur_extra_step:4}: {action}goto step_to; // {op.name} ({op_step})') + cur_extra_step += 1 + op_step += 1 + + for op in OPS: + op_step = 0 + op.step_index = cur_step + op.extra_step_index = cur_extra_step + for i,mcycle in enumerate(op.mcycles): action = (f"{mcycle.items['action']};" if 'action' in mcycle.items else '') if mcycle.type == 'fetch': pass elif mcycle.type == 'mread': - l(f'// -- mread') addr = mcycle.items['ab'] - store = mcycle.items['dst'].replace('_X_', '_gd()') + store = mcycle.items['dst'] add('') add(f'_wait();_mread({addr});') add(f'{store}=_gd();{action}') for _ in range(3,mcycle.tcycles): add('') elif mcycle.type == 'mwrite': - l(f'// -- mwrite') addr = mcycle.items['ab'] data = mcycle.items['db'] add('') @@ -344,9 +346,8 @@ def add_fetch(action): for _ in range(3,mcycle.tcycles): add('') elif mcycle.type == 'ioread': - l(f'// -- ioread') addr = mcycle.items['ab'] - store = mcycle.items['dst'].replace('_X_', '_gd()') + store = mcycle.items['dst'] add('') add('') add(f'_wait();_ioread({addr});') @@ -354,7 +355,6 @@ def add_fetch(action): for _ in range(4,mcycle.tcycles): add('') elif mcycle.type == 'iowrite': - l(f'// -- iowrite') addr = mcycle.items['ab'] data = mcycle.items['db'] add('') @@ -364,66 +364,98 @@ def add_fetch(action): for _ in range(4,mcycle.tcycles): add('') elif mcycle.type == 'generic': - l(f'// -- generic') add(f'{action}') for _ in range(1,mcycle.tcycles): add('') elif mcycle.type == 'overlapped': - l(f'// -- overlapped') action = (f"{mcycle.items['action']};" if 'action' in mcycle.items else '') if 'post_action' in mcycle.items: # if a post-action is defined we can jump to the common fetch block but # instead squeeze the fetch before the fetch action post_action = (f"{mcycle.items['post_action']};" if 'post_action' in mcycle.items else '') - add(f"{action}pins=_z80_fetch(cpu,pins);{post_action}") + add_stepto(f"{action}pins=_z80_fetch(cpu,pins);{post_action}") elif 'prefix' in mcycle.items: # likewise if this is a prefix instruction special case - add(f"{action}_fetch_{mcycle.items['prefix']}();") + add_stepto(f"{action}_fetch_{mcycle.items['prefix']}();") else: - # regular case, jump to the shared fetch block after the + # regular case, jump to the shared fetch block after the add_fetch(f'{action}') - op.num_steps = step + return { 'out_lines': out_lines + out_extra_lines, 'max_step': cur_extra_step } + +def extra_step_defines_string(max_step): + manual_steps = [ + "DDFD_M1_T2", + "DDFD_M1_T3", + "DDFD_M1_T4", + "DDFD_D_T1", + "DDFD_D_T2", + "DDFD_D_T3", + "DDFD_D_T4", + "DDFD_D_T5", + "DDFD_D_T6", + "DDFD_D_T7", + "DDFD_D_T8", + "DDFD_LDHLN_WR_T1", + "DDFD_LDHLN_WR_T2", + "DDFD_LDHLN_WR_T3", + "DDFD_LDHLN_OVERLAPPED", + "CB_M1_T2", + "CB_M1_T3", + "CB_M1_T4", + "ED_M1_T2", + "ED_M1_T3", + "ED_M1_T4", + "M1_T2", + "M1_T3", + "M1_T4", + ] + res = '' + step_index = max_step + for step_name in manual_steps: + res += f'#define Z80_{step_name} {step_index}\n' + step_index += 1 + special_steps = { + 'cb': 'CB_STEP', + 'cbhl': 'CBHL_STEP', + 'ddfdcb': 'DDFDCB_STEP', + 'int_im0': 'INT_IM0_STEP', + 'int_im1': 'INT_IM1_STEP', + 'int_im2': 'INT_IM2_STEP', + 'nmi': 'NMI_STEP', + } + for op_name, step_name in special_steps.items(): + op = find_op(op_name) + res += f'#define Z80_{step_name} {op.extra_step_index}\n' + return res -def optable_to_string(type): - global indent - indent = 1 +def indirect_table_string(): res = '' - for op_index,maybe_op in enumerate(OPS): - if (type == 'main' or type == 'ddfd') and op_index > 255: - continue - elif type == 'ed' and (op_index < 256 or op_index > 511): - continue - elif type == 'special' and op_index < 512: - continue - op = unwrap(maybe_op) - # map redundant 'single' ops to the original - if flag(op, 'single') and op.first_op_index != op_index: - op = unwrap(OPS[op.first_op_index]) - if type == 'ddfd' and flag(op, 'indirect') and flag(op, 'imm8'): - step = "_Z80_OPSTATE_STEP_INDIRECT_IMM8" - elif type == 'ddfd' and flag(op, 'indirect'): - step = "_Z80_OPSTATE_STEP_INDIRECT" + for i in range(0, 256): + op = OPS[i] + if i % 16 == 0: + res += ' ' + if flag(op, 'indirect'): + res += '1,' else: - step = f"{op.decoder_offset - 1:4}" - res += tab() + f'{step},' - res += f' // {op_index&0xFF:02X}: {op.name} (M:{len(op.mcycles)-1} T:{op.num_cycles} steps:{op.num_steps})\n' + res += '0,' + if i % 16 == 15: + res += '\n' return res -def write_result(): - with open(TEMPL_PATH, 'r') as templf: - templ = Template(templf.read()) - c_src = templ.safe_substitute( - decode_block = out_lines, - optable = optable_to_string('main'), - ddfd_optable = optable_to_string('ddfd'), - ed_optable = optable_to_string('ed'), - special_optable = optable_to_string('special')) - - with open(OUT_PATH, 'w') as outf: - outf.write(c_src) - -if __name__=='__main__': +def write_result(decoder_output): + out_lines = decoder_output['out_lines'] + max_step = decoder_output['max_step'] + with open(INOUT_PATH, 'r') as f: + lines = f.read().splitlines() + lines = templ.replace(lines, 'decoder', out_lines) + lines = templ.replace(lines, 'extra_step_defines', extra_step_defines_string(max_step)) + lines = templ.replace(lines, 'indirect_table', indirect_table_string()) + out_str = '\n'.join(lines) + '\n' + with open(INOUT_PATH, 'w') as f: + f.write(out_str) + +if __name__ == '__main__': parse_opdescs() expand_optable() - gen_decoder() - write_result() + decoder_output = gen_decoder() + write_result(decoder_output) diff --git a/codegen/z80_gen.sh b/codegen/z80_gen.sh new file mode 100755 index 00000000..2b682970 --- /dev/null +++ b/codegen/z80_gen.sh @@ -0,0 +1,4 @@ +python3 -m venv .venv +source .venv/bin/activate +python3 -m pip install pyyaml +python3 z80_gen.py \ No newline at end of file