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The example ignores the ready signal on the output side.
expectDequeueSeq fails to catch the problem because it consumes the data as soon as it is available. It tests the correctness of the data, but not whether the interface can handle backpressure.
BTW, by pure chance it is able to handle a single cycle or ready being false because the handshake takes an additional cycle after busy is set to false.
The bits remains valid because it is initially set to DontCare except for when it is assigned to (xInitial, yInitial, x). Chisel is free to just connect bits to (xInitial, yInitial, x) and it does, making the data valid for that additional cycle.
The text was updated successfully, but these errors were encountered:
The example ignores the
ready
signal on the output side.expectDequeueSeq
fails to catch the problem because it consumes the data as soon as it is available. It tests the correctness of the data, but not whether the interface can handle backpressure.BTW, by pure chance it is able to handle a single cycle or
ready
being false because the handshake takes an additional cycle afterbusy
is set to false.The
bits
remains valid because it is initially set toDontCare
except for when it is assigned to(xInitial, yInitial, x)
. Chisel is free to just connectbits
to(xInitial, yInitial, x)
and it does, making the data valid for that additional cycle.The text was updated successfully, but these errors were encountered: