{"payload":{"feedbackUrl":"https://github.com/orgs/community/discussions/53140","repo":{"id":461494646,"defaultBranch":"master","name":"optee_os","ownerLogin":"gagachang","currentUserCanPush":false,"isFork":true,"isEmpty":false,"createdAt":"2022-02-20T13:23:12.000Z","ownerAvatar":"https://avatars.githubusercontent.com/u/43228610?v=4","public":true,"private":false,"isOrgOwned":false},"refInfo":{"name":"","listCacheKey":"v0:1727318760.0","currentOid":""},"activityList":{"items":[{"before":"aaf781bb9066d16b396cbecc65765b6a23a37582","after":"bbd7b836ab12e7b709886943ea278092f8642e18","ref":"refs/heads/dev-riscv-improve-0926","pushedAt":"2024-09-27T08:36:44.000Z","pushType":"force_push","commitsCount":0,"pusher":{"login":"gagachang","name":"Alvin Che-Chia Chang","path":"/gagachang","primaryAvatarUrl":"https://avatars.githubusercontent.com/u/43228610?s=80&v=4"},"commit":{"message":"core: riscv: Improve thread user mode record\n\nMake the asm definitions be more human-readable.\n\nBesides, it's unnecessary to save and restore kernel SP and GP into\nthread_user_mode_rec, since they will be setup by system call trap\nhandler before executing thread_unwind_user_mode().\n\nSigned-off-by: Alvin Chang \nReviewed-by: Yu Chien Peter Lin ","shortMessageHtmlLink":"core: riscv: Improve thread user mode record"}},{"before":null,"after":"aaf781bb9066d16b396cbecc65765b6a23a37582","ref":"refs/heads/dev-riscv-improve-0926","pushedAt":"2024-09-26T02:46:00.000Z","pushType":"branch_creation","commitsCount":0,"pusher":{"login":"gagachang","name":"Alvin Che-Chia Chang","path":"/gagachang","primaryAvatarUrl":"https://avatars.githubusercontent.com/u/43228610?s=80&v=4"},"commit":{"message":"core: riscv: Improve thread user mode record\n\nMake the asm definitions be more human-readable.\n\nBesides, it's unnecessary to save and restore kernel SP and GP into\nthread_user_mode_rec, since they will be setup by system call trap\nhandler before executing thread_unwind_user_mode().\n\nSigned-off-by: Alvin Chang ","shortMessageHtmlLink":"core: riscv: Improve thread user mode record"}},{"before":"258b72d242cd1a8ae56c87f9572a0624084785c7","after":"19662e417055e7b115edcd3253e4df920162b859","ref":"refs/heads/master","pushedAt":"2024-09-25T14:34:13.000Z","pushType":"push","commitsCount":6,"pusher":{"login":"gagachang","name":"Alvin Che-Chia Chang","path":"/gagachang","primaryAvatarUrl":"https://avatars.githubusercontent.com/u/43228610?s=80&v=4"},"commit":{"message":"ta: apply __no_stack_protector to __ta_entry() or __ta_entry_c()\n\nApply the __no_stack_protector attribute to the first C function called\nfollowing the TA entry point (i.e., __ta_entry(), or for the special\ncase of ARM32, __ta_entry_c()). This is required because\n__stack_chk_guard is initialized in this very function, therefore stack\nprotection cannot be assumed to be functional at this point.\n\nFixes a TA crash on QEMUv7 with Clang 18.1.7 [1].\n\nLink: https://github.com/OP-TEE/optee_os/issues/7047 [1]\nSigned-off-by: Jerome Forissier \nAcked-by: Etienne Carriere \nAcked-by: Jens Wiklander \nReviewed-by: Khoa Hoang ","shortMessageHtmlLink":"ta: apply __no_stack_protector to __ta_entry() or __ta_entry_c()"}},{"before":"f2fe4f00a67b8504d9d7f35d4c7de6200b334aff","after":"258b72d242cd1a8ae56c87f9572a0624084785c7","ref":"refs/heads/master","pushedAt":"2024-09-25T12:37:24.000Z","pushType":"push","commitsCount":1,"pusher":{"login":"gagachang","name":"Alvin Che-Chia Chang","path":"/gagachang","primaryAvatarUrl":"https://avatars.githubusercontent.com/u/43228610?s=80&v=4"},"commit":{"message":"core: plat-corstone1000: Increase TZDRAM size\n\nIncreased TZDRAM size using space.\n\nNS_SHARED_RAM region is not used by Corstone1000 platform. It is\nremoved to create more space in secure RAM for BL32 image.\nThus, there is more space in the secure RAM that can be used by OP-TEE.\n\nSigned-off-by: Ali Can Ozaslan \nSigned-off-by: Emekcan Aras \nSigned-off-by: Harsimran Singh Tungal \nAcked-by: Jerome Forissier ","shortMessageHtmlLink":"core: plat-corstone1000: Increase TZDRAM size"}},{"before":"a75748346692554f662003ffc4306c3e667783a9","after":"f2fe4f00a67b8504d9d7f35d4c7de6200b334aff","ref":"refs/heads/master","pushedAt":"2024-09-23T14:44:49.000Z","pushType":"push","commitsCount":2,"pusher":{"login":"gagachang","name":"Alvin Che-Chia Chang","path":"/gagachang","primaryAvatarUrl":"https://avatars.githubusercontent.com/u/43228610?s=80&v=4"},"commit":{"message":"drivers: stm32_rng: use default PRNG init if RNG is disabled in the DT\n\nIn case RNG peripheral is not enabled in device tree, fallback to the\ndefault RNG initialization implementation.\n\nSigned-off-by: Thomas Bourgoin \nAcked-by: Jens Wiklander \nAcked-by: Jerome Forissier \nReviewed-by: Etienne Carriere ","shortMessageHtmlLink":"drivers: stm32_rng: use default PRNG init if RNG is disabled in the DT"}},{"before":"16b9b1ef7b421bb768ce816e53797fc0d60f236a","after":"a75748346692554f662003ffc4306c3e667783a9","ref":"refs/heads/master","pushedAt":"2024-09-19T13:28:19.000Z","pushType":"push","commitsCount":1,"pusher":{"login":"gagachang","name":"Alvin Che-Chia Chang","path":"/gagachang","primaryAvatarUrl":"https://avatars.githubusercontent.com/u/43228610?s=80&v=4"},"commit":{"message":"core: timeout_elapsed(): fix expiration threshold\n\nFix timeout threshold that should return once the time expires,\nnot 1 tick after it has expired. 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It that case, since counter never increments, the\nudelay(0) call in IO_READ32_POLL_TIMEOUT() never returns while we expect\nthe macro to endlessly poll (as timeout would never be detected) until\npoll condition is met or system watchdog is triggered.\n\nSigned-off-by: Etienne Carriere \nAcked-by: Jens Wiklander \nReviewed-by: Jerome Forissier ","shortMessageHtmlLink":"core: timeout_elapsed(): fix expiration threshold"}},{"before":"87a932c8121ee8a6794db5e760577fb7cd9d8495","after":"27eb28ab261893f8d0c3fbacb4d4ee22e530354f","ref":"refs/heads/dev-riscv-remove-exit-user-mode","pushedAt":"2024-09-19T06:37:22.000Z","pushType":"force_push","commitsCount":0,"pusher":{"login":"gagachang","name":"Alvin Che-Chia Chang","path":"/gagachang","primaryAvatarUrl":"https://avatars.githubusercontent.com/u/43228610?s=80&v=4"},"commit":{"message":"core: riscv: Remove thread_exit_user_mode()\n\nCurrently, the user mode abort and some system calls return to kernel\nmode by thread_exit_user_mode(). Although this function creates a\nshorter path to return to kernel mode, it leads to some problems because\nthe function does not update the core local flags. Especially when\nCFG_CORE_DEBUG_CHECK_STACKS=y, some checks will fail due to wrong type\nof stack recorded in the core local flags.\n\nFix it by removing thread_exit_user_mode(). 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Especially when\nCFG_CORE_DEBUG_CHECK_STACKS=y, some checks will fail due to wrong type\nof stack recorded in the core local flags.\n\nFix it by removing thread_exit_user_mode(). So that the core local flags\ncan be correctly updated in the common trap handler.\n\nSigned-off-by: Alvin Chang \nReviewed-by: Yu Chien Peter Lin ","shortMessageHtmlLink":"core: riscv: Remove thread_exit_user_mode()"}},{"before":"6f750c6d0d18be8629f646f4e09fbee136fefe25","after":"d36769d7a879c1e7e39fbcf1971387793d628a0e","ref":"refs/heads/dev-riscv-improve-0913","pushedAt":"2024-09-18T06:14:28.000Z","pushType":"force_push","commitsCount":0,"pusher":{"login":"gagachang","name":"Alvin Che-Chia Chang","path":"/gagachang","primaryAvatarUrl":"https://avatars.githubusercontent.com/u/43228610?s=80&v=4"},"commit":{"message":"core: riscv: Use sp as base register of load instructions\n\nUse sp as base register of load instructions can reduce code size if RVC\nextension is enabled to generate 16-bit instructions. The following code\nshows the difference after applying this commit.\n\nBefore:\n f10009da:\t0d053d83 \tld\ts11,208(a0)\n f10009de:\t0c853d03 \tld\ts10,200(a0)\n f10009e2:\t0c053c83 \tld\ts9,192(a0)\n f10009e6:\t0b853c03 \tld\ts8,184(a0)\n f10009ea:\t0b053b83 \tld\ts7,176(a0)\n f10009ee:\t0a853b03 \tld\ts6,168(a0)\n f10009f2:\t0a053a83 \tld\ts5,160(a0)\n f10009f6:\t09853a03 \tld\ts4,152(a0)\n f10009fa:\t09053983 \tld\ts3,144(a0)\n f10009fe:\t08853903 \tld\ts2,136(a0)\n\nAfter:\n f10009a6:\t6dce \tld\ts11,208(sp)\n f10009a8:\t6d2e \tld\ts10,200(sp)\n f10009aa:\t6c8e \tld\ts9,192(sp)\n f10009ac:\t7c6a \tld\ts8,184(sp)\n f10009ae:\t7bca \tld\ts7,176(sp)\n f10009b0:\t7b2a \tld\ts6,168(sp)\n f10009b2:\t7a8a \tld\ts5,160(sp)\n f10009b4:\t6a6a \tld\ts4,152(sp)\n f10009b6:\t69ca \tld\ts3,144(sp)\n f10009b8:\t692a \tld\ts2,136(sp)\n\nSigned-off-by: Alvin Chang \nReviewed-by: Yu Chien Peter Lin ","shortMessageHtmlLink":"core: riscv: Use sp as base register of load instructions"}},{"before":"66ce705c311603026a78e03e98c1b3f4aacd3a3d","after":"6f750c6d0d18be8629f646f4e09fbee136fefe25","ref":"refs/heads/dev-riscv-improve-0913","pushedAt":"2024-09-16T08:52:56.000Z","pushType":"force_push","commitsCount":0,"pusher":{"login":"gagachang","name":"Alvin Che-Chia Chang","path":"/gagachang","primaryAvatarUrl":"https://avatars.githubusercontent.com/u/43228610?s=80&v=4"},"commit":{"message":"core: riscv: Use sp as base register of load instructions\n\nUse sp as base register of load instructions can reduce code size if RVC\nextension is enabled to generate 16-bit instructions. The following code\nshows the difference after applying this commit.\n\nBefore:\n f10009da:\t0d053d83 \tld\ts11,208(a0)\n f10009de:\t0c853d03 \tld\ts10,200(a0)\n f10009e2:\t0c053c83 \tld\ts9,192(a0)\n f10009e6:\t0b853c03 \tld\ts8,184(a0)\n f10009ea:\t0b053b83 \tld\ts7,176(a0)\n f10009ee:\t0a853b03 \tld\ts6,168(a0)\n f10009f2:\t0a053a83 \tld\ts5,160(a0)\n f10009f6:\t09853a03 \tld\ts4,152(a0)\n f10009fa:\t09053983 \tld\ts3,144(a0)\n f10009fe:\t08853903 \tld\ts2,136(a0)\n\nAfter:\n f10009a6:\t6dce \tld\ts11,208(sp)\n f10009a8:\t6d2e \tld\ts10,200(sp)\n f10009aa:\t6c8e \tld\ts9,192(sp)\n f10009ac:\t7c6a \tld\ts8,184(sp)\n f10009ae:\t7bca \tld\ts7,176(sp)\n f10009b0:\t7b2a \tld\ts6,168(sp)\n f10009b2:\t7a8a \tld\ts5,160(sp)\n f10009b4:\t6a6a \tld\ts4,152(sp)\n f10009b6:\t69ca \tld\ts3,144(sp)\n f10009b8:\t692a \tld\ts2,136(sp)\n\nSigned-off-by: Alvin Chang ","shortMessageHtmlLink":"core: riscv: Use sp as base register of load instructions"}},{"before":"55a4d839310ce46aca79a12015ab8e1da9f110e5","after":"16b9b1ef7b421bb768ce816e53797fc0d60f236a","ref":"refs/heads/master","pushedAt":"2024-09-16T08:51:39.000Z","pushType":"push","commitsCount":13,"pusher":{"login":"gagachang","name":"Alvin Che-Chia Chang","path":"/gagachang","primaryAvatarUrl":"https://avatars.githubusercontent.com/u/43228610?s=80&v=4"},"commit":{"message":"riscv: plat-virt: allow enabling CFG_TEE_CORE_DEBUG for virt machine\n\nAllow enabling CFG_TEE_CORE_DEBUG to make assertions useful.\n\nSigned-off-by: Yu Chien Peter Lin \nReviewed-by: Alvin Chang \nTested-by: Alvin Chang \nAcked-by: Etienne Carriere ","shortMessageHtmlLink":"riscv: plat-virt: allow enabling CFG_TEE_CORE_DEBUG for virt machine"}},{"before":"706191e0b4a5140cc180dc18d44a3506e38e3b36","after":"66ce705c311603026a78e03e98c1b3f4aacd3a3d","ref":"refs/heads/dev-riscv-improve-0913","pushedAt":"2024-09-13T01:37:36.000Z","pushType":"force_push","commitsCount":0,"pusher":{"login":"gagachang","name":"Alvin Che-Chia Chang","path":"/gagachang","primaryAvatarUrl":"https://avatars.githubusercontent.com/u/43228610?s=80&v=4"},"commit":{"message":"core: riscv: Use sp as base register of load instructions\n\nUse sp as base register of load instructions can reduce code size if RVC\nextension is enabled to generate 16-bit instructions. The following code\nshows the difference after applying this commit.\n\nBefore:\n f10009da:\t0d053d83 \tld\ts11,208(a0)\n f10009de:\t0c853d03 \tld\ts10,200(a0)\n f10009e2:\t0c053c83 \tld\ts9,192(a0)\n f10009e6:\t0b853c03 \tld\ts8,184(a0)\n f10009ea:\t0b053b83 \tld\ts7,176(a0)\n f10009ee:\t0a853b03 \tld\ts6,168(a0)\n f10009f2:\t0a053a83 \tld\ts5,160(a0)\n f10009f6:\t09853a03 \tld\ts4,152(a0)\n f10009fa:\t09053983 \tld\ts3,144(a0)\n f10009fe:\t08853903 \tld\ts2,136(a0)\n\nAfter:\n f10009a6:\t6dce \tld\ts11,208(sp)\n f10009a8:\t6d2e \tld\ts10,200(sp)\n f10009aa:\t6c8e \tld\ts9,192(sp)\n f10009ac:\t7c6a \tld\ts8,184(sp)\n f10009ae:\t7bca \tld\ts7,176(sp)\n f10009b0:\t7b2a \tld\ts6,168(sp)\n f10009b2:\t7a8a \tld\ts5,160(sp)\n f10009b4:\t6a6a \tld\ts4,152(sp)\n f10009b6:\t69ca \tld\ts3,144(sp)\n f10009b8:\t692a \tld\ts2,136(sp)\n\nSigned-off-by: Alvin Chang ","shortMessageHtmlLink":"core: riscv: Use sp as base register of load instructions"}},{"before":"d360ab4a2b036ab9b223a8debb4f2d8aaa1d1f7d","after":"706191e0b4a5140cc180dc18d44a3506e38e3b36","ref":"refs/heads/dev-riscv-improve-0913","pushedAt":"2024-09-13T01:31:48.000Z","pushType":"push","commitsCount":1,"pusher":{"login":"gagachang","name":"Alvin Che-Chia Chang","path":"/gagachang","primaryAvatarUrl":"https://avatars.githubusercontent.com/u/43228610?s=80&v=4"},"commit":{"message":"123","shortMessageHtmlLink":"123"}},{"before":null,"after":"d360ab4a2b036ab9b223a8debb4f2d8aaa1d1f7d","ref":"refs/heads/dev-riscv-improve-0913","pushedAt":"2024-09-13T01:28:59.000Z","pushType":"branch_creation","commitsCount":0,"pusher":{"login":"gagachang","name":"Alvin Che-Chia Chang","path":"/gagachang","primaryAvatarUrl":"https://avatars.githubusercontent.com/u/43228610?s=80&v=4"},"commit":{"message":"core: riscv: Fix misconfiguration of XSCRATCH when XRET to kernel mode\n\nWhen the program wants to XRET to kernel mode, the value of XSCRATCH\nmust be cleared to zero.\n\nSigned-off-by: Alvin Chang ","shortMessageHtmlLink":"core: riscv: Fix misconfiguration of XSCRATCH when XRET to kernel mode"}},{"before":"fd20a4f3f66650b5d2fb14df951773b1fb27de85","after":"9c11c01a2c0014a95f445e61a5d825f9123d4899","ref":"refs/heads/dev-riscv-improve-0819","pushedAt":"2024-09-11T07:57:23.000Z","pushType":"force_push","commitsCount":0,"pusher":{"login":"gagachang","name":"Alvin Che-Chia Chang","path":"/gagachang","primaryAvatarUrl":"https://avatars.githubusercontent.com/u/43228610?s=80&v=4"},"commit":{"message":"core: riscv: Fix misconfiguration of XSCRATCH when XRET to kernel mode\n\nWhen the program wants to XRET to kernel mode, the value of XSCRATCH\nmust be cleared to zero.\n\nSigned-off-by: Alvin Chang ","shortMessageHtmlLink":"core: riscv: Fix misconfiguration of XSCRATCH when XRET to kernel mode"}},{"before":"a84301a43aae5d149249c78e273907e7d83d5693","after":"fd20a4f3f66650b5d2fb14df951773b1fb27de85","ref":"refs/heads/dev-riscv-improve-0819","pushedAt":"2024-09-11T07:53:10.000Z","pushType":"push","commitsCount":1,"pusher":{"login":"gagachang","name":"Alvin Che-Chia Chang","path":"/gagachang","primaryAvatarUrl":"https://avatars.githubusercontent.com/u/43228610?s=80&v=4"},"commit":{"message":"core: riscv: Fix misconfiguration of XSCRATCH when XRET to kernel mode\n\nWhen the program wants to XRET to kernel mode, the value of XSCRATCH\nmust be cleared to zero.\n\nSigned-off-by: Alvin Chang ","shortMessageHtmlLink":"core: riscv: Fix misconfiguration of XSCRATCH when XRET to kernel mode"}},{"before":"7b76de3dc3b0c49260b118ed2ad05de8944620d2","after":"55a4d839310ce46aca79a12015ab8e1da9f110e5","ref":"refs/heads/master","pushedAt":"2024-09-10T16:19:08.000Z","pushType":"push","commitsCount":2,"pusher":{"login":"gagachang","name":"Alvin Che-Chia Chang","path":"/gagachang","primaryAvatarUrl":"https://avatars.githubusercontent.com/u/43228610?s=80&v=4"},"commit":{"message":"ta: pkcs11: fix memory leak\n\nOn update_persistent_object_attributes failure, head_new (stored in\nobj->attributes) is not freed, causing a memory leak.\n\nReported-by: Christian Zoia \nCloses: https://github.com/OP-TEE/optee_os/issues/7023\nFixes: 6959626e1621 (\"ta: pkcs11: preserve object when set attribute fails\")\nSigned-off-by: Georges Savoundararadj \nReviewed-by: Jerome Forissier \nReviewed-by: Etienne Carriere ","shortMessageHtmlLink":"ta: pkcs11: fix memory leak"}},{"before":"0e75590b83f8370c053e2e1cb2d654d7f24f40d6","after":"a84301a43aae5d149249c78e273907e7d83d5693","ref":"refs/heads/dev-riscv-improve-0819","pushedAt":"2024-09-10T05:30:50.000Z","pushType":"force_push","commitsCount":0,"pusher":{"login":"gagachang","name":"Alvin Che-Chia Chang","path":"/gagachang","primaryAvatarUrl":"https://avatars.githubusercontent.com/u/43228610?s=80&v=4"},"commit":{"message":"core: riscv: Ensure XSTATUS is restored before XIE\n\nIn previous implementation, we found some accidental interrupts during\nentering user mode and resuming of thread. We fixed it by clearing\nXSTATUS.XIE, which is global interrupt enable bit, to ensure there are\nno interrupts.\n\nNow we found the better solution: restore XSTATUS before restoring XIE.\nThis can ensure the global interrupt bit is cleared before we restore\nindividual interrupt bits in XIE.\n\nSigned-off-by: Alvin Chang ","shortMessageHtmlLink":"core: riscv: Ensure XSTATUS is restored before XIE"}},{"before":"86d1ca289c07d6985739069b3b4215e04a46918c","after":"0e75590b83f8370c053e2e1cb2d654d7f24f40d6","ref":"refs/heads/dev-riscv-improve-0819","pushedAt":"2024-09-10T05:23:45.000Z","pushType":"force_push","commitsCount":0,"pusher":{"login":"gagachang","name":"Alvin Che-Chia Chang","path":"/gagachang","primaryAvatarUrl":"https://avatars.githubusercontent.com/u/43228610?s=80&v=4"},"commit":{"message":"core: riscv: Ensure XSTATUS is restored before XIE\n\nIn previous implementation, we found some accidental interrupts during\nentering user mode and resuming of thread. We fixed it by clearing\nXSTATUS.XIE, which is global interrupt enable bit, to ensure there are\nno interrrupts.\n\nNow we found the better solution: restore XSTATUS before restoring XIE.\nThis can ensure the global interrupt bit is cleared before we restore\nindividual interrupt bits in XIE.\n\nSigned-off-by: Alvin Chang ","shortMessageHtmlLink":"core: riscv: Ensure XSTATUS is restored before XIE"}},{"before":"74d63113a4b98abb8a2045597b599f224d1fdad7","after":"7b76de3dc3b0c49260b118ed2ad05de8944620d2","ref":"refs/heads/master","pushedAt":"2024-09-09T16:43:42.000Z","pushType":"push","commitsCount":5,"pusher":{"login":"gagachang","name":"Alvin Che-Chia Chang","path":"/gagachang","primaryAvatarUrl":"https://avatars.githubusercontent.com/u/43228610?s=80&v=4"},"commit":{"message":"core: riscv: Let platform choose native and foreign interrupts\n\nPlatform may want to choose different types of native and foreign\ninterrupts. This commit adds two definitions for the platforms:\n1. PLAT_THREAD_EXCP_FOREIGN_INTR: to define platform specific foreign\n interrupts\n2. PLAT_THREAD_EXCP_NATIVE_INTR: to define platform specific native\n interrupts.\n\nFor RISC-V virt machine, we define all external/mtimer/software\ninterrupts as foreign interrupts. For RISC-V spike platform, we define\nexternal interrupts as foreign interrupts, and mtimer/software\ninterrupts as native interrupts.\n\nSigned-off-by: Alvin Chang \nReviewed-by: Yu Chien Peter Lin \nAcked-by: Jens Wiklander ","shortMessageHtmlLink":"core: riscv: Let platform choose native and foreign interrupts"}},{"before":"6e5cb5c9f42119509079fb0736d04cd8aae9c36e","after":"74d63113a4b98abb8a2045597b599f224d1fdad7","ref":"refs/heads/master","pushedAt":"2024-09-09T09:40:21.000Z","pushType":"push","commitsCount":2,"pusher":{"login":"gagachang","name":"Alvin Che-Chia Chang","path":"/gagachang","primaryAvatarUrl":"https://avatars.githubusercontent.com/u/43228610?s=80&v=4"},"commit":{"message":"core: arm: Remove duplicated sp assignment for ARM64 in set_ctx_regs()\n\nThere are two lines of code to assign value of sp for ARM64. Remove one\nof them.\n\nSigned-off-by: Alvin Chang \nReviewed-by: Etienne Carriere \nReviewed-by: Jens Wiklander ","shortMessageHtmlLink":"core: arm: Remove duplicated sp assignment for ARM64 in set_ctx_regs()"}},{"before":"f830bfe906c2473273905349836466ed194ada22","after":"982e5ea2420a51172a7cc539ad4e2f157a16a59e","ref":"refs/heads/dev-arm-20240909","pushedAt":"2024-09-09T08:26:59.000Z","pushType":"force_push","commitsCount":0,"pusher":{"login":"gagachang","name":"Alvin Che-Chia Chang","path":"/gagachang","primaryAvatarUrl":"https://avatars.githubusercontent.com/u/43228610?s=80&v=4"},"commit":{"message":"core: arm: Remove duplicated sp assignment for ARM64 in set_ctx_regs()\n\nThere are two lines of code to assign value of sp for ARM64. Remove one\nof them.\n\nSigned-off-by: Alvin Chang \nReviewed-by: Etienne Carriere \nReviewed-by: Jens Wiklander ","shortMessageHtmlLink":"core: arm: Remove duplicated sp assignment for ARM64 in set_ctx_regs()"}},{"before":"a3acc05c83c2bbf01e7121a711e168a5c29cd5b4","after":"86d1ca289c07d6985739069b3b4215e04a46918c","ref":"refs/heads/dev-riscv-improve-0819","pushedAt":"2024-09-09T08:26:05.000Z","pushType":"force_push","commitsCount":0,"pusher":{"login":"gagachang","name":"Alvin Che-Chia Chang","path":"/gagachang","primaryAvatarUrl":"https://avatars.githubusercontent.com/u/43228610?s=80&v=4"},"commit":{"message":"core: riscv: Use sp as base register of load instructions\n\nUse sp as base register of load instructions can reduce code size if RVC\nextension is enabled to generate 16-bit instructions. The following code\nshows the difference after applying this commit.\n\nBefore:\n f10009da:\t0d053d83 \tld\ts11,208(a0)\n f10009de:\t0c853d03 \tld\ts10,200(a0)\n f10009e2:\t0c053c83 \tld\ts9,192(a0)\n f10009e6:\t0b853c03 \tld\ts8,184(a0)\n f10009ea:\t0b053b83 \tld\ts7,176(a0)\n f10009ee:\t0a853b03 \tld\ts6,168(a0)\n f10009f2:\t0a053a83 \tld\ts5,160(a0)\n f10009f6:\t09853a03 \tld\ts4,152(a0)\n f10009fa:\t09053983 \tld\ts3,144(a0)\n f10009fe:\t08853903 \tld\ts2,136(a0)\n\nAfter:\n f10009a6:\t6dce \tld\ts11,208(sp)\n f10009a8:\t6d2e \tld\ts10,200(sp)\n f10009aa:\t6c8e \tld\ts9,192(sp)\n f10009ac:\t7c6a \tld\ts8,184(sp)\n f10009ae:\t7bca \tld\ts7,176(sp)\n f10009b0:\t7b2a \tld\ts6,168(sp)\n f10009b2:\t7a8a \tld\ts5,160(sp)\n f10009b4:\t6a6a \tld\ts4,152(sp)\n f10009b6:\t69ca \tld\ts3,144(sp)\n f10009b8:\t692a \tld\ts2,136(sp)\n\nSigned-off-by: Alvin Chang ","shortMessageHtmlLink":"core: riscv: Use sp as base register of load instructions"}},{"before":"9ad9e705263d63bc89e01b35d55b04bdc232d32f","after":"a3acc05c83c2bbf01e7121a711e168a5c29cd5b4","ref":"refs/heads/dev-riscv-improve-0819","pushedAt":"2024-09-09T06:05:27.000Z","pushType":"push","commitsCount":1,"pusher":{"login":"gagachang","name":"Alvin Che-Chia Chang","path":"/gagachang","primaryAvatarUrl":"https://avatars.githubusercontent.com/u/43228610?s=80&v=4"},"commit":{"message":"core: riscv: Use sp as base register of load instructions\n\nUse sp as base register of load instructions can reduce code size if RVC\nextension is enabled to generate 16-bit instructions. The following code\nshows the difference after applying this commit.\n\nBefore:\n f10009da:\t0d053d83 \tld\ts11,208(a0)\n f10009de:\t0c853d03 \tld\ts10,200(a0)\n f10009e2:\t0c053c83 \tld\ts9,192(a0)\n f10009e6:\t0b853c03 \tld\ts8,184(a0)\n f10009ea:\t0b053b83 \tld\ts7,176(a0)\n f10009ee:\t0a853b03 \tld\ts6,168(a0)\n f10009f2:\t0a053a83 \tld\ts5,160(a0)\n f10009f6:\t09853a03 \tld\ts4,152(a0)\n f10009fa:\t09053983 \tld\ts3,144(a0)\n f10009fe:\t08853903 \tld\ts2,136(a0)\n\nAfter:\n f10009a6:\t6dce \tld\ts11,208(sp)\n f10009a8:\t6d2e \tld\ts10,200(sp)\n f10009aa:\t6c8e \tld\ts9,192(sp)\n f10009ac:\t7c6a \tld\ts8,184(sp)\n f10009ae:\t7bca \tld\ts7,176(sp)\n f10009b0:\t7b2a \tld\ts6,168(sp)\n f10009b2:\t7a8a \tld\ts5,160(sp)\n f10009b4:\t6a6a \tld\ts4,152(sp)\n f10009b6:\t69ca \tld\ts3,144(sp)\n f10009b8:\t692a \tld\ts2,136(sp)\n\nSigned-off-by: Alvin Chang ","shortMessageHtmlLink":"core: riscv: Use sp as base register of load instructions"}},{"before":"a523f76247fc6ecf5b2e1b379497bfd67e7c53bf","after":"9ad9e705263d63bc89e01b35d55b04bdc232d32f","ref":"refs/heads/dev-riscv-improve-0819","pushedAt":"2024-09-09T05:45:14.000Z","pushType":"push","commitsCount":1,"pusher":{"login":"gagachang","name":"Alvin Che-Chia Chang","path":"/gagachang","primaryAvatarUrl":"https://avatars.githubusercontent.com/u/43228610?s=80&v=4"},"commit":{"message":"core: riscv: Set exception return PC into XEPC instead of ra\n\nInstead of setting exception return PC into \"ra\" register and assign it\nto XEPC, we should directly set exception return PC into \"XEPC\" CSR to\nimprove code redability.\n\nSigned-off-by: Alvin Chang ","shortMessageHtmlLink":"core: riscv: Set exception return PC into XEPC instead of ra"}},{"before":"fbdf1288cd67bbd91afaee7b149fa64b0ff33df6","after":"a523f76247fc6ecf5b2e1b379497bfd67e7c53bf","ref":"refs/heads/dev-riscv-improve-0819","pushedAt":"2024-09-09T05:25:01.000Z","pushType":"force_push","commitsCount":0,"pusher":{"login":"gagachang","name":"Alvin Che-Chia Chang","path":"/gagachang","primaryAvatarUrl":"https://avatars.githubusercontent.com/u/43228610?s=80&v=4"},"commit":{"message":"core: riscv: Improve thread user mode record\n\nThe following steps descript the program flow of kernel context during\nentering and exiting user mode:\n\n1. thread_enter_user_mode(): prepare user mode context\n2. __thread_enter_user_mode(): allocate thread_user_mode_rec from kernel\n stack, and save kernel RA and callee-saved registers into\n thread_user_mode_rec. Save kernel SP into thread context.\n Enter user mode context.\n\nIf there is a user ecall which wants to return to kernel mode:\n 3. ecall_from_user(): Already set kernel SP, GP, and TP.\n 4. setup_unwind_user_mode(): prepare to return to kernel mode.\nIf there is a user abort which should return to kernel mode:\n 3. abort_from_user(): Already set kernel SP, GP, and TP.\n 4. handle_user_mode_panic(): prepare to return to kernel mode.\n\n5. XRET to kernel mode with kernel SP, GP, and TP are already set.\n6. thread_unwind_user_mode(): Restore kernel RA and callee-saved\n registers from thread_user_mode_rec.\n\nThus, it's unnecessary to save kernel SP and GP into\nthread_user_mode_rec, since they have already set by trap handler and\nit's unnecessary to set them again in thread_unwind_user_mode().\n\nAlso, rename THREAD_USER_MODE_REC_XX to their register names.\n\nSigned-off-by: Alvin Chang ","shortMessageHtmlLink":"core: riscv: Improve thread user mode record"}},{"before":null,"after":"f830bfe906c2473273905349836466ed194ada22","ref":"refs/heads/dev-arm-20240909","pushedAt":"2024-09-09T02:45:13.000Z","pushType":"branch_creation","commitsCount":0,"pusher":{"login":"gagachang","name":"Alvin Che-Chia Chang","path":"/gagachang","primaryAvatarUrl":"https://avatars.githubusercontent.com/u/43228610?s=80&v=4"},"commit":{"message":"core: arm: Remove duplicated sp assignment for ARM64 in set_ctx_regs()\n\nThere are two lines of code to assign value of sp for ARM64. Remove one\nof them.\n\nSigned-off-by: Alvin Chang ","shortMessageHtmlLink":"core: arm: Remove duplicated sp assignment for ARM64 in set_ctx_regs()"}},{"before":"5a1d868726068e0e540b08bf9315465b29e2eb4e","after":"fbdf1288cd67bbd91afaee7b149fa64b0ff33df6","ref":"refs/heads/dev-riscv-improve-0819","pushedAt":"2024-09-09T02:39:56.000Z","pushType":"force_push","commitsCount":0,"pusher":{"login":"gagachang","name":"Alvin Che-Chia Chang","path":"/gagachang","primaryAvatarUrl":"https://avatars.githubusercontent.com/u/43228610?s=80&v=4"},"commit":{"message":"core: riscv: Improve thread user mode record\n\nThe following steps descript the program flow of kernel context during\nentering and exiting user mode:\n\n1. thread_enter_user_mode(): prepare user mode context\n2. __thread_enter_user_mode(): allocate thread_user_mode_rec from kernel\n stack, and save kernel RA and callee-saved registers into\n thread_user_mode_rec. Save kernel SP into thread context.\n Enter user mode context.\n\nIf there is a user ecall which wants to return to kernel mode:\n 3. ecall_from_user(): Already set kernel SP, GP, and TP.\n 4. setup_unwind_user_mode(): prepare to return to kernel mode.\nIf there is a user abort which should return to kernel mode:\n 3. abort_from_user(): Already set kernel SP, GP, and TP.\n 4. handle_user_mode_panic(): prepare to return to kernel mode.\n\n5. XRET to kernel mode with kernel SP, GP, and TP are already set.\n6. thread_unwind_user_mode(): Restore kernel RA and callee-saved\n registers from thread_user_mode_rec.\n\nThus, it's unnecessary to save kernel SP and GP into\nthread_user_mode_rec, since they have already set by trap handler and\nit's unnecessary to set them again in thread_unwind_user_mode().\n\nAlso, rename THREAD_USER_MODE_REC_XX to their register names.\n\nSigned-off-by: Alvin Chang ","shortMessageHtmlLink":"core: riscv: Improve thread user mode record"}},{"before":"cd7384a0a94b2eba741a797f27974338b063f391","after":"6e5cb5c9f42119509079fb0736d04cd8aae9c36e","ref":"refs/heads/master","pushedAt":"2024-09-05T11:00:27.000Z","pushType":"push","commitsCount":4,"pusher":{"login":"gagachang","name":"Alvin Che-Chia Chang","path":"/gagachang","primaryAvatarUrl":"https://avatars.githubusercontent.com/u/43228610?s=80&v=4"},"commit":{"message":"checkpatch: add ignore=STRLCPY\n\nCheckpatch complains over strlcpy:\nWARNING: Prefer strscpy over strlcpy - see: https://github.com/KSPP/linux/issues/89\n\nHowever, OP-TEE doesn't have a strscpy() function to use, so silence the\nwarning until one is available.\n\nSigned-off-by: Jens Wiklander \nReviewed-by: Etienne Carriere ","shortMessageHtmlLink":"checkpatch: add ignore=STRLCPY"}},{"before":"cd488cee50d7009502247ebbb567030ce7d55725","after":"5a1d868726068e0e540b08bf9315465b29e2eb4e","ref":"refs/heads/dev-riscv-improve-0819","pushedAt":"2024-09-05T06:19:31.000Z","pushType":"force_push","commitsCount":0,"pusher":{"login":"gagachang","name":"Alvin Che-Chia Chang","path":"/gagachang","primaryAvatarUrl":"https://avatars.githubusercontent.com/u/43228610?s=80&v=4"},"commit":{"message":"core: riscv: Improve thread user mode record\n\nThe following steps descript the program flow of kernel context during\nentering and exiting user mode:\n\n1. thread_enter_user_mode(): prepare user mode context\n2. __thread_enter_user_mode(): allocate thread_user_mode_rec from kernel\n stack, and save kernel RA and callee-saved registers into\n thread_user_mode_rec. Save kernel SP into thread context.\n Enter user mode context.\n\nIf there is a user ecall which wants to return to kernel mode:\n 3. ecall_from_user(): Already set kernel SP, GP, and TP.\n 4. setup_unwind_user_mode(): prepare to return to kernel mode.\nIf there is a user abort which should return to kernel mode:\n 3. abort_from_user(): Already set kernel SP, GP, and TP.\n 4. handle_user_mode_panic(): prepare to return to kernel mode.\n\n5. XRET to kernel mode with kernel SP, GP, and TP are already set.\n6. thread_unwind_user_mode(): Restore kernel RA and callee-saved\n registers from thread_user_mode_rec.\n\nThus, it's unnecessary to save kernel SP and GP into\nthread_user_mode_rec, since they have already set by trap handler and\nit's unnecessary to set them again in thread_unwind_user_mode().\n\nAlso, rename THREAD_USER_MODE_REC_XX to their register names.\n\nSigned-off-by: Alvin Chang ","shortMessageHtmlLink":"core: riscv: Improve thread user mode record"}}],"hasNextPage":true,"hasPreviousPage":false,"activityType":"all","actor":null,"timePeriod":"all","sort":"DESC","perPage":30,"startCursor":"Y3Vyc29yOnYyOpK7MjAyNC0wOS0yN1QwODozNjo0NC4wMDAwMDBazwAAAATCXn5d","endCursor":"Y3Vyc29yOnYyOpK7MjAyNC0wOS0wNVQwNjoxOTozMS4wMDAwMDBazwAAAAStdpeh"}},"title":"Activity ยท gagachang/optee_os"}