From 3b5e85cd132e4690f21f7e560a29880a2ba0c381 Mon Sep 17 00:00:00 2001 From: Alvin Chang Date: Mon, 14 Oct 2024 15:15:02 +0800 Subject: [PATCH] core: riscv: Disable traps by clearing XIE CSR Ensure we disable traps by clearing XIE CSR instead of clearing XSTATUS.IE which is global interrupt enable bit. Signed-off-by: Alvin Chang Reviewed-by: Yu Chien Peter Lin Reviewed-by: Marouene Boubakri --- core/arch/riscv/kernel/thread_optee_abi_rv.S | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/core/arch/riscv/kernel/thread_optee_abi_rv.S b/core/arch/riscv/kernel/thread_optee_abi_rv.S index 975ca56f9ec..3702940ae77 100644 --- a/core/arch/riscv/kernel/thread_optee_abi_rv.S +++ b/core/arch/riscv/kernel/thread_optee_abi_rv.S @@ -46,8 +46,8 @@ FUNC thread_std_abi_entry , : /* Save return value */ mv s0, a0 - /* Disable all interrupts */ - csrc CSR_XSTATUS, CSR_XSTATUS_IE + /* Mask all maskable exceptions before switching to temporary stack */ + csrw CSR_XIE, x0 /* Switch to temporary stack */ jal thread_get_tmp_sp