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Behaviour of "open" serial transfers #558

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ISSOtm opened this issue Jul 3, 2024 · 2 comments
Open

Behaviour of "open" serial transfers #558

ISSOtm opened this issue Jul 3, 2024 · 2 comments
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@ISSOtm
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ISSOtm commented Jul 3, 2024

Originally raised as #556 (review):

I'm now wondering what value is obtained from attempting a transfer when the other GB(C) has not set its bit 7. Could it depend on the last transferred bit?

This can be expanded to "what happens if the serial port is not connected to another console?"; to the best of my knowledge, bits shifted in are 1s, but this isn't stated clearly.

@ISSOtm ISSOtm added the research label Jul 3, 2024
@quinnyo
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quinnyo commented Jul 3, 2024

I have some limited test results about this. I tested various no-connection and live disconnection scenarios (cable out, power down, SC.7 == 0).
I say 'limited' because I wasn't specifically testing what happened upon disconnection while/after receiving certain values. It seems likely that I did inadvertently test both 1 and 0 but it's possible I got lucky and always happened to transfer the right value just before disconnection.

The table shows the various scenarios (remote status) and the value received.

remote status value rx
not connected 1
connected, unpowered 0
connected, SC.7 == 0 0

Each status includes booting up in that configuration as well as forcing that configuration after some amount of successful transfers. I found no differences in that sense so I just condensed the table down.

Test notes:
  • Test devices: DMG, MGB, CGB(clear), CGB(red)
  • all combinations (each as clock provider and not) of MGB & CGB: same result.
  • CGB(red) has a flaky connector so wasn't tested further.
  • all combinations of DMG, MGB, and CGB(clear): same result.
  • CGB mode not used.
  • test program simply started the next transfer if not transferring
  • test values were either counting patterns or random numbers
  • the last ~8 received bytes were printed on screen
  • results collected by lookin' at numbers

@nitro2k01
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From a hardware standpoint, not connected and connected, unpowered are exactly what I would expect.

For the "not connected" case, the SI pin has an internal pullup resistor, which sets a default value of 1.

For the "connected, unpowered" case, the SoC pins other side will have clamping diodes going to ground and Vcc, for protecting against ESD and excursions outside the voltage rails. You could backfeed power to a device through these diodes, as showcased in this classic hack using an ATTiny microcontroller as an RFID tag. However, in this case there won't be enough power to power the SoC due to all the series resistors, and instead this will effectively just clamp everything to a logic low.

For "connected, SC.7 == 0" I would expect the other side to permanently drive whatever was the last bit it output on the link port, in other words the previous transfer's bit 0, or a starting value of 0 if no transfer had been done since last reset. At least according to DMG-CPU-Inside, this is a fairly simple circuit where the ELYS latch in the bottom right of the schematic drives the output. Might be interesting to do some corner case research on GBC and especially GBA where the circuitry might be shared with the GBA's more advanced link port circuit.

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