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It turns out that this causes a chicken-and-egg problem when the ULPI is clocking the USB domain, as it needs a handful clock cycles for deasserting reset on the ULPI PHY, which won't happen on most ULPI chips when under reset.
The text was updated successfully, but these errors were encountered:
Some time ago reset circuitry was added to the ULPI-UTMI translator for driving the reset pin:
cf6abaa#diff-de77f76028125aedf4c17b29d20a297397b3cf32507f0c202df785f0d76974c7R861-R866
It turns out that this causes a chicken-and-egg problem when the ULPI is clocking the USB domain, as it needs a handful clock cycles for deasserting reset on the ULPI PHY, which won't happen on most ULPI chips when under reset.
The text was updated successfully, but these errors were encountered: