HBMDevice.ini

;2n prefetch architecture with 256 bits per memory read and write access 
;BL = 2 and 4
;Up to 8 channels/stack
;8 or 16 banks per channel; varies by device density/channel
;Bank Grouping supported
;2K or 4K Bytes per page; varies by device density/channel
;IO voltage 1.2 V
;DRAM core voltage 1.2 V, independent of IO voltage
;Channel density of 1 Gb to 32 Gb
;Page Size = 2^COL_BITS * (PREFETCH_SIZE/8) where COL_BITS is the number of column address bits

NUM_BANKS=16         ;1Gb:8     2Gb:8      4Gb:16         based on JESD235
NUM_ROWS=16384       ;1Gb:8192  2Gb:16384  4Gb:16384      based on JESD235
NUM_COLS=128         ;1Gb:64*2  2Gb:64*2   4Gb:64*2       based on JESD235 (legacy mode)
PREFETCH_SIZE=512    ;1Gb:256*2 2Gb:256*2  4Gb:256*2      based on JESD235 (legacy mode)
BL=4                 ;2 or 4

;in nanoseconds
REFRESH_PERIOD=3900  ;1Gb,2Gb,4Gb: 3.9 us 
tCK=2                ;clock speed up to 500 MHz (1Gbps, considering DDR)

;in clock cycles, based on JESD235 and Ramulator
CL=7 
tRCD=7
tRP=7
AL=0
tRAS=17
tRTP=7
tRC=24
tWR=8
tFAW=20
tCKE=5
tCMD=1
tRRDS=4
tRRDL=5
tCCD=3         ;tCCDS=2, tCCDL=3
tWTR=4         ;tWTRS=2, tWTRL=4
tXP=5          ;Power-down exit time
tRTRS=1        ;Dead time to hand-off DQS control to other rank (column reads to different ranks)
tRFC=55        ;1Gb:55, 2Gb:80, 4Gb:130
;tREFI1B=64     ;1Gb:64, 2Gb:128, 4Gb:256
;tXS=60         ;1Gb:60, 2Gb:85, 4Gb:135
;nRCDR=7
;nRCDW=6
;nRP=7
;nCWL=4
;nPD=5
;nCKESR=5