Skip to content
New issue

Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.

By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.

Already on GitHub? Sign in to your account

Question about DMA setup time modeling #106

Open
daecheolyou opened this issue Oct 25, 2021 · 2 comments
Open

Question about DMA setup time modeling #106

daecheolyou opened this issue Oct 25, 2021 · 2 comments

Comments

@daecheolyou
Copy link

In the datapath, there is DMA setup time modeling, which delays the DMA transaction considering CPU cache flush or invalidation latency. However, to my knowledge, directory controller of MESI_Two_Level protocol sends an invalidate signal to the line owner when it receives DMA read or write request for the line in modified state (transition(M, DMA_READ, M_DRD) or transition(M, DMA_WRITE, M_DWR) in dir.sm). I think CPU cache flush/invalidation latency is duplicated if ignore_cache_flush is set to false. What do you think about it?

@yaoyuannnn
Copy link
Member

yaoyuannnn commented Oct 26, 2021

The DMA setup time was added to mode the setup phase of the DMA controller, which was validated against a Zynq Zedboard. I think we have a pipelined_dma parameter to pipeline this across multiple DMA requests. But this latency is different from the CPU cache flush and invalidation latencies, which were added to model incorrect DMA behaviors. I agree that since the MESI_Two_Level protocol models a coherent DMA controller, these are not really needed.

@xyzsam
Copy link
Member

xyzsam commented Oct 26, 2021

To add to what Yuan explained, this was added very early in gem5-Aladdin history, long before we had a dedicated ruby model for coherency (which Yuan added). It exists purely as a relic of the past, and we should probably remove it to simplify the code considerably.

Sign up for free to join this conversation on GitHub. Already have an account? Sign in to comment
Labels
None yet
Projects
None yet
Development

No branches or pull requests

3 participants