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Hello, I think in the current framework. The cycle time of the accelerator is stored as integers, so the max accelerator clock frequency is 1GHz. Is it possible to simulate the accelerator with a higher frequency?
The text was updated successfully, but these errors were encountered:
Aladdin's clock frequency is mostly for power modeling, not performance modeling. Most accelerator operations are defined in terms of cycles, not in terms of absolute time. So if you were running Aladdin in standalone mode (unlikely since you're asking in the context of SMAUG), you could change the cycle time to any arbitrary value, and you'll get the same total cycle count at the end, just with a different power number.
With gem5, you can connect an arbitrary system clock from gem5 to Aladdin and you will get the results you expect. The cycle time parameter in Aladdin does not affect gem5's modeled performance in any way.
Thanks so much for the reply. I asked the question because the frequency and the latency are fixed for the DRAM main memory. So I want to change the accelerator frequency and see the performance variation for certain memory configurations.
Hello, I think in the current framework. The cycle time of the accelerator is stored as integers, so the max accelerator clock frequency is 1GHz. Is it possible to simulate the accelerator with a higher frequency?
The text was updated successfully, but these errors were encountered: