diff --git a/Cargo.toml b/Cargo.toml index 3da185e2..b6650c3d 100644 --- a/Cargo.toml +++ b/Cargo.toml @@ -60,6 +60,10 @@ optional = true [dependencies.ral-registers] version = "0.1.3" +[dependencies.defmt] +workspace = true +optional = true + ####################### # imxrt-rs dependencies ####################### @@ -117,6 +121,7 @@ imxrt-log = { path = "logging", default-features = false, features = [ imxrt-ral = "0.6" imxrt-rt = "0.1.5" imxrt-usbd = "0.3" +defmt = "0.3" [workspace.package] repository = "https://github.com/imxrt-rs/imxrt-hal" @@ -154,7 +159,6 @@ imxrt-rt = { workspace = true } menu = "0.3.2" rtic = { version = "2.0", features = ["thumbv7-backend"] } log = "0.4" -defmt = "0.3" pin-utils = "0.1" usb-device = { version = "0.3", features = ["test-class-high-speed"] } usbd-serial = "0.2" diff --git a/board/src/lib.rs b/board/src/lib.rs index 8973ee99..725f4532 100644 --- a/board/src/lib.rs +++ b/board/src/lib.rs @@ -21,7 +21,7 @@ mod ral_shim; /// and power settings for these variants. They're /// typically follow the recommendations in the /// data sheet. -#[derive(Debug, Clone, Copy, PartialEq, Eq)] +#[derive(Debug, Clone, Copy, PartialEq, Eq, defmt::Format)] #[non_exhaustive] pub enum RunMode { /// The fastest, highest-power mode. diff --git a/src/chip/drivers/adc.rs b/src/chip/drivers/adc.rs index 8973d5c2..16701b34 100644 --- a/src/chip/drivers/adc.rs +++ b/src/chip/drivers/adc.rs @@ -37,6 +37,7 @@ use eh02::adc::{Channel, OneShot}; /// The clock input for an ADC #[allow(non_camel_case_types)] +#[cfg_attr(feature = "defmt", derive(defmt::Format))] #[derive(Debug, Default, Clone, Copy, PartialEq, Eq)] pub enum ClockSelect { /// IPG clock @@ -49,6 +50,7 @@ pub enum ClockSelect { } /// How much to divide the clock input +#[cfg_attr(feature = "defmt", derive(defmt::Format))] #[derive(Debug, Default, Clone, Copy, PartialEq, Eq)] pub enum ClockDivision { /// Input clock / 1 @@ -63,6 +65,7 @@ pub enum ClockDivision { } /// Conversion speeds done by clock cycles +#[cfg_attr(feature = "defmt", derive(defmt::Format))] #[derive(Debug, Clone, Copy, PartialEq, Eq)] pub enum ConversionSpeed { /// 25 ADC clock cycles (24 on imxrt102x) @@ -76,6 +79,7 @@ pub enum ConversionSpeed { } /// Denotes how much hardware averaging to do +#[cfg_attr(feature = "defmt", derive(defmt::Format))] #[derive(Debug, Clone, Copy, PartialEq, Eq)] pub enum AveragingCount { /// 1 sample average. @@ -91,6 +95,7 @@ pub enum AveragingCount { } /// Specifies the resolution the ADC +#[cfg_attr(feature = "defmt", derive(defmt::Format))] #[derive(Debug, Clone, Copy, PartialEq, Eq)] pub enum ResolutionBits { /// 8 bit resolution. diff --git a/src/chip/drivers/ccm_10xx.rs b/src/chip/drivers/ccm_10xx.rs index 20e9c2bc..32d568f4 100644 --- a/src/chip/drivers/ccm_10xx.rs +++ b/src/chip/drivers/ccm_10xx.rs @@ -50,6 +50,7 @@ pub mod perclk_clk { use crate::ral::{self, ccm::CCM}; /// PERCLK clock selection. + #[cfg_attr(feature = "defmt", derive(defmt::Format))] #[derive(Debug, Clone, Copy, PartialEq, Eq)] #[repr(u32)] pub enum Selection { @@ -136,6 +137,7 @@ pub(crate) fn wait_handshake(ccm: &crate::ral::ccm::CCM) { /// /// Practically, this affects the processor behavior when you use WFI, WFE, or enter another /// low-power state. Low-power settings that aren't "run" halt the ARM SYSTICK peripheral. +#[cfg_attr(feature = "defmt", derive(defmt::Format))] #[derive(Debug, Clone, Copy, PartialEq, Eq)] #[repr(u32)] pub enum LowPowerMode { @@ -216,6 +218,7 @@ pub mod uart_clk { } /// UART clock selection. + #[cfg_attr(feature = "defmt", derive(defmt::Format))] #[derive(Debug, Clone, Copy, PartialEq, Eq)] #[repr(u32)] pub enum Selection { @@ -293,6 +296,7 @@ pub mod lpi2c_clk { } /// LPI2C clock selections. + #[cfg_attr(feature = "defmt", derive(defmt::Format))] #[derive(Debug, Clone, Copy, PartialEq, Eq)] #[repr(u32)] pub enum Selection { @@ -372,6 +376,7 @@ pub mod lpspi_clk { } /// LPSPI clock selections. + #[cfg_attr(feature = "defmt", derive(defmt::Format))] #[derive(Debug, Clone, Copy, PartialEq, Eq)] #[repr(u32)] pub enum Selection { @@ -458,7 +463,7 @@ macro_rules! ccm_flexio { } #[doc = concat!($desc, " clock selections.")] - #[derive(Debug, Clone, Copy, PartialEq, Eq)] + #[cfg_attr(feature = "defmt", derive(defmt::Format))] #[derive(Debug, Clone, Copy, PartialEq, Eq)] #[repr(u32)] pub enum Selection { /// Derive from PLL4. diff --git a/src/chip/drivers/ccm_10xx/ahb_clk.rs b/src/chip/drivers/ccm_10xx/ahb_clk.rs index c2b53f07..e1710072 100644 --- a/src/chip/drivers/ccm_10xx/ahb_clk.rs +++ b/src/chip/drivers/ccm_10xx/ahb_clk.rs @@ -30,6 +30,7 @@ pub fn divider(ccm: &CCM) -> u32 { } /// Peripheral clock selection. +#[cfg_attr(feature = "defmt", derive(defmt::Format))] #[derive(Debug, Clone, Copy, PartialEq, Eq)] #[repr(u32)] pub enum Selection { diff --git a/src/chip/drivers/ccm_10xx/clock_gate.rs b/src/chip/drivers/ccm_10xx/clock_gate.rs index 0753eb22..77243f2e 100644 --- a/src/chip/drivers/ccm_10xx/clock_gate.rs +++ b/src/chip/drivers/ccm_10xx/clock_gate.rs @@ -59,6 +59,7 @@ use crate::ral::{self, ccm::CCM}; /// A clock gate setting. +#[cfg_attr(feature = "defmt", derive(defmt::Format))] #[derive(Debug, Clone, Copy, PartialEq, Eq)] #[repr(u32)] pub enum Setting { @@ -87,6 +88,7 @@ impl Setting { } /// Clock gating register. +#[cfg_attr(feature = "defmt", derive(defmt::Format))] #[derive(Debug, Clone, Copy, PartialEq, Eq)] #[allow(unused)] #[repr(u8)] @@ -104,6 +106,7 @@ enum Register { use Register::*; /// Clock gate. +#[cfg_attr(feature = "defmt", derive(defmt::Format))] #[derive(Debug, Clone, Copy, PartialEq, Eq)] #[allow(unused)] #[repr(u8)] @@ -141,6 +144,7 @@ impl Gate { /// /// These are reachable through the various function /// provided in this module. +#[cfg_attr(feature = "defmt", derive(defmt::Format))] #[derive(Debug, PartialEq, Eq, Clone, Copy)] pub struct Locator { register: Register, diff --git a/src/chip/drivers/ccm_10xx/output_source.rs b/src/chip/drivers/ccm_10xx/output_source.rs index 98174e65..8a5a0021 100644 --- a/src/chip/drivers/ccm_10xx/output_source.rs +++ b/src/chip/drivers/ccm_10xx/output_source.rs @@ -64,6 +64,7 @@ pub mod clko1 { /// The CLKO1 output *pin* can represent either CLKO1 or CLKO2. /// Use [`set_output`] to set this configuration. #[repr(u32)] + #[cfg_attr(feature = "defmt", derive(defmt::Format))] #[derive(Debug, Clone, Copy, PartialEq, Eq)] pub enum Output { /// Use CLKO1's selection. diff --git a/src/chip/drivers/ccm_10xx/periph_clk2_sel.rs b/src/chip/drivers/ccm_10xx/periph_clk2_sel.rs index 51885db9..ffcd6335 100644 --- a/src/chip/drivers/ccm_10xx/periph_clk2_sel.rs +++ b/src/chip/drivers/ccm_10xx/periph_clk2_sel.rs @@ -5,6 +5,7 @@ use crate::ral::{self, ccm::CCM}; /// Peripheral CLK2 selection. +#[cfg_attr(feature = "defmt", derive(defmt::Format))] #[derive(Debug, Clone, Copy, PartialEq, Eq)] #[repr(u32)] pub enum Selection { diff --git a/src/chip/drivers/ccm_10xx/pre_periph_clk_pll1.rs b/src/chip/drivers/ccm_10xx/pre_periph_clk_pll1.rs index b480890c..c639228c 100644 --- a/src/chip/drivers/ccm_10xx/pre_periph_clk_pll1.rs +++ b/src/chip/drivers/ccm_10xx/pre_periph_clk_pll1.rs @@ -3,6 +3,7 @@ use crate::ral::{self, ccm::CCM}; /// Pre-peripheral clock selection. +#[cfg_attr(feature = "defmt", derive(defmt::Format))] #[derive(Debug, Clone, Copy, PartialEq, Eq)] #[repr(u32)] pub enum Selection { diff --git a/src/chip/drivers/ccm_10xx/pre_periph_clk_pll6.rs b/src/chip/drivers/ccm_10xx/pre_periph_clk_pll6.rs index 3a7ae0b8..26800bd8 100644 --- a/src/chip/drivers/ccm_10xx/pre_periph_clk_pll6.rs +++ b/src/chip/drivers/ccm_10xx/pre_periph_clk_pll6.rs @@ -3,6 +3,7 @@ use crate::ral::{self, ccm::CCM}; /// Pre-peripheral clock selection. +#[cfg_attr(feature = "defmt", derive(defmt::Format))] #[derive(Debug, Clone, Copy, PartialEq, Eq)] #[repr(u32)] pub enum Selection { diff --git a/src/chip/drivers/ccm_11xx/clock_gate.rs b/src/chip/drivers/ccm_11xx/clock_gate.rs index 31009f2c..6a979ebb 100644 --- a/src/chip/drivers/ccm_11xx/clock_gate.rs +++ b/src/chip/drivers/ccm_11xx/clock_gate.rs @@ -7,6 +7,7 @@ use crate::ral::{self, ccm::CCM}; /// A clock gate setting. +#[cfg_attr(feature = "defmt", derive(defmt::Format))] #[derive(Debug, Clone, Copy, PartialEq, Eq)] #[repr(u32)] pub enum Setting { @@ -32,6 +33,7 @@ impl Setting { } /// A clock gate locator. +#[cfg_attr(feature = "defmt", derive(defmt::Format))] #[derive(Debug, PartialEq, Eq, Clone, Copy)] pub struct Locator { offset: usize, diff --git a/src/chip/drivers/gpio.rs b/src/chip/drivers/gpio.rs index b7e5ceb7..5b238617 100644 --- a/src/chip/drivers/gpio.rs +++ b/src/chip/drivers/gpio.rs @@ -226,6 +226,7 @@ pub struct Input

{ unsafe impl Send for Input

{} /// Input interrupt triggers. +#[cfg_attr(feature = "defmt", derive(defmt::Format))] #[derive(Debug, Clone, Copy, PartialEq, Eq)] #[repr(u32)] pub enum Trigger { diff --git a/src/chip/drivers/rgpio.rs b/src/chip/drivers/rgpio.rs index 051a792f..63f62b6c 100644 --- a/src/chip/drivers/rgpio.rs +++ b/src/chip/drivers/rgpio.rs @@ -183,6 +183,7 @@ pub struct Input

{ unsafe impl Send for Input

{} /// Input interrupt triggers. +#[cfg_attr(feature = "defmt", derive(defmt::Format))] #[derive(Debug, Clone, Copy, PartialEq, Eq)] #[repr(u32)] pub enum Trigger { diff --git a/src/chip/drivers/snvs/srtc.rs b/src/chip/drivers/snvs/srtc.rs index 70e42cb5..d79ce8a3 100644 --- a/src/chip/drivers/snvs/srtc.rs +++ b/src/chip/drivers/snvs/srtc.rs @@ -90,6 +90,7 @@ impl Disabled { } /// Indicates the result of the `try_enable` method +#[cfg_attr(feature = "defmt", derive(defmt::Format))] #[derive(Debug)] pub enum EnabledState { /// The SRTC was already enabled, and it's currently counting from `seconds` @@ -224,3 +225,10 @@ impl fmt::Debug for Srtc { // very basic, just to prevent compile errors if user puts it in a struct } } + +#[cfg(feature = "defmt")] +impl defmt::Format for Srtc { + fn format(&self, f: defmt::Formatter) { + defmt::write!(f, "SRTC {{ ... }}") + } +} diff --git a/src/chip/drivers/tempmon.rs b/src/chip/drivers/tempmon.rs index 204d791c..c7abe805 100644 --- a/src/chip/drivers/tempmon.rs +++ b/src/chip/drivers/tempmon.rs @@ -99,6 +99,7 @@ use crate::ral; /// /// If you receive this error, `power_up()` the temperature monitor first, /// and try again. +#[cfg_attr(feature = "defmt", derive(defmt::Format))] #[derive(Debug, Clone, Copy, PartialEq, Eq)] pub struct PowerDownError(()); @@ -143,6 +144,19 @@ impl core::fmt::Debug for TempMon { } } +#[cfg(feature = "defmt")] +impl defmt::Format for TempMon { + fn format(&self, f: defmt::Formatter) { + defmt::write!( + f, + "TempMon {{ scaler: {}, hot_count: {}, hot_temp: {} }}", + self.scaler, + self.hot_count, + self.hot_temp, + ) + } +} + impl TempMon { /// Initialize and create the temperature monitor. pub fn new(tempmon: ral::tempmon::TEMPMON) -> Self { diff --git a/src/chip/drivers/trng.rs b/src/chip/drivers/trng.rs index 6ea9f65c..0f149277 100644 --- a/src/chip/drivers/trng.rs +++ b/src/chip/drivers/trng.rs @@ -54,6 +54,7 @@ use crate::ral::trng; use crate::ral::{modify_reg, read_reg, write_reg}; /// TRNG sampling mode +#[cfg_attr(feature = "defmt", derive(defmt::Format))] #[derive(Copy, Clone, Debug, PartialEq, Eq)] #[repr(u32)] pub enum SampleMode { @@ -96,12 +97,20 @@ impl fmt::Debug for Trng { } } +#[cfg(feature = "defmt")] +impl defmt::Format for Trng { + fn format(&self, f: defmt::Formatter) { + defmt::write!(f, "Trng {{ block: {}, index: {} }}", self.block, self.index) + } +} + /// The number of retry attempts. /// /// Describes the number of times to retry /// after a test failure before an error is declared. Valid /// range `1..=15`. The default retry count is the largest /// possible value. +#[cfg_attr(feature = "defmt", derive(defmt::Format))] #[derive(Debug, Clone, Copy, PartialEq, Eq)] pub struct RetryCount(u32); @@ -332,11 +341,13 @@ impl rand_core::RngCore for RngCoreWrapper { } /// A TRNG error occurred, such as a statistical test failing. +#[cfg_attr(feature = "defmt", derive(defmt::Format))] #[derive(Copy, Clone, Debug, PartialEq, Eq)] pub struct Error(pub ErrorFlags); bitflags::bitflags! { /// Specific errors that may occur during entropy generation + #[cfg_attr(feature = "defmt", derive(defmt::Format))] pub struct ErrorFlags : u32 { // STATUS register starts here (automatically set from bits) /// 1-bit run sampling 0s test failed diff --git a/src/chip/imxrt1010.rs b/src/chip/imxrt1010.rs index 9d956767..8b7982bc 100644 --- a/src/chip/imxrt1010.rs +++ b/src/chip/imxrt1010.rs @@ -99,6 +99,7 @@ pub(crate) mod config { pub(crate) mod clko { /// CLKO1 output clock selections. #[repr(u32)] + #[cfg_attr(feature = "defmt", derive(defmt::Format))] #[derive(Debug, Clone, Copy, PartialEq, Eq)] pub enum Clko1Selection { /// PLL3 divided by 2. @@ -119,6 +120,7 @@ pub(crate) mod config { /// CLKO2 output clock selections. #[repr(u32)] + #[cfg_attr(feature = "defmt", derive(defmt::Format))] #[derive(Debug, Clone, Copy, PartialEq, Eq)] pub enum Clko2Selection { /// LPI2C clock root. diff --git a/src/chip/imxrt1020.rs b/src/chip/imxrt1020.rs index 04426515..3e31e30e 100644 --- a/src/chip/imxrt1020.rs +++ b/src/chip/imxrt1020.rs @@ -115,6 +115,7 @@ pub(crate) mod config { pub(crate) mod clko { /// CLKO1 output clock selections. #[repr(u32)] + #[cfg_attr(feature = "defmt", derive(defmt::Format))] #[derive(Debug, Clone, Copy, PartialEq, Eq)] pub enum Clko1Selection { /// PLL3 divided by 2. @@ -137,6 +138,7 @@ pub(crate) mod config { /// CLKO2 output clock selections. #[repr(u32)] + #[cfg_attr(feature = "defmt", derive(defmt::Format))] #[derive(Debug, Clone, Copy, PartialEq, Eq)] pub enum Clko2Selection { /// USDHC1 clock root. diff --git a/src/chip/imxrt1060.rs b/src/chip/imxrt1060.rs index 85d1774c..2fd088fa 100644 --- a/src/chip/imxrt1060.rs +++ b/src/chip/imxrt1060.rs @@ -119,12 +119,14 @@ pub(crate) mod config { pub(crate) mod clko { /// CLKO1 output clock selections. // #[repr(u32)] + #[cfg_attr(feature = "defmt", derive(defmt::Format))] #[derive(Debug, Clone, Copy, PartialEq, Eq)] pub enum Clko1Selection {} /// CLKO2 output clock selections. // #[repr(u32)] + #[cfg_attr(feature = "defmt", derive(defmt::Format))] #[derive(Debug, Clone, Copy, PartialEq, Eq)] pub enum Clko2Selection {} diff --git a/src/chip/imxrt1170.rs b/src/chip/imxrt1170.rs index 4906ca9c..22ff6468 100644 --- a/src/chip/imxrt1170.rs +++ b/src/chip/imxrt1170.rs @@ -37,6 +37,7 @@ pub(crate) mod config { pub(crate) mod clko { /// CLKO1 output clock selections. #[repr(u32)] + #[cfg_attr(feature = "defmt", derive(defmt::Format))] #[derive(Debug, Clone, Copy, PartialEq, Eq)] pub enum Clko1Selection { /// 48MHz RC oscillator, divided by 2. @@ -59,6 +60,7 @@ pub(crate) mod config { /// CLKO2 output clock selections. #[repr(u32)] + #[cfg_attr(feature = "defmt", derive(defmt::Format))] #[derive(Debug, Clone, Copy, PartialEq, Eq)] pub enum Clko2Selection { /// 48MHz RC oscillator, divided by 2. diff --git a/src/common/flexpwm.rs b/src/common/flexpwm.rs index f3882742..7c55a0c7 100644 --- a/src/common/flexpwm.rs +++ b/src/common/flexpwm.rs @@ -504,6 +504,7 @@ impl Submodule { /// PWM clock prescaler. /// /// Affects all timing, except for the glitch filters. +#[cfg_attr(feature = "defmt", derive(defmt::Format))] #[derive(Debug, Clone, Copy, PartialEq, Eq)] #[repr(u16)] pub enum Prescaler { @@ -533,6 +534,7 @@ impl Prescaler { } /// Describes how PWM channels A and B operate. +#[cfg_attr(feature = "defmt", derive(defmt::Format))] #[derive(Debug, Clone, Copy, PartialEq, Eq)] #[repr(u16)] pub enum PairOperation { @@ -543,6 +545,7 @@ pub enum PairOperation { } /// PWM input clock selection. +#[cfg_attr(feature = "defmt", derive(defmt::Format))] #[derive(Debug, Clone, Copy, PartialEq, Eq)] #[repr(u16)] pub enum ClockSelect { @@ -563,6 +566,7 @@ pub enum ClockSelect { /// /// Use the associated methods to simply define `ReloadCycle` /// values. +#[cfg_attr(feature = "defmt", derive(defmt::Format))] #[derive(Debug, Clone, Copy, PartialEq, Eq)] pub enum LoadMode { /// Reload on the next cycle after `LDOK` is set. @@ -673,6 +677,7 @@ bitflags::bitflags! { /// These value registers describe when PWM counters reset, and when outputs /// turn on and off. Consider using more descriptive constants, enums, and /// const functions to describe these values. +#[cfg_attr(feature = "defmt", derive(defmt::Format))] #[derive(Debug, Clone, Copy, PartialEq, Eq)] pub enum ValueRegister { /// The [`HALF_RELOAD_VALUE_REGISTER`]. @@ -723,6 +728,7 @@ pub const fn turn_off(channel: Channel) -> ValueRegister { } /// PWM channels. +#[cfg_attr(feature = "defmt", derive(defmt::Format))] #[derive(Debug, Clone, Copy, PartialEq, Eq)] pub enum Channel { /// Channel A. diff --git a/src/common/gpt.rs b/src/common/gpt.rs index 83bf297c..a8f88fe0 100644 --- a/src/common/gpt.rs +++ b/src/common/gpt.rs @@ -122,6 +122,7 @@ pub type Gpt1 = Gpt<1>; pub type Gpt2 = Gpt<2>; /// GPT clock source. +#[cfg_attr(feature = "defmt", derive(defmt::Format))] #[derive(Debug, Clone, Copy, PartialEq, Eq)] #[repr(u32)] pub enum ClockSource { @@ -140,6 +141,7 @@ pub enum ClockSource { } /// An output compare register (OCR). +#[cfg_attr(feature = "defmt", derive(defmt::Format))] #[derive(Clone, Copy, PartialEq, Eq, Debug)] #[repr(usize)] pub enum OutputCompareRegister { @@ -151,6 +153,7 @@ pub enum OutputCompareRegister { OCR3 = 2, } +#[cfg_attr(feature = "defmt", derive(defmt::Format))] #[derive(Debug, Clone, Copy, PartialEq, Eq)] /// Possible modes of the GPT. pub enum Mode { diff --git a/src/common/lpi2c.rs b/src/common/lpi2c.rs index 996db7ef..50e920ec 100644 --- a/src/common/lpi2c.rs +++ b/src/common/lpi2c.rs @@ -61,6 +61,7 @@ use crate::ral; use eh02::blocking::i2c as blocking; /// Data direction. +#[cfg_attr(feature = "defmt", derive(defmt::Format))] #[derive(Debug, Clone, Copy, PartialEq, Eq)] pub enum Direction { /// Transmit direction (leaving the peripheral). @@ -330,6 +331,7 @@ impl Lpi2c { } /// The number of words in each FIFO. +#[cfg_attr(feature = "defmt", derive(defmt::Format))] #[derive(Debug, Clone, Copy, PartialEq, Eq)] pub struct ControllerFifoStatus { /// Number of words in the receive FIFO. @@ -543,6 +545,7 @@ bitflags::bitflags! { } /// (N)ACK responses. +#[cfg_attr(feature = "defmt", derive(defmt::Format))] #[derive(Debug, Clone, Copy, PartialEq, Eq)] pub enum Response { /// Response is acknowledge. @@ -552,6 +555,7 @@ pub enum Response { } /// LPI2C controller commands. +#[cfg_attr(feature = "defmt", derive(defmt::Format))] #[derive(Debug, Clone, Copy, PartialEq, Eq)] #[non_exhaustive] pub enum ControllerCommand { @@ -909,6 +913,7 @@ mod transaction { /// less than eight bits are truncated by the implementation. You're /// responsible for making sure that these parameters meet their timing /// parameter restrictions. +#[cfg_attr(feature = "defmt", derive(defmt::Format))] #[derive(Debug, Clone, Copy, PartialEq, Eq)] pub struct ClockConfiguration { /// Clock high period. @@ -946,6 +951,7 @@ pub struct ClockConfiguration { /// Source clock prescaler. /// /// Affects all timing, except for the glitch filters. +#[cfg_attr(feature = "defmt", derive(defmt::Format))] #[derive(Debug, Clone, Copy, PartialEq, Eq)] #[repr(u32)] pub enum Prescaler { @@ -980,6 +986,7 @@ const _: () = assert!(Prescaler::Prescaler1.divider() == 1); const _: () = assert!(Prescaler::Prescaler128.divider() == 128); /// Clock speed. +#[cfg_attr(feature = "defmt", derive(defmt::Format))] #[derive(Clone, Copy, Debug)] pub enum ClockSpeed { /// 100 KHz. @@ -1006,6 +1013,7 @@ impl ClockSpeed { /// but you can override this after construction. /// /// The simplest way to construct a `Timing` is to use [`ideal()`](Timing::ideal). +#[cfg_attr(feature = "defmt", derive(defmt::Format))] #[derive(Debug, Clone, Copy, PartialEq, Eq)] pub struct Timing { clock_configuration: ClockConfiguration, diff --git a/src/common/lpspi.rs b/src/common/lpspi.rs index 5078e6d3..55e99fca 100644 --- a/src/common/lpspi.rs +++ b/src/common/lpspi.rs @@ -94,6 +94,7 @@ use crate::ral; pub use eh02::spi::{Mode, Phase, Polarity, MODE_0, MODE_1, MODE_2, MODE_3}; /// Data direction. +#[cfg_attr(feature = "defmt", derive(defmt::Format))] #[derive(Debug, Clone, Copy, PartialEq, Eq)] pub enum Direction { /// Transmit direction (leaving the peripheral). @@ -103,6 +104,7 @@ pub enum Direction { } /// Bit order. +#[cfg_attr(feature = "defmt", derive(defmt::Format))] #[derive(Debug, Default, Clone, Copy, PartialEq, Eq)] #[repr(u32)] pub enum BitOrder { @@ -114,6 +116,7 @@ pub enum BitOrder { } /// Receive sample point behavior. +#[cfg_attr(feature = "defmt", derive(defmt::Format))] #[derive(Debug, Clone, Copy, PartialEq, Eq)] pub enum SamplePoint { /// Input data is sampled on SCK edge. @@ -123,6 +126,7 @@ pub enum SamplePoint { } /// Possible errors when interfacing the LPSPI. +#[cfg_attr(feature = "defmt", derive(defmt::Format))] #[derive(Debug, Clone, Copy, PartialEq, Eq)] pub enum LpspiError { /// The transaction frame size is incorrect. @@ -1046,6 +1050,7 @@ impl Status { } /// The number of words in each FIFO. +#[cfg_attr(feature = "defmt", derive(defmt::Format))] #[derive(Debug, Clone, Copy, PartialEq, Eq)] pub struct FifoStatus { /// Number of words in the receive FIFO. diff --git a/src/common/lpuart.rs b/src/common/lpuart.rs index 31a19b4a..2fb847ef 100644 --- a/src/common/lpuart.rs +++ b/src/common/lpuart.rs @@ -90,6 +90,7 @@ pub struct Lpuart { } /// Serial direction. +#[cfg_attr(feature = "defmt", derive(defmt::Format))] #[derive(Debug, Clone, Copy, PartialEq, Eq)] pub enum Direction { /// Transfer direction (leaving the peripheral). @@ -531,6 +532,7 @@ impl<'a, const N: u8> Disabled<'a, N> { /// const UART_CLOCK_HZ: u32 = 24_000_000; /// const BAUD: Baud = Baud::compute(UART_CLOCK_HZ, 115200); /// ``` +#[cfg_attr(feature = "defmt", derive(defmt::Format))] #[derive(Debug, Clone, Copy, PartialEq, Eq)] pub struct Baud { /// Oversampling rate. @@ -621,6 +623,7 @@ impl Baud { /// [`Lpuart::parity`](crate::lpuart::Lpuart::parity) for more information. /// Consider using the associated constants to quickly specify /// parity bits. +#[cfg_attr(feature = "defmt", derive(defmt::Format))] #[derive(Debug, Clone, Copy, PartialEq, Eq)] #[repr(u32)] pub enum Parity { @@ -722,6 +725,7 @@ impl Interrupts { /// The data contains flags, which may indicate errors /// in the received data. If the flags indicate value data, /// use `u8::from` to convert the data into its raw byte. +#[cfg_attr(feature = "defmt", derive(defmt::Format))] #[derive(Clone, Copy, Debug, PartialEq, Eq)] #[repr(transparent)] pub struct ReadData(u32); @@ -876,6 +880,7 @@ impl Status { /// /// See [`Lpuart::enable_fifo`](crate::lpuart::Disabled::enable_fifo) for more /// information. +#[cfg_attr(feature = "defmt", derive(defmt::Format))] #[derive(Debug, Clone, Copy)] pub struct Watermark { direction: Direction,