From 95289cffd555c271461c87dfcf7a22bfb4f6e1bb Mon Sep 17 00:00:00 2001 From: Ian McIntyre Date: Fri, 6 Sep 2024 07:38:59 -0400 Subject: [PATCH] Remove NVIC, SCB from the 1176 The 1176 imxrt-ral modules no longer provide an API for the NVIC or SCB. It's the same process as b1fee46, but applied to the 1176 modules. I re-introduced core interrupts by attaching them to the miscellaneous control module (MCM). All separate GPC peripheral blocks are logically within a single 'GPC' space, so selecting the standby sub-module was an arbitrary decision. Notice that this commit marks the GPU2D interrupt as reserved. This is intentional; the SVDs do not describe a GPU2D peripheral, so imxrt-ral doesn't have a corresponding module. This interrupt probably piggy-packed on the NVIC. We can re-introduce that interrupt when we describe the GPU2D peripheral. --- CHANGELOG.md | 7 + devices/imxrt1176_cm4.yaml | 18 + devices/imxrt1176_cm7.yaml | 24 + src/blocks/imxrt1176_cm4/nvic.rs | 1661 ----------- src/blocks/imxrt1176_cm7/system_control.rs | 2944 -------------------- src/imxrt1176_cm4.rs | 160 +- src/imxrt1176_cm4.x | 19 - src/imxrt1176_cm7.rs | 168 +- src/imxrt1176_cm7.x | 16 - 9 files changed, 84 insertions(+), 4933 deletions(-) delete mode 100644 src/blocks/imxrt1176_cm4/nvic.rs delete mode 100644 src/blocks/imxrt1176_cm7/system_control.rs diff --git a/CHANGELOG.md b/CHANGELOG.md index 8c57eb83541e..66c74c7c4494 100644 --- a/CHANGELOG.md +++ b/CHANGELOG.md @@ -2,6 +2,13 @@ ## [Unreleased] +**BREAKING** Remove the NVIC and SCB peripherals from the 1176. If you need an +API for Cortex-M registers, check out the +[`cortex-m`][https://crates.io/crates/cortex-m] crate. + +**BREAKING** The 1176 GPU2D interrupt is marked as reserved, and it's not +available in the `Interrupt` enum. + **BREAKING** In the 1176 API, there is only one SAI module. All SAI instances, including those that only have a single channel, now appear to support multiple channels. The user is responsible for making sure their SAI instance can diff --git a/devices/imxrt1176_cm4.yaml b/devices/imxrt1176_cm4.yaml index a232c936b048..8a453d69c74e 100644 --- a/devices/imxrt1176_cm4.yaml +++ b/devices/imxrt1176_cm4.yaml @@ -49,6 +49,10 @@ _delete: - USB_OTG2 - USBNC_OTG2 + # Do you need these? Check out the cortex-m crate (v0.7). + - NVIC + - SystemControl + _modify: _peripherals: CM7_GPIO2: @@ -193,3 +197,17 @@ PWM?: bitOffset: 2 bitWidth: 1 access: read-write + +MCM: + _add: + _interrupts: + CORE: + description: CORE + value: 19 + +GPC_STBY_CTRL: + _add: + _interrupts: + GPC: + description: GPC + value: 117 diff --git a/devices/imxrt1176_cm7.yaml b/devices/imxrt1176_cm7.yaml index da3e952cfb40..fd333345ce15 100644 --- a/devices/imxrt1176_cm7.yaml +++ b/devices/imxrt1176_cm7.yaml @@ -10,6 +10,10 @@ _delete: - USB_OTG2 - USBNC_OTG2 + # Do you need these? Check out the cortex-m crate (v0.7). + - NVIC + - SystemControl + _include: - "common_patches/dma0/tcd_cluster.yaml" - "common_patches/usb1.yaml" @@ -133,3 +137,23 @@ PWM?: bitOffset: 2 bitWidth: 1 access: read-write + +CM7_MCM: + _add: + _interrupts: + CTI_TRIGGER_OUT0: + description: CTI_TRIGGER_OUT0 + value: 17 + CTI_TRIGGER_OUT1: + description: CTI_TRIGGER_OUT1 + value: 18 + CORE: + description: CORE + value: 19 + +GPC_STBY_CTRL: + _add: + _interrupts: + GPC: + description: GPC + value: 117 diff --git a/src/blocks/imxrt1176_cm4/nvic.rs b/src/blocks/imxrt1176_cm4/nvic.rs deleted file mode 100644 index 74630fc25ac7..000000000000 --- a/src/blocks/imxrt1176_cm4/nvic.rs +++ /dev/null @@ -1,1661 +0,0 @@ -#[doc = "Nested Vectored Interrupt Controller"] -#[repr(C)] -pub struct RegisterBlock { - #[doc = "Interrupt Set Enable Register n"] - pub NVICISER0: crate::RWRegister, - #[doc = "Interrupt Set Enable Register n"] - pub NVICISER1: crate::RWRegister, - #[doc = "Interrupt Set Enable Register n"] - pub NVICISER2: crate::RWRegister, - #[doc = "Interrupt Set Enable Register n"] - pub NVICISER3: crate::RWRegister, - _reserved0: [u8; 0x70], - #[doc = "Interrupt Clear Enable Register n"] - pub NVICICER0: crate::RWRegister, - #[doc = "Interrupt Clear Enable Register n"] - pub NVICICER1: crate::RWRegister, - #[doc = "Interrupt Clear Enable Register n"] - pub NVICICER2: crate::RWRegister, - #[doc = "Interrupt Clear Enable Register n"] - pub NVICICER3: crate::RWRegister, - _reserved1: [u8; 0x70], - #[doc = "Interrupt Set Pending Register n"] - pub NVICISPR0: crate::RWRegister, - #[doc = "Interrupt Set Pending Register n"] - pub NVICISPR1: crate::RWRegister, - #[doc = "Interrupt Set Pending Register n"] - pub NVICISPR2: crate::RWRegister, - #[doc = "Interrupt Set Pending Register n"] - pub NVICISPR3: crate::RWRegister, - _reserved2: [u8; 0x70], - #[doc = "Interrupt Clear Pending Register n"] - pub NVICICPR0: crate::RWRegister, - #[doc = "Interrupt Clear Pending Register n"] - pub NVICICPR1: crate::RWRegister, - #[doc = "Interrupt Clear Pending Register n"] - pub NVICICPR2: crate::RWRegister, - #[doc = "Interrupt Clear Pending Register n"] - pub NVICICPR3: crate::RWRegister, - _reserved3: [u8; 0x70], - #[doc = "Interrupt Active bit Register n"] - pub NVICIABR0: crate::RWRegister, - #[doc = "Interrupt Active bit Register n"] - pub NVICIABR1: crate::RWRegister, - #[doc = "Interrupt Active bit Register n"] - pub NVICIABR2: crate::RWRegister, - #[doc = "Interrupt Active bit Register n"] - pub NVICIABR3: crate::RWRegister, - _reserved4: [u8; 0xf0], - #[doc = "Interrupt Priority Register 0"] - pub NVICIP0: crate::RWRegister, - #[doc = "Interrupt Priority Register 1"] - pub NVICIP1: crate::RWRegister, - #[doc = "Interrupt Priority Register 2"] - pub NVICIP2: crate::RWRegister, - #[doc = "Interrupt Priority Register 3"] - pub NVICIP3: crate::RWRegister, - #[doc = "Interrupt Priority Register 4"] - pub NVICIP4: crate::RWRegister, - #[doc = "Interrupt Priority Register 5"] - pub NVICIP5: crate::RWRegister, - #[doc = "Interrupt Priority Register 6"] - pub NVICIP6: crate::RWRegister, - #[doc = "Interrupt Priority Register 7"] - pub NVICIP7: crate::RWRegister, - #[doc = "Interrupt Priority Register 8"] - pub NVICIP8: crate::RWRegister, - #[doc = "Interrupt Priority Register 9"] - pub NVICIP9: crate::RWRegister, - #[doc = "Interrupt Priority Register 10"] - pub NVICIP10: crate::RWRegister, - #[doc = "Interrupt Priority Register 11"] - pub NVICIP11: crate::RWRegister, - #[doc = "Interrupt Priority Register 12"] - pub NVICIP12: crate::RWRegister, - #[doc = "Interrupt Priority Register 13"] - pub NVICIP13: crate::RWRegister, - #[doc = "Interrupt Priority Register 14"] - pub NVICIP14: crate::RWRegister, - #[doc = "Interrupt Priority Register 15"] - pub NVICIP15: crate::RWRegister, - #[doc = "Interrupt Priority Register 16"] - pub NVICIP16: crate::RWRegister, - #[doc = "Interrupt Priority Register 17"] - pub NVICIP17: crate::RWRegister, - #[doc = "Interrupt Priority Register 18"] - pub NVICIP18: crate::RWRegister, - #[doc = "Interrupt Priority Register 19"] - pub NVICIP19: crate::RWRegister, - #[doc = "Interrupt Priority Register 20"] - pub NVICIP20: crate::RWRegister, - #[doc = "Interrupt Priority Register 21"] - pub NVICIP21: crate::RWRegister, - #[doc = "Interrupt Priority Register 22"] - pub NVICIP22: crate::RWRegister, - #[doc = "Interrupt Priority Register 23"] - pub NVICIP23: crate::RWRegister, - #[doc = "Interrupt Priority Register 24"] - pub NVICIP24: crate::RWRegister, - #[doc = "Interrupt Priority Register 25"] - pub NVICIP25: crate::RWRegister, - #[doc = "Interrupt Priority Register 26"] - pub NVICIP26: crate::RWRegister, - #[doc = "Interrupt Priority Register 27"] - pub NVICIP27: crate::RWRegister, - #[doc = "Interrupt Priority Register 28"] - pub NVICIP28: crate::RWRegister, - #[doc = "Interrupt Priority Register 29"] - pub NVICIP29: crate::RWRegister, - #[doc = "Interrupt Priority Register 30"] - pub NVICIP30: crate::RWRegister, - #[doc = "Interrupt Priority Register 31"] - pub NVICIP31: crate::RWRegister, - #[doc = "Interrupt Priority Register 32"] - pub NVICIP32: crate::RWRegister, - #[doc = "Interrupt Priority Register 33"] - pub NVICIP33: crate::RWRegister, - #[doc = "Interrupt Priority Register 34"] - pub NVICIP34: crate::RWRegister, - #[doc = "Interrupt Priority Register 35"] - pub NVICIP35: crate::RWRegister, - #[doc = "Interrupt Priority Register 36"] - pub NVICIP36: crate::RWRegister, - #[doc = "Interrupt Priority Register 37"] - pub NVICIP37: crate::RWRegister, - #[doc = "Interrupt Priority Register 38"] - pub NVICIP38: crate::RWRegister, - #[doc = "Interrupt Priority Register 39"] - pub NVICIP39: crate::RWRegister, - #[doc = "Interrupt Priority Register 40"] - pub NVICIP40: crate::RWRegister, - #[doc = "Interrupt Priority Register 41"] - pub NVICIP41: crate::RWRegister, - #[doc = "Interrupt Priority Register 42"] - pub NVICIP42: crate::RWRegister, - #[doc = "Interrupt Priority Register 43"] - pub NVICIP43: crate::RWRegister, - #[doc = "Interrupt Priority Register 44"] - pub NVICIP44: crate::RWRegister, - #[doc = "Interrupt Priority Register 45"] - pub NVICIP45: crate::RWRegister, - #[doc = "Interrupt Priority Register 46"] - pub NVICIP46: crate::RWRegister, - #[doc = "Interrupt Priority Register 47"] - pub NVICIP47: crate::RWRegister, - #[doc = "Interrupt Priority Register 48"] - pub NVICIP48: crate::RWRegister, - #[doc = "Interrupt Priority Register 49"] - pub NVICIP49: crate::RWRegister, - #[doc = "Interrupt Priority Register 50"] - pub NVICIP50: crate::RWRegister, - #[doc = "Interrupt Priority Register 51"] - pub NVICIP51: crate::RWRegister, - #[doc = "Interrupt Priority Register 52"] - pub NVICIP52: crate::RWRegister, - #[doc = "Interrupt Priority Register 53"] - pub NVICIP53: crate::RWRegister, - #[doc = "Interrupt Priority Register 54"] - pub NVICIP54: crate::RWRegister, - #[doc = "Interrupt Priority Register 55"] - pub NVICIP55: crate::RWRegister, - #[doc = "Interrupt Priority Register 56"] - pub NVICIP56: crate::RWRegister, - #[doc = "Interrupt Priority Register 57"] - pub NVICIP57: crate::RWRegister, - #[doc = "Interrupt Priority Register 58"] - pub NVICIP58: crate::RWRegister, - #[doc = "Interrupt Priority Register 59"] - pub NVICIP59: crate::RWRegister, - #[doc = "Interrupt Priority Register 60"] - pub NVICIP60: crate::RWRegister, - #[doc = "Interrupt Priority Register 61"] - pub NVICIP61: crate::RWRegister, - #[doc = "Interrupt Priority Register 62"] - pub NVICIP62: crate::RWRegister, - #[doc = "Interrupt Priority Register 63"] - pub NVICIP63: crate::RWRegister, - #[doc = "Interrupt Priority Register 64"] - pub NVICIP64: crate::RWRegister, - #[doc = "Interrupt Priority Register 65"] - pub NVICIP65: crate::RWRegister, - #[doc = "Interrupt Priority Register 66"] - pub NVICIP66: crate::RWRegister, - #[doc = "Interrupt Priority Register 67"] - pub NVICIP67: crate::RWRegister, - #[doc = "Interrupt Priority Register 68"] - pub NVICIP68: crate::RWRegister, - #[doc = "Interrupt Priority Register 69"] - pub NVICIP69: crate::RWRegister, - #[doc = "Interrupt Priority Register 70"] - pub NVICIP70: crate::RWRegister, - #[doc = "Interrupt Priority Register 71"] - pub NVICIP71: crate::RWRegister, - #[doc = "Interrupt Priority Register 72"] - pub NVICIP72: crate::RWRegister, - #[doc = "Interrupt Priority Register 73"] - pub NVICIP73: crate::RWRegister, - #[doc = "Interrupt Priority Register 74"] - pub NVICIP74: crate::RWRegister, - #[doc = "Interrupt Priority Register 75"] - pub NVICIP75: crate::RWRegister, - #[doc = "Interrupt Priority Register 76"] - pub NVICIP76: crate::RWRegister, - #[doc = "Interrupt Priority Register 77"] - pub NVICIP77: crate::RWRegister, - #[doc = "Interrupt Priority Register 78"] - pub NVICIP78: crate::RWRegister, - #[doc = "Interrupt Priority Register 79"] - pub NVICIP79: crate::RWRegister, - #[doc = "Interrupt Priority Register 80"] - pub NVICIP80: crate::RWRegister, - #[doc = "Interrupt Priority Register 81"] - pub NVICIP81: crate::RWRegister, - #[doc = "Interrupt Priority Register 82"] - pub NVICIP82: crate::RWRegister, - #[doc = "Interrupt Priority Register 83"] - pub NVICIP83: crate::RWRegister, - #[doc = "Interrupt Priority Register 84"] - pub NVICIP84: crate::RWRegister, - #[doc = "Interrupt Priority Register 85"] - pub NVICIP85: crate::RWRegister, - #[doc = "Interrupt Priority Register 86"] - pub NVICIP86: crate::RWRegister, - #[doc = "Interrupt Priority Register 87"] - pub NVICIP87: crate::RWRegister, - #[doc = "Interrupt Priority Register 88"] - pub NVICIP88: crate::RWRegister, - #[doc = "Interrupt Priority Register 89"] - pub NVICIP89: crate::RWRegister, - #[doc = "Interrupt Priority Register 90"] - pub NVICIP90: crate::RWRegister, - #[doc = "Interrupt Priority Register 91"] - pub NVICIP91: crate::RWRegister, - #[doc = "Interrupt Priority Register 92"] - pub NVICIP92: crate::RWRegister, - #[doc = "Interrupt Priority Register 93"] - pub NVICIP93: crate::RWRegister, - #[doc = "Interrupt Priority Register 94"] - pub NVICIP94: crate::RWRegister, - #[doc = "Interrupt Priority Register 95"] - pub NVICIP95: crate::RWRegister, - #[doc = "Interrupt Priority Register 96"] - pub NVICIP96: crate::RWRegister, - #[doc = "Interrupt Priority Register 97"] - pub NVICIP97: crate::RWRegister, - #[doc = "Interrupt Priority Register 98"] - pub NVICIP98: crate::RWRegister, - #[doc = "Interrupt Priority Register 99"] - pub NVICIP99: crate::RWRegister, - #[doc = "Interrupt Priority Register 100"] - pub NVICIP100: crate::RWRegister, - #[doc = "Interrupt Priority Register 101"] - pub NVICIP101: crate::RWRegister, - #[doc = "Interrupt Priority Register 102"] - pub NVICIP102: crate::RWRegister, - #[doc = "Interrupt Priority Register 103"] - pub NVICIP103: crate::RWRegister, - #[doc = "Interrupt Priority Register 104"] - pub NVICIP104: crate::RWRegister, - #[doc = "Interrupt Priority Register 105"] - pub NVICIP105: crate::RWRegister, - _reserved5: [u8; 0x0a96], - #[doc = "Software Trigger Interrupt Register"] - pub NVICSTIR: crate::RWRegister, -} -#[doc = "Interrupt Set Enable Register n"] -pub mod NVICISER0 { - #[doc = "Interrupt set enable bits"] - pub mod SETENA { - pub const offset: u32 = 0; - pub const mask: u32 = 0xffff_ffff << offset; - pub mod R {} - pub mod W {} - pub mod RW {} - } -} -#[doc = "Interrupt Set Enable Register n"] -pub mod NVICISER1 { - #[doc = "Interrupt set enable bits"] - pub mod SETENA { - pub const offset: u32 = 0; - pub const mask: u32 = 0xffff_ffff << offset; - pub mod R {} - pub mod W {} - pub mod RW {} - } -} -#[doc = "Interrupt Set Enable Register n"] -pub mod NVICISER2 { - #[doc = "Interrupt set enable bits"] - pub mod SETENA { - pub const offset: u32 = 0; - pub const mask: u32 = 0xffff_ffff << offset; - pub mod R {} - pub mod W {} - pub mod RW {} - } -} -#[doc = "Interrupt Set Enable Register n"] -pub mod NVICISER3 { - #[doc = "Interrupt set enable bits"] - pub mod SETENA { - pub const offset: u32 = 0; - pub const mask: u32 = 0xffff_ffff << offset; - pub mod R {} - pub mod W {} - pub mod RW {} - } -} -#[doc = "Interrupt Clear Enable Register n"] -pub mod NVICICER0 { - #[doc = "Interrupt clear-enable bits"] - pub mod CLRENA { - pub const offset: u32 = 0; - pub const mask: u32 = 0xffff_ffff << offset; - pub mod R {} - pub mod W {} - pub mod RW {} - } -} -#[doc = "Interrupt Clear Enable Register n"] -pub mod NVICICER1 { - #[doc = "Interrupt clear-enable bits"] - pub mod CLRENA { - pub const offset: u32 = 0; - pub const mask: u32 = 0xffff_ffff << offset; - pub mod R {} - pub mod W {} - pub mod RW {} - } -} -#[doc = "Interrupt Clear Enable Register n"] -pub mod NVICICER2 { - #[doc = "Interrupt clear-enable bits"] - pub mod CLRENA { - pub const offset: u32 = 0; - pub const mask: u32 = 0xffff_ffff << offset; - pub mod R {} - pub mod W {} - pub mod RW {} - } -} -#[doc = "Interrupt Clear Enable Register n"] -pub mod NVICICER3 { - #[doc = "Interrupt clear-enable bits"] - pub mod CLRENA { - pub const offset: u32 = 0; - pub const mask: u32 = 0xffff_ffff << offset; - pub mod R {} - pub mod W {} - pub mod RW {} - } -} -#[doc = "Interrupt Set Pending Register n"] -pub mod NVICISPR0 { - #[doc = "Interrupt set-pending bits"] - pub mod SETPEND { - pub const offset: u32 = 0; - pub const mask: u32 = 0xffff_ffff << offset; - pub mod R {} - pub mod W {} - pub mod RW {} - } -} -#[doc = "Interrupt Set Pending Register n"] -pub mod NVICISPR1 { - #[doc = "Interrupt set-pending bits"] - pub mod SETPEND { - pub const offset: u32 = 0; - pub const mask: u32 = 0xffff_ffff << offset; - pub mod R {} - pub mod W {} - pub mod RW {} - } -} -#[doc = "Interrupt Set Pending Register n"] -pub mod NVICISPR2 { - #[doc = "Interrupt set-pending bits"] - pub mod SETPEND { - pub const offset: u32 = 0; - pub const mask: u32 = 0xffff_ffff << offset; - pub mod R {} - pub mod W {} - pub mod RW {} - } -} -#[doc = "Interrupt Set Pending Register n"] -pub mod NVICISPR3 { - #[doc = "Interrupt set-pending bits"] - pub mod SETPEND { - pub const offset: u32 = 0; - pub const mask: u32 = 0xffff_ffff << offset; - pub mod R {} - pub mod W {} - pub mod RW {} - } -} -#[doc = "Interrupt Clear Pending Register n"] -pub mod NVICICPR0 { - #[doc = "Interrupt clear-pending bits"] - pub mod CLRPEND { - pub const offset: u32 = 0; - pub const mask: u32 = 0xffff_ffff << offset; - pub mod R {} - pub mod W {} - pub mod RW {} - } -} -#[doc = "Interrupt Clear Pending Register n"] -pub mod NVICICPR1 { - #[doc = "Interrupt clear-pending bits"] - pub mod CLRPEND { - pub const offset: u32 = 0; - pub const mask: u32 = 0xffff_ffff << offset; - pub mod R {} - pub mod W {} - pub mod RW {} - } -} -#[doc = "Interrupt Clear Pending Register n"] -pub mod NVICICPR2 { - #[doc = "Interrupt clear-pending bits"] - pub mod CLRPEND { - pub const offset: u32 = 0; - pub const mask: u32 = 0xffff_ffff << offset; - pub mod R {} - pub mod W {} - pub mod RW {} - } -} -#[doc = "Interrupt Clear Pending Register n"] -pub mod NVICICPR3 { - #[doc = "Interrupt clear-pending bits"] - pub mod CLRPEND { - pub const offset: u32 = 0; - pub const mask: u32 = 0xffff_ffff << offset; - pub mod R {} - pub mod W {} - pub mod RW {} - } -} -#[doc = "Interrupt Active bit Register n"] -pub mod NVICIABR0 { - #[doc = "Interrupt active flags"] - pub mod ACTIVE { - pub const offset: u32 = 0; - pub const mask: u32 = 0xffff_ffff << offset; - pub mod R {} - pub mod W {} - pub mod RW {} - } -} -#[doc = "Interrupt Active bit Register n"] -pub mod NVICIABR1 { - #[doc = "Interrupt active flags"] - pub mod ACTIVE { - pub const offset: u32 = 0; - pub const mask: u32 = 0xffff_ffff << offset; - pub mod R {} - pub mod W {} - pub mod RW {} - } -} -#[doc = "Interrupt Active bit Register n"] -pub mod NVICIABR2 { - #[doc = "Interrupt active flags"] - pub mod ACTIVE { - pub const offset: u32 = 0; - pub const mask: u32 = 0xffff_ffff << offset; - pub mod R {} - pub mod W {} - pub mod RW {} - } -} -#[doc = "Interrupt Active bit Register n"] -pub mod NVICIABR3 { - #[doc = "Interrupt active flags"] - pub mod ACTIVE { - pub const offset: u32 = 0; - pub const mask: u32 = 0xffff_ffff << offset; - pub mod R {} - pub mod W {} - pub mod RW {} - } -} -#[doc = "Interrupt Priority Register 0"] -pub mod NVICIP0 { - #[doc = "Priority of interrupt 0"] - pub mod PRI0 { - pub const offset: u8 = 4; - pub const mask: u8 = 0x0f << offset; - pub mod R {} - pub mod W {} - pub mod RW {} - } -} -#[doc = "Interrupt Priority Register 1"] -pub mod NVICIP1 { - #[doc = "Priority of interrupt 1"] - pub mod PRI1 { - pub const offset: u8 = 4; - pub const mask: u8 = 0x0f << offset; - pub mod R {} - pub mod W {} - pub mod RW {} - } -} -#[doc = "Interrupt Priority Register 2"] -pub mod NVICIP2 { - #[doc = "Priority of interrupt 2"] - pub mod PRI2 { - pub const offset: u8 = 4; - pub const mask: u8 = 0x0f << offset; - pub mod R {} - pub mod W {} - pub mod RW {} - } -} -#[doc = "Interrupt Priority Register 3"] -pub mod NVICIP3 { - #[doc = "Priority of interrupt 3"] - pub mod PRI3 { - pub const offset: u8 = 4; - pub const mask: u8 = 0x0f << offset; - pub mod R {} - pub mod W {} - pub mod RW {} - } -} -#[doc = "Interrupt Priority Register 4"] -pub mod NVICIP4 { - #[doc = "Priority of interrupt 4"] - pub mod PRI4 { - pub const offset: u8 = 4; - pub const mask: u8 = 0x0f << offset; - pub mod R {} - pub mod W {} - pub mod RW {} - } -} -#[doc = "Interrupt Priority Register 5"] -pub mod NVICIP5 { - #[doc = "Priority of interrupt 5"] - pub mod PRI5 { - pub const offset: u8 = 4; - pub const mask: u8 = 0x0f << offset; - pub mod R {} - pub mod W {} - pub mod RW {} - } -} -#[doc = "Interrupt Priority Register 6"] -pub mod NVICIP6 { - #[doc = "Priority of interrupt 6"] - pub mod PRI6 { - pub const offset: u8 = 4; - pub const mask: u8 = 0x0f << offset; - pub mod R {} - pub mod W {} - pub mod RW {} - } -} -#[doc = "Interrupt Priority Register 7"] -pub mod NVICIP7 { - #[doc = "Priority of interrupt 7"] - pub mod PRI7 { - pub const offset: u8 = 4; - pub const mask: u8 = 0x0f << offset; - pub mod R {} - pub mod W {} - pub mod RW {} - } -} -#[doc = "Interrupt Priority Register 8"] -pub mod NVICIP8 { - #[doc = "Priority of interrupt 8"] - pub mod PRI8 { - pub const offset: u8 = 4; - pub const mask: u8 = 0x0f << offset; - pub mod R {} - pub mod W {} - pub mod RW {} - } -} -#[doc = "Interrupt Priority Register 9"] -pub mod NVICIP9 { - #[doc = "Priority of interrupt 9"] - pub mod PRI9 { - pub const offset: u8 = 4; - pub const mask: u8 = 0x0f << offset; - pub mod R {} - pub mod W {} - pub mod RW {} - } -} -#[doc = "Interrupt Priority Register 10"] -pub mod NVICIP10 { - #[doc = "Priority of interrupt 10"] - pub mod PRI10 { - pub const offset: u8 = 4; - pub const mask: u8 = 0x0f << offset; - pub mod R {} - pub mod W {} - pub mod RW {} - } -} -#[doc = "Interrupt Priority Register 11"] -pub mod NVICIP11 { - #[doc = "Priority of interrupt 11"] - pub mod PRI11 { - pub const offset: u8 = 4; - pub const mask: u8 = 0x0f << offset; - pub mod R {} - pub mod W {} - pub mod RW {} - } -} -#[doc = "Interrupt Priority Register 12"] -pub mod NVICIP12 { - #[doc = "Priority of interrupt 12"] - pub mod PRI12 { - pub const offset: u8 = 4; - pub const mask: u8 = 0x0f << offset; - pub mod R {} - pub mod W {} - pub mod RW {} - } -} -#[doc = "Interrupt Priority Register 13"] -pub mod NVICIP13 { - #[doc = "Priority of interrupt 13"] - pub mod PRI13 { - pub const offset: u8 = 4; - pub const mask: u8 = 0x0f << offset; - pub mod R {} - pub mod W {} - pub mod RW {} - } -} -#[doc = "Interrupt Priority Register 14"] -pub mod NVICIP14 { - #[doc = "Priority of interrupt 14"] - pub mod PRI14 { - pub const offset: u8 = 4; - pub const mask: u8 = 0x0f << offset; - pub mod R {} - pub mod W {} - pub mod RW {} - } -} -#[doc = "Interrupt Priority Register 15"] -pub mod NVICIP15 { - #[doc = "Priority of interrupt 15"] - pub mod PRI15 { - pub const offset: u8 = 4; - pub const mask: u8 = 0x0f << offset; - pub mod R {} - pub mod W {} - pub mod RW {} - } -} -#[doc = "Interrupt Priority Register 16"] -pub mod NVICIP16 { - #[doc = "Priority of interrupt 16"] - pub mod PRI16 { - pub const offset: u8 = 4; - pub const mask: u8 = 0x0f << offset; - pub mod R {} - pub mod W {} - pub mod RW {} - } -} -#[doc = "Interrupt Priority Register 17"] -pub mod NVICIP17 { - #[doc = "Priority of interrupt 17"] - pub mod PRI17 { - pub const offset: u8 = 4; - pub const mask: u8 = 0x0f << offset; - pub mod R {} - pub mod W {} - pub mod RW {} - } -} -#[doc = "Interrupt Priority Register 18"] -pub mod NVICIP18 { - #[doc = "Priority of interrupt 18"] - pub mod PRI18 { - pub const offset: u8 = 4; - pub const mask: u8 = 0x0f << offset; - pub mod R {} - pub mod W {} - pub mod RW {} - } -} -#[doc = "Interrupt Priority Register 19"] -pub mod NVICIP19 { - #[doc = "Priority of interrupt 19"] - pub mod PRI19 { - pub const offset: u8 = 4; - pub const mask: u8 = 0x0f << offset; - pub mod R {} - pub mod W {} - pub mod RW {} - } -} -#[doc = "Interrupt Priority Register 20"] -pub mod NVICIP20 { - #[doc = "Priority of interrupt 20"] - pub mod PRI20 { - pub const offset: u8 = 4; - pub const mask: u8 = 0x0f << offset; - pub mod R {} - pub mod W {} - pub mod RW {} - } -} -#[doc = "Interrupt Priority Register 21"] -pub mod NVICIP21 { - #[doc = "Priority of interrupt 21"] - pub mod PRI21 { - pub const offset: u8 = 4; - pub const mask: u8 = 0x0f << offset; - pub mod R {} - pub mod W {} - pub mod RW {} - } -} -#[doc = "Interrupt Priority Register 22"] -pub mod NVICIP22 { - #[doc = "Priority of interrupt 22"] - pub mod PRI22 { - pub const offset: u8 = 4; - pub const mask: u8 = 0x0f << offset; - pub mod R {} - pub mod W {} - pub mod RW {} - } -} -#[doc = "Interrupt Priority Register 23"] -pub mod NVICIP23 { - #[doc = "Priority of interrupt 23"] - pub mod PRI23 { - pub const offset: u8 = 4; - pub const mask: u8 = 0x0f << offset; - pub mod R {} - pub mod W {} - pub mod RW {} - } -} -#[doc = "Interrupt Priority Register 24"] -pub mod NVICIP24 { - #[doc = "Priority of interrupt 24"] - pub mod PRI24 { - pub const offset: u8 = 4; - pub const mask: u8 = 0x0f << offset; - pub mod R {} - pub mod W {} - pub mod RW {} - } -} -#[doc = "Interrupt Priority Register 25"] -pub mod NVICIP25 { - #[doc = "Priority of interrupt 25"] - pub mod PRI25 { - pub const offset: u8 = 4; - pub const mask: u8 = 0x0f << offset; - pub mod R {} - pub mod W {} - pub mod RW {} - } -} -#[doc = "Interrupt Priority Register 26"] -pub mod NVICIP26 { - #[doc = "Priority of interrupt 26"] - pub mod PRI26 { - pub const offset: u8 = 4; - pub const mask: u8 = 0x0f << offset; - pub mod R {} - pub mod W {} - pub mod RW {} - } -} -#[doc = "Interrupt Priority Register 27"] -pub mod NVICIP27 { - #[doc = "Priority of interrupt 27"] - pub mod PRI27 { - pub const offset: u8 = 4; - pub const mask: u8 = 0x0f << offset; - pub mod R {} - pub mod W {} - pub mod RW {} - } -} -#[doc = "Interrupt Priority Register 28"] -pub mod NVICIP28 { - #[doc = "Priority of interrupt 28"] - pub mod PRI28 { - pub const offset: u8 = 4; - pub const mask: u8 = 0x0f << offset; - pub mod R {} - pub mod W {} - pub mod RW {} - } -} -#[doc = "Interrupt Priority Register 29"] -pub mod NVICIP29 { - #[doc = "Priority of interrupt 29"] - pub mod PRI29 { - pub const offset: u8 = 4; - pub const mask: u8 = 0x0f << offset; - pub mod R {} - pub mod W {} - pub mod RW {} - } -} -#[doc = "Interrupt Priority Register 30"] -pub mod NVICIP30 { - #[doc = "Priority of interrupt 30"] - pub mod PRI30 { - pub const offset: u8 = 4; - pub const mask: u8 = 0x0f << offset; - pub mod R {} - pub mod W {} - pub mod RW {} - } -} -#[doc = "Interrupt Priority Register 31"] -pub mod NVICIP31 { - #[doc = "Priority of interrupt 31"] - pub mod PRI31 { - pub const offset: u8 = 4; - pub const mask: u8 = 0x0f << offset; - pub mod R {} - pub mod W {} - pub mod RW {} - } -} -#[doc = "Interrupt Priority Register 32"] -pub mod NVICIP32 { - #[doc = "Priority of interrupt 32"] - pub mod PRI32 { - pub const offset: u8 = 4; - pub const mask: u8 = 0x0f << offset; - pub mod R {} - pub mod W {} - pub mod RW {} - } -} -#[doc = "Interrupt Priority Register 33"] -pub mod NVICIP33 { - #[doc = "Priority of interrupt 33"] - pub mod PRI33 { - pub const offset: u8 = 4; - pub const mask: u8 = 0x0f << offset; - pub mod R {} - pub mod W {} - pub mod RW {} - } -} -#[doc = "Interrupt Priority Register 34"] -pub mod NVICIP34 { - #[doc = "Priority of interrupt 34"] - pub mod PRI34 { - pub const offset: u8 = 4; - pub const mask: u8 = 0x0f << offset; - pub mod R {} - pub mod W {} - pub mod RW {} - } -} -#[doc = "Interrupt Priority Register 35"] -pub mod NVICIP35 { - #[doc = "Priority of interrupt 35"] - pub mod PRI35 { - pub const offset: u8 = 4; - pub const mask: u8 = 0x0f << offset; - pub mod R {} - pub mod W {} - pub mod RW {} - } -} -#[doc = "Interrupt Priority Register 36"] -pub mod NVICIP36 { - #[doc = "Priority of interrupt 36"] - pub mod PRI36 { - pub const offset: u8 = 4; - pub const mask: u8 = 0x0f << offset; - pub mod R {} - pub mod W {} - pub mod RW {} - } -} -#[doc = "Interrupt Priority Register 37"] -pub mod NVICIP37 { - #[doc = "Priority of interrupt 37"] - pub mod PRI37 { - pub const offset: u8 = 4; - pub const mask: u8 = 0x0f << offset; - pub mod R {} - pub mod W {} - pub mod RW {} - } -} -#[doc = "Interrupt Priority Register 38"] -pub mod NVICIP38 { - #[doc = "Priority of interrupt 38"] - pub mod PRI38 { - pub const offset: u8 = 4; - pub const mask: u8 = 0x0f << offset; - pub mod R {} - pub mod W {} - pub mod RW {} - } -} -#[doc = "Interrupt Priority Register 39"] -pub mod NVICIP39 { - #[doc = "Priority of interrupt 39"] - pub mod PRI39 { - pub const offset: u8 = 4; - pub const mask: u8 = 0x0f << offset; - pub mod R {} - pub mod W {} - pub mod RW {} - } -} -#[doc = "Interrupt Priority Register 40"] -pub mod NVICIP40 { - #[doc = "Priority of interrupt 40"] - pub mod PRI40 { - pub const offset: u8 = 4; - pub const mask: u8 = 0x0f << offset; - pub mod R {} - pub mod W {} - pub mod RW {} - } -} -#[doc = "Interrupt Priority Register 41"] -pub mod NVICIP41 { - #[doc = "Priority of interrupt 41"] - pub mod PRI41 { - pub const offset: u8 = 4; - pub const mask: u8 = 0x0f << offset; - pub mod R {} - pub mod W {} - pub mod RW {} - } -} -#[doc = "Interrupt Priority Register 42"] -pub mod NVICIP42 { - #[doc = "Priority of interrupt 42"] - pub mod PRI42 { - pub const offset: u8 = 4; - pub const mask: u8 = 0x0f << offset; - pub mod R {} - pub mod W {} - pub mod RW {} - } -} -#[doc = "Interrupt Priority Register 43"] -pub mod NVICIP43 { - #[doc = "Priority of interrupt 43"] - pub mod PRI43 { - pub const offset: u8 = 4; - pub const mask: u8 = 0x0f << offset; - pub mod R {} - pub mod W {} - pub mod RW {} - } -} -#[doc = "Interrupt Priority Register 44"] -pub mod NVICIP44 { - #[doc = "Priority of interrupt 44"] - pub mod PRI44 { - pub const offset: u8 = 4; - pub const mask: u8 = 0x0f << offset; - pub mod R {} - pub mod W {} - pub mod RW {} - } -} -#[doc = "Interrupt Priority Register 45"] -pub mod NVICIP45 { - #[doc = "Priority of interrupt 45"] - pub mod PRI45 { - pub const offset: u8 = 4; - pub const mask: u8 = 0x0f << offset; - pub mod R {} - pub mod W {} - pub mod RW {} - } -} -#[doc = "Interrupt Priority Register 46"] -pub mod NVICIP46 { - #[doc = "Priority of interrupt 46"] - pub mod PRI46 { - pub const offset: u8 = 4; - pub const mask: u8 = 0x0f << offset; - pub mod R {} - pub mod W {} - pub mod RW {} - } -} -#[doc = "Interrupt Priority Register 47"] -pub mod NVICIP47 { - #[doc = "Priority of interrupt 47"] - pub mod PRI47 { - pub const offset: u8 = 4; - pub const mask: u8 = 0x0f << offset; - pub mod R {} - pub mod W {} - pub mod RW {} - } -} -#[doc = "Interrupt Priority Register 48"] -pub mod NVICIP48 { - #[doc = "Priority of interrupt 48"] - pub mod PRI48 { - pub const offset: u8 = 4; - pub const mask: u8 = 0x0f << offset; - pub mod R {} - pub mod W {} - pub mod RW {} - } -} -#[doc = "Interrupt Priority Register 49"] -pub mod NVICIP49 { - #[doc = "Priority of interrupt 49"] - pub mod PRI49 { - pub const offset: u8 = 4; - pub const mask: u8 = 0x0f << offset; - pub mod R {} - pub mod W {} - pub mod RW {} - } -} -#[doc = "Interrupt Priority Register 50"] -pub mod NVICIP50 { - #[doc = "Priority of interrupt 50"] - pub mod PRI50 { - pub const offset: u8 = 4; - pub const mask: u8 = 0x0f << offset; - pub mod R {} - pub mod W {} - pub mod RW {} - } -} -#[doc = "Interrupt Priority Register 51"] -pub mod NVICIP51 { - #[doc = "Priority of interrupt 51"] - pub mod PRI51 { - pub const offset: u8 = 4; - pub const mask: u8 = 0x0f << offset; - pub mod R {} - pub mod W {} - pub mod RW {} - } -} -#[doc = "Interrupt Priority Register 52"] -pub mod NVICIP52 { - #[doc = "Priority of interrupt 52"] - pub mod PRI52 { - pub const offset: u8 = 4; - pub const mask: u8 = 0x0f << offset; - pub mod R {} - pub mod W {} - pub mod RW {} - } -} -#[doc = "Interrupt Priority Register 53"] -pub mod NVICIP53 { - #[doc = "Priority of interrupt 53"] - pub mod PRI53 { - pub const offset: u8 = 4; - pub const mask: u8 = 0x0f << offset; - pub mod R {} - pub mod W {} - pub mod RW {} - } -} -#[doc = "Interrupt Priority Register 54"] -pub mod NVICIP54 { - #[doc = "Priority of interrupt 54"] - pub mod PRI54 { - pub const offset: u8 = 4; - pub const mask: u8 = 0x0f << offset; - pub mod R {} - pub mod W {} - pub mod RW {} - } -} -#[doc = "Interrupt Priority Register 55"] -pub mod NVICIP55 { - #[doc = "Priority of interrupt 55"] - pub mod PRI55 { - pub const offset: u8 = 4; - pub const mask: u8 = 0x0f << offset; - pub mod R {} - pub mod W {} - pub mod RW {} - } -} -#[doc = "Interrupt Priority Register 56"] -pub mod NVICIP56 { - #[doc = "Priority of interrupt 56"] - pub mod PRI56 { - pub const offset: u8 = 4; - pub const mask: u8 = 0x0f << offset; - pub mod R {} - pub mod W {} - pub mod RW {} - } -} -#[doc = "Interrupt Priority Register 57"] -pub mod NVICIP57 { - #[doc = "Priority of interrupt 57"] - pub mod PRI57 { - pub const offset: u8 = 4; - pub const mask: u8 = 0x0f << offset; - pub mod R {} - pub mod W {} - pub mod RW {} - } -} -#[doc = "Interrupt Priority Register 58"] -pub mod NVICIP58 { - #[doc = "Priority of interrupt 58"] - pub mod PRI58 { - pub const offset: u8 = 4; - pub const mask: u8 = 0x0f << offset; - pub mod R {} - pub mod W {} - pub mod RW {} - } -} -#[doc = "Interrupt Priority Register 59"] -pub mod NVICIP59 { - #[doc = "Priority of interrupt 59"] - pub mod PRI59 { - pub const offset: u8 = 4; - pub const mask: u8 = 0x0f << offset; - pub mod R {} - pub mod W {} - pub mod RW {} - } -} -#[doc = "Interrupt Priority Register 60"] -pub mod NVICIP60 { - #[doc = "Priority of interrupt 60"] - pub mod PRI60 { - pub const offset: u8 = 4; - pub const mask: u8 = 0x0f << offset; - pub mod R {} - pub mod W {} - pub mod RW {} - } -} -#[doc = "Interrupt Priority Register 61"] -pub mod NVICIP61 { - #[doc = "Priority of interrupt 61"] - pub mod PRI61 { - pub const offset: u8 = 4; - pub const mask: u8 = 0x0f << offset; - pub mod R {} - pub mod W {} - pub mod RW {} - } -} -#[doc = "Interrupt Priority Register 62"] -pub mod NVICIP62 { - #[doc = "Priority of interrupt 62"] - pub mod PRI62 { - pub const offset: u8 = 4; - pub const mask: u8 = 0x0f << offset; - pub mod R {} - pub mod W {} - pub mod RW {} - } -} -#[doc = "Interrupt Priority Register 63"] -pub mod NVICIP63 { - #[doc = "Priority of interrupt 63"] - pub mod PRI63 { - pub const offset: u8 = 4; - pub const mask: u8 = 0x0f << offset; - pub mod R {} - pub mod W {} - pub mod RW {} - } -} -#[doc = "Interrupt Priority Register 64"] -pub mod NVICIP64 { - #[doc = "Priority of interrupt 64"] - pub mod PRI64 { - pub const offset: u8 = 4; - pub const mask: u8 = 0x0f << offset; - pub mod R {} - pub mod W {} - pub mod RW {} - } -} -#[doc = "Interrupt Priority Register 65"] -pub mod NVICIP65 { - #[doc = "Priority of interrupt 65"] - pub mod PRI65 { - pub const offset: u8 = 4; - pub const mask: u8 = 0x0f << offset; - pub mod R {} - pub mod W {} - pub mod RW {} - } -} -#[doc = "Interrupt Priority Register 66"] -pub mod NVICIP66 { - #[doc = "Priority of interrupt 66"] - pub mod PRI66 { - pub const offset: u8 = 4; - pub const mask: u8 = 0x0f << offset; - pub mod R {} - pub mod W {} - pub mod RW {} - } -} -#[doc = "Interrupt Priority Register 67"] -pub mod NVICIP67 { - #[doc = "Priority of interrupt 67"] - pub mod PRI67 { - pub const offset: u8 = 4; - pub const mask: u8 = 0x0f << offset; - pub mod R {} - pub mod W {} - pub mod RW {} - } -} -#[doc = "Interrupt Priority Register 68"] -pub mod NVICIP68 { - #[doc = "Priority of interrupt 68"] - pub mod PRI68 { - pub const offset: u8 = 4; - pub const mask: u8 = 0x0f << offset; - pub mod R {} - pub mod W {} - pub mod RW {} - } -} -#[doc = "Interrupt Priority Register 69"] -pub mod NVICIP69 { - #[doc = "Priority of interrupt 69"] - pub mod PRI69 { - pub const offset: u8 = 4; - pub const mask: u8 = 0x0f << offset; - pub mod R {} - pub mod W {} - pub mod RW {} - } -} -#[doc = "Interrupt Priority Register 70"] -pub mod NVICIP70 { - #[doc = "Priority of interrupt 70"] - pub mod PRI70 { - pub const offset: u8 = 4; - pub const mask: u8 = 0x0f << offset; - pub mod R {} - pub mod W {} - pub mod RW {} - } -} -#[doc = "Interrupt Priority Register 71"] -pub mod NVICIP71 { - #[doc = "Priority of interrupt 71"] - pub mod PRI71 { - pub const offset: u8 = 4; - pub const mask: u8 = 0x0f << offset; - pub mod R {} - pub mod W {} - pub mod RW {} - } -} -#[doc = "Interrupt Priority Register 72"] -pub mod NVICIP72 { - #[doc = "Priority of interrupt 72"] - pub mod PRI72 { - pub const offset: u8 = 4; - pub const mask: u8 = 0x0f << offset; - pub mod R {} - pub mod W {} - pub mod RW {} - } -} -#[doc = "Interrupt Priority Register 73"] -pub mod NVICIP73 { - #[doc = "Priority of interrupt 73"] - pub mod PRI73 { - pub const offset: u8 = 4; - pub const mask: u8 = 0x0f << offset; - pub mod R {} - pub mod W {} - pub mod RW {} - } -} -#[doc = "Interrupt Priority Register 74"] -pub mod NVICIP74 { - #[doc = "Priority of interrupt 74"] - pub mod PRI74 { - pub const offset: u8 = 4; - pub const mask: u8 = 0x0f << offset; - pub mod R {} - pub mod W {} - pub mod RW {} - } -} -#[doc = "Interrupt Priority Register 75"] -pub mod NVICIP75 { - #[doc = "Priority of interrupt 75"] - pub mod PRI75 { - pub const offset: u8 = 4; - pub const mask: u8 = 0x0f << offset; - pub mod R {} - pub mod W {} - pub mod RW {} - } -} -#[doc = "Interrupt Priority Register 76"] -pub mod NVICIP76 { - #[doc = "Priority of interrupt 76"] - pub mod PRI76 { - pub const offset: u8 = 4; - pub const mask: u8 = 0x0f << offset; - pub mod R {} - pub mod W {} - pub mod RW {} - } -} -#[doc = "Interrupt Priority Register 77"] -pub mod NVICIP77 { - #[doc = "Priority of interrupt 77"] - pub mod PRI77 { - pub const offset: u8 = 4; - pub const mask: u8 = 0x0f << offset; - pub mod R {} - pub mod W {} - pub mod RW {} - } -} -#[doc = "Interrupt Priority Register 78"] -pub mod NVICIP78 { - #[doc = "Priority of interrupt 78"] - pub mod PRI78 { - pub const offset: u8 = 4; - pub const mask: u8 = 0x0f << offset; - pub mod R {} - pub mod W {} - pub mod RW {} - } -} -#[doc = "Interrupt Priority Register 79"] -pub mod NVICIP79 { - #[doc = "Priority of interrupt 79"] - pub mod PRI79 { - pub const offset: u8 = 4; - pub const mask: u8 = 0x0f << offset; - pub mod R {} - pub mod W {} - pub mod RW {} - } -} -#[doc = "Interrupt Priority Register 80"] -pub mod NVICIP80 { - #[doc = "Priority of interrupt 80"] - pub mod PRI80 { - pub const offset: u8 = 4; - pub const mask: u8 = 0x0f << offset; - pub mod R {} - pub mod W {} - pub mod RW {} - } -} -#[doc = "Interrupt Priority Register 81"] -pub mod NVICIP81 { - #[doc = "Priority of interrupt 81"] - pub mod PRI81 { - pub const offset: u8 = 4; - pub const mask: u8 = 0x0f << offset; - pub mod R {} - pub mod W {} - pub mod RW {} - } -} -#[doc = "Interrupt Priority Register 82"] -pub mod NVICIP82 { - #[doc = "Priority of interrupt 82"] - pub mod PRI82 { - pub const offset: u8 = 4; - pub const mask: u8 = 0x0f << offset; - pub mod R {} - pub mod W {} - pub mod RW {} - } -} -#[doc = "Interrupt Priority Register 83"] -pub mod NVICIP83 { - #[doc = "Priority of interrupt 83"] - pub mod PRI83 { - pub const offset: u8 = 4; - pub const mask: u8 = 0x0f << offset; - pub mod R {} - pub mod W {} - pub mod RW {} - } -} -#[doc = "Interrupt Priority Register 84"] -pub mod NVICIP84 { - #[doc = "Priority of interrupt 84"] - pub mod PRI84 { - pub const offset: u8 = 4; - pub const mask: u8 = 0x0f << offset; - pub mod R {} - pub mod W {} - pub mod RW {} - } -} -#[doc = "Interrupt Priority Register 85"] -pub mod NVICIP85 { - #[doc = "Priority of interrupt 85"] - pub mod PRI85 { - pub const offset: u8 = 4; - pub const mask: u8 = 0x0f << offset; - pub mod R {} - pub mod W {} - pub mod RW {} - } -} -#[doc = "Interrupt Priority Register 86"] -pub mod NVICIP86 { - #[doc = "Priority of interrupt 86"] - pub mod PRI86 { - pub const offset: u8 = 4; - pub const mask: u8 = 0x0f << offset; - pub mod R {} - pub mod W {} - pub mod RW {} - } -} -#[doc = "Interrupt Priority Register 87"] -pub mod NVICIP87 { - #[doc = "Priority of interrupt 87"] - pub mod PRI87 { - pub const offset: u8 = 4; - pub const mask: u8 = 0x0f << offset; - pub mod R {} - pub mod W {} - pub mod RW {} - } -} -#[doc = "Interrupt Priority Register 88"] -pub mod NVICIP88 { - #[doc = "Priority of interrupt 88"] - pub mod PRI88 { - pub const offset: u8 = 4; - pub const mask: u8 = 0x0f << offset; - pub mod R {} - pub mod W {} - pub mod RW {} - } -} -#[doc = "Interrupt Priority Register 89"] -pub mod NVICIP89 { - #[doc = "Priority of interrupt 89"] - pub mod PRI89 { - pub const offset: u8 = 4; - pub const mask: u8 = 0x0f << offset; - pub mod R {} - pub mod W {} - pub mod RW {} - } -} -#[doc = "Interrupt Priority Register 90"] -pub mod NVICIP90 { - #[doc = "Priority of interrupt 90"] - pub mod PRI90 { - pub const offset: u8 = 4; - pub const mask: u8 = 0x0f << offset; - pub mod R {} - pub mod W {} - pub mod RW {} - } -} -#[doc = "Interrupt Priority Register 91"] -pub mod NVICIP91 { - #[doc = "Priority of interrupt 91"] - pub mod PRI91 { - pub const offset: u8 = 4; - pub const mask: u8 = 0x0f << offset; - pub mod R {} - pub mod W {} - pub mod RW {} - } -} -#[doc = "Interrupt Priority Register 92"] -pub mod NVICIP92 { - #[doc = "Priority of interrupt 92"] - pub mod PRI92 { - pub const offset: u8 = 4; - pub const mask: u8 = 0x0f << offset; - pub mod R {} - pub mod W {} - pub mod RW {} - } -} -#[doc = "Interrupt Priority Register 93"] -pub mod NVICIP93 { - #[doc = "Priority of interrupt 93"] - pub mod PRI93 { - pub const offset: u8 = 4; - pub const mask: u8 = 0x0f << offset; - pub mod R {} - pub mod W {} - pub mod RW {} - } -} -#[doc = "Interrupt Priority Register 94"] -pub mod NVICIP94 { - #[doc = "Priority of interrupt 94"] - pub mod PRI94 { - pub const offset: u8 = 4; - pub const mask: u8 = 0x0f << offset; - pub mod R {} - pub mod W {} - pub mod RW {} - } -} -#[doc = "Interrupt Priority Register 95"] -pub mod NVICIP95 { - #[doc = "Priority of interrupt 95"] - pub mod PRI95 { - pub const offset: u8 = 4; - pub const mask: u8 = 0x0f << offset; - pub mod R {} - pub mod W {} - pub mod RW {} - } -} -#[doc = "Interrupt Priority Register 96"] -pub mod NVICIP96 { - #[doc = "Priority of interrupt 96"] - pub mod PRI96 { - pub const offset: u8 = 4; - pub const mask: u8 = 0x0f << offset; - pub mod R {} - pub mod W {} - pub mod RW {} - } -} -#[doc = "Interrupt Priority Register 97"] -pub mod NVICIP97 { - #[doc = "Priority of interrupt 97"] - pub mod PRI97 { - pub const offset: u8 = 4; - pub const mask: u8 = 0x0f << offset; - pub mod R {} - pub mod W {} - pub mod RW {} - } -} -#[doc = "Interrupt Priority Register 98"] -pub mod NVICIP98 { - #[doc = "Priority of interrupt 98"] - pub mod PRI98 { - pub const offset: u8 = 4; - pub const mask: u8 = 0x0f << offset; - pub mod R {} - pub mod W {} - pub mod RW {} - } -} -#[doc = "Interrupt Priority Register 99"] -pub mod NVICIP99 { - #[doc = "Priority of interrupt 99"] - pub mod PRI99 { - pub const offset: u8 = 4; - pub const mask: u8 = 0x0f << offset; - pub mod R {} - pub mod W {} - pub mod RW {} - } -} -#[doc = "Interrupt Priority Register 100"] -pub mod NVICIP100 { - #[doc = "Priority of interrupt 100"] - pub mod PRI100 { - pub const offset: u8 = 4; - pub const mask: u8 = 0x0f << offset; - pub mod R {} - pub mod W {} - pub mod RW {} - } -} -#[doc = "Interrupt Priority Register 101"] -pub mod NVICIP101 { - #[doc = "Priority of interrupt 101"] - pub mod PRI101 { - pub const offset: u8 = 4; - pub const mask: u8 = 0x0f << offset; - pub mod R {} - pub mod W {} - pub mod RW {} - } -} -#[doc = "Interrupt Priority Register 102"] -pub mod NVICIP102 { - #[doc = "Priority of interrupt 102"] - pub mod PRI102 { - pub const offset: u8 = 4; - pub const mask: u8 = 0x0f << offset; - pub mod R {} - pub mod W {} - pub mod RW {} - } -} -#[doc = "Interrupt Priority Register 103"] -pub mod NVICIP103 { - #[doc = "Priority of interrupt 103"] - pub mod PRI103 { - pub const offset: u8 = 4; - pub const mask: u8 = 0x0f << offset; - pub mod R {} - pub mod W {} - pub mod RW {} - } -} -#[doc = "Interrupt Priority Register 104"] -pub mod NVICIP104 { - #[doc = "Priority of interrupt 104"] - pub mod PRI104 { - pub const offset: u8 = 4; - pub const mask: u8 = 0x0f << offset; - pub mod R {} - pub mod W {} - pub mod RW {} - } -} -#[doc = "Interrupt Priority Register 105"] -pub mod NVICIP105 { - #[doc = "Priority of interrupt 105"] - pub mod PRI105 { - pub const offset: u8 = 4; - pub const mask: u8 = 0x0f << offset; - pub mod R {} - pub mod W {} - pub mod RW {} - } -} -#[doc = "Software Trigger Interrupt Register"] -pub mod NVICSTIR { - #[doc = "Interrupt ID of the interrupt to trigger, in the range 0-239. For example, a value of 0x03 specifies interrupt IRQ3."] - pub mod INTID { - pub const offset: u32 = 0; - pub const mask: u32 = 0x01ff << offset; - pub mod R {} - pub mod W {} - pub mod RW {} - } -} diff --git a/src/blocks/imxrt1176_cm7/system_control.rs b/src/blocks/imxrt1176_cm7/system_control.rs deleted file mode 100644 index f2624aea8d79..000000000000 --- a/src/blocks/imxrt1176_cm7/system_control.rs +++ /dev/null @@ -1,2944 +0,0 @@ -#[doc = "System Control Block"] -#[repr(C)] -pub struct RegisterBlock { - _reserved0: [u8; 0x08], - #[doc = "Auxiliary Control Register,"] - pub ACTLR: crate::RWRegister, - _reserved1: [u8; 0x0cf4], - #[doc = "CPUID Base Register"] - pub CPUID: crate::RORegister, - #[doc = "Interrupt Control and State Register"] - pub ICSR: crate::RWRegister, - #[doc = "Vector Table Offset Register"] - pub VTOR: crate::RWRegister, - #[doc = "Application Interrupt and Reset Control Register"] - pub AIRCR: crate::RWRegister, - #[doc = "System Control Register"] - pub SCR: crate::RWRegister, - #[doc = "Configuration and Control Register"] - pub CCR: crate::RWRegister, - #[doc = "System Handler Priority Register 1"] - pub SHPR1: crate::RWRegister, - #[doc = "System Handler Priority Register 2"] - pub SHPR2: crate::RWRegister, - #[doc = "System Handler Priority Register 3"] - pub SHPR3: crate::RWRegister, - #[doc = "System Handler Control and State Register"] - pub SHCSR: crate::RWRegister, - #[doc = "Configurable Fault Status Register"] - pub CFSR: crate::RWRegister, - #[doc = "HardFault Status register"] - pub HFSR: crate::RWRegister, - #[doc = "Debug Fault Status Register"] - pub DFSR: crate::RWRegister, - #[doc = "MemManage Fault Address Register"] - pub MMFAR: crate::RWRegister, - #[doc = "BusFault Address Register"] - pub BFAR: crate::RWRegister, - _reserved2: [u8; 0x04], - #[doc = "Processor Feature Register 0"] - pub ID_PFR0: crate::RORegister, - #[doc = "Processor Feature Register 1"] - pub ID_PFR1: crate::RORegister, - #[doc = "Debug Feature Register"] - pub ID_DFR0: crate::RORegister, - #[doc = "Auxiliary Feature Register"] - pub ID_AFR0: crate::RORegister, - #[doc = "Memory Model Feature Register 0"] - pub ID_MMFR0: crate::RORegister, - #[doc = "Memory Model Feature Register 1"] - pub ID_MMFR1: crate::RORegister, - #[doc = "Memory Model Feature Register 2"] - pub ID_MMFR2: crate::RORegister, - #[doc = "Memory Model Feature Register 3"] - pub ID_MMFR3: crate::RORegister, - #[doc = "Instruction Set Attributes Register 0"] - pub ID_ISAR0: crate::RORegister, - #[doc = "Instruction Set Attributes Register 1"] - pub ID_ISAR1: crate::RORegister, - #[doc = "Instruction Set Attributes Register 2"] - pub ID_ISAR2: crate::RORegister, - #[doc = "Instruction Set Attributes Register 3"] - pub ID_ISAR3: crate::RORegister, - #[doc = "Instruction Set Attributes Register 4"] - pub ID_ISAR4: crate::RORegister, - _reserved3: [u8; 0x04], - #[doc = "Cache Level ID register"] - pub CLIDR: crate::RORegister, - #[doc = "Cache Type register"] - pub CTR: crate::RORegister, - #[doc = "Cache Size ID Register"] - pub CCSIDR: crate::RORegister, - #[doc = "Cache Size Selection Register"] - pub CSSELR: crate::RWRegister, - #[doc = "Coprocessor Access Control Register"] - pub CPACR: crate::RWRegister, - _reserved4: [u8; 0x0174], - #[doc = "Instruction cache invalidate all to Point of Unification (PoU)"] - pub STIR: crate::WORegister, - _reserved5: [u8; 0x4c], - #[doc = "Instruction cache invalidate all to Point of Unification (PoU)"] - pub ICIALLU: crate::WORegister, - _reserved6: [u8; 0x04], - #[doc = "Instruction cache invalidate by address to PoU"] - pub ICIMVAU: crate::WORegister, - #[doc = "Data cache invalidate by address to Point of Coherency (PoC)"] - pub DCIMVAC: crate::WORegister, - #[doc = "Data cache invalidate by set/way"] - pub DCISW: crate::WORegister, - #[doc = "Data cache by address to PoU"] - pub DCCMVAU: crate::WORegister, - #[doc = "Data cache clean by address to PoC"] - pub DCCMVAC: crate::WORegister, - #[doc = "Data cache clean by set/way"] - pub DCCSW: crate::WORegister, - #[doc = "Data cache clean and invalidate by address to PoC"] - pub DCCIMVAC: crate::WORegister, - #[doc = "Data cache clean and invalidate by set/way"] - pub DCCISW: crate::WORegister, - _reserved7: [u8; 0x18], - #[doc = "Instruction Tightly-Coupled Memory Control Register"] - pub CM7_ITCMCR: crate::RWRegister, - #[doc = "Data Tightly-Coupled Memory Control Register"] - pub CM7_DTCMCR: crate::RWRegister, - #[doc = "AHBP Control Register"] - pub CM7_AHBPCR: crate::RWRegister, - #[doc = "L1 Cache Control Register"] - pub CM7_CACR: crate::RWRegister, - #[doc = "AHB Slave Control Register"] - pub CM7_AHBSCR: crate::RWRegister, - _reserved8: [u8; 0x04], - #[doc = "Auxiliary Bus Fault Status Register"] - pub CM7_ABFSR: crate::RWRegister, -} -#[doc = "Auxiliary Control Register,"] -pub mod ACTLR { - #[doc = "Disables folding of IT instructions."] - pub mod DISFOLD { - pub const offset: u32 = 2; - pub const mask: u32 = 0x01 << offset; - pub mod R {} - pub mod W {} - pub mod RW { - #[doc = "Normal operation."] - pub const DISFOLD_0: u32 = 0; - } - } - #[doc = "Disables FPU exception outputs."] - pub mod FPEXCODIS { - pub const offset: u32 = 10; - pub const mask: u32 = 0x01 << offset; - pub mod R {} - pub mod W {} - pub mod RW { - #[doc = "Normal operation."] - pub const FPEXCODIS_0: u32 = 0; - #[doc = "FPU exception outputs are disabled."] - pub const FPEXCODIS_1: u32 = 0x01; - } - } - #[doc = "Disables dynamic read allocate mode for Write-Back Write-Allocate memory regions."] - pub mod DISRAMODE { - pub const offset: u32 = 11; - pub const mask: u32 = 0x01 << offset; - pub mod R {} - pub mod W {} - pub mod RW { - #[doc = "Normal operation."] - pub const DISRAMODE_0: u32 = 0; - #[doc = "Dynamic disabled."] - pub const DISRAMODE_1: u32 = 0x01; - } - } - #[doc = "Disables ITM and DWT ATB flush."] - pub mod DISITMATBFLUSH { - pub const offset: u32 = 12; - pub const mask: u32 = 0x01 << offset; - pub mod R {} - pub mod W {} - pub mod RW { - #[doc = "ITM and DWT ATB flush disabled, this bit is always 1."] - pub const DISITMATBFLUSH_1: u32 = 0x01; - } - } - #[doc = "Disables BTAC read."] - pub mod DISBTACREAD { - pub const offset: u32 = 13; - pub const mask: u32 = 0x01 << offset; - pub mod R {} - pub mod W {} - pub mod RW { - #[doc = "Normal operation."] - pub const DISBTACREAD_0: u32 = 0; - #[doc = "BTAC is not used and only static branch prediction can occur."] - pub const DISBTACREAD_1: u32 = 0x01; - } - } - #[doc = "Disables BTAC allocate."] - pub mod DISBTACALLOC { - pub const offset: u32 = 14; - pub const mask: u32 = 0x01 << offset; - pub mod R {} - pub mod W {} - pub mod RW { - #[doc = "Normal operation."] - pub const DISBTACALLOC_0: u32 = 0; - #[doc = "No new entries are allocated in Branch Target Address Cache (BTAC), but existing entries can be updated."] - pub const DISBTACALLOC_1: u32 = 0x01; - } - } - #[doc = "Disables critical AXI Read-Under-Read."] - pub mod DISCRITAXIRUR { - pub const offset: u32 = 15; - pub const mask: u32 = 0x01 << offset; - pub mod R {} - pub mod W {} - pub mod RW { - #[doc = "Normal operation."] - pub const DISCRITAXIRUR_0: u32 = 0; - #[doc = "An AXI read to Strongly-Ordered or Device memory, or an LDREX to Shareable memory, is not put on AXI if there are any outstanding reads on AXI. Transactions on AXI cannot be interrupted. This bit might reduce the time that these transactions are in progress and might improve worst case interrupt latency. Performance is decreased when this bit is set."] - pub const DISCRITAXIRUR_1: u32 = 0x01; - } - } - #[doc = "Disables dual-issued."] - pub mod DISDI { - pub const offset: u32 = 16; - pub const mask: u32 = 0x1f << offset; - pub mod R {} - pub mod W {} - pub mod RW { - #[doc = "Normal operation."] - pub const DISDI_0: u32 = 0; - #[doc = "Nothing can be dual-issued when this instruction type is in channel 0."] - pub const DISDI_1: u32 = 0x01; - } - } - #[doc = "Disables dual-issued."] - pub mod DISISSCH1 { - pub const offset: u32 = 21; - pub const mask: u32 = 0x1f << offset; - pub mod R {} - pub mod W {} - pub mod RW { - #[doc = "Normal operation."] - pub const DISISSCH1_0: u32 = 0; - #[doc = "Nothing can be dual-issued when this instruction type is in channel 1."] - pub const DISISSCH1_1: u32 = 0x01; - } - } - #[doc = "Disables dynamic allocation of ADD and SUB instructions"] - pub mod DISDYNADD { - pub const offset: u32 = 26; - pub const mask: u32 = 0x01 << offset; - pub mod R {} - pub mod W {} - pub mod RW { - #[doc = "Normal operation. Some ADD and SUB instrctions are resolved in EX1."] - pub const DISDYNADD_0: u32 = 0; - #[doc = "All ADD and SUB instructions are resolved in EX2."] - pub const DISDYNADD_1: u32 = 0x01; - } - } - #[doc = "Disables critical AXI read-under-write"] - pub mod DISCRITAXIRUW { - pub const offset: u32 = 27; - pub const mask: u32 = 0x01 << offset; - pub mod R {} - pub mod W {} - pub mod RW { - #[doc = "Normal operation. This is backwards compatible with r0."] - pub const DISCRITAXIRUW_0: u32 = 0; - #[doc = "AXI reads to DEV/SO memory. Exclusive reads to Shareable memory are not initiated on the AXIM AR channel until all outstanding stores on AXI are complete."] - pub const DISCRITAXIRUW_1: u32 = 0x01; - } - } - #[doc = "Disables critical AXI read-under-write"] - pub mod DISFPUISSOPT { - pub const offset: u32 = 28; - pub const mask: u32 = 0x01 << offset; - pub mod R {} - pub mod W {} - pub mod RW { - #[doc = "Normal operation."] - pub const DISFPUISSOPT_0: u32 = 0; - } - } -} -#[doc = "CPUID Base Register"] -pub mod CPUID { - #[doc = "Indicates patch release: 0x0 = Patch 0"] - pub mod REVISION { - pub const offset: u32 = 0; - pub const mask: u32 = 0x0f << offset; - pub mod R {} - pub mod W {} - pub mod RW {} - } - #[doc = "Indicates part number"] - pub mod PARTNO { - pub const offset: u32 = 4; - pub const mask: u32 = 0x0fff << offset; - pub mod R {} - pub mod W {} - pub mod RW {} - } - #[doc = "ARCHITECTURE"] - pub mod ARCHITECTURE { - pub const offset: u32 = 16; - pub const mask: u32 = 0x0f << offset; - pub mod R {} - pub mod W {} - pub mod RW {} - } - #[doc = "Indicates processor revision: 0x2 = Revision 2"] - pub mod VARIANT { - pub const offset: u32 = 20; - pub const mask: u32 = 0x0f << offset; - pub mod R {} - pub mod W {} - pub mod RW {} - } - #[doc = "Implementer code"] - pub mod IMPLEMENTER { - pub const offset: u32 = 24; - pub const mask: u32 = 0xff << offset; - pub mod R {} - pub mod W {} - pub mod RW {} - } -} -#[doc = "Interrupt Control and State Register"] -pub mod ICSR { - #[doc = "Active exception number"] - pub mod VECTACTIVE { - pub const offset: u32 = 0; - pub const mask: u32 = 0x01ff << offset; - pub mod R {} - pub mod W {} - pub mod RW {} - } - #[doc = "Indicates whether there are preempted active exceptions"] - pub mod RETTOBASE { - pub const offset: u32 = 11; - pub const mask: u32 = 0x01 << offset; - pub mod R {} - pub mod W {} - pub mod RW { - #[doc = "there are preempted active exceptions to execute"] - pub const RETTOBASE_0: u32 = 0; - #[doc = "there are no active exceptions, or the currently-executing exception is the only active exception"] - pub const RETTOBASE_1: u32 = 0x01; - } - } - #[doc = "Exception number of the highest priority pending enabled exception"] - pub mod VECTPENDING { - pub const offset: u32 = 12; - pub const mask: u32 = 0x01ff << offset; - pub mod R {} - pub mod W {} - pub mod RW {} - } - #[doc = "Interrupt pending flag, excluding NMI and Faults"] - pub mod ISRPENDING { - pub const offset: u32 = 22; - pub const mask: u32 = 0x01 << offset; - pub mod R {} - pub mod W {} - pub mod RW { - #[doc = "No external interrupt pending."] - pub const ISRPENDING_0: u32 = 0; - #[doc = "External interrupt pending."] - pub const ISRPENDING_1: u32 = 0x01; - } - } - #[doc = "SysTick exception clear-pending bit"] - pub mod PENDSTCLR { - pub const offset: u32 = 25; - pub const mask: u32 = 0x01 << offset; - pub mod R {} - pub mod W {} - pub mod RW { - #[doc = "no effect"] - pub const PENDSTCLR_0: u32 = 0; - #[doc = "removes the pending state from the SysTick exception"] - pub const PENDSTCLR_1: u32 = 0x01; - } - } - #[doc = "SysTick exception set-pending bit"] - pub mod PENDSTSET { - pub const offset: u32 = 26; - pub const mask: u32 = 0x01 << offset; - pub mod R {} - pub mod W {} - pub mod RW { - #[doc = "write: no effect; read: SysTick exception is not pending"] - pub const PENDSTSET_0: u32 = 0; - #[doc = "write: changes SysTick exception state to pending; read: SysTick exception is pending"] - pub const PENDSTSET_1: u32 = 0x01; - } - } - #[doc = "PendSV clear-pending bit"] - pub mod PENDSVCLR { - pub const offset: u32 = 27; - pub const mask: u32 = 0x01 << offset; - pub mod R {} - pub mod W {} - pub mod RW { - #[doc = "no effect"] - pub const PENDSVCLR_0: u32 = 0; - #[doc = "removes the pending state from the PendSV exception"] - pub const PENDSVCLR_1: u32 = 0x01; - } - } - #[doc = "PendSV set-pending bit"] - pub mod PENDSVSET { - pub const offset: u32 = 28; - pub const mask: u32 = 0x01 << offset; - pub mod R {} - pub mod W {} - pub mod RW { - #[doc = "write: no effect; read: PendSV exception is not pending"] - pub const PENDSVSET_0: u32 = 0; - #[doc = "write: changes PendSV exception state to pending; read: PendSV exception is pending"] - pub const PENDSVSET_1: u32 = 0x01; - } - } - #[doc = "NMI set-pending bit"] - pub mod NMIPENDSET { - pub const offset: u32 = 31; - pub const mask: u32 = 0x01 << offset; - pub mod R {} - pub mod W {} - pub mod RW { - #[doc = "write: no effect; read: NMI exception is not pending"] - pub const NMIPENDSET_0: u32 = 0; - #[doc = "write: changes NMI exception state to pending; read: NMI exception is pending"] - pub const NMIPENDSET_1: u32 = 0x01; - } - } -} -#[doc = "Vector Table Offset Register"] -pub mod VTOR { - #[doc = "Vector table base offset"] - pub mod TBLOFF { - pub const offset: u32 = 7; - pub const mask: u32 = 0x01ff_ffff << offset; - pub mod R {} - pub mod W {} - pub mod RW {} - } -} -#[doc = "Application Interrupt and Reset Control Register"] -pub mod AIRCR { - #[doc = "Writing 1 to this bit causes a local system reset"] - pub mod VECTRESET { - pub const offset: u32 = 0; - pub const mask: u32 = 0x01 << offset; - pub mod R {} - pub mod W {} - pub mod RW { - #[doc = "No change"] - pub const VECTRESET_0: u32 = 0; - #[doc = "Causes a local system reset"] - pub const VECTRESET_1: u32 = 0x01; - } - } - #[doc = "Writing 1 to this bit clears all active state information for fixed and configurable exceptions."] - pub mod VECTCLRACTIVE { - pub const offset: u32 = 1; - pub const mask: u32 = 0x01 << offset; - pub mod R {} - pub mod W {} - pub mod RW { - #[doc = "No change"] - pub const VECTCLRACTIVE_0: u32 = 0; - #[doc = "Clears all active state information for fixed and configurable exceptions"] - pub const VECTCLRACTIVE_1: u32 = 0x01; - } - } - #[doc = "System reset request"] - pub mod SYSRESETREQ { - pub const offset: u32 = 2; - pub const mask: u32 = 0x01 << offset; - pub mod R {} - pub mod W {} - pub mod RW { - #[doc = "no system reset request"] - pub const SYSRESETREQ_0: u32 = 0; - #[doc = "asserts a signal to the outer system that requests a reset"] - pub const SYSRESETREQ_1: u32 = 0x01; - } - } - #[doc = "Interrupt priority grouping field. This field determines the split of group priority from subpriority."] - pub mod PRIGROUP { - pub const offset: u32 = 8; - pub const mask: u32 = 0x07 << offset; - pub mod R {} - pub mod W {} - pub mod RW {} - } - #[doc = "Data endianness"] - pub mod ENDIANNESS { - pub const offset: u32 = 15; - pub const mask: u32 = 0x01 << offset; - pub mod R {} - pub mod W {} - pub mod RW { - #[doc = "Little-endian"] - pub const ENDIANNESS_0: u32 = 0; - #[doc = "Big-endian"] - pub const ENDIANNESS_1: u32 = 0x01; - } - } - #[doc = "Register key"] - pub mod VECTKEY { - pub const offset: u32 = 16; - pub const mask: u32 = 0xffff << offset; - pub mod R {} - pub mod W {} - pub mod RW {} - } -} -#[doc = "System Control Register"] -pub mod SCR { - #[doc = "Indicates sleep-on-exit when returning from Handler mode to Thread mode"] - pub mod SLEEPONEXIT { - pub const offset: u32 = 1; - pub const mask: u32 = 0x01 << offset; - pub mod R {} - pub mod W {} - pub mod RW { - #[doc = "o not sleep when returning to Thread mode"] - pub const SLEEPONEXIT_0: u32 = 0; - #[doc = "enter sleep, or deep sleep, on return from an ISR"] - pub const SLEEPONEXIT_1: u32 = 0x01; - } - } - #[doc = "Controls whether the processor uses sleep or deep sleep as its low power mode"] - pub mod SLEEPDEEP { - pub const offset: u32 = 2; - pub const mask: u32 = 0x01 << offset; - pub mod R {} - pub mod W {} - pub mod RW { - #[doc = "sleep"] - pub const SLEEPDEEP_0: u32 = 0; - #[doc = "deep sleep"] - pub const SLEEPDEEP_1: u32 = 0x01; - } - } - #[doc = "Send Event on Pending bit"] - pub mod SEVONPEND { - pub const offset: u32 = 4; - pub const mask: u32 = 0x01 << offset; - pub mod R {} - pub mod W {} - pub mod RW { - #[doc = "only enabled interrupts or events can wakeup the processor, disabled interrupts are excluded"] - pub const SEVONPEND_0: u32 = 0; - #[doc = "enabled events and all interrupts, including disabled interrupts, can wakeup the processor"] - pub const SEVONPEND_1: u32 = 0x01; - } - } -} -#[doc = "Configuration and Control Register"] -pub mod CCR { - #[doc = "Indicates how the processor enters Thread mode"] - pub mod NONBASETHRDENA { - pub const offset: u32 = 0; - pub const mask: u32 = 0x01 << offset; - pub mod R {} - pub mod W {} - pub mod RW { - #[doc = "processor can enter Thread mode only when no exception is active"] - pub const NONBASETHRDENA_0: u32 = 0; - #[doc = "processor can enter Thread mode from any level under the control of an EXC_RETURN value"] - pub const NONBASETHRDENA_1: u32 = 0x01; - } - } - #[doc = "Enables unprivileged software access to the STIR"] - pub mod USERSETMPEND { - pub const offset: u32 = 1; - pub const mask: u32 = 0x01 << offset; - pub mod R {} - pub mod W {} - pub mod RW { - #[doc = "disable"] - pub const USERSETMPEND_0: u32 = 0; - #[doc = "enable"] - pub const USERSETMPEND_1: u32 = 0x01; - } - } - #[doc = "Enables unaligned access traps"] - pub mod UNALIGN_TRP { - pub const offset: u32 = 3; - pub const mask: u32 = 0x01 << offset; - pub mod R {} - pub mod W {} - pub mod RW { - #[doc = "do not trap unaligned halfword and word accesses"] - pub const UNALIGN_TRP_0: u32 = 0; - #[doc = "trap unaligned halfword and word accesses"] - pub const UNALIGN_TRP_1: u32 = 0x01; - } - } - #[doc = "Enables faulting or halting when the processor executes an SDIV or UDIV instruction with a divisor of 0"] - pub mod DIV_0_TRP { - pub const offset: u32 = 4; - pub const mask: u32 = 0x01 << offset; - pub mod R {} - pub mod W {} - pub mod RW { - #[doc = "do not trap divide by 0"] - pub const DIV_0_TRP_0: u32 = 0; - #[doc = "trap divide by 0"] - pub const DIV_0_TRP_1: u32 = 0x01; - } - } - #[doc = "Enables handlers with priority -1 or -2 to ignore data BusFaults caused by load and store instructions."] - pub mod BFHFNMIGN { - pub const offset: u32 = 8; - pub const mask: u32 = 0x01 << offset; - pub mod R {} - pub mod W {} - pub mod RW { - #[doc = "data bus faults caused by load and store instructions cause a lock-up"] - pub const BFHFNMIGN_0: u32 = 0; - #[doc = "handlers running at priority -1 and -2 ignore data bus faults caused by load and store instructions"] - pub const BFHFNMIGN_1: u32 = 0x01; - } - } - #[doc = "Indicates stack alignment on exception entry"] - pub mod STKALIGN { - pub const offset: u32 = 9; - pub const mask: u32 = 0x01 << offset; - pub mod R {} - pub mod W {} - pub mod RW { - #[doc = "4-byte aligned"] - pub const STKALIGN_0: u32 = 0; - #[doc = "8-byte aligned"] - pub const STKALIGN_1: u32 = 0x01; - } - } - #[doc = "Enables L1 data cache."] - pub mod DC { - pub const offset: u32 = 16; - pub const mask: u32 = 0x01 << offset; - pub mod R {} - pub mod W {} - pub mod RW { - #[doc = "L1 data cache disabled"] - pub const DC_0: u32 = 0; - #[doc = "L1 data cache enabled"] - pub const DC_1: u32 = 0x01; - } - } - #[doc = "Enables L1 instruction cache."] - pub mod IC { - pub const offset: u32 = 17; - pub const mask: u32 = 0x01 << offset; - pub mod R {} - pub mod W {} - pub mod RW { - #[doc = "L1 instruction cache disabled"] - pub const IC_0: u32 = 0; - #[doc = "L1 instruction cache enabled"] - pub const IC_1: u32 = 0x01; - } - } - #[doc = "Always reads-as-one. It indicates branch prediction is enabled."] - pub mod BP { - pub const offset: u32 = 18; - pub const mask: u32 = 0x01 << offset; - pub mod R {} - pub mod W {} - pub mod RW {} - } -} -#[doc = "System Handler Priority Register 1"] -pub mod SHPR1 { - #[doc = "Priority of system handler 4, MemManage"] - pub mod PRI_4 { - pub const offset: u32 = 0; - pub const mask: u32 = 0xff << offset; - pub mod R {} - pub mod W {} - pub mod RW {} - } - #[doc = "Priority of system handler 5, BusFault"] - pub mod PRI_5 { - pub const offset: u32 = 8; - pub const mask: u32 = 0xff << offset; - pub mod R {} - pub mod W {} - pub mod RW {} - } - #[doc = "Priority of system handler 6, UsageFault"] - pub mod PRI_6 { - pub const offset: u32 = 16; - pub const mask: u32 = 0xff << offset; - pub mod R {} - pub mod W {} - pub mod RW {} - } -} -#[doc = "System Handler Priority Register 2"] -pub mod SHPR2 { - #[doc = "Priority of system handler 11, SVCall"] - pub mod PRI_11 { - pub const offset: u32 = 24; - pub const mask: u32 = 0xff << offset; - pub mod R {} - pub mod W {} - pub mod RW {} - } -} -#[doc = "System Handler Priority Register 3"] -pub mod SHPR3 { - #[doc = "Priority of system handler 14, PendSV"] - pub mod PRI_14 { - pub const offset: u32 = 16; - pub const mask: u32 = 0xff << offset; - pub mod R {} - pub mod W {} - pub mod RW {} - } - #[doc = "Priority of system handler 15, SysTick exception"] - pub mod PRI_15 { - pub const offset: u32 = 24; - pub const mask: u32 = 0xff << offset; - pub mod R {} - pub mod W {} - pub mod RW {} - } -} -#[doc = "System Handler Control and State Register"] -pub mod SHCSR { - #[doc = "MemManage exception active bit"] - pub mod MEMFAULTACT { - pub const offset: u32 = 0; - pub const mask: u32 = 0x01 << offset; - pub mod R {} - pub mod W {} - pub mod RW { - #[doc = "exception is not active"] - pub const MEMFAULTACT_0: u32 = 0; - #[doc = "exception is active"] - pub const MEMFAULTACT_1: u32 = 0x01; - } - } - #[doc = "BusFault exception active bit"] - pub mod BUSFAULTACT { - pub const offset: u32 = 1; - pub const mask: u32 = 0x01 << offset; - pub mod R {} - pub mod W {} - pub mod RW { - #[doc = "exception is not active"] - pub const BUSFAULTACT_0: u32 = 0; - #[doc = "exception is active"] - pub const BUSFAULTACT_1: u32 = 0x01; - } - } - #[doc = "UsageFault exception active bit"] - pub mod USGFAULTACT { - pub const offset: u32 = 3; - pub const mask: u32 = 0x01 << offset; - pub mod R {} - pub mod W {} - pub mod RW { - #[doc = "exception is not active"] - pub const USGFAULTACT_0: u32 = 0; - #[doc = "exception is active"] - pub const USGFAULTACT_1: u32 = 0x01; - } - } - #[doc = "SVCall active bit"] - pub mod SVCALLACT { - pub const offset: u32 = 7; - pub const mask: u32 = 0x01 << offset; - pub mod R {} - pub mod W {} - pub mod RW { - #[doc = "exception is not active"] - pub const SVCALLACT_0: u32 = 0; - #[doc = "exception is active"] - pub const SVCALLACT_1: u32 = 0x01; - } - } - #[doc = "Debug monitor active bit"] - pub mod MONITORACT { - pub const offset: u32 = 8; - pub const mask: u32 = 0x01 << offset; - pub mod R {} - pub mod W {} - pub mod RW { - #[doc = "exception is not active"] - pub const MONITORACT_0: u32 = 0; - #[doc = "exception is active"] - pub const MONITORACT_1: u32 = 0x01; - } - } - #[doc = "PendSV exception active bit"] - pub mod PENDSVACT { - pub const offset: u32 = 10; - pub const mask: u32 = 0x01 << offset; - pub mod R {} - pub mod W {} - pub mod RW { - #[doc = "exception is not active"] - pub const PENDSVACT_0: u32 = 0; - #[doc = "exception is active"] - pub const PENDSVACT_1: u32 = 0x01; - } - } - #[doc = "SysTick exception active bit"] - pub mod SYSTICKACT { - pub const offset: u32 = 11; - pub const mask: u32 = 0x01 << offset; - pub mod R {} - pub mod W {} - pub mod RW { - #[doc = "exception is not active"] - pub const SYSTICKACT_0: u32 = 0; - #[doc = "exception is active"] - pub const SYSTICKACT_1: u32 = 0x01; - } - } - #[doc = "UsageFault exception pending bit"] - pub mod USGFAULTPENDED { - pub const offset: u32 = 12; - pub const mask: u32 = 0x01 << offset; - pub mod R {} - pub mod W {} - pub mod RW { - #[doc = "exception is not pending"] - pub const USGFAULTPENDED_0: u32 = 0; - #[doc = "exception is pending"] - pub const USGFAULTPENDED_1: u32 = 0x01; - } - } - #[doc = "MemManage exception pending bit"] - pub mod MEMFAULTPENDED { - pub const offset: u32 = 13; - pub const mask: u32 = 0x01 << offset; - pub mod R {} - pub mod W {} - pub mod RW { - #[doc = "exception is not pending"] - pub const MEMFAULTPENDED_0: u32 = 0; - #[doc = "exception is pending"] - pub const MEMFAULTPENDED_1: u32 = 0x01; - } - } - #[doc = "BusFault exception pending bit"] - pub mod BUSFAULTPENDED { - pub const offset: u32 = 14; - pub const mask: u32 = 0x01 << offset; - pub mod R {} - pub mod W {} - pub mod RW { - #[doc = "exception is not pending"] - pub const BUSFAULTPENDED_0: u32 = 0; - #[doc = "exception is pending"] - pub const BUSFAULTPENDED_1: u32 = 0x01; - } - } - #[doc = "SVCall pending bit"] - pub mod SVCALLPENDED { - pub const offset: u32 = 15; - pub const mask: u32 = 0x01 << offset; - pub mod R {} - pub mod W {} - pub mod RW { - #[doc = "exception is not pending"] - pub const SVCALLPENDED_0: u32 = 0; - #[doc = "exception is pending"] - pub const SVCALLPENDED_1: u32 = 0x01; - } - } - #[doc = "MemManage enable bit"] - pub mod MEMFAULTENA { - pub const offset: u32 = 16; - pub const mask: u32 = 0x01 << offset; - pub mod R {} - pub mod W {} - pub mod RW { - #[doc = "disable the exception"] - pub const MEMFAULTENA_0: u32 = 0; - #[doc = "enable the exception"] - pub const MEMFAULTENA_1: u32 = 0x01; - } - } - #[doc = "BusFault enable bit"] - pub mod BUSFAULTENA { - pub const offset: u32 = 17; - pub const mask: u32 = 0x01 << offset; - pub mod R {} - pub mod W {} - pub mod RW { - #[doc = "disable the exception"] - pub const BUSFAULTENA_0: u32 = 0; - #[doc = "enable the exception"] - pub const BUSFAULTENA_1: u32 = 0x01; - } - } - #[doc = "UsageFault enable bit"] - pub mod USGFAULTENA { - pub const offset: u32 = 18; - pub const mask: u32 = 0x01 << offset; - pub mod R {} - pub mod W {} - pub mod RW { - #[doc = "disable the exception"] - pub const USGFAULTENA_0: u32 = 0; - #[doc = "enable the exception"] - pub const USGFAULTENA_1: u32 = 0x01; - } - } -} -#[doc = "Configurable Fault Status Register"] -pub mod CFSR { - #[doc = "Instruction access violation flag"] - pub mod IACCVIOL { - pub const offset: u32 = 0; - pub const mask: u32 = 0x01 << offset; - pub mod R {} - pub mod W {} - pub mod RW { - #[doc = "no instruction access violation fault"] - pub const IACCVIOL_0: u32 = 0; - #[doc = "the processor attempted an instruction fetch from a location that does not permit execution"] - pub const IACCVIOL_1: u32 = 0x01; - } - } - #[doc = "Data access violation flag"] - pub mod DACCVIOL { - pub const offset: u32 = 1; - pub const mask: u32 = 0x01 << offset; - pub mod R {} - pub mod W {} - pub mod RW { - #[doc = "no data access violation fault"] - pub const DACCVIOL_0: u32 = 0; - #[doc = "the processor attempted a load or store at a location that does not permit the operation"] - pub const DACCVIOL_1: u32 = 0x01; - } - } - #[doc = "MemManage fault on unstacking for a return from exception"] - pub mod MUNSTKERR { - pub const offset: u32 = 3; - pub const mask: u32 = 0x01 << offset; - pub mod R {} - pub mod W {} - pub mod RW { - #[doc = "no unstacking fault"] - pub const MUNSTKERR_0: u32 = 0; - #[doc = "unstack for an exception return has caused one or more access violations"] - pub const MUNSTKERR_1: u32 = 0x01; - } - } - #[doc = "MemManage fault on stacking for exception entry"] - pub mod MSTKERR { - pub const offset: u32 = 4; - pub const mask: u32 = 0x01 << offset; - pub mod R {} - pub mod W {} - pub mod RW { - #[doc = "no stacking fault"] - pub const MSTKERR_0: u32 = 0; - #[doc = "stacking for an exception entry has caused one or more access violations"] - pub const MSTKERR_1: u32 = 0x01; - } - } - #[doc = "MemManage fault occurred during floating-point lazy state preservation"] - pub mod MLSPERR { - pub const offset: u32 = 5; - pub const mask: u32 = 0x01 << offset; - pub mod R {} - pub mod W {} - pub mod RW { - #[doc = "No MemManage fault occurred during floating-point lazy state preservation"] - pub const MLSPERR_0: u32 = 0; - #[doc = "A MemManage fault occurred during floating-point lazy state preservation"] - pub const MLSPERR_1: u32 = 0x01; - } - } - #[doc = "MemManage Fault Address Register (MMFAR) valid flag"] - pub mod MMARVALID { - pub const offset: u32 = 7; - pub const mask: u32 = 0x01 << offset; - pub mod R {} - pub mod W {} - pub mod RW { - #[doc = "value in MMAR is not a valid fault address"] - pub const MMARVALID_0: u32 = 0; - #[doc = "MMAR holds a valid fault address"] - pub const MMARVALID_1: u32 = 0x01; - } - } - #[doc = "Instruction bus error"] - pub mod IBUSERR { - pub const offset: u32 = 8; - pub const mask: u32 = 0x01 << offset; - pub mod R {} - pub mod W {} - pub mod RW { - #[doc = "no instruction bus error"] - pub const IBUSERR_0: u32 = 0; - #[doc = "instruction bus error"] - pub const IBUSERR_1: u32 = 0x01; - } - } - #[doc = "Precise data bus error"] - pub mod PRECISERR { - pub const offset: u32 = 9; - pub const mask: u32 = 0x01 << offset; - pub mod R {} - pub mod W {} - pub mod RW { - #[doc = "no precise data bus error"] - pub const PRECISERR_0: u32 = 0; - #[doc = "a data bus error has occurred, and the PC value stacked for the exception return points to the instruction that caused the fault"] - pub const PRECISERR_1: u32 = 0x01; - } - } - #[doc = "Imprecise data bus error"] - pub mod IMPRECISERR { - pub const offset: u32 = 10; - pub const mask: u32 = 0x01 << offset; - pub mod R {} - pub mod W {} - pub mod RW { - #[doc = "no imprecise data bus error"] - pub const IMPRECISERR_0: u32 = 0; - #[doc = "a data bus error has occurred, but the return address in the stack frame is not related to the instruction that caused the error"] - pub const IMPRECISERR_1: u32 = 0x01; - } - } - #[doc = "BusFault on unstacking for a return from exception"] - pub mod UNSTKERR { - pub const offset: u32 = 11; - pub const mask: u32 = 0x01 << offset; - pub mod R {} - pub mod W {} - pub mod RW { - #[doc = "no unstacking fault"] - pub const UNSTKERR_0: u32 = 0; - #[doc = "unstack for an exception return has caused one or more BusFaults"] - pub const UNSTKERR_1: u32 = 0x01; - } - } - #[doc = "BusFault on stacking for exception entry"] - pub mod STKERR { - pub const offset: u32 = 12; - pub const mask: u32 = 0x01 << offset; - pub mod R {} - pub mod W {} - pub mod RW { - #[doc = "no stacking fault"] - pub const STKERR_0: u32 = 0; - #[doc = "stacking for an exception entry has caused one or more BusFaults"] - pub const STKERR_1: u32 = 0x01; - } - } - #[doc = "Bus fault occurred during floating-point lazy state preservation"] - pub mod LSPERR { - pub const offset: u32 = 13; - pub const mask: u32 = 0x01 << offset; - pub mod R {} - pub mod W {} - pub mod RW { - #[doc = "No bus fault occurred during floating-point lazy state preservation"] - pub const LSPERR_0: u32 = 0; - #[doc = "A bus fault occurred during floating-point lazy state preservation"] - pub const LSPERR_1: u32 = 0x01; - } - } - #[doc = "BusFault Address Register (BFAR) valid flag"] - pub mod BFARVALID { - pub const offset: u32 = 15; - pub const mask: u32 = 0x01 << offset; - pub mod R {} - pub mod W {} - pub mod RW { - #[doc = "value in BFAR is not a valid fault address"] - pub const BFARVALID_0: u32 = 0; - #[doc = "BFAR holds a valid fault address"] - pub const BFARVALID_1: u32 = 0x01; - } - } - #[doc = "Undefined instruction UsageFault"] - pub mod UNDEFINSTR { - pub const offset: u32 = 16; - pub const mask: u32 = 0x01 << offset; - pub mod R {} - pub mod W {} - pub mod RW { - #[doc = "no undefined instruction UsageFault"] - pub const UNDEFINSTR_0: u32 = 0; - #[doc = "the processor has attempted to execute an undefined instruction"] - pub const UNDEFINSTR_1: u32 = 0x01; - } - } - #[doc = "Invalid state UsageFault"] - pub mod INVSTATE { - pub const offset: u32 = 17; - pub const mask: u32 = 0x01 << offset; - pub mod R {} - pub mod W {} - pub mod RW { - #[doc = "no invalid state UsageFault"] - pub const INVSTATE_0: u32 = 0; - #[doc = "the processor has attempted to execute an instruction that makes illegal use of the EPSR"] - pub const INVSTATE_1: u32 = 0x01; - } - } - #[doc = "Invalid PC load UsageFault, caused by an invalid PC load by EXC_RETURN"] - pub mod INVPC { - pub const offset: u32 = 18; - pub const mask: u32 = 0x01 << offset; - pub mod R {} - pub mod W {} - pub mod RW { - #[doc = "no invalid PC load UsageFault"] - pub const INVPC_0: u32 = 0; - #[doc = "the processor has attempted an illegal load of EXC_RETURN to the PC"] - pub const INVPC_1: u32 = 0x01; - } - } - #[doc = "No coprocessor UsageFault"] - pub mod NOCP { - pub const offset: u32 = 19; - pub const mask: u32 = 0x01 << offset; - pub mod R {} - pub mod W {} - pub mod RW { - #[doc = "no UsageFault caused by attempting to access a coprocessor"] - pub const NOCP_0: u32 = 0; - #[doc = "the processor has attempted to access a coprocessor"] - pub const NOCP_1: u32 = 0x01; - } - } - #[doc = "Unaligned access UsageFault"] - pub mod UNALIGNED { - pub const offset: u32 = 24; - pub const mask: u32 = 0x01 << offset; - pub mod R {} - pub mod W {} - pub mod RW { - #[doc = "no unaligned access fault, or unaligned access trapping not enabled"] - pub const UNALIGNED_0: u32 = 0; - #[doc = "the processor has made an unaligned memory access"] - pub const UNALIGNED_1: u32 = 0x01; - } - } - #[doc = "Divide by zero UsageFault"] - pub mod DIVBYZERO { - pub const offset: u32 = 25; - pub const mask: u32 = 0x01 << offset; - pub mod R {} - pub mod W {} - pub mod RW { - #[doc = "no divide by zero fault, or divide by zero trapping not enabled"] - pub const DIVBYZERO_0: u32 = 0; - #[doc = "the processor has executed an SDIV or UDIV instruction with a divisor of 0"] - pub const DIVBYZERO_1: u32 = 0x01; - } - } -} -#[doc = "HardFault Status register"] -pub mod HFSR { - #[doc = "Indicates a BusFault on a vector table read during exception processing."] - pub mod VECTTBL { - pub const offset: u32 = 1; - pub const mask: u32 = 0x01 << offset; - pub mod R {} - pub mod W {} - pub mod RW { - #[doc = "no BusFault on vector table read"] - pub const VECTTBL_0: u32 = 0; - #[doc = "BusFault on vector table read"] - pub const VECTTBL_1: u32 = 0x01; - } - } - #[doc = "Indicates a forced hard fault, generated by escalation of a fault with configurable priority that cannot be handles, either because of priority or because it is disabled."] - pub mod FORCED { - pub const offset: u32 = 30; - pub const mask: u32 = 0x01 << offset; - pub mod R {} - pub mod W {} - pub mod RW { - #[doc = "no forced HardFault"] - pub const FORCED_0: u32 = 0; - #[doc = "forced HardFault"] - pub const FORCED_1: u32 = 0x01; - } - } -} -#[doc = "Debug Fault Status Register"] -pub mod DFSR { - #[doc = "Indicates a debug event generated by either a C_HALT or C_STEP request, triggered by a write to the DHCSR or a step request triggered by setting DEMCR.MON_STEP to 1."] - pub mod HALTED { - pub const offset: u32 = 0; - pub const mask: u32 = 0x01 << offset; - pub mod R {} - pub mod W {} - pub mod RW { - #[doc = "No active halt request debug event"] - pub const HALTED_0: u32 = 0; - #[doc = "Halt request debug event active"] - pub const HALTED_1: u32 = 0x01; - } - } - #[doc = "Debug event generated by BKPT instruction execution or a breakpoint match in FPB"] - pub mod BKPT { - pub const offset: u32 = 1; - pub const mask: u32 = 0x01 << offset; - pub mod R {} - pub mod W {} - pub mod RW { - #[doc = "No current breakpoint debug event"] - pub const BKPT_0: u32 = 0; - #[doc = "At least one current breakpoint debug event"] - pub const BKPT_1: u32 = 0x01; - } - } - #[doc = "Debug event generated by the DWT"] - pub mod DWTTRAP { - pub const offset: u32 = 2; - pub const mask: u32 = 0x01 << offset; - pub mod R {} - pub mod W {} - pub mod RW { - #[doc = "No current debug events generated by the DWT"] - pub const DWTTRAP_0: u32 = 0; - #[doc = "At least one current debug event generated by the DWT"] - pub const DWTTRAP_1: u32 = 0x01; - } - } - #[doc = "Indicates triggering of a Vector catch"] - pub mod VCATCH { - pub const offset: u32 = 3; - pub const mask: u32 = 0x01 << offset; - pub mod R {} - pub mod W {} - pub mod RW { - #[doc = "No Vector catch triggered"] - pub const VCATCH_0: u32 = 0; - #[doc = "Vector catch triggered"] - pub const VCATCH_1: u32 = 0x01; - } - } - #[doc = "Debug event generated because of the assertion of an external debug request"] - pub mod EXTERNAL { - pub const offset: u32 = 4; - pub const mask: u32 = 0x01 << offset; - pub mod R {} - pub mod W {} - pub mod RW { - #[doc = "No external debug request debug event"] - pub const EXTERNAL_0: u32 = 0; - #[doc = "External debug request debug event"] - pub const EXTERNAL_1: u32 = 0x01; - } - } -} -#[doc = "MemManage Fault Address Register"] -pub mod MMFAR { - #[doc = "Address of MemManage fault location"] - pub mod ADDRESS { - pub const offset: u32 = 0; - pub const mask: u32 = 0xffff_ffff << offset; - pub mod R {} - pub mod W {} - pub mod RW {} - } -} -#[doc = "BusFault Address Register"] -pub mod BFAR { - #[doc = "Address of the BusFault location"] - pub mod ADDRESS { - pub const offset: u32 = 0; - pub const mask: u32 = 0xffff_ffff << offset; - pub mod R {} - pub mod W {} - pub mod RW {} - } -} -#[doc = "Processor Feature Register 0"] -pub mod ID_PFR0 { - #[doc = "ARM instruction set support"] - pub mod STATE0 { - pub const offset: u32 = 0; - pub const mask: u32 = 0x0f << offset; - pub mod R {} - pub mod W {} - pub mod RW { - #[doc = "ARMv7-M unused"] - pub const STATE0_0: u32 = 0; - #[doc = "ARMv7-M unused"] - pub const STATE0_1: u32 = 0x01; - #[doc = "ARMv7-M unused"] - pub const STATE0_2: u32 = 0x02; - #[doc = "Support for Thumb encoding including Thumb-2 technology, with all basic 16-bit and 32-bit instructions."] - pub const STATE0_3: u32 = 0x03; - } - } - #[doc = "Thumb instruction set support"] - pub mod STATE1 { - pub const offset: u32 = 4; - pub const mask: u32 = 0x0f << offset; - pub mod R {} - pub mod W {} - pub mod RW { - #[doc = "The processor does not support the ARM instruction set."] - pub const STATE1_0: u32 = 0; - #[doc = "ARMv7-M unused"] - pub const STATE1_1: u32 = 0x01; - } - } - #[doc = "ARMv7-M unused"] - pub mod STATE2 { - pub const offset: u32 = 8; - pub const mask: u32 = 0x0f << offset; - pub mod R {} - pub mod W {} - pub mod RW {} - } - #[doc = "ARMv7-M unused"] - pub mod STATE3 { - pub const offset: u32 = 12; - pub const mask: u32 = 0x0f << offset; - pub mod R {} - pub mod W {} - pub mod RW {} - } -} -#[doc = "Processor Feature Register 1"] -pub mod ID_PFR1 { - #[doc = "M profile programmers' model"] - pub mod PROGMODEL { - pub const offset: u32 = 8; - pub const mask: u32 = 0x0f << offset; - pub mod R {} - pub mod W {} - pub mod RW { - #[doc = "ARMv7-M unused"] - pub const PROGMODEL_0: u32 = 0; - #[doc = "Two-stack programmers' model supported"] - pub const PROGMODEL_2: u32 = 0x02; - } - } -} -#[doc = "Debug Feature Register"] -pub mod ID_DFR0 { - #[doc = "Support for memory-mapped debug model for M profile processors"] - pub mod DEBUGMODEL { - pub const offset: u32 = 20; - pub const mask: u32 = 0x0f << offset; - pub mod R {} - pub mod W {} - pub mod RW { - #[doc = "Not supported"] - pub const DEBUGMODEL_0: u32 = 0; - #[doc = "Support for M profile Debug architecture, with memory-mapped access."] - pub const DEBUGMODEL_1: u32 = 0x01; - } - } -} -#[doc = "Auxiliary Feature Register"] -pub mod ID_AFR0 { - #[doc = "Gives information about the IMPLEMENTATION DEFINED features of a processor implementation."] - pub mod IMPLEMENTATION_DEFINED0 { - pub const offset: u32 = 0; - pub const mask: u32 = 0x0f << offset; - pub mod R {} - pub mod W {} - pub mod RW {} - } - #[doc = "Gives information about the IMPLEMENTATION DEFINED features of a processor implementation."] - pub mod IMPLEMENTATION_DEFINED1 { - pub const offset: u32 = 4; - pub const mask: u32 = 0x0f << offset; - pub mod R {} - pub mod W {} - pub mod RW {} - } - #[doc = "Gives information about the IMPLEMENTATION DEFINED features of a processor implementation."] - pub mod IMPLEMENTATION_DEFINED2 { - pub const offset: u32 = 8; - pub const mask: u32 = 0x0f << offset; - pub mod R {} - pub mod W {} - pub mod RW {} - } - #[doc = "Gives information about the IMPLEMENTATION DEFINED features of a processor implementation."] - pub mod IMPLEMENTATION_DEFINED3 { - pub const offset: u32 = 12; - pub const mask: u32 = 0x0f << offset; - pub mod R {} - pub mod W {} - pub mod RW {} - } -} -#[doc = "Memory Model Feature Register 0"] -pub mod ID_MMFR0 { - #[doc = "Indicates support for a PMSA"] - pub mod PMSASUPPORT { - pub const offset: u32 = 4; - pub const mask: u32 = 0x0f << offset; - pub mod R {} - pub mod W {} - pub mod RW { - #[doc = "Not supported"] - pub const PMSASUPPORT_0: u32 = 0; - #[doc = "ARMv7-M unused"] - pub const PMSASUPPORT_1: u32 = 0x01; - #[doc = "ARMv7-M unused"] - pub const PMSASUPPORT_2: u32 = 0x02; - #[doc = "PMSAv7, providing support for a base region and subregions."] - pub const PMSASUPPORT_3: u32 = 0x03; - } - } - #[doc = "Indicates the outermost shareability domain implemented"] - pub mod OUTERMOST_SHAREABILITY { - pub const offset: u32 = 8; - pub const mask: u32 = 0x0f << offset; - pub mod R {} - pub mod W {} - pub mod RW { - #[doc = "Implemented as Non-cacheable"] - pub const OUTERMOST_SHAREABILITY_0: u32 = 0; - #[doc = "ARMv7-M unused"] - pub const OUTERMOST_SHAREABILITY_1: u32 = 0x01; - #[doc = "ARMv7-M unused"] - pub const OUTERMOST_SHAREABILITY_2: u32 = 0x02; - #[doc = "ARMv7-M unused"] - pub const OUTERMOST_SHAREABILITY_3: u32 = 0x03; - #[doc = "ARMv7-M unused"] - pub const OUTERMOST_SHAREABILITY_4: u32 = 0x04; - #[doc = "ARMv7-M unused"] - pub const OUTERMOST_SHAREABILITY_5: u32 = 0x05; - #[doc = "ARMv7-M unused"] - pub const OUTERMOST_SHAREABILITY_6: u32 = 0x06; - #[doc = "ARMv7-M unused"] - pub const OUTERMOST_SHAREABILITY_7: u32 = 0x07; - #[doc = "ARMv7-M unused"] - pub const OUTERMOST_SHAREABILITY_8: u32 = 0x08; - #[doc = "ARMv7-M unused"] - pub const OUTERMOST_SHAREABILITY_9: u32 = 0x09; - #[doc = "ARMv7-M unused"] - pub const OUTERMOST_SHAREABILITY_10: u32 = 0x0a; - #[doc = "ARMv7-M unused"] - pub const OUTERMOST_SHAREABILITY_11: u32 = 0x0b; - #[doc = "ARMv7-M unused"] - pub const OUTERMOST_SHAREABILITY_12: u32 = 0x0c; - #[doc = "ARMv7-M unused"] - pub const OUTERMOST_SHAREABILITY_13: u32 = 0x0d; - #[doc = "ARMv7-M unused"] - pub const OUTERMOST_SHAREABILITY_14: u32 = 0x0e; - #[doc = "Shareability ignored."] - pub const OUTERMOST_SHAREABILITY_15: u32 = 0x0f; - } - } - #[doc = "Indicates the number of shareability levels implemented"] - pub mod SHAREABILITY_LEVELS { - pub const offset: u32 = 12; - pub const mask: u32 = 0x0f << offset; - pub mod R {} - pub mod W {} - pub mod RW { - #[doc = "One level of shareability implemented"] - pub const SHAREABILITY_LEVELS_0: u32 = 0; - #[doc = "ARMv7-M unused"] - pub const SHAREABILITY_LEVELS_1: u32 = 0x01; - } - } - #[doc = "Indicates the support for Tightly Coupled Memory"] - pub mod TCM_SUPPORT { - pub const offset: u32 = 16; - pub const mask: u32 = 0x0f << offset; - pub mod R {} - pub mod W {} - pub mod RW { - #[doc = "No tightly coupled memories implemented."] - pub const TCM_SUPPORT_0: u32 = 0; - #[doc = "Tightly coupled memories implemented with IMPLEMENTATION DEFINED control."] - pub const TCM_SUPPORT_1: u32 = 0x01; - #[doc = "ARMv7-M unused"] - pub const TCM_SUPPORT_2: u32 = 0x02; - } - } - #[doc = "Indicates the support for Auxiliary registers"] - pub mod AUXILIARY_REGISTERS { - pub const offset: u32 = 20; - pub const mask: u32 = 0x0f << offset; - pub mod R {} - pub mod W {} - pub mod RW { - #[doc = "Not supported"] - pub const AUXILIARY_REGISTERS_0: u32 = 0; - #[doc = "Support for Auxiliary Control Register only."] - pub const AUXILIARY_REGISTERS_1: u32 = 0x01; - #[doc = "ARMv7-M unused"] - pub const AUXILIARY_REGISTERS_2: u32 = 0x02; - } - } -} -#[doc = "Memory Model Feature Register 1"] -pub mod ID_MMFR1 { - #[doc = "Gives information about the implemented memory model and memory management support."] - pub mod ID_MMFR1 { - pub const offset: u32 = 0; - pub const mask: u32 = 0xffff_ffff << offset; - pub mod R {} - pub mod W {} - pub mod RW {} - } -} -#[doc = "Memory Model Feature Register 2"] -pub mod ID_MMFR2 { - #[doc = "Indicates the support for Wait For Interrupt (WFI) stalling"] - pub mod WFI_STALL { - pub const offset: u32 = 24; - pub const mask: u32 = 0x0f << offset; - pub mod R {} - pub mod W {} - pub mod RW { - #[doc = "Not supported"] - pub const WFI_STALL_0: u32 = 0; - #[doc = "Support for WFI stalling"] - pub const WFI_STALL_1: u32 = 0x01; - } - } -} -#[doc = "Memory Model Feature Register 3"] -pub mod ID_MMFR3 { - #[doc = "Gives information about the implemented memory model and memory management support."] - pub mod ID_MMFR3 { - pub const offset: u32 = 0; - pub const mask: u32 = 0xffff_ffff << offset; - pub mod R {} - pub mod W {} - pub mod RW {} - } -} -#[doc = "Instruction Set Attributes Register 0"] -pub mod ID_ISAR0 { - #[doc = "Indicates the supported Bit Counting instructions"] - pub mod BITCOUNT_INSTRS { - pub const offset: u32 = 4; - pub const mask: u32 = 0x0f << offset; - pub mod R {} - pub mod W {} - pub mod RW { - #[doc = "None supported, ARMv7-M unused"] - pub const BITCOUNT_INSTRS_0: u32 = 0; - #[doc = "Adds support for the CLZ instruction"] - pub const BITCOUNT_INSTRS_1: u32 = 0x01; - } - } - #[doc = "Indicates the supported BitField instructions"] - pub mod BITFIELD_INSTRS { - pub const offset: u32 = 8; - pub const mask: u32 = 0x0f << offset; - pub mod R {} - pub mod W {} - pub mod RW { - #[doc = "None supported, ARMv7-M unused"] - pub const BITFIELD_INSTRS_0: u32 = 0; - #[doc = "Adds support for the BFC, BFI, SBFX, and UBFX instructions"] - pub const BITFIELD_INSTRS_1: u32 = 0x01; - } - } - #[doc = "Indicates the supported combined Compare and Branch instructions"] - pub mod CMPBRANCH_INSTRS { - pub const offset: u32 = 12; - pub const mask: u32 = 0x0f << offset; - pub mod R {} - pub mod W {} - pub mod RW { - #[doc = "None supported, ARMv7-M unused"] - pub const CMPBRANCH_INSTRS_0: u32 = 0; - #[doc = "Adds support for the CBNZ and CBZ instructions"] - pub const CMPBRANCH_INSTRS_1: u32 = 0x01; - } - } - #[doc = "Indicates the supported Coprocessor instructions"] - pub mod COPROC_INSTRS { - pub const offset: u32 = 16; - pub const mask: u32 = 0x0f << offset; - pub mod R {} - pub mod W {} - pub mod RW { - #[doc = "None supported, except for separately attributed architectures, for example the Floating-point extension"] - pub const COPROC_INSTRS_0: u32 = 0; - #[doc = "Adds support for generic CDP, LDC, MCR, MRC, and STC instructions"] - pub const COPROC_INSTRS_1: u32 = 0x01; - #[doc = "As for 1, and adds support for generic CDP2, LDC2, MCR2, MRC2, and STC2 instructions"] - pub const COPROC_INSTRS_2: u32 = 0x02; - #[doc = "As for 2, and adds support for generic MCRR and MRRC instructions"] - pub const COPROC_INSTRS_3: u32 = 0x03; - #[doc = "As for 3, and adds support for generic MCRR2 and MRRC2 instructions"] - pub const COPROC_INSTRS_4: u32 = 0x04; - } - } - #[doc = "Indicates the supported Debug instructions"] - pub mod DEBUG_INSTRS { - pub const offset: u32 = 20; - pub const mask: u32 = 0x0f << offset; - pub mod R {} - pub mod W {} - pub mod RW { - #[doc = "None supported, ARMv7-M unused"] - pub const DEBUG_INSTRS_0: u32 = 0; - #[doc = "Adds support for the BKPT instruction"] - pub const DEBUG_INSTRS_1: u32 = 0x01; - } - } - #[doc = "Indicates the supported Divide instructions"] - pub mod DIVIDE_INSTRS { - pub const offset: u32 = 24; - pub const mask: u32 = 0x0f << offset; - pub mod R {} - pub mod W {} - pub mod RW { - #[doc = "None supported, ARMv7-M unused"] - pub const DIVIDE_INSTRS_0: u32 = 0; - #[doc = "Adds support for the SDIV and UDIV instructions"] - pub const DIVIDE_INSTRS_1: u32 = 0x01; - } - } -} -#[doc = "Instruction Set Attributes Register 1"] -pub mod ID_ISAR1 { - #[doc = "Indicates the supported Extend instructions"] - pub mod EXTEND_INSTRS { - pub const offset: u32 = 12; - pub const mask: u32 = 0x0f << offset; - pub mod R {} - pub mod W {} - pub mod RW { - #[doc = "None supported, ARMv7-M unused"] - pub const EXTEND_INSTRS_0: u32 = 0; - #[doc = "Adds support for the SXTB, SXTH, UXTB, and UXTH instructions"] - pub const EXTEND_INSTRS_1: u32 = 0x01; - #[doc = "As for 1, and adds support for the SXTAB, SXTAB16, SXTAH, SXTB16, UXTAB, UXTAB16, UXTAH, and UXTB16 instructions"] - pub const EXTEND_INSTRS_2: u32 = 0x02; - } - } - #[doc = "Indicates the supported IfThen instructions"] - pub mod IFTHEN_INSTRS { - pub const offset: u32 = 16; - pub const mask: u32 = 0x0f << offset; - pub mod R {} - pub mod W {} - pub mod RW { - #[doc = "None supported, ARMv7-M unused"] - pub const IFTHEN_INSTRS_0: u32 = 0; - #[doc = "Adds support for the IT instructions, and for the IT bits in the PSRs"] - pub const IFTHEN_INSTRS_1: u32 = 0x01; - } - } - #[doc = "Indicates the support for data-processing instructions with long immediate"] - pub mod IMMEDIATE_INSTRS { - pub const offset: u32 = 20; - pub const mask: u32 = 0x0f << offset; - pub mod R {} - pub mod W {} - pub mod RW { - #[doc = "None supported, ARMv7-M unused"] - pub const IMMEDIATE_INSTRS_0: u32 = 0; - #[doc = "Adds support for the ADDW, MOVW, MOVT, and SUBW instructions"] - pub const IMMEDIATE_INSTRS_1: u32 = 0x01; - } - } - #[doc = "Indicates the supported Interworking instructions"] - pub mod INTERWORK_INSTRS { - pub const offset: u32 = 24; - pub const mask: u32 = 0x0f << offset; - pub mod R {} - pub mod W {} - pub mod RW { - #[doc = "None supported, ARMv7-M unused"] - pub const INTERWORK_INSTRS_0: u32 = 0; - #[doc = "Adds support for the BX instruction, and the T bit in the PSR"] - pub const INTERWORK_INSTRS_1: u32 = 0x01; - #[doc = "As for 1, and adds support for the BLX instruction, and PC loads have BX-like behavior"] - pub const INTERWORK_INSTRS_2: u32 = 0x02; - #[doc = "ARMv7-M unused"] - pub const INTERWORK_INSTRS_3: u32 = 0x03; - } - } -} -#[doc = "Instruction Set Attributes Register 2"] -pub mod ID_ISAR2 { - #[doc = "Indicates the supported additional load and store instructions"] - pub mod LOADSTORE_INSTRS { - pub const offset: u32 = 0; - pub const mask: u32 = 0x0f << offset; - pub mod R {} - pub mod W {} - pub mod RW { - #[doc = "None supported, ARMv7-M unused"] - pub const LOADSTORE_INSTRS_0: u32 = 0; - #[doc = "Adds support for the LDRD and STRD instructions"] - pub const LOADSTORE_INSTRS_1: u32 = 0x01; - } - } - #[doc = "Indicates the supported Memory Hint instructions"] - pub mod MEMHINT_INSTRS { - pub const offset: u32 = 4; - pub const mask: u32 = 0x0f << offset; - pub mod R {} - pub mod W {} - pub mod RW { - #[doc = "None supported, ARMv7-M unused."] - pub const MEMHINT_INSTRS_0: u32 = 0; - #[doc = "Adds support for the PLD instruction, ARMv7-M unused."] - pub const MEMHINT_INSTRS_1: u32 = 0x01; - #[doc = "As for 1, ARMv7-M unused."] - pub const MEMHINT_INSTRS_2: u32 = 0x02; - #[doc = "As for 1 or 2, and adds support for the PLI instruction."] - pub const MEMHINT_INSTRS_3: u32 = 0x03; - } - } - #[doc = "Indicates the support for multi-access interruptible instructions"] - pub mod MULTIACCESSINT_INSTRS { - pub const offset: u32 = 8; - pub const mask: u32 = 0x0f << offset; - pub mod R {} - pub mod W {} - pub mod RW { - #[doc = "None supported. This means the LDM and STM instructions are not interruptible. ARMv7-M unused."] - pub const MULTIACCESSINT_INSTRS_0: u32 = 0; - #[doc = "LDM and STM instructions are restartable."] - pub const MULTIACCESSINT_INSTRS_1: u32 = 0x01; - #[doc = "LDM and STM instructions are continuable."] - pub const MULTIACCESSINT_INSTRS_2: u32 = 0x02; - } - } - #[doc = "Indicates the supported additional Multiply instructions"] - pub mod MULT_INSTRS { - pub const offset: u32 = 12; - pub const mask: u32 = 0x0f << offset; - pub mod R {} - pub mod W {} - pub mod RW { - #[doc = "None supported. This means only MUL is supported. ARMv7-M unused."] - pub const MULT_INSTRS_0: u32 = 0; - #[doc = "Adds support for the MLA instruction, ARMv7-M unused."] - pub const MULT_INSTRS_1: u32 = 0x01; - #[doc = "As for 1, and adds support for the MLS instruction."] - pub const MULT_INSTRS_2: u32 = 0x02; - } - } - #[doc = "Indicates the supported advanced signed Multiply instructions"] - pub mod MULTS_INSTRS { - pub const offset: u32 = 16; - pub const mask: u32 = 0x0f << offset; - pub mod R {} - pub mod W {} - pub mod RW { - #[doc = "None supported, ARMv7-M unused"] - pub const MULTS_INSTRS_0: u32 = 0; - #[doc = "Adds support for the SMULL and SMLAL instructions"] - pub const MULTS_INSTRS_1: u32 = 0x01; - #[doc = "As for 1, and adds support for the SMLABB, SMLABT, SMLALBB, SMLALBT, SMLALTB, SMLALTT, SMLATB, SMLATT, SMLAWB, SMLAWT, SMULBB, SMULBT, SMULTB, SMULTT, SMULWB, and SMULWT instructions."] - pub const MULTS_INSTRS_2: u32 = 0x02; - #[doc = "As for 2, and adds support for the SMLAD, SMLADX, SMLALD, SMLALDX, SMLSD, SMLSDX, SMLSLD, SMLSLDX, SMMLA, SMMLAR, SMMLS, SMMLSR, SMMUL, SMMULR, SMUAD, SMUADX, SMUSD, and SMUSDX instructions."] - pub const MULTS_INSTRS_3: u32 = 0x03; - } - } - #[doc = "Indicates the supported advanced unsigned Multiply instructions"] - pub mod MULTU_INSTRS { - pub const offset: u32 = 20; - pub const mask: u32 = 0x0f << offset; - pub mod R {} - pub mod W {} - pub mod RW { - #[doc = "None supported, ARMv7-M unused"] - pub const MULTU_INSTRS_0: u32 = 0; - #[doc = "Adds support for the UMULL and UMLAL instructions."] - pub const MULTU_INSTRS_1: u32 = 0x01; - #[doc = "As for 1, and adds support for the UMAAL instruction."] - pub const MULTU_INSTRS_2: u32 = 0x02; - } - } - #[doc = "Indicates the supported Reversal instructions"] - pub mod REVERSAL_INSTRS { - pub const offset: u32 = 28; - pub const mask: u32 = 0x0f << offset; - pub mod R {} - pub mod W {} - pub mod RW { - #[doc = "None supported, ARMv7-M unused"] - pub const REVERSAL_INSTRS_0: u32 = 0; - #[doc = "Adds support for the REV, REV16, and REVSH instructions, ARMv7-M unused."] - pub const REVERSAL_INSTRS_1: u32 = 0x01; - #[doc = "As for 1, and adds support for the RBIT instruction."] - pub const REVERSAL_INSTRS_2: u32 = 0x02; - } - } -} -#[doc = "Instruction Set Attributes Register 3"] -pub mod ID_ISAR3 { - #[doc = "Indicates the supported Saturate instructions"] - pub mod SATURATE_INSTRS { - pub const offset: u32 = 0; - pub const mask: u32 = 0x0f << offset; - pub mod R {} - pub mod W {} - pub mod RW { - #[doc = "None supported"] - pub const SATURATE_INSTRS_0: u32 = 0; - #[doc = "Adds support for the QADD, QDADD, QDSUB, and QSUB instructions, and for the Q bit in the PSRs."] - pub const SATURATE_INSTRS_1: u32 = 0x01; - } - } - #[doc = "Indicates the supported SIMD instructions"] - pub mod SIMD_INSTRS { - pub const offset: u32 = 4; - pub const mask: u32 = 0x0f << offset; - pub mod R {} - pub mod W {} - pub mod RW { - #[doc = "None supported, ARMv7-M unused."] - pub const SIMD_INSTRS_0: u32 = 0; - #[doc = "Adds support for the SSAT and USAT instructions, and for the Q bit in the PSRs."] - pub const SIMD_INSTRS_1: u32 = 0x01; - #[doc = "As for 1, and adds support for the PKHBT, PKHTB, QADD16, QADD8, QASX, QSUB16, QSUB8, QSAX, SADD16, SADD8, SASX, SEL, SHADD16, SHADD8, SHASX, SHSUB16, SHSUB8, SHSAX, SSAT16, SSUB16, SSUB8, SSAX, SXTAB16, SXTB16, UADD16, UADD8, UASX, UHADD16, UHADD8, UHASX, UHSUB16, UHSUB8, UHSAX, UQADD16, UQADD8, UQASX, UQSUB16, UQSUB8, UQSAX, USAD8, USADA8, USAT16, USUB16, USUB8, USAX, UXTAB16, and UXTB16 instructions. Also adds support for the GE\\[3:0\\] bits in the PSRs."] - pub const SIMD_INSTRS_3: u32 = 0x03; - } - } - #[doc = "Indicates the supported SVC instructions"] - pub mod SVC_INSTRS { - pub const offset: u32 = 8; - pub const mask: u32 = 0x0f << offset; - pub mod R {} - pub mod W {} - pub mod RW { - #[doc = "None supported, ARMv7-M unused."] - pub const SVC_INSTRS_0: u32 = 0; - #[doc = "Adds support for the SVC instruction."] - pub const SVC_INSTRS_1: u32 = 0x01; - } - } - #[doc = "Together with the ID_ISAR4\\[SYNCHPRIM_INSTRS_FRAC\\] indicates the supported Synchronization Primitives"] - pub mod SYNCHPRIM_INSTRS { - pub const offset: u32 = 12; - pub const mask: u32 = 0x0f << offset; - pub mod R {} - pub mod W {} - pub mod RW {} - } - #[doc = "Indicates the supported Table Branch instructions"] - pub mod TABBRANCH_INSTRS { - pub const offset: u32 = 16; - pub const mask: u32 = 0x0f << offset; - pub mod R {} - pub mod W {} - pub mod RW { - #[doc = "None supported, ARMv7-M unused."] - pub const TABBRANCH_INSTRS_0: u32 = 0; - #[doc = "Adds support for the TBB and TBH instructions."] - pub const TABBRANCH_INSTRS_1: u32 = 0x01; - } - } - #[doc = "Indicates the supported non flag-setting MOV instructions"] - pub mod THUMBCOPY_INSTRS { - pub const offset: u32 = 20; - pub const mask: u32 = 0x0f << offset; - pub mod R {} - pub mod W {} - pub mod RW { - #[doc = "None supported, ARMv7-M unused."] - pub const THUMBCOPY_INSTRS_0: u32 = 0; - #[doc = "Adds support for encoding T1 of the MOV (register) instruction copying from a low register to a low register."] - pub const THUMBCOPY_INSTRS_1: u32 = 0x01; - } - } - #[doc = "Indicates the supported non flag-setting MOV instructions"] - pub mod TRUENOP_INSTRS { - pub const offset: u32 = 24; - pub const mask: u32 = 0x0f << offset; - pub mod R {} - pub mod W {} - pub mod RW { - #[doc = "None supported, ARMv7-M unused."] - pub const TRUENOP_INSTRS_0: u32 = 0; - #[doc = "Adds support for encoding T1 of the MOV (register) instruction copying from a low register to a low register."] - pub const TRUENOP_INSTRS_1: u32 = 0x01; - } - } -} -#[doc = "Instruction Set Attributes Register 4"] -pub mod ID_ISAR4 { - #[doc = "Indicates the supported unprivileged instructions. These are the instruction variants indicated by a T suffix."] - pub mod UNPRIV_INSTRS { - pub const offset: u32 = 0; - pub const mask: u32 = 0x0f << offset; - pub mod R {} - pub mod W {} - pub mod RW { - #[doc = "None supported, ARMv7-M unused."] - pub const UNPRIV_INSTRS_0: u32 = 0; - #[doc = "Adds support for the LDRBT, LDRT, STRBT, and STRT instructions."] - pub const UNPRIV_INSTRS_1: u32 = 0x01; - #[doc = "As for 1, and adds support for the LDRHT, LDRSBT, LDRSHT, and STRHT instructions."] - pub const UNPRIV_INSTRS_2: u32 = 0x02; - } - } - #[doc = "Indicates the support for instructions with shifts"] - pub mod WITHSHIFTS_INSTRS { - pub const offset: u32 = 4; - pub const mask: u32 = 0x0f << offset; - pub mod R {} - pub mod W {} - pub mod RW { - #[doc = "Nonzero shifts supported only in MOV and shift instructions."] - pub const WITHSHIFTS_INSTRS_0: u32 = 0; - #[doc = "Adds support for shifts of loads and stores over the range LSL 0-3."] - pub const WITHSHIFTS_INSTRS_1: u32 = 0x01; - #[doc = "As for 1, and adds support for other constant shift options, on loads, stores, and other instructions."] - pub const WITHSHIFTS_INSTRS_3: u32 = 0x03; - #[doc = "ARMv7-M unused."] - pub const WITHSHIFTS_INSTRS_4: u32 = 0x04; - } - } - #[doc = "Indicates the support for Writeback addressing modes"] - pub mod WRITEBACK_INSTRS { - pub const offset: u32 = 8; - pub const mask: u32 = 0x0f << offset; - pub mod R {} - pub mod W {} - pub mod RW { - #[doc = "Basic support. Only the LDM, STM, PUSH, and POP instructions support writeback addressing modes. ARMv7-M unused."] - pub const WRITEBACK_INSTRS_0: u32 = 0; - #[doc = "Adds support for all of the writeback addressing modes defined in the ARMv7-M architecture."] - pub const WRITEBACK_INSTRS_1: u32 = 0x01; - } - } - #[doc = "Indicates the supported Barrier instructions"] - pub mod BARRIER_INSTRS { - pub const offset: u32 = 16; - pub const mask: u32 = 0x0f << offset; - pub mod R {} - pub mod W {} - pub mod RW { - #[doc = "None supported, ARMv7-M unused."] - pub const BARRIER_INSTRS_0: u32 = 0; - #[doc = "Adds support for the DMB, DSB, and ISB barrier instructions."] - pub const BARRIER_INSTRS_1: u32 = 0x01; - } - } - #[doc = "Together with the ID_ISAR3\\[SYNCHPRIM_INSTRS\\] indicates the supported Synchronization Primitives"] - pub mod SYNCHPRIM_INSTRS_FRAC { - pub const offset: u32 = 20; - pub const mask: u32 = 0x0f << offset; - pub mod R {} - pub mod W {} - pub mod RW {} - } - #[doc = "Indicates the supported M profile instructions to modify the PSRs"] - pub mod PSR_M_INSTRS { - pub const offset: u32 = 24; - pub const mask: u32 = 0x0f << offset; - pub mod R {} - pub mod W {} - pub mod RW { - #[doc = "None supported, ARMv7-M unused."] - pub const PSR_M_INSTRS_0: u32 = 0; - #[doc = "Adds support for the M-profile forms of the CPS, MRS, and MSR instructions, to access the PSRs."] - pub const PSR_M_INSTRS_1: u32 = 0x01; - } - } -} -#[doc = "Cache Level ID register"] -pub mod CLIDR { - #[doc = "Indicate the type of cache implemented at level 1."] - pub mod CL1 { - pub const offset: u32 = 0; - pub const mask: u32 = 0x07 << offset; - pub mod R {} - pub mod W {} - pub mod RW { - #[doc = "No cache"] - pub const CL1_0: u32 = 0; - #[doc = "Instruction cache only"] - pub const CL1_1: u32 = 0x01; - #[doc = "Data cache only"] - pub const CL1_2: u32 = 0x02; - #[doc = "Separate instruction and data caches"] - pub const CL1_3: u32 = 0x03; - #[doc = "Unified cache"] - pub const CL1_4: u32 = 0x04; - } - } - #[doc = "Indicate the type of cache implemented at level 2."] - pub mod CL2 { - pub const offset: u32 = 3; - pub const mask: u32 = 0x07 << offset; - pub mod R {} - pub mod W {} - pub mod RW { - #[doc = "No cache"] - pub const CL2_0: u32 = 0; - #[doc = "Instruction cache only"] - pub const CL2_1: u32 = 0x01; - #[doc = "Data cache only"] - pub const CL2_2: u32 = 0x02; - #[doc = "Separate instruction and data caches"] - pub const CL2_3: u32 = 0x03; - #[doc = "Unified cache"] - pub const CL2_4: u32 = 0x04; - } - } - #[doc = "Indicate the type of cache implemented at level 3."] - pub mod CL3 { - pub const offset: u32 = 6; - pub const mask: u32 = 0x07 << offset; - pub mod R {} - pub mod W {} - pub mod RW { - #[doc = "No cache"] - pub const CL3_0: u32 = 0; - #[doc = "Instruction cache only"] - pub const CL3_1: u32 = 0x01; - #[doc = "Data cache only"] - pub const CL3_2: u32 = 0x02; - #[doc = "Separate instruction and data caches"] - pub const CL3_3: u32 = 0x03; - #[doc = "Unified cache"] - pub const CL3_4: u32 = 0x04; - } - } - #[doc = "Indicate the type of cache implemented at level 4."] - pub mod CL4 { - pub const offset: u32 = 9; - pub const mask: u32 = 0x07 << offset; - pub mod R {} - pub mod W {} - pub mod RW { - #[doc = "No cache"] - pub const CL4_0: u32 = 0; - #[doc = "Instruction cache only"] - pub const CL4_1: u32 = 0x01; - #[doc = "Data cache only"] - pub const CL4_2: u32 = 0x02; - #[doc = "Separate instruction and data caches"] - pub const CL4_3: u32 = 0x03; - #[doc = "Unified cache"] - pub const CL4_4: u32 = 0x04; - } - } - #[doc = "Indicate the type of cache implemented at level 5."] - pub mod CL5 { - pub const offset: u32 = 12; - pub const mask: u32 = 0x07 << offset; - pub mod R {} - pub mod W {} - pub mod RW { - #[doc = "No cache"] - pub const CL5_0: u32 = 0; - #[doc = "Instruction cache only"] - pub const CL5_1: u32 = 0x01; - #[doc = "Data cache only"] - pub const CL5_2: u32 = 0x02; - #[doc = "Separate instruction and data caches"] - pub const CL5_3: u32 = 0x03; - #[doc = "Unified cache"] - pub const CL5_4: u32 = 0x04; - } - } - #[doc = "Indicate the type of cache implemented at level 6."] - pub mod CL6 { - pub const offset: u32 = 15; - pub const mask: u32 = 0x07 << offset; - pub mod R {} - pub mod W {} - pub mod RW { - #[doc = "No cache"] - pub const CL6_0: u32 = 0; - #[doc = "Instruction cache only"] - pub const CL6_1: u32 = 0x01; - #[doc = "Data cache only"] - pub const CL6_2: u32 = 0x02; - #[doc = "Separate instruction and data caches"] - pub const CL6_3: u32 = 0x03; - #[doc = "Unified cache"] - pub const CL6_4: u32 = 0x04; - } - } - #[doc = "Indicate the type of cache implemented at level 7."] - pub mod CL7 { - pub const offset: u32 = 18; - pub const mask: u32 = 0x07 << offset; - pub mod R {} - pub mod W {} - pub mod RW { - #[doc = "No cache"] - pub const CL7_0: u32 = 0; - #[doc = "Instruction cache only"] - pub const CL7_1: u32 = 0x01; - #[doc = "Data cache only"] - pub const CL7_2: u32 = 0x02; - #[doc = "Separate instruction and data caches"] - pub const CL7_3: u32 = 0x03; - #[doc = "Unified cache"] - pub const CL7_4: u32 = 0x04; - } - } - #[doc = "Level of Unification Inner Shareable for the cache hierarchy. This field is RAZ."] - pub mod LOUIS { - pub const offset: u32 = 21; - pub const mask: u32 = 0x07 << offset; - pub mod R {} - pub mod W {} - pub mod RW { - #[doc = "0"] - pub const LOUIS_0: u32 = 0; - #[doc = "1"] - pub const LOUIS_1: u32 = 0x01; - #[doc = "2"] - pub const LOUIS_2: u32 = 0x02; - #[doc = "3"] - pub const LOUIS_3: u32 = 0x03; - #[doc = "4"] - pub const LOUIS_4: u32 = 0x04; - #[doc = "5"] - pub const LOUIS_5: u32 = 0x05; - #[doc = "6"] - pub const LOUIS_6: u32 = 0x06; - #[doc = "7"] - pub const LOUIS_7: u32 = 0x07; - } - } - #[doc = "Level of Coherency for the cache hierarchy"] - pub mod LOC { - pub const offset: u32 = 24; - pub const mask: u32 = 0x07 << offset; - pub mod R {} - pub mod W {} - pub mod RW { - #[doc = "0"] - pub const LOC_0: u32 = 0; - #[doc = "1"] - pub const LOC_1: u32 = 0x01; - #[doc = "2"] - pub const LOC_2: u32 = 0x02; - #[doc = "3"] - pub const LOC_3: u32 = 0x03; - #[doc = "4"] - pub const LOC_4: u32 = 0x04; - #[doc = "5"] - pub const LOC_5: u32 = 0x05; - #[doc = "6"] - pub const LOC_6: u32 = 0x06; - #[doc = "7"] - pub const LOC_7: u32 = 0x07; - } - } - #[doc = "Level of Unification for the cache hierarchy"] - pub mod LOU { - pub const offset: u32 = 27; - pub const mask: u32 = 0x07 << offset; - pub mod R {} - pub mod W {} - pub mod RW { - #[doc = "0"] - pub const LOU_0: u32 = 0; - #[doc = "1"] - pub const LOU_1: u32 = 0x01; - #[doc = "2"] - pub const LOU_2: u32 = 0x02; - #[doc = "3"] - pub const LOU_3: u32 = 0x03; - #[doc = "4"] - pub const LOU_4: u32 = 0x04; - #[doc = "5"] - pub const LOU_5: u32 = 0x05; - #[doc = "6"] - pub const LOU_6: u32 = 0x06; - #[doc = "7"] - pub const LOU_7: u32 = 0x07; - } - } -} -#[doc = "Cache Type register"] -pub mod CTR { - #[doc = "Log2 of the number of words in the smallest cache line of all the instruction caches that are controlled by the processor."] - pub mod IMINLINE { - pub const offset: u32 = 0; - pub const mask: u32 = 0x0f << offset; - pub mod R {} - pub mod W {} - pub mod RW {} - } - #[doc = "Log2 of the number of words in the smallest cache line of all the data caches and unified caches that are controlled by the processor."] - pub mod DMINLINE { - pub const offset: u32 = 16; - pub const mask: u32 = 0x0f << offset; - pub mod R {} - pub mod W {} - pub mod RW {} - } - #[doc = "Exclusives Reservation Granule. The maximum size of the reservation granule that has been implemented for the Load-Exclusive and Store-Exclusive instructions, encoded as Log2 of the number of words."] - pub mod ERG { - pub const offset: u32 = 20; - pub const mask: u32 = 0x0f << offset; - pub mod R {} - pub mod W {} - pub mod RW {} - } - #[doc = "Cache Write-back Granule. The maximum size of memory that can be overwritten as a result of the eviction of a cache entry that has had a memory location in it modified, encoded as Log2 of the number of words."] - pub mod CWG { - pub const offset: u32 = 24; - pub const mask: u32 = 0x0f << offset; - pub mod R {} - pub mod W {} - pub mod RW {} - } - #[doc = "Indicates the implemented CTR format."] - pub mod FORMAT { - pub const offset: u32 = 29; - pub const mask: u32 = 0x07 << offset; - pub mod R {} - pub mod W {} - pub mod RW { - #[doc = "ARMv7 format."] - pub const FORMAT_4: u32 = 0x04; - } - } -} -#[doc = "Cache Size ID Register"] -pub mod CCSIDR { - #[doc = "(Log2(Number of words in cache line)) - 2."] - pub mod LINESIZE { - pub const offset: u32 = 0; - pub const mask: u32 = 0x07 << offset; - pub mod R {} - pub mod W {} - pub mod RW { - #[doc = "The line length of 4 words."] - pub const LINESIZE_0: u32 = 0; - #[doc = "The line length of 8 words."] - pub const LINESIZE_1: u32 = 0x01; - #[doc = "The line length of 16 words."] - pub const LINESIZE_2: u32 = 0x02; - #[doc = "The line length of 32 words."] - pub const LINESIZE_3: u32 = 0x03; - #[doc = "The line length of 64 words."] - pub const LINESIZE_4: u32 = 0x04; - #[doc = "The line length of 128 words."] - pub const LINESIZE_5: u32 = 0x05; - #[doc = "The line length of 256 words."] - pub const LINESIZE_6: u32 = 0x06; - #[doc = "The line length of 512 words."] - pub const LINESIZE_7: u32 = 0x07; - } - } - #[doc = "(Associativity of cache) - 1, therefore a value of 0 indicates an associativity of 1. The associativity does not have to be a power of 2."] - pub mod ASSOCIATIVITY { - pub const offset: u32 = 3; - pub const mask: u32 = 0x03ff << offset; - pub mod R {} - pub mod W {} - pub mod RW {} - } - #[doc = "(Number of sets in cache) - 1, therefore a value of 0 indicates 1 set in the cache. The number of sets does not have to be a power of 2."] - pub mod NUMSETS { - pub const offset: u32 = 13; - pub const mask: u32 = 0x7fff << offset; - pub mod R {} - pub mod W {} - pub mod RW {} - } - #[doc = "Indicates whether the cache level supports write-allocation"] - pub mod WA { - pub const offset: u32 = 28; - pub const mask: u32 = 0x01 << offset; - pub mod R {} - pub mod W {} - pub mod RW { - #[doc = "Feature not supported"] - pub const WA_0: u32 = 0; - #[doc = "Feature supported"] - pub const WA_1: u32 = 0x01; - } - } - #[doc = "Indicates whether the cache level supports read-allocation"] - pub mod RA { - pub const offset: u32 = 29; - pub const mask: u32 = 0x01 << offset; - pub mod R {} - pub mod W {} - pub mod RW { - #[doc = "Feature not supported"] - pub const RA_0: u32 = 0; - #[doc = "Feature supported"] - pub const RA_1: u32 = 0x01; - } - } - #[doc = "Indicates whether the cache level supports write-back"] - pub mod WB { - pub const offset: u32 = 30; - pub const mask: u32 = 0x01 << offset; - pub mod R {} - pub mod W {} - pub mod RW { - #[doc = "Feature not supported"] - pub const WB_0: u32 = 0; - #[doc = "Feature supported"] - pub const WB_1: u32 = 0x01; - } - } - #[doc = "Indicates whether the cache level supports write-through"] - pub mod WT { - pub const offset: u32 = 31; - pub const mask: u32 = 0x01 << offset; - pub mod R {} - pub mod W {} - pub mod RW { - #[doc = "Feature not supported"] - pub const WT_0: u32 = 0; - #[doc = "Feature supported"] - pub const WT_1: u32 = 0x01; - } - } -} -#[doc = "Cache Size Selection Register"] -pub mod CSSELR { - #[doc = "Instruction not data bit"] - pub mod IND { - pub const offset: u32 = 0; - pub const mask: u32 = 0x01 << offset; - pub mod R {} - pub mod W {} - pub mod RW { - #[doc = "Data or unified cache."] - pub const IND_0: u32 = 0; - #[doc = "Instruction cache."] - pub const IND_1: u32 = 0x01; - } - } - #[doc = "Cache level of required cache"] - pub mod LEVEL { - pub const offset: u32 = 1; - pub const mask: u32 = 0x07 << offset; - pub mod R {} - pub mod W {} - pub mod RW { - #[doc = "Level 1 cache."] - pub const LEVEL_0: u32 = 0; - #[doc = "Level 2 cache."] - pub const LEVEL_1: u32 = 0x01; - #[doc = "Level 3 cache."] - pub const LEVEL_2: u32 = 0x02; - #[doc = "Level 4 cache."] - pub const LEVEL_3: u32 = 0x03; - #[doc = "Level 5 cache."] - pub const LEVEL_4: u32 = 0x04; - #[doc = "Level 6 cache."] - pub const LEVEL_5: u32 = 0x05; - #[doc = "Level 7 cache."] - pub const LEVEL_6: u32 = 0x06; - } - } -} -#[doc = "Coprocessor Access Control Register"] -pub mod CPACR { - #[doc = "Access privileges for coprocessor 0."] - pub mod CP0 { - pub const offset: u32 = 0; - pub const mask: u32 = 0x03 << offset; - pub mod R {} - pub mod W {} - pub mod RW { - #[doc = "Access denied. Any attempted access generates a NOCP UsageFault."] - pub const CP0_0: u32 = 0; - #[doc = "Privileged access only. An unprivileged access generates a NOCP UsageFault."] - pub const CP0_1: u32 = 0x01; - #[doc = "Full access."] - pub const CP0_3: u32 = 0x03; - } - } - #[doc = "Access privileges for coprocessor 1."] - pub mod CP1 { - pub const offset: u32 = 2; - pub const mask: u32 = 0x03 << offset; - pub mod R {} - pub mod W {} - pub mod RW { - #[doc = "Access denied. Any attempted access generates a NOCP UsageFault."] - pub const CP1_0: u32 = 0; - #[doc = "Privileged access only. An unprivileged access generates a NOCP UsageFault."] - pub const CP1_1: u32 = 0x01; - #[doc = "Full access."] - pub const CP1_3: u32 = 0x03; - } - } - #[doc = "Access privileges for coprocessor 2."] - pub mod CP2 { - pub const offset: u32 = 4; - pub const mask: u32 = 0x03 << offset; - pub mod R {} - pub mod W {} - pub mod RW { - #[doc = "Access denied. Any attempted access generates a NOCP UsageFault."] - pub const CP2_0: u32 = 0; - #[doc = "Privileged access only. An unprivileged access generates a NOCP UsageFault."] - pub const CP2_1: u32 = 0x01; - #[doc = "Full access."] - pub const CP2_3: u32 = 0x03; - } - } - #[doc = "Access privileges for coprocessor 3."] - pub mod CP3 { - pub const offset: u32 = 6; - pub const mask: u32 = 0x03 << offset; - pub mod R {} - pub mod W {} - pub mod RW { - #[doc = "Access denied. Any attempted access generates a NOCP UsageFault."] - pub const CP3_0: u32 = 0; - #[doc = "Privileged access only. An unprivileged access generates a NOCP UsageFault."] - pub const CP3_1: u32 = 0x01; - #[doc = "Full access."] - pub const CP3_3: u32 = 0x03; - } - } - #[doc = "Access privileges for coprocessor 4."] - pub mod CP4 { - pub const offset: u32 = 8; - pub const mask: u32 = 0x03 << offset; - pub mod R {} - pub mod W {} - pub mod RW { - #[doc = "Access denied. Any attempted access generates a NOCP UsageFault."] - pub const CP4_0: u32 = 0; - #[doc = "Privileged access only. An unprivileged access generates a NOCP UsageFault."] - pub const CP4_1: u32 = 0x01; - #[doc = "Full access."] - pub const CP4_3: u32 = 0x03; - } - } - #[doc = "Access privileges for coprocessor 5."] - pub mod CP5 { - pub const offset: u32 = 10; - pub const mask: u32 = 0x03 << offset; - pub mod R {} - pub mod W {} - pub mod RW { - #[doc = "Access denied. Any attempted access generates a NOCP UsageFault."] - pub const CP5_0: u32 = 0; - #[doc = "Privileged access only. An unprivileged access generates a NOCP UsageFault."] - pub const CP5_1: u32 = 0x01; - #[doc = "Full access."] - pub const CP5_3: u32 = 0x03; - } - } - #[doc = "Access privileges for coprocessor 6."] - pub mod CP6 { - pub const offset: u32 = 12; - pub const mask: u32 = 0x03 << offset; - pub mod R {} - pub mod W {} - pub mod RW { - #[doc = "Access denied. Any attempted access generates a NOCP UsageFault."] - pub const CP6_0: u32 = 0; - #[doc = "Privileged access only. An unprivileged access generates a NOCP UsageFault."] - pub const CP6_1: u32 = 0x01; - #[doc = "Full access."] - pub const CP6_3: u32 = 0x03; - } - } - #[doc = "Access privileges for coprocessor 7."] - pub mod CP7 { - pub const offset: u32 = 14; - pub const mask: u32 = 0x03 << offset; - pub mod R {} - pub mod W {} - pub mod RW { - #[doc = "Access denied. Any attempted access generates a NOCP UsageFault."] - pub const CP7_0: u32 = 0; - #[doc = "Privileged access only. An unprivileged access generates a NOCP UsageFault."] - pub const CP7_1: u32 = 0x01; - #[doc = "Full access."] - pub const CP7_3: u32 = 0x03; - } - } - #[doc = "Access privileges for coprocessor 10."] - pub mod CP10 { - pub const offset: u32 = 20; - pub const mask: u32 = 0x03 << offset; - pub mod R {} - pub mod W {} - pub mod RW { - #[doc = "Access denied. Any attempted access generates a NOCP UsageFault."] - pub const CP10_0: u32 = 0; - #[doc = "Privileged access only. An unprivileged access generates a NOCP UsageFault."] - pub const CP10_1: u32 = 0x01; - #[doc = "Full access."] - pub const CP10_3: u32 = 0x03; - } - } - #[doc = "Access privileges for coprocessor 11."] - pub mod CP11 { - pub const offset: u32 = 22; - pub const mask: u32 = 0x03 << offset; - pub mod R {} - pub mod W {} - pub mod RW { - #[doc = "Access denied. Any attempted access generates a NOCP UsageFault."] - pub const CP11_0: u32 = 0; - #[doc = "Privileged access only. An unprivileged access generates a NOCP UsageFault."] - pub const CP11_1: u32 = 0x01; - #[doc = "Full access."] - pub const CP11_3: u32 = 0x03; - } - } -} -#[doc = "Instruction cache invalidate all to Point of Unification (PoU)"] -pub mod STIR { - #[doc = "Indicates the interrupt to be triggered"] - pub mod INTID { - pub const offset: u32 = 0; - pub const mask: u32 = 0x01ff << offset; - pub mod R {} - pub mod W {} - pub mod RW {} - } -} -#[doc = "Instruction cache invalidate all to Point of Unification (PoU)"] -pub mod ICIALLU { - #[doc = "I-cache invalidate all to PoU"] - pub mod ICIALLU { - pub const offset: u32 = 0; - pub const mask: u32 = 0xffff_ffff << offset; - pub mod R {} - pub mod W {} - pub mod RW {} - } -} -#[doc = "Instruction cache invalidate by address to PoU"] -pub mod ICIMVAU { - #[doc = "I-cache invalidate by MVA to PoU"] - pub mod ICIMVAU { - pub const offset: u32 = 0; - pub const mask: u32 = 0xffff_ffff << offset; - pub mod R {} - pub mod W {} - pub mod RW {} - } -} -#[doc = "Data cache invalidate by address to Point of Coherency (PoC)"] -pub mod DCIMVAC { - #[doc = "D-cache invalidate by MVA to PoC"] - pub mod DCIMVAC { - pub const offset: u32 = 0; - pub const mask: u32 = 0xffff_ffff << offset; - pub mod R {} - pub mod W {} - pub mod RW {} - } -} -#[doc = "Data cache invalidate by set/way"] -pub mod DCISW { - #[doc = "D-cache invalidate by set-way"] - pub mod DCISW { - pub const offset: u32 = 0; - pub const mask: u32 = 0xffff_ffff << offset; - pub mod R {} - pub mod W {} - pub mod RW {} - } -} -#[doc = "Data cache by address to PoU"] -pub mod DCCMVAU { - #[doc = "D-cache clean by MVA to PoU"] - pub mod DCCMVAU { - pub const offset: u32 = 0; - pub const mask: u32 = 0xffff_ffff << offset; - pub mod R {} - pub mod W {} - pub mod RW {} - } -} -#[doc = "Data cache clean by address to PoC"] -pub mod DCCMVAC { - #[doc = "D-cache clean by MVA to PoC"] - pub mod DCCMVAC { - pub const offset: u32 = 0; - pub const mask: u32 = 0xffff_ffff << offset; - pub mod R {} - pub mod W {} - pub mod RW {} - } -} -#[doc = "Data cache clean by set/way"] -pub mod DCCSW { - #[doc = "D-cache clean by set-way"] - pub mod DCCSW { - pub const offset: u32 = 0; - pub const mask: u32 = 0xffff_ffff << offset; - pub mod R {} - pub mod W {} - pub mod RW {} - } -} -#[doc = "Data cache clean and invalidate by address to PoC"] -pub mod DCCIMVAC { - #[doc = "D-cache clean and invalidate by MVA to PoC"] - pub mod DCCIMVAC { - pub const offset: u32 = 0; - pub const mask: u32 = 0xffff_ffff << offset; - pub mod R {} - pub mod W {} - pub mod RW {} - } -} -#[doc = "Data cache clean and invalidate by set/way"] -pub mod DCCISW { - #[doc = "D-cache clean and invalidate by set-way"] - pub mod DCCISW { - pub const offset: u32 = 0; - pub const mask: u32 = 0xffff_ffff << offset; - pub mod R {} - pub mod W {} - pub mod RW {} - } -} -#[doc = "Instruction Tightly-Coupled Memory Control Register"] -pub mod CM7_ITCMCR { - #[doc = "TCM enable. When a TCM is disabled all accesses are made to the AXIM interface."] - pub mod EN { - pub const offset: u32 = 0; - pub const mask: u32 = 0x01 << offset; - pub mod R {} - pub mod W {} - pub mod RW { - #[doc = "TCM disabled."] - pub const EN_0: u32 = 0; - #[doc = "TCM enabled."] - pub const EN_1: u32 = 0x01; - } - } - #[doc = "Read-Modify-Write (RMW) enable. Indicates that all writes to TCM, that are not the full width of the TCM RAM, use a RMW sequence."] - pub mod RMW { - pub const offset: u32 = 1; - pub const mask: u32 = 0x01 << offset; - pub mod R {} - pub mod W {} - pub mod RW { - #[doc = "RMW disabled."] - pub const RMW_0: u32 = 0; - #[doc = "RMW enabled."] - pub const RMW_1: u32 = 0x01; - } - } - #[doc = "Retry phase enable. When enabled the processor guarantees to honor the retry output on the corresponding TCM interface, re-executing the instruction which carried out the TCM access."] - pub mod RETEN { - pub const offset: u32 = 2; - pub const mask: u32 = 0x01 << offset; - pub mod R {} - pub mod W {} - pub mod RW { - #[doc = "Retry phase disabled."] - pub const RETEN_0: u32 = 0; - #[doc = "Retry phase enabled."] - pub const RETEN_1: u32 = 0x01; - } - } - #[doc = "TCM size. Indicates the size of the relevant TCM."] - pub mod SZ { - pub const offset: u32 = 3; - pub const mask: u32 = 0x0f << offset; - pub mod R {} - pub mod W {} - pub mod RW { - #[doc = "No TCM implemented."] - pub const SZ_0: u32 = 0; - #[doc = "4KB."] - pub const SZ_3: u32 = 0x03; - #[doc = "8KB."] - pub const SZ_4: u32 = 0x04; - #[doc = "16KB."] - pub const SZ_5: u32 = 0x05; - #[doc = "32KB."] - pub const SZ_6: u32 = 0x06; - #[doc = "64KB."] - pub const SZ_7: u32 = 0x07; - #[doc = "128KB."] - pub const SZ_8: u32 = 0x08; - #[doc = "256KB."] - pub const SZ_9: u32 = 0x09; - #[doc = "512KB."] - pub const SZ_10: u32 = 0x0a; - #[doc = "1MB."] - pub const SZ_11: u32 = 0x0b; - #[doc = "2MB."] - pub const SZ_12: u32 = 0x0c; - #[doc = "4MB."] - pub const SZ_13: u32 = 0x0d; - #[doc = "8MB."] - pub const SZ_14: u32 = 0x0e; - #[doc = "16MB."] - pub const SZ_15: u32 = 0x0f; - } - } -} -#[doc = "Data Tightly-Coupled Memory Control Register"] -pub mod CM7_DTCMCR { - #[doc = "TCM enable. When a TCM is disabled all accesses are made to the AXIM interface."] - pub mod EN { - pub const offset: u32 = 0; - pub const mask: u32 = 0x01 << offset; - pub mod R {} - pub mod W {} - pub mod RW { - #[doc = "TCM disabled."] - pub const EN_0: u32 = 0; - #[doc = "TCM enabled."] - pub const EN_1: u32 = 0x01; - } - } - #[doc = "Read-Modify-Write (RMW) enable. Indicates that all writes to TCM, that are not the full width of the TCM RAM, use a RMW sequence."] - pub mod RMW { - pub const offset: u32 = 1; - pub const mask: u32 = 0x01 << offset; - pub mod R {} - pub mod W {} - pub mod RW { - #[doc = "RMW disabled."] - pub const RMW_0: u32 = 0; - #[doc = "RMW enabled."] - pub const RMW_1: u32 = 0x01; - } - } - #[doc = "Retry phase enable. When enabled the processor guarantees to honor the retry output on the corresponding TCM interface, re-executing the instruction which carried out the TCM access."] - pub mod RETEN { - pub const offset: u32 = 2; - pub const mask: u32 = 0x01 << offset; - pub mod R {} - pub mod W {} - pub mod RW { - #[doc = "Retry phase disabled."] - pub const RETEN_0: u32 = 0; - #[doc = "Retry phase enabled."] - pub const RETEN_1: u32 = 0x01; - } - } - #[doc = "TCM size. Indicates the size of the relevant TCM."] - pub mod SZ { - pub const offset: u32 = 3; - pub const mask: u32 = 0x0f << offset; - pub mod R {} - pub mod W {} - pub mod RW { - #[doc = "No TCM implemented."] - pub const SZ_0: u32 = 0; - #[doc = "4KB."] - pub const SZ_3: u32 = 0x03; - #[doc = "8KB."] - pub const SZ_4: u32 = 0x04; - #[doc = "16KB."] - pub const SZ_5: u32 = 0x05; - #[doc = "32KB."] - pub const SZ_6: u32 = 0x06; - #[doc = "64KB."] - pub const SZ_7: u32 = 0x07; - #[doc = "128KB."] - pub const SZ_8: u32 = 0x08; - #[doc = "256KB."] - pub const SZ_9: u32 = 0x09; - #[doc = "512KB."] - pub const SZ_10: u32 = 0x0a; - #[doc = "1MB."] - pub const SZ_11: u32 = 0x0b; - #[doc = "2MB."] - pub const SZ_12: u32 = 0x0c; - #[doc = "4MB."] - pub const SZ_13: u32 = 0x0d; - #[doc = "8MB."] - pub const SZ_14: u32 = 0x0e; - #[doc = "16MB."] - pub const SZ_15: u32 = 0x0f; - } - } -} -#[doc = "AHBP Control Register"] -pub mod CM7_AHBPCR { - #[doc = "AHBP enable."] - pub mod EN { - pub const offset: u32 = 0; - pub const mask: u32 = 0x01 << offset; - pub mod R {} - pub mod W {} - pub mod RW { - #[doc = "AHBP disabled. When disabled all accesses are made to the AXIM interface."] - pub const EN_0: u32 = 0; - #[doc = "AHBP enabled."] - pub const EN_1: u32 = 0x01; - } - } - #[doc = "AHBP size."] - pub mod SZ { - pub const offset: u32 = 1; - pub const mask: u32 = 0x07 << offset; - pub mod R {} - pub mod W {} - pub mod RW { - #[doc = "0MB. AHBP disabled."] - pub const SZ_0: u32 = 0; - #[doc = "64MB."] - pub const SZ_1: u32 = 0x01; - #[doc = "128MB."] - pub const SZ_2: u32 = 0x02; - #[doc = "256MB."] - pub const SZ_3: u32 = 0x03; - #[doc = "512MB."] - pub const SZ_4: u32 = 0x04; - } - } -} -#[doc = "L1 Cache Control Register"] -pub mod CM7_CACR { - #[doc = "Shared cacheable-is-WT for data cache. Enables limited cache coherency usage."] - pub mod SIWT { - pub const offset: u32 = 0; - pub const mask: u32 = 0x01 << offset; - pub mod R {} - pub mod W {} - pub mod RW { - #[doc = "Normal Cacheable Shared locations are treated as being Non-cacheable. Default mode of operation for Shared memory."] - pub const SIWT_0: u32 = 0; - #[doc = "Normal Cacheable shared locations are treated as Write-Through."] - pub const SIWT_1: u32 = 0x01; - } - } - #[doc = "Enables ECC in the instruction and data cache."] - pub mod ECCDIS { - pub const offset: u32 = 1; - pub const mask: u32 = 0x01 << offset; - pub mod R {} - pub mod W {} - pub mod RW { - #[doc = "Enables ECC in the instruction and data cache."] - pub const ECCDIS_0: u32 = 0; - #[doc = "Disables ECC in the instruction and data cache."] - pub const ECCDIS_1: u32 = 0x01; - } - } - #[doc = "Enables Force Write-Through in the data cache."] - pub mod FORCEWT { - pub const offset: u32 = 2; - pub const mask: u32 = 0x01 << offset; - pub mod R {} - pub mod W {} - pub mod RW { - #[doc = "Disables Force Write-Through."] - pub const FORCEWT_0: u32 = 0; - #[doc = "Enables Force Write-Through. All Cacheable memory regions are treated as Write-Through."] - pub const FORCEWT_1: u32 = 0x01; - } - } -} -#[doc = "AHB Slave Control Register"] -pub mod CM7_AHBSCR { - #[doc = "AHBS prioritization control."] - pub mod CTL { - pub const offset: u32 = 0; - pub const mask: u32 = 0x03 << offset; - pub mod R {} - pub mod W {} - pub mod RW { - #[doc = "AHBS access priority demoted. This is the reset value."] - pub const CTL_0: u32 = 0; - #[doc = "Software access priority demoted."] - pub const CTL_1: u32 = 0x01; - #[doc = "AHBS access priority demoted by initializing the fairness counter to the CM7_AHBSCR\\[INITCOUNT\\] value when the software execution priority is higher than or equal to the threshold level programed in CM7_AHBSCR\\[TPRI\\]."] - pub const CTL_2: u32 = 0x02; - #[doc = "AHBSPRI signal has control of access priority."] - pub const CTL_3: u32 = 0x03; - } - } - #[doc = "Threshold execution priority for AHBS traffic demotion."] - pub mod TPRI { - pub const offset: u32 = 2; - pub const mask: u32 = 0x01ff << offset; - pub mod R {} - pub mod W {} - pub mod RW {} - } - #[doc = "Fairness counter initialization value."] - pub mod INITCOUNT { - pub const offset: u32 = 11; - pub const mask: u32 = 0x1f << offset; - pub mod R {} - pub mod W {} - pub mod RW {} - } -} -#[doc = "Auxiliary Bus Fault Status Register"] -pub mod CM7_ABFSR { - #[doc = "Asynchronous fault on ITCM interface."] - pub mod ITCM { - pub const offset: u32 = 0; - pub const mask: u32 = 0x01 << offset; - pub mod R {} - pub mod W {} - pub mod RW {} - } - #[doc = "Asynchronous fault on DTCM interface."] - pub mod DTCM { - pub const offset: u32 = 1; - pub const mask: u32 = 0x01 << offset; - pub mod R {} - pub mod W {} - pub mod RW {} - } - #[doc = "Asynchronous fault on AHBP interface."] - pub mod AHBP { - pub const offset: u32 = 2; - pub const mask: u32 = 0x01 << offset; - pub mod R {} - pub mod W {} - pub mod RW {} - } - #[doc = "Asynchronous fault on AXIM interface."] - pub mod AXIM { - pub const offset: u32 = 3; - pub const mask: u32 = 0x01 << offset; - pub mod R {} - pub mod W {} - pub mod RW {} - } - #[doc = "Asynchronous fault on EPPB interface."] - pub mod EPPB { - pub const offset: u32 = 4; - pub const mask: u32 = 0x01 << offset; - pub mod R {} - pub mod W {} - pub mod RW {} - } - #[doc = "Indicates the type of fault on the AXIM interface. Only valid when AXIM is 1."] - pub mod AXIMTYPE { - pub const offset: u32 = 8; - pub const mask: u32 = 0x03 << offset; - pub mod R {} - pub mod W {} - pub mod RW { - #[doc = "OKAY."] - pub const AXIMTYPE_0: u32 = 0; - #[doc = "EXOKAY."] - pub const AXIMTYPE_1: u32 = 0x01; - #[doc = "SLVERR."] - pub const AXIMTYPE_2: u32 = 0x02; - #[doc = "DECERR."] - pub const AXIMTYPE_3: u32 = 0x03; - } - } -} diff --git a/src/imxrt1176_cm4.rs b/src/imxrt1176_cm4.rs index 0e6fb868fd4e..0766d973e42e 100644 --- a/src/imxrt1176_cm4.rs +++ b/src/imxrt1176_cm4.rs @@ -34,10 +34,6 @@ pub enum Interrupt { DMA15_DMA31 = 15, #[doc = "16 - DMA_ERROR"] DMA_ERROR = 16, - #[doc = "17 - RESERVED33"] - RESERVED33 = 17, - #[doc = "18 - RESERVED34"] - RESERVED34 = 18, #[doc = "19 - CORE"] CORE = 19, #[doc = "20 - LPUART1"] @@ -100,12 +96,8 @@ pub enum Interrupt { CAN3 = 48, #[doc = "49 - CAN3_ERROR"] CAN3_ERROR = 49, - #[doc = "50 - RESERVED66"] - RESERVED66 = 50, #[doc = "51 - KPP"] KPP = 51, - #[doc = "52 - RESERVED68"] - RESERVED68 = 52, #[doc = "53 - GPR_IRQ"] GPR_IRQ = 53, #[doc = "54 - ELCDIF"] @@ -120,8 +112,6 @@ pub enum Interrupt { MIPI_CSI = 58, #[doc = "59 - MIPI_DSI"] MIPI_DSI = 59, - #[doc = "60 - GPU2D"] - GPU2D = 60, #[doc = "61 - GPIO12_COMBINED_0_15"] GPIO12_COMBINED_0_15 = 61, #[doc = "62 - GPIO12_COMBINED_16_31"] @@ -310,14 +300,6 @@ pub enum Interrupt { ACMP3 = 159, #[doc = "160 - ACMP4"] ACMP4 = 160, - #[doc = "161 - RESERVED177"] - RESERVED177 = 161, - #[doc = "162 - RESERVED178"] - RESERVED178 = 162, - #[doc = "163 - RESERVED179"] - RESERVED179 = 163, - #[doc = "164 - RESERVED180"] - RESERVED180 = 164, #[doc = "165 - ENC1"] ENC1 = 165, #[doc = "166 - ENC2"] @@ -326,10 +308,6 @@ pub enum Interrupt { ENC3 = 167, #[doc = "168 - ENC4"] ENC4 = 168, - #[doc = "169 - RESERVED185"] - RESERVED185 = 169, - #[doc = "170 - RESERVED186"] - RESERVED186 = 170, #[doc = "171 - TMR1"] TMR1 = 171, #[doc = "172 - TMR2"] @@ -372,22 +350,6 @@ pub enum Interrupt { PWM4_3 = 190, #[doc = "191 - PWM4_FAULT"] PWM4_FAULT = 191, - #[doc = "192 - RESERVED208"] - RESERVED208 = 192, - #[doc = "193 - RESERVED209"] - RESERVED209 = 193, - #[doc = "194 - RESERVED210"] - RESERVED210 = 194, - #[doc = "195 - RESERVED211"] - RESERVED211 = 195, - #[doc = "196 - RESERVED212"] - RESERVED212 = 196, - #[doc = "197 - RESERVED213"] - RESERVED213 = 197, - #[doc = "198 - RESERVED214"] - RESERVED214 = 198, - #[doc = "199 - RESERVED215"] - RESERVED215 = 199, #[doc = "200 - PDM_HWVAD_EVENT"] PDM_HWVAD_EVENT = 200, #[doc = "201 - PDM_HWVAD_ERROR"] @@ -452,8 +414,6 @@ mod _vectors { fn DMA14_DMA30(); fn DMA15_DMA31(); fn DMA_ERROR(); - fn RESERVED33(); - fn RESERVED34(); fn CORE(); fn LPUART1(); fn LPUART2(); @@ -485,9 +445,7 @@ mod _vectors { fn CAN2_ERROR(); fn CAN3(); fn CAN3_ERROR(); - fn RESERVED66(); fn KPP(); - fn RESERVED68(); fn GPR_IRQ(); fn ELCDIF(); fn LCDIFV2(); @@ -495,7 +453,6 @@ mod _vectors { fn PXP(); fn MIPI_CSI(); fn MIPI_DSI(); - fn GPU2D(); fn GPIO12_COMBINED_0_15(); fn GPIO12_COMBINED_16_31(); fn DAC(); @@ -590,16 +547,10 @@ mod _vectors { fn ACMP2(); fn ACMP3(); fn ACMP4(); - fn RESERVED177(); - fn RESERVED178(); - fn RESERVED179(); - fn RESERVED180(); fn ENC1(); fn ENC2(); fn ENC3(); fn ENC4(); - fn RESERVED185(); - fn RESERVED186(); fn TMR1(); fn TMR2(); fn TMR3(); @@ -621,14 +572,6 @@ mod _vectors { fn PWM4_2(); fn PWM4_3(); fn PWM4_FAULT(); - fn RESERVED208(); - fn RESERVED209(); - fn RESERVED210(); - fn RESERVED211(); - fn RESERVED212(); - fn RESERVED213(); - fn RESERVED214(); - fn RESERVED215(); fn PDM_HWVAD_EVENT(); fn PDM_HWVAD_ERROR(); fn PDM_EVENT(); @@ -706,12 +649,8 @@ mod _vectors { Vector { _handler: DMA_ERROR, }, - Vector { - _handler: RESERVED33, - }, - Vector { - _handler: RESERVED34, - }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, Vector { _handler: CORE }, Vector { _handler: LPUART1 }, Vector { _handler: LPUART2 }, @@ -749,13 +688,9 @@ mod _vectors { Vector { _handler: CAN3_ERROR, }, - Vector { - _handler: RESERVED66, - }, + Vector { _reserved: 0 }, Vector { _handler: KPP }, - Vector { - _handler: RESERVED68, - }, + Vector { _reserved: 0 }, Vector { _handler: GPR_IRQ }, Vector { _handler: ELCDIF }, Vector { _handler: LCDIFV2 }, @@ -763,7 +698,7 @@ mod _vectors { Vector { _handler: PXP }, Vector { _handler: MIPI_CSI }, Vector { _handler: MIPI_DSI }, - Vector { _handler: GPU2D }, + Vector { _reserved: 0 }, Vector { _handler: GPIO12_COMBINED_0_15, }, @@ -952,28 +887,16 @@ mod _vectors { Vector { _handler: ACMP2 }, Vector { _handler: ACMP3 }, Vector { _handler: ACMP4 }, - Vector { - _handler: RESERVED177, - }, - Vector { - _handler: RESERVED178, - }, - Vector { - _handler: RESERVED179, - }, - Vector { - _handler: RESERVED180, - }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, Vector { _handler: ENC1 }, Vector { _handler: ENC2 }, Vector { _handler: ENC3 }, Vector { _handler: ENC4 }, - Vector { - _handler: RESERVED185, - }, - Vector { - _handler: RESERVED186, - }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, Vector { _handler: TMR1 }, Vector { _handler: TMR2 }, Vector { _handler: TMR3 }, @@ -1005,30 +928,14 @@ mod _vectors { Vector { _handler: PWM4_FAULT, }, - Vector { - _handler: RESERVED208, - }, - Vector { - _handler: RESERVED209, - }, - Vector { - _handler: RESERVED210, - }, - Vector { - _handler: RESERVED211, - }, - Vector { - _handler: RESERVED212, - }, - Vector { - _handler: RESERVED213, - }, - Vector { - _handler: RESERVED214, - }, - Vector { - _handler: RESERVED215, - }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, Vector { _handler: PDM_HWVAD_EVENT, }, @@ -3803,33 +3710,6 @@ pub mod mub { } } #[path = "."] -pub mod nvic { - #[doc = "Nested Vectored Interrupt Controller"] - pub const NVIC: *const RegisterBlock = 0xe000_e100 as *const RegisterBlock; - #[path = "blocks/imxrt1176_cm4/nvic.rs"] - mod blocks; - pub use blocks::*; - pub type Instance = crate::Instance; - pub type NVIC = Instance<{ crate::SOLE_INSTANCE }>; - impl crate::private::Sealed for NVIC {} - impl crate::Valid for NVIC {} - impl NVIC { - #[doc = r" Acquire a vaild, but possibly aliased, instance."] - #[doc = r""] - #[doc = r" # Safety"] - #[doc = r""] - #[doc = r" See [the struct-level safety documentation](crate::Instance)."] - #[inline] - pub const unsafe fn instance() -> Self { - Instance::new(NVIC) - } - } - #[doc = r" Returns the instance number `N` for a peripheral instance."] - pub fn number(rb: *const RegisterBlock) -> Option { - core::ptr::eq(rb, NVIC).then_some(0) - } -} -#[path = "."] pub mod ocotp { #[doc = "no description available"] pub const OCOTP: *const RegisterBlock = 0x40ca_c000 as *const RegisterBlock; @@ -5595,7 +5475,6 @@ pub struct Instances { pub MIPI_CSI2RX: mipi_csi2rx::MIPI_CSI2RX, pub MMCAU: mmcau::MMCAU, pub MUB: mub::MUB, - pub NVIC: nvic::NVIC, pub OCOTP: ocotp::OCOTP, pub OSC_RC_400M: osc_rc_400m::OSC_RC_400M, pub OTFAD1: otfad::OTFAD1, @@ -5800,7 +5679,6 @@ impl Instances { MIPI_CSI2RX: mipi_csi2rx::MIPI_CSI2RX::instance(), MMCAU: mmcau::MMCAU::instance(), MUB: mub::MUB::instance(), - NVIC: nvic::NVIC::instance(), OCOTP: ocotp::OCOTP::instance(), OSC_RC_400M: osc_rc_400m::OSC_RC_400M::instance(), OTFAD1: otfad::OTFAD1::instance(), diff --git a/src/imxrt1176_cm4.x b/src/imxrt1176_cm4.x index ed7a76bf7218..bb1f16c68753 100644 --- a/src/imxrt1176_cm4.x +++ b/src/imxrt1176_cm4.x @@ -15,8 +15,6 @@ PROVIDE(DMA13_DMA29 = DefaultHandler); PROVIDE(DMA14_DMA30 = DefaultHandler); PROVIDE(DMA15_DMA31 = DefaultHandler); PROVIDE(DMA_ERROR = DefaultHandler); -PROVIDE(RESERVED33 = DefaultHandler); -PROVIDE(RESERVED34 = DefaultHandler); PROVIDE(CORE = DefaultHandler); PROVIDE(LPUART1 = DefaultHandler); PROVIDE(LPUART2 = DefaultHandler); @@ -48,9 +46,7 @@ PROVIDE(CAN2 = DefaultHandler); PROVIDE(CAN2_ERROR = DefaultHandler); PROVIDE(CAN3 = DefaultHandler); PROVIDE(CAN3_ERROR = DefaultHandler); -PROVIDE(RESERVED66 = DefaultHandler); PROVIDE(KPP = DefaultHandler); -PROVIDE(RESERVED68 = DefaultHandler); PROVIDE(GPR_IRQ = DefaultHandler); PROVIDE(ELCDIF = DefaultHandler); PROVIDE(LCDIFV2 = DefaultHandler); @@ -58,7 +54,6 @@ PROVIDE(CSI = DefaultHandler); PROVIDE(PXP = DefaultHandler); PROVIDE(MIPI_CSI = DefaultHandler); PROVIDE(MIPI_DSI = DefaultHandler); -PROVIDE(GPU2D = DefaultHandler); PROVIDE(GPIO12_COMBINED_0_15 = DefaultHandler); PROVIDE(GPIO12_COMBINED_16_31 = DefaultHandler); PROVIDE(DAC = DefaultHandler); @@ -153,16 +148,10 @@ PROVIDE(ACMP1 = DefaultHandler); PROVIDE(ACMP2 = DefaultHandler); PROVIDE(ACMP3 = DefaultHandler); PROVIDE(ACMP4 = DefaultHandler); -PROVIDE(RESERVED177 = DefaultHandler); -PROVIDE(RESERVED178 = DefaultHandler); -PROVIDE(RESERVED179 = DefaultHandler); -PROVIDE(RESERVED180 = DefaultHandler); PROVIDE(ENC1 = DefaultHandler); PROVIDE(ENC2 = DefaultHandler); PROVIDE(ENC3 = DefaultHandler); PROVIDE(ENC4 = DefaultHandler); -PROVIDE(RESERVED185 = DefaultHandler); -PROVIDE(RESERVED186 = DefaultHandler); PROVIDE(TMR1 = DefaultHandler); PROVIDE(TMR2 = DefaultHandler); PROVIDE(TMR3 = DefaultHandler); @@ -184,14 +173,6 @@ PROVIDE(PWM4_1 = DefaultHandler); PROVIDE(PWM4_2 = DefaultHandler); PROVIDE(PWM4_3 = DefaultHandler); PROVIDE(PWM4_FAULT = DefaultHandler); -PROVIDE(RESERVED208 = DefaultHandler); -PROVIDE(RESERVED209 = DefaultHandler); -PROVIDE(RESERVED210 = DefaultHandler); -PROVIDE(RESERVED211 = DefaultHandler); -PROVIDE(RESERVED212 = DefaultHandler); -PROVIDE(RESERVED213 = DefaultHandler); -PROVIDE(RESERVED214 = DefaultHandler); -PROVIDE(RESERVED215 = DefaultHandler); PROVIDE(PDM_HWVAD_EVENT = DefaultHandler); PROVIDE(PDM_HWVAD_ERROR = DefaultHandler); PROVIDE(PDM_EVENT = DefaultHandler); diff --git a/src/imxrt1176_cm7.rs b/src/imxrt1176_cm7.rs index 11889bb5bcff..aff644255ce2 100644 --- a/src/imxrt1176_cm7.rs +++ b/src/imxrt1176_cm7.rs @@ -104,8 +104,6 @@ pub enum Interrupt { FLEXRAM = 50, #[doc = "51 - KPP"] KPP = 51, - #[doc = "52 - RESERVED68"] - RESERVED68 = 52, #[doc = "53 - GPR_IRQ"] GPR_IRQ = 53, #[doc = "54 - ELCDIF"] @@ -120,8 +118,6 @@ pub enum Interrupt { MIPI_CSI = 58, #[doc = "59 - MIPI_DSI"] MIPI_DSI = 59, - #[doc = "60 - GPU2D"] - GPU2D = 60, #[doc = "61 - GPIO6_COMBINED_0_15"] GPIO6_COMBINED_0_15 = 61, #[doc = "62 - GPIO6_COMBINED_16_31"] @@ -310,14 +306,6 @@ pub enum Interrupt { ACMP3 = 159, #[doc = "160 - ACMP4"] ACMP4 = 160, - #[doc = "161 - RESERVED177"] - RESERVED177 = 161, - #[doc = "162 - RESERVED178"] - RESERVED178 = 162, - #[doc = "163 - RESERVED179"] - RESERVED179 = 163, - #[doc = "164 - RESERVED180"] - RESERVED180 = 164, #[doc = "165 - ENC1"] ENC1 = 165, #[doc = "166 - ENC2"] @@ -326,10 +314,6 @@ pub enum Interrupt { ENC3 = 167, #[doc = "168 - ENC4"] ENC4 = 168, - #[doc = "169 - RESERVED185"] - RESERVED185 = 169, - #[doc = "170 - RESERVED186"] - RESERVED186 = 170, #[doc = "171 - TMR1"] TMR1 = 171, #[doc = "172 - TMR2"] @@ -372,22 +356,6 @@ pub enum Interrupt { PWM4_3 = 190, #[doc = "191 - PWM4_FAULT"] PWM4_FAULT = 191, - #[doc = "192 - RESERVED208"] - RESERVED208 = 192, - #[doc = "193 - RESERVED209"] - RESERVED209 = 193, - #[doc = "194 - RESERVED210"] - RESERVED210 = 194, - #[doc = "195 - RESERVED211"] - RESERVED211 = 195, - #[doc = "196 - RESERVED212"] - RESERVED212 = 196, - #[doc = "197 - RESERVED213"] - RESERVED213 = 197, - #[doc = "198 - RESERVED214"] - RESERVED214 = 198, - #[doc = "199 - RESERVED215"] - RESERVED215 = 199, #[doc = "200 - PDM_HWVAD_EVENT"] PDM_HWVAD_EVENT = 200, #[doc = "201 - PDM_HWVAD_ERROR"] @@ -487,7 +455,6 @@ mod _vectors { fn CAN3_ERROR(); fn FLEXRAM(); fn KPP(); - fn RESERVED68(); fn GPR_IRQ(); fn ELCDIF(); fn LCDIFV2(); @@ -495,7 +462,6 @@ mod _vectors { fn PXP(); fn MIPI_CSI(); fn MIPI_DSI(); - fn GPU2D(); fn GPIO6_COMBINED_0_15(); fn GPIO6_COMBINED_16_31(); fn DAC(); @@ -590,16 +556,10 @@ mod _vectors { fn ACMP2(); fn ACMP3(); fn ACMP4(); - fn RESERVED177(); - fn RESERVED178(); - fn RESERVED179(); - fn RESERVED180(); fn ENC1(); fn ENC2(); fn ENC3(); fn ENC4(); - fn RESERVED185(); - fn RESERVED186(); fn TMR1(); fn TMR2(); fn TMR3(); @@ -621,14 +581,6 @@ mod _vectors { fn PWM4_2(); fn PWM4_3(); fn PWM4_FAULT(); - fn RESERVED208(); - fn RESERVED209(); - fn RESERVED210(); - fn RESERVED211(); - fn RESERVED212(); - fn RESERVED213(); - fn RESERVED214(); - fn RESERVED215(); fn PDM_HWVAD_EVENT(); fn PDM_HWVAD_ERROR(); fn PDM_EVENT(); @@ -751,9 +703,7 @@ mod _vectors { }, Vector { _handler: FLEXRAM }, Vector { _handler: KPP }, - Vector { - _handler: RESERVED68, - }, + Vector { _reserved: 0 }, Vector { _handler: GPR_IRQ }, Vector { _handler: ELCDIF }, Vector { _handler: LCDIFV2 }, @@ -761,7 +711,7 @@ mod _vectors { Vector { _handler: PXP }, Vector { _handler: MIPI_CSI }, Vector { _handler: MIPI_DSI }, - Vector { _handler: GPU2D }, + Vector { _reserved: 0 }, Vector { _handler: GPIO6_COMBINED_0_15, }, @@ -950,28 +900,16 @@ mod _vectors { Vector { _handler: ACMP2 }, Vector { _handler: ACMP3 }, Vector { _handler: ACMP4 }, - Vector { - _handler: RESERVED177, - }, - Vector { - _handler: RESERVED178, - }, - Vector { - _handler: RESERVED179, - }, - Vector { - _handler: RESERVED180, - }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, Vector { _handler: ENC1 }, Vector { _handler: ENC2 }, Vector { _handler: ENC3 }, Vector { _handler: ENC4 }, - Vector { - _handler: RESERVED185, - }, - Vector { - _handler: RESERVED186, - }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, Vector { _handler: TMR1 }, Vector { _handler: TMR2 }, Vector { _handler: TMR3 }, @@ -1003,30 +941,14 @@ mod _vectors { Vector { _handler: PWM4_FAULT, }, - Vector { - _handler: RESERVED208, - }, - Vector { - _handler: RESERVED209, - }, - Vector { - _handler: RESERVED210, - }, - Vector { - _handler: RESERVED211, - }, - Vector { - _handler: RESERVED212, - }, - Vector { - _handler: RESERVED213, - }, - Vector { - _handler: RESERVED214, - }, - Vector { - _handler: RESERVED215, - }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, Vector { _handler: PDM_HWVAD_EVENT, }, @@ -3781,33 +3703,6 @@ pub mod mua { } } #[path = "."] -pub mod nvic { - #[doc = "Nested Vectored Interrupt Controller"] - pub const NVIC: *const RegisterBlock = 0xe000_e100 as *const RegisterBlock; - #[path = "blocks/imxrt1176_cm4/nvic.rs"] - mod blocks; - pub use blocks::*; - pub type Instance = crate::Instance; - pub type NVIC = Instance<{ crate::SOLE_INSTANCE }>; - impl crate::private::Sealed for NVIC {} - impl crate::Valid for NVIC {} - impl NVIC { - #[doc = r" Acquire a vaild, but possibly aliased, instance."] - #[doc = r""] - #[doc = r" # Safety"] - #[doc = r""] - #[doc = r" See [the struct-level safety documentation](crate::Instance)."] - #[inline] - pub const unsafe fn instance() -> Self { - Instance::new(NVIC) - } - } - #[doc = r" Returns the instance number `N` for a peripheral instance."] - pub fn number(rb: *const RegisterBlock) -> Option { - core::ptr::eq(rb, NVIC).then_some(0) - } -} -#[path = "."] pub mod ocotp { #[doc = "no description available"] pub const OCOTP: *const RegisterBlock = 0x40ca_c000 as *const RegisterBlock; @@ -4833,33 +4728,6 @@ pub mod ssarc_lp { } } #[path = "."] -pub mod system_control { - #[doc = "System Control Block"] - pub const SYSTEMCONTROL: *const RegisterBlock = 0xe000_e000 as *const RegisterBlock; - #[path = "blocks/imxrt1176_cm7/system_control.rs"] - mod blocks; - pub use blocks::*; - pub type Instance = crate::Instance; - pub type SYSTEMCONTROL = Instance<{ crate::SOLE_INSTANCE }>; - impl crate::private::Sealed for SYSTEMCONTROL {} - impl crate::Valid for SYSTEMCONTROL {} - impl SYSTEMCONTROL { - #[doc = r" Acquire a vaild, but possibly aliased, instance."] - #[doc = r""] - #[doc = r" # Safety"] - #[doc = r""] - #[doc = r" See [the struct-level safety documentation](crate::Instance)."] - #[inline] - pub const unsafe fn instance() -> Self { - Instance::new(SYSTEMCONTROL) - } - } - #[doc = r" Returns the instance number `N` for a peripheral instance."] - pub fn number(rb: *const RegisterBlock) -> Option { - core::ptr::eq(rb, SYSTEMCONTROL).then_some(0) - } -} -#[path = "."] pub mod tmpsns { #[doc = "Temperature Sensor Memory Map"] pub const TMPSNS: *const RegisterBlock = 0 as *const RegisterBlock; @@ -5600,7 +5468,6 @@ pub struct Instances { pub MECC2: mecc::MECC2, pub MIPI_CSI2RX: mipi_csi2rx::MIPI_CSI2RX, pub MUA: mua::MUA, - pub NVIC: nvic::NVIC, pub OCOTP: ocotp::OCOTP, pub OSC_RC_400M: osc_rc_400m::OSC_RC_400M, pub OTFAD1: otfad::OTFAD1, @@ -5646,7 +5513,6 @@ pub struct Instances { pub SRC: src::SRC, pub SSARC_HP: ssarc_hp::SSARC_HP, pub SSARC_LP: ssarc_lp::SSARC_LP, - pub SYSTEMCONTROL: system_control::SYSTEMCONTROL, pub TMPSNS: tmpsns::TMPSNS, pub TMR1: tmr::TMR1, pub TMR2: tmr::TMR2, @@ -5806,7 +5672,6 @@ impl Instances { MECC2: mecc::MECC2::instance(), MIPI_CSI2RX: mipi_csi2rx::MIPI_CSI2RX::instance(), MUA: mua::MUA::instance(), - NVIC: nvic::NVIC::instance(), OCOTP: ocotp::OCOTP::instance(), OSC_RC_400M: osc_rc_400m::OSC_RC_400M::instance(), OTFAD1: otfad::OTFAD1::instance(), @@ -5852,7 +5717,6 @@ impl Instances { SRC: src::SRC::instance(), SSARC_HP: ssarc_hp::SSARC_HP::instance(), SSARC_LP: ssarc_lp::SSARC_LP::instance(), - SYSTEMCONTROL: system_control::SYSTEMCONTROL::instance(), TMPSNS: tmpsns::TMPSNS::instance(), TMR1: tmr::TMR1::instance(), TMR2: tmr::TMR2::instance(), diff --git a/src/imxrt1176_cm7.x b/src/imxrt1176_cm7.x index fc9ae0ee05a0..4b9276ea52bd 100644 --- a/src/imxrt1176_cm7.x +++ b/src/imxrt1176_cm7.x @@ -50,7 +50,6 @@ PROVIDE(CAN3 = DefaultHandler); PROVIDE(CAN3_ERROR = DefaultHandler); PROVIDE(FLEXRAM = DefaultHandler); PROVIDE(KPP = DefaultHandler); -PROVIDE(RESERVED68 = DefaultHandler); PROVIDE(GPR_IRQ = DefaultHandler); PROVIDE(ELCDIF = DefaultHandler); PROVIDE(LCDIFV2 = DefaultHandler); @@ -58,7 +57,6 @@ PROVIDE(CSI = DefaultHandler); PROVIDE(PXP = DefaultHandler); PROVIDE(MIPI_CSI = DefaultHandler); PROVIDE(MIPI_DSI = DefaultHandler); -PROVIDE(GPU2D = DefaultHandler); PROVIDE(GPIO6_COMBINED_0_15 = DefaultHandler); PROVIDE(GPIO6_COMBINED_16_31 = DefaultHandler); PROVIDE(DAC = DefaultHandler); @@ -153,16 +151,10 @@ PROVIDE(ACMP1 = DefaultHandler); PROVIDE(ACMP2 = DefaultHandler); PROVIDE(ACMP3 = DefaultHandler); PROVIDE(ACMP4 = DefaultHandler); -PROVIDE(RESERVED177 = DefaultHandler); -PROVIDE(RESERVED178 = DefaultHandler); -PROVIDE(RESERVED179 = DefaultHandler); -PROVIDE(RESERVED180 = DefaultHandler); PROVIDE(ENC1 = DefaultHandler); PROVIDE(ENC2 = DefaultHandler); PROVIDE(ENC3 = DefaultHandler); PROVIDE(ENC4 = DefaultHandler); -PROVIDE(RESERVED185 = DefaultHandler); -PROVIDE(RESERVED186 = DefaultHandler); PROVIDE(TMR1 = DefaultHandler); PROVIDE(TMR2 = DefaultHandler); PROVIDE(TMR3 = DefaultHandler); @@ -184,14 +176,6 @@ PROVIDE(PWM4_1 = DefaultHandler); PROVIDE(PWM4_2 = DefaultHandler); PROVIDE(PWM4_3 = DefaultHandler); PROVIDE(PWM4_FAULT = DefaultHandler); -PROVIDE(RESERVED208 = DefaultHandler); -PROVIDE(RESERVED209 = DefaultHandler); -PROVIDE(RESERVED210 = DefaultHandler); -PROVIDE(RESERVED211 = DefaultHandler); -PROVIDE(RESERVED212 = DefaultHandler); -PROVIDE(RESERVED213 = DefaultHandler); -PROVIDE(RESERVED214 = DefaultHandler); -PROVIDE(RESERVED215 = DefaultHandler); PROVIDE(PDM_HWVAD_EVENT = DefaultHandler); PROVIDE(PDM_HWVAD_ERROR = DefaultHandler); PROVIDE(PDM_EVENT = DefaultHandler);