Looking for ARM/PowerPC owner/maintainers

[pablodelara]

As you might have seen, we are working towards a new release, hopefully next January.
We need help from someone that has worked on the code for aarch64 (ARM) and ppc64le (PowerPC).
Could we get some owner for the implementations of these architectures?

Your help is much appreciated. Thanks!

[pablodelara]

@yuhaoth, @zhiyuan-zhu, @cyb70289 would you or someone in your organization (assuming you still work on ARM) could help on the aarch64 side?

@iii-i, @penghongbo, would you or someone in your organization (assuming you still work on IBM) could help on the ppc64le side?
Thanks!!

[tom-cosgrove-arm]

On the aarch64 side, we (Arm) do wish to help - capacity is limited at the moment, but we are planning to build this, to be able to help during 2024

[pablodelara]

Thanks @tom-cosgrove-arm, much appreciated! It would be great if you can double check if #259 fixes the existing compilation issue on aarch64.

[gerrith3]

So, I see your request for Power support. I have a couple of teams that do this internally, one being my own, another focused on Kubernetes based internals, and possibly another in our Storage team. And we love having the request to get involved and love it when more people are thinking about the Power architecture. But what I can't see is what the use case is and how it ties into anything that the Power brand is doing. I have heard that this might be related to ODF in some way, which would be interesting, but is there someone that could enlighten me as to what the value is here? I'd love to be able to help, but everything we do with our rather small team has a priority list tied to some major customer driven needs and we'd have to prioritize any involvement here against those other requests. If someone could spell it out for me either here or in email I will take an honest look at it to see what we can do but the "why" is important. Thanks for helping to connect the dots for me and then I'll see what we could do. BTW, we aren't the only Power architecture people in town and there may be others (e.g. Raptor) that might be even more interested. And if we can't help, you might be able to raise it with the Open Power Foundation - they've been looking for more opportunities to help with this as well. Sorry for the long response with so many questions, but hopefully this will get everyone to the same understanding about the need here.

[pablodelara]

Hi @gerrith3. Support for PowerPC was added back in 2020, adding code for Erasure Coding, optimized for PowerPC, from what I can see. My request is to have someone to verify everything looks OK for PowerPC before the release. So the value here is to make sure that the library is in a good shape for all architectures, that's it (for instance, there is currently an issue that is fixed in #259, so having someone from IBM or someone else using PowerPC checking if it actually fixes the issue would be ideal). Thanks!

[gerrith3]

Okay - thanks for the insights. I'm probably going to defer this to one of my colleagues in storage, either within IBM or Red Hat to see if they would be willing to take a look. While I was once upon a time a deep expert in storage arrays and led the push to knock over EMC and other data arrays with IO throughput from Dynix/PTX on our NUMA aware hardware, those days are a bit of a distant past (gack, was that the 90's?) those brain cells have been shelved to make room for other fun projects. Since most everyone is out until January and the fan restarts for everyone as the mud chunks start flying it may take a month or so to identify someone willing and able to reply, but I've got it for now and feel free to ping me if it looks like I've dropped the ball somewhere along the way...

[pablodelara]

Thanks @gerrith3!

[pablodelara]

@gerrith3 could you or someone in your organization test #259, to see if the build is fixed? Thanks!

[liuqinfei]

@pablodelara I would like to take the job for ARM. In fact, Our team has nearly 20 people. We have rich experience in optimizing ARM-related distributed storage performance. And we have enough Arm servers for verification.
crc: optimize by supporting arm xor fusion feature #247
crc16: Accelerate T10DIF performance with prefetch and pmull2 #204
erasure_code: Fix text relocation on aarch64 #172

[pablodelara]

Thanks for stepping up @liuqinfei!

[tom-cosgrove-arm]

@liuqinfei that's great - let us know if you need any support from our side