Support for Fenghuang

[lunzima]

I have a AMD Fenghuang (K17.5) and it's not supported by ZenStates.

It supports several SMU mailbox commands from Raven e.g. TDC (values too small causes a reboot),

[lunzima]

Trying with CPUHandler.CPUType.DEBUG and it throws InvalidArguments exception

[irusanov]

Try it with forcing CPUtype to Raven_Ridge. DEBUG type doesn't do much and I haven't changed that part of the code. It only sets some Pstates and default values, but nothing more. You can't use most of the functions, because it needs correct addresses.

Edit: Perhaps one possible way to deal with it is to make the app try different addresses and send a test message. When the response is correct, then it would mean the app have found the correct address. Some kind of an automatic detection, although this might have unexpected consequences if some of these addresses match something else. But it could be used for a debug purposes at least.

[lunzima]

It seems that this CPU has only two P-state P0 and P1,
ZenStates can read P0 correctly but not P1.

[irusanov]

Thanks for the report. This makes it harder with all the variations. I will have to think about a way to detect supported P-States reliably.

[irusanov]

First version is up: https://github.com/irusanov/SMUDebugTool
You can set the addresses and command manually. There's basic support for Renoir, however I don't know if it works at all. What makes it even more difficult is your APU is an ES, so many things might be different than future retails.

[lunzima]

Got nothing with SMUDebugTool.

An outsourced AMD field application engineer (literally "Agricultural Enterprise contract employee") said this is expected behavior.

Considering Fenghuang a legacy of AMD Shanghai, that's it.

[irusanov]

Yes, that's expected. It probably has different offset between msg and rsp. I will give you a set of addresses to try.
Edit: It seems this is a custom Ryzen SoC, perhaps based on first generation, regardless the newer CPUID.

[irusanov]

Can you try these sets:

CMD Address: 0x3B1051C
RSP Address: 0x3B10568
ARG Address: 0x3B10590

CMD Address: 0x3B10A20
RSP Address: 0x3B10A80
ARG Address: 0x3B10A88

CMD Address: 0x3B10524
RSP Address: 0x3B10570
ARG Address: 0x3B10590

CMD Address: 0x3B10524
RSP Address: 0x3B10570
ARG Address: 0x3B10A40

CMD Address: 0x3B10520
RSP Address: 0x3B1056C
ARG Address: 0x3B109B8

Try to send 0x1 and/or 0x2 command from SMU tab and if any of these give you OK, then you can use the addresses that worked. If not, we'll have to try something else.

[lunzima]

The second set of SMU address is working, so you should treat Fenghuang as a variant of Raven although useful mailbox commands is limited.
With wrong SMU address the graphics driver goes wrong and produces garbled display, so be careful.

[irusanov]

Thanks for the valuable info. Yes, the tool is not entirely safe and may cause unpredictable issues.
Based on your test, it seems to be using Picasso's SMU addresses. That is Zen+ with Vega graphics.

The commands for the APUs are entirely different than the ones of the desktop parts. It is more in line with what FlyGoat has in his repo, but I have to compare. There are commands for the GFX on top of the CPU ones and I think it needs a little different approach.

Perhaps it's a good idea to have a separate app for APUs, because it would be difficult to support all possible CPUs in one package.

[lunzima]

Flygoat (aka "Bed sheet works contract employee") has been implementing "Core Boost" functions on Loongson 3A4000 (with integrated GS132 "SMU" equivalent) these days, so there might be few update on his ryzen_nb_smu :-(
In fact, Flygoat told me that this ZenStates exists, so I tested this on my Subor RUYI.

[alexantone]

Thanks for the report. This makes it harder with all the variations. I will have to think about a way to detect supported P-States reliably.

Based on the amd MSR documentation the number of pstates is given by bits [6:4] of
MSR 0xC0010061 [P-state Current Limit]*

Bits	Description
63:7	Reserved.
6:4	PstateMaxVal: P-state maximum value. Specifies the lowest-performance non-boosted P-state (highest non-boosted value) allowed.
3	Reserved. Read-only. Reset: Fixed,0.
2:0	CurPstateLimit: current P-state limit. Specifies the highest-performance P-state (lowest value) allowed. CurPstateLimit is always bounded by PstateMaxVal.

*Open-Source Register Reference for AMD Family 17h Processors (PUB)

[irusanov]

Yes, I've implemented it in the new version of the app some time ago. There is more information available about the SMU, discovered just recently and I will try to work on it in the next weeks.

https://github.com/irusanov/ZenStates/blob/dev/MainForm.cs#L419

[irusanov]

This test version should support it now.

ZenStates_2.0.0_debug_20200529.zip

[lunzima]

Sorry, but it does not work.

[irusanov]

I mean the P-States. Should detect just 2 P-States which could be manipulated. The manual OC will be disabled or removed for CPUs that don't support it.
I found that manual OC does not work on my desktop RavenRidge-based APUs, so I guess it's the same with Fenghuang.