Future_Features.md

Future Features

Presented in no particular order, below are some additional features that will extend and enhance the simulator. (Once-future features that have already been implemented have been struck through.)

1. superscalar out-of-order pipeline implementation (code name: Yuzu)
2. retool per-core execution to leverage Python's threading module
3. per-core cycle count
4. cache snooping
5. pipeline implementation with value prediction
6. perfect branch predictor
7. perfect value predictor
8. return address stack
9. implement new eviction policies (e.g., least frequently used) for SimpleCache and SimpleBTB
10. Kubernetes deployment
11. ARM instruction set support
12. MIPS instruction set support
13. x86_64 instruction set support
14. SPARC v9 instruction set support
15. "component'ized" Tangelo reimplementation (code name: Tangerine)
16. "component'ized" Bergamot reimplementation (code name: Etrog)
17. MMU service
18. shared caches
19. accelerated mmap-based main memory implementation
20. sample Jupyter Notebook for fetching and processing data from MongoDB
21. pipeline implementation with decoupled fetch engine
22. multi-core support with cache sharing
23. syscall proxying
24. launch from binary's _start label rather than main label
25. tool for cataloging, indexing, and retrieving simulator runs

That said, since this is a toolkit intended to facilitate microarchitecture research, some of these, as my math textbooks used to say, "will be left as an exercise" for researchers.