New version ?

[forthyen]

Could you upload new updated source code for new version Verilator's XML output file ?

[jrrk]

The most up to date version is here: <https://github.com/jrrk2/sysver2ver> [sysver2ver.png] jrrk2/sysver2ver: Converting System Verilog to plain Verilog using .xml dump from Verilator<https://github.com/jrrk2/sysver2ver> github.com<https://github.com/jrrk2/sysver2ver> However this is incomplete and does not output valid Verilog at the moment. I’m interested what you are using it for, perhaps I can help. Meanwhile sv2v which is more advanced in many ways has improved significantly.

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