From 7ddaa4cb7512aa7b1abb1f7cd8f2ad8cd8e37558 Mon Sep 17 00:00:00 2001
From: Ivan Kosarev <mail@ivankosarev.com>
Date: Mon, 5 Aug 2024 22:04:17 +0100
Subject: [PATCH] [Python][#61] Support OUTI instruction.

---
 tests/testsuite.py | 1 +
 z80/__init__.py    | 3 ++-
 z80/_disasm.py     | 4 +++-
 z80/_instr.py      | 4 ++++
 4 files changed, 10 insertions(+), 2 deletions(-)

diff --git a/tests/testsuite.py b/tests/testsuite.py
index 6eca4e1..63d7692 100644
--- a/tests/testsuite.py
+++ b/tests/testsuite.py
@@ -14,6 +14,7 @@ def runTest(self):
             (b'\xdd\xe5', 'push ix'),
             (b'\xfd\xe1', 'pop iy'),
             (b'\xed\x50', 'in d, (c)'),
+            (b'\xed\xa3', 'outi'),
             )
 
         builder = z80.Z80InstrBuilder()
diff --git a/z80/__init__.py b/z80/__init__.py
index 2fd8d26..d7fcdad 100644
--- a/z80/__init__.py
+++ b/z80/__init__.py
@@ -12,7 +12,8 @@
 from ._instr import (ADD, ADC, AND, CP, OR, SBC, SUB, XOR, BIT, CALL, CCF, CPL,
                      DAA, DEC, DI, DJNZ, EI, EX, EXX, HALT, IM, INC, IN, JP,
                      JR, LD, LDDR, LDIR, NEG, NOP, RLC, RL, RR, RRC, SLA, SRA,
-                     SRL, OUT, POP, PUSH, RES, RET, RLA, RLCA, RLD, RRA, RRCA,
+                     SRL, OUT, OUTI, POP, PUSH, RES, RET,
+                     RLA, RLCA, RLD, RRA, RRCA,
                      RST, SCF, SET, A, AF, AF2, CF, M, NC, NZ, PO, P, Z, DE,
                      BC, HL, IReg, IY, IX, SP, B, C, D, E, H, L, UnknownInstr,
                      JumpInstr, CallInstr, RetInstr, At, IndexReg, Add)
diff --git a/z80/_disasm.py b/z80/_disasm.py
index d86d541..b9f4582 100644
--- a/z80/_disasm.py
+++ b/z80/_disasm.py
@@ -16,7 +16,8 @@
 from ._instr import (ADD, ADC, AND, CP, OR, SBC, SUB, XOR, BIT, CALL, CCF, CPL,
                      DAA, DEC, DI, DJNZ, EI, EX, EXX, HALT, IM, INC, IN, JP,
                      JR, LD, LDDR, LDIR, NEG, NOP, RLC, RL, RR, RRC, SLA, SRA,
-                     SRL, OUT, POP, PUSH, RES, RET, RLA, RLCA, RLD, RRA, RRCA,
+                     SRL, OUT, OUTI, POP, PUSH, RES, RET,
+                     RLA, RLCA, RLD, RRA, RRCA,
                      RST, SCF, SET, A, AF, AF2, CF, M, NC, NZ, PO, P, Z, DE,
                      BC, HL, IReg, IY, IX, SP, B, C, D, E, H, L, UnknownInstr,
                      JumpInstr, CallInstr, RetInstr, At, IndexReg, Add)
@@ -183,6 +184,7 @@ class Z80InstrBuilder(object):
         'sbc': SBC,
         'scf': SCF,
         'set': SET,
+        'Touti': OUTI,
     }
 
     __OPS = {
diff --git a/z80/_instr.py b/z80/_instr.py
index cf8882e..bdbc32e 100644
--- a/z80/_instr.py
+++ b/z80/_instr.py
@@ -328,6 +328,10 @@ class OUT(Instr):
     pass
 
 
+class OUTI(Instr):
+    pass
+
+
 class POP(Instr):
     pass