diff --git a/include/circt/Dialect/FIRRTL/FIRRTLIntrinsics.td b/include/circt/Dialect/FIRRTL/FIRRTLIntrinsics.td
index 99aa2770d51c..9a24d7f2d77d 100644
--- a/include/circt/Dialect/FIRRTL/FIRRTLIntrinsics.td
+++ b/include/circt/Dialect/FIRRTL/FIRRTLIntrinsics.td
@@ -231,4 +231,16 @@ def DPICallIntrinsicOp : FIRRTLOp<"int.dpi.call",
   let hasVerifier = 1;
 }
 
+def ViewIntrinsicOp : FIRRTLOp<"view", []> {
+  let summary = "A SystemVerilog Interface only usable for waveform debugging";
+  let description = [{
+    This will become a SystemVerilog Interface that is driven by its arguments.
+    This is _not_ intended to be used for anything other than assistance when
+    debugging in a waveform.  This is _not_ a true SystemVerilog Interface, it
+    is only lowered to one.
+  }];
+  let arguments = (ins StrAttr:$name, AugmentedBundleType:$augmentedType, Variadic<RefType>:$probes);
+  let assemblyFormat = "$name `,` $augmentedType (`,` $probes^)? attr-dict `:` type($probes)";
+}
+
 #endif // CIRCT_DIALECT_FIRRTL_FIRRTLINTRINSICS_TD
diff --git a/test/Dialect/FIRRTL/round-trip.mlir b/test/Dialect/FIRRTL/round-trip.mlir
index cfda6999fcd5..345792b40148 100644
--- a/test/Dialect/FIRRTL/round-trip.mlir
+++ b/test/Dialect/FIRRTL/round-trip.mlir
@@ -40,6 +40,39 @@ firrtl.module @Intrinsics(in %ui : !firrtl.uint, in %clock: !firrtl.clock, in %u
   %p = firrtl.int.generic "params" <FORMAT: none = "foobar"> : () -> !firrtl.bundle<x: uint<1>>
   %po = firrtl.int.generic "params_and_operand" <X: i64 = 123> %ui1 : (!firrtl.uint<1>) -> !firrtl.clock
   firrtl.int.generic "inputs" %clock, %ui1, %clock : (!firrtl.clock, !firrtl.uint<1>, !firrtl.clock) -> ()
+
+  %probe = firrtl.wire : !firrtl.probe<uint<1>>
+  // CHECK: firrtl.view "View"
+  // CHECK-SAME: <{
+  // CHECK-SAME:     elements = [
+  // CHECK-SAME:       {
+  // CHECK-SAME:         class = "sifive.enterprise.grandcentral.AugmentedGroundType",
+  // CHECK-SAME:         id = 0 : i64,
+  // CHECK-SAME:         name = "baz"
+  // CHECK-SAME:       },
+  // CHECK-SAME:       {
+  // CHECK-SAME:         class = "sifive.enterprise.grandcentral.AugmentedGroundType",
+  // CHECK-SAME:         id = 0 : i64,
+  // CHECK-SAME:         name = "qux"
+  // CHECK-SAME:       }
+  // CHECK-SAME:     ]
+  // CHECK-SAME: }>, %probe, %probe : !firrtl.probe<uint<1>>, !firrtl.probe<uint<1>>
+  firrtl.view "View", <{
+    class = "sifive.enterprise.grandcentral.AugmentedBundleType",
+    defName = "Bar",
+    elements = [
+      {
+        class = "sifive.enterprise.grandcentral.AugmentedGroundType",
+        id = 0 : i64,
+        name = "baz"
+      },
+      {
+        class = "sifive.enterprise.grandcentral.AugmentedGroundType",
+        id = 0 : i64,
+        name = "qux"
+      }
+    ]
+  }>, %probe, %probe : !firrtl.probe<uint<1>>, !firrtl.probe<uint<1>>
 }
 
 // CHECK-LABEL: firrtl.module @FPGAProbe