diff --git a/llvm/lib/Analysis/ValueTracking.cpp b/llvm/lib/Analysis/ValueTracking.cpp
index 69b2710420391d..dcd30c85fdae95 100644
--- a/llvm/lib/Analysis/ValueTracking.cpp
+++ b/llvm/lib/Analysis/ValueTracking.cpp
@@ -724,10 +724,22 @@ static void computeKnownBitsFromCond(const Value *V, Value *Cond,
     Known = Known.unionWith(Known2);
   }
 
-  if (auto *Cmp = dyn_cast<ICmpInst>(Cond))
-    computeKnownBitsFromCmp(
-        V, Invert ? Cmp->getInversePredicate() : Cmp->getPredicate(),
-        Cmp->getOperand(0), Cmp->getOperand(1), Known, SQ);
+  if (auto *Cmp = dyn_cast<ICmpInst>(Cond)) {
+    ICmpInst::Predicate Pred =
+        Invert ? Cmp->getInversePredicate() : Cmp->getPredicate();
+    Value *LHS = Cmp->getOperand(0);
+    Value *RHS = Cmp->getOperand(1);
+
+    // Handle icmp pred (trunc V), C
+    if (match(LHS, m_Trunc(m_Specific(V)))) {
+      KnownBits DstKnown(LHS->getType()->getScalarSizeInBits());
+      computeKnownBitsFromCmp(LHS, Pred, LHS, RHS, DstKnown, SQ);
+      Known = Known.unionWith(DstKnown.anyext(Known.getBitWidth()));
+      return;
+    }
+
+    computeKnownBitsFromCmp(V, Pred, LHS, RHS, Known, SQ);
+  }
 }
 
 void llvm::computeKnownBitsFromContext(const Value *V, KnownBits &Known,
@@ -9111,7 +9123,7 @@ addValueAffectedByCondition(Value *V,
 
     // Peek through unary operators to find the source of the condition.
     Value *Op;
-    if (match(I, m_PtrToInt(m_Value(Op)))) {
+    if (match(I, m_CombineOr(m_PtrToInt(m_Value(Op)), m_Trunc(m_Value(Op))))) {
       if (isa<Instruction>(Op) || isa<Argument>(Op))
         InsertAffected(Op);
     }
diff --git a/llvm/test/Transforms/InstCombine/known-bits.ll b/llvm/test/Transforms/InstCombine/known-bits.ll
index 49e0e1dd226231..b022f91340c6c5 100644
--- a/llvm/test/Transforms/InstCombine/known-bits.ll
+++ b/llvm/test/Transforms/InstCombine/known-bits.ll
@@ -350,8 +350,7 @@ define i32 @test_icmp_trunc1(i32 %x){
 ; CHECK-NEXT:    [[CMP:%.*]] = icmp eq i16 [[Y]], 7
 ; CHECK-NEXT:    br i1 [[CMP]], label [[THEN:%.*]], label [[ELSE:%.*]]
 ; CHECK:       then:
-; CHECK-NEXT:    [[Z:%.*]] = and i32 [[X]], 15
-; CHECK-NEXT:    ret i32 [[Z]]
+; CHECK-NEXT:    ret i32 7
 ; CHECK:       else:
 ; CHECK-NEXT:    ret i32 0
 ;
@@ -372,9 +371,8 @@ define i64 @test_icmp_trunc2(i64 %x) {
 ; CHECK-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[CONV]], 12
 ; CHECK-NEXT:    br i1 [[CMP]], label [[IF_THEN:%.*]], label [[IF_ELSE:%.*]]
 ; CHECK:       if.then:
-; CHECK-NEXT:    [[SEXT:%.*]] = shl i64 [[X]], 32
-; CHECK-NEXT:    [[RET:%.*]] = ashr exact i64 [[SEXT]], 32
-; CHECK-NEXT:    ret i64 [[RET]]
+; CHECK-NEXT:    [[SEXT:%.*]] = and i64 [[X]], 2147483647
+; CHECK-NEXT:    ret i64 [[SEXT]]
 ; CHECK:       if.else:
 ; CHECK-NEXT:    ret i64 0
 ;
@@ -397,7 +395,7 @@ define i64 @test_icmp_trunc3(i64 %n) {
 ; CHECK-NEXT:    [[CMP:%.*]] = icmp ult i32 [[CONV]], 96
 ; CHECK-NEXT:    br i1 [[CMP]], label [[IF_THEN:%.*]], label [[IF_ELSE:%.*]]
 ; CHECK:       if.then:
-; CHECK-NEXT:    [[RET:%.*]] = and i64 [[N]], 4294967295
+; CHECK-NEXT:    [[RET:%.*]] = and i64 [[N]], 127
 ; CHECK-NEXT:    ret i64 [[RET]]
 ; CHECK:       if.else:
 ; CHECK-NEXT:    ret i64 0
@@ -422,7 +420,7 @@ define i8 @test_icmp_trunc4(i64 %n) {
 ; CHECK-NEXT:    br i1 [[CMP]], label [[IF_THEN:%.*]], label [[IF_ELSE:%.*]]
 ; CHECK:       if.then:
 ; CHECK-NEXT:    [[CONV2:%.*]] = trunc i64 [[N]] to i8
-; CHECK-NEXT:    [[ADD:%.*]] = add i8 [[CONV2]], 48
+; CHECK-NEXT:    [[ADD:%.*]] = or disjoint i8 [[CONV2]], 48
 ; CHECK-NEXT:    ret i8 [[ADD]]
 ; CHECK:       if.else:
 ; CHECK-NEXT:    ret i8 0
@@ -448,8 +446,8 @@ define i64 @test_icmp_trunc5(i64 %n) {
 ; CHECK-NEXT:    [[CMP:%.*]] = icmp ugt i32 [[CONV1]], -13
 ; CHECK-NEXT:    br i1 [[CMP]], label [[IF_THEN:%.*]], label [[IF_ELSE:%.*]]
 ; CHECK:       if.then:
-; CHECK-NEXT:    [[AND:%.*]] = and i64 [[SHR]], 4294967295
-; CHECK-NEXT:    [[NOT:%.*]] = xor i64 [[AND]], 4294967295
+; CHECK-NEXT:    [[TMP0:%.*]] = and i64 [[SHR]], 15
+; CHECK-NEXT:    [[NOT:%.*]] = xor i64 [[TMP0]], 15
 ; CHECK-NEXT:    ret i64 [[NOT]]
 ; CHECK:       if.else:
 ; CHECK-NEXT:    ret i64 13