[ValueTracking] Missed optimization: indicate knownbits from dominating condition switch(trunc(a))

[XChy]

Alive2 proof: https://alive2.llvm.org/ce/z/NdBYVJ

Motivating example

define i32 @src(i64 %addr, i32 %0) {
entry:
  %trunc = trunc i32 %0 to i16
  switch i16 %trunc, label %fail [
    i16 267, label %common.ret
    i16 204, label %common.ret
    i16 263, label %common.ret
    i16 1, label %sw.bb
  ]

common.ret:
  ret i32 0

sw.bb:
  %and75 = and i32 %0, 65535
  ret i32 %and75

fail:
  call void @dummy()
  br label %common.ret
}

can be folded to:

define i32 @tgt(i64 %addr, i32 %0) {
entry:
  %trunc = trunc i32 %0 to i16
  switch i16 %trunc, label %fail [
    i16 267, label %common.ret
    i16 204, label %common.ret
    i16 263, label %common.ret
    i16 1, label %sw.bb
  ]

common.ret:
  ret i32 0

sw.bb:
  ret i32 1

fail:
  call void @dummy()
  br label %common.ret
}

Real-world motivation

This snippet of IR is derived from qemu/hw/core/loader.c@load_aout (after O3 pipeline).
The example above is a reduced version. If you're interested in the original suboptimal IR and optimal IR, see also:https://godbolt.org/z/Woa6n1rW1

Let me know if you can confirm that it's an optimization opportunity, thanks.

[nikic]

Hm, I thought that @dtcxzyw recently added support for this.

[XChy]

Hm, I thought that @dtcxzyw recently added support for this.

Oh, sorry for duplicating it. It seems that opt on Alive2 doesn't optimize the case without switch, but godbolt does: https://godbolt.org/z/KxMn1Mbnd
However, the switch case in real world isn't optimized: https://godbolt.org/z/Wcz73rdP6

Edit: And could you post the link of patch posted by @dtcxzyw? I can't find it.

[nikic]

@XChy The patch is #82803. It landed recently, and I think alive2 updates fairly rarely.

[dtcxzyw]

Hm, I thought that @dtcxzyw recently added support for this.

Emm, currently DomConditionCache doesn't support switches. @nikic Do you plan to fix it?