Maintain backward compatibility for concat_pass_wire

[alaindargelas]

Describe the bug
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To Reproduce
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1. Clone OpenFPGA repository and checkout commit id:

5164421...2ae0d08#diff-3594f5423ea1e44928a56cc5c62ff68cefed5658f5898e67331c6da77a162a56

2. Execute OpenFPGA task or your own example:
3. See error

Expected behavior
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After this PR, all pre-existing vpr.xml have to be amended like following:
From:
<layout tileable="true" through_channel="true">
To:
<layout tileable="true" through_channel="true" concat_wire="false" concat_pass_wire="true">

To maintain Bitstream backward compatibility.
This pauses a problem for tape-outs in progress.
Please invert the logic so the default value of concat_wire="false" concat_pass_wire="true" are as noted here.

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