synthesis timing error

[anudeepdharavathu]

Synthesis tool: Synopsys design compiler Version U-2022.12 for linux64
script used: run_script_openfpga.txt
timing constraint: TOP.txt
Command used: dcnxt_shell -f run_script_openfpga.tcl
Notes: I am trying to synthesize the openFPGA fabric generated with the attached task.conf file.
Can someone please help me set the right constraint because the timing report generated doesn't look correct?

task.txt

run_script_openfpga.txt
TOP.txt