Getting an error regarding route_chan_width

[PradyumnaG]

Hey, I ran the code for generate_fabric but with fpga_flow as yosys_vpr. I'm encountering an error:
Error 1:
Type: Routing
File: /home/pradyumna/Documents/vtr_2/OpenFPGA/vtr-verilog-to-routing/vpr/src/base/place_and_route.cpp
Line: 173
Message: This circuit requires a channel width above 1000, probably is not going to route.
Aborting routing procedure.

The entire flow of VPR took 42.24 seconds (max_rss 196.8 MiB)
Fatal error occurred!
OpenFPGA Abort

Error 2: Command 'vpr' execution has fatal errors

Finish execution with 2 errors
The above works for and2.v but does not work for vtr_benchmarks like diffeq1.v
I'm attaching the vpr_stdout.log and task.conf file, can you help me resolve this error
vpr_stdout.log
task.txt

Also I'm using the arch files given in the vpr_arch and openfpga_arch
I'm also attaching the arch files

k6_frac_N10_adder_chain_frac_mem32K_frac_dsp36_40nm_GlobalTile8Clk_openfpga.txt
k6_frac_N10_tileable_adder_chain_frac_mem32K_frac_dsp36_GlobalTile8Clk_40nm.txt

If the above arch files are not compatible for diffeq1.v, can you suggest arch files which can support diffeq1.v

[tangxifan]

@PradyumnaG Please use ideal for clock modeling when calling VPR, as you are using the GlobalTileClk feature.

vpr /home/pradyumna/Documents/vtr_2/OpenFPGA/openfpga_flow/tasks/basic_tests/generate_fabric/run030/k6_frac_N10_tileable_adder_chain_frac_mem32K_frac_dsp36_GlobalTile8Clk_40nm/diffeq_paj_convert/MIN_ROUTE_CHAN_WIDTH/arch/k6_frac_N10_tileable_adder_chain_frac_mem32K_frac_dsp36_GlobalTile8Clk_40nm.xml diffeq_paj_convert.blif --clock_modeling ideal