ibex_demo_system.core

CAPI=2:
# Copyright lowRISC contributors.
# Licensed under the Apache License, Version 2.0, see LICENSE for details.
# SPDX-License-Identifier: Apache-2.0
name: "lowrisc:ibex:demo_system"
description: "Ibex Demo System for Arty A7 boards (both, -35 and -100)"
filesets:
  files_rtl:
    depend:
      - lowrisc:ibex:demo_system_core

  files_xilinx:
    depend:
      - lowrisc:ibex:rv_timer
      - lowrisc:ibex:fpga_xilinx_shared
    files:
      - rtl/fpga/top_artya7.sv
    file_type: systemVerilogSource

  files_xilinx_cw305:
    depend:
      - lowrisc:ibex:rv_timer
      - lowrisc:ibex:fpga_xilinx_shared
    files:
      - rtl/fpga/top_cw305.sv
    file_type: systemVerilogSource

  files_xilinx_cw312a35:
    depend:
      - lowrisc:ibex:rv_timer
      - lowrisc:ibex:fpga_xilinx_shared
    files:
      - rtl/fpga/top_cw312a35.sv
    file_type: systemVerilogSource

  files_sonata:
    depend:
      - lowrisc:ibex:rv_timer
      - lowrisc:ibex:fpga_xilinx_shared
    files:
      - rtl/fpga/top_sonata.sv
      - rtl/fpga/clkgen_sonata.sv
      - rtl/fpga/rst_ctrl.sv
    file_type: systemVerilogSource

  files_verilator:
    depend:
      - lowrisc:ibex:sim_shared
      - lowrisc:dv_verilator:memutil_verilator
      - lowrisc:dv_verilator:simutil_verilator
      - lowrisc:dv_verilator:ibex_pcounts
      - lowrisc:dv_dpi_c:uartdpi:0.1
      - lowrisc:dv_dpi_sv:uartdpi:0.1
    files:
      - dv/verilator/top_verilator.sv: { file_type: systemVerilogSource }
      - dv/verilator/ibex_demo_system.cc: { file_type: cppSource }
      - dv/verilator/ibex_demo_system.h:  { file_type: cppSource, is_include_file: true}
      - dv/verilator/ibex_demo_system_main.cc: { file_type: cppSource }
      - dv/verilator/demo_system_verilator_lint.vlt:  { file_type: vlt }

  files_constraints:
    files:
      - data/pins_artya7.xdc
    file_type: xdc

  files_constraints_cw305:
    files:
      - data/pins_cw305.xdc
    file_type: xdc

  files_constraints_cw312a35:
    files:
      - data/pins_cw312a35.xdc
    file_type: xdc

  files_constraints_sonata:
    files:
      - data/pins_sonata.xdc
    file_type: xdc

parameters:
  # XXX: This parameter needs to be absolute, or relative to the *.runs/synth_1
  # directory. It's best to pass it as absolute path when invoking fusesoc, e.g.
  # --SRAMInitFile=$PWD/sw/led/led.vmem
  # XXX: The VMEM file should be added to the sources of the Vivado project to
  # make the Vivado dependency tracking work. However this requires changes to
  # fusesoc first.
  SRAMInitFile:
    datatype: str
    description: SRAM initialization file in vmem hex format
    default: "../../../../../sw/c/build/blank/blank.vmem"
    paramtype: vlogparam

  # For value definition, please see ip/prim/rtl/prim_pkg.sv
  PRIM_DEFAULT_IMPL:
    datatype: str
    paramtype: vlogdefine
    description: Primitives implementation to use, e.g. "prim_pkg::ImplGeneric".

targets:
  default: &default_target
    filesets:
      - files_rtl
  synth:
    <<: *default_target
    default_tool: vivado
    filesets_append:
      - files_xilinx
      - files_constraints
    toplevel: top_artya7
    tools:
      vivado:
        part: "xc7a35tcsg324-1"  # Default to Arty A7-35
    parameters:
      - SRAMInitFile
      - PRIM_DEFAULT_IMPL=prim_pkg::ImplXilinx
    flags:
      use_bscane_tap: true
  synth_cw305:
    <<: *default_target
    default_tool: vivado
    filesets_append:
      - files_xilinx_cw305
      - files_constraints_cw305
    toplevel: top_cw305
    tools:
      vivado:
        part: "xc7a100tftg256-2" # default to a100 part
        #part: "xc7a35tftg256-2" # a35 option
    parameters:
      - SRAMInitFile
      - PRIM_DEFAULT_IMPL=prim_pkg::ImplXilinx
    flags:
      use_bscane_tap: true
  synth_cw312a35:
    <<: *default_target
    default_tool: vivado
    filesets_append:
      - files_xilinx_cw312a35
      - files_constraints_cw312a35
    toplevel: top_cw312a35
    tools:
      vivado:
        part: "xc7a35tcsg324-1"
    parameters:
      - SRAMInitFile
      - PRIM_DEFAULT_IMPL=prim_pkg::ImplXilinx
    flags:
      use_bscane_tap: true
  synth_sonata:
    <<: *default_target
    default_tool: vivado
    filesets_append:
      - files_sonata
      - files_constraints_sonata
    toplevel: top_sonata
    tools:
      vivado:
        part: "xc7a50tcsg324-1"
    parameters:
      - SRAMInitFile
      - PRIM_DEFAULT_IMPL=prim_pkg::ImplXilinx

  sim:
    <<: *default_target
    default_tool: verilator
    filesets_append:
      - files_verilator
    toplevel: top_verilator
    tools:
      verilator:
        mode: cc
        verilator_options:
          # Disabling tracing reduces compile times but doesn't have a
          # huge influence on runtime performance.
          - '--trace'
          - '--trace-fst' # this requires -DVM_TRACE_FMT_FST in CFLAGS below!
          - '--trace-structs'
          - '--trace-params'
          - '--trace-max-array 1024'
          - '-CFLAGS "-std=c++14 -Wall -DVM_TRACE_FMT_FST -DTOPLEVEL_NAME=top_verilator"'
          - '-LDFLAGS "-pthread -lutil -lelf"'
          - "-Wall"
          - "-Wwarn-IMPERFECTSCH"
          # RAM primitives wider than 64bit (required for ECC) fail to build in
          # Verilator without increasing the unroll count (see Verilator#1266)
          - "--unroll-count 72"
    parameters:
      - PRIM_DEFAULT_IMPL=prim_pkg::ImplGeneric