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Triggered_ADC_Sequencer_hw.tcl
executable file
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Triggered_ADC_Sequencer_hw.tcl
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# TCL File Generated by Component Editor 15.0
# Thu Sep 17 15:59:53 BST 2015
# DO NOT MODIFY
#
# Triggered_ADC_Sequencer "Triggered ADC Sequencer" v1.0
# 2015.09.17.15:59:53
#
#
#
# request TCL package from ACDS 15.0
#
package require -exact qsys 15.0
#
# module Triggered_ADC_Sequencer
#
set_module_property DESCRIPTION ""
set_module_property NAME Triggered_ADC_Sequencer
set_module_property VERSION 1.0
set_module_property INTERNAL false
set_module_property OPAQUE_ADDRESS_MAP true
set_module_property AUTHOR ""
set_module_property DISPLAY_NAME "Triggered ADC Sequencer"
set_module_property INSTANTIATE_IN_SYSTEM_MODULE true
set_module_property EDITABLE true
set_module_property REPORT_TO_TALKBACK false
set_module_property ALLOW_GREYBOX_GENERATION false
set_module_property REPORT_HIERARCHY false
#
# file sets
#
add_fileset QUARTUS_SYNTH QUARTUS_SYNTH "" ""
set_fileset_property QUARTUS_SYNTH TOP_LEVEL Triggered_ADC_Sequencer
set_fileset_property QUARTUS_SYNTH ENABLE_RELATIVE_INCLUDE_PATHS false
set_fileset_property QUARTUS_SYNTH ENABLE_FILE_OVERWRITE_MODE true
add_fileset_file Triggered_ADC_Sequencer.v VERILOG PATH Triggered_ADC_Sequencer.v TOP_LEVEL_FILE
add_fileset SIM_VERILOG SIM_VERILOG "" ""
set_fileset_property SIM_VERILOG TOP_LEVEL Triggered_ADC_Sequencer
set_fileset_property SIM_VERILOG ENABLE_RELATIVE_INCLUDE_PATHS false
set_fileset_property SIM_VERILOG ENABLE_FILE_OVERWRITE_MODE true
add_fileset_file Triggered_ADC_Sequencer.v VERILOG PATH Triggered_ADC_Sequencer.v
#
# parameters
#
#
# display items
#
#
# connection point clock_sink
#
add_interface clock_sink clock end
set_interface_property clock_sink clockRate 0
set_interface_property clock_sink ENABLED true
set_interface_property clock_sink EXPORT_OF ""
set_interface_property clock_sink PORT_NAME_MAP ""
set_interface_property clock_sink CMSIS_SVD_VARIABLES ""
set_interface_property clock_sink SVD_ADDRESS_GROUP ""
add_interface_port clock_sink clk clk Input 1
#
# connection point reset_sink
#
add_interface reset_sink reset end
set_interface_property reset_sink associatedClock clock_sink
set_interface_property reset_sink synchronousEdges DEASSERT
set_interface_property reset_sink ENABLED true
set_interface_property reset_sink EXPORT_OF ""
set_interface_property reset_sink PORT_NAME_MAP ""
set_interface_property reset_sink CMSIS_SVD_VARIABLES ""
set_interface_property reset_sink SVD_ADDRESS_GROUP ""
add_interface_port reset_sink reset_n reset_n Input 1
#
# connection point cmd_ch_as_data
#
add_interface cmd_ch_as_data avalon_streaming start
set_interface_property cmd_ch_as_data associatedClock clock_sink
set_interface_property cmd_ch_as_data associatedReset reset_sink
set_interface_property cmd_ch_as_data dataBitsPerSymbol 5
set_interface_property cmd_ch_as_data errorDescriptor ""
set_interface_property cmd_ch_as_data firstSymbolInHighOrderBits true
set_interface_property cmd_ch_as_data maxChannel 0
set_interface_property cmd_ch_as_data readyLatency 0
set_interface_property cmd_ch_as_data ENABLED true
set_interface_property cmd_ch_as_data EXPORT_OF ""
set_interface_property cmd_ch_as_data PORT_NAME_MAP ""
set_interface_property cmd_ch_as_data CMSIS_SVD_VARIABLES ""
set_interface_property cmd_ch_as_data SVD_ADDRESS_GROUP ""
add_interface_port cmd_ch_as_data chout_ready ready Input 1
add_interface_port cmd_ch_as_data chout_valid valid Output 1
add_interface_port cmd_ch_as_data chout_data data Output 5
add_interface_port cmd_ch_as_data chout_startofpacket startofpacket Output 1
add_interface_port cmd_ch_as_data chout_endofpacket endofpacket Output 1
#
# connection point interrupt_sender
#
add_interface interrupt_sender interrupt end
set_interface_property interrupt_sender associatedAddressablePoint avalon_slave
set_interface_property interrupt_sender associatedClock clock_sink
set_interface_property interrupt_sender associatedReset reset_sink
set_interface_property interrupt_sender bridgedReceiverOffset ""
set_interface_property interrupt_sender bridgesToReceiver ""
set_interface_property interrupt_sender ENABLED true
set_interface_property interrupt_sender EXPORT_OF ""
set_interface_property interrupt_sender PORT_NAME_MAP ""
set_interface_property interrupt_sender CMSIS_SVD_VARIABLES ""
set_interface_property interrupt_sender SVD_ADDRESS_GROUP ""
add_interface_port interrupt_sender irq_out irq Output 1
#
# connection point avalon_slave
#
add_interface avalon_slave avalon end
set_interface_property avalon_slave addressUnits WORDS
set_interface_property avalon_slave associatedClock clock_sink
set_interface_property avalon_slave associatedReset reset_sink
set_interface_property avalon_slave bitsPerSymbol 8
set_interface_property avalon_slave burstOnBurstBoundariesOnly false
set_interface_property avalon_slave burstcountUnits WORDS
set_interface_property avalon_slave explicitAddressSpan 0
set_interface_property avalon_slave holdTime 0
set_interface_property avalon_slave linewrapBursts false
set_interface_property avalon_slave maximumPendingReadTransactions 0
set_interface_property avalon_slave maximumPendingWriteTransactions 0
set_interface_property avalon_slave readLatency 0
set_interface_property avalon_slave readWaitStates 0
set_interface_property avalon_slave readWaitTime 0
set_interface_property avalon_slave setupTime 0
set_interface_property avalon_slave timingUnits Cycles
set_interface_property avalon_slave writeWaitTime 0
set_interface_property avalon_slave ENABLED true
set_interface_property avalon_slave EXPORT_OF ""
set_interface_property avalon_slave PORT_NAME_MAP ""
set_interface_property avalon_slave CMSIS_SVD_VARIABLES ""
set_interface_property avalon_slave SVD_ADDRESS_GROUP ""
add_interface_port avalon_slave MMS_read read Input 1
add_interface_port avalon_slave MMS_write write Input 1
add_interface_port avalon_slave MMS_address address Input 5
add_interface_port avalon_slave MMS_readdata readdata Output 32
add_interface_port avalon_slave MMS_writedata writedata Input 32
set_interface_assignment avalon_slave embeddedsw.configuration.isFlash 0
set_interface_assignment avalon_slave embeddedsw.configuration.isMemoryDevice 0
set_interface_assignment avalon_slave embeddedsw.configuration.isNonVolatileStorage 0
set_interface_assignment avalon_slave embeddedsw.configuration.isPrintableDevice 0
#
# connection point ADC_response
#
add_interface ADC_response avalon_streaming end
set_interface_property ADC_response associatedClock clock_sink
set_interface_property ADC_response associatedReset reset_sink
set_interface_property ADC_response dataBitsPerSymbol 12
set_interface_property ADC_response errorDescriptor ""
set_interface_property ADC_response firstSymbolInHighOrderBits true
set_interface_property ADC_response maxChannel 31
set_interface_property ADC_response readyLatency 0
set_interface_property ADC_response ENABLED true
set_interface_property ADC_response EXPORT_OF ""
set_interface_property ADC_response PORT_NAME_MAP ""
set_interface_property ADC_response CMSIS_SVD_VARIABLES ""
set_interface_property ADC_response SVD_ADDRESS_GROUP ""
add_interface_port ADC_response resp_valid valid Input 1
add_interface_port ADC_response resp_data data Input 12
add_interface_port ADC_response resp_channel channel Input 5
add_interface_port ADC_response resp_startofpacket startofpacket Input 1
add_interface_port ADC_response resp_endofpacket endofpacket Input 1
#
# connection point Trig
#
add_interface Trig interrupt start
set_interface_property Trig associatedAddressablePoint ""
set_interface_property Trig associatedClock clock_sink
set_interface_property Trig associatedReset reset_sink
set_interface_property Trig irqScheme INDIVIDUAL_REQUESTS
set_interface_property Trig ENABLED true
set_interface_property Trig EXPORT_OF ""
set_interface_property Trig PORT_NAME_MAP ""
set_interface_property Trig CMSIS_SVD_VARIABLES ""
set_interface_property Trig SVD_ADDRESS_GROUP ""
add_interface_port Trig trig_in irq Input 1