From 73af6068298f80de8bed818cd4d9f74e1ee7c97b Mon Sep 17 00:00:00 2001 From: memN0ps <89628341+memN0ps@users.noreply.github.com> Date: Thu, 15 Feb 2024 02:35:07 +1300 Subject: [PATCH] Fixes --- driver/src/main.rs | 4 ++-- hypervisor/src/intel/ept/mtrr.rs | 4 ++-- hypervisor/src/intel/mod.rs | 1 + hypervisor/src/intel/vm.rs | 8 ++++++-- hypervisor/src/intel/vmcs.rs | 2 +- hypervisor/src/intel/vmx.rs | 8 ++++---- hypervisor/src/intel/vmxon.rs | 8 ++++---- 7 files changed, 20 insertions(+), 15 deletions(-) diff --git a/driver/src/main.rs b/driver/src/main.rs index 21844b8..9d76cec 100644 --- a/driver/src/main.rs +++ b/driver/src/main.rs @@ -6,8 +6,8 @@ extern crate alloc; use { log::*, uefi::prelude::*, - hypervisor::vmm::is_hypervisor_present, - crate::{virtualize::virtualize_system, capture::{capture_registers, GuestRegisters}}, + hypervisor::{vmm::is_hypervisor_present, intel::capture::{capture_registers, GuestRegisters}}, + crate::virtualize::virtualize_system, }; pub mod virtualize; diff --git a/hypervisor/src/intel/ept/mtrr.rs b/hypervisor/src/intel/ept/mtrr.rs index 0267507..f7e5f3c 100644 --- a/hypervisor/src/intel/ept/mtrr.rs +++ b/hypervisor/src/intel/ept/mtrr.rs @@ -43,10 +43,10 @@ impl Mtrr { // Skip Write Back type as it's the default memory type. if item.is_enabled && item.mem_type != MemoryType::WriteBack { - let end_address = Self::calculate_end_address(item.base.pa(), item.mask); + let end_address = Self::calculate_end_address(item.base, item.mask); let descriptor = MtrrRangeDescriptor { - base_address: item.base.pa(), + base_address: item.base, end_address, memory_type: item.mem_type, }; diff --git a/hypervisor/src/intel/mod.rs b/hypervisor/src/intel/mod.rs index 5c9b3fd..b8a474b 100644 --- a/hypervisor/src/intel/mod.rs +++ b/hypervisor/src/intel/mod.rs @@ -1,6 +1,7 @@ pub mod capture; pub mod controls; pub mod descriptor; +pub mod page; pub mod ept; //pub mod events; //pub mod invept; diff --git a/hypervisor/src/intel/vm.rs b/hypervisor/src/intel/vm.rs index bb3611e..44d0d2d 100644 --- a/hypervisor/src/intel/vm.rs +++ b/hypervisor/src/intel/vm.rs @@ -33,7 +33,9 @@ pub struct Vm { impl Vm { pub fn new(guest_registers: &GuestRegisters, shared_data: &mut SharedData) -> Self { - let mut vmcs = Box::::default(); + let vmcs = Box::::default(); + let guest_descriptor_table = unsafe { Box::::new_zeroed().assume_init() }; + let host_descriptor_table = unsafe { Box::::new_zeroed().assume_init() }; let mut host_paging = unsafe { Box::::new_zeroed().assume_init() }; host_paging.build_identity(); @@ -41,6 +43,8 @@ impl Vm { Self { vmcs_region: vmcs, host_paging, + host_descriptor_table, + guest_descriptor_table, guest_registers: guest_registers.clone(), shared_data: unsafe { NonNull::new_unchecked(shared_data as *mut _) }, } @@ -63,7 +67,7 @@ impl Vm { } pub fn setup_vmcs(&mut self) -> Result<(), HypervisorError> { - Vmcs::setup_guest_registers_state(&self.guest_descriptor_table, &mut self.guest_registers)?; + Vmcs::setup_guest_registers_state(&self.guest_descriptor_table, &mut self.guest_registers); Vmcs::setup_host_registers_state(&self.host_descriptor_table, &self.host_paging)?; Vmcs::setup_vmcs_control_fields(&mut self.shared_data)?; diff --git a/hypervisor/src/intel/vmcs.rs b/hypervisor/src/intel/vmcs.rs index 4757022..dcfe0a2 100644 --- a/hypervisor/src/intel/vmcs.rs +++ b/hypervisor/src/intel/vmcs.rs @@ -61,7 +61,7 @@ impl Vmcs { unsafe { vmwrite(vmcs::guest::CR3, controlregs::cr3()) }; vmwrite(vmcs::guest::CR4, Cr4::read_raw()); - vmwrite(vmcs::guest::DR7, unsafe { dr7().0.bits() }); + vmwrite(vmcs::guest::DR7, unsafe { dr7().0 as u64 }); vmwrite(vmcs::guest::RSP, guest_registers.rsp); vmwrite(vmcs::guest::RIP, guest_registers.rip); diff --git a/hypervisor/src/intel/vmx.rs b/hypervisor/src/intel/vmx.rs index 983b161..9f3d158 100644 --- a/hypervisor/src/intel/vmx.rs +++ b/hypervisor/src/intel/vmx.rs @@ -30,19 +30,19 @@ impl Vmx { /// Enables VMX operation by setting appropriate bits and executing the VMXON instruction. fn setup_vmxon(&mut self) -> Result<(), HypervisorError> { log::trace!("Enabling Virtual Machine Extensions (VMX)"); - Self::enable_vmx_operation(); + Vmxon::enable_vmx_operation(); log::trace!("VMX enabled"); log::trace!("Adjusting IA32_FEATURE_CONTROL MSR"); - Self::adjust_feature_control_msr()?; + Vmxon::adjust_feature_control_msr()?; log::trace!("IA32_FEATURE_CONTROL MSR adjusted"); log::trace!("Setting CR0 bits"); - Self::set_cr0_bits(); + Vmxon::set_cr0_bits(); log::trace!("CR0 bits set"); log::trace!("Setting CR4 bits"); - Self::set_cr4_bits(); + Vmxon::set_cr4_bits(); log::trace!("CR4 bits set"); self.vmxon_region.revision_id.set_bit(31, false); diff --git a/hypervisor/src/intel/vmxon.rs b/hypervisor/src/intel/vmxon.rs index ecef462..3e0ba6f 100644 --- a/hypervisor/src/intel/vmxon.rs +++ b/hypervisor/src/intel/vmxon.rs @@ -33,7 +33,7 @@ impl Default for Vmxon { impl Vmxon { /// Enables VMX operation by setting appropriate bits and executing the VMXON instruction. - fn enable_vmx_operation() { + pub fn enable_vmx_operation() { const CR4_VMX_ENABLE_BIT: usize = 13; let mut cr4 = Cr4::read_raw(); cr4.set_bit(CR4_VMX_ENABLE_BIT, true); @@ -41,7 +41,7 @@ impl Vmxon { } /// Sets the lock bit in IA32_FEATURE_CONTROL if necessary. - fn adjust_feature_control_msr() -> Result<(), HypervisorError> { + pub fn adjust_feature_control_msr() -> Result<(), HypervisorError> { const VMX_LOCK_BIT: u64 = 1 << 0; const VMXON_OUTSIDE_SMX: u64 = 1 << 2; @@ -62,7 +62,7 @@ impl Vmxon { } /// Modifies CR0 to set and clear mandatory bits. - fn set_cr0_bits() { + pub fn set_cr0_bits() { let ia32_vmx_cr0_fixed0 = unsafe { msr::rdmsr(msr::IA32_VMX_CR0_FIXED0) }; let ia32_vmx_cr0_fixed1 = unsafe { msr::rdmsr(msr::IA32_VMX_CR0_FIXED1) }; @@ -75,7 +75,7 @@ impl Vmxon { } /// Modifies CR4 to set and clear mandatory bits. - fn set_cr4_bits() { + pub fn set_cr4_bits() { let ia32_vmx_cr4_fixed0 = unsafe { msr::rdmsr(msr::IA32_VMX_CR4_FIXED0) }; let ia32_vmx_cr4_fixed1 = unsafe { msr::rdmsr(msr::IA32_VMX_CR4_FIXED1) };