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ath_info.c
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ath_info.c
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/* -*- linux-c -*- */
/*-
* Copyright (c) 2011 Nick Kossifidis <[email protected]>
* Copyright (c) 2011 Joerg Albert <jal2 *at* gmx.de>
*
* This program is free software you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY, without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
/* Needed for strtoull, u_int etc */
#define _GNU_SOURCE
#include <stdio.h>
#include <stdlib.h>
#include <unistd.h>
#include <errno.h>
#include <string.h>
#include <fcntl.h>
#include <sys/mman.h>
#include <endian.h>
#include <byteswap.h>
#include "eeprom.h"
#undef ARRAY_SIZE
#define ARRAY_SIZE(arr) (sizeof(arr) / sizeof((arr)[0]))
#define dbg(...) \
do { \
if (verbose) { \
printf("#DBG %s: ", __func__); \
printf(__VA_ARGS__); \
printf("\n"); \
} \
} while (0)
#define err(...) \
do { \
printf("#ERR %s: ", __func__); \
printf(__VA_ARGS__); \
printf("\n"); \
} while (0)
#define AR5K_PCI_MEM_SIZE 0x10000
#define AR5K_NUM_GPIO 6
#define AR5K_GPIOCR 0x4014 /* Register Address */
#define AR5K_GPIOCR_OUT(n) (3 << ((n) * 2)) /* Mode 3 for pin n */
#define AR5K_GPIOCR_INT_SEL(n) ((n) << 12) /* Interrupt for GPIO pin n */
/*
* GPIO (General Purpose Input/Output) data output register
*/
#define AR5K_GPIODO 0x4018
/*
* GPIO (General Purpose Input/Output) data input register
*/
#define AR5K_GPIODI 0x401c
struct ath5k_srev_name {
const char *sr_name;
u_int8_t sr_val;
};
#define AR5K_SREV_UNKNOWN 0xff
#define AR5K_SREV_AR5210 0x00 /* Crete */
#define AR5K_SREV_AR5311 0x10 /* Maui 1 */
#define AR5K_SREV_AR5311A 0x20 /* Maui 2 */
#define AR5K_SREV_AR5311B 0x30 /* Spirit */
#define AR5K_SREV_AR5211 0x40 /* Oahu */
#define AR5K_SREV_AR5212 0x50 /* Venice */
#define AR5K_SREV_AR5213 0x55 /* ??? */
#define AR5K_SREV_AR5213A 0x59 /* Hainan */
#define AR5K_SREV_AR2413 0x78 /* Griffin lite */
#define AR5K_SREV_AR2414 0x70 /* Griffin */
#define AR5K_SREV_AR5424 0x90 /* Condor */
#define AR5K_SREV_AR5413 0xa4 /* Eagle lite */
#define AR5K_SREV_AR5414 0xa0 /* Eagle */
#define AR5K_SREV_AR2415 0xb0 /* Cobra */
#define AR5K_SREV_AR5416 0xc0 /* PCI-E */
#define AR5K_SREV_AR5418 0xca /* PCI-E */
#define AR5K_SREV_AR2425 0xe0 /* Swan */
#define AR5K_SREV_AR2417 0xf0 /* Nala */
#define AR5K_SREV_RAD_5110 0x00
#define AR5K_SREV_RAD_5111 0x10
#define AR5K_SREV_RAD_5111A 0x15
#define AR5K_SREV_RAD_2111 0x20
#define AR5K_SREV_RAD_5112 0x30
#define AR5K_SREV_RAD_5112A 0x35
#define AR5K_SREV_RAD_5112B 0x36
#define AR5K_SREV_RAD_2112 0x40
#define AR5K_SREV_RAD_2112A 0x45
#define AR5K_SREV_RAD_2112B 0x46
#define AR5K_SREV_RAD_2413 0x50
#define AR5K_SREV_RAD_5413 0x60
#define AR5K_SREV_RAD_2316 0x70
#define AR5K_SREV_RAD_2317 0x80
#define AR5K_SREV_RAD_5424 0xa0 /* Mostly same as 5413 */
#define AR5K_SREV_RAD_2425 0xa2
#define AR5K_SREV_RAD_5133 0xc0
#define AR5K_SREV_PHY_5211 0x30
#define AR5K_SREV_PHY_5212 0x41
#define AR5K_SREV_PHY_2112B 0x43
#define AR5K_SREV_PHY_2413 0x45
#define AR5K_SREV_PHY_5413 0x61
#define AR5K_SREV_PHY_2425 0x70
static const struct ath5k_srev_name ath5k_mac_names[] = {
{ "5210", AR5K_SREV_AR5210 },
{ "5311", AR5K_SREV_AR5311 },
{ "5311A", AR5K_SREV_AR5311A },
{ "5311B", AR5K_SREV_AR5311B },
{ "5211", AR5K_SREV_AR5211 },
{ "5212", AR5K_SREV_AR5212 },
{ "5213", AR5K_SREV_AR5213 },
{ "5213A", AR5K_SREV_AR5213A },
{ "2413", AR5K_SREV_AR2413 },
{ "2414", AR5K_SREV_AR2414 },
{ "5424", AR5K_SREV_AR5424 },
{ "5413", AR5K_SREV_AR5413 },
{ "5414", AR5K_SREV_AR5414 },
{ "2415", AR5K_SREV_AR2415 },
{ "5416", AR5K_SREV_AR5416 },
{ "5418", AR5K_SREV_AR5418 },
{ "2425", AR5K_SREV_AR2425 },
{ "2417", AR5K_SREV_AR2417 },
{ "xxxxx", AR5K_SREV_UNKNOWN },
};
static const struct ath5k_srev_name ath5k_phy_names[] = {
{ "5110", AR5K_SREV_RAD_5110 },
{ "5111", AR5K_SREV_RAD_5111 },
{ "5111A", AR5K_SREV_RAD_5111A },
{ "2111", AR5K_SREV_RAD_2111 },
{ "5112", AR5K_SREV_RAD_5112 },
{ "5112A", AR5K_SREV_RAD_5112A },
{ "5112B", AR5K_SREV_RAD_5112B },
{ "2112", AR5K_SREV_RAD_2112 },
{ "2112A", AR5K_SREV_RAD_2112A },
{ "2112B", AR5K_SREV_RAD_2112B },
{ "2413", AR5K_SREV_RAD_2413 },
{ "5413", AR5K_SREV_RAD_5413 },
{ "2316", AR5K_SREV_RAD_2316 },
{ "2317", AR5K_SREV_RAD_2317 },
{ "5424", AR5K_SREV_RAD_5424 },
{ "5133", AR5K_SREV_RAD_5133 },
{ "xxxxx", AR5K_SREV_UNKNOWN },
};
/*
* Silicon revision register
*/
#define AR5K_SREV 0x4020 /* Register Address */
#define AR5K_SREV_VER 0x000000f0 /* Mask for version */
#define AR5K_SREV_REV 0x000000ff /* Mask for revision */
/*
* PHY chip revision register
*/
#define AR5K_PHY_CHIP_ID 0x9818
/*
* PHY register
*/
#define AR5K_PHY_BASE 0x9800
#define AR5K_PHY(_n) (AR5K_PHY_BASE + ((_n) << 2))
#define AR5K_PHY_SHIFT_2GHZ 0x00004007
#define AR5K_PHY_SHIFT_5GHZ 0x00000007
#define AR5K_RESET_CTL 0x4000 /* Register Address */
#define AR5K_RESET_CTL_PCU 0x00000001 /* Protocol Control Unit reset */
#define AR5K_RESET_CTL_DMA 0x00000002 /* DMA (Rx/Tx) reset -5210 only */
#define AR5K_RESET_CTL_BASEBAND 0x00000002 /* Baseband reset (5211/5212) */
#define AR5K_RESET_CTL_MAC 0x00000004 /* MAC reset (PCU+Baseband?) -5210 only */
#define AR5K_RESET_CTL_PHY 0x00000008 /* PHY reset -5210 only */
#define AR5K_RESET_CTL_PCI 0x00000010 /* PCI Core reset (interrupts etc) */
#define AR5K_RESET_CTL_CHIP (AR5K_RESET_CTL_PCU | AR5K_RESET_CTL_DMA | \
AR5K_RESET_CTL_MAC | AR5K_RESET_CTL_PHY)
/*
* Sleep control register
*/
#define AR5K_SLEEP_CTL 0x4004 /* Register Address */
#define AR5K_SLEEP_CTL_SLDUR 0x0000ffff /* Sleep duration mask */
#define AR5K_SLEEP_CTL_SLDUR_S 0
#define AR5K_SLEEP_CTL_SLE 0x00030000 /* Sleep enable mask */
#define AR5K_SLEEP_CTL_SLE_S 16
#define AR5K_SLEEP_CTL_SLE_WAKE 0x00000000 /* Force chip awake */
#define AR5K_SLEEP_CTL_SLE_SLP 0x00010000 /* Force chip sleep */
#define AR5K_SLEEP_CTL_SLE_ALLOW 0x00020000
#define AR5K_SLEEP_CTL_SLE_UNITS 0x00000008 /* not on 5210 */
#define AR5K_PCICFG 0x4010 /* Register Address */
#define AR5K_PCICFG_EEAE 0x00000001 /* EEPROM access enable [5210] */
#define AR5K_PCICFG_CLKRUNEN 0x00000004 /* CLKRUN enable [5211+] */
#define AR5K_PCICFG_EESIZE 0x00000018 /* Mask for EEPROM size [5211+] */
#define AR5K_PCICFG_EESIZE_S 3
#define AR5K_PCICFG_EESIZE_4K 0 /* 4K */
#define AR5K_PCICFG_EESIZE_8K 1 /* 8K */
#define AR5K_PCICFG_EESIZE_16K 2 /* 16K */
#define AR5K_PCICFG_EESIZE_FAIL 3 /* Failed to get size (?) [5211+] */
#define AR5K_PCICFG_SPWR_DN 0x00010000 /* Mask for power status (5210) */
#define AR5K_EEPROM_BASE 0x6000
/*
* EEPROM data register
*/
#define AR5K_EEPROM_DATA_5211 0x6004
#define AR5K_EEPROM_DATA_5210 0x6800
#define AR5K_EEPROM_DATA (eeprom_access == AR5K_EEPROM_ACCESS_5210 ? \
AR5K_EEPROM_DATA_5210 : AR5K_EEPROM_DATA_5211)
/*
* EEPROM command register
*/
#define AR5K_EEPROM_CMD 0x6008 /* Register Address */
#define AR5K_EEPROM_CMD_READ 0x00000001 /* EEPROM read */
#define AR5K_EEPROM_CMD_WRITE 0x00000002 /* EEPROM write */
#define AR5K_EEPROM_CMD_RESET 0x00000004 /* EEPROM reset */
/*
* EEPROM status register
*/
#define AR5K_EEPROM_STAT_5210 0x6c00 /* Register Address [5210] */
#define AR5K_EEPROM_STAT_5211 0x600c /* Register Address [5211+] */
#define AR5K_EEPROM_STATUS (eeprom_access == AR5K_EEPROM_ACCESS_5210 ? \
AR5K_EEPROM_STAT_5210 : AR5K_EEPROM_STAT_5211)
#define AR5K_EEPROM_STAT_RDERR 0x00000001 /* EEPROM read failed */
#define AR5K_EEPROM_STAT_RDDONE 0x00000002 /* EEPROM read successful */
#define AR5K_EEPROM_STAT_WRERR 0x00000004 /* EEPROM write failed */
#define AR5K_EEPROM_STAT_WRDONE 0x00000008 /* EEPROM write successful */
/*
* EEPROM config register (?)
*/
#define AR5K_EEPROM_CFG 0x6010
/*
* Read data by masking
*/
#define AR5K_REG_MS(_val, _flags) \
(((_val) & (_flags)) >> _flags##_S)
/*
* Access device registers
*/
#if __BYTE_ORDER == __BIG_ENDIAN
#define AR5K_REG_READ(_reg) \
__bswap_32(*((volatile u_int32_t *)(mem + (_reg))))
#define AR5K_REG_WRITE(_reg, _val) \
(*((volatile u_int32_t *)(mem + (_reg))) = __bswap_32(_val))
#else
#define AR5K_REG_READ(_reg) \
(*((volatile u_int32_t *)(mem + (_reg))))
#define AR5K_REG_WRITE(_reg, _val) \
(*((volatile u_int32_t *)(mem + (_reg))) = (_val))
#endif
#define AR5K_REG_ENABLE_BITS(_reg, _flags) \
AR5K_REG_WRITE(_reg, AR5K_REG_READ(_reg) | (_flags))
#define AR5K_REG_DISABLE_BITS(_reg, _flags) \
AR5K_REG_WRITE(_reg, AR5K_REG_READ(_reg) & ~(_flags))
#define AR5K_TUNE_REGISTER_TIMEOUT 20000
#define AR5K_EEPROM_READ(_o, _v) do { \
if ((ret = ath5k_hw_eeprom_read((_o), &(_v))) != 0) \
return (ret); \
} while (0)
/* Names for EEPROM fields */
struct eeprom_entry {
const char *name;
int addr;
};
static const struct eeprom_entry eeprom_addr[] = {
{"pci_dev_id", 0},
{"pci_vendor_id", 1},
{"pci_class", 2},
{"pci_rev_id", 3},
{"pci_subsys_dev_id", 7},
{"pci_subsys_vendor_id", 8},
{"regdomain", AR5K_EEPROM_REG_DOMAIN},
};
/* Command line settings */
static int force_write = 0;
static int verbose = 0;
/* Global device characteristics */
static enum {
AR5K_EEPROM_ACCESS_5210,
AR5K_EEPROM_ACCESS_5211,
AR5K_EEPROM_ACCESS_5416
} eeprom_access;
static unsigned int eeprom_size;
static int mac_revision;
static void *mem;
/* forward decl. */
static void usage(const char *n);
static u_int32_t ath5k_hw_bitswap(u_int32_t val, u_int bits)
{
u_int32_t retval = 0, bit, i;
for (i = 0; i < bits; i++) {
bit = (val >> i) & 1;
retval = (retval << 1) | bit;
}
return (retval);
}
/*
* Get the PHY Chip revision
*/
static u_int16_t ath5k_hw_radio_revision(u_int8_t chip)
{
int i;
u_int32_t srev;
u_int16_t ret;
/*
* Set the radio chip access register
*/
switch (chip) {
case 0:
AR5K_REG_WRITE(AR5K_PHY(0), AR5K_PHY_SHIFT_2GHZ);
break;
case 1:
AR5K_REG_WRITE(AR5K_PHY(0), AR5K_PHY_SHIFT_5GHZ);
break;
default:
return (0);
}
usleep(2000);
/* ...wait until PHY is ready and read the selected radio revision */
AR5K_REG_WRITE(AR5K_PHY(0x34), 0x00001c16);
for (i = 0; i < 8; i++)
AR5K_REG_WRITE(AR5K_PHY(0x20), 0x00010000);
if (mac_revision == AR5K_SREV_AR5210) {
srev = AR5K_REG_READ(AR5K_PHY(256) >> 28) & 0xf;
ret = (u_int16_t)ath5k_hw_bitswap(srev, 4) + 1;
} else {
srev = (AR5K_REG_READ(AR5K_PHY(0x100)) >> 24) & 0xff;
ret = (u_int16_t)ath5k_hw_bitswap(((srev & 0xf0) >> 4) |
((srev & 0x0f) << 4), 8);
}
/* Reset to the 5GHz mode */
AR5K_REG_WRITE(AR5K_PHY(0), AR5K_PHY_SHIFT_5GHZ);
return (ret);
}
/*
* Read from EEPROM
*/
static int ath5k_hw_eeprom_read(u_int32_t offset, u_int16_t *data)
{
u_int32_t status, timeout;
/*
* Initialize EEPROM access
*/
if (eeprom_access == AR5K_EEPROM_ACCESS_5210) {
AR5K_REG_ENABLE_BITS(AR5K_PCICFG, AR5K_PCICFG_EEAE);
(void)AR5K_REG_READ(AR5K_EEPROM_BASE + (4 * offset));
} else {
AR5K_REG_WRITE(AR5K_EEPROM_BASE, offset);
AR5K_REG_ENABLE_BITS(AR5K_EEPROM_CMD, AR5K_EEPROM_CMD_READ);
}
for (timeout = AR5K_TUNE_REGISTER_TIMEOUT; timeout > 0; timeout--) {
status = AR5K_REG_READ(AR5K_EEPROM_STATUS);
if (status & AR5K_EEPROM_STAT_RDDONE) {
if (status & AR5K_EEPROM_STAT_RDERR)
return 1;
*data = (u_int16_t)
(AR5K_REG_READ(AR5K_EEPROM_DATA) & 0xffff);
return (0);
}
usleep(15);
}
return 1;
}
/*
* Write to EEPROM
*/
static int ath5k_hw_eeprom_write(u_int32_t offset, u_int16_t data)
{
u_int32_t status, timeout;
u_int16_t read_data;
/*
* Initialize EEPROM access
*/
if (eeprom_access == AR5K_EEPROM_ACCESS_5210) {
AR5K_REG_ENABLE_BITS(AR5K_PCICFG, AR5K_PCICFG_EEAE);
/* data to write */
(void)AR5K_REG_WRITE(AR5K_EEPROM_BASE + (4 * offset), data);
} else {
/* not 5210 */
/* reset EEPROM access */
AR5K_REG_WRITE(AR5K_EEPROM_CMD, AR5K_EEPROM_CMD_RESET);
usleep(5);
AR5K_REG_WRITE(AR5K_EEPROM_DATA, data);
/* set offset in EEPROM to write to */
AR5K_REG_WRITE(AR5K_EEPROM_BASE, offset);
usleep(5);
/* issue write command */
AR5K_REG_WRITE(AR5K_EEPROM_CMD, AR5K_EEPROM_CMD_WRITE);
}
for (timeout = AR5K_TUNE_REGISTER_TIMEOUT; timeout > 0; timeout--) {
status = AR5K_REG_READ(AR5K_EEPROM_STATUS);
if (status & AR5K_EEPROM_STAT_WRDONE) {
if (status & AR5K_EEPROM_STAT_WRERR) {
err("EEPROM write access to 0x%04x failed",
offset);
return 1;
}
ath5k_hw_eeprom_read( offset, &read_data);
if (read_data != data) {
err("data doesn't match, write failed at 0x%04x\n",
offset);
return 1;
}
return 0;
}
usleep(15);
}
return 1;
}
/*
* Translate binary channel representation in EEPROM to frequency
*/
static u_int16_t ath5k_eeprom_bin2freq(struct ath5k_eeprom_info *ee,
u_int16_t bin, unsigned int mode)
{
u_int16_t val;
if (bin == AR5K_EEPROM_CHANNEL_DIS)
return bin;
if (mode == AR5K_EEPROM_MODE_11A) {
if (ee->ee_version > AR5K_EEPROM_VERSION_3_2)
val = (5 * bin) + 4800;
else
val = bin > 62 ? (10 * 62) + (5 * (bin - 62)) + 5100 :
(bin * 10) + 5100;
} else {
if (ee->ee_version > AR5K_EEPROM_VERSION_3_2)
val = bin + 2300;
else
val = bin + 2400;
}
return val;
}
/*
* Read antenna info from EEPROM
*/
static int ath5k_eeprom_read_ants(struct ath5k_eeprom_info *ee,
u_int32_t *offset, unsigned int mode)
{
u_int32_t o = *offset;
u_int16_t val;
int ret, i = 0;
AR5K_EEPROM_READ(o++, val);
ee->ee_switch_settling[mode] = (val >> 8) & 0x7f;
ee->ee_atn_tx_rx[mode] = (val >> 2) & 0x3f;
ee->ee_ant_control[mode][i] = (val << 4) & 0x3f;
AR5K_EEPROM_READ(o++, val);
ee->ee_ant_control[mode][i++] |= (val >> 12) & 0xf;
ee->ee_ant_control[mode][i++] = (val >> 6) & 0x3f;
ee->ee_ant_control[mode][i++] = val & 0x3f;
AR5K_EEPROM_READ(o++, val);
ee->ee_ant_control[mode][i++] = (val >> 10) & 0x3f;
ee->ee_ant_control[mode][i++] = (val >> 4) & 0x3f;
ee->ee_ant_control[mode][i] = (val << 2) & 0x3f;
AR5K_EEPROM_READ(o++, val);
ee->ee_ant_control[mode][i++] |= (val >> 14) & 0x3;
ee->ee_ant_control[mode][i++] = (val >> 8) & 0x3f;
ee->ee_ant_control[mode][i++] = (val >> 2) & 0x3f;
ee->ee_ant_control[mode][i] = (val << 4) & 0x3f;
AR5K_EEPROM_READ(o++, val);
ee->ee_ant_control[mode][i++] |= (val >> 12) & 0xf;
ee->ee_ant_control[mode][i++] = (val >> 6) & 0x3f;
ee->ee_ant_control[mode][i++] = val & 0x3f;
/* Get antenna modes */
ee->ee_antenna[mode][0] =
(ee->ee_ant_control[mode][0] << 4) | 0x1;
ee->ee_antenna[mode][AR5K_ANT_FIXED_A] =
ee->ee_ant_control[mode][1] |
(ee->ee_ant_control[mode][2] << 6) |
(ee->ee_ant_control[mode][3] << 12) |
(ee->ee_ant_control[mode][4] << 18) |
(ee->ee_ant_control[mode][5] << 24);
ee->ee_antenna[mode][AR5K_ANT_FIXED_B] =
ee->ee_ant_control[mode][6] |
(ee->ee_ant_control[mode][7] << 6) |
(ee->ee_ant_control[mode][8] << 12) |
(ee->ee_ant_control[mode][9] << 18) |
(ee->ee_ant_control[mode][10] << 24);
/* return new offset */
*offset = o;
return 0;
}
/*
* Read supported modes from EEPROM
*/
static int ath5k_eeprom_read_modes(struct ath5k_eeprom_info *ee,
u_int32_t *offset, unsigned int mode)
{
u_int32_t o = *offset;
u_int16_t val;
int ret;
switch (mode){
case AR5K_EEPROM_MODE_11A:
AR5K_EEPROM_READ(o++, val);
ee->ee_adc_desired_size[mode] = (int8_t)((val >> 8) & 0xff);
ee->ee_ob[mode][3] = (val >> 5) & 0x7;
ee->ee_db[mode][3] = (val >> 2) & 0x7;
ee->ee_ob[mode][2] = (val << 1) & 0x7;
AR5K_EEPROM_READ(o++, val);
ee->ee_ob[mode][2] |= (val >> 15) & 0x1;
ee->ee_db[mode][2] = (val >> 12) & 0x7;
ee->ee_ob[mode][1] = (val >> 9) & 0x7;
ee->ee_db[mode][1] = (val >> 6) & 0x7;
ee->ee_ob[mode][0] = (val >> 3) & 0x7;
ee->ee_db[mode][0] = val & 0x7;
break;
case AR5K_EEPROM_MODE_11B:
AR5K_EEPROM_READ(o++, val);
ee->ee_adc_desired_size[mode] = (int8_t)((val >> 8) & 0xff);
ee->ee_ob[mode][1] = (val >> 4) & 0x7;
ee->ee_db[mode][1] = val & 0x7;
break;
case AR5K_EEPROM_MODE_11G:
AR5K_EEPROM_READ(o++, val);
ee->ee_adc_desired_size[mode] = (signed short int)((val >> 8) & 0xff);
ee->ee_ob[mode][1] = (val >> 4) & 0x7;
ee->ee_db[mode][1] = val & 0x7;
break;
}
AR5K_EEPROM_READ(o++, val);
ee->ee_tx_end2xlna_enable[mode] = (val >> 8) & 0xff;
ee->ee_thr_62[mode] = val & 0xff;
if (ee->ee_version <= AR5K_EEPROM_VERSION_3_2)
ee->ee_thr_62[mode] = mode == AR5K_EEPROM_MODE_11A ? 15 : 28;
AR5K_EEPROM_READ(o++, val);
ee->ee_tx_end2xpa_disable[mode] = (val >> 8) & 0xff;
ee->ee_tx_frm2xpa_enable[mode] = val & 0xff;
AR5K_EEPROM_READ(o++, val);
ee->ee_pga_desired_size[mode] = (val >> 8) & 0xff;
if ((val & 0xff) & 0x80)
ee->ee_noise_floor_thr[mode] = -((((val & 0xff) ^ 0xff)) + 1);
else
ee->ee_noise_floor_thr[mode] = val & 0xff;
if (ee->ee_version <= AR5K_EEPROM_VERSION_3_2)
ee->ee_noise_floor_thr[mode] =
mode == AR5K_EEPROM_MODE_11A ? -54 : -1;
AR5K_EEPROM_READ(o++, val);
ee->ee_xlna_gain[mode] = (val >> 5) & 0xff;
ee->ee_x_gain[mode] = (val >> 1) & 0xf;
ee->ee_xpd[mode] = val & 0x1;
if (ee->ee_version >= AR5K_EEPROM_VERSION_4_0)
ee->ee_fixed_bias[mode] = (val >> 13) & 0x1;
if (ee->ee_version >= AR5K_EEPROM_VERSION_3_3) {
AR5K_EEPROM_READ(o++, val);
ee->ee_false_detect[mode] = (val >> 6) & 0x7f;
if (mode == AR5K_EEPROM_MODE_11A)
ee->ee_xr_power[mode] = val & 0x3f;
else {
ee->ee_ob[mode][0] = val & 0x7;
ee->ee_db[mode][0] = (val >> 3) & 0x7;
}
}
if (ee->ee_version < AR5K_EEPROM_VERSION_3_4) {
ee->ee_i_gain[mode] = AR5K_EEPROM_I_GAIN;
ee->ee_cck_ofdm_power_delta = AR5K_EEPROM_CCK_OFDM_DELTA;
} else {
ee->ee_i_gain[mode] = (val >> 13) & 0x7;
AR5K_EEPROM_READ(o++, val);
ee->ee_i_gain[mode] |= (val << 3) & 0x38;
if (mode == AR5K_EEPROM_MODE_11G) {
ee->ee_cck_ofdm_power_delta = (val >> 3) & 0xff;
if (ee->ee_version >= AR5K_EEPROM_VERSION_4_6)
ee->ee_scaled_cck_delta = (val >> 11) & 0x1f;
}
}
if (ee->ee_version >= AR5K_EEPROM_VERSION_4_0 &&
mode == AR5K_EEPROM_MODE_11A) {
ee->ee_i_cal[mode] = (val >> 8) & 0x3f;
ee->ee_q_cal[mode] = (val >> 3) & 0x1f;
}
if (ee->ee_version >= AR5K_EEPROM_VERSION_4_0) {
switch (mode) {
case AR5K_EEPROM_MODE_11B:
AR5K_EEPROM_READ(o++, val);
ee->ee_cal_piers_b = 0;
ee->ee_pwr_cal_b[0].freq =
ath5k_eeprom_bin2freq(ee, val & 0xff, mode);
if (ee->ee_pwr_cal_b[0].freq != AR5K_EEPROM_CHANNEL_DIS)
ee->ee_cal_piers_b++;
ee->ee_pwr_cal_b[1].freq =
ath5k_eeprom_bin2freq(ee, (val >> 8) & 0xff, mode);
if (ee->ee_pwr_cal_b[1].freq != AR5K_EEPROM_CHANNEL_DIS)
ee->ee_cal_piers_b++;
AR5K_EEPROM_READ(o++, val);
ee->ee_pwr_cal_b[2].freq =
ath5k_eeprom_bin2freq(ee, val & 0xff, mode);
if (ee->ee_pwr_cal_b[2].freq != AR5K_EEPROM_CHANNEL_DIS)
ee->ee_cal_piers_b++;
break;
case AR5K_EEPROM_MODE_11G:
AR5K_EEPROM_READ(o++, val);
ee->ee_cal_piers_g = 0;
ee->ee_pwr_cal_g[0].freq =
ath5k_eeprom_bin2freq(ee, val & 0xff, mode);
if (ee->ee_pwr_cal_g[0].freq != AR5K_EEPROM_CHANNEL_DIS)
ee->ee_cal_piers_g++;
ee->ee_pwr_cal_g[1].freq =
ath5k_eeprom_bin2freq(ee, (val >> 8) & 0xff, mode);
if (ee->ee_pwr_cal_g[1].freq != AR5K_EEPROM_CHANNEL_DIS)
ee->ee_cal_piers_g++;
AR5K_EEPROM_READ(o++, val);
ee->ee_turbo_max_power[mode] = val & 0x7f;
ee->ee_xr_power[mode] = (val >> 7) & 0x3f;
AR5K_EEPROM_READ(o++, val);
ee->ee_pwr_cal_g[2].freq =
ath5k_eeprom_bin2freq(ee, val & 0xff, mode);
if (ee->ee_pwr_cal_g[2].freq != AR5K_EEPROM_CHANNEL_DIS)
ee->ee_cal_piers_g++;
break;
}
}
if (ee->ee_version >= AR5K_EEPROM_VERSION_4_1) {
switch (mode) {
case AR5K_EEPROM_MODE_11A:
AR5K_EEPROM_READ(o++, val);
ee->ee_margin_tx_rx[mode] = val & 0x3f;
break;
case AR5K_EEPROM_MODE_11B:
case AR5K_EEPROM_MODE_11G:
ee->ee_margin_tx_rx[mode] = (val >> 8) & 0x3f;
break;
}
}
if (ee->ee_version >= AR5K_EEPROM_VERSION_4_0 &&
mode == AR5K_EEPROM_MODE_11G) {
AR5K_EEPROM_READ(o++, val);
ee->ee_i_cal[mode] = (val >> 8) & 0x3f;
ee->ee_q_cal[mode] = (val >> 3) & 0x1f;
if (ee->ee_version >= AR5K_EEPROM_VERSION_4_2) {
AR5K_EEPROM_READ(o++, val);
ee->ee_cck_ofdm_gain_delta = val & 0xff;
}
}
/*
* Read turbo mode information on newer EEPROM versions
*/
if (ee->ee_version >= AR5K_EEPROM_VERSION_5_0 &&
mode == AR5K_EEPROM_MODE_11A) {
ee->ee_switch_settling_turbo[mode] = (val >> 6) & 0x7f;
ee->ee_atn_tx_rx_turbo[mode] = (val >> 13) & 0x7;
AR5K_EEPROM_READ(o++, val);
ee->ee_atn_tx_rx_turbo[mode] |= (val & 0x7) << 3;
ee->ee_margin_tx_rx_turbo[mode] = (val >> 3) & 0x3f;
ee->ee_adc_desired_size_turbo[mode] = (val >> 9) & 0x7f;
AR5K_EEPROM_READ(o++, val);
ee->ee_adc_desired_size_turbo[mode] |= (val & 0x1) << 7;
ee->ee_pga_desired_size_turbo[mode] = (val >> 1) & 0xff;
if (AR5K_EEPROM_EEMAP(ee->ee_misc0) >=2)
ee->ee_pd_gain_overlap = (val >> 9) & 0xf;
}
if (ee->ee_version >= AR5K_EEPROM_VERSION_5_0 &&
mode == AR5K_EEPROM_MODE_11G) {
ee->ee_switch_settling_turbo[mode] = (val >> 8) & 0x7f;
ee->ee_atn_tx_rx_turbo[mode] = (val >> 15) & 0x7;
AR5K_EEPROM_READ(o++, val);
ee->ee_atn_tx_rx_turbo[mode] |= (val & 0x1f) << 1;
ee->ee_margin_tx_rx_turbo[mode] = (val >> 5) & 0x3f;
ee->ee_adc_desired_size_turbo[mode] = (val >> 11) & 0x7f;
AR5K_EEPROM_READ(o++, val);
ee->ee_adc_desired_size_turbo[mode] |= (val & 0x7) << 5;
ee->ee_pga_desired_size_turbo[mode] = (val >> 3) & 0xff;
}
/* return new offset */
*offset = o;
return 0;
}
/*
* Read per channel calibration info from EEPROM
*
* This info is used to calibrate the baseband power table. Imagine
* that for each channel there is a power curve that's hw specific
* (depends on amplifier) and we try to "correct" this curve using offests
* we pass on to phy chip (baseband -> before amplifier) so that it can
* use accurate power values when setting tx power (takes amplifier's
* performance on each channel into account).
*
* EEPROM provides us with the offsets for some pre-calibrated channels
* and we have to scale (to create the full table for these channels) and
* interpolate (in order to create the table for any channel).
*/
static int ath5k_eeprom_read_rf5111_pcal_info(struct ath5k_eeprom_info *ee,
unsigned int mode)
{
u_int32_t offset;
unsigned int i, c;
int ret;
u_int16_t val;
struct ath5k_chan_pcal_info *gen_chan_info;
struct ath5k_chan_pcal_info_rf5111 *chan_pcal_info;
u_int16_t cal_piers;
/* Fixed percentage intercepts */
static const u_int8_t intercepts_3[] =
{ 0, 5, 10, 20, 30, 50, 70, 85, 90, 95, 100 };
static const u_int8_t intercepts_3_2[] =
{ 0, 10, 20, 30, 40, 50, 60, 70, 80, 90, 100 };
const u_int8_t *intercepts =
ee->ee_version < AR5K_EEPROM_VERSION_3_2 ?
intercepts_3 : intercepts_3_2;
switch (mode) {
case AR5K_EEPROM_MODE_11A:
/*
* Read 5GHz EEPROM channels
*/
offset = AR5K_EEPROM_GROUPS_START(ee->ee_version);
gen_chan_info = ee->ee_pwr_cal_a;
ee->ee_cal_piers_a = 0;
/* Different frequency mask for < 3.2 */
if (ee->ee_version <= AR5K_EEPROM_VERSION_3_2) {
AR5K_EEPROM_READ(offset++, val);
gen_chan_info[0].freq =
ath5k_eeprom_bin2freq(ee, val >> 9 & 0x7f,
AR5K_EEPROM_MODE_11A);
gen_chan_info[1].freq =
ath5k_eeprom_bin2freq(ee, val >> 2 & 0x7f,
AR5K_EEPROM_MODE_11A);
gen_chan_info[2].freq = val << 5 & 0x7f;
AR5K_EEPROM_READ(offset++, val);
gen_chan_info[2].freq |= val >> 11 & 0x1f;
gen_chan_info[2].freq =
ath5k_eeprom_bin2freq(ee, gen_chan_info[2].freq,
AR5K_EEPROM_MODE_11A);
gen_chan_info[3].freq =
ath5k_eeprom_bin2freq(ee, val >> 4 & 0x7f,
AR5K_EEPROM_MODE_11A);
gen_chan_info[4].freq = val << 3 & 0x7f;
AR5K_EEPROM_READ(offset++, val);
gen_chan_info[4].freq |= val >> 13 & 0x7;
gen_chan_info[4].freq =
ath5k_eeprom_bin2freq(ee, gen_chan_info[4].freq,
AR5K_EEPROM_MODE_11A);
gen_chan_info[5].freq =
ath5k_eeprom_bin2freq(ee, val >> 6 & 0x7f,
AR5K_EEPROM_MODE_11A);
gen_chan_info[6].freq = val << 1 & 0x7f;
AR5K_EEPROM_READ(offset++, val);
gen_chan_info[6].freq |= val >> 15 & 0x1;
gen_chan_info[6].freq =
ath5k_eeprom_bin2freq(ee, gen_chan_info[6].freq,
AR5K_EEPROM_MODE_11A);
gen_chan_info[7].freq =
ath5k_eeprom_bin2freq(ee, val >> 8 & 0x7f,
AR5K_EEPROM_MODE_11A);
gen_chan_info[8].freq =
ath5k_eeprom_bin2freq(ee, val >> 1 & 0x7f,
AR5K_EEPROM_MODE_11A);
gen_chan_info[9].freq = val << 6 & 0x7f;
AR5K_EEPROM_READ(offset++, val);
gen_chan_info[9].freq |= val >> 10 & 0x3f;
gen_chan_info[9].freq =
ath5k_eeprom_bin2freq(ee, gen_chan_info[9].freq,
AR5K_EEPROM_MODE_11A);
ee->ee_cal_piers_a = 10;
} else {
for (i = 0; i < AR5K_EEPROM_N_5GHZ_CHAN; i++) {
AR5K_EEPROM_READ(offset++, val);
if ((val & 0xff) == 0)
break;
ee->ee_pwr_cal_a[i].freq =
ath5k_eeprom_bin2freq(ee, val & 0xff,
AR5K_EEPROM_MODE_11A);
ee->ee_cal_piers_a++;
if (((val >> 8) & 0xff) == 0)
break;
ee->ee_pwr_cal_a[++i].freq =
ath5k_eeprom_bin2freq(ee, (val >> 8) & 0xff,
AR5K_EEPROM_MODE_11A);
ee->ee_cal_piers_a++;
}
}
offset = AR5K_EEPROM_GROUPS_START(ee->ee_version) +
AR5K_EEPROM_GROUP2_OFFSET;
cal_piers = ee->ee_cal_piers_a;
break;
case AR5K_EEPROM_MODE_11B:
offset = AR5K_EEPROM_GROUPS_START(ee->ee_version) +
AR5K_EEPROM_GROUP3_OFFSET;
gen_chan_info = ee->ee_pwr_cal_b;
/* Fixed cal piers */
gen_chan_info[0].freq = 2412;
gen_chan_info[1].freq = 2447;
gen_chan_info[2].freq = 2484;
ee->ee_cal_piers_b = 3;
cal_piers = ee->ee_cal_piers_b;
break;
case AR5K_EEPROM_MODE_11G:
offset = AR5K_EEPROM_GROUPS_START(ee->ee_version) +
AR5K_EEPROM_GROUP4_OFFSET;
gen_chan_info = ee->ee_pwr_cal_g;
/* Fixed cal piers */
gen_chan_info[0].freq = 2312;
gen_chan_info[1].freq = 2412;
gen_chan_info[2].freq = 2484;
ee->ee_cal_piers_b = 3;
cal_piers = ee->ee_cal_piers_g;
break;
default:
return -EINVAL;
}
for (i = 0; i < cal_piers; i++) {
gen_chan_info[i].rf5111_info =
malloc(sizeof(struct ath5k_chan_pcal_info_rf5111));
chan_pcal_info = gen_chan_info[i].rf5111_info;
AR5K_EEPROM_READ(offset++, val);
chan_pcal_info->pcdac_max = (u_int16_t)((val >> 10) & 0x3f);
chan_pcal_info->pcdac_min = (u_int16_t)((val >> 4) & 0x3f);
chan_pcal_info->pwr[0] = (u_int16_t)((val << 2) & 0x3f);
AR5K_EEPROM_READ(offset++, val);
chan_pcal_info->pwr[0] |= (u_int16_t)((val >> 14) & 0x3);
chan_pcal_info->pwr[1] = (u_int16_t)((val >> 8) & 0x3f);
chan_pcal_info->pwr[2] = (u_int16_t)((val >> 2) & 0x3f);
chan_pcal_info->pwr[3] = (u_int16_t)((val << 4) & 0x3f);
AR5K_EEPROM_READ(offset++, val);
chan_pcal_info->pwr[3] |= (u_int16_t)((val >> 12) & 0xf);
chan_pcal_info->pwr[4] = (u_int16_t)((val >> 6) & 0x3f);
chan_pcal_info->pwr[5] = (u_int16_t)(val & 0x3f);
AR5K_EEPROM_READ(offset++, val);
chan_pcal_info->pwr[6] = (u_int16_t)((val >> 10) & 0x3f);
chan_pcal_info->pwr[7] = (u_int16_t)((val >> 4) & 0x3f);
chan_pcal_info->pwr[8] = (u_int16_t)((val << 2) & 0x3f);
AR5K_EEPROM_READ(offset++, val);
chan_pcal_info->pwr[8] |= (u_int16_t)((val >> 14) & 0x3);
chan_pcal_info->pwr[9] = (u_int16_t)((val >> 8) & 0x3f);
chan_pcal_info->pwr[10] = (u_int16_t)((val >> 2) & 0x3f);
/* Recreate pcdac offsets table for this channel
* using intercepts table and PCDAC min/max */
for (c = 0; c < AR5K_EEPROM_N_PWR_POINTS_5111; c++ )
chan_pcal_info->pcdac[c] =
(intercepts[c] * chan_pcal_info->pcdac_max +
(100 - intercepts[c]) * chan_pcal_info->pcdac_min) / 100;
}
return 0;
}
static int ath5k_eeprom_read_rf5112_pcal_info(struct ath5k_eeprom_info *ee,
unsigned int mode)
{
u_int32_t offset;
unsigned int i, c;
int ret;
u_int16_t val;
struct ath5k_chan_pcal_info *gen_chan_info;
struct ath5k_chan_pcal_info_rf5112 *chan_pcal_info;
u_int16_t cal_piers;
switch (mode) {
case AR5K_EEPROM_MODE_11A:
/*
* Read 5GHz EEPROM channels
*/
offset = AR5K_EEPROM_GROUPS_START(ee->ee_version);
ee->ee_cal_piers_a = 0;
for (i = 0; i < AR5K_EEPROM_N_5GHZ_CHAN; i++) {
AR5K_EEPROM_READ(offset++, val);
if ((val & 0xff) == 0)
break;
ee->ee_pwr_cal_a[i].freq =
ath5k_eeprom_bin2freq(ee, val & 0xff,
AR5K_EEPROM_MODE_11A);
ee->ee_cal_piers_a++;