From 569d1ee8d65cc5288f163db677a123e933e99d80 Mon Sep 17 00:00:00 2001 From: Tim 'mithro' Ansell Date: Thu, 30 Jan 2020 21:19:47 +0100 Subject: [PATCH] Updating submodules. * litex changed from v0.1-1384-g02bfda5e to v0.1-1572-g7a6c04db * 7a6c04db - build/altera/quartus: fix fmt_r typo * c6b9676d - cpu/minerva: update (use new nMigen API) * 9d289472 - inteconnect/stream: use PipeValid implementation for Buffer * 1c88c0f8 - inteconnect/stream: cleanup * cafd9c35 - Merge pull request #366 from gsomlo/gls-csr-followup |\ | * ff2775c2 - software, integration/export: (re-)expose CSR subregister accessors * | f3f9808d - interconnect/stream: add PipeValid and PipeWait to cut timing paths. * | b22ad1ac - build/xilinx/vivado: improve readability of generated tcl/xdc files |/ * 7bc34a9b - integration/soc_core: revert integrate_sram_size default value (cause issues when using External SPRAM). * b4b56db4 - Merge pull request #363 from antmicro/litex-sim-ddr4 |\ | * c02dd5e8 - tools/litex_sim: add ddr4 PhySettings |/ * 0820adbd - tools/litex_sim: add --sdram-init parameter * 01ae10b8 - software/bios: revert M-Labs MiSoC copyright. * ea5ef8c1 - README: update copyright year and make sure LICENSE/README both mention MiSoC * 95cfa6a8 - platforms/netv2: add pcie pins * f9bc98ed - Merge pull request #359 from gregdavill/bios_ddr3_ecp5 |\ | * 1f439062 - soc/software/bios/sdram: ECP5 move strobe dly_sel | * f84f57d6 - soc/software/bios/sdram: On ECP5 strobe dly_sel after read leveling |/ * 52765488 - tools/litex_sim: update copyrights and cosmetic changes * b280bb2f - Merge pull request #358 from antmicro/litex_sim_ddr |\ | * 9aa97c2e - tools/litex_sim: add support for other sdram types (DDR, LPDDR, DDR2, DDR3) * | 19ef19ce - cores/clock/create_clkout: rename clk_ce to ce, improve error reporting * | 7e088360 - Merge pull request #357 from betrusted-io/add_clk_ce |\ \ | |/ |/| | * 1f7549b4 - add BUFIO to clockgen buffer options | * b3f9aa11 - add option for BUFGCE to the clock generator buffer types * | cbc081c4 - tools/litex_sim: review/cleanup sdram-module/sdram-data-width features. * | b35ea459 - Merge pull request #354 from antmicro/litex_sim_ddr |\ \ | * | 674cfcde - tools/litex_sim: specify dram chip and data width via commandline * | | b23f13d9 - Merge pull request #351 from antmicro/fix_sram_size_argument |\ \ \ | |/ / |/| | | * | 7a05353a - soc_core: rename integrated_sram_size argument | * | c4bb4169 - soc_core: fix integrated_sram_size argument type * | | 5845df76 - build/xilinx/vivado: add pre_placement/pre_routing commands * | | 13880882 - cores/icap: add add_timing_constraints method * | | 2074a86e - cores/dna: cleanup and add add_timing_constraints method |/ / * | d39dc8cf - tools/litex_sim: cleanup/simplify * | a0d95766 - build/sim: add -Wl,--no-as-needed to LDFLAGS for Ubuntu 16.04 support (thanks kamejoko80) * | 80c3dc41 - targets: use mem_region.origin instead of mem_map definition (prepare for automatic mem_region allocation) * | 53bc18cc - soc_core: add new alloc_mem/add_mem_region to allow automatic allocation of memory regions |/ * eae0e004 - cores/clock/xadc: ease DRP timings * 7b92a17c - test/test_targets: limit max_sdram_size to 1GB * 008a0894 - targets/nexys4ddr: fix typo * 36e5274a - SoCSDRAM: set default max_sdram_size to 1GB (maximum we can map with current mem_map) * 46c1c5c1 - targets/kcu105: remove main_ram_size_limit * 5913c91c - SoCSDRAM: rename main_ram_size_limit to max_sdram_size and make it a parameter of SoCSDRAM, expose SoCSDRAM parameters to user * 1c465f89 - build/lattice: add add_false_path_constraint method for API compatibility but false paths are not yet used/translated to .lpf file * b4ba2a47 - soc/cores/uart: set rx_fifo_rx_we to True on UARTCrossover * 5aa516cb - soc/cores/uart: add rx_fifo_rx_we parameter to pulse rx_fifo.source.ready on rxtx register read. * 862e784e - cpu/vexriscv: use 32-bit signal for externalResetVector * f2a1673f - targets/arty/genesys2: fix EthernetSoC/EtherboneSoC selection * 990870d0 - targets/genesys2: add EtherboneSoC * 820e79bf - platforms/de0nano: specify gpio for serial * ba366d42 - targets: cleanup EthernetSoC * a2685370 - soc/interconnect/packet/Depacketizer: use both sink.valid and sink.ready to update sink_d, fix Etherbone regression on Arty. * a168ecba - targets/arty: add EtherboneSoC * 7a4ecfa5 - targets/kcu105: update * 68e225fb - test/test_targets: update * 42efa998 - SoCCore: set default integrated_rom/ram_size to 0. For targets, defaults values are provided by soc_core_args. * 4050e608 - SoCCore: use hex for integrated_rom/sram_size * f818755c - Merge pull request #339 from gsomlo/gls-csr-cleanup |\ | * b073ebad - bios/sdram: switch to updated CSR accessors, and misc. cleanup | * 2c393041 - software, integration/export: rename and reimplement CSR accessors * | f1606dbc - tools/litex_sim: use default integrated_rom_size * | 4648db0c - cores/uart/UARTInterface: remove connect method * | 6c9f418d - soc_core: fix uart stub |/ * 63cd23c9 - cpu/vexriscv: revert mem_map_linux/main_ram * 83a7225c - SoCCore: set integrated rom/sram size default values in soc_core_args and use it in targets * 6e3f25a7 - cpu/vexriscv/mem_map_linux: update main_ram to 0x40000000 * fe14b9cf - targets/genesys2: update self.register_sdram * 39ce39a2 - soc_sdram: add l2_data_width parameter to set minimal l2_data_width to improve DRAM accesses efficiency. * 23175190 - cores/uart: add UARTCrossover * 2f03d323 - cores/uart/UART: add stream interface (phy=None), add connect method and use this for UART Stub/Crossover. * d92bd8ff - gen/fhdl/verilog: fix signed init values * ff066a5e - Merge pull request #338 from DurandA/master |\ | * d24a4b54 - Add optional 'ignore-loops' flag to nextpnr * | 26fe45fc - cores/uart: rename BridgedUART to UARTEmulator and rework/simplify it. Also integrated it in SoCCore with uart_name="emulator" * | d40bf9d8 - Merge pull request #340 from xobs/bridged-uart |\ \ | |/ |/| | * 5079a3c3 - uart: add BridgedUart |/ * f70dd482 - bios/sdram: add memspeed * fa22d6aa - wishbone/Cache: avoid REFILL_WRTAG state to improve speed. * f408527d - soc/cores/cpu: add riscv64-linux toolchain support for risc-v cpus. * 8889821c - targets: sync with litex-boards * aba8fc5c - build/altera/quartus: allow multiple call of add_period_constraint if constraint is similar. * e318287e - Merge pull request #337 from gregdavill/spi-flash |\ | * 49781467 - soc/cores/spi_flash: Don't tristate DQ2/DQ3 when bitbanging * | 2cf95e9f - platforms/minispartan6: rename sd to sdcard and regroup data lines * | e99740e8 - platforms/nexys4ddr: add sdcard pins * | 83ad674f - build/lattice/trellis: use a single fonction to parse device * | 018c7ca8 - Merge pull request #336 from kbeckmann/trellis-speed |\ \ | * | 426ab676 - trellis: Pass speed grade argument to nextpnr |/ / * | fd4cbd80 - Merge pull request #331 from betrusted-io/xadc_mods |\ \ | * | 378722a7 - soc/cores/xadc: define analog_layout and simplify analog_pads connections | * | 87d456ca - bring back analog_pads specifier, remove reset conditions on VP | * | 4dc0a614 - soc/core/xadc: cleanup, simplify and add expose_drp method - keep CSR ordering with older version, requested for software compatibility. - always enable analog capability (user will just not use it if not needed). - add expose_drp method (similar to clock.py) for cases where DRP is needed. | * | 5eec7432 - fix a couple bugs in the DRP readout path | * | 56ccaeeb - add support for DRP on XADC * | | 642d0737 - cpu/minerva: fix variant syntax warning * | | 8ba204c7 - Merge pull request #332 from gsomlo/gls-csr-mem-sel |\ \ \ | * | | d087e2e0 - interconnect/csr_bus/SRAM: allow 64-bit alignment (on 64-bit CPUs) |/ / / * | | 690de79d - cpu/microwatt: reorder sources, add comments * | | e36df2a6 - build/lattice/icestorm: increase similarities with trellis. * | | 197edad3 - soc/integration/soc_core/SoCController: specify initial reset value of scratch register in description * | | b65a36e7 - soc/integration/soc_core/SoCController: rephrase CSR descriptions a bit * | | 1f27b21f - Merge pull request #330 from xobs/document-ctrl-timer0 |\ \ \ | * | | c5aa929d - cores: timer: clean up wording for timer documentation | * | | 2d75aee7 - soc_core: ctrl: document registers | * | | a251d712 - cores: timer: fix documentation formatting |/ / / * | | db7a48c0 - soc/cores/clock: also allow margin=0 on iCE40PLL and ECP5PLL * | | caacc411 - Merge pull request #328 from betrusted-io/precise_clocks |\| | | * | 219bb7f2 - add the possibility for a "precise" clock solution |/ / * | 9336fe11 - build/microsemi/libero_soc: update add_period_constraint behavior when clock is already constrainted. * | 3022f02b - build/xilinx/vivado: update add_period_constraint behavior when clock is already constrainted. * | fe4eaf58 - build/lattice/icestorm/add_period_constraint: improve * | 6b91e882 - soc/integration/builder: avoid try/except on LiteDRAM import, just check if SoC has an sdram and do the import if so * | 2157d0f3 - Merge pull request #327 from zakgi/master |\ \ | * | 39ae230b - moving RAM offsets outside of CSR_ETHMAC define * | | f0b5c672 - Allow specifying the same clock constraint multiple times. * | | 8b955e6f - Allow LiteX builder to be used without LiteDRAM. * | | a738739a - Improve the invalid CPU type error message. * | | 85ade2b3 - build/xilinx/programmer: fix vivado_cmd when settings are sourced manually. |/ / * | ffa7ca8f - Merge pull request #321 from gsomlo/gls-rocket-aximem-wide |\ \ | * | cd8feca5 - cpu/rocket: variants with double (128b) and quad (256b) wide mem_axi * | | e754c055 - Merge pull request #319 from DurandA/feature-integer-attributes |\ \ \ | |/ / |/| | | * | 94e239ff - Add integer attributes | * | f8c58216 - Revert "gen/fhdl/verilog: allow single element verilog inline attribute" * | | 40c35550 - Merge pull request #320 from gsomlo/gls-touch-up |\ \ \ | * | | 585b50b2 - soc_core: csr_alignment assertions | * | | b6818c20 - cpu/rocket: access PLIC registers via pointer dereference |/ / / * / / 0e46913d - cpu/microwatt: add initial software support |/ / * | f883f0c7 - cpu/microwatt: add submodule * | 5da0bcbd - cpu/microwatt: set csr to 0xc0000000 (IO region) * | 39a8ebe7 - cpu/microwatt: fix add_source/add_sources * | d74a7463 - soc/cores/pwm: remove debug print(n) * | bd15f07c - platforms/netv2: add xc7a100t support * | 76e57414 - platforms/minispartan6: add assert on available devices * | bfe0bf64 - cpu/microwatt: simplify add_sources * | b9edde20 - cpu/microwatt: add io_regions and gcc_flags * | 16e7c6b6 - cpu/microwatt: update copyright * | 3d79324f - cpu/microwatt: drive stall signal (no burst support) * | da3a178b - soc/cores/pwm: add clock_domain support * | 9da28c4e - build/xilinx/XilinxMultiRegImpl: fix n=0 case * | ec7dc2d8 - build/xilinx/ise: cleanup/simplify pass, remove mist support (not aware of anyone using it) * | 1b963bb2 - soc/cores/cpu: add initial Microwatt gateware support * | c34255d2 - soc/cores/cpu/minerva: add self.reset to i_rst * | 8b6f9e0a - Merge pull request #315 from gsomlo/gls-csr-assert |\ \ | * | a0dad1b0 - soc_core: additional CSR safety assertions |/ / * | fb6b0786 - soc_core: remove static 16MB csr region allocation (use csr_address_width to allocate the correct size) * | b1a1e5e2 - soc_core: add sort of CSR regions by origin (allow csr.h/csr.csv to be ordered by origin) * | 061d593d - cores/8b10b: use real Memory for 6b5b table (to improve timings on ECP5) * | a0122f98 - build/xilinx/vivado: move build_script generation * | 18ff8f38 - build/xilinx/vivado: cleanup/simplify * | 0931ccc9 - build/lattice/icestorm: cleanup/simplify (and remove arachne-pnr support) * | b1b92053 - build/xilinx/common/platform/programmer: cleanup pass * | edaa66bb - boards: add Lambdaconcept's PCIe Screamer (R02) * | a8635c48 - targets/versa_ecp5: fix compilation with diamond * | 30a18808 - boards/targets: keep attributes are no longer needed since automatically added when applying constraints to signals. * | 23c33cfa - build: automatically add keep attribute to signals with timing constraints. * | 4c9af635 - build/altera/quartus: allow adding period constraints on nets and add optional additional sdc/qsf commands * | 22e6f5ac - build/lattice/trellis: nextpnr now handle LPF timing constraints and multiple clock domains, freq_constraint is no longer needed. * | 8fb3f9a9 - build/lattice: cleanup/simplify (no functional changes) * | 946478a7 - build/lattice: cleanup/simplify * | 60edca23 - build/microsemi: cleanup/simplify (no functional change) * | 50fdc5ce - build/altera: cleanup/simplify (no functional change) * | b17dfafa - Merge pull request #313 from mmicko/yosys_ise_flow_fix |\ \ | * | 783dfa50 - Properly select family for those currently supported | * | 6560911d - Integrate with latest yosys changes * | | 8d90f4e9 - build/xilinx/vivado: use VHDL 2008 as default * | | cfd17321 - targets/nexys4ddr: remove MEMTEST_ADDR_SIZE limitation (no longer needed) * | | 201d60f3 - targets/netv2: switch to MVP DDR3 (K4B2G1646F instead of MT41J128M16) * | | 6b820647 - targets: uniformize, improve presentation * | | 718f6995 - README: fix LitePCIe Travis-CI link * | | 6de20f18 - soc/interconnect/csr: add fields support for CSRStorage's write simulation method * | | 2567a0ae - soc/cores/gpio: add GPIO Tristate * | | d702c0fe - setup.py: update long_description * | | c9665aed - README.md: use litex logo * | | 82819dd5 - README: switch to Markdown * | | 90f9ffc5 - Merge pull request #311 from kbeckmann/trellis_cabga256 |\ \ \ | |/ / |/| | | * | f411d6d3 - trellis: Support the CABGA256 package |/ / * | 3d20442f - Merge pull request #310 from xobs/spi-flash-mode3-doc |\ \ | |/ |/| | * 581c2372 - spi_flash: correct documentation on SPI mode |/ * de205d4a - tools/remote/comm_udp: only use one socket * bdaca40f - build/generic_platform: avoid duplicate in GenericPlatform.sources * 6883a436 - soc/cores/clock: change drp_locked to CSRStatus and connect it :) * 36107cdf - soc/cores/clock: reset PLL/MMCM on all 7-series/Ultrascale with self.reset signal * e8e70b16 - Merge pull request #309 from antmicro/mmcm-fix |\ | * fd14b765 - soc/cores/clock: add lock reg and assign reset * 04017519 - soc/interconnect/axi: add Wishbone2AXILite * 4b073a44 - test/test_axi: cosmetic * d9055211 - build/tools/get_migen/litex_git_revision: avoid git fatal error message is not installed as a git repository Full submodule status -- 3a6108a75be356a3dc53760d22782f1323248b6b edid-decode (remotes/origin/HEAD) 3a06aa84b62ad24467fb0d2c6ceddf565e9ea447 flash_proxies (remotes/origin/HEAD) a35a1f7790cba537d52ccc8ae73c4e230a6cba8d litedram (heads/master-217-ga35a1f7) f532a12b40648e84cef626e9343f428e5e366fb4 liteeth (remotes/origin/HEAD) 935703636b20306a66d3253f34a4473f0e8d2844 litepcie (heads/master-127-g9357036) 1e3573b07d382eac50ef764fd839009bf90cb8ce litesata (remotes/origin/HEAD) daf10e9473fb70b3034e0331ef89005661ac04e0 litescope (remotes/origin/HEAD) 7457a29b1a47fe15e81fa37f3bbdd510788f1d53 liteusb (remotes/origin/HEAD) 49bafa481075e0bfbaf067b63c351ec29e993894 litevideo (heads/master-5-g49bafa4) 7a6c04db9e8d830b8729e64834bc5c97277cca4f litex (v0.1-1572-g7a6c04db) 84164f8fab5c65e2dd828ed20422d14026f5b140 litex-boards (heads/master) 70e884e88c25d997ea5e3dd1e2a8bb08f0d02f90 litex-renode (remotes/origin/HEAD) 0d0e17a5e65fc21a2f08a16b55594739c98cf89e migen (0.6.dev-322-g0d0e17a5) f207f3f62098a56d24de90bb833f02eedf55b054 nmigen (v0.1-4-gf207f3f) --- third_party/litex | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/third_party/litex b/third_party/litex index 02bfda5e3..7a6c04db9 160000 --- a/third_party/litex +++ b/third_party/litex @@ -1 +1 @@ -Subproject commit 02bfda5e38f33c66e2fe9bb2f63ec02756657233 +Subproject commit 7a6c04db9e8d830b8729e64834bc5c97277cca4f