diff --git a/spirack/D5a_module.py b/spirack/D5a_module.py
index 27d0d21..31cae46 100644
--- a/spirack/D5a_module.py
+++ b/spirack/D5a_module.py
@@ -71,7 +71,7 @@ def __init__(self, spi_rack, module, reset_voltages=True, num_dacs=16):
         self.voltages = [np.NaN]*self._num_dacs
 
         for i in range(self._num_dacs):
-            self.voltages[i], self.span[i] = self.get_settings(i)
+            self.get_settings(i)
 
         if reset_voltages:
             for i in range(self._num_dacs):
@@ -298,15 +298,15 @@ def set_voltage(self, DAC, voltage):
             self.voltages[DAC] = maxV
             if voltage > maxV:
                 print("Voltage too high for set span, DAC set to max value")
-                logger.warning('D5a module %d: voltage too high for set span, '
-                               'DAC set to max value: %f V', self.module, maxV)
+                logger.warning('D5a module %d: voltage %f V too high for set span, '
+                               'DAC set to max value: %f V', self.module, voltage, maxV)
         elif voltage <= minV:
             self.voltages[DAC] = minV
             bit_value = 0
             if voltage < minV:
                 print("Voltage too low for set span, DAC set to min value")
-                logger.warning('D5a module %d: voltage too low for set span, '
-                               'DAC set to min value: %f V', self.module, minV)
+                logger.warning('D5a module %d: voltage %f V too low for set span, '
+                               'DAC set to min value: %f V', self.module, voltage, minV)
 
         self.change_value_update(DAC, bit_value)
 
diff --git a/spirack/S4g_module.py b/spirack/S4g_module.py
index b9b2cbc..e9e0c64 100644
--- a/spirack/S4g_module.py
+++ b/spirack/S4g_module.py
@@ -15,10 +15,14 @@
     *Add checks on writing span and values
 """
 
+import logging
+
 import numpy as np
 
 from .chip_mode import LTC2758_MODE, LTC2758_SPEED, LTC2758_RD_SPEED
 
+logger = logging.getLogger(__name__)
+
 class S4g_module(object):
     """S4g module interface class
 
@@ -68,7 +72,7 @@ def __init__(self, spi_rack, module, max_current=50e-3, reset_currents=True):
         self.max_current = max_current
 
         for i in range(4):
-            self.currents[i], self.span[i] = self.get_settings(i)
+            self.get_settings(i)
 
         if reset_currents:
             for i in range(4):
@@ -234,10 +238,14 @@ def set_current(self, DAC, current):
             bit_value = (2**18)-1
             self.currents[DAC] = maxI
             print("Current too high for set span, DAC set to max value")
+            logger.warning('S4g module %d: current %f mA too high for set span,'
+                           'current set to max value: %f mA', self.module, current, maxI)
         elif current <= minI:
             self.currents[DAC] = minI
             bit_value = 0
             print("Current too low for set span, DAC set to min value")
+            logger.warning('S4g module %d: current %f mA too low for set span,'
+                           'current set to min value: %f mA', self.module, current, minI)
 
         self.change_value_update(DAC, bit_value)
 
@@ -303,4 +311,7 @@ def get_settings(self, DAC):
         else:
             raise ValueError("Span {} should not be used. Accepted values are: {}".format(span, [0, 2, 4]))
 
+        self.currents[DAC] = current
+        self.span[DAC] = span
+
         return [current, span]
diff --git a/spirack/S5i_module.py b/spirack/S5i_module.py
index c0013c8..e303ce1 100644
--- a/spirack/S5i_module.py
+++ b/spirack/S5i_module.py
@@ -72,14 +72,25 @@ def write_registers(self):
     def set_output_power(self, level):
         """Sets the source output power
 
-        Sets the output power of the unit. Can be varied over ~30 dB.
+        Sets the output power of the unit. Can be varied over ~30 dB. Stepsize is 1 dBm
+        with an accuracy of +- 0.5 dBm
+
         Args:
-            level: value between -20 and 14 (dBm))
+            level (int): value between -20 and 15 (dBm))
         """
-        if level < -20 or level > 14:
-            raise ValueError('Level {} not allowed. Has to be between -20 and 14 (dBm)'.format(level))
+        if level < -20 or level > 15:
+            raise ValueError('Level {} not allowed. Has to be between -20 and 15 (dBm)'.format(level))
+        
+        # The curve below contains the DAC values corresponding to the output power from
+        # -20dBm to 15 dBm in steps of 1 dBm. This is based on the average of 3 S5i output 
+        # power curves.
+        output_curve = np.array([ 8849, 14876, 17441, 18852, 19878, 20776, 21417, 22186, 22828,
+                                    23597, 24238, 25136, 25906, 26932, 28086, 29368, 30651, 32062,
+                                    33601, 35011, 36422, 37448, 38474, 39500, 40398, 41424, 42322,
+                                    43348, 44245, 45399, 46425, 47580, 48734, 50016, 51555, 63354])
+
+        value = output_curve[int(level)+20]
 
-        value = int(1927.5*level + 38550)
         s_data = bytearray([64|(value>>10), (value>>2)&0xFF, (value&3)<<6])
         self.spi_rack.write_data(self.module, 1, MAX521x_MODE, MAX521x_SPEED, s_data)
 
diff --git a/spirack/version.py b/spirack/version.py
index 7fd229a..fc79d63 100644
--- a/spirack/version.py
+++ b/spirack/version.py
@@ -1 +1 @@
-__version__ = '0.2.0'
+__version__ = '0.2.1'